./Ultimate.py --spec ../../sv-benchmarks/c/properties/valid-memsafety.prp --file ../../sv-benchmarks/c/memsafety/20051113-1.i --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for memory safety (deref-memtrack) Using default analysis Version 38b53e6a Calling Ultimate with: /usr/lib/jvm/java-1.11.0-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f26c41a-56d7-4548-8d02-7cd563b233b6/bin/uautomizer-ZsLfNo2U6R/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f26c41a-56d7-4548-8d02-7cd563b233b6/bin/uautomizer-ZsLfNo2U6R/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f26c41a-56d7-4548-8d02-7cd563b233b6/bin/uautomizer-ZsLfNo2U6R/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f26c41a-56d7-4548-8d02-7cd563b233b6/bin/uautomizer-ZsLfNo2U6R/config/AutomizerMemDerefMemtrack.xml -i ../../sv-benchmarks/c/memsafety/20051113-1.i -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f26c41a-56d7-4548-8d02-7cd563b233b6/bin/uautomizer-ZsLfNo2U6R/config/svcomp-DerefFreeMemtrack-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f26c41a-56d7-4548-8d02-7cd563b233b6/bin/uautomizer-ZsLfNo2U6R --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G valid-free) ) CHECK( init(main()), LTL(G valid-deref) ) CHECK( init(main()), LTL(G valid-memtrack) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 2a43a02844acf962bfa6f77d0e1512c06ac1cc2fb3c3905e584a292a069b5426 --- Real Ultimate output --- [0.001s][warning][os,container] Duplicate cpuset controllers detected. Picking /sys/fs/cgroup/cpuset, skipping /sys/fs/cgroup/cpuset. This is Ultimate 0.2.2-dev-38b53e6 [2022-11-25 18:23:13,510 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-11-25 18:23:13,512 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-11-25 18:23:13,533 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-11-25 18:23:13,533 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-11-25 18:23:13,535 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-11-25 18:23:13,536 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-11-25 18:23:13,538 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-11-25 18:23:13,540 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-11-25 18:23:13,541 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-11-25 18:23:13,542 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-11-25 18:23:13,543 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-11-25 18:23:13,544 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-11-25 18:23:13,545 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-11-25 18:23:13,547 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-11-25 18:23:13,548 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-11-25 18:23:13,549 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-11-25 18:23:13,550 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-11-25 18:23:13,552 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-11-25 18:23:13,555 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-11-25 18:23:13,557 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-11-25 18:23:13,558 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-11-25 18:23:13,559 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-11-25 18:23:13,560 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-11-25 18:23:13,564 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-11-25 18:23:13,565 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-11-25 18:23:13,565 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-11-25 18:23:13,566 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-11-25 18:23:13,567 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-11-25 18:23:13,568 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-11-25 18:23:13,569 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-11-25 18:23:13,570 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-11-25 18:23:13,571 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-11-25 18:23:13,572 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-11-25 18:23:13,573 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-11-25 18:23:13,574 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-11-25 18:23:13,575 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-11-25 18:23:13,575 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-11-25 18:23:13,576 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-11-25 18:23:13,577 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-11-25 18:23:13,578 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-11-25 18:23:13,579 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f26c41a-56d7-4548-8d02-7cd563b233b6/bin/uautomizer-ZsLfNo2U6R/config/svcomp-DerefFreeMemtrack-32bit-Automizer_Default.epf [2022-11-25 18:23:13,603 INFO L113 SettingsManager]: Loading preferences was successful [2022-11-25 18:23:13,603 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-11-25 18:23:13,604 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-11-25 18:23:13,604 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-11-25 18:23:13,605 INFO L136 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2022-11-25 18:23:13,606 INFO L138 SettingsManager]: * Ignore calls to procedures called more than once=ONLY_FOR_SEQUENTIAL_PROGRAMS [2022-11-25 18:23:13,607 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-11-25 18:23:13,607 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-11-25 18:23:13,607 INFO L138 SettingsManager]: * Use SBE=true [2022-11-25 18:23:13,608 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-11-25 18:23:13,608 INFO L138 SettingsManager]: * sizeof long=4 [2022-11-25 18:23:13,608 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2022-11-25 18:23:13,609 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-11-25 18:23:13,609 INFO L138 SettingsManager]: * sizeof POINTER=4 [2022-11-25 18:23:13,609 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-11-25 18:23:13,610 INFO L138 SettingsManager]: * Check for the main procedure if all allocated memory was freed=true [2022-11-25 18:23:13,610 INFO L138 SettingsManager]: * Bitprecise bitfields=true [2022-11-25 18:23:13,610 INFO L138 SettingsManager]: * SV-COMP memtrack compatibility mode=true [2022-11-25 18:23:13,610 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2022-11-25 18:23:13,611 INFO L138 SettingsManager]: * Adapt memory model on pointer casts if necessary=true [2022-11-25 18:23:13,611 INFO L138 SettingsManager]: * sizeof long double=12 [2022-11-25 18:23:13,611 INFO L138 SettingsManager]: * Use constant arrays=true [2022-11-25 18:23:13,612 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-11-25 18:23:13,612 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-11-25 18:23:13,612 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2022-11-25 18:23:13,613 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2022-11-25 18:23:13,613 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-11-25 18:23:13,613 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2022-11-25 18:23:13,614 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-11-25 18:23:13,614 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2022-11-25 18:23:13,614 INFO L138 SettingsManager]: * Automaton type used in concurrency analysis=PETRI_NET [2022-11-25 18:23:13,614 INFO L138 SettingsManager]: * Order on configurations for Petri net unfoldings=DBO [2022-11-25 18:23:13,615 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2022-11-25 18:23:13,615 INFO L138 SettingsManager]: * Looper check in Petri net analysis=SEMANTIC WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f26c41a-56d7-4548-8d02-7cd563b233b6/bin/uautomizer-ZsLfNo2U6R/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f26c41a-56d7-4548-8d02-7cd563b233b6/bin/uautomizer-ZsLfNo2U6R Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G valid-free) ) CHECK( init(main()), LTL(G valid-deref) ) CHECK( init(main()), LTL(G valid-memtrack) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 2a43a02844acf962bfa6f77d0e1512c06ac1cc2fb3c3905e584a292a069b5426 [2022-11-25 18:23:13,869 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-11-25 18:23:13,903 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-11-25 18:23:13,905 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-11-25 18:23:13,907 INFO L271 PluginConnector]: Initializing CDTParser... [2022-11-25 18:23:13,907 INFO L275 PluginConnector]: CDTParser initialized [2022-11-25 18:23:13,908 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f26c41a-56d7-4548-8d02-7cd563b233b6/bin/uautomizer-ZsLfNo2U6R/../../sv-benchmarks/c/memsafety/20051113-1.i [2022-11-25 18:23:16,978 INFO L500 CDTParser]: Created temporary CDT project at NULL [2022-11-25 18:23:17,351 INFO L351 CDTParser]: Found 1 translation units. [2022-11-25 18:23:17,351 INFO L172 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f26c41a-56d7-4548-8d02-7cd563b233b6/sv-benchmarks/c/memsafety/20051113-1.i [2022-11-25 18:23:17,370 INFO L394 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f26c41a-56d7-4548-8d02-7cd563b233b6/bin/uautomizer-ZsLfNo2U6R/data/841301c0a/fedc89f835f04925a376713431b6659c/FLAGf91dd8e7b [2022-11-25 18:23:17,394 INFO L402 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f26c41a-56d7-4548-8d02-7cd563b233b6/bin/uautomizer-ZsLfNo2U6R/data/841301c0a/fedc89f835f04925a376713431b6659c [2022-11-25 18:23:17,400 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-11-25 18:23:17,403 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-11-25 18:23:17,407 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-11-25 18:23:17,407 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-11-25 18:23:17,411 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-11-25 18:23:17,412 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 25.11 06:23:17" (1/1) ... [2022-11-25 18:23:17,413 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@1348da4d and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.11 06:23:17, skipping insertion in model container [2022-11-25 18:23:17,414 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 25.11 06:23:17" (1/1) ... [2022-11-25 18:23:17,422 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-11-25 18:23:17,459 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-11-25 18:23:17,889 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-11-25 18:23:17,907 INFO L203 MainTranslator]: Completed pre-run [2022-11-25 18:23:17,974 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-11-25 18:23:18,009 INFO L208 MainTranslator]: Completed translation [2022-11-25 18:23:18,011 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.11 06:23:18 WrapperNode [2022-11-25 18:23:18,012 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-11-25 18:23:18,014 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-11-25 18:23:18,014 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-11-25 18:23:18,015 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-11-25 18:23:18,023 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.11 06:23:18" (1/1) ... [2022-11-25 18:23:18,046 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.11 06:23:18" (1/1) ... [2022-11-25 18:23:18,070 INFO L138 Inliner]: procedures = 125, calls = 23, calls flagged for inlining = 5, calls inlined = 5, statements flattened = 77 [2022-11-25 18:23:18,070 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-11-25 18:23:18,071 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-11-25 18:23:18,071 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-11-25 18:23:18,071 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-11-25 18:23:18,082 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.11 06:23:18" (1/1) ... [2022-11-25 18:23:18,082 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.11 06:23:18" (1/1) ... [2022-11-25 18:23:18,084 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.11 06:23:18" (1/1) ... [2022-11-25 18:23:18,085 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.11 06:23:18" (1/1) ... [2022-11-25 18:23:18,099 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.11 06:23:18" (1/1) ... [2022-11-25 18:23:18,103 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.11 06:23:18" (1/1) ... [2022-11-25 18:23:18,104 INFO L185 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.11 06:23:18" (1/1) ... [2022-11-25 18:23:18,105 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.11 06:23:18" (1/1) ... [2022-11-25 18:23:18,108 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-11-25 18:23:18,109 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-11-25 18:23:18,109 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-11-25 18:23:18,109 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-11-25 18:23:18,110 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.11 06:23:18" (1/1) ... [2022-11-25 18:23:18,121 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2022-11-25 18:23:18,137 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f26c41a-56d7-4548-8d02-7cd563b233b6/bin/uautomizer-ZsLfNo2U6R/z3 [2022-11-25 18:23:18,157 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f26c41a-56d7-4548-8d02-7cd563b233b6/bin/uautomizer-ZsLfNo2U6R/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) [2022-11-25 18:23:18,186 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f26c41a-56d7-4548-8d02-7cd563b233b6/bin/uautomizer-ZsLfNo2U6R/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (1)] Waiting until timeout for monitored process [2022-11-25 18:23:18,210 INFO L130 BoogieDeclarations]: Found specification of procedure read~int [2022-11-25 18:23:18,210 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2022-11-25 18:23:18,211 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnHeap [2022-11-25 18:23:18,211 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-11-25 18:23:18,211 INFO L130 BoogieDeclarations]: Found specification of procedure dummy_abort [2022-11-25 18:23:18,211 INFO L138 BoogieDeclarations]: Found implementation of procedure dummy_abort [2022-11-25 18:23:18,211 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-11-25 18:23:18,211 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-11-25 18:23:18,211 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-11-25 18:23:18,348 INFO L235 CfgBuilder]: Building ICFG [2022-11-25 18:23:18,351 INFO L261 CfgBuilder]: Building CFG for each procedure with an implementation [2022-11-25 18:23:18,755 INFO L276 CfgBuilder]: Performing block encoding [2022-11-25 18:23:18,762 INFO L295 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-11-25 18:23:18,762 INFO L300 CfgBuilder]: Removed 2 assume(true) statements. [2022-11-25 18:23:18,764 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 25.11 06:23:18 BoogieIcfgContainer [2022-11-25 18:23:18,764 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-11-25 18:23:18,767 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2022-11-25 18:23:18,767 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2022-11-25 18:23:18,770 INFO L275 PluginConnector]: TraceAbstraction initialized [2022-11-25 18:23:18,770 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 25.11 06:23:17" (1/3) ... [2022-11-25 18:23:18,771 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@42d48c89 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 25.11 06:23:18, skipping insertion in model container [2022-11-25 18:23:18,771 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.11 06:23:18" (2/3) ... [2022-11-25 18:23:18,772 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@42d48c89 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 25.11 06:23:18, skipping insertion in model container [2022-11-25 18:23:18,772 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 25.11 06:23:18" (3/3) ... [2022-11-25 18:23:18,773 INFO L112 eAbstractionObserver]: Analyzing ICFG 20051113-1.i [2022-11-25 18:23:18,793 INFO L203 ceAbstractionStarter]: Automizer settings: Hoare:false NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2022-11-25 18:23:18,794 INFO L162 ceAbstractionStarter]: Applying trace abstraction to program that has 25 error locations. [2022-11-25 18:23:18,836 INFO L356 AbstractCegarLoop]: ======== Iteration 0 == of CEGAR loop == AllErrorsAtOnce ======== [2022-11-25 18:23:18,842 INFO L357 AbstractCegarLoop]: Settings: SEPARATE_VIOLATION_CHECK=true, mInterprocedural=true, mMaxIterations=1000000, mWatchIteration=1000000, mArtifact=RCFG, mInterpolation=FPandBP, mInterpolantAutomaton=STRAIGHT_LINE, mDumpAutomata=false, mAutomataFormat=ATS_NUMERATE, mDumpPath=., mDeterminiation=PREDICATE_ABSTRACTION, mMinimize=MINIMIZE_SEVPA, mHoare=false, mAutomataTypeConcurrency=PETRI_NET, mHoareTripleChecks=INCREMENTAL, mHoareAnnotationPositions=All, mDumpOnlyReuseAutomata=false, mLimitTraceHistogram=0, mErrorLocTimeLimit=0, mLimitPathProgramCount=0, mCollectInterpolantStatistics=true, mHeuristicEmptinessCheck=false, mHeuristicEmptinessCheckAStarHeuristic=ZERO, mHeuristicEmptinessCheckAStarHeuristicRandomSeed=1337, mHeuristicEmptinessCheckSmtFeatureScoringMethod=DAGSIZE, mSMTFeatureExtraction=false, mSMTFeatureExtractionDumpPath=., mOverrideInterpolantAutomaton=false, mMcrInterpolantMethod=WP, mPorIndependenceSettings=[Lde.uni_freiburg.informatik.ultimate.lib.tracecheckerutils.partialorder.independence.IndependenceSettings;@4c176aca, mLbeIndependenceSettings=[IndependenceType=SEMANTIC, AbstractionType=NONE, UseConditional=false, UseSemiCommutativity=true, Solver=Z3, SolverTimeout=1000ms] [2022-11-25 18:23:18,842 INFO L358 AbstractCegarLoop]: Starting to check reachability of 25 error locations. [2022-11-25 18:23:18,846 INFO L276 IsEmpty]: Start isEmpty. Operand has 64 states, 35 states have (on average 1.9142857142857144) internal successors, (67), 62 states have internal predecessors, (67), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2022-11-25 18:23:18,851 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 4 [2022-11-25 18:23:18,851 INFO L187 NwaCegarLoop]: Found error trace [2022-11-25 18:23:18,851 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1] [2022-11-25 18:23:18,852 INFO L420 AbstractCegarLoop]: === Iteration 1 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE === [ULTIMATE.startErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr2REQUIRES_VIOLATIONMEMORY_DEREFERENCE (and 22 more)] === [2022-11-25 18:23:18,857 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 18:23:18,858 INFO L85 PathProgramCache]: Analyzing trace with hash 30849, now seen corresponding path program 1 times [2022-11-25 18:23:18,865 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 18:23:18,866 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [561214130] [2022-11-25 18:23:18,866 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 18:23:18,866 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 18:23:18,968 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-25 18:23:19,128 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-25 18:23:19,133 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-25 18:23:19,133 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [561214130] [2022-11-25 18:23:19,134 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [561214130] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-25 18:23:19,134 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-25 18:23:19,135 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-11-25 18:23:19,136 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [801528405] [2022-11-25 18:23:19,138 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-25 18:23:19,143 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 3 states [2022-11-25 18:23:19,144 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-25 18:23:19,190 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-25 18:23:19,191 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-25 18:23:19,193 INFO L87 Difference]: Start difference. First operand has 64 states, 35 states have (on average 1.9142857142857144) internal successors, (67), 62 states have internal predecessors, (67), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) Second operand has 3 states, 2 states have (on average 1.5) internal successors, (3), 3 states have internal predecessors, (3), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 18:23:19,315 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-25 18:23:19,316 INFO L93 Difference]: Finished difference Result 63 states and 68 transitions. [2022-11-25 18:23:19,318 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-25 18:23:19,319 INFO L78 Accepts]: Start accepts. Automaton has has 3 states, 2 states have (on average 1.5) internal successors, (3), 3 states have internal predecessors, (3), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 3 [2022-11-25 18:23:19,321 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-25 18:23:19,328 INFO L225 Difference]: With dead ends: 63 [2022-11-25 18:23:19,329 INFO L226 Difference]: Without dead ends: 61 [2022-11-25 18:23:19,331 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-25 18:23:19,336 INFO L413 NwaCegarLoop]: 39 mSDtfsCounter, 61 mSDsluCounter, 1 mSDsCounter, 0 mSdLazyCounter, 32 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 63 SdHoareTripleChecker+Valid, 40 SdHoareTripleChecker+Invalid, 32 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 32 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-11-25 18:23:19,338 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [63 Valid, 40 Invalid, 32 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 32 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2022-11-25 18:23:19,356 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 61 states. [2022-11-25 18:23:19,379 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 61 to 61. [2022-11-25 18:23:19,381 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 61 states, 34 states have (on average 1.8235294117647058) internal successors, (62), 59 states have internal predecessors, (62), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2022-11-25 18:23:19,384 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 61 states to 61 states and 66 transitions. [2022-11-25 18:23:19,386 INFO L78 Accepts]: Start accepts. Automaton has 61 states and 66 transitions. Word has length 3 [2022-11-25 18:23:19,387 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-25 18:23:19,387 INFO L495 AbstractCegarLoop]: Abstraction has 61 states and 66 transitions. [2022-11-25 18:23:19,388 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 3 states, 2 states have (on average 1.5) internal successors, (3), 3 states have internal predecessors, (3), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 18:23:19,388 INFO L276 IsEmpty]: Start isEmpty. Operand 61 states and 66 transitions. [2022-11-25 18:23:19,388 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 5 [2022-11-25 18:23:19,389 INFO L187 NwaCegarLoop]: Found error trace [2022-11-25 18:23:19,389 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1] [2022-11-25 18:23:19,389 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable0 [2022-11-25 18:23:19,390 INFO L420 AbstractCegarLoop]: === Iteration 2 === Targeting ULTIMATE.startErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE === [ULTIMATE.startErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr2REQUIRES_VIOLATIONMEMORY_DEREFERENCE (and 22 more)] === [2022-11-25 18:23:19,392 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 18:23:19,392 INFO L85 PathProgramCache]: Analyzing trace with hash 956356, now seen corresponding path program 1 times [2022-11-25 18:23:19,392 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 18:23:19,392 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1235232596] [2022-11-25 18:23:19,393 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 18:23:19,393 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 18:23:19,421 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-25 18:23:19,624 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-25 18:23:19,625 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-25 18:23:19,625 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1235232596] [2022-11-25 18:23:19,625 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1235232596] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-25 18:23:19,626 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-25 18:23:19,626 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-11-25 18:23:19,626 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [337882339] [2022-11-25 18:23:19,626 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-25 18:23:19,627 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 3 states [2022-11-25 18:23:19,628 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-25 18:23:19,628 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-25 18:23:19,629 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-25 18:23:19,629 INFO L87 Difference]: Start difference. First operand 61 states and 66 transitions. Second operand has 3 states, 2 states have (on average 2.0) internal successors, (4), 3 states have internal predecessors, (4), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 18:23:19,714 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-25 18:23:19,715 INFO L93 Difference]: Finished difference Result 60 states and 65 transitions. [2022-11-25 18:23:19,715 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-25 18:23:19,715 INFO L78 Accepts]: Start accepts. Automaton has has 3 states, 2 states have (on average 2.0) internal successors, (4), 3 states have internal predecessors, (4), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 4 [2022-11-25 18:23:19,716 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-25 18:23:19,716 INFO L225 Difference]: With dead ends: 60 [2022-11-25 18:23:19,717 INFO L226 Difference]: Without dead ends: 60 [2022-11-25 18:23:19,717 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-25 18:23:19,719 INFO L413 NwaCegarLoop]: 38 mSDtfsCounter, 57 mSDsluCounter, 1 mSDsCounter, 0 mSdLazyCounter, 30 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 59 SdHoareTripleChecker+Valid, 39 SdHoareTripleChecker+Invalid, 30 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 30 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-11-25 18:23:19,719 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [59 Valid, 39 Invalid, 30 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 30 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2022-11-25 18:23:19,720 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 60 states. [2022-11-25 18:23:19,725 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 60 to 60. [2022-11-25 18:23:19,725 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 60 states, 34 states have (on average 1.7941176470588236) internal successors, (61), 58 states have internal predecessors, (61), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2022-11-25 18:23:19,726 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 60 states to 60 states and 65 transitions. [2022-11-25 18:23:19,727 INFO L78 Accepts]: Start accepts. Automaton has 60 states and 65 transitions. Word has length 4 [2022-11-25 18:23:19,727 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-25 18:23:19,727 INFO L495 AbstractCegarLoop]: Abstraction has 60 states and 65 transitions. [2022-11-25 18:23:19,728 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 3 states, 2 states have (on average 2.0) internal successors, (4), 3 states have internal predecessors, (4), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 18:23:19,728 INFO L276 IsEmpty]: Start isEmpty. Operand 60 states and 65 transitions. [2022-11-25 18:23:19,728 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 8 [2022-11-25 18:23:19,728 INFO L187 NwaCegarLoop]: Found error trace [2022-11-25 18:23:19,729 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1] [2022-11-25 18:23:19,729 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable1 [2022-11-25 18:23:19,729 INFO L420 AbstractCegarLoop]: === Iteration 3 === Targeting ULTIMATE.startErr2REQUIRES_VIOLATIONMEMORY_DEREFERENCE === [ULTIMATE.startErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr2REQUIRES_VIOLATIONMEMORY_DEREFERENCE (and 22 more)] === [2022-11-25 18:23:19,730 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 18:23:19,730 INFO L85 PathProgramCache]: Analyzing trace with hash -1573926710, now seen corresponding path program 1 times [2022-11-25 18:23:19,730 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 18:23:19,731 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [592344062] [2022-11-25 18:23:19,731 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 18:23:19,731 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 18:23:19,744 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-25 18:23:19,852 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-25 18:23:19,853 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-25 18:23:19,854 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [592344062] [2022-11-25 18:23:19,855 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [592344062] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-25 18:23:19,855 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-25 18:23:19,855 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2022-11-25 18:23:19,855 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1042128284] [2022-11-25 18:23:19,857 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-25 18:23:19,857 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2022-11-25 18:23:19,857 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-25 18:23:19,858 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-11-25 18:23:19,858 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2022-11-25 18:23:19,859 INFO L87 Difference]: Start difference. First operand 60 states and 65 transitions. Second operand has 5 states, 4 states have (on average 1.75) internal successors, (7), 5 states have internal predecessors, (7), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 18:23:19,949 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-25 18:23:19,950 INFO L93 Difference]: Finished difference Result 53 states and 58 transitions. [2022-11-25 18:23:19,950 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-25 18:23:19,951 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 4 states have (on average 1.75) internal successors, (7), 5 states have internal predecessors, (7), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 7 [2022-11-25 18:23:19,951 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-25 18:23:19,952 INFO L225 Difference]: With dead ends: 53 [2022-11-25 18:23:19,952 INFO L226 Difference]: Without dead ends: 53 [2022-11-25 18:23:19,952 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2022-11-25 18:23:19,953 INFO L413 NwaCegarLoop]: 30 mSDtfsCounter, 92 mSDsluCounter, 2 mSDsCounter, 0 mSdLazyCounter, 38 mSolverCounterSat, 9 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 94 SdHoareTripleChecker+Valid, 32 SdHoareTripleChecker+Invalid, 47 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 9 IncrementalHoareTripleChecker+Valid, 38 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-11-25 18:23:19,954 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [94 Valid, 32 Invalid, 47 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [9 Valid, 38 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2022-11-25 18:23:19,955 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 53 states. [2022-11-25 18:23:19,958 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 53 to 53. [2022-11-25 18:23:19,959 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 53 states, 34 states have (on average 1.588235294117647) internal successors, (54), 51 states have internal predecessors, (54), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2022-11-25 18:23:19,960 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 53 states to 53 states and 58 transitions. [2022-11-25 18:23:19,960 INFO L78 Accepts]: Start accepts. Automaton has 53 states and 58 transitions. Word has length 7 [2022-11-25 18:23:19,960 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-25 18:23:19,961 INFO L495 AbstractCegarLoop]: Abstraction has 53 states and 58 transitions. [2022-11-25 18:23:19,961 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 4 states have (on average 1.75) internal successors, (7), 5 states have internal predecessors, (7), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 18:23:19,961 INFO L276 IsEmpty]: Start isEmpty. Operand 53 states and 58 transitions. [2022-11-25 18:23:19,961 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 8 [2022-11-25 18:23:19,961 INFO L187 NwaCegarLoop]: Found error trace [2022-11-25 18:23:19,962 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1] [2022-11-25 18:23:19,962 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable2 [2022-11-25 18:23:19,962 INFO L420 AbstractCegarLoop]: === Iteration 4 === Targeting ULTIMATE.startErr3REQUIRES_VIOLATIONMEMORY_DEREFERENCE === [ULTIMATE.startErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr2REQUIRES_VIOLATIONMEMORY_DEREFERENCE (and 22 more)] === [2022-11-25 18:23:19,963 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 18:23:19,963 INFO L85 PathProgramCache]: Analyzing trace with hash -1573926709, now seen corresponding path program 1 times [2022-11-25 18:23:19,963 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 18:23:19,963 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1919164386] [2022-11-25 18:23:19,964 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 18:23:19,964 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 18:23:19,975 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-25 18:23:20,086 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-25 18:23:20,087 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-25 18:23:20,087 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1919164386] [2022-11-25 18:23:20,087 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1919164386] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-25 18:23:20,087 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-25 18:23:20,088 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-11-25 18:23:20,088 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [620965687] [2022-11-25 18:23:20,088 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-25 18:23:20,088 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 3 states [2022-11-25 18:23:20,089 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-25 18:23:20,089 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-25 18:23:20,089 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-25 18:23:20,090 INFO L87 Difference]: Start difference. First operand 53 states and 58 transitions. Second operand has 3 states, 2 states have (on average 3.5) internal successors, (7), 3 states have internal predecessors, (7), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 18:23:20,148 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-25 18:23:20,149 INFO L93 Difference]: Finished difference Result 46 states and 51 transitions. [2022-11-25 18:23:20,149 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-25 18:23:20,149 INFO L78 Accepts]: Start accepts. Automaton has has 3 states, 2 states have (on average 3.5) internal successors, (7), 3 states have internal predecessors, (7), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 7 [2022-11-25 18:23:20,150 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-25 18:23:20,150 INFO L225 Difference]: With dead ends: 46 [2022-11-25 18:23:20,155 INFO L226 Difference]: Without dead ends: 46 [2022-11-25 18:23:20,155 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-25 18:23:20,157 INFO L413 NwaCegarLoop]: 33 mSDtfsCounter, 38 mSDsluCounter, 2 mSDsCounter, 0 mSdLazyCounter, 22 mSolverCounterSat, 6 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 40 SdHoareTripleChecker+Valid, 35 SdHoareTripleChecker+Invalid, 28 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 6 IncrementalHoareTripleChecker+Valid, 22 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-11-25 18:23:20,158 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [40 Valid, 35 Invalid, 28 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [6 Valid, 22 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2022-11-25 18:23:20,159 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 46 states. [2022-11-25 18:23:20,164 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 46 to 46. [2022-11-25 18:23:20,168 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 46 states, 34 states have (on average 1.3823529411764706) internal successors, (47), 44 states have internal predecessors, (47), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2022-11-25 18:23:20,169 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 46 states to 46 states and 51 transitions. [2022-11-25 18:23:20,169 INFO L78 Accepts]: Start accepts. Automaton has 46 states and 51 transitions. Word has length 7 [2022-11-25 18:23:20,169 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-25 18:23:20,169 INFO L495 AbstractCegarLoop]: Abstraction has 46 states and 51 transitions. [2022-11-25 18:23:20,171 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 3 states, 2 states have (on average 3.5) internal successors, (7), 3 states have internal predecessors, (7), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 18:23:20,172 INFO L276 IsEmpty]: Start isEmpty. Operand 46 states and 51 transitions. [2022-11-25 18:23:20,172 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 16 [2022-11-25 18:23:20,172 INFO L187 NwaCegarLoop]: Found error trace [2022-11-25 18:23:20,172 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 18:23:20,173 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable3 [2022-11-25 18:23:20,173 INFO L420 AbstractCegarLoop]: === Iteration 5 === Targeting ULTIMATE.startErr16REQUIRES_VIOLATIONMEMORY_DEREFERENCE === [ULTIMATE.startErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr2REQUIRES_VIOLATIONMEMORY_DEREFERENCE (and 22 more)] === [2022-11-25 18:23:20,174 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 18:23:20,175 INFO L85 PathProgramCache]: Analyzing trace with hash 1365553495, now seen corresponding path program 1 times [2022-11-25 18:23:20,175 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 18:23:20,175 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [850313706] [2022-11-25 18:23:20,175 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 18:23:20,176 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 18:23:20,218 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-25 18:23:20,374 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-25 18:23:20,374 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-25 18:23:20,375 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [850313706] [2022-11-25 18:23:20,375 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [850313706] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-25 18:23:20,375 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-25 18:23:20,375 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-11-25 18:23:20,376 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1085528642] [2022-11-25 18:23:20,376 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-25 18:23:20,376 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2022-11-25 18:23:20,376 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-25 18:23:20,377 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2022-11-25 18:23:20,378 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2022-11-25 18:23:20,378 INFO L87 Difference]: Start difference. First operand 46 states and 51 transitions. Second operand has 6 states, 5 states have (on average 3.0) internal successors, (15), 6 states have internal predecessors, (15), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 18:23:20,454 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-25 18:23:20,455 INFO L93 Difference]: Finished difference Result 44 states and 49 transitions. [2022-11-25 18:23:20,455 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2022-11-25 18:23:20,456 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 5 states have (on average 3.0) internal successors, (15), 6 states have internal predecessors, (15), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 15 [2022-11-25 18:23:20,456 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-25 18:23:20,456 INFO L225 Difference]: With dead ends: 44 [2022-11-25 18:23:20,457 INFO L226 Difference]: Without dead ends: 44 [2022-11-25 18:23:20,457 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2022-11-25 18:23:20,459 INFO L413 NwaCegarLoop]: 27 mSDtfsCounter, 66 mSDsluCounter, 8 mSDsCounter, 0 mSdLazyCounter, 49 mSolverCounterSat, 6 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 66 SdHoareTripleChecker+Valid, 35 SdHoareTripleChecker+Invalid, 55 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 6 IncrementalHoareTripleChecker+Valid, 49 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-11-25 18:23:20,459 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [66 Valid, 35 Invalid, 55 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [6 Valid, 49 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2022-11-25 18:23:20,460 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 44 states. [2022-11-25 18:23:20,463 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 44 to 44. [2022-11-25 18:23:20,464 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 44 states, 34 states have (on average 1.3235294117647058) internal successors, (45), 42 states have internal predecessors, (45), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2022-11-25 18:23:20,465 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 44 states to 44 states and 49 transitions. [2022-11-25 18:23:20,465 INFO L78 Accepts]: Start accepts. Automaton has 44 states and 49 transitions. Word has length 15 [2022-11-25 18:23:20,465 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-25 18:23:20,466 INFO L495 AbstractCegarLoop]: Abstraction has 44 states and 49 transitions. [2022-11-25 18:23:20,466 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 5 states have (on average 3.0) internal successors, (15), 6 states have internal predecessors, (15), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 18:23:20,466 INFO L276 IsEmpty]: Start isEmpty. Operand 44 states and 49 transitions. [2022-11-25 18:23:20,467 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 16 [2022-11-25 18:23:20,467 INFO L187 NwaCegarLoop]: Found error trace [2022-11-25 18:23:20,467 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 18:23:20,467 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable4 [2022-11-25 18:23:20,468 INFO L420 AbstractCegarLoop]: === Iteration 6 === Targeting ULTIMATE.startErr17REQUIRES_VIOLATIONMEMORY_DEREFERENCE === [ULTIMATE.startErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr2REQUIRES_VIOLATIONMEMORY_DEREFERENCE (and 22 more)] === [2022-11-25 18:23:20,468 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 18:23:20,469 INFO L85 PathProgramCache]: Analyzing trace with hash 1365553496, now seen corresponding path program 1 times [2022-11-25 18:23:20,469 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 18:23:20,469 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1774280940] [2022-11-25 18:23:20,469 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 18:23:20,470 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 18:23:20,488 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-25 18:23:20,721 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-25 18:23:20,721 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-25 18:23:20,721 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1774280940] [2022-11-25 18:23:20,722 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1774280940] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-25 18:23:20,722 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-25 18:23:20,722 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-25 18:23:20,722 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [826917312] [2022-11-25 18:23:20,722 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-25 18:23:20,724 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2022-11-25 18:23:20,724 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-25 18:23:20,725 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-11-25 18:23:20,726 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-11-25 18:23:20,726 INFO L87 Difference]: Start difference. First operand 44 states and 49 transitions. Second operand has 4 states, 3 states have (on average 5.0) internal successors, (15), 4 states have internal predecessors, (15), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 18:23:20,794 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-25 18:23:20,794 INFO L93 Difference]: Finished difference Result 43 states and 48 transitions. [2022-11-25 18:23:20,796 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2022-11-25 18:23:20,796 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 3 states have (on average 5.0) internal successors, (15), 4 states have internal predecessors, (15), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 15 [2022-11-25 18:23:20,798 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-25 18:23:20,799 INFO L225 Difference]: With dead ends: 43 [2022-11-25 18:23:20,799 INFO L226 Difference]: Without dead ends: 43 [2022-11-25 18:23:20,799 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2022-11-25 18:23:20,805 INFO L413 NwaCegarLoop]: 31 mSDtfsCounter, 56 mSDsluCounter, 7 mSDsCounter, 0 mSdLazyCounter, 33 mSolverCounterSat, 4 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 56 SdHoareTripleChecker+Valid, 38 SdHoareTripleChecker+Invalid, 37 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 4 IncrementalHoareTripleChecker+Valid, 33 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-11-25 18:23:20,809 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [56 Valid, 38 Invalid, 37 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [4 Valid, 33 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2022-11-25 18:23:20,811 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 43 states. [2022-11-25 18:23:20,817 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 43 to 43. [2022-11-25 18:23:20,817 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 43 states, 34 states have (on average 1.2941176470588236) internal successors, (44), 41 states have internal predecessors, (44), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2022-11-25 18:23:20,821 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 43 states to 43 states and 48 transitions. [2022-11-25 18:23:20,822 INFO L78 Accepts]: Start accepts. Automaton has 43 states and 48 transitions. Word has length 15 [2022-11-25 18:23:20,822 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-25 18:23:20,823 INFO L495 AbstractCegarLoop]: Abstraction has 43 states and 48 transitions. [2022-11-25 18:23:20,823 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 3 states have (on average 5.0) internal successors, (15), 4 states have internal predecessors, (15), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 18:23:20,823 INFO L276 IsEmpty]: Start isEmpty. Operand 43 states and 48 transitions. [2022-11-25 18:23:20,824 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 18 [2022-11-25 18:23:20,824 INFO L187 NwaCegarLoop]: Found error trace [2022-11-25 18:23:20,824 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 18:23:20,825 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable5 [2022-11-25 18:23:20,825 INFO L420 AbstractCegarLoop]: === Iteration 7 === Targeting ULTIMATE.startErr19REQUIRES_VIOLATIONMEMORY_DEREFERENCE === [ULTIMATE.startErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr2REQUIRES_VIOLATIONMEMORY_DEREFERENCE (and 22 more)] === [2022-11-25 18:23:20,827 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 18:23:20,827 INFO L85 PathProgramCache]: Analyzing trace with hash -1963083303, now seen corresponding path program 1 times [2022-11-25 18:23:20,828 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 18:23:20,828 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [252517380] [2022-11-25 18:23:20,829 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 18:23:20,829 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 18:23:20,874 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-25 18:23:21,087 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-25 18:23:21,088 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-25 18:23:21,088 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [252517380] [2022-11-25 18:23:21,089 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [252517380] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-25 18:23:21,089 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-25 18:23:21,089 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-25 18:23:21,089 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1821684792] [2022-11-25 18:23:21,090 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-25 18:23:21,091 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2022-11-25 18:23:21,091 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-25 18:23:21,092 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-11-25 18:23:21,092 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-11-25 18:23:21,093 INFO L87 Difference]: Start difference. First operand 43 states and 48 transitions. Second operand has 4 states, 3 states have (on average 5.666666666666667) internal successors, (17), 4 states have internal predecessors, (17), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 18:23:21,197 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-25 18:23:21,197 INFO L93 Difference]: Finished difference Result 69 states and 79 transitions. [2022-11-25 18:23:21,197 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2022-11-25 18:23:21,198 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 3 states have (on average 5.666666666666667) internal successors, (17), 4 states have internal predecessors, (17), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 17 [2022-11-25 18:23:21,198 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-25 18:23:21,202 INFO L225 Difference]: With dead ends: 69 [2022-11-25 18:23:21,202 INFO L226 Difference]: Without dead ends: 69 [2022-11-25 18:23:21,203 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2022-11-25 18:23:21,206 INFO L413 NwaCegarLoop]: 30 mSDtfsCounter, 77 mSDsluCounter, 24 mSDsCounter, 0 mSdLazyCounter, 49 mSolverCounterSat, 4 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 79 SdHoareTripleChecker+Valid, 54 SdHoareTripleChecker+Invalid, 53 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 4 IncrementalHoareTripleChecker+Valid, 49 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-11-25 18:23:21,207 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [79 Valid, 54 Invalid, 53 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [4 Valid, 49 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2022-11-25 18:23:21,210 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 69 states. [2022-11-25 18:23:21,214 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 69 to 46. [2022-11-25 18:23:21,215 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 46 states, 37 states have (on average 1.2972972972972974) internal successors, (48), 44 states have internal predecessors, (48), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2022-11-25 18:23:21,216 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 46 states to 46 states and 52 transitions. [2022-11-25 18:23:21,216 INFO L78 Accepts]: Start accepts. Automaton has 46 states and 52 transitions. Word has length 17 [2022-11-25 18:23:21,216 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-25 18:23:21,216 INFO L495 AbstractCegarLoop]: Abstraction has 46 states and 52 transitions. [2022-11-25 18:23:21,217 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 3 states have (on average 5.666666666666667) internal successors, (17), 4 states have internal predecessors, (17), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 18:23:21,217 INFO L276 IsEmpty]: Start isEmpty. Operand 46 states and 52 transitions. [2022-11-25 18:23:21,218 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 22 [2022-11-25 18:23:21,218 INFO L187 NwaCegarLoop]: Found error trace [2022-11-25 18:23:21,218 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 18:23:21,218 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable6 [2022-11-25 18:23:21,219 INFO L420 AbstractCegarLoop]: === Iteration 8 === Targeting ULTIMATE.startErr20REQUIRES_VIOLATIONMEMORY_DEREFERENCE === [ULTIMATE.startErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr2REQUIRES_VIOLATIONMEMORY_DEREFERENCE (and 22 more)] === [2022-11-25 18:23:21,219 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 18:23:21,219 INFO L85 PathProgramCache]: Analyzing trace with hash -58695891, now seen corresponding path program 1 times [2022-11-25 18:23:21,220 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 18:23:21,220 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1536483265] [2022-11-25 18:23:21,220 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 18:23:21,220 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 18:23:21,236 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-25 18:23:21,306 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-25 18:23:21,307 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-25 18:23:21,307 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1536483265] [2022-11-25 18:23:21,307 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1536483265] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-25 18:23:21,308 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-25 18:23:21,308 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2022-11-25 18:23:21,308 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [931278959] [2022-11-25 18:23:21,308 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-25 18:23:21,309 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2022-11-25 18:23:21,309 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-25 18:23:21,309 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-11-25 18:23:21,310 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-11-25 18:23:21,310 INFO L87 Difference]: Start difference. First operand 46 states and 52 transitions. Second operand has 5 states, 4 states have (on average 5.25) internal successors, (21), 5 states have internal predecessors, (21), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 18:23:21,401 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-25 18:23:21,402 INFO L93 Difference]: Finished difference Result 44 states and 50 transitions. [2022-11-25 18:23:21,402 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-11-25 18:23:21,403 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 4 states have (on average 5.25) internal successors, (21), 5 states have internal predecessors, (21), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 21 [2022-11-25 18:23:21,403 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-25 18:23:21,404 INFO L225 Difference]: With dead ends: 44 [2022-11-25 18:23:21,404 INFO L226 Difference]: Without dead ends: 44 [2022-11-25 18:23:21,404 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2022-11-25 18:23:21,405 INFO L413 NwaCegarLoop]: 27 mSDtfsCounter, 70 mSDsluCounter, 20 mSDsCounter, 0 mSdLazyCounter, 54 mSolverCounterSat, 7 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 70 SdHoareTripleChecker+Valid, 47 SdHoareTripleChecker+Invalid, 61 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 7 IncrementalHoareTripleChecker+Valid, 54 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-11-25 18:23:21,405 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [70 Valid, 47 Invalid, 61 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [7 Valid, 54 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2022-11-25 18:23:21,406 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 44 states. [2022-11-25 18:23:21,408 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 44 to 44. [2022-11-25 18:23:21,409 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 44 states, 37 states have (on average 1.2432432432432432) internal successors, (46), 42 states have internal predecessors, (46), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2022-11-25 18:23:21,410 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 44 states to 44 states and 50 transitions. [2022-11-25 18:23:21,410 INFO L78 Accepts]: Start accepts. Automaton has 44 states and 50 transitions. Word has length 21 [2022-11-25 18:23:21,410 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-25 18:23:21,410 INFO L495 AbstractCegarLoop]: Abstraction has 44 states and 50 transitions. [2022-11-25 18:23:21,411 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 4 states have (on average 5.25) internal successors, (21), 5 states have internal predecessors, (21), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 18:23:21,411 INFO L276 IsEmpty]: Start isEmpty. Operand 44 states and 50 transitions. [2022-11-25 18:23:21,411 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 22 [2022-11-25 18:23:21,412 INFO L187 NwaCegarLoop]: Found error trace [2022-11-25 18:23:21,412 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 18:23:21,412 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable7 [2022-11-25 18:23:21,412 INFO L420 AbstractCegarLoop]: === Iteration 9 === Targeting ULTIMATE.startErr21REQUIRES_VIOLATIONMEMORY_DEREFERENCE === [ULTIMATE.startErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr2REQUIRES_VIOLATIONMEMORY_DEREFERENCE (and 22 more)] === [2022-11-25 18:23:21,413 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 18:23:21,413 INFO L85 PathProgramCache]: Analyzing trace with hash -58695890, now seen corresponding path program 1 times [2022-11-25 18:23:21,413 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 18:23:21,414 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [212882940] [2022-11-25 18:23:21,414 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 18:23:21,414 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 18:23:21,430 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-25 18:23:21,488 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-25 18:23:21,489 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-25 18:23:21,489 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [212882940] [2022-11-25 18:23:21,489 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [212882940] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-25 18:23:21,489 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-25 18:23:21,490 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-11-25 18:23:21,490 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1535070110] [2022-11-25 18:23:21,490 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-25 18:23:21,490 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2022-11-25 18:23:21,491 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-25 18:23:21,491 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-11-25 18:23:21,491 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-11-25 18:23:21,492 INFO L87 Difference]: Start difference. First operand 44 states and 50 transitions. Second operand has 5 states, 5 states have (on average 4.2) internal successors, (21), 5 states have internal predecessors, (21), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 18:23:21,534 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-25 18:23:21,534 INFO L93 Difference]: Finished difference Result 64 states and 73 transitions. [2022-11-25 18:23:21,535 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2022-11-25 18:23:21,535 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 4.2) internal successors, (21), 5 states have internal predecessors, (21), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 21 [2022-11-25 18:23:21,535 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-25 18:23:21,536 INFO L225 Difference]: With dead ends: 64 [2022-11-25 18:23:21,536 INFO L226 Difference]: Without dead ends: 64 [2022-11-25 18:23:21,536 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2022-11-25 18:23:21,537 INFO L413 NwaCegarLoop]: 44 mSDtfsCounter, 37 mSDsluCounter, 127 mSDsCounter, 0 mSdLazyCounter, 16 mSolverCounterSat, 4 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 37 SdHoareTripleChecker+Valid, 171 SdHoareTripleChecker+Invalid, 20 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 4 IncrementalHoareTripleChecker+Valid, 16 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2022-11-25 18:23:21,537 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [37 Valid, 171 Invalid, 20 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [4 Valid, 16 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2022-11-25 18:23:21,538 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 64 states. [2022-11-25 18:23:21,540 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 64 to 47. [2022-11-25 18:23:21,541 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 47 states, 40 states have (on average 1.225) internal successors, (49), 45 states have internal predecessors, (49), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2022-11-25 18:23:21,541 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 47 states to 47 states and 53 transitions. [2022-11-25 18:23:21,542 INFO L78 Accepts]: Start accepts. Automaton has 47 states and 53 transitions. Word has length 21 [2022-11-25 18:23:21,542 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-25 18:23:21,542 INFO L495 AbstractCegarLoop]: Abstraction has 47 states and 53 transitions. [2022-11-25 18:23:21,542 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 4.2) internal successors, (21), 5 states have internal predecessors, (21), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 18:23:21,543 INFO L276 IsEmpty]: Start isEmpty. Operand 47 states and 53 transitions. [2022-11-25 18:23:21,543 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 23 [2022-11-25 18:23:21,543 INFO L187 NwaCegarLoop]: Found error trace [2022-11-25 18:23:21,544 INFO L195 NwaCegarLoop]: trace histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 18:23:21,544 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable8 [2022-11-25 18:23:21,544 INFO L420 AbstractCegarLoop]: === Iteration 10 === Targeting ULTIMATE.startErr19REQUIRES_VIOLATIONMEMORY_DEREFERENCE === [ULTIMATE.startErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr2REQUIRES_VIOLATIONMEMORY_DEREFERENCE (and 22 more)] === [2022-11-25 18:23:21,545 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 18:23:21,545 INFO L85 PathProgramCache]: Analyzing trace with hash -309999949, now seen corresponding path program 1 times [2022-11-25 18:23:21,545 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 18:23:21,545 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1434618648] [2022-11-25 18:23:21,545 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 18:23:21,546 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 18:23:21,562 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-25 18:23:21,769 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-25 18:23:21,769 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-25 18:23:21,769 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1434618648] [2022-11-25 18:23:21,769 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1434618648] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-25 18:23:21,770 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [25841535] [2022-11-25 18:23:21,770 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 18:23:21,770 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-25 18:23:21,770 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f26c41a-56d7-4548-8d02-7cd563b233b6/bin/uautomizer-ZsLfNo2U6R/z3 [2022-11-25 18:23:21,775 INFO L229 MonitoredProcess]: Starting monitored process 2 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f26c41a-56d7-4548-8d02-7cd563b233b6/bin/uautomizer-ZsLfNo2U6R/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-25 18:23:21,788 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f26c41a-56d7-4548-8d02-7cd563b233b6/bin/uautomizer-ZsLfNo2U6R/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Waiting until timeout for monitored process [2022-11-25 18:23:21,880 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-25 18:23:21,882 INFO L263 TraceCheckSpWp]: Trace formula consists of 148 conjuncts, 18 conjunts are in the unsatisfiable core [2022-11-25 18:23:21,888 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-25 18:23:22,137 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-25 18:23:22,137 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-25 18:23:22,398 INFO L321 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-11-25 18:23:22,399 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 13 treesize of output 17 [2022-11-25 18:23:22,458 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-25 18:23:22,458 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [25841535] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-25 18:23:22,458 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-25 18:23:22,458 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 6, 6] total 13 [2022-11-25 18:23:22,459 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1832513787] [2022-11-25 18:23:22,459 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-25 18:23:22,459 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 14 states [2022-11-25 18:23:22,459 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-25 18:23:22,460 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2022-11-25 18:23:22,460 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=42, Invalid=140, Unknown=0, NotChecked=0, Total=182 [2022-11-25 18:23:22,460 INFO L87 Difference]: Start difference. First operand 47 states and 53 transitions. Second operand has 14 states, 13 states have (on average 4.6923076923076925) internal successors, (61), 14 states have internal predecessors, (61), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 18:23:22,810 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-25 18:23:22,810 INFO L93 Difference]: Finished difference Result 111 states and 130 transitions. [2022-11-25 18:23:22,810 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2022-11-25 18:23:22,811 INFO L78 Accepts]: Start accepts. Automaton has has 14 states, 13 states have (on average 4.6923076923076925) internal successors, (61), 14 states have internal predecessors, (61), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 22 [2022-11-25 18:23:22,811 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-25 18:23:22,812 INFO L225 Difference]: With dead ends: 111 [2022-11-25 18:23:22,812 INFO L226 Difference]: Without dead ends: 111 [2022-11-25 18:23:22,812 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 50 GetRequests, 33 SyntacticMatches, 1 SemanticMatches, 16 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 32 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=86, Invalid=220, Unknown=0, NotChecked=0, Total=306 [2022-11-25 18:23:22,813 INFO L413 NwaCegarLoop]: 44 mSDtfsCounter, 417 mSDsluCounter, 104 mSDsCounter, 0 mSdLazyCounter, 182 mSolverCounterSat, 37 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 417 SdHoareTripleChecker+Valid, 148 SdHoareTripleChecker+Invalid, 219 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 37 IncrementalHoareTripleChecker+Valid, 182 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2022-11-25 18:23:22,813 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [417 Valid, 148 Invalid, 219 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [37 Valid, 182 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2022-11-25 18:23:22,814 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 111 states. [2022-11-25 18:23:22,817 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 111 to 57. [2022-11-25 18:23:22,818 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 57 states, 50 states have (on average 1.22) internal successors, (61), 55 states have internal predecessors, (61), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2022-11-25 18:23:22,818 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 57 states to 57 states and 65 transitions. [2022-11-25 18:23:22,819 INFO L78 Accepts]: Start accepts. Automaton has 57 states and 65 transitions. Word has length 22 [2022-11-25 18:23:22,819 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-25 18:23:22,819 INFO L495 AbstractCegarLoop]: Abstraction has 57 states and 65 transitions. [2022-11-25 18:23:22,819 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 14 states, 13 states have (on average 4.6923076923076925) internal successors, (61), 14 states have internal predecessors, (61), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 18:23:22,820 INFO L276 IsEmpty]: Start isEmpty. Operand 57 states and 65 transitions. [2022-11-25 18:23:22,820 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 25 [2022-11-25 18:23:22,820 INFO L187 NwaCegarLoop]: Found error trace [2022-11-25 18:23:22,820 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 18:23:22,832 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f26c41a-56d7-4548-8d02-7cd563b233b6/bin/uautomizer-ZsLfNo2U6R/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Forceful destruction successful, exit code 0 [2022-11-25 18:23:23,027 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 2 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f26c41a-56d7-4548-8d02-7cd563b233b6/bin/uautomizer-ZsLfNo2U6R/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable9 [2022-11-25 18:23:23,027 INFO L420 AbstractCegarLoop]: === Iteration 11 === Targeting ULTIMATE.startErr21REQUIRES_VIOLATIONMEMORY_DEREFERENCE === [ULTIMATE.startErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr2REQUIRES_VIOLATIONMEMORY_DEREFERENCE (and 22 more)] === [2022-11-25 18:23:23,028 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 18:23:23,028 INFO L85 PathProgramCache]: Analyzing trace with hash -612311662, now seen corresponding path program 1 times [2022-11-25 18:23:23,028 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 18:23:23,028 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1327622384] [2022-11-25 18:23:23,028 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 18:23:23,028 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 18:23:23,059 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-25 18:23:23,236 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 19 [2022-11-25 18:23:23,238 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-25 18:23:23,241 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-25 18:23:23,241 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-25 18:23:23,241 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1327622384] [2022-11-25 18:23:23,241 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1327622384] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-25 18:23:23,242 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-25 18:23:23,242 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-25 18:23:23,242 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [503567885] [2022-11-25 18:23:23,242 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-25 18:23:23,243 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2022-11-25 18:23:23,243 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-25 18:23:23,244 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-11-25 18:23:23,244 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-11-25 18:23:23,244 INFO L87 Difference]: Start difference. First operand 57 states and 65 transitions. Second operand has 4 states, 3 states have (on average 7.333333333333333) internal successors, (22), 4 states have internal predecessors, (22), 1 states have call successors, (1), 1 states have call predecessors, (1), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-11-25 18:23:23,315 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-25 18:23:23,316 INFO L93 Difference]: Finished difference Result 56 states and 64 transitions. [2022-11-25 18:23:23,316 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2022-11-25 18:23:23,317 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 3 states have (on average 7.333333333333333) internal successors, (22), 4 states have internal predecessors, (22), 1 states have call successors, (1), 1 states have call predecessors, (1), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 24 [2022-11-25 18:23:23,317 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-25 18:23:23,318 INFO L225 Difference]: With dead ends: 56 [2022-11-25 18:23:23,318 INFO L226 Difference]: Without dead ends: 56 [2022-11-25 18:23:23,318 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2022-11-25 18:23:23,319 INFO L413 NwaCegarLoop]: 29 mSDtfsCounter, 32 mSDsluCounter, 15 mSDsCounter, 0 mSdLazyCounter, 37 mSolverCounterSat, 2 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 32 SdHoareTripleChecker+Valid, 44 SdHoareTripleChecker+Invalid, 39 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Valid, 37 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2022-11-25 18:23:23,319 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [32 Valid, 44 Invalid, 39 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [2 Valid, 37 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2022-11-25 18:23:23,320 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 56 states. [2022-11-25 18:23:23,323 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 56 to 56. [2022-11-25 18:23:23,323 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 56 states, 50 states have (on average 1.2) internal successors, (60), 54 states have internal predecessors, (60), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2022-11-25 18:23:23,324 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 56 states to 56 states and 64 transitions. [2022-11-25 18:23:23,324 INFO L78 Accepts]: Start accepts. Automaton has 56 states and 64 transitions. Word has length 24 [2022-11-25 18:23:23,324 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-25 18:23:23,325 INFO L495 AbstractCegarLoop]: Abstraction has 56 states and 64 transitions. [2022-11-25 18:23:23,325 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 3 states have (on average 7.333333333333333) internal successors, (22), 4 states have internal predecessors, (22), 1 states have call successors, (1), 1 states have call predecessors, (1), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-11-25 18:23:23,325 INFO L276 IsEmpty]: Start isEmpty. Operand 56 states and 64 transitions. [2022-11-25 18:23:23,326 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 27 [2022-11-25 18:23:23,326 INFO L187 NwaCegarLoop]: Found error trace [2022-11-25 18:23:23,326 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 18:23:23,326 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable10 [2022-11-25 18:23:23,327 INFO L420 AbstractCegarLoop]: === Iteration 12 === Targeting ULTIMATE.startErr23REQUIRES_VIOLATIONMEMORY_DEREFERENCE === [ULTIMATE.startErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr2REQUIRES_VIOLATIONMEMORY_DEREFERENCE (and 22 more)] === [2022-11-25 18:23:23,327 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 18:23:23,328 INFO L85 PathProgramCache]: Analyzing trace with hash -20987021, now seen corresponding path program 1 times [2022-11-25 18:23:23,328 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 18:23:23,328 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [284175601] [2022-11-25 18:23:23,328 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 18:23:23,329 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 18:23:23,346 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-25 18:23:23,470 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 19 [2022-11-25 18:23:23,472 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-25 18:23:23,474 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-25 18:23:23,474 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-25 18:23:23,474 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [284175601] [2022-11-25 18:23:23,475 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [284175601] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-25 18:23:23,475 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-25 18:23:23,475 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-25 18:23:23,475 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1233542011] [2022-11-25 18:23:23,475 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-25 18:23:23,476 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2022-11-25 18:23:23,476 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-25 18:23:23,476 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-11-25 18:23:23,477 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-11-25 18:23:23,477 INFO L87 Difference]: Start difference. First operand 56 states and 64 transitions. Second operand has 4 states, 3 states have (on average 8.0) internal successors, (24), 4 states have internal predecessors, (24), 1 states have call successors, (1), 1 states have call predecessors, (1), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-11-25 18:23:23,542 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-25 18:23:23,542 INFO L93 Difference]: Finished difference Result 68 states and 78 transitions. [2022-11-25 18:23:23,543 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2022-11-25 18:23:23,543 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 3 states have (on average 8.0) internal successors, (24), 4 states have internal predecessors, (24), 1 states have call successors, (1), 1 states have call predecessors, (1), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 26 [2022-11-25 18:23:23,543 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-25 18:23:23,544 INFO L225 Difference]: With dead ends: 68 [2022-11-25 18:23:23,544 INFO L226 Difference]: Without dead ends: 68 [2022-11-25 18:23:23,544 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2022-11-25 18:23:23,545 INFO L413 NwaCegarLoop]: 27 mSDtfsCounter, 38 mSDsluCounter, 22 mSDsCounter, 0 mSdLazyCounter, 47 mSolverCounterSat, 2 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 39 SdHoareTripleChecker+Valid, 49 SdHoareTripleChecker+Invalid, 49 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Valid, 47 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2022-11-25 18:23:23,545 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [39 Valid, 49 Invalid, 49 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [2 Valid, 47 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2022-11-25 18:23:23,546 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 68 states. [2022-11-25 18:23:23,548 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 68 to 59. [2022-11-25 18:23:23,548 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 59 states, 53 states have (on average 1.2075471698113207) internal successors, (64), 57 states have internal predecessors, (64), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2022-11-25 18:23:23,549 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 59 states to 59 states and 68 transitions. [2022-11-25 18:23:23,549 INFO L78 Accepts]: Start accepts. Automaton has 59 states and 68 transitions. Word has length 26 [2022-11-25 18:23:23,549 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-25 18:23:23,550 INFO L495 AbstractCegarLoop]: Abstraction has 59 states and 68 transitions. [2022-11-25 18:23:23,550 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 3 states have (on average 8.0) internal successors, (24), 4 states have internal predecessors, (24), 1 states have call successors, (1), 1 states have call predecessors, (1), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-11-25 18:23:23,550 INFO L276 IsEmpty]: Start isEmpty. Operand 59 states and 68 transitions. [2022-11-25 18:23:23,551 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 31 [2022-11-25 18:23:23,551 INFO L187 NwaCegarLoop]: Found error trace [2022-11-25 18:23:23,551 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 18:23:23,551 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable11 [2022-11-25 18:23:23,552 INFO L420 AbstractCegarLoop]: === Iteration 13 === Targeting ULTIMATE.startErr24ASSERT_VIOLATIONMEMORY_LEAK === [ULTIMATE.startErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr2REQUIRES_VIOLATIONMEMORY_DEREFERENCE (and 22 more)] === [2022-11-25 18:23:23,552 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 18:23:23,552 INFO L85 PathProgramCache]: Analyzing trace with hash 1184799620, now seen corresponding path program 1 times [2022-11-25 18:23:23,552 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 18:23:23,553 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1500822803] [2022-11-25 18:23:23,553 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 18:23:23,553 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 18:23:23,569 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-25 18:23:23,621 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 19 [2022-11-25 18:23:23,622 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-25 18:23:23,624 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-25 18:23:23,624 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-25 18:23:23,624 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1500822803] [2022-11-25 18:23:23,624 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1500822803] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-25 18:23:23,625 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-25 18:23:23,625 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-11-25 18:23:23,625 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1275564297] [2022-11-25 18:23:23,625 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-25 18:23:23,625 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2022-11-25 18:23:23,626 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-25 18:23:23,626 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-11-25 18:23:23,626 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-11-25 18:23:23,627 INFO L87 Difference]: Start difference. First operand 59 states and 68 transitions. Second operand has 5 states, 5 states have (on average 5.6) internal successors, (28), 5 states have internal predecessors, (28), 1 states have call successors, (1), 1 states have call predecessors, (1), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-11-25 18:23:23,661 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-25 18:23:23,661 INFO L93 Difference]: Finished difference Result 67 states and 76 transitions. [2022-11-25 18:23:23,661 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2022-11-25 18:23:23,662 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 5.6) internal successors, (28), 5 states have internal predecessors, (28), 1 states have call successors, (1), 1 states have call predecessors, (1), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 30 [2022-11-25 18:23:23,662 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-25 18:23:23,662 INFO L225 Difference]: With dead ends: 67 [2022-11-25 18:23:23,663 INFO L226 Difference]: Without dead ends: 67 [2022-11-25 18:23:23,663 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2022-11-25 18:23:23,664 INFO L413 NwaCegarLoop]: 44 mSDtfsCounter, 11 mSDsluCounter, 125 mSDsCounter, 0 mSdLazyCounter, 16 mSolverCounterSat, 2 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 11 SdHoareTripleChecker+Valid, 169 SdHoareTripleChecker+Invalid, 18 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Valid, 16 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2022-11-25 18:23:23,664 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [11 Valid, 169 Invalid, 18 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [2 Valid, 16 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2022-11-25 18:23:23,665 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 67 states. [2022-11-25 18:23:23,667 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 67 to 62. [2022-11-25 18:23:23,667 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 62 states, 56 states have (on average 1.1964285714285714) internal successors, (67), 60 states have internal predecessors, (67), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2022-11-25 18:23:23,667 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 62 states to 62 states and 71 transitions. [2022-11-25 18:23:23,668 INFO L78 Accepts]: Start accepts. Automaton has 62 states and 71 transitions. Word has length 30 [2022-11-25 18:23:23,668 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-25 18:23:23,668 INFO L495 AbstractCegarLoop]: Abstraction has 62 states and 71 transitions. [2022-11-25 18:23:23,668 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 5.6) internal successors, (28), 5 states have internal predecessors, (28), 1 states have call successors, (1), 1 states have call predecessors, (1), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-11-25 18:23:23,669 INFO L276 IsEmpty]: Start isEmpty. Operand 62 states and 71 transitions. [2022-11-25 18:23:23,669 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 32 [2022-11-25 18:23:23,670 INFO L187 NwaCegarLoop]: Found error trace [2022-11-25 18:23:23,670 INFO L195 NwaCegarLoop]: trace histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 18:23:23,670 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable12 [2022-11-25 18:23:23,670 INFO L420 AbstractCegarLoop]: === Iteration 14 === Targeting ULTIMATE.startErr23REQUIRES_VIOLATIONMEMORY_DEREFERENCE === [ULTIMATE.startErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr2REQUIRES_VIOLATIONMEMORY_DEREFERENCE (and 22 more)] === [2022-11-25 18:23:23,671 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 18:23:23,671 INFO L85 PathProgramCache]: Analyzing trace with hash -416344648, now seen corresponding path program 1 times [2022-11-25 18:23:23,671 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 18:23:23,671 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [404924731] [2022-11-25 18:23:23,672 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 18:23:23,672 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 18:23:23,691 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-25 18:23:23,897 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 19 [2022-11-25 18:23:23,898 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-25 18:23:23,900 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-11-25 18:23:23,900 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-25 18:23:23,900 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [404924731] [2022-11-25 18:23:23,901 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [404924731] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-25 18:23:23,901 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-25 18:23:23,901 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2022-11-25 18:23:23,901 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1258409822] [2022-11-25 18:23:23,901 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-25 18:23:23,901 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 7 states [2022-11-25 18:23:23,902 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-25 18:23:23,902 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2022-11-25 18:23:23,902 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2022-11-25 18:23:23,902 INFO L87 Difference]: Start difference. First operand 62 states and 71 transitions. Second operand has 7 states, 7 states have (on average 4.142857142857143) internal successors, (29), 7 states have internal predecessors, (29), 1 states have call successors, (1), 1 states have call predecessors, (1), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-11-25 18:23:24,059 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-25 18:23:24,060 INFO L93 Difference]: Finished difference Result 73 states and 83 transitions. [2022-11-25 18:23:24,060 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2022-11-25 18:23:24,060 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 4.142857142857143) internal successors, (29), 7 states have internal predecessors, (29), 1 states have call successors, (1), 1 states have call predecessors, (1), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 31 [2022-11-25 18:23:24,061 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-25 18:23:24,061 INFO L225 Difference]: With dead ends: 73 [2022-11-25 18:23:24,061 INFO L226 Difference]: Without dead ends: 73 [2022-11-25 18:23:24,061 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 14 GetRequests, 5 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=33, Invalid=77, Unknown=0, NotChecked=0, Total=110 [2022-11-25 18:23:24,062 INFO L413 NwaCegarLoop]: 41 mSDtfsCounter, 27 mSDsluCounter, 134 mSDsCounter, 0 mSdLazyCounter, 111 mSolverCounterSat, 4 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 27 SdHoareTripleChecker+Valid, 175 SdHoareTripleChecker+Invalid, 115 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 4 IncrementalHoareTripleChecker+Valid, 111 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-11-25 18:23:24,063 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [27 Valid, 175 Invalid, 115 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [4 Valid, 111 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2022-11-25 18:23:24,063 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 73 states. [2022-11-25 18:23:24,067 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 73 to 66. [2022-11-25 18:23:24,067 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 66 states, 59 states have (on average 1.1864406779661016) internal successors, (70), 63 states have internal predecessors, (70), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2022-11-25 18:23:24,068 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 66 states to 66 states and 76 transitions. [2022-11-25 18:23:24,068 INFO L78 Accepts]: Start accepts. Automaton has 66 states and 76 transitions. Word has length 31 [2022-11-25 18:23:24,068 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-25 18:23:24,068 INFO L495 AbstractCegarLoop]: Abstraction has 66 states and 76 transitions. [2022-11-25 18:23:24,068 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 7 states, 7 states have (on average 4.142857142857143) internal successors, (29), 7 states have internal predecessors, (29), 1 states have call successors, (1), 1 states have call predecessors, (1), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-11-25 18:23:24,068 INFO L276 IsEmpty]: Start isEmpty. Operand 66 states and 76 transitions. [2022-11-25 18:23:24,072 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 34 [2022-11-25 18:23:24,073 INFO L187 NwaCegarLoop]: Found error trace [2022-11-25 18:23:24,073 INFO L195 NwaCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 18:23:24,073 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable13 [2022-11-25 18:23:24,073 INFO L420 AbstractCegarLoop]: === Iteration 15 === Targeting ULTIMATE.startErr24ASSERT_VIOLATIONMEMORY_LEAK === [ULTIMATE.startErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr2REQUIRES_VIOLATIONMEMORY_DEREFERENCE (and 22 more)] === [2022-11-25 18:23:24,074 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 18:23:24,074 INFO L85 PathProgramCache]: Analyzing trace with hash 241915192, now seen corresponding path program 1 times [2022-11-25 18:23:24,074 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 18:23:24,074 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1622334479] [2022-11-25 18:23:24,074 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 18:23:24,074 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 18:23:24,097 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-25 18:23:24,460 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 19 [2022-11-25 18:23:24,461 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-25 18:23:24,463 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 28 [2022-11-25 18:23:24,464 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-25 18:23:24,466 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2022-11-25 18:23:24,466 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-25 18:23:24,466 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1622334479] [2022-11-25 18:23:24,466 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1622334479] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-25 18:23:24,466 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-25 18:23:24,467 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-11-25 18:23:24,469 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [187158762] [2022-11-25 18:23:24,469 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-25 18:23:24,469 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2022-11-25 18:23:24,470 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-25 18:23:24,470 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-11-25 18:23:24,470 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-11-25 18:23:24,470 INFO L87 Difference]: Start difference. First operand 66 states and 76 transitions. Second operand has 5 states, 5 states have (on average 5.6) internal successors, (28), 5 states have internal predecessors, (28), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2022-11-25 18:23:24,544 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-25 18:23:24,544 INFO L93 Difference]: Finished difference Result 65 states and 73 transitions. [2022-11-25 18:23:24,545 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2022-11-25 18:23:24,545 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 5.6) internal successors, (28), 5 states have internal predecessors, (28), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) Word has length 33 [2022-11-25 18:23:24,546 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-25 18:23:24,546 INFO L225 Difference]: With dead ends: 65 [2022-11-25 18:23:24,546 INFO L226 Difference]: Without dead ends: 58 [2022-11-25 18:23:24,547 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 17 GetRequests, 12 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2022-11-25 18:23:24,547 INFO L413 NwaCegarLoop]: 31 mSDtfsCounter, 27 mSDsluCounter, 57 mSDsCounter, 0 mSdLazyCounter, 58 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 28 SdHoareTripleChecker+Valid, 88 SdHoareTripleChecker+Invalid, 58 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 58 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-11-25 18:23:24,548 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [28 Valid, 88 Invalid, 58 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 58 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2022-11-25 18:23:24,548 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 58 states. [2022-11-25 18:23:24,550 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 58 to 56. [2022-11-25 18:23:24,550 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 56 states, 50 states have (on average 1.18) internal successors, (59), 54 states have internal predecessors, (59), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2022-11-25 18:23:24,551 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 56 states to 56 states and 63 transitions. [2022-11-25 18:23:24,551 INFO L78 Accepts]: Start accepts. Automaton has 56 states and 63 transitions. Word has length 33 [2022-11-25 18:23:24,551 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-25 18:23:24,551 INFO L495 AbstractCegarLoop]: Abstraction has 56 states and 63 transitions. [2022-11-25 18:23:24,552 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 5.6) internal successors, (28), 5 states have internal predecessors, (28), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2022-11-25 18:23:24,552 INFO L276 IsEmpty]: Start isEmpty. Operand 56 states and 63 transitions. [2022-11-25 18:23:24,552 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 33 [2022-11-25 18:23:24,552 INFO L187 NwaCegarLoop]: Found error trace [2022-11-25 18:23:24,553 INFO L195 NwaCegarLoop]: trace histogram [4, 4, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 18:23:24,553 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable14 [2022-11-25 18:23:24,553 INFO L420 AbstractCegarLoop]: === Iteration 16 === Targeting ULTIMATE.startErr19REQUIRES_VIOLATIONMEMORY_DEREFERENCE === [ULTIMATE.startErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr2REQUIRES_VIOLATIONMEMORY_DEREFERENCE (and 22 more)] === [2022-11-25 18:23:24,554 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 18:23:24,554 INFO L85 PathProgramCache]: Analyzing trace with hash 701429363, now seen corresponding path program 2 times [2022-11-25 18:23:24,554 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 18:23:24,554 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1085222914] [2022-11-25 18:23:24,554 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 18:23:24,555 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 18:23:24,571 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-25 18:23:24,976 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 10 proven. 14 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-25 18:23:24,976 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-25 18:23:24,977 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1085222914] [2022-11-25 18:23:24,977 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1085222914] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-25 18:23:24,977 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2042017812] [2022-11-25 18:23:24,977 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-11-25 18:23:24,977 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-25 18:23:24,977 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f26c41a-56d7-4548-8d02-7cd563b233b6/bin/uautomizer-ZsLfNo2U6R/z3 [2022-11-25 18:23:24,978 INFO L229 MonitoredProcess]: Starting monitored process 3 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f26c41a-56d7-4548-8d02-7cd563b233b6/bin/uautomizer-ZsLfNo2U6R/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-25 18:23:24,992 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f26c41a-56d7-4548-8d02-7cd563b233b6/bin/uautomizer-ZsLfNo2U6R/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Waiting until timeout for monitored process [2022-11-25 18:23:25,098 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2022-11-25 18:23:25,099 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-25 18:23:25,101 INFO L263 TraceCheckSpWp]: Trace formula consists of 131 conjuncts, 5 conjunts are in the unsatisfiable core [2022-11-25 18:23:25,103 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-25 18:23:25,159 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2022-11-25 18:23:25,159 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-25 18:23:25,159 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2042017812] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-25 18:23:25,159 INFO L184 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2022-11-25 18:23:25,159 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [9] total 11 [2022-11-25 18:23:25,160 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [743819123] [2022-11-25 18:23:25,160 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-25 18:23:25,160 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2022-11-25 18:23:25,160 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-25 18:23:25,160 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-11-25 18:23:25,161 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=24, Invalid=86, Unknown=0, NotChecked=0, Total=110 [2022-11-25 18:23:25,161 INFO L87 Difference]: Start difference. First operand 56 states and 63 transitions. Second operand has 4 states, 4 states have (on average 5.0) internal successors, (20), 4 states have internal predecessors, (20), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 18:23:25,177 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-25 18:23:25,177 INFO L93 Difference]: Finished difference Result 57 states and 64 transitions. [2022-11-25 18:23:25,177 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-11-25 18:23:25,178 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 5.0) internal successors, (20), 4 states have internal predecessors, (20), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 32 [2022-11-25 18:23:25,178 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-25 18:23:25,178 INFO L225 Difference]: With dead ends: 57 [2022-11-25 18:23:25,178 INFO L226 Difference]: Without dead ends: 57 [2022-11-25 18:23:25,179 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 46 GetRequests, 37 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 12 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=24, Invalid=86, Unknown=0, NotChecked=0, Total=110 [2022-11-25 18:23:25,179 INFO L413 NwaCegarLoop]: 42 mSDtfsCounter, 37 mSDsluCounter, 39 mSDsCounter, 0 mSdLazyCounter, 8 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 39 SdHoareTripleChecker+Valid, 81 SdHoareTripleChecker+Invalid, 8 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 8 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2022-11-25 18:23:25,179 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [39 Valid, 81 Invalid, 8 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 8 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2022-11-25 18:23:25,180 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 57 states. [2022-11-25 18:23:25,181 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 57 to 57. [2022-11-25 18:23:25,181 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 57 states, 51 states have (on average 1.1764705882352942) internal successors, (60), 55 states have internal predecessors, (60), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2022-11-25 18:23:25,182 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 57 states to 57 states and 64 transitions. [2022-11-25 18:23:25,182 INFO L78 Accepts]: Start accepts. Automaton has 57 states and 64 transitions. Word has length 32 [2022-11-25 18:23:25,182 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-25 18:23:25,182 INFO L495 AbstractCegarLoop]: Abstraction has 57 states and 64 transitions. [2022-11-25 18:23:25,182 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 5.0) internal successors, (20), 4 states have internal predecessors, (20), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 18:23:25,183 INFO L276 IsEmpty]: Start isEmpty. Operand 57 states and 64 transitions. [2022-11-25 18:23:25,183 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 34 [2022-11-25 18:23:25,183 INFO L187 NwaCegarLoop]: Found error trace [2022-11-25 18:23:25,183 INFO L195 NwaCegarLoop]: trace histogram [4, 4, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 18:23:25,204 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f26c41a-56d7-4548-8d02-7cd563b233b6/bin/uautomizer-ZsLfNo2U6R/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Forceful destruction successful, exit code 0 [2022-11-25 18:23:25,395 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 3 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f26c41a-56d7-4548-8d02-7cd563b233b6/bin/uautomizer-ZsLfNo2U6R/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable15 [2022-11-25 18:23:25,396 INFO L420 AbstractCegarLoop]: === Iteration 17 === Targeting ULTIMATE.startErr19REQUIRES_VIOLATIONMEMORY_DEREFERENCE === [ULTIMATE.startErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr2REQUIRES_VIOLATIONMEMORY_DEREFERENCE (and 22 more)] === [2022-11-25 18:23:25,396 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 18:23:25,396 INFO L85 PathProgramCache]: Analyzing trace with hash 1203352596, now seen corresponding path program 1 times [2022-11-25 18:23:25,396 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 18:23:25,396 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2009037060] [2022-11-25 18:23:25,396 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 18:23:25,397 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 18:23:25,414 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-25 18:23:25,854 INFO L134 CoverageAnalysis]: Checked inductivity of 25 backedges. 10 proven. 14 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-11-25 18:23:25,854 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-25 18:23:25,854 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2009037060] [2022-11-25 18:23:25,855 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2009037060] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-25 18:23:25,855 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1859082291] [2022-11-25 18:23:25,855 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 18:23:25,855 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-25 18:23:25,855 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f26c41a-56d7-4548-8d02-7cd563b233b6/bin/uautomizer-ZsLfNo2U6R/z3 [2022-11-25 18:23:25,856 INFO L229 MonitoredProcess]: Starting monitored process 4 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f26c41a-56d7-4548-8d02-7cd563b233b6/bin/uautomizer-ZsLfNo2U6R/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-25 18:23:25,874 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f26c41a-56d7-4548-8d02-7cd563b233b6/bin/uautomizer-ZsLfNo2U6R/z3 -smt2 -in SMTLIB2_COMPLIANT=true (4)] Waiting until timeout for monitored process [2022-11-25 18:23:25,957 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-25 18:23:25,959 INFO L263 TraceCheckSpWp]: Trace formula consists of 189 conjuncts, 33 conjunts are in the unsatisfiable core [2022-11-25 18:23:25,963 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-25 18:23:26,002 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 7 [2022-11-25 18:23:26,030 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-25 18:23:26,031 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 20 [2022-11-25 18:23:26,048 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-25 18:23:26,049 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 20 [2022-11-25 18:23:26,071 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-25 18:23:26,072 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 20 [2022-11-25 18:23:26,090 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-25 18:23:26,091 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 20 [2022-11-25 18:23:26,107 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-25 18:23:26,108 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 20 [2022-11-25 18:23:26,128 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-25 18:23:26,129 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 20 [2022-11-25 18:23:26,323 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2022-11-25 18:23:26,342 INFO L134 CoverageAnalysis]: Checked inductivity of 25 backedges. 21 proven. 3 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-11-25 18:23:26,342 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-25 18:23:26,451 INFO L134 CoverageAnalysis]: Checked inductivity of 25 backedges. 21 proven. 3 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-11-25 18:23:26,452 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1859082291] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-25 18:23:26,452 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-25 18:23:26,452 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9, 8] total 17 [2022-11-25 18:23:26,453 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2135538408] [2022-11-25 18:23:26,453 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-25 18:23:26,454 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 17 states [2022-11-25 18:23:26,454 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-25 18:23:26,454 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2022-11-25 18:23:26,455 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=59, Invalid=213, Unknown=0, NotChecked=0, Total=272 [2022-11-25 18:23:26,457 INFO L87 Difference]: Start difference. First operand 57 states and 64 transitions. Second operand has 17 states, 17 states have (on average 4.117647058823529) internal successors, (70), 17 states have internal predecessors, (70), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 18:23:26,861 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-25 18:23:26,861 INFO L93 Difference]: Finished difference Result 97 states and 111 transitions. [2022-11-25 18:23:26,861 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2022-11-25 18:23:26,862 INFO L78 Accepts]: Start accepts. Automaton has has 17 states, 17 states have (on average 4.117647058823529) internal successors, (70), 17 states have internal predecessors, (70), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 33 [2022-11-25 18:23:26,862 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-25 18:23:26,862 INFO L225 Difference]: With dead ends: 97 [2022-11-25 18:23:26,862 INFO L226 Difference]: Without dead ends: 97 [2022-11-25 18:23:26,863 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 88 GetRequests, 59 SyntacticMatches, 5 SemanticMatches, 24 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 136 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=170, Invalid=480, Unknown=0, NotChecked=0, Total=650 [2022-11-25 18:23:26,863 INFO L413 NwaCegarLoop]: 68 mSDtfsCounter, 125 mSDsluCounter, 333 mSDsCounter, 0 mSdLazyCounter, 300 mSolverCounterSat, 23 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 125 SdHoareTripleChecker+Valid, 401 SdHoareTripleChecker+Invalid, 323 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 23 IncrementalHoareTripleChecker+Valid, 300 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2022-11-25 18:23:26,864 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [125 Valid, 401 Invalid, 323 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [23 Valid, 300 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2022-11-25 18:23:26,864 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 97 states. [2022-11-25 18:23:26,866 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 97 to 55. [2022-11-25 18:23:26,866 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 55 states, 50 states have (on average 1.14) internal successors, (57), 53 states have internal predecessors, (57), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2022-11-25 18:23:26,866 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 55 states to 55 states and 61 transitions. [2022-11-25 18:23:26,867 INFO L78 Accepts]: Start accepts. Automaton has 55 states and 61 transitions. Word has length 33 [2022-11-25 18:23:26,867 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-25 18:23:26,867 INFO L495 AbstractCegarLoop]: Abstraction has 55 states and 61 transitions. [2022-11-25 18:23:26,867 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 17 states, 17 states have (on average 4.117647058823529) internal successors, (70), 17 states have internal predecessors, (70), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 18:23:26,867 INFO L276 IsEmpty]: Start isEmpty. Operand 55 states and 61 transitions. [2022-11-25 18:23:26,868 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 35 [2022-11-25 18:23:26,868 INFO L187 NwaCegarLoop]: Found error trace [2022-11-25 18:23:26,868 INFO L195 NwaCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 18:23:26,878 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f26c41a-56d7-4548-8d02-7cd563b233b6/bin/uautomizer-ZsLfNo2U6R/z3 -smt2 -in SMTLIB2_COMPLIANT=true (4)] Forceful destruction successful, exit code 0 [2022-11-25 18:23:27,073 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 4 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f26c41a-56d7-4548-8d02-7cd563b233b6/bin/uautomizer-ZsLfNo2U6R/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable16 [2022-11-25 18:23:27,074 INFO L420 AbstractCegarLoop]: === Iteration 18 === Targeting ULTIMATE.startErr23REQUIRES_VIOLATIONMEMORY_DEREFERENCE === [ULTIMATE.startErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr2REQUIRES_VIOLATIONMEMORY_DEREFERENCE (and 22 more)] === [2022-11-25 18:23:27,074 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 18:23:27,074 INFO L85 PathProgramCache]: Analyzing trace with hash -149943807, now seen corresponding path program 1 times [2022-11-25 18:23:27,075 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 18:23:27,075 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [180489571] [2022-11-25 18:23:27,075 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 18:23:27,075 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 18:23:27,094 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-25 18:23:27,541 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2022-11-25 18:23:27,541 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-25 18:23:27,541 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [180489571] [2022-11-25 18:23:27,541 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [180489571] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-25 18:23:27,541 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1830023104] [2022-11-25 18:23:27,541 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 18:23:27,542 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-25 18:23:27,542 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f26c41a-56d7-4548-8d02-7cd563b233b6/bin/uautomizer-ZsLfNo2U6R/z3 [2022-11-25 18:23:27,543 INFO L229 MonitoredProcess]: Starting monitored process 5 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f26c41a-56d7-4548-8d02-7cd563b233b6/bin/uautomizer-ZsLfNo2U6R/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-25 18:23:27,547 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f26c41a-56d7-4548-8d02-7cd563b233b6/bin/uautomizer-ZsLfNo2U6R/z3 -smt2 -in SMTLIB2_COMPLIANT=true (5)] Waiting until timeout for monitored process [2022-11-25 18:23:27,646 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-25 18:23:27,647 INFO L263 TraceCheckSpWp]: Trace formula consists of 197 conjuncts, 18 conjunts are in the unsatisfiable core [2022-11-25 18:23:27,649 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-25 18:23:27,900 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2022-11-25 18:23:27,900 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-25 18:23:28,180 INFO L321 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-11-25 18:23:28,181 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 13 treesize of output 17 [2022-11-25 18:23:28,228 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2022-11-25 18:23:28,229 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1830023104] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-25 18:23:28,229 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-25 18:23:28,229 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 6, 6] total 18 [2022-11-25 18:23:28,229 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1549414388] [2022-11-25 18:23:28,230 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-25 18:23:28,230 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 18 states [2022-11-25 18:23:28,230 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-25 18:23:28,231 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2022-11-25 18:23:28,231 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=51, Invalid=255, Unknown=0, NotChecked=0, Total=306 [2022-11-25 18:23:28,232 INFO L87 Difference]: Start difference. First operand 55 states and 61 transitions. Second operand has 18 states, 18 states have (on average 5.333333333333333) internal successors, (96), 18 states have internal predecessors, (96), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 18:23:28,667 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-25 18:23:28,668 INFO L93 Difference]: Finished difference Result 79 states and 88 transitions. [2022-11-25 18:23:28,668 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2022-11-25 18:23:28,668 INFO L78 Accepts]: Start accepts. Automaton has has 18 states, 18 states have (on average 5.333333333333333) internal successors, (96), 18 states have internal predecessors, (96), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 34 [2022-11-25 18:23:28,668 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-25 18:23:28,669 INFO L225 Difference]: With dead ends: 79 [2022-11-25 18:23:28,669 INFO L226 Difference]: Without dead ends: 79 [2022-11-25 18:23:28,670 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 91 GetRequests, 65 SyntacticMatches, 0 SemanticMatches, 26 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 95 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=168, Invalid=588, Unknown=0, NotChecked=0, Total=756 [2022-11-25 18:23:28,670 INFO L413 NwaCegarLoop]: 23 mSDtfsCounter, 192 mSDsluCounter, 103 mSDsCounter, 0 mSdLazyCounter, 217 mSolverCounterSat, 17 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 192 SdHoareTripleChecker+Valid, 126 SdHoareTripleChecker+Invalid, 234 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 17 IncrementalHoareTripleChecker+Valid, 217 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2022-11-25 18:23:28,671 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [192 Valid, 126 Invalid, 234 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [17 Valid, 217 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2022-11-25 18:23:28,671 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 79 states. [2022-11-25 18:23:28,673 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 79 to 65. [2022-11-25 18:23:28,673 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 65 states, 60 states have (on average 1.1333333333333333) internal successors, (68), 63 states have internal predecessors, (68), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2022-11-25 18:23:28,674 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 65 states to 65 states and 72 transitions. [2022-11-25 18:23:28,674 INFO L78 Accepts]: Start accepts. Automaton has 65 states and 72 transitions. Word has length 34 [2022-11-25 18:23:28,674 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-25 18:23:28,674 INFO L495 AbstractCegarLoop]: Abstraction has 65 states and 72 transitions. [2022-11-25 18:23:28,674 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 18 states, 18 states have (on average 5.333333333333333) internal successors, (96), 18 states have internal predecessors, (96), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 18:23:28,675 INFO L276 IsEmpty]: Start isEmpty. Operand 65 states and 72 transitions. [2022-11-25 18:23:28,675 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 44 [2022-11-25 18:23:28,675 INFO L187 NwaCegarLoop]: Found error trace [2022-11-25 18:23:28,675 INFO L195 NwaCegarLoop]: trace histogram [3, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 18:23:28,686 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f26c41a-56d7-4548-8d02-7cd563b233b6/bin/uautomizer-ZsLfNo2U6R/z3 -smt2 -in SMTLIB2_COMPLIANT=true (5)] Forceful destruction successful, exit code 0 [2022-11-25 18:23:28,881 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 5 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f26c41a-56d7-4548-8d02-7cd563b233b6/bin/uautomizer-ZsLfNo2U6R/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable17 [2022-11-25 18:23:28,881 INFO L420 AbstractCegarLoop]: === Iteration 19 === Targeting ULTIMATE.startErr24ASSERT_VIOLATIONMEMORY_LEAK === [ULTIMATE.startErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr2REQUIRES_VIOLATIONMEMORY_DEREFERENCE (and 22 more)] === [2022-11-25 18:23:28,882 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 18:23:28,882 INFO L85 PathProgramCache]: Analyzing trace with hash 1336889422, now seen corresponding path program 1 times [2022-11-25 18:23:28,882 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 18:23:28,882 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2050304930] [2022-11-25 18:23:28,882 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 18:23:28,882 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 18:23:28,903 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-25 18:23:29,359 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 9 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2022-11-25 18:23:29,360 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-25 18:23:29,360 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2050304930] [2022-11-25 18:23:29,360 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2050304930] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-25 18:23:29,360 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [260406371] [2022-11-25 18:23:29,361 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 18:23:29,361 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-25 18:23:29,361 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f26c41a-56d7-4548-8d02-7cd563b233b6/bin/uautomizer-ZsLfNo2U6R/z3 [2022-11-25 18:23:29,362 INFO L229 MonitoredProcess]: Starting monitored process 6 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f26c41a-56d7-4548-8d02-7cd563b233b6/bin/uautomizer-ZsLfNo2U6R/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-25 18:23:29,395 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f26c41a-56d7-4548-8d02-7cd563b233b6/bin/uautomizer-ZsLfNo2U6R/z3 -smt2 -in SMTLIB2_COMPLIANT=true (6)] Waiting until timeout for monitored process [2022-11-25 18:23:29,481 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-25 18:23:29,483 INFO L263 TraceCheckSpWp]: Trace formula consists of 228 conjuncts, 29 conjunts are in the unsatisfiable core [2022-11-25 18:23:29,486 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-25 18:23:29,516 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2022-11-25 18:23:29,756 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2022-11-25 18:23:29,775 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 1 proven. 10 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-11-25 18:23:29,776 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-25 18:23:29,968 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 8 proven. 3 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-11-25 18:23:29,969 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [260406371] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-25 18:23:29,969 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-25 18:23:29,969 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 10, 9] total 24 [2022-11-25 18:23:29,969 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1157057645] [2022-11-25 18:23:29,970 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-25 18:23:29,970 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 24 states [2022-11-25 18:23:29,970 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-25 18:23:29,971 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2022-11-25 18:23:29,971 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=83, Invalid=469, Unknown=0, NotChecked=0, Total=552 [2022-11-25 18:23:29,972 INFO L87 Difference]: Start difference. First operand 65 states and 72 transitions. Second operand has 24 states, 24 states have (on average 4.583333333333333) internal successors, (110), 24 states have internal predecessors, (110), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 18:23:30,637 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-25 18:23:30,637 INFO L93 Difference]: Finished difference Result 65 states and 70 transitions. [2022-11-25 18:23:30,638 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2022-11-25 18:23:30,638 INFO L78 Accepts]: Start accepts. Automaton has has 24 states, 24 states have (on average 4.583333333333333) internal successors, (110), 24 states have internal predecessors, (110), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 43 [2022-11-25 18:23:30,638 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-25 18:23:30,639 INFO L225 Difference]: With dead ends: 65 [2022-11-25 18:23:30,639 INFO L226 Difference]: Without dead ends: 65 [2022-11-25 18:23:30,640 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 112 GetRequests, 77 SyntacticMatches, 0 SemanticMatches, 35 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 236 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=293, Invalid=1039, Unknown=0, NotChecked=0, Total=1332 [2022-11-25 18:23:30,640 INFO L413 NwaCegarLoop]: 27 mSDtfsCounter, 144 mSDsluCounter, 192 mSDsCounter, 0 mSdLazyCounter, 266 mSolverCounterSat, 16 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 144 SdHoareTripleChecker+Valid, 219 SdHoareTripleChecker+Invalid, 282 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 16 IncrementalHoareTripleChecker+Valid, 266 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2022-11-25 18:23:30,640 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [144 Valid, 219 Invalid, 282 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [16 Valid, 266 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2022-11-25 18:23:30,641 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 65 states. [2022-11-25 18:23:30,642 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 65 to 65. [2022-11-25 18:23:30,642 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 65 states, 60 states have (on average 1.1) internal successors, (66), 63 states have internal predecessors, (66), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2022-11-25 18:23:30,642 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 65 states to 65 states and 70 transitions. [2022-11-25 18:23:30,643 INFO L78 Accepts]: Start accepts. Automaton has 65 states and 70 transitions. Word has length 43 [2022-11-25 18:23:30,643 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-25 18:23:30,643 INFO L495 AbstractCegarLoop]: Abstraction has 65 states and 70 transitions. [2022-11-25 18:23:30,643 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 24 states, 24 states have (on average 4.583333333333333) internal successors, (110), 24 states have internal predecessors, (110), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 18:23:30,643 INFO L276 IsEmpty]: Start isEmpty. Operand 65 states and 70 transitions. [2022-11-25 18:23:30,643 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 54 [2022-11-25 18:23:30,643 INFO L187 NwaCegarLoop]: Found error trace [2022-11-25 18:23:30,644 INFO L195 NwaCegarLoop]: trace histogram [4, 3, 3, 3, 3, 3, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 18:23:30,650 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f26c41a-56d7-4548-8d02-7cd563b233b6/bin/uautomizer-ZsLfNo2U6R/z3 -smt2 -in SMTLIB2_COMPLIANT=true (6)] Forceful destruction successful, exit code 0 [2022-11-25 18:23:30,849 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable18,6 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f26c41a-56d7-4548-8d02-7cd563b233b6/bin/uautomizer-ZsLfNo2U6R/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-25 18:23:30,850 INFO L420 AbstractCegarLoop]: === Iteration 20 === Targeting ULTIMATE.startErr24ASSERT_VIOLATIONMEMORY_LEAK === [ULTIMATE.startErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr2REQUIRES_VIOLATIONMEMORY_DEREFERENCE (and 22 more)] === [2022-11-25 18:23:30,850 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 18:23:30,850 INFO L85 PathProgramCache]: Analyzing trace with hash -990509317, now seen corresponding path program 2 times [2022-11-25 18:23:30,850 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 18:23:30,850 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [248009628] [2022-11-25 18:23:30,851 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 18:23:30,851 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 18:23:30,873 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-25 18:23:31,459 INFO L134 CoverageAnalysis]: Checked inductivity of 31 backedges. 0 proven. 17 refuted. 0 times theorem prover too weak. 14 trivial. 0 not checked. [2022-11-25 18:23:31,459 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-25 18:23:31,459 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [248009628] [2022-11-25 18:23:31,460 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [248009628] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-25 18:23:31,460 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1297594700] [2022-11-25 18:23:31,460 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-11-25 18:23:31,460 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-25 18:23:31,460 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f26c41a-56d7-4548-8d02-7cd563b233b6/bin/uautomizer-ZsLfNo2U6R/z3 [2022-11-25 18:23:31,461 INFO L229 MonitoredProcess]: Starting monitored process 7 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f26c41a-56d7-4548-8d02-7cd563b233b6/bin/uautomizer-ZsLfNo2U6R/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-25 18:23:31,489 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f26c41a-56d7-4548-8d02-7cd563b233b6/bin/uautomizer-ZsLfNo2U6R/z3 -smt2 -in SMTLIB2_COMPLIANT=true (7)] Waiting until timeout for monitored process [2022-11-25 18:23:31,624 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-11-25 18:23:31,624 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-25 18:23:31,627 INFO L263 TraceCheckSpWp]: Trace formula consists of 262 conjuncts, 31 conjunts are in the unsatisfiable core [2022-11-25 18:23:31,630 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-25 18:23:31,667 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2022-11-25 18:23:32,093 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2022-11-25 18:23:32,118 INFO L134 CoverageAnalysis]: Checked inductivity of 31 backedges. 7 proven. 23 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-11-25 18:23:32,118 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-25 18:23:32,361 INFO L134 CoverageAnalysis]: Checked inductivity of 31 backedges. 19 proven. 11 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-11-25 18:23:32,362 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1297594700] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-25 18:23:32,362 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-25 18:23:32,362 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 12, 11] total 27 [2022-11-25 18:23:32,362 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [888355487] [2022-11-25 18:23:32,362 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-25 18:23:32,363 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 27 states [2022-11-25 18:23:32,363 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-25 18:23:32,364 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 27 interpolants. [2022-11-25 18:23:32,364 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=125, Invalid=577, Unknown=0, NotChecked=0, Total=702 [2022-11-25 18:23:32,364 INFO L87 Difference]: Start difference. First operand 65 states and 70 transitions. Second operand has 27 states, 27 states have (on average 4.518518518518518) internal successors, (122), 27 states have internal predecessors, (122), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 18:23:33,050 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-25 18:23:33,051 INFO L93 Difference]: Finished difference Result 67 states and 71 transitions. [2022-11-25 18:23:33,051 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2022-11-25 18:23:33,052 INFO L78 Accepts]: Start accepts. Automaton has has 27 states, 27 states have (on average 4.518518518518518) internal successors, (122), 27 states have internal predecessors, (122), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 53 [2022-11-25 18:23:33,052 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-25 18:23:33,052 INFO L225 Difference]: With dead ends: 67 [2022-11-25 18:23:33,052 INFO L226 Difference]: Without dead ends: 67 [2022-11-25 18:23:33,053 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 136 GetRequests, 93 SyntacticMatches, 4 SemanticMatches, 39 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 432 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=421, Invalid=1219, Unknown=0, NotChecked=0, Total=1640 [2022-11-25 18:23:33,054 INFO L413 NwaCegarLoop]: 28 mSDtfsCounter, 173 mSDsluCounter, 154 mSDsCounter, 0 mSdLazyCounter, 269 mSolverCounterSat, 20 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 173 SdHoareTripleChecker+Valid, 182 SdHoareTripleChecker+Invalid, 289 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 20 IncrementalHoareTripleChecker+Valid, 269 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2022-11-25 18:23:33,054 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [173 Valid, 182 Invalid, 289 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [20 Valid, 269 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2022-11-25 18:23:33,054 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 67 states. [2022-11-25 18:23:33,056 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 67 to 65. [2022-11-25 18:23:33,056 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 65 states, 60 states have (on average 1.0833333333333333) internal successors, (65), 63 states have internal predecessors, (65), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2022-11-25 18:23:33,056 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 65 states to 65 states and 69 transitions. [2022-11-25 18:23:33,057 INFO L78 Accepts]: Start accepts. Automaton has 65 states and 69 transitions. Word has length 53 [2022-11-25 18:23:33,057 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-25 18:23:33,057 INFO L495 AbstractCegarLoop]: Abstraction has 65 states and 69 transitions. [2022-11-25 18:23:33,057 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 27 states, 27 states have (on average 4.518518518518518) internal successors, (122), 27 states have internal predecessors, (122), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 18:23:33,057 INFO L276 IsEmpty]: Start isEmpty. Operand 65 states and 69 transitions. [2022-11-25 18:23:33,057 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 55 [2022-11-25 18:23:33,058 INFO L187 NwaCegarLoop]: Found error trace [2022-11-25 18:23:33,058 INFO L195 NwaCegarLoop]: trace histogram [4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 18:23:33,070 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f26c41a-56d7-4548-8d02-7cd563b233b6/bin/uautomizer-ZsLfNo2U6R/z3 -smt2 -in SMTLIB2_COMPLIANT=true (7)] Forceful destruction successful, exit code 0 [2022-11-25 18:23:33,265 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable19,7 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f26c41a-56d7-4548-8d02-7cd563b233b6/bin/uautomizer-ZsLfNo2U6R/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-25 18:23:33,265 INFO L420 AbstractCegarLoop]: === Iteration 21 === Targeting ULTIMATE.startErr23REQUIRES_VIOLATIONMEMORY_DEREFERENCE === [ULTIMATE.startErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr2REQUIRES_VIOLATIONMEMORY_DEREFERENCE (and 22 more)] === [2022-11-25 18:23:33,266 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 18:23:33,266 INFO L85 PathProgramCache]: Analyzing trace with hash 868555041, now seen corresponding path program 2 times [2022-11-25 18:23:33,266 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 18:23:33,266 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [119954694] [2022-11-25 18:23:33,266 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 18:23:33,266 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 18:23:33,324 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-25 18:23:33,792 INFO L134 CoverageAnalysis]: Checked inductivity of 46 backedges. 10 proven. 35 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-11-25 18:23:33,792 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-25 18:23:33,792 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [119954694] [2022-11-25 18:23:33,792 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [119954694] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-25 18:23:33,793 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1952465299] [2022-11-25 18:23:33,793 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-11-25 18:23:33,793 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-25 18:23:33,793 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f26c41a-56d7-4548-8d02-7cd563b233b6/bin/uautomizer-ZsLfNo2U6R/z3 [2022-11-25 18:23:33,794 INFO L229 MonitoredProcess]: Starting monitored process 8 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f26c41a-56d7-4548-8d02-7cd563b233b6/bin/uautomizer-ZsLfNo2U6R/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-25 18:23:33,822 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f26c41a-56d7-4548-8d02-7cd563b233b6/bin/uautomizer-ZsLfNo2U6R/z3 -smt2 -in SMTLIB2_COMPLIANT=true (8)] Waiting until timeout for monitored process [2022-11-25 18:23:33,950 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-11-25 18:23:33,950 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-25 18:23:33,952 INFO L263 TraceCheckSpWp]: Trace formula consists of 265 conjuncts, 31 conjunts are in the unsatisfiable core [2022-11-25 18:23:33,956 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-25 18:23:33,991 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 7 [2022-11-25 18:23:34,026 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-25 18:23:34,027 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 20 [2022-11-25 18:23:34,038 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-25 18:23:34,039 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 20 [2022-11-25 18:23:34,051 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-25 18:23:34,052 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 20 [2022-11-25 18:23:34,064 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-25 18:23:34,065 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 20 [2022-11-25 18:23:34,074 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-25 18:23:34,075 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 20 [2022-11-25 18:23:34,094 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-25 18:23:34,099 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 20 [2022-11-25 18:23:34,366 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2022-11-25 18:23:34,388 INFO L134 CoverageAnalysis]: Checked inductivity of 46 backedges. 21 proven. 3 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2022-11-25 18:23:34,388 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-25 18:23:34,571 INFO L134 CoverageAnalysis]: Checked inductivity of 46 backedges. 21 proven. 3 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2022-11-25 18:23:34,572 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1952465299] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-25 18:23:34,572 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-25 18:23:34,572 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 9, 8] total 23 [2022-11-25 18:23:34,572 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [782141037] [2022-11-25 18:23:34,573 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-25 18:23:34,573 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 23 states [2022-11-25 18:23:34,573 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-25 18:23:34,574 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 23 interpolants. [2022-11-25 18:23:34,574 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=82, Invalid=424, Unknown=0, NotChecked=0, Total=506 [2022-11-25 18:23:34,575 INFO L87 Difference]: Start difference. First operand 65 states and 69 transitions. Second operand has 23 states, 23 states have (on average 5.0) internal successors, (115), 23 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 18:23:35,198 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-25 18:23:35,198 INFO L93 Difference]: Finished difference Result 63 states and 66 transitions. [2022-11-25 18:23:35,199 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2022-11-25 18:23:35,199 INFO L78 Accepts]: Start accepts. Automaton has has 23 states, 23 states have (on average 5.0) internal successors, (115), 23 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 54 [2022-11-25 18:23:35,199 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-25 18:23:35,200 INFO L225 Difference]: With dead ends: 63 [2022-11-25 18:23:35,200 INFO L226 Difference]: Without dead ends: 63 [2022-11-25 18:23:35,200 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 137 GetRequests, 96 SyntacticMatches, 5 SemanticMatches, 36 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 368 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=266, Invalid=1140, Unknown=0, NotChecked=0, Total=1406 [2022-11-25 18:23:35,201 INFO L413 NwaCegarLoop]: 26 mSDtfsCounter, 96 mSDsluCounter, 232 mSDsCounter, 0 mSdLazyCounter, 370 mSolverCounterSat, 12 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 96 SdHoareTripleChecker+Valid, 258 SdHoareTripleChecker+Invalid, 382 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 12 IncrementalHoareTripleChecker+Valid, 370 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.3s IncrementalHoareTripleChecker+Time [2022-11-25 18:23:35,201 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [96 Valid, 258 Invalid, 382 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [12 Valid, 370 Invalid, 0 Unknown, 0 Unchecked, 0.3s Time] [2022-11-25 18:23:35,202 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 63 states. [2022-11-25 18:23:35,203 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 63 to 63. [2022-11-25 18:23:35,203 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 63 states, 59 states have (on average 1.0508474576271187) internal successors, (62), 61 states have internal predecessors, (62), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2022-11-25 18:23:35,204 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 63 states to 63 states and 66 transitions. [2022-11-25 18:23:35,204 INFO L78 Accepts]: Start accepts. Automaton has 63 states and 66 transitions. Word has length 54 [2022-11-25 18:23:35,204 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-25 18:23:35,204 INFO L495 AbstractCegarLoop]: Abstraction has 63 states and 66 transitions. [2022-11-25 18:23:35,204 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 23 states, 23 states have (on average 5.0) internal successors, (115), 23 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 18:23:35,204 INFO L276 IsEmpty]: Start isEmpty. Operand 63 states and 66 transitions. [2022-11-25 18:23:35,205 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 59 [2022-11-25 18:23:35,205 INFO L187 NwaCegarLoop]: Found error trace [2022-11-25 18:23:35,205 INFO L195 NwaCegarLoop]: trace histogram [4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 18:23:35,219 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f26c41a-56d7-4548-8d02-7cd563b233b6/bin/uautomizer-ZsLfNo2U6R/z3 -smt2 -in SMTLIB2_COMPLIANT=true (8)] Forceful destruction successful, exit code 0 [2022-11-25 18:23:35,413 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable20,8 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f26c41a-56d7-4548-8d02-7cd563b233b6/bin/uautomizer-ZsLfNo2U6R/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-25 18:23:35,414 INFO L420 AbstractCegarLoop]: === Iteration 22 === Targeting ULTIMATE.startErr24ASSERT_VIOLATIONMEMORY_LEAK === [ULTIMATE.startErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr2REQUIRES_VIOLATIONMEMORY_DEREFERENCE (and 22 more)] === [2022-11-25 18:23:35,414 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 18:23:35,415 INFO L85 PathProgramCache]: Analyzing trace with hash 679832114, now seen corresponding path program 3 times [2022-11-25 18:23:35,415 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 18:23:35,415 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [193044368] [2022-11-25 18:23:35,415 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 18:23:35,415 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 18:23:35,463 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-25 18:23:35,591 INFO L134 CoverageAnalysis]: Checked inductivity of 43 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 42 trivial. 0 not checked. [2022-11-25 18:23:35,591 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-25 18:23:35,592 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [193044368] [2022-11-25 18:23:35,592 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [193044368] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-25 18:23:35,592 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [12706376] [2022-11-25 18:23:35,592 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2022-11-25 18:23:35,592 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-25 18:23:35,592 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f26c41a-56d7-4548-8d02-7cd563b233b6/bin/uautomizer-ZsLfNo2U6R/z3 [2022-11-25 18:23:35,594 INFO L229 MonitoredProcess]: Starting monitored process 9 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f26c41a-56d7-4548-8d02-7cd563b233b6/bin/uautomizer-ZsLfNo2U6R/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-25 18:23:35,616 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f26c41a-56d7-4548-8d02-7cd563b233b6/bin/uautomizer-ZsLfNo2U6R/z3 -smt2 -in SMTLIB2_COMPLIANT=true (9)] Waiting until timeout for monitored process [2022-11-25 18:23:35,955 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 2 check-sat command(s) [2022-11-25 18:23:35,955 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-25 18:23:35,956 INFO L263 TraceCheckSpWp]: Trace formula consists of 211 conjuncts, 8 conjunts are in the unsatisfiable core [2022-11-25 18:23:35,958 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-25 18:23:36,002 INFO L134 CoverageAnalysis]: Checked inductivity of 43 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 42 trivial. 0 not checked. [2022-11-25 18:23:36,003 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-25 18:23:36,062 INFO L134 CoverageAnalysis]: Checked inductivity of 43 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 42 trivial. 0 not checked. [2022-11-25 18:23:36,062 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [12706376] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-25 18:23:36,063 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-25 18:23:36,063 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 5, 5] total 9 [2022-11-25 18:23:36,063 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1407370830] [2022-11-25 18:23:36,063 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-25 18:23:36,064 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 9 states [2022-11-25 18:23:36,064 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-25 18:23:36,064 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2022-11-25 18:23:36,065 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=29, Invalid=43, Unknown=0, NotChecked=0, Total=72 [2022-11-25 18:23:36,065 INFO L87 Difference]: Start difference. First operand 63 states and 66 transitions. Second operand has 9 states, 9 states have (on average 4.777777777777778) internal successors, (43), 9 states have internal predecessors, (43), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 18:23:36,171 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-25 18:23:36,171 INFO L93 Difference]: Finished difference Result 66 states and 69 transitions. [2022-11-25 18:23:36,172 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2022-11-25 18:23:36,172 INFO L78 Accepts]: Start accepts. Automaton has has 9 states, 9 states have (on average 4.777777777777778) internal successors, (43), 9 states have internal predecessors, (43), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 58 [2022-11-25 18:23:36,172 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-25 18:23:36,173 INFO L225 Difference]: With dead ends: 66 [2022-11-25 18:23:36,173 INFO L226 Difference]: Without dead ends: 66 [2022-11-25 18:23:36,173 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 122 GetRequests, 111 SyntacticMatches, 1 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 19 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=53, Invalid=79, Unknown=0, NotChecked=0, Total=132 [2022-11-25 18:23:36,174 INFO L413 NwaCegarLoop]: 40 mSDtfsCounter, 69 mSDsluCounter, 50 mSDsCounter, 0 mSdLazyCounter, 14 mSolverCounterSat, 6 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 69 SdHoareTripleChecker+Valid, 90 SdHoareTripleChecker+Invalid, 20 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 6 IncrementalHoareTripleChecker+Valid, 14 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2022-11-25 18:23:36,174 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [69 Valid, 90 Invalid, 20 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [6 Valid, 14 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2022-11-25 18:23:36,174 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 66 states. [2022-11-25 18:23:36,175 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 66 to 66. [2022-11-25 18:23:36,176 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 66 states, 62 states have (on average 1.0483870967741935) internal successors, (65), 64 states have internal predecessors, (65), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2022-11-25 18:23:36,176 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 66 states to 66 states and 69 transitions. [2022-11-25 18:23:36,176 INFO L78 Accepts]: Start accepts. Automaton has 66 states and 69 transitions. Word has length 58 [2022-11-25 18:23:36,176 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-25 18:23:36,176 INFO L495 AbstractCegarLoop]: Abstraction has 66 states and 69 transitions. [2022-11-25 18:23:36,177 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 9 states, 9 states have (on average 4.777777777777778) internal successors, (43), 9 states have internal predecessors, (43), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 18:23:36,177 INFO L276 IsEmpty]: Start isEmpty. Operand 66 states and 69 transitions. [2022-11-25 18:23:36,177 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 62 [2022-11-25 18:23:36,177 INFO L187 NwaCegarLoop]: Found error trace [2022-11-25 18:23:36,177 INFO L195 NwaCegarLoop]: trace histogram [4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 18:23:36,189 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f26c41a-56d7-4548-8d02-7cd563b233b6/bin/uautomizer-ZsLfNo2U6R/z3 -smt2 -in SMTLIB2_COMPLIANT=true (9)] Forceful destruction successful, exit code 0 [2022-11-25 18:23:36,384 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 9 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f26c41a-56d7-4548-8d02-7cd563b233b6/bin/uautomizer-ZsLfNo2U6R/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable21 [2022-11-25 18:23:36,384 INFO L420 AbstractCegarLoop]: === Iteration 23 === Targeting ULTIMATE.startErr24ASSERT_VIOLATIONMEMORY_LEAK === [ULTIMATE.startErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr2REQUIRES_VIOLATIONMEMORY_DEREFERENCE (and 22 more)] === [2022-11-25 18:23:36,384 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 18:23:36,384 INFO L85 PathProgramCache]: Analyzing trace with hash -220059533, now seen corresponding path program 4 times [2022-11-25 18:23:36,385 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 18:23:36,385 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2038821488] [2022-11-25 18:23:36,385 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 18:23:36,385 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 18:23:36,417 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-25 18:23:36,650 INFO L134 CoverageAnalysis]: Checked inductivity of 52 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 42 trivial. 0 not checked. [2022-11-25 18:23:36,651 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-25 18:23:36,651 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2038821488] [2022-11-25 18:23:36,651 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2038821488] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-25 18:23:36,652 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1970701760] [2022-11-25 18:23:36,652 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2022-11-25 18:23:36,652 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-25 18:23:36,652 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f26c41a-56d7-4548-8d02-7cd563b233b6/bin/uautomizer-ZsLfNo2U6R/z3 [2022-11-25 18:23:36,655 INFO L229 MonitoredProcess]: Starting monitored process 10 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f26c41a-56d7-4548-8d02-7cd563b233b6/bin/uautomizer-ZsLfNo2U6R/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-25 18:23:36,678 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f26c41a-56d7-4548-8d02-7cd563b233b6/bin/uautomizer-ZsLfNo2U6R/z3 -smt2 -in SMTLIB2_COMPLIANT=true (10)] Waiting until timeout for monitored process [2022-11-25 18:23:37,092 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2022-11-25 18:23:37,092 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-25 18:23:37,094 INFO L263 TraceCheckSpWp]: Trace formula consists of 300 conjuncts, 13 conjunts are in the unsatisfiable core [2022-11-25 18:23:37,095 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-25 18:23:37,197 INFO L134 CoverageAnalysis]: Checked inductivity of 52 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 42 trivial. 0 not checked. [2022-11-25 18:23:37,197 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-25 18:23:37,322 INFO L134 CoverageAnalysis]: Checked inductivity of 52 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 42 trivial. 0 not checked. [2022-11-25 18:23:37,322 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1970701760] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-25 18:23:37,322 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-25 18:23:37,322 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 8, 8] total 18 [2022-11-25 18:23:37,322 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [22705413] [2022-11-25 18:23:37,322 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-25 18:23:37,323 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 18 states [2022-11-25 18:23:37,323 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-25 18:23:37,323 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2022-11-25 18:23:37,323 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=104, Invalid=202, Unknown=0, NotChecked=0, Total=306 [2022-11-25 18:23:37,324 INFO L87 Difference]: Start difference. First operand 66 states and 69 transitions. Second operand has 18 states, 18 states have (on average 2.888888888888889) internal successors, (52), 18 states have internal predecessors, (52), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 18:23:37,850 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-25 18:23:37,850 INFO L93 Difference]: Finished difference Result 72 states and 75 transitions. [2022-11-25 18:23:37,850 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2022-11-25 18:23:37,850 INFO L78 Accepts]: Start accepts. Automaton has has 18 states, 18 states have (on average 2.888888888888889) internal successors, (52), 18 states have internal predecessors, (52), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 61 [2022-11-25 18:23:37,851 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-25 18:23:37,851 INFO L225 Difference]: With dead ends: 72 [2022-11-25 18:23:37,851 INFO L226 Difference]: Without dead ends: 72 [2022-11-25 18:23:37,852 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 133 GetRequests, 111 SyntacticMatches, 1 SemanticMatches, 21 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 103 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=174, Invalid=332, Unknown=0, NotChecked=0, Total=506 [2022-11-25 18:23:37,852 INFO L413 NwaCegarLoop]: 40 mSDtfsCounter, 40 mSDsluCounter, 230 mSDsCounter, 0 mSdLazyCounter, 69 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 42 SdHoareTripleChecker+Valid, 270 SdHoareTripleChecker+Invalid, 70 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 69 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-11-25 18:23:37,852 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [42 Valid, 270 Invalid, 70 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 69 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2022-11-25 18:23:37,853 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 72 states. [2022-11-25 18:23:37,854 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 72 to 72. [2022-11-25 18:23:37,854 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 72 states, 68 states have (on average 1.0441176470588236) internal successors, (71), 70 states have internal predecessors, (71), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2022-11-25 18:23:37,855 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 72 states to 72 states and 75 transitions. [2022-11-25 18:23:37,855 INFO L78 Accepts]: Start accepts. Automaton has 72 states and 75 transitions. Word has length 61 [2022-11-25 18:23:37,855 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-25 18:23:37,855 INFO L495 AbstractCegarLoop]: Abstraction has 72 states and 75 transitions. [2022-11-25 18:23:37,855 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 18 states, 18 states have (on average 2.888888888888889) internal successors, (52), 18 states have internal predecessors, (52), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 18:23:37,856 INFO L276 IsEmpty]: Start isEmpty. Operand 72 states and 75 transitions. [2022-11-25 18:23:37,856 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2022-11-25 18:23:37,856 INFO L187 NwaCegarLoop]: Found error trace [2022-11-25 18:23:37,856 INFO L195 NwaCegarLoop]: trace histogram [10, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 18:23:37,867 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f26c41a-56d7-4548-8d02-7cd563b233b6/bin/uautomizer-ZsLfNo2U6R/z3 -smt2 -in SMTLIB2_COMPLIANT=true (10)] Forceful destruction successful, exit code 0 [2022-11-25 18:23:38,057 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable22,10 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f26c41a-56d7-4548-8d02-7cd563b233b6/bin/uautomizer-ZsLfNo2U6R/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-25 18:23:38,057 INFO L420 AbstractCegarLoop]: === Iteration 24 === Targeting ULTIMATE.startErr24ASSERT_VIOLATIONMEMORY_LEAK === [ULTIMATE.startErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr2REQUIRES_VIOLATIONMEMORY_DEREFERENCE (and 22 more)] === [2022-11-25 18:23:38,057 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 18:23:38,058 INFO L85 PathProgramCache]: Analyzing trace with hash -179470317, now seen corresponding path program 5 times [2022-11-25 18:23:38,058 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 18:23:38,058 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1374674990] [2022-11-25 18:23:38,058 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 18:23:38,058 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 18:23:38,105 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-25 18:23:38,530 INFO L134 CoverageAnalysis]: Checked inductivity of 97 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 42 trivial. 0 not checked. [2022-11-25 18:23:38,530 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-25 18:23:38,530 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1374674990] [2022-11-25 18:23:38,530 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1374674990] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-25 18:23:38,530 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [947020634] [2022-11-25 18:23:38,530 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2022-11-25 18:23:38,531 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-25 18:23:38,531 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f26c41a-56d7-4548-8d02-7cd563b233b6/bin/uautomizer-ZsLfNo2U6R/z3 [2022-11-25 18:23:38,532 INFO L229 MonitoredProcess]: Starting monitored process 11 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f26c41a-56d7-4548-8d02-7cd563b233b6/bin/uautomizer-ZsLfNo2U6R/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-25 18:23:38,558 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f26c41a-56d7-4548-8d02-7cd563b233b6/bin/uautomizer-ZsLfNo2U6R/z3 -smt2 -in SMTLIB2_COMPLIANT=true (11)] Waiting until timeout for monitored process [2022-11-25 18:23:39,650 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 6 check-sat command(s) [2022-11-25 18:23:39,650 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-25 18:23:39,655 INFO L263 TraceCheckSpWp]: Trace formula consists of 342 conjuncts, 25 conjunts are in the unsatisfiable core [2022-11-25 18:23:39,657 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-25 18:23:40,005 INFO L134 CoverageAnalysis]: Checked inductivity of 97 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 42 trivial. 0 not checked. [2022-11-25 18:23:40,005 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-25 18:23:40,495 INFO L134 CoverageAnalysis]: Checked inductivity of 97 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 42 trivial. 0 not checked. [2022-11-25 18:23:40,497 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [947020634] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-25 18:23:40,497 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-25 18:23:40,497 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 14, 14] total 36 [2022-11-25 18:23:40,497 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2049745215] [2022-11-25 18:23:40,497 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-25 18:23:40,498 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 36 states [2022-11-25 18:23:40,498 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-25 18:23:40,499 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 36 interpolants. [2022-11-25 18:23:40,499 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=362, Invalid=898, Unknown=0, NotChecked=0, Total=1260 [2022-11-25 18:23:40,500 INFO L87 Difference]: Start difference. First operand 72 states and 75 transitions. Second operand has 36 states, 36 states have (on average 1.9444444444444444) internal successors, (70), 36 states have internal predecessors, (70), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 18:23:46,541 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-25 18:23:46,541 INFO L93 Difference]: Finished difference Result 84 states and 87 transitions. [2022-11-25 18:23:46,542 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2022-11-25 18:23:46,542 INFO L78 Accepts]: Start accepts. Automaton has has 36 states, 36 states have (on average 1.9444444444444444) internal successors, (70), 36 states have internal predecessors, (70), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 67 [2022-11-25 18:23:46,542 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-25 18:23:46,543 INFO L225 Difference]: With dead ends: 84 [2022-11-25 18:23:46,543 INFO L226 Difference]: Without dead ends: 84 [2022-11-25 18:23:46,544 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 157 GetRequests, 111 SyntacticMatches, 1 SemanticMatches, 45 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 493 ImplicationChecksByTransitivity, 6.6s TimeCoverageRelationStatistics Valid=648, Invalid=1514, Unknown=0, NotChecked=0, Total=2162 [2022-11-25 18:23:46,545 INFO L413 NwaCegarLoop]: 40 mSDtfsCounter, 46 mSDsluCounter, 415 mSDsCounter, 0 mSdLazyCounter, 253 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 48 SdHoareTripleChecker+Valid, 455 SdHoareTripleChecker+Invalid, 254 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 253 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2022-11-25 18:23:46,545 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [48 Valid, 455 Invalid, 254 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 253 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2022-11-25 18:23:46,546 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 84 states. [2022-11-25 18:23:46,547 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 84 to 84. [2022-11-25 18:23:46,547 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 84 states, 80 states have (on average 1.0375) internal successors, (83), 82 states have internal predecessors, (83), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2022-11-25 18:23:46,548 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 84 states to 84 states and 87 transitions. [2022-11-25 18:23:46,548 INFO L78 Accepts]: Start accepts. Automaton has 84 states and 87 transitions. Word has length 67 [2022-11-25 18:23:46,548 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-25 18:23:46,548 INFO L495 AbstractCegarLoop]: Abstraction has 84 states and 87 transitions. [2022-11-25 18:23:46,548 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 36 states, 36 states have (on average 1.9444444444444444) internal successors, (70), 36 states have internal predecessors, (70), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 18:23:46,548 INFO L276 IsEmpty]: Start isEmpty. Operand 84 states and 87 transitions. [2022-11-25 18:23:46,549 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 80 [2022-11-25 18:23:46,549 INFO L187 NwaCegarLoop]: Found error trace [2022-11-25 18:23:46,549 INFO L195 NwaCegarLoop]: trace histogram [22, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 18:23:46,559 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f26c41a-56d7-4548-8d02-7cd563b233b6/bin/uautomizer-ZsLfNo2U6R/z3 -smt2 -in SMTLIB2_COMPLIANT=true (11)] Forceful destruction successful, exit code 0 [2022-11-25 18:23:46,754 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 11 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f26c41a-56d7-4548-8d02-7cd563b233b6/bin/uautomizer-ZsLfNo2U6R/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable23 [2022-11-25 18:23:46,755 INFO L420 AbstractCegarLoop]: === Iteration 25 === Targeting ULTIMATE.startErr24ASSERT_VIOLATIONMEMORY_LEAK === [ULTIMATE.startErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr2REQUIRES_VIOLATIONMEMORY_DEREFERENCE (and 22 more)] === [2022-11-25 18:23:46,755 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 18:23:46,755 INFO L85 PathProgramCache]: Analyzing trace with hash -595228845, now seen corresponding path program 6 times [2022-11-25 18:23:46,755 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 18:23:46,755 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [350155831] [2022-11-25 18:23:46,756 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 18:23:46,756 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 18:23:46,819 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-25 18:23:47,950 INFO L134 CoverageAnalysis]: Checked inductivity of 295 backedges. 0 proven. 253 refuted. 0 times theorem prover too weak. 42 trivial. 0 not checked. [2022-11-25 18:23:47,950 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-25 18:23:47,951 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [350155831] [2022-11-25 18:23:47,951 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [350155831] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-25 18:23:47,951 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1834925414] [2022-11-25 18:23:47,951 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2022-11-25 18:23:47,951 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-25 18:23:47,951 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f26c41a-56d7-4548-8d02-7cd563b233b6/bin/uautomizer-ZsLfNo2U6R/z3 [2022-11-25 18:23:47,955 INFO L229 MonitoredProcess]: Starting monitored process 12 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f26c41a-56d7-4548-8d02-7cd563b233b6/bin/uautomizer-ZsLfNo2U6R/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-25 18:23:47,974 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f26c41a-56d7-4548-8d02-7cd563b233b6/bin/uautomizer-ZsLfNo2U6R/z3 -smt2 -in SMTLIB2_COMPLIANT=true (12)] Waiting until timeout for monitored process [2022-11-25 18:24:15,709 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 12 check-sat command(s) [2022-11-25 18:24:15,709 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-25 18:24:15,727 INFO L263 TraceCheckSpWp]: Trace formula consists of 426 conjuncts, 62 conjunts are in the unsatisfiable core [2022-11-25 18:24:15,729 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-25 18:24:16,841 INFO L134 CoverageAnalysis]: Checked inductivity of 295 backedges. 0 proven. 253 refuted. 0 times theorem prover too weak. 42 trivial. 0 not checked. [2022-11-25 18:24:16,841 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-25 18:24:19,103 INFO L134 CoverageAnalysis]: Checked inductivity of 295 backedges. 0 proven. 253 refuted. 0 times theorem prover too weak. 42 trivial. 0 not checked. [2022-11-25 18:24:19,104 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1834925414] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-25 18:24:19,104 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-25 18:24:19,104 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [26, 26, 26] total 72 [2022-11-25 18:24:19,104 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1037954183] [2022-11-25 18:24:19,105 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-25 18:24:19,105 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 72 states [2022-11-25 18:24:19,105 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-25 18:24:19,106 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 72 interpolants. [2022-11-25 18:24:19,108 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1310, Invalid=3802, Unknown=0, NotChecked=0, Total=5112 [2022-11-25 18:24:19,109 INFO L87 Difference]: Start difference. First operand 84 states and 87 transitions. Second operand has 72 states, 72 states have (on average 1.4722222222222223) internal successors, (106), 72 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 18:24:42,013 WARN L233 SmtUtils]: Spent 8.25s on a formula simplification. DAG size of input: 120 DAG size of output: 14 (called from [L 361] de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.smt.predicates.PredicateUnifier.getOrConstructPredicate) [2022-11-25 18:24:59,808 WARN L233 SmtUtils]: Spent 7.44s on a formula simplification. DAG size of input: 114 DAG size of output: 14 (called from [L 361] de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.smt.predicates.PredicateUnifier.getOrConstructPredicate) [2022-11-25 18:25:13,428 WARN L233 SmtUtils]: Spent 5.03s on a formula simplification. DAG size of input: 108 DAG size of output: 14 (called from [L 361] de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.smt.predicates.PredicateUnifier.getOrConstructPredicate) [2022-11-25 18:28:09,978 WARN L233 SmtUtils]: Spent 35.44s on a formula simplification. DAG size of input: 116 DAG size of output: 26 (called from [L 361] de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.smt.predicates.PredicateUnifier.getOrConstructPredicate) [2022-11-25 18:28:13,060 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-25 18:28:13,061 INFO L93 Difference]: Finished difference Result 108 states and 111 transitions. [2022-11-25 18:28:13,062 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 50 states. [2022-11-25 18:28:13,062 INFO L78 Accepts]: Start accepts. Automaton has has 72 states, 72 states have (on average 1.4722222222222223) internal successors, (106), 72 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 79 [2022-11-25 18:28:13,062 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-25 18:28:13,063 INFO L225 Difference]: With dead ends: 108 [2022-11-25 18:28:13,063 INFO L226 Difference]: Without dead ends: 108 [2022-11-25 18:28:13,066 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 206 GetRequests, 111 SyntacticMatches, 1 SemanticMatches, 94 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2192 ImplicationChecksByTransitivity, 233.6s TimeCoverageRelationStatistics Valid=2498, Invalid=6621, Unknown=1, NotChecked=0, Total=9120 [2022-11-25 18:28:13,067 INFO L413 NwaCegarLoop]: 40 mSDtfsCounter, 468 mSDsluCounter, 688 mSDsCounter, 0 mSdLazyCounter, 1021 mSolverCounterSat, 38 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 3.7s Time, 0 mProtectedPredicate, 0 mProtectedAction, 468 SdHoareTripleChecker+Valid, 728 SdHoareTripleChecker+Invalid, 1059 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 38 IncrementalHoareTripleChecker+Valid, 1021 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 3.9s IncrementalHoareTripleChecker+Time [2022-11-25 18:28:13,067 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [468 Valid, 728 Invalid, 1059 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [38 Valid, 1021 Invalid, 0 Unknown, 0 Unchecked, 3.9s Time] [2022-11-25 18:28:13,068 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 108 states. [2022-11-25 18:28:13,070 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 108 to 108. [2022-11-25 18:28:13,070 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 108 states, 104 states have (on average 1.0288461538461537) internal successors, (107), 106 states have internal predecessors, (107), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2022-11-25 18:28:13,071 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 108 states to 108 states and 111 transitions. [2022-11-25 18:28:13,071 INFO L78 Accepts]: Start accepts. Automaton has 108 states and 111 transitions. Word has length 79 [2022-11-25 18:28:13,071 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-25 18:28:13,071 INFO L495 AbstractCegarLoop]: Abstraction has 108 states and 111 transitions. [2022-11-25 18:28:13,072 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 72 states, 72 states have (on average 1.4722222222222223) internal successors, (106), 72 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 18:28:13,072 INFO L276 IsEmpty]: Start isEmpty. Operand 108 states and 111 transitions. [2022-11-25 18:28:13,073 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 104 [2022-11-25 18:28:13,073 INFO L187 NwaCegarLoop]: Found error trace [2022-11-25 18:28:13,073 INFO L195 NwaCegarLoop]: trace histogram [46, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 18:28:13,086 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f26c41a-56d7-4548-8d02-7cd563b233b6/bin/uautomizer-ZsLfNo2U6R/z3 -smt2 -in SMTLIB2_COMPLIANT=true (12)] Forceful destruction successful, exit code 0 [2022-11-25 18:28:13,285 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 12 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f26c41a-56d7-4548-8d02-7cd563b233b6/bin/uautomizer-ZsLfNo2U6R/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable24 [2022-11-25 18:28:13,285 INFO L420 AbstractCegarLoop]: === Iteration 26 === Targeting ULTIMATE.startErr24ASSERT_VIOLATIONMEMORY_LEAK === [ULTIMATE.startErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr2REQUIRES_VIOLATIONMEMORY_DEREFERENCE (and 22 more)] === [2022-11-25 18:28:13,286 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 18:28:13,286 INFO L85 PathProgramCache]: Analyzing trace with hash 51574227, now seen corresponding path program 7 times [2022-11-25 18:28:13,286 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 18:28:13,286 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [778587677] [2022-11-25 18:28:13,286 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 18:28:13,286 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 18:28:13,433 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-25 18:28:16,860 INFO L134 CoverageAnalysis]: Checked inductivity of 1123 backedges. 0 proven. 1081 refuted. 0 times theorem prover too weak. 42 trivial. 0 not checked. [2022-11-25 18:28:16,860 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-25 18:28:16,860 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [778587677] [2022-11-25 18:28:16,861 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [778587677] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-25 18:28:16,861 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [352974615] [2022-11-25 18:28:16,861 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2022-11-25 18:28:16,861 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-25 18:28:16,861 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f26c41a-56d7-4548-8d02-7cd563b233b6/bin/uautomizer-ZsLfNo2U6R/z3 [2022-11-25 18:28:16,867 INFO L229 MonitoredProcess]: Starting monitored process 13 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f26c41a-56d7-4548-8d02-7cd563b233b6/bin/uautomizer-ZsLfNo2U6R/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-25 18:28:16,875 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f26c41a-56d7-4548-8d02-7cd563b233b6/bin/uautomizer-ZsLfNo2U6R/z3 -smt2 -in SMTLIB2_COMPLIANT=true (13)] Waiting until timeout for monitored process [2022-11-25 18:28:17,647 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-25 18:28:17,653 INFO L263 TraceCheckSpWp]: Trace formula consists of 594 conjuncts, 97 conjunts are in the unsatisfiable core [2022-11-25 18:28:17,657 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-25 18:28:21,876 INFO L134 CoverageAnalysis]: Checked inductivity of 1123 backedges. 0 proven. 1081 refuted. 0 times theorem prover too weak. 42 trivial. 0 not checked. [2022-11-25 18:28:21,877 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-25 18:28:28,405 INFO L134 CoverageAnalysis]: Checked inductivity of 1123 backedges. 0 proven. 1081 refuted. 0 times theorem prover too weak. 42 trivial. 0 not checked. [2022-11-25 18:28:28,405 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [352974615] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-25 18:28:28,406 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-25 18:28:28,406 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [50, 50, 50] total 144 [2022-11-25 18:28:28,406 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1785758607] [2022-11-25 18:28:28,406 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-25 18:28:28,407 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 144 states [2022-11-25 18:28:28,407 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-25 18:28:28,411 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 144 interpolants. [2022-11-25 18:28:28,418 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=4934, Invalid=15658, Unknown=0, NotChecked=0, Total=20592 [2022-11-25 18:28:28,419 INFO L87 Difference]: Start difference. First operand 108 states and 111 transitions. Second operand has 144 states, 144 states have (on average 1.2361111111111112) internal successors, (178), 144 states have internal predecessors, (178), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 18:28:32,235 WARN L837 $PredicateComparison]: unable to prove that (let ((.cse0 (mod |c_ULTIMATE.start_#Ultimate.C_memset_#amount#1| 4294967296))) (and (< (mod (+ 18 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 8 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 24) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 43) 4294967296) .cse0) (< (mod (+ 3 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 45 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (<= |c_ULTIMATE.start_#Ultimate.C_memset_#amount#1| 94) (< (mod (+ 41 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 34 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 19 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 5 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 9 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 37) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 1) 4294967296) .cse0) (< (mod (+ 20 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 23 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 10) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 4) 4294967296) .cse0) (< (mod (+ 33 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 11) 4294967296) .cse0) (< (mod (+ 32 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 38 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 29 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 36 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 40 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 42 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 46 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 7 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 2 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (<= 94 |c_ULTIMATE.start_#Ultimate.C_memset_#amount#1|) (< (mod (+ 44 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 21 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 17) 4294967296) .cse0) (< (mod (+ 15 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 14 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 13) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 25) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 26) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 28) 4294967296) .cse0) (< (mod (+ 12 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 16 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 6 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 22 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 31 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 27) 4294967296) .cse0) (< (mod (+ 35 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 39 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 30 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0))) is different from false [2022-11-25 18:28:34,260 WARN L837 $PredicateComparison]: unable to prove that (let ((.cse0 (mod |c_ULTIMATE.start_#Ultimate.C_memset_#amount#1| 4294967296))) (and (< (mod (+ 18 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 8 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 24) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 43) 4294967296) .cse0) (< (mod (+ 3 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 45 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 41 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 34 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 19 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 5 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 9 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 37) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 1) 4294967296) .cse0) (< (mod (+ 20 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 23 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 10) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 4) 4294967296) .cse0) (< (mod (+ 33 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 11) 4294967296) .cse0) (< (mod (+ 32 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 38 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 29 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 36 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 40 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 42 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 7 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 2 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 44 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 21 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 17) 4294967296) .cse0) (< (mod (+ 15 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 14 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 13) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 25) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 26) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 28) 4294967296) .cse0) (< (mod (+ 12 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 16 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 6 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 22 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 31 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 27) 4294967296) .cse0) (< (mod (+ 35 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 39 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 30 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0))) is different from false [2022-11-25 18:28:36,278 WARN L837 $PredicateComparison]: unable to prove that (let ((.cse0 (mod |c_ULTIMATE.start_#Ultimate.C_memset_#amount#1| 4294967296))) (and (< (mod (+ 18 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 8 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 24) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 43) 4294967296) .cse0) (< (mod (+ 3 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 41 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 34 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 19 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 5 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 9 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 37) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 1) 4294967296) .cse0) (< (mod (+ 20 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 23 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 10) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 4) 4294967296) .cse0) (< (mod (+ 33 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 11) 4294967296) .cse0) (< (mod (+ 32 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 38 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 29 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 36 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 40 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 42 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 7 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 2 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 44 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 21 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 17) 4294967296) .cse0) (< (mod (+ 15 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 14 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 13) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 25) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 26) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 28) 4294967296) .cse0) (< (mod (+ 12 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 16 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 6 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 22 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 31 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 27) 4294967296) .cse0) (< (mod (+ 35 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 39 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 30 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0))) is different from false [2022-11-25 18:28:38,296 WARN L837 $PredicateComparison]: unable to prove that (let ((.cse0 (mod |c_ULTIMATE.start_#Ultimate.C_memset_#amount#1| 4294967296))) (and (< (mod (+ 18 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 8 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 24) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 43) 4294967296) .cse0) (< (mod (+ 3 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 41 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 34 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 19 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 5 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 9 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 37) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 1) 4294967296) .cse0) (< (mod (+ 20 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 23 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 10) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 4) 4294967296) .cse0) (< (mod (+ 33 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 11) 4294967296) .cse0) (< (mod (+ 32 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 38 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 29 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 36 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 40 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 42 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 7 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 2 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 21 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 17) 4294967296) .cse0) (< (mod (+ 15 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 14 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 13) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 25) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 26) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 28) 4294967296) .cse0) (< (mod (+ 12 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 16 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 6 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 22 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 31 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 27) 4294967296) .cse0) (< (mod (+ 35 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 39 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 30 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0))) is different from false [2022-11-25 18:28:40,325 WARN L837 $PredicateComparison]: unable to prove that (let ((.cse0 (mod |c_ULTIMATE.start_#Ultimate.C_memset_#amount#1| 4294967296))) (and (< (mod (+ 18 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 8 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 24) 4294967296) .cse0) (< (mod (+ 3 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 41 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 34 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 19 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 5 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 9 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 37) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 1) 4294967296) .cse0) (< (mod (+ 20 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 23 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 10) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 4) 4294967296) .cse0) (< (mod (+ 33 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 11) 4294967296) .cse0) (< (mod (+ 32 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 38 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 29 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 36 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 40 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 42 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 7 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 2 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 21 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 17) 4294967296) .cse0) (< (mod (+ 15 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 14 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 13) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 25) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 26) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 28) 4294967296) .cse0) (< (mod (+ 12 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 16 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 6 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 22 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 31 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 27) 4294967296) .cse0) (< (mod (+ 35 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 39 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 30 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0))) is different from false [2022-11-25 18:28:42,348 WARN L837 $PredicateComparison]: unable to prove that (let ((.cse0 (mod |c_ULTIMATE.start_#Ultimate.C_memset_#amount#1| 4294967296))) (and (< (mod (+ 18 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 8 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 24) 4294967296) .cse0) (< (mod (+ 3 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 41 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 34 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 19 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 5 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 9 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 37) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 1) 4294967296) .cse0) (< (mod (+ 20 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 23 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 10) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 4) 4294967296) .cse0) (< (mod (+ 33 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 11) 4294967296) .cse0) (< (mod (+ 32 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 38 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 29 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 36 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 40 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 7 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 2 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 21 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 17) 4294967296) .cse0) (< (mod (+ 15 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 14 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 13) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 25) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 26) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 28) 4294967296) .cse0) (< (mod (+ 12 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 16 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 6 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 22 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 31 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 27) 4294967296) .cse0) (< (mod (+ 35 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 39 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 30 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0))) is different from false [2022-11-25 18:28:44,359 WARN L837 $PredicateComparison]: unable to prove that (let ((.cse0 (mod |c_ULTIMATE.start_#Ultimate.C_memset_#amount#1| 4294967296))) (and (< (mod (+ 18 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 8 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 24) 4294967296) .cse0) (< (mod (+ 3 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 34 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 19 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 5 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 9 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 37) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 1) 4294967296) .cse0) (< (mod (+ 20 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 23 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 10) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 4) 4294967296) .cse0) (< (mod (+ 33 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 11) 4294967296) .cse0) (< (mod (+ 32 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 38 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 29 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 36 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 40 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 7 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 2 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 21 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 17) 4294967296) .cse0) (< (mod (+ 15 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 14 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 13) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 25) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 26) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 28) 4294967296) .cse0) (< (mod (+ 12 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 16 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 6 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 22 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 31 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 27) 4294967296) .cse0) (< (mod (+ 35 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 39 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 30 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0))) is different from false [2022-11-25 18:28:46,370 WARN L837 $PredicateComparison]: unable to prove that (let ((.cse0 (mod |c_ULTIMATE.start_#Ultimate.C_memset_#amount#1| 4294967296))) (and (< (mod (+ 18 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 8 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 24) 4294967296) .cse0) (< (mod (+ 3 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 34 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 19 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 5 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 9 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 37) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 1) 4294967296) .cse0) (< (mod (+ 20 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 23 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 10) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 4) 4294967296) .cse0) (< (mod (+ 33 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 11) 4294967296) .cse0) (< (mod (+ 32 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 38 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 29 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 36 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 7 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 2 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 21 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 17) 4294967296) .cse0) (< (mod (+ 15 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 14 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 13) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 25) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 26) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 28) 4294967296) .cse0) (< (mod (+ 12 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 16 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 6 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 22 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 31 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 27) 4294967296) .cse0) (< (mod (+ 35 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 39 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 30 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0))) is different from false [2022-11-25 18:28:48,384 WARN L837 $PredicateComparison]: unable to prove that (let ((.cse0 (mod |c_ULTIMATE.start_#Ultimate.C_memset_#amount#1| 4294967296))) (and (< (mod (+ 18 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 8 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 24) 4294967296) .cse0) (< (mod (+ 3 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 34 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 19 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 5 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 9 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 37) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 1) 4294967296) .cse0) (< (mod (+ 20 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 23 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 10) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 4) 4294967296) .cse0) (< (mod (+ 33 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 11) 4294967296) .cse0) (< (mod (+ 32 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 38 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 29 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 36 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 7 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 2 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 21 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 17) 4294967296) .cse0) (< (mod (+ 15 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 14 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 13) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 25) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 26) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 28) 4294967296) .cse0) (< (mod (+ 12 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 16 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 6 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 22 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 31 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 27) 4294967296) .cse0) (< (mod (+ 35 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 30 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0))) is different from false [2022-11-25 18:28:50,399 WARN L837 $PredicateComparison]: unable to prove that (let ((.cse0 (mod |c_ULTIMATE.start_#Ultimate.C_memset_#amount#1| 4294967296))) (and (< (mod (+ 18 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 8 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 24) 4294967296) .cse0) (< (mod (+ 3 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 34 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 19 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 5 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 9 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 37) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 1) 4294967296) .cse0) (< (mod (+ 20 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 23 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 10) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 4) 4294967296) .cse0) (< (mod (+ 33 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 11) 4294967296) .cse0) (< (mod (+ 32 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 29 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 36 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 7 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 2 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 21 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 17) 4294967296) .cse0) (< (mod (+ 15 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 14 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 13) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 25) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 26) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 28) 4294967296) .cse0) (< (mod (+ 12 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 16 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 6 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 22 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 31 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 27) 4294967296) .cse0) (< (mod (+ 35 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 30 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0))) is different from false [2022-11-25 18:28:52,426 WARN L837 $PredicateComparison]: unable to prove that (let ((.cse0 (mod |c_ULTIMATE.start_#Ultimate.C_memset_#amount#1| 4294967296))) (and (< (mod (+ 18 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 8 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 24) 4294967296) .cse0) (< (mod (+ 3 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 34 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 19 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 5 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 9 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 1) 4294967296) .cse0) (< (mod (+ 20 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 23 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 10) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 4) 4294967296) .cse0) (< (mod (+ 33 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 11) 4294967296) .cse0) (< (mod (+ 32 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 29 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 36 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 7 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 2 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 21 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 17) 4294967296) .cse0) (< (mod (+ 15 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 14 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 13) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 25) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 26) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 28) 4294967296) .cse0) (< (mod (+ 12 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 16 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 6 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 22 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 31 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 27) 4294967296) .cse0) (< (mod (+ 35 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 30 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0))) is different from false [2022-11-25 18:28:54,449 WARN L837 $PredicateComparison]: unable to prove that (let ((.cse0 (mod |c_ULTIMATE.start_#Ultimate.C_memset_#amount#1| 4294967296))) (and (< (mod (+ 18 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 8 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 24) 4294967296) .cse0) (< (mod (+ 3 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 34 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 19 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 5 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 9 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 1) 4294967296) .cse0) (< (mod (+ 20 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 23 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 10) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 4) 4294967296) .cse0) (< (mod (+ 33 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 11) 4294967296) .cse0) (< (mod (+ 32 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 29 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 7 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 2 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 21 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 17) 4294967296) .cse0) (< (mod (+ 15 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 14 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 13) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 25) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 26) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 28) 4294967296) .cse0) (< (mod (+ 12 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 16 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 6 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 22 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 31 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 27) 4294967296) .cse0) (< (mod (+ 35 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 30 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0))) is different from false [2022-11-25 18:28:56,462 WARN L837 $PredicateComparison]: unable to prove that (let ((.cse0 (mod |c_ULTIMATE.start_#Ultimate.C_memset_#amount#1| 4294967296))) (and (< (mod (+ 18 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 8 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 24) 4294967296) .cse0) (< (mod (+ 3 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 34 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 19 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 5 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 9 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 1) 4294967296) .cse0) (< (mod (+ 20 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 23 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 10) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 4) 4294967296) .cse0) (< (mod (+ 33 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 11) 4294967296) .cse0) (< (mod (+ 32 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 29 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 7 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 2 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 21 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 17) 4294967296) .cse0) (< (mod (+ 15 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 14 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 13) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 25) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 26) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 28) 4294967296) .cse0) (< (mod (+ 12 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 16 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 6 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 22 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 31 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 27) 4294967296) .cse0) (< (mod (+ 30 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0))) is different from false [2022-11-25 18:28:58,475 WARN L837 $PredicateComparison]: unable to prove that (let ((.cse0 (mod |c_ULTIMATE.start_#Ultimate.C_memset_#amount#1| 4294967296))) (and (< (mod (+ 18 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 8 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 24) 4294967296) .cse0) (< (mod (+ 3 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 19 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 5 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 9 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 1) 4294967296) .cse0) (< (mod (+ 20 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 23 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 10) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 4) 4294967296) .cse0) (< (mod (+ 33 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 11) 4294967296) .cse0) (< (mod (+ 32 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 29 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 7 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 2 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 21 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 17) 4294967296) .cse0) (< (mod (+ 15 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 14 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 13) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 25) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 26) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 28) 4294967296) .cse0) (< (mod (+ 12 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 16 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 6 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 22 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 31 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 27) 4294967296) .cse0) (< (mod (+ 30 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0))) is different from false [2022-11-25 18:29:00,491 WARN L837 $PredicateComparison]: unable to prove that (let ((.cse0 (mod |c_ULTIMATE.start_#Ultimate.C_memset_#amount#1| 4294967296))) (and (< (mod (+ 18 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 8 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 24) 4294967296) .cse0) (< (mod (+ 3 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 19 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 5 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 9 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 1) 4294967296) .cse0) (< (mod (+ 20 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 23 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 10) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 4) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 11) 4294967296) .cse0) (< (mod (+ 32 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 29 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 7 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 2 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 21 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 17) 4294967296) .cse0) (< (mod (+ 15 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 14 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 13) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 25) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 26) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 28) 4294967296) .cse0) (< (mod (+ 12 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 16 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 6 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 22 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 31 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 27) 4294967296) .cse0) (< (mod (+ 30 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0))) is different from false [2022-11-25 18:29:02,507 WARN L837 $PredicateComparison]: unable to prove that (let ((.cse0 (mod |c_ULTIMATE.start_#Ultimate.C_memset_#amount#1| 4294967296))) (and (< (mod (+ 18 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 8 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 24) 4294967296) .cse0) (< (mod (+ 3 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 19 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 5 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 9 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 1) 4294967296) .cse0) (< (mod (+ 20 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 23 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 10) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 4) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 11) 4294967296) .cse0) (< (mod (+ 29 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 7 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 2 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 21 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 17) 4294967296) .cse0) (< (mod (+ 15 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 14 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 13) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 25) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 26) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 28) 4294967296) .cse0) (< (mod (+ 12 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 16 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 6 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 22 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 31 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 27) 4294967296) .cse0) (< (mod (+ 30 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0))) is different from false [2022-11-25 18:29:04,532 WARN L837 $PredicateComparison]: unable to prove that (let ((.cse0 (mod |c_ULTIMATE.start_#Ultimate.C_memset_#amount#1| 4294967296))) (and (< (mod (+ 18 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 8 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 24) 4294967296) .cse0) (< (mod (+ 3 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 19 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 5 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 9 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 1) 4294967296) .cse0) (< (mod (+ 20 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 23 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 10) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 4) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 11) 4294967296) .cse0) (< (mod (+ 29 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 7 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 2 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 21 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 17) 4294967296) .cse0) (< (mod (+ 15 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 14 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 13) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 25) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 26) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 28) 4294967296) .cse0) (< (mod (+ 12 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 16 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 6 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 22 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 27) 4294967296) .cse0) (< (mod (+ 30 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0))) is different from false [2022-11-25 18:29:06,547 WARN L837 $PredicateComparison]: unable to prove that (let ((.cse0 (mod |c_ULTIMATE.start_#Ultimate.C_memset_#amount#1| 4294967296))) (and (< (mod (+ 18 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 8 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 24) 4294967296) .cse0) (< (mod (+ 3 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 19 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 5 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 9 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 1) 4294967296) .cse0) (< (mod (+ 20 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 23 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 10) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 4) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 11) 4294967296) .cse0) (< (mod (+ 29 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 7 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 2 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 21 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 17) 4294967296) .cse0) (< (mod (+ 15 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 14 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 13) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 25) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 26) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 28) 4294967296) .cse0) (< (mod (+ 12 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 16 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 6 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 22 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 27) 4294967296) .cse0))) is different from false [2022-11-25 18:29:08,559 WARN L837 $PredicateComparison]: unable to prove that (let ((.cse0 (mod |c_ULTIMATE.start_#Ultimate.C_memset_#amount#1| 4294967296))) (and (< (mod (+ 18 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 8 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 24) 4294967296) .cse0) (< (mod (+ 3 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 19 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 5 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 9 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 1) 4294967296) .cse0) (< (mod (+ 20 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 23 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 10) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 4) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 11) 4294967296) .cse0) (< (mod (+ 7 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 2 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 21 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 17) 4294967296) .cse0) (< (mod (+ 15 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 14 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 13) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 25) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 26) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 28) 4294967296) .cse0) (< (mod (+ 12 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 16 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 6 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 22 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 27) 4294967296) .cse0))) is different from false [2022-11-25 18:29:10,588 WARN L837 $PredicateComparison]: unable to prove that (let ((.cse0 (mod |c_ULTIMATE.start_#Ultimate.C_memset_#amount#1| 4294967296))) (and (< (mod (+ 18 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 8 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 24) 4294967296) .cse0) (< (mod (+ 3 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 19 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 5 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 9 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 1) 4294967296) .cse0) (< (mod (+ 20 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 23 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 10) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 4) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 11) 4294967296) .cse0) (< (mod (+ 7 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 2 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 21 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 17) 4294967296) .cse0) (< (mod (+ 15 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 14 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 13) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 25) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 26) 4294967296) .cse0) (< (mod (+ 12 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 16 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 6 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 22 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 27) 4294967296) .cse0))) is different from false [2022-11-25 18:32:30,740 WARN L233 SmtUtils]: Spent 1.57m on a formula simplification that was a NOOP. DAG size: 111 (called from [L 361] de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.smt.predicates.PredicateUnifier.getOrConstructPredicate) [2022-11-25 18:32:32,746 WARN L539 Checker$ProtectedHtc]: IncrementalHoareTripleChecker took 2.00s for a HTC check with result UNKNOWN. Formula has sorts [Array, Bool, Int], hasArrays=true, hasNonlinArith=false, quantifiers [] [2022-11-25 18:32:34,753 WARN L539 Checker$ProtectedHtc]: IncrementalHoareTripleChecker took 2.01s for a HTC check with result UNKNOWN. Formula has sorts [Array, Bool, Int], hasArrays=true, hasNonlinArith=false, quantifiers [] [2022-11-25 18:32:36,767 WARN L539 Checker$ProtectedHtc]: IncrementalHoareTripleChecker took 2.01s for a HTC check with result UNKNOWN. Formula has sorts [Array, Bool, Int], hasArrays=true, hasNonlinArith=false, quantifiers [] [2022-11-25 18:32:38,218 WARN L539 Checker$ProtectedHtc]: IncrementalHoareTripleChecker took 1.45s for a HTC check with result INVALID. Formula has sorts [Array, Bool, Int], hasArrays=true, hasNonlinArith=false, quantifiers [] [2022-11-25 18:32:40,775 WARN L539 Checker$ProtectedHtc]: IncrementalHoareTripleChecker took 1.68s for a HTC check with result INVALID. Formula has sorts [Array, Bool, Int], hasArrays=true, hasNonlinArith=false, quantifiers [] [2022-11-25 18:32:42,779 WARN L539 Checker$ProtectedHtc]: IncrementalHoareTripleChecker took 2.00s for a HTC check with result UNKNOWN. Formula has sorts [Array, Bool, Int], hasArrays=true, hasNonlinArith=false, quantifiers [] [2022-11-25 18:32:44,982 WARN L539 Checker$ProtectedHtc]: IncrementalHoareTripleChecker took 2.02s for a HTC check with result UNKNOWN. Formula has sorts [Array, Bool, Int], hasArrays=true, hasNonlinArith=false, quantifiers [] [2022-11-25 18:32:46,987 WARN L539 Checker$ProtectedHtc]: IncrementalHoareTripleChecker took 2.00s for a HTC check with result UNKNOWN. Formula has sorts [Array, Bool, Int], hasArrays=true, hasNonlinArith=false, quantifiers [] [2022-11-25 18:32:48,780 WARN L539 Checker$ProtectedHtc]: IncrementalHoareTripleChecker took 1.79s for a HTC check with result INVALID. Formula has sorts [Array, Bool, Int], hasArrays=true, hasNonlinArith=false, quantifiers [] [2022-11-25 18:32:50,785 WARN L539 Checker$ProtectedHtc]: IncrementalHoareTripleChecker took 2.00s for a HTC check with result UNKNOWN. Formula has sorts [Array, Bool, Int], hasArrays=true, hasNonlinArith=false, quantifiers [] [2022-11-25 18:32:52,845 WARN L539 Checker$ProtectedHtc]: IncrementalHoareTripleChecker took 2.00s for a HTC check with result UNKNOWN. Formula has sorts [Array, Bool, Int], hasArrays=true, hasNonlinArith=false, quantifiers [] [2022-11-25 18:32:54,850 WARN L539 Checker$ProtectedHtc]: IncrementalHoareTripleChecker took 2.00s for a HTC check with result UNKNOWN. Formula has sorts [Array, Bool, Int], hasArrays=true, hasNonlinArith=false, quantifiers [] [2022-11-25 18:32:58,129 WARN L539 Checker$ProtectedHtc]: IncrementalHoareTripleChecker took 2.01s for a HTC check with result UNKNOWN. Formula has sorts [Array, Bool, Int], hasArrays=true, hasNonlinArith=false, quantifiers [] [2022-11-25 18:32:59,364 WARN L539 Checker$ProtectedHtc]: IncrementalHoareTripleChecker took 1.23s for a HTC check with result INVALID. Formula has sorts [Array, Bool, Int], hasArrays=true, hasNonlinArith=false, quantifiers [] [2022-11-25 18:33:01,370 WARN L539 Checker$ProtectedHtc]: IncrementalHoareTripleChecker took 2.01s for a HTC check with result UNKNOWN. Formula has sorts [Array, Bool, Int], hasArrays=true, hasNonlinArith=false, quantifiers [] [2022-11-25 18:33:03,895 WARN L837 $PredicateComparison]: unable to prove that (let ((.cse0 (mod |c_ULTIMATE.start_#Ultimate.C_memset_#amount#1| 4294967296))) (and (< (mod (+ 18 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 8 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 24) 4294967296) .cse0) (< (mod (+ 3 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 19 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 5 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 9 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 1) 4294967296) .cse0) (< (mod (+ 20 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 23 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 10) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 4) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 11) 4294967296) .cse0) (< (mod (+ 7 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 2 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 21 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 17) 4294967296) .cse0) (< (mod (+ 15 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 14 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 13) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 25) 4294967296) .cse0) (< (mod (+ 12 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 16 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 6 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 22 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 4294967296) .cse0))) is different from false [2022-11-25 18:33:05,911 WARN L837 $PredicateComparison]: unable to prove that (let ((.cse0 (mod |c_ULTIMATE.start_#Ultimate.C_memset_#amount#1| 4294967296))) (and (< (mod (+ 18 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 8 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 24) 4294967296) .cse0) (< (mod (+ 3 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 19 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 5 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 9 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 1) 4294967296) .cse0) (< (mod (+ 20 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 23 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 10) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 4) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 11) 4294967296) .cse0) (< (mod (+ 7 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 2 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 21 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 17) 4294967296) .cse0) (< (mod (+ 15 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 14 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 13) 4294967296) .cse0) (< (mod (+ 12 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 16 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 6 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 22 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 4294967296) .cse0))) is different from false [2022-11-25 18:33:07,927 WARN L837 $PredicateComparison]: unable to prove that (let ((.cse0 (mod |c_ULTIMATE.start_#Ultimate.C_memset_#amount#1| 4294967296))) (and (< (mod (+ 18 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 8 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 3 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 19 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 5 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 9 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 1) 4294967296) .cse0) (< (mod (+ 20 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 23 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 10) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 4) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 11) 4294967296) .cse0) (< (mod (+ 7 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 2 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 21 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 17) 4294967296) .cse0) (< (mod (+ 15 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 14 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 13) 4294967296) .cse0) (< (mod (+ 12 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 16 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 6 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 22 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 4294967296) .cse0))) is different from false [2022-11-25 18:33:09,948 WARN L837 $PredicateComparison]: unable to prove that (let ((.cse0 (mod |c_ULTIMATE.start_#Ultimate.C_memset_#amount#1| 4294967296))) (and (< (mod (+ 18 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 8 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 3 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 19 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 5 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 9 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 1) 4294967296) .cse0) (< (mod (+ 20 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 10) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 4) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 11) 4294967296) .cse0) (< (mod (+ 7 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 2 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 21 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 17) 4294967296) .cse0) (< (mod (+ 15 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 14 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 13) 4294967296) .cse0) (< (mod (+ 12 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 16 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 6 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 22 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 4294967296) .cse0))) is different from false [2022-11-25 18:33:11,959 WARN L837 $PredicateComparison]: unable to prove that (let ((.cse0 (mod |c_ULTIMATE.start_#Ultimate.C_memset_#amount#1| 4294967296))) (and (< (mod (+ 18 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 8 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 3 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 19 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 5 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 9 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 1) 4294967296) .cse0) (< (mod (+ 20 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 10) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 4) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 11) 4294967296) .cse0) (< (mod (+ 7 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 2 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 21 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 17) 4294967296) .cse0) (< (mod (+ 15 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 14 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 13) 4294967296) .cse0) (< (mod (+ 12 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 16 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 6 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 4294967296) .cse0))) is different from false [2022-11-25 18:33:13,971 WARN L837 $PredicateComparison]: unable to prove that (let ((.cse0 (mod |c_ULTIMATE.start_#Ultimate.C_memset_#amount#1| 4294967296))) (and (< (mod (+ 18 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 8 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 3 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 19 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 5 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 9 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 1) 4294967296) .cse0) (< (mod (+ 20 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 10) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 4) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 11) 4294967296) .cse0) (< (mod (+ 7 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 2 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 17) 4294967296) .cse0) (< (mod (+ 15 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 14 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 13) 4294967296) .cse0) (< (mod (+ 12 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 16 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 6 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 4294967296) .cse0))) is different from false [2022-11-25 18:33:15,979 WARN L837 $PredicateComparison]: unable to prove that (let ((.cse0 (mod |c_ULTIMATE.start_#Ultimate.C_memset_#amount#1| 4294967296))) (and (< (mod (+ 18 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 8 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 3 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 19 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 5 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 9 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 1) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 10) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 4) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 11) 4294967296) .cse0) (< (mod (+ 7 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 2 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 17) 4294967296) .cse0) (< (mod (+ 15 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 14 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 13) 4294967296) .cse0) (< (mod (+ 12 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 16 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 6 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 4294967296) .cse0))) is different from false [2022-11-25 18:35:55,975 WARN L233 SmtUtils]: Spent 41.53s on a formula simplification that was a NOOP. DAG size: 79 (called from [L 361] de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.smt.predicates.PredicateUnifier.getOrConstructPredicate) [2022-11-25 18:35:59,900 WARN L539 Checker$ProtectedHtc]: IncrementalHoareTripleChecker took 1.45s for a HTC check with result INVALID. Formula has sorts [Array, Bool, Int], hasArrays=true, hasNonlinArith=false, quantifiers [] [2022-11-25 18:36:01,906 WARN L539 Checker$ProtectedHtc]: IncrementalHoareTripleChecker took 2.01s for a HTC check with result UNKNOWN. Formula has sorts [Array, Bool, Int], hasArrays=true, hasNonlinArith=false, quantifiers [] [2022-11-25 18:36:05,010 WARN L539 Checker$ProtectedHtc]: IncrementalHoareTripleChecker took 2.00s for a HTC check with result UNKNOWN. Formula has sorts [Array, Bool, Int], hasArrays=true, hasNonlinArith=false, quantifiers [] [2022-11-25 18:38:19,437 WARN L233 SmtUtils]: Spent 41.47s on a formula simplification that was a NOOP. DAG size: 75 (called from [L 361] de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.smt.predicates.PredicateUnifier.getOrConstructPredicate) [2022-11-25 18:38:21,443 WARN L539 Checker$ProtectedHtc]: IncrementalHoareTripleChecker took 2.00s for a HTC check with result UNKNOWN. Formula has sorts [Array, Bool, Int], hasArrays=true, hasNonlinArith=false, quantifiers [] [2022-11-25 18:38:23,510 WARN L539 Checker$ProtectedHtc]: IncrementalHoareTripleChecker took 2.00s for a HTC check with result UNKNOWN. Formula has sorts [Array, Bool, Int], hasArrays=true, hasNonlinArith=false, quantifiers [] [2022-11-25 18:38:25,523 WARN L837 $PredicateComparison]: unable to prove that (let ((.cse0 (mod |c_ULTIMATE.start_#Ultimate.C_memset_#amount#1| 4294967296))) (and (< (mod (+ 8 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 3 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 5 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 9 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 1) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 10) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 4) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 11) 4294967296) .cse0) (< (mod (+ 7 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 2 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 15 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 14 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 13) 4294967296) .cse0) (< (mod (+ 12 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 16 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 6 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 4294967296) .cse0))) is different from false [2022-11-25 18:38:27,531 WARN L837 $PredicateComparison]: unable to prove that (let ((.cse0 (mod |c_ULTIMATE.start_#Ultimate.C_memset_#amount#1| 4294967296))) (and (< (mod (+ 8 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 3 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 5 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 9 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 1) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 10) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 4) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 11) 4294967296) .cse0) (< (mod (+ 7 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 2 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 15 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 14 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 13) 4294967296) .cse0) (< (mod (+ 12 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 6 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 4294967296) .cse0))) is different from false [2022-11-25 18:38:29,540 WARN L837 $PredicateComparison]: unable to prove that (let ((.cse0 (mod |c_ULTIMATE.start_#Ultimate.C_memset_#amount#1| 4294967296))) (and (< (mod (+ 8 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 3 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 5 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 9 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 1) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 10) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 4) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 11) 4294967296) .cse0) (< (mod (+ 7 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 2 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 14 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 13) 4294967296) .cse0) (< (mod (+ 12 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 6 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 4294967296) .cse0))) is different from false