./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/kundu.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 2329fc70 Calling Ultimate with: /usr/lib/jvm/java-1.11.0-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_56720457-c443-4d3f-8e29-b3fb4d49ec52/bin/uautomizer-uyxdKDjOR8/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_56720457-c443-4d3f-8e29-b3fb4d49ec52/bin/uautomizer-uyxdKDjOR8/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_56720457-c443-4d3f-8e29-b3fb4d49ec52/bin/uautomizer-uyxdKDjOR8/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_56720457-c443-4d3f-8e29-b3fb4d49ec52/bin/uautomizer-uyxdKDjOR8/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/kundu.cil.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_56720457-c443-4d3f-8e29-b3fb4d49ec52/bin/uautomizer-uyxdKDjOR8/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_56720457-c443-4d3f-8e29-b3fb4d49ec52/bin/uautomizer-uyxdKDjOR8 --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 941010afb19994aa6e2e07f5c4b80f87a4c5e60b4e0ef3217e91339d9dc3aacb --- Real Ultimate output --- [0.001s][warning][os,container] Duplicate cpuset controllers detected. Picking /sys/fs/cgroup/cpuset, skipping /sys/fs/cgroup/cpuset. This is Ultimate 0.2.2-dev-2329fc7 [2022-12-13 14:11:53,803 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-12-13 14:11:53,805 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-12-13 14:11:53,824 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-12-13 14:11:53,824 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-12-13 14:11:53,825 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-12-13 14:11:53,827 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-12-13 14:11:53,828 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-12-13 14:11:53,830 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-12-13 14:11:53,831 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-12-13 14:11:53,832 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-12-13 14:11:53,833 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-12-13 14:11:53,833 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-12-13 14:11:53,834 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-12-13 14:11:53,835 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-12-13 14:11:53,837 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-12-13 14:11:53,837 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-12-13 14:11:53,838 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-12-13 14:11:53,840 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-12-13 14:11:53,842 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-12-13 14:11:53,843 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-12-13 14:11:53,845 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-12-13 14:11:53,846 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-12-13 14:11:53,846 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-12-13 14:11:53,850 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-12-13 14:11:53,850 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-12-13 14:11:53,851 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-12-13 14:11:53,852 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-12-13 14:11:53,852 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-12-13 14:11:53,853 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-12-13 14:11:53,853 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-12-13 14:11:53,854 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-12-13 14:11:53,855 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-12-13 14:11:53,856 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-12-13 14:11:53,857 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-12-13 14:11:53,857 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-12-13 14:11:53,858 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-12-13 14:11:53,858 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-12-13 14:11:53,858 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-12-13 14:11:53,859 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-12-13 14:11:53,859 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-12-13 14:11:53,860 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_56720457-c443-4d3f-8e29-b3fb4d49ec52/bin/uautomizer-uyxdKDjOR8/config/svcomp-Termination-32bit-Automizer_Default.epf [2022-12-13 14:11:53,882 INFO L113 SettingsManager]: Loading preferences was successful [2022-12-13 14:11:53,883 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-12-13 14:11:53,883 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-12-13 14:11:53,883 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-12-13 14:11:53,884 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-12-13 14:11:53,884 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-12-13 14:11:53,885 INFO L138 SettingsManager]: * Use SBE=true [2022-12-13 14:11:53,885 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2022-12-13 14:11:53,885 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2022-12-13 14:11:53,885 INFO L138 SettingsManager]: * Use old map elimination=false [2022-12-13 14:11:53,885 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2022-12-13 14:11:53,885 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2022-12-13 14:11:53,886 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2022-12-13 14:11:53,886 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-12-13 14:11:53,886 INFO L138 SettingsManager]: * sizeof long=4 [2022-12-13 14:11:53,886 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2022-12-13 14:11:53,886 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-12-13 14:11:53,887 INFO L138 SettingsManager]: * sizeof POINTER=4 [2022-12-13 14:11:53,887 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-12-13 14:11:53,887 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2022-12-13 14:11:53,887 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2022-12-13 14:11:53,887 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2022-12-13 14:11:53,887 INFO L138 SettingsManager]: * sizeof long double=12 [2022-12-13 14:11:53,888 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-12-13 14:11:53,888 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2022-12-13 14:11:53,888 INFO L138 SettingsManager]: * Use constant arrays=true [2022-12-13 14:11:53,888 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2022-12-13 14:11:53,888 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-12-13 14:11:53,888 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-12-13 14:11:53,889 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-12-13 14:11:53,889 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-12-13 14:11:53,890 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-12-13 14:11:53,890 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_56720457-c443-4d3f-8e29-b3fb4d49ec52/bin/uautomizer-uyxdKDjOR8/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_56720457-c443-4d3f-8e29-b3fb4d49ec52/bin/uautomizer-uyxdKDjOR8 Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 941010afb19994aa6e2e07f5c4b80f87a4c5e60b4e0ef3217e91339d9dc3aacb [2022-12-13 14:11:54,107 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-12-13 14:11:54,126 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-12-13 14:11:54,128 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-12-13 14:11:54,130 INFO L271 PluginConnector]: Initializing CDTParser... [2022-12-13 14:11:54,130 INFO L275 PluginConnector]: CDTParser initialized [2022-12-13 14:11:54,131 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_56720457-c443-4d3f-8e29-b3fb4d49ec52/bin/uautomizer-uyxdKDjOR8/../../sv-benchmarks/c/systemc/kundu.cil.c [2022-12-13 14:11:56,761 INFO L500 CDTParser]: Created temporary CDT project at NULL [2022-12-13 14:11:56,912 INFO L351 CDTParser]: Found 1 translation units. [2022-12-13 14:11:56,912 INFO L172 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_56720457-c443-4d3f-8e29-b3fb4d49ec52/sv-benchmarks/c/systemc/kundu.cil.c [2022-12-13 14:11:56,918 INFO L394 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_56720457-c443-4d3f-8e29-b3fb4d49ec52/bin/uautomizer-uyxdKDjOR8/data/dbb428612/f81b77b7086740bca911b1268eb71d6e/FLAG8926d8ad4 [2022-12-13 14:11:56,928 INFO L402 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_56720457-c443-4d3f-8e29-b3fb4d49ec52/bin/uautomizer-uyxdKDjOR8/data/dbb428612/f81b77b7086740bca911b1268eb71d6e [2022-12-13 14:11:56,931 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-12-13 14:11:56,932 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-12-13 14:11:56,934 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-12-13 14:11:56,934 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-12-13 14:11:56,937 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-12-13 14:11:56,938 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.12 02:11:56" (1/1) ... [2022-12-13 14:11:56,939 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@72d6ae50 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 02:11:56, skipping insertion in model container [2022-12-13 14:11:56,939 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.12 02:11:56" (1/1) ... [2022-12-13 14:11:56,946 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-12-13 14:11:56,975 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-12-13 14:11:57,096 WARN L237 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_56720457-c443-4d3f-8e29-b3fb4d49ec52/sv-benchmarks/c/systemc/kundu.cil.c[635,648] [2022-12-13 14:11:57,147 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-12-13 14:11:57,159 INFO L203 MainTranslator]: Completed pre-run [2022-12-13 14:11:57,170 WARN L237 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_56720457-c443-4d3f-8e29-b3fb4d49ec52/sv-benchmarks/c/systemc/kundu.cil.c[635,648] [2022-12-13 14:11:57,194 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-12-13 14:11:57,209 INFO L208 MainTranslator]: Completed translation [2022-12-13 14:11:57,210 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 02:11:57 WrapperNode [2022-12-13 14:11:57,210 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-12-13 14:11:57,211 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-12-13 14:11:57,211 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-12-13 14:11:57,211 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-12-13 14:11:57,216 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 02:11:57" (1/1) ... [2022-12-13 14:11:57,223 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 02:11:57" (1/1) ... [2022-12-13 14:11:57,252 INFO L138 Inliner]: procedures = 34, calls = 40, calls flagged for inlining = 35, calls inlined = 45, statements flattened = 534 [2022-12-13 14:11:57,252 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-12-13 14:11:57,253 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-12-13 14:11:57,253 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-12-13 14:11:57,253 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-12-13 14:11:57,262 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 02:11:57" (1/1) ... [2022-12-13 14:11:57,262 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 02:11:57" (1/1) ... [2022-12-13 14:11:57,264 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 02:11:57" (1/1) ... [2022-12-13 14:11:57,264 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 02:11:57" (1/1) ... [2022-12-13 14:11:57,271 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 02:11:57" (1/1) ... [2022-12-13 14:11:57,278 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 02:11:57" (1/1) ... [2022-12-13 14:11:57,280 INFO L185 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 02:11:57" (1/1) ... [2022-12-13 14:11:57,282 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 02:11:57" (1/1) ... [2022-12-13 14:11:57,285 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-12-13 14:11:57,285 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-12-13 14:11:57,286 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-12-13 14:11:57,286 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-12-13 14:11:57,287 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 02:11:57" (1/1) ... [2022-12-13 14:11:57,293 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-12-13 14:11:57,303 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_56720457-c443-4d3f-8e29-b3fb4d49ec52/bin/uautomizer-uyxdKDjOR8/z3 [2022-12-13 14:11:57,314 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_56720457-c443-4d3f-8e29-b3fb4d49ec52/bin/uautomizer-uyxdKDjOR8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-12-13 14:11:57,316 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_56720457-c443-4d3f-8e29-b3fb4d49ec52/bin/uautomizer-uyxdKDjOR8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2022-12-13 14:11:57,349 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-12-13 14:11:57,349 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-12-13 14:11:57,349 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-12-13 14:11:57,349 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-12-13 14:11:57,418 INFO L235 CfgBuilder]: Building ICFG [2022-12-13 14:11:57,420 INFO L261 CfgBuilder]: Building CFG for each procedure with an implementation [2022-12-13 14:11:57,804 INFO L276 CfgBuilder]: Performing block encoding [2022-12-13 14:11:57,810 INFO L295 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-12-13 14:11:57,810 INFO L300 CfgBuilder]: Removed 5 assume(true) statements. [2022-12-13 14:11:57,812 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.12 02:11:57 BoogieIcfgContainer [2022-12-13 14:11:57,812 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-12-13 14:11:57,813 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2022-12-13 14:11:57,813 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2022-12-13 14:11:57,816 INFO L275 PluginConnector]: BuchiAutomizer initialized [2022-12-13 14:11:57,817 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-12-13 14:11:57,817 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 13.12 02:11:56" (1/3) ... [2022-12-13 14:11:57,817 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@6c6dfe16 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 13.12 02:11:57, skipping insertion in model container [2022-12-13 14:11:57,818 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-12-13 14:11:57,818 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 02:11:57" (2/3) ... [2022-12-13 14:11:57,818 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@6c6dfe16 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 13.12 02:11:57, skipping insertion in model container [2022-12-13 14:11:57,818 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-12-13 14:11:57,818 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.12 02:11:57" (3/3) ... [2022-12-13 14:11:57,820 INFO L332 chiAutomizerObserver]: Analyzing ICFG kundu.cil.c [2022-12-13 14:11:57,870 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2022-12-13 14:11:57,870 INFO L304 stractBuchiCegarLoop]: Hoare is false [2022-12-13 14:11:57,871 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2022-12-13 14:11:57,871 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2022-12-13 14:11:57,871 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2022-12-13 14:11:57,871 INFO L308 stractBuchiCegarLoop]: Difference is false [2022-12-13 14:11:57,871 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2022-12-13 14:11:57,871 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2022-12-13 14:11:57,876 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 191 states, 190 states have (on average 1.5052631578947369) internal successors, (286), 190 states have internal predecessors, (286), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 14:11:57,903 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 154 [2022-12-13 14:11:57,903 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 14:11:57,903 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 14:11:57,911 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 14:11:57,911 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 14:11:57,912 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2022-12-13 14:11:57,913 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 191 states, 190 states have (on average 1.5052631578947369) internal successors, (286), 190 states have internal predecessors, (286), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 14:11:57,922 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 154 [2022-12-13 14:11:57,922 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 14:11:57,922 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 14:11:57,925 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 14:11:57,925 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 14:11:57,932 INFO L748 eck$LassoCheckResult]: Stem: 52#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(12, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~clk~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 70#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~clk~0 := 0;~max_loop~0 := 8;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1; 182#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 64#update_channels_returnLabel#1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 93#L305true assume !(1 == ~P_1_i~0);~P_1_st~0 := 2; 164#L305-2true assume 1 == ~P_2_i~0;~P_2_st~0 := 0; 108#L310-1true assume !(1 == ~C_1_i~0);~C_1_st~0 := 2; 168#L315-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 131#fire_delta_events_returnLabel#1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 130#L118true assume !(1 == ~P_1_pc~0); 89#L118-2true is_P_1_triggered_~__retres1~0#1 := 0; 159#L129true is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 80#is_P_1_triggered_returnLabel#1true activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 6#L491true assume 0 != activate_threads_~tmp~1#1;~P_1_st~0 := 0; 165#L491-2true assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 97#L186true assume 1 == ~P_2_pc~0; 172#L187true assume 1 == ~P_2_ev~0;is_P_2_triggered_~__retres1~1#1 := 1; 102#L197true is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 162#is_P_2_triggered_returnLabel#1true activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 76#L499true assume !(0 != activate_threads_~tmp___0~1#1); 82#L499-2true assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 38#L268true assume 1 == ~C_1_pc~0; 94#L269true assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1; 60#L289true is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 176#is_C_1_triggered_returnLabel#1true activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 39#L507true assume !(0 != activate_threads_~tmp___1~1#1); 47#L507-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 156#reset_delta_events_returnLabel#1true assume { :end_inline_reset_delta_events } true; 67#L561-2true [2022-12-13 14:11:57,934 INFO L750 eck$LassoCheckResult]: Loop: 67#L561-2true assume !false; 115#L562true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 175#L397true assume !true; 118#eval_returnLabel#1true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 163#update_channels_returnLabel#2true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 69#fire_delta_events_returnLabel#2true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 160#L118-6true assume !(1 == ~P_1_pc~0); 8#L118-8true is_P_1_triggered_~__retres1~0#1 := 0; 25#L129-2true is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 73#is_P_1_triggered_returnLabel#3true activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 142#L491-6true assume 0 != activate_threads_~tmp~1#1;~P_1_st~0 := 0; 45#L491-8true assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 96#L186-6true assume 1 == ~P_2_pc~0; 116#L187-2true assume 1 == ~P_2_ev~0;is_P_2_triggered_~__retres1~1#1 := 1; 154#L197-2true is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 186#is_P_2_triggered_returnLabel#3true activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 53#L499-6true assume 0 != activate_threads_~tmp___0~1#1;~P_2_st~0 := 0; 51#L499-8true assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 19#L268-6true assume 1 == ~C_1_pc~0; 181#L269-2true assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1; 28#L289-2true is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 178#is_C_1_triggered_returnLabel#3true activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 35#L507-6true assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0; 124#L507-8true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 133#reset_delta_events_returnLabel#2true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 105#L328-1true assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 113#L345-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 137#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 3#L580true assume !(0 == start_simulation_~tmp~3#1); 22#L580-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 101#L328-2true assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 161#L345-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 61#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 121#L535true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 12#L542true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 188#stop_simulation_returnLabel#1true start_simulation_#t~ret14#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 106#L593true assume !(0 != start_simulation_~tmp___0~2#1); 67#L561-2true [2022-12-13 14:11:57,938 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 14:11:57,938 INFO L85 PathProgramCache]: Analyzing trace with hash 1332213672, now seen corresponding path program 1 times [2022-12-13 14:11:57,945 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 14:11:57,945 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1664953103] [2022-12-13 14:11:57,945 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 14:11:57,946 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 14:11:58,014 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 14:11:58,101 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 14:11:58,102 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 14:11:58,102 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1664953103] [2022-12-13 14:11:58,103 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1664953103] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 14:11:58,103 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 14:11:58,103 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 14:11:58,104 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [409812946] [2022-12-13 14:11:58,105 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 14:11:58,109 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 14:11:58,109 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 14:11:58,110 INFO L85 PathProgramCache]: Analyzing trace with hash 595290373, now seen corresponding path program 1 times [2022-12-13 14:11:58,110 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 14:11:58,110 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1427464781] [2022-12-13 14:11:58,110 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 14:11:58,111 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 14:11:58,117 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 14:11:58,126 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 14:11:58,127 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 14:11:58,127 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1427464781] [2022-12-13 14:11:58,127 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1427464781] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 14:11:58,127 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 14:11:58,127 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-12-13 14:11:58,127 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1289770967] [2022-12-13 14:11:58,128 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 14:11:58,129 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 14:11:58,129 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 14:11:58,152 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 14:11:58,153 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 14:11:58,155 INFO L87 Difference]: Start difference. First operand has 191 states, 190 states have (on average 1.5052631578947369) internal successors, (286), 190 states have internal predecessors, (286), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 9.333333333333334) internal successors, (28), 3 states have internal predecessors, (28), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 14:11:58,183 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 14:11:58,183 INFO L93 Difference]: Finished difference Result 187 states and 270 transitions. [2022-12-13 14:11:58,184 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 187 states and 270 transitions. [2022-12-13 14:11:58,188 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 146 [2022-12-13 14:11:58,192 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 187 states to 179 states and 262 transitions. [2022-12-13 14:11:58,193 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 179 [2022-12-13 14:11:58,193 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 179 [2022-12-13 14:11:58,194 INFO L73 IsDeterministic]: Start isDeterministic. Operand 179 states and 262 transitions. [2022-12-13 14:11:58,195 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 14:11:58,195 INFO L218 hiAutomatonCegarLoop]: Abstraction has 179 states and 262 transitions. [2022-12-13 14:11:58,208 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 179 states and 262 transitions. [2022-12-13 14:11:58,218 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 179 to 179. [2022-12-13 14:11:58,219 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 179 states, 179 states have (on average 1.4636871508379887) internal successors, (262), 178 states have internal predecessors, (262), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 14:11:58,220 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 179 states to 179 states and 262 transitions. [2022-12-13 14:11:58,220 INFO L240 hiAutomatonCegarLoop]: Abstraction has 179 states and 262 transitions. [2022-12-13 14:11:58,221 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 14:11:58,224 INFO L428 stractBuchiCegarLoop]: Abstraction has 179 states and 262 transitions. [2022-12-13 14:11:58,224 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2022-12-13 14:11:58,224 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 179 states and 262 transitions. [2022-12-13 14:11:58,225 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 146 [2022-12-13 14:11:58,226 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 14:11:58,226 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 14:11:58,226 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 14:11:58,226 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 14:11:58,227 INFO L748 eck$LassoCheckResult]: Stem: 486#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(12, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~clk~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 487#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~clk~0 := 0;~max_loop~0 := 8;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1; 512#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 504#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 505#L305 assume 1 == ~P_1_i~0;~P_1_st~0 := 0; 532#L305-2 assume 1 == ~P_2_i~0;~P_2_st~0 := 0; 545#L310-1 assume !(1 == ~C_1_i~0);~C_1_st~0 := 2; 546#L315-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 557#fire_delta_events_returnLabel#1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 555#L118 assume !(1 == ~P_1_pc~0); 526#L118-2 is_P_1_triggered_~__retres1~0#1 := 0; 527#L129 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 522#is_P_1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 396#L491 assume 0 != activate_threads_~tmp~1#1;~P_1_st~0 := 0; 397#L491-2 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 534#L186 assume 1 == ~P_2_pc~0; 535#L187 assume 1 == ~P_2_ev~0;is_P_2_triggered_~__retres1~1#1 := 1; 416#L197 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 539#is_P_2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 518#L499 assume !(0 != activate_threads_~tmp___0~1#1); 519#L499-2 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 461#L268 assume 1 == ~C_1_pc~0; 463#L269 assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1; 496#L289 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 497#is_C_1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 464#L507 assume !(0 != activate_threads_~tmp___1~1#1); 465#L507-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 478#reset_delta_events_returnLabel#1 assume { :end_inline_reset_delta_events } true; 507#L561-2 [2022-12-13 14:11:58,227 INFO L750 eck$LassoCheckResult]: Loop: 507#L561-2 assume !false; 508#L562 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 419#L397 assume !false; 437#L358 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 438#L328 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 480#L345 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 433#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 434#L362 assume !(0 != eval_~tmp___2~0#1); 550#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 551#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 509#fire_delta_events_returnLabel#2 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 510#L118-6 assume 1 == ~P_1_pc~0; 517#L119-2 assume 1 == ~P_1_ev~0;is_P_1_triggered_~__retres1~0#1 := 1; 399#L129-2 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 432#is_P_1_triggered_returnLabel#3 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 514#L491-6 assume 0 != activate_threads_~tmp~1#1;~P_1_st~0 := 0; 472#L491-8 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 473#L186-6 assume 1 == ~P_2_pc~0; 533#L187-2 assume 1 == ~P_2_ev~0;is_P_2_triggered_~__retres1~1#1 := 1; 475#L197-2 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 565#is_P_2_triggered_returnLabel#3 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 488#L499-6 assume 0 != activate_threads_~tmp___0~1#1;~P_2_st~0 := 0; 485#L499-8 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 422#L268-6 assume 1 == ~C_1_pc~0; 423#L269-2 assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1; 439#L289-2 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 440#is_C_1_triggered_returnLabel#3 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 454#L507-6 assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0; 455#L507-8 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 552#reset_delta_events_returnLabel#2 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 543#L328-1 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 401#L345-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 548#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 387#L580 assume !(0 == start_simulation_~tmp~3#1); 389#L580-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 429#L328-2 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 537#L345-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 498#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 499#L535 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 407#L542 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 408#stop_simulation_returnLabel#1 start_simulation_#t~ret14#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 544#L593 assume !(0 != start_simulation_~tmp___0~2#1); 507#L561-2 [2022-12-13 14:11:58,227 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 14:11:58,228 INFO L85 PathProgramCache]: Analyzing trace with hash 1466227178, now seen corresponding path program 1 times [2022-12-13 14:11:58,228 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 14:11:58,228 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [989039031] [2022-12-13 14:11:58,228 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 14:11:58,228 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 14:11:58,238 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 14:11:58,267 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 14:11:58,268 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 14:11:58,268 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [989039031] [2022-12-13 14:11:58,268 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [989039031] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 14:11:58,268 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 14:11:58,268 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 14:11:58,268 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [978929535] [2022-12-13 14:11:58,268 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 14:11:58,269 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 14:11:58,269 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 14:11:58,269 INFO L85 PathProgramCache]: Analyzing trace with hash 1194162143, now seen corresponding path program 1 times [2022-12-13 14:11:58,269 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 14:11:58,270 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [195493028] [2022-12-13 14:11:58,270 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 14:11:58,270 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 14:11:58,285 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 14:11:58,333 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 14:11:58,333 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 14:11:58,333 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [195493028] [2022-12-13 14:11:58,333 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [195493028] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 14:11:58,334 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 14:11:58,334 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-12-13 14:11:58,334 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [934717490] [2022-12-13 14:11:58,334 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 14:11:58,334 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 14:11:58,334 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 14:11:58,335 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 14:11:58,335 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 14:11:58,335 INFO L87 Difference]: Start difference. First operand 179 states and 262 transitions. cyclomatic complexity: 84 Second operand has 3 states, 3 states have (on average 9.333333333333334) internal successors, (28), 3 states have internal predecessors, (28), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 14:11:58,348 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 14:11:58,348 INFO L93 Difference]: Finished difference Result 179 states and 261 transitions. [2022-12-13 14:11:58,348 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 179 states and 261 transitions. [2022-12-13 14:11:58,349 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 146 [2022-12-13 14:11:58,350 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 179 states to 179 states and 261 transitions. [2022-12-13 14:11:58,350 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 179 [2022-12-13 14:11:58,350 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 179 [2022-12-13 14:11:58,350 INFO L73 IsDeterministic]: Start isDeterministic. Operand 179 states and 261 transitions. [2022-12-13 14:11:58,351 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 14:11:58,351 INFO L218 hiAutomatonCegarLoop]: Abstraction has 179 states and 261 transitions. [2022-12-13 14:11:58,351 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 179 states and 261 transitions. [2022-12-13 14:11:58,355 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 179 to 179. [2022-12-13 14:11:58,355 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 179 states, 179 states have (on average 1.458100558659218) internal successors, (261), 178 states have internal predecessors, (261), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 14:11:58,356 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 179 states to 179 states and 261 transitions. [2022-12-13 14:11:58,356 INFO L240 hiAutomatonCegarLoop]: Abstraction has 179 states and 261 transitions. [2022-12-13 14:11:58,356 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 14:11:58,357 INFO L428 stractBuchiCegarLoop]: Abstraction has 179 states and 261 transitions. [2022-12-13 14:11:58,357 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2022-12-13 14:11:58,357 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 179 states and 261 transitions. [2022-12-13 14:11:58,358 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 146 [2022-12-13 14:11:58,358 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 14:11:58,359 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 14:11:58,359 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 14:11:58,359 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 14:11:58,360 INFO L748 eck$LassoCheckResult]: Stem: 853#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(12, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~clk~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 854#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~clk~0 := 0;~max_loop~0 := 8;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1; 878#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 870#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 871#L305 assume 1 == ~P_1_i~0;~P_1_st~0 := 0; 899#L305-2 assume 1 == ~P_2_i~0;~P_2_st~0 := 0; 912#L310-1 assume 1 == ~C_1_i~0;~C_1_st~0 := 0; 913#L315-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 924#fire_delta_events_returnLabel#1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 922#L118 assume !(1 == ~P_1_pc~0); 893#L118-2 is_P_1_triggered_~__retres1~0#1 := 0; 894#L129 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 889#is_P_1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 761#L491 assume 0 != activate_threads_~tmp~1#1;~P_1_st~0 := 0; 762#L491-2 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 901#L186 assume 1 == ~P_2_pc~0; 902#L187 assume 1 == ~P_2_ev~0;is_P_2_triggered_~__retres1~1#1 := 1; 781#L197 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 906#is_P_2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 884#L499 assume !(0 != activate_threads_~tmp___0~1#1); 885#L499-2 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 827#L268 assume 1 == ~C_1_pc~0; 829#L269 assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1; 863#L289 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 864#is_C_1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 830#L507 assume !(0 != activate_threads_~tmp___1~1#1); 831#L507-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 843#reset_delta_events_returnLabel#1 assume { :end_inline_reset_delta_events } true; 873#L561-2 [2022-12-13 14:11:58,360 INFO L750 eck$LassoCheckResult]: Loop: 873#L561-2 assume !false; 874#L562 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 784#L397 assume !false; 802#L358 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 803#L328 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 845#L345 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 799#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 800#L362 assume !(0 != eval_~tmp___2~0#1); 917#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 918#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 876#fire_delta_events_returnLabel#2 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 877#L118-6 assume 1 == ~P_1_pc~0; 886#L119-2 assume 1 == ~P_1_ev~0;is_P_1_triggered_~__retres1~0#1 := 1; 766#L129-2 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 801#is_P_1_triggered_returnLabel#3 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 881#L491-6 assume 0 != activate_threads_~tmp~1#1;~P_1_st~0 := 0; 839#L491-8 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 840#L186-6 assume 1 == ~P_2_pc~0; 900#L187-2 assume 1 == ~P_2_ev~0;is_P_2_triggered_~__retres1~1#1 := 1; 842#L197-2 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 932#is_P_2_triggered_returnLabel#3 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 855#L499-6 assume 0 != activate_threads_~tmp___0~1#1;~P_2_st~0 := 0; 852#L499-8 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 789#L268-6 assume 1 == ~C_1_pc~0; 790#L269-2 assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1; 806#L289-2 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 807#is_C_1_triggered_returnLabel#3 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 821#L507-6 assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0; 822#L507-8 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 919#reset_delta_events_returnLabel#2 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 910#L328-1 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 768#L345-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 915#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 754#L580 assume !(0 == start_simulation_~tmp~3#1); 756#L580-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 796#L328-2 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 904#L345-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 865#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 866#L535 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 774#L542 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 775#stop_simulation_returnLabel#1 start_simulation_#t~ret14#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 911#L593 assume !(0 != start_simulation_~tmp___0~2#1); 873#L561-2 [2022-12-13 14:11:58,360 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 14:11:58,360 INFO L85 PathProgramCache]: Analyzing trace with hash 1247372460, now seen corresponding path program 1 times [2022-12-13 14:11:58,360 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 14:11:58,360 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [498220695] [2022-12-13 14:11:58,361 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 14:11:58,361 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 14:11:58,370 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 14:11:58,410 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 14:11:58,410 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 14:11:58,410 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [498220695] [2022-12-13 14:11:58,410 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [498220695] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 14:11:58,410 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 14:11:58,410 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-12-13 14:11:58,411 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [705865099] [2022-12-13 14:11:58,411 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 14:11:58,411 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 14:11:58,412 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 14:11:58,412 INFO L85 PathProgramCache]: Analyzing trace with hash 1194162143, now seen corresponding path program 2 times [2022-12-13 14:11:58,412 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 14:11:58,412 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [955355029] [2022-12-13 14:11:58,412 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 14:11:58,412 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 14:11:58,423 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 14:11:58,468 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 14:11:58,468 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 14:11:58,468 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [955355029] [2022-12-13 14:11:58,468 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [955355029] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 14:11:58,468 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 14:11:58,468 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-12-13 14:11:58,469 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [118181048] [2022-12-13 14:11:58,469 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 14:11:58,469 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 14:11:58,469 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 14:11:58,469 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-12-13 14:11:58,470 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-12-13 14:11:58,470 INFO L87 Difference]: Start difference. First operand 179 states and 261 transitions. cyclomatic complexity: 83 Second operand has 5 states, 5 states have (on average 5.6) internal successors, (28), 5 states have internal predecessors, (28), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 14:11:58,565 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 14:11:58,565 INFO L93 Difference]: Finished difference Result 483 states and 703 transitions. [2022-12-13 14:11:58,566 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 483 states and 703 transitions. [2022-12-13 14:11:58,569 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 411 [2022-12-13 14:11:58,571 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 483 states to 483 states and 703 transitions. [2022-12-13 14:11:58,571 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 483 [2022-12-13 14:11:58,572 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 483 [2022-12-13 14:11:58,573 INFO L73 IsDeterministic]: Start isDeterministic. Operand 483 states and 703 transitions. [2022-12-13 14:11:58,574 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 14:11:58,575 INFO L218 hiAutomatonCegarLoop]: Abstraction has 483 states and 703 transitions. [2022-12-13 14:11:58,576 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 483 states and 703 transitions. [2022-12-13 14:11:58,585 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 483 to 191. [2022-12-13 14:11:58,585 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 191 states, 191 states have (on average 1.4293193717277486) internal successors, (273), 190 states have internal predecessors, (273), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 14:11:58,586 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 191 states to 191 states and 273 transitions. [2022-12-13 14:11:58,586 INFO L240 hiAutomatonCegarLoop]: Abstraction has 191 states and 273 transitions. [2022-12-13 14:11:58,587 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-12-13 14:11:58,587 INFO L428 stractBuchiCegarLoop]: Abstraction has 191 states and 273 transitions. [2022-12-13 14:11:58,588 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2022-12-13 14:11:58,588 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 191 states and 273 transitions. [2022-12-13 14:11:58,589 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 155 [2022-12-13 14:11:58,589 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 14:11:58,589 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 14:11:58,590 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 14:11:58,590 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 14:11:58,591 INFO L748 eck$LassoCheckResult]: Stem: 1530#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(12, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~clk~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 1531#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~clk~0 := 0;~max_loop~0 := 8;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1; 1558#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1549#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1550#L305 assume 1 == ~P_1_i~0;~P_1_st~0 := 0; 1581#L305-2 assume 1 == ~P_2_i~0;~P_2_st~0 := 0; 1595#L310-1 assume 1 == ~C_1_i~0;~C_1_st~0 := 0; 1596#L315-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1607#fire_delta_events_returnLabel#1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 1605#L118 assume !(1 == ~P_1_pc~0); 1575#L118-2 is_P_1_triggered_~__retres1~0#1 := 0; 1576#L129 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 1620#is_P_1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 1440#L491 assume !(0 != activate_threads_~tmp~1#1); 1441#L491-2 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 1583#L186 assume 1 == ~P_2_pc~0; 1584#L187 assume 1 == ~P_2_ev~0;is_P_2_triggered_~__retres1~1#1 := 1; 1463#L197 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 1589#is_P_2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 1566#L499 assume !(0 != activate_threads_~tmp___0~1#1); 1567#L499-2 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 1505#L268 assume 1 == ~C_1_pc~0; 1507#L269 assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1; 1541#L289 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 1542#is_C_1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1508#L507 assume !(0 != activate_threads_~tmp___1~1#1); 1509#L507-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1525#reset_delta_events_returnLabel#1 assume { :end_inline_reset_delta_events } true; 1553#L561-2 [2022-12-13 14:11:58,591 INFO L750 eck$LassoCheckResult]: Loop: 1553#L561-2 assume !false; 1554#L562 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 1459#L397 assume !false; 1479#L358 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 1480#L328 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 1521#L345 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 1476#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1477#L362 assume !(0 != eval_~tmp___2~0#1); 1600#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1601#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1555#fire_delta_events_returnLabel#2 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 1556#L118-6 assume !(1 == ~P_1_pc~0); 1442#L118-8 is_P_1_triggered_~__retres1~0#1 := 0; 1443#L129-2 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 1478#is_P_1_triggered_returnLabel#3 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 1610#L491-6 assume !(0 != activate_threads_~tmp~1#1); 1516#L491-8 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 1517#L186-6 assume 1 == ~P_2_pc~0; 1582#L187-2 assume 1 == ~P_2_ev~0;is_P_2_triggered_~__retres1~1#1 := 1; 1519#L197-2 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 1619#is_P_2_triggered_returnLabel#3 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 1532#L499-6 assume 0 != activate_threads_~tmp___0~1#1;~P_2_st~0 := 0; 1529#L499-8 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 1466#L268-6 assume 1 == ~C_1_pc~0; 1467#L269-2 assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1; 1483#L289-2 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 1484#is_C_1_triggered_returnLabel#3 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1498#L507-6 assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0; 1499#L507-8 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1602#reset_delta_events_returnLabel#2 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 1593#L328-1 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 1445#L345-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 1598#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 1431#L580 assume !(0 == start_simulation_~tmp~3#1); 1433#L580-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 1473#L328-2 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 1587#L345-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 1543#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 1544#L535 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1451#L542 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1452#stop_simulation_returnLabel#1 start_simulation_#t~ret14#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 1594#L593 assume !(0 != start_simulation_~tmp___0~2#1); 1553#L561-2 [2022-12-13 14:11:58,591 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 14:11:58,591 INFO L85 PathProgramCache]: Analyzing trace with hash -32491218, now seen corresponding path program 1 times [2022-12-13 14:11:58,591 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 14:11:58,592 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [345126427] [2022-12-13 14:11:58,592 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 14:11:58,592 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 14:11:58,604 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 14:11:58,645 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 14:11:58,645 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 14:11:58,645 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [345126427] [2022-12-13 14:11:58,645 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [345126427] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 14:11:58,645 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 14:11:58,645 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2022-12-13 14:11:58,646 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1178674243] [2022-12-13 14:11:58,646 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 14:11:58,646 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 14:11:58,646 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 14:11:58,647 INFO L85 PathProgramCache]: Analyzing trace with hash 1345919202, now seen corresponding path program 1 times [2022-12-13 14:11:58,647 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 14:11:58,647 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [134410781] [2022-12-13 14:11:58,647 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 14:11:58,647 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 14:11:58,656 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 14:11:58,690 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 14:11:58,691 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 14:11:58,691 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [134410781] [2022-12-13 14:11:58,691 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [134410781] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 14:11:58,691 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 14:11:58,691 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-12-13 14:11:58,691 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1683632771] [2022-12-13 14:11:58,691 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 14:11:58,692 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 14:11:58,692 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 14:11:58,692 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 14:11:58,692 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 14:11:58,693 INFO L87 Difference]: Start difference. First operand 191 states and 273 transitions. cyclomatic complexity: 83 Second operand has 4 states, 4 states have (on average 7.0) internal successors, (28), 4 states have internal predecessors, (28), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 14:11:58,762 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 14:11:58,762 INFO L93 Difference]: Finished difference Result 478 states and 671 transitions. [2022-12-13 14:11:58,762 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 478 states and 671 transitions. [2022-12-13 14:11:58,765 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 415 [2022-12-13 14:11:58,768 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 478 states to 478 states and 671 transitions. [2022-12-13 14:11:58,768 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 478 [2022-12-13 14:11:58,769 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 478 [2022-12-13 14:11:58,769 INFO L73 IsDeterministic]: Start isDeterministic. Operand 478 states and 671 transitions. [2022-12-13 14:11:58,770 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 14:11:58,770 INFO L218 hiAutomatonCegarLoop]: Abstraction has 478 states and 671 transitions. [2022-12-13 14:11:58,771 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 478 states and 671 transitions. [2022-12-13 14:11:58,780 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 478 to 436. [2022-12-13 14:11:58,781 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 436 states, 436 states have (on average 1.4128440366972477) internal successors, (616), 435 states have internal predecessors, (616), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 14:11:58,783 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 436 states to 436 states and 616 transitions. [2022-12-13 14:11:58,783 INFO L240 hiAutomatonCegarLoop]: Abstraction has 436 states and 616 transitions. [2022-12-13 14:11:58,783 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 14:11:58,784 INFO L428 stractBuchiCegarLoop]: Abstraction has 436 states and 616 transitions. [2022-12-13 14:11:58,784 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2022-12-13 14:11:58,784 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 436 states and 616 transitions. [2022-12-13 14:11:58,786 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 399 [2022-12-13 14:11:58,786 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 14:11:58,787 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 14:11:58,787 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 14:11:58,787 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 14:11:58,788 INFO L748 eck$LassoCheckResult]: Stem: 2213#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(12, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~clk~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 2214#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~clk~0 := 0;~max_loop~0 := 8;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1; 2240#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2231#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2232#L305 assume 1 == ~P_1_i~0;~P_1_st~0 := 0; 2262#L305-2 assume 1 == ~P_2_i~0;~P_2_st~0 := 0; 2274#L310-1 assume 1 == ~C_1_i~0;~C_1_st~0 := 0; 2275#L315-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2290#fire_delta_events_returnLabel#1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 2289#L118 assume !(1 == ~P_1_pc~0); 2256#L118-2 is_P_1_triggered_~__retres1~0#1 := 0; 2257#L129 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 2252#is_P_1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 2120#L491 assume !(0 != activate_threads_~tmp~1#1); 2121#L491-2 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 2263#L186 assume !(1 == ~P_2_pc~0); 2139#L186-2 is_P_2_triggered_~__retres1~1#1 := 0; 2140#L197 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 2267#is_P_2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 2245#L499 assume !(0 != activate_threads_~tmp___0~1#1); 2246#L499-2 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 2187#L268 assume 1 == ~C_1_pc~0; 2189#L269 assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1; 2224#L289 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 2225#is_C_1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 2190#L507 assume !(0 != activate_threads_~tmp___1~1#1); 2191#L507-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2203#reset_delta_events_returnLabel#1 assume { :end_inline_reset_delta_events } true; 2234#L561-2 [2022-12-13 14:11:58,788 INFO L750 eck$LassoCheckResult]: Loop: 2234#L561-2 assume !false; 2235#L562 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 2143#L397 assume !false; 2162#L358 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 2163#L328 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 2430#L345 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 2427#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 2308#L362 assume !(0 != eval_~tmp___2~0#1); 2284#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2285#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2237#fire_delta_events_returnLabel#2 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 2238#L118-6 assume !(1 == ~P_1_pc~0); 2124#L118-8 is_P_1_triggered_~__retres1~0#1 := 0; 2125#L129-2 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 2161#is_P_1_triggered_returnLabel#3 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 2242#L491-6 assume !(0 != activate_threads_~tmp~1#1); 2199#L491-8 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 2200#L186-6 assume !(1 == ~P_2_pc~0); 2201#L186-8 is_P_2_triggered_~__retres1~1#1 := 0; 2202#L197-2 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 2302#is_P_2_triggered_returnLabel#3 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 2217#L499-6 assume 0 != activate_threads_~tmp___0~1#1;~P_2_st~0 := 0; 2218#L499-8 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 2390#L268-6 assume 1 == ~C_1_pc~0; 2309#L269-2 assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1; 2166#L289-2 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 2167#is_C_1_triggered_returnLabel#3 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 2183#L507-6 assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0; 2184#L507-8 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2286#reset_delta_events_returnLabel#2 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 2272#L328-1 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 2130#L345-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 2277#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 2113#L580 assume !(0 == start_simulation_~tmp~3#1); 2115#L580-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 2156#L328-2 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 2265#L345-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 2226#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 2227#L535 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2133#L542 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2134#stop_simulation_returnLabel#1 start_simulation_#t~ret14#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 2270#L593 assume !(0 != start_simulation_~tmp___0~2#1); 2234#L561-2 [2022-12-13 14:11:58,788 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 14:11:58,788 INFO L85 PathProgramCache]: Analyzing trace with hash -1311815953, now seen corresponding path program 1 times [2022-12-13 14:11:58,789 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 14:11:58,789 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1158026773] [2022-12-13 14:11:58,789 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 14:11:58,789 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 14:11:58,796 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 14:11:58,830 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 14:11:58,830 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 14:11:58,831 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1158026773] [2022-12-13 14:11:58,831 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1158026773] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 14:11:58,831 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 14:11:58,831 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2022-12-13 14:11:58,831 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [998879252] [2022-12-13 14:11:58,831 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 14:11:58,832 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 14:11:58,832 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 14:11:58,832 INFO L85 PathProgramCache]: Analyzing trace with hash -711684829, now seen corresponding path program 1 times [2022-12-13 14:11:58,832 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 14:11:58,832 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [715978551] [2022-12-13 14:11:58,833 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 14:11:58,833 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 14:11:58,839 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 14:11:58,871 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 14:11:58,871 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 14:11:58,871 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [715978551] [2022-12-13 14:11:58,871 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [715978551] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 14:11:58,871 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 14:11:58,871 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-12-13 14:11:58,872 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [469528810] [2022-12-13 14:11:58,872 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 14:11:58,872 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 14:11:58,872 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 14:11:58,872 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 14:11:58,873 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 14:11:58,873 INFO L87 Difference]: Start difference. First operand 436 states and 616 transitions. cyclomatic complexity: 182 Second operand has 4 states, 4 states have (on average 7.0) internal successors, (28), 4 states have internal predecessors, (28), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 14:11:58,972 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 14:11:58,972 INFO L93 Difference]: Finished difference Result 1188 states and 1642 transitions. [2022-12-13 14:11:58,972 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1188 states and 1642 transitions. [2022-12-13 14:11:58,980 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1108 [2022-12-13 14:11:58,986 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1188 states to 1188 states and 1642 transitions. [2022-12-13 14:11:58,986 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1188 [2022-12-13 14:11:58,988 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1188 [2022-12-13 14:11:58,988 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1188 states and 1642 transitions. [2022-12-13 14:11:58,990 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 14:11:58,990 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1188 states and 1642 transitions. [2022-12-13 14:11:58,991 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1188 states and 1642 transitions. [2022-12-13 14:11:59,008 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1188 to 1129. [2022-12-13 14:11:59,010 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1129 states, 1129 states have (on average 1.3906111603188662) internal successors, (1570), 1128 states have internal predecessors, (1570), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 14:11:59,014 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1129 states to 1129 states and 1570 transitions. [2022-12-13 14:11:59,014 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1129 states and 1570 transitions. [2022-12-13 14:11:59,015 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 14:11:59,015 INFO L428 stractBuchiCegarLoop]: Abstraction has 1129 states and 1570 transitions. [2022-12-13 14:11:59,016 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2022-12-13 14:11:59,016 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1129 states and 1570 transitions. [2022-12-13 14:11:59,021 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1087 [2022-12-13 14:11:59,021 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 14:11:59,021 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 14:11:59,022 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 14:11:59,022 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 14:11:59,022 INFO L748 eck$LassoCheckResult]: Stem: 3850#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(12, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~clk~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 3851#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~clk~0 := 0;~max_loop~0 := 8;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1; 3875#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3867#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3868#L305 assume 1 == ~P_1_i~0;~P_1_st~0 := 0; 3903#L305-2 assume 1 == ~P_2_i~0;~P_2_st~0 := 0; 3918#L310-1 assume 1 == ~C_1_i~0;~C_1_st~0 := 0; 3919#L315-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3938#fire_delta_events_returnLabel#1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 3937#L118 assume !(1 == ~P_1_pc~0); 3897#L118-2 is_P_1_triggered_~__retres1~0#1 := 0; 3898#L129 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 3890#is_P_1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 3757#L491 assume !(0 != activate_threads_~tmp~1#1); 3758#L491-2 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 3906#L186 assume !(1 == ~P_2_pc~0); 3776#L186-2 is_P_2_triggered_~__retres1~1#1 := 0; 3777#L197 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 3911#is_P_2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 3883#L499 assume !(0 != activate_threads_~tmp___0~1#1); 3884#L499-2 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 3824#L268 assume !(1 == ~C_1_pc~0); 3825#L268-2 assume 2 == ~C_1_pc~0; 3894#L279 assume 1 == ~C_1_ev~0;is_C_1_triggered_~__retres1~2#1 := 1; 3860#L289 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 3861#is_C_1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 3826#L507 assume !(0 != activate_threads_~tmp___1~1#1); 3827#L507-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3840#reset_delta_events_returnLabel#1 assume { :end_inline_reset_delta_events } true; 3870#L561-2 [2022-12-13 14:11:59,023 INFO L750 eck$LassoCheckResult]: Loop: 3870#L561-2 assume !false; 3871#L562 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 3780#L397 assume !false; 3799#L358 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 3800#L328 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 3842#L345 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 3796#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 3797#L362 assume !(0 != eval_~tmp___2~0#1); 3930#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3931#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3873#fire_delta_events_returnLabel#2 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 3874#L118-6 assume !(1 == ~P_1_pc~0); 3761#L118-8 is_P_1_triggered_~__retres1~0#1 := 0; 3762#L129-2 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 3798#is_P_1_triggered_returnLabel#3 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 3879#L491-6 assume !(0 != activate_threads_~tmp~1#1); 3836#L491-8 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 3837#L186-6 assume !(1 == ~P_2_pc~0); 3905#L186-8 is_P_2_triggered_~__retres1~1#1 := 0; 4861#L197-2 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 4860#is_P_2_triggered_returnLabel#3 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 4859#L499-6 assume 0 != activate_threads_~tmp___0~1#1;~P_2_st~0 := 0; 4858#L499-8 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 4857#L268-6 assume !(1 == ~C_1_pc~0); 4856#L268-8 assume !(2 == ~C_1_pc~0); 3856#L278-5 is_C_1_triggered_~__retres1~2#1 := 0; 3803#L289-2 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 3804#is_C_1_triggered_returnLabel#3 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 3818#L507-6 assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0; 3819#L507-8 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3934#reset_delta_events_returnLabel#2 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 3940#L328-1 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 3921#L345-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 3922#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 3750#L580 assume !(0 == start_simulation_~tmp~3#1); 3752#L580-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 3908#L328-2 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 3909#L345-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 3862#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 3863#L535 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3770#L542 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3771#stop_simulation_returnLabel#1 start_simulation_#t~ret14#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 3916#L593 assume !(0 != start_simulation_~tmp___0~2#1); 3870#L561-2 [2022-12-13 14:11:59,023 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 14:11:59,023 INFO L85 PathProgramCache]: Analyzing trace with hash -122788309, now seen corresponding path program 1 times [2022-12-13 14:11:59,023 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 14:11:59,023 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1733380729] [2022-12-13 14:11:59,024 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 14:11:59,024 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 14:11:59,030 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 14:11:59,056 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 14:11:59,056 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 14:11:59,057 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1733380729] [2022-12-13 14:11:59,057 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1733380729] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 14:11:59,057 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 14:11:59,057 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 14:11:59,057 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [315210741] [2022-12-13 14:11:59,057 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 14:11:59,057 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 14:11:59,058 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 14:11:59,058 INFO L85 PathProgramCache]: Analyzing trace with hash 2031917307, now seen corresponding path program 1 times [2022-12-13 14:11:59,058 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 14:11:59,058 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1220709610] [2022-12-13 14:11:59,058 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 14:11:59,059 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 14:11:59,065 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 14:11:59,092 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 14:11:59,092 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 14:11:59,093 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1220709610] [2022-12-13 14:11:59,093 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1220709610] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 14:11:59,093 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 14:11:59,093 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-12-13 14:11:59,093 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1569758426] [2022-12-13 14:11:59,093 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 14:11:59,094 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 14:11:59,094 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 14:11:59,094 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 14:11:59,094 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 14:11:59,094 INFO L87 Difference]: Start difference. First operand 1129 states and 1570 transitions. cyclomatic complexity: 445 Second operand has 3 states, 3 states have (on average 9.666666666666666) internal successors, (29), 3 states have internal predecessors, (29), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 14:11:59,132 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 14:11:59,132 INFO L93 Difference]: Finished difference Result 1500 states and 2055 transitions. [2022-12-13 14:11:59,133 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1500 states and 2055 transitions. [2022-12-13 14:11:59,146 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1453 [2022-12-13 14:11:59,154 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1500 states to 1500 states and 2055 transitions. [2022-12-13 14:11:59,154 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1500 [2022-12-13 14:11:59,155 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1500 [2022-12-13 14:11:59,156 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1500 states and 2055 transitions. [2022-12-13 14:11:59,157 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 14:11:59,157 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1500 states and 2055 transitions. [2022-12-13 14:11:59,158 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1500 states and 2055 transitions. [2022-12-13 14:11:59,169 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1500 to 1476. [2022-12-13 14:11:59,171 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1476 states, 1476 states have (on average 1.3719512195121952) internal successors, (2025), 1475 states have internal predecessors, (2025), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 14:11:59,173 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1476 states to 1476 states and 2025 transitions. [2022-12-13 14:11:59,174 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1476 states and 2025 transitions. [2022-12-13 14:11:59,174 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 14:11:59,174 INFO L428 stractBuchiCegarLoop]: Abstraction has 1476 states and 2025 transitions. [2022-12-13 14:11:59,175 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2022-12-13 14:11:59,175 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1476 states and 2025 transitions. [2022-12-13 14:11:59,179 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1429 [2022-12-13 14:11:59,179 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 14:11:59,179 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 14:11:59,180 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 14:11:59,180 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 14:11:59,180 INFO L748 eck$LassoCheckResult]: Stem: 6488#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(12, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~clk~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 6489#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~clk~0 := 0;~max_loop~0 := 8;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1; 6517#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 6507#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6508#L305 assume 1 == ~P_1_i~0;~P_1_st~0 := 0; 6547#L305-2 assume 1 == ~P_2_i~0;~P_2_st~0 := 0; 6562#L310-1 assume 1 == ~C_1_i~0;~C_1_st~0 := 0; 6563#L315-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 6580#fire_delta_events_returnLabel#1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 6579#L118 assume !(1 == ~P_1_pc~0); 6542#L118-2 is_P_1_triggered_~__retres1~0#1 := 0; 6543#L129 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 6532#is_P_1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 6395#L491 assume !(0 != activate_threads_~tmp~1#1); 6396#L491-2 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 6549#L186 assume !(1 == ~P_2_pc~0); 6413#L186-2 is_P_2_triggered_~__retres1~1#1 := 0; 6414#L197 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 6554#is_P_2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 6525#L499 assume !(0 != activate_threads_~tmp___0~1#1); 6526#L499-2 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 6464#L268 assume !(1 == ~C_1_pc~0); 6465#L268-2 assume !(2 == ~C_1_pc~0); 6588#L278-1 is_C_1_triggered_~__retres1~2#1 := 0; 6500#L289 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 6501#is_C_1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 6466#L507 assume !(0 != activate_threads_~tmp___1~1#1); 6467#L507-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6478#reset_delta_events_returnLabel#1 assume { :end_inline_reset_delta_events } true; 6558#L561-2 [2022-12-13 14:11:59,180 INFO L750 eck$LassoCheckResult]: Loop: 6558#L561-2 assume !false; 7730#L562 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 7729#L397 assume !false; 7653#L358 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 7647#L328 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 7618#L345 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 7617#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 7561#L362 assume !(0 != eval_~tmp___2~0#1); 6571#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 6572#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 6514#fire_delta_events_returnLabel#2 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 6515#L118-6 assume !(1 == ~P_1_pc~0); 6399#L118-8 is_P_1_triggered_~__retres1~0#1 := 0; 6400#L129-2 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 6435#is_P_1_triggered_returnLabel#3 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 6520#L491-6 assume !(0 != activate_threads_~tmp~1#1); 6590#L491-8 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 6548#L186-6 assume !(1 == ~P_2_pc~0); 6476#L186-8 is_P_2_triggered_~__retres1~1#1 := 0; 6477#L197-2 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 6598#is_P_2_triggered_returnLabel#3 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 7830#L499-6 assume 0 != activate_threads_~tmp___0~1#1;~P_2_st~0 := 0; 7829#L499-8 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 7828#L268-6 assume !(1 == ~C_1_pc~0); 7827#L268-8 assume !(2 == ~C_1_pc~0); 7826#L278-5 is_C_1_triggered_~__retres1~2#1 := 0; 7824#L289-2 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 6611#is_C_1_triggered_returnLabel#3 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 6458#L507-6 assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0; 6459#L507-8 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6575#reset_delta_events_returnLabel#2 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 6560#L328-1 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 6404#L345-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 6566#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 6584#L580 assume !(0 == start_simulation_~tmp~3#1); 6424#L580-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 6425#L328-2 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 6552#L345-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 6502#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 6503#L535 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 6407#L542 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 6408#stop_simulation_returnLabel#1 start_simulation_#t~ret14#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 6557#L593 assume !(0 != start_simulation_~tmp___0~2#1); 6558#L561-2 [2022-12-13 14:11:59,180 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 14:11:59,180 INFO L85 PathProgramCache]: Analyzing trace with hash 1966545068, now seen corresponding path program 1 times [2022-12-13 14:11:59,180 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 14:11:59,180 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [891663162] [2022-12-13 14:11:59,181 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 14:11:59,181 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 14:11:59,193 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 14:11:59,193 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 14:11:59,197 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 14:11:59,212 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 14:11:59,213 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 14:11:59,213 INFO L85 PathProgramCache]: Analyzing trace with hash 2031917307, now seen corresponding path program 2 times [2022-12-13 14:11:59,213 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 14:11:59,213 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [356108382] [2022-12-13 14:11:59,213 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 14:11:59,213 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 14:11:59,218 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 14:11:59,238 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 14:11:59,238 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 14:11:59,238 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [356108382] [2022-12-13 14:11:59,238 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [356108382] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 14:11:59,238 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 14:11:59,238 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-12-13 14:11:59,239 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1884330659] [2022-12-13 14:11:59,239 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 14:11:59,239 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 14:11:59,239 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 14:11:59,239 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-12-13 14:11:59,239 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-12-13 14:11:59,239 INFO L87 Difference]: Start difference. First operand 1476 states and 2025 transitions. cyclomatic complexity: 553 Second operand has 5 states, 5 states have (on average 8.6) internal successors, (43), 5 states have internal predecessors, (43), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 14:11:59,302 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 14:11:59,302 INFO L93 Difference]: Finished difference Result 2613 states and 3559 transitions. [2022-12-13 14:11:59,302 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2613 states and 3559 transitions. [2022-12-13 14:11:59,318 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2548 [2022-12-13 14:11:59,329 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2613 states to 2613 states and 3559 transitions. [2022-12-13 14:11:59,329 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2613 [2022-12-13 14:11:59,332 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2613 [2022-12-13 14:11:59,332 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2613 states and 3559 transitions. [2022-12-13 14:11:59,335 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 14:11:59,336 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2613 states and 3559 transitions. [2022-12-13 14:11:59,338 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2613 states and 3559 transitions. [2022-12-13 14:11:59,362 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2613 to 1512. [2022-12-13 14:11:59,364 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1512 states, 1512 states have (on average 1.3630952380952381) internal successors, (2061), 1511 states have internal predecessors, (2061), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 14:11:59,369 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1512 states to 1512 states and 2061 transitions. [2022-12-13 14:11:59,369 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1512 states and 2061 transitions. [2022-12-13 14:11:59,369 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2022-12-13 14:11:59,370 INFO L428 stractBuchiCegarLoop]: Abstraction has 1512 states and 2061 transitions. [2022-12-13 14:11:59,370 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2022-12-13 14:11:59,370 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1512 states and 2061 transitions. [2022-12-13 14:11:59,377 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1465 [2022-12-13 14:11:59,377 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 14:11:59,377 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 14:11:59,377 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 14:11:59,378 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 14:11:59,378 INFO L748 eck$LassoCheckResult]: Stem: 10593#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(12, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~clk~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 10594#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~clk~0 := 0;~max_loop~0 := 8;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1; 10623#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 10613#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 10614#L305 assume 1 == ~P_1_i~0;~P_1_st~0 := 0; 10650#L305-2 assume 1 == ~P_2_i~0;~P_2_st~0 := 0; 10664#L310-1 assume 1 == ~C_1_i~0;~C_1_st~0 := 0; 10665#L315-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 10681#fire_delta_events_returnLabel#1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 10680#L118 assume !(1 == ~P_1_pc~0); 10644#L118-2 is_P_1_triggered_~__retres1~0#1 := 0; 10645#L129 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 10635#is_P_1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 10502#L491 assume !(0 != activate_threads_~tmp~1#1); 10503#L491-2 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 10652#L186 assume !(1 == ~P_2_pc~0); 10523#L186-2 is_P_2_triggered_~__retres1~1#1 := 0; 10524#L197 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 10657#is_P_2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 10631#L499 assume !(0 != activate_threads_~tmp___0~1#1); 10632#L499-2 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 10568#L268 assume !(1 == ~C_1_pc~0); 10569#L268-2 assume !(2 == ~C_1_pc~0); 10689#L278-1 is_C_1_triggered_~__retres1~2#1 := 0; 10604#L289 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 10605#is_C_1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 10570#L507 assume !(0 != activate_threads_~tmp___1~1#1); 10571#L507-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10588#reset_delta_events_returnLabel#1 assume { :end_inline_reset_delta_events } true; 10618#L561-2 [2022-12-13 14:11:59,378 INFO L750 eck$LassoCheckResult]: Loop: 10618#L561-2 assume !false; 10619#L562 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 10520#L397 assume !false; 10540#L358 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 10541#L328 assume !(0 == ~P_1_st~0); 10583#L332 assume !(0 == ~P_2_st~0); 10585#L336 assume !(0 == ~C_1_st~0);exists_runnable_thread_~__retres1~3#1 := 0; 10666#L345 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 10708#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 11827#L362 assume !(0 != eval_~tmp___2~0#1); 11935#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 11992#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 11991#fire_delta_events_returnLabel#2 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 11990#L118-6 assume !(1 == ~P_1_pc~0); 11989#L118-8 is_P_1_triggered_~__retres1~0#1 := 0; 11988#L129-2 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 11987#is_P_1_triggered_returnLabel#3 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 11986#L491-6 assume !(0 != activate_threads_~tmp~1#1); 11985#L491-8 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 11984#L186-6 assume !(1 == ~P_2_pc~0); 11983#L186-8 is_P_2_triggered_~__retres1~1#1 := 0; 11982#L197-2 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 11981#is_P_2_triggered_returnLabel#3 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 11980#L499-6 assume 0 != activate_threads_~tmp___0~1#1;~P_2_st~0 := 0; 11979#L499-8 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 11978#L268-6 assume !(1 == ~C_1_pc~0); 11977#L268-8 assume !(2 == ~C_1_pc~0); 11976#L278-5 is_C_1_triggered_~__retres1~2#1 := 0; 11975#L289-2 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 11974#is_C_1_triggered_returnLabel#3 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 11973#L507-6 assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0; 11972#L507-8 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11971#reset_delta_events_returnLabel#2 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 11970#L328-1 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 11967#L345-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 11965#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 11964#L580 assume !(0 == start_simulation_~tmp~3#1); 11962#L580-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 10654#L328-2 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 10655#L345-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 10606#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 10607#L535 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 10512#L542 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 10513#stop_simulation_returnLabel#1 start_simulation_#t~ret14#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 10662#L593 assume !(0 != start_simulation_~tmp___0~2#1); 10618#L561-2 [2022-12-13 14:11:59,378 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 14:11:59,378 INFO L85 PathProgramCache]: Analyzing trace with hash 1966545068, now seen corresponding path program 2 times [2022-12-13 14:11:59,379 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 14:11:59,379 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1262179760] [2022-12-13 14:11:59,379 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 14:11:59,379 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 14:11:59,386 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 14:11:59,386 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 14:11:59,390 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 14:11:59,395 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 14:11:59,396 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 14:11:59,396 INFO L85 PathProgramCache]: Analyzing trace with hash -1502717854, now seen corresponding path program 1 times [2022-12-13 14:11:59,396 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 14:11:59,396 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1165347414] [2022-12-13 14:11:59,396 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 14:11:59,396 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 14:11:59,402 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 14:11:59,419 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 14:11:59,419 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 14:11:59,419 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1165347414] [2022-12-13 14:11:59,419 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1165347414] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 14:11:59,419 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 14:11:59,419 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 14:11:59,420 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [758888703] [2022-12-13 14:11:59,420 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 14:11:59,420 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 14:11:59,420 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 14:11:59,421 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 14:11:59,421 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 14:11:59,421 INFO L87 Difference]: Start difference. First operand 1512 states and 2061 transitions. cyclomatic complexity: 553 Second operand has 3 states, 3 states have (on average 15.0) internal successors, (45), 3 states have internal predecessors, (45), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 14:11:59,450 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 14:11:59,450 INFO L93 Difference]: Finished difference Result 2343 states and 3154 transitions. [2022-12-13 14:11:59,450 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2343 states and 3154 transitions. [2022-12-13 14:11:59,458 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 2246 [2022-12-13 14:11:59,464 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2343 states to 2343 states and 3154 transitions. [2022-12-13 14:11:59,464 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2343 [2022-12-13 14:11:59,465 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2343 [2022-12-13 14:11:59,465 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2343 states and 3154 transitions. [2022-12-13 14:11:59,467 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 14:11:59,467 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2343 states and 3154 transitions. [2022-12-13 14:11:59,469 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2343 states and 3154 transitions. [2022-12-13 14:11:59,487 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2343 to 2343. [2022-12-13 14:11:59,489 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2343 states, 2343 states have (on average 1.3461374306444729) internal successors, (3154), 2342 states have internal predecessors, (3154), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 14:11:59,493 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2343 states to 2343 states and 3154 transitions. [2022-12-13 14:11:59,493 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2343 states and 3154 transitions. [2022-12-13 14:11:59,493 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 14:11:59,494 INFO L428 stractBuchiCegarLoop]: Abstraction has 2343 states and 3154 transitions. [2022-12-13 14:11:59,494 INFO L335 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2022-12-13 14:11:59,494 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2343 states and 3154 transitions. [2022-12-13 14:11:59,500 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 2246 [2022-12-13 14:11:59,500 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 14:11:59,500 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 14:11:59,500 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 14:11:59,500 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 14:11:59,501 INFO L748 eck$LassoCheckResult]: Stem: 14454#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(12, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~clk~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 14455#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~clk~0 := 0;~max_loop~0 := 8;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1; 14486#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 14477#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 14478#L305 assume 1 == ~P_1_i~0;~P_1_st~0 := 0; 14514#L305-2 assume 1 == ~P_2_i~0;~P_2_st~0 := 0; 14529#L310-1 assume 1 == ~C_1_i~0;~C_1_st~0 := 0; 14530#L315-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 14549#fire_delta_events_returnLabel#1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 14548#L118 assume !(1 == ~P_1_pc~0); 14509#L118-2 is_P_1_triggered_~__retres1~0#1 := 0; 14510#L129 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 14499#is_P_1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 14363#L491 assume !(0 != activate_threads_~tmp~1#1); 14364#L491-2 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 14519#L186 assume !(1 == ~P_2_pc~0); 14384#L186-2 is_P_2_triggered_~__retres1~1#1 := 0; 14385#L197 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 14522#is_P_2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 14495#L499 assume !(0 != activate_threads_~tmp___0~1#1); 14496#L499-2 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 14429#L268 assume !(1 == ~C_1_pc~0); 14430#L268-2 assume !(2 == ~C_1_pc~0); 14559#L278-1 is_C_1_triggered_~__retres1~2#1 := 0; 14468#L289 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 14469#is_C_1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 14431#L507 assume !(0 != activate_threads_~tmp___1~1#1); 14432#L507-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14448#reset_delta_events_returnLabel#1 assume { :end_inline_reset_delta_events } true; 14574#L561-2 assume !false; 16560#L562 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 16443#L397 [2022-12-13 14:11:59,501 INFO L750 eck$LassoCheckResult]: Loop: 16443#L397 assume !false; 16557#L358 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 16554#L328 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 16553#L345 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 16552#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 16546#L362 assume 0 != eval_~tmp___2~0#1; 16525#L362-1 assume 0 == ~P_1_st~0;eval_~tmp~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 14515#L371 assume !(0 != eval_~tmp~0#1); 14517#L367 assume !(0 == ~P_2_st~0); 16447#L382 assume !(0 == ~C_1_st~0); 16443#L397 [2022-12-13 14:11:59,501 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 14:11:59,501 INFO L85 PathProgramCache]: Analyzing trace with hash 64203950, now seen corresponding path program 1 times [2022-12-13 14:11:59,501 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 14:11:59,501 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [183192495] [2022-12-13 14:11:59,501 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 14:11:59,501 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 14:11:59,506 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 14:11:59,506 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 14:11:59,508 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 14:11:59,512 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 14:11:59,512 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 14:11:59,512 INFO L85 PathProgramCache]: Analyzing trace with hash -658300295, now seen corresponding path program 1 times [2022-12-13 14:11:59,512 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 14:11:59,512 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1585758912] [2022-12-13 14:11:59,512 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 14:11:59,513 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 14:11:59,515 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 14:11:59,515 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 14:11:59,516 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 14:11:59,517 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 14:11:59,518 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 14:11:59,518 INFO L85 PathProgramCache]: Analyzing trace with hash -1216570650, now seen corresponding path program 1 times [2022-12-13 14:11:59,518 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 14:11:59,518 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1449250247] [2022-12-13 14:11:59,518 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 14:11:59,518 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 14:11:59,523 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 14:11:59,535 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 14:11:59,535 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 14:11:59,536 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1449250247] [2022-12-13 14:11:59,536 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1449250247] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 14:11:59,536 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 14:11:59,536 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 14:11:59,536 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [820490808] [2022-12-13 14:11:59,536 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 14:11:59,585 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 14:11:59,585 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 14:11:59,586 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 14:11:59,586 INFO L87 Difference]: Start difference. First operand 2343 states and 3154 transitions. cyclomatic complexity: 818 Second operand has 3 states, 3 states have (on average 13.666666666666666) internal successors, (41), 3 states have internal predecessors, (41), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 14:11:59,644 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 14:11:59,644 INFO L93 Difference]: Finished difference Result 3913 states and 5192 transitions. [2022-12-13 14:11:59,644 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3913 states and 5192 transitions. [2022-12-13 14:11:59,673 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 3761 [2022-12-13 14:11:59,705 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3913 states to 3913 states and 5192 transitions. [2022-12-13 14:11:59,705 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3913 [2022-12-13 14:11:59,710 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3913 [2022-12-13 14:11:59,710 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3913 states and 5192 transitions. [2022-12-13 14:11:59,717 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 14:11:59,717 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3913 states and 5192 transitions. [2022-12-13 14:11:59,722 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3913 states and 5192 transitions. [2022-12-13 14:11:59,778 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3913 to 3829. [2022-12-13 14:11:59,786 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3829 states, 3829 states have (on average 1.329328806476887) internal successors, (5090), 3828 states have internal predecessors, (5090), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 14:11:59,799 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3829 states to 3829 states and 5090 transitions. [2022-12-13 14:11:59,799 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3829 states and 5090 transitions. [2022-12-13 14:11:59,800 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 14:11:59,800 INFO L428 stractBuchiCegarLoop]: Abstraction has 3829 states and 5090 transitions. [2022-12-13 14:11:59,800 INFO L335 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2022-12-13 14:11:59,801 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3829 states and 5090 transitions. [2022-12-13 14:11:59,815 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 3677 [2022-12-13 14:11:59,816 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 14:11:59,816 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 14:11:59,816 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 14:11:59,816 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 14:11:59,817 INFO L748 eck$LassoCheckResult]: Stem: 20711#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(12, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~clk~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 20712#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~clk~0 := 0;~max_loop~0 := 8;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1; 20742#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 20732#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 20733#L305 assume 1 == ~P_1_i~0;~P_1_st~0 := 0; 20769#L305-2 assume !(1 == ~P_2_i~0);~P_2_st~0 := 2; 20784#L310-1 assume 1 == ~C_1_i~0;~C_1_st~0 := 0; 20785#L315-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 20804#fire_delta_events_returnLabel#1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 20803#L118 assume !(1 == ~P_1_pc~0); 20764#L118-2 is_P_1_triggered_~__retres1~0#1 := 0; 20765#L129 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 20757#is_P_1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 20625#L491 assume !(0 != activate_threads_~tmp~1#1); 20626#L491-2 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 20773#L186 assume !(1 == ~P_2_pc~0); 20643#L186-2 is_P_2_triggered_~__retres1~1#1 := 0; 20644#L197 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 20776#is_P_2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 20749#L499 assume 0 != activate_threads_~tmp___0~1#1;~P_2_st~0 := 0; 20750#L499-2 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 23082#L268 assume !(1 == ~C_1_pc~0); 23081#L268-2 assume !(2 == ~C_1_pc~0); 23080#L278-1 is_C_1_triggered_~__retres1~2#1 := 0; 23079#L289 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 23078#is_C_1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 23077#L507 assume !(0 != activate_threads_~tmp___1~1#1); 23076#L507-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 23075#reset_delta_events_returnLabel#1 assume { :end_inline_reset_delta_events } true; 23074#L561-2 assume !false; 23065#L562 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 23062#L397 [2022-12-13 14:11:59,817 INFO L750 eck$LassoCheckResult]: Loop: 23062#L397 assume !false; 23058#L358 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 23051#L328 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 23047#L345 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 23043#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 23039#L362 assume 0 != eval_~tmp___2~0#1; 23032#L362-1 assume 0 == ~P_1_st~0;eval_~tmp~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 23009#L371 assume !(0 != eval_~tmp~0#1); 23011#L367 assume 0 == ~P_2_st~0;eval_~tmp___0~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 22155#L386 assume !(0 != eval_~tmp___0~0#1); 22156#L382 assume !(0 == ~C_1_st~0); 23062#L397 [2022-12-13 14:11:59,817 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 14:11:59,817 INFO L85 PathProgramCache]: Analyzing trace with hash -131921874, now seen corresponding path program 1 times [2022-12-13 14:11:59,817 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 14:11:59,817 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1413153614] [2022-12-13 14:11:59,818 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 14:11:59,818 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 14:11:59,824 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 14:11:59,836 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 14:11:59,836 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 14:11:59,836 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1413153614] [2022-12-13 14:11:59,836 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1413153614] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 14:11:59,836 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 14:11:59,836 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 14:11:59,836 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [139999960] [2022-12-13 14:11:59,836 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 14:11:59,837 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 14:11:59,837 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 14:11:59,837 INFO L85 PathProgramCache]: Analyzing trace with hash 1067386761, now seen corresponding path program 1 times [2022-12-13 14:11:59,837 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 14:11:59,837 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1992272970] [2022-12-13 14:11:59,837 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 14:11:59,838 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 14:11:59,841 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 14:11:59,841 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 14:11:59,843 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 14:11:59,845 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 14:11:59,912 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 14:11:59,912 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 14:11:59,912 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 14:11:59,912 INFO L87 Difference]: Start difference. First operand 3829 states and 5090 transitions. cyclomatic complexity: 1268 Second operand has 3 states, 3 states have (on average 10.333333333333334) internal successors, (31), 3 states have internal predecessors, (31), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 14:11:59,925 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 14:11:59,926 INFO L93 Difference]: Finished difference Result 3804 states and 5062 transitions. [2022-12-13 14:11:59,926 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3804 states and 5062 transitions. [2022-12-13 14:11:59,942 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 3677 [2022-12-13 14:11:59,955 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3804 states to 3804 states and 5062 transitions. [2022-12-13 14:11:59,955 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3804 [2022-12-13 14:11:59,958 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3804 [2022-12-13 14:11:59,958 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3804 states and 5062 transitions. [2022-12-13 14:11:59,961 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 14:11:59,962 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3804 states and 5062 transitions. [2022-12-13 14:11:59,966 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3804 states and 5062 transitions. [2022-12-13 14:12:00,001 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3804 to 3804. [2022-12-13 14:12:00,006 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3804 states, 3804 states have (on average 1.3307045215562565) internal successors, (5062), 3803 states have internal predecessors, (5062), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 14:12:00,013 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3804 states to 3804 states and 5062 transitions. [2022-12-13 14:12:00,014 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3804 states and 5062 transitions. [2022-12-13 14:12:00,014 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 14:12:00,014 INFO L428 stractBuchiCegarLoop]: Abstraction has 3804 states and 5062 transitions. [2022-12-13 14:12:00,015 INFO L335 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2022-12-13 14:12:00,015 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3804 states and 5062 transitions. [2022-12-13 14:12:00,035 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 3677 [2022-12-13 14:12:00,035 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 14:12:00,035 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 14:12:00,036 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 14:12:00,036 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 14:12:00,036 INFO L748 eck$LassoCheckResult]: Stem: 28355#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(12, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~clk~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 28356#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~clk~0 := 0;~max_loop~0 := 8;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1; 28386#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 28378#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 28379#L305 assume 1 == ~P_1_i~0;~P_1_st~0 := 0; 28413#L305-2 assume 1 == ~P_2_i~0;~P_2_st~0 := 0; 28428#L310-1 assume 1 == ~C_1_i~0;~C_1_st~0 := 0; 28429#L315-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 28452#fire_delta_events_returnLabel#1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 28451#L118 assume !(1 == ~P_1_pc~0); 28408#L118-2 is_P_1_triggered_~__retres1~0#1 := 0; 28409#L129 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 28400#is_P_1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 28266#L491 assume !(0 != activate_threads_~tmp~1#1); 28267#L491-2 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 28418#L186 assume !(1 == ~P_2_pc~0); 28287#L186-2 is_P_2_triggered_~__retres1~1#1 := 0; 28288#L197 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 28421#is_P_2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 28396#L499 assume !(0 != activate_threads_~tmp___0~1#1); 28397#L499-2 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 28331#L268 assume !(1 == ~C_1_pc~0); 28332#L268-2 assume !(2 == ~C_1_pc~0); 28459#L278-1 is_C_1_triggered_~__retres1~2#1 := 0; 28369#L289 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 28370#is_C_1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 28333#L507 assume !(0 != activate_threads_~tmp___1~1#1); 28334#L507-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 28350#reset_delta_events_returnLabel#1 assume { :end_inline_reset_delta_events } true; 28472#L561-2 assume !false; 31261#L562 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 29909#L397 [2022-12-13 14:12:00,036 INFO L750 eck$LassoCheckResult]: Loop: 29909#L397 assume !false; 31257#L358 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 31255#L328 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 31253#L345 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 31251#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 31249#L362 assume 0 != eval_~tmp___2~0#1; 31247#L362-1 assume 0 == ~P_1_st~0;eval_~tmp~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 31243#L371 assume !(0 != eval_~tmp~0#1); 30732#L367 assume 0 == ~P_2_st~0;eval_~tmp___0~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 30729#L386 assume !(0 != eval_~tmp___0~0#1); 29926#L382 assume !(0 == ~C_1_st~0); 29909#L397 [2022-12-13 14:12:00,036 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 14:12:00,036 INFO L85 PathProgramCache]: Analyzing trace with hash 64203950, now seen corresponding path program 2 times [2022-12-13 14:12:00,037 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 14:12:00,037 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [48897642] [2022-12-13 14:12:00,037 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 14:12:00,037 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 14:12:00,043 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 14:12:00,043 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 14:12:00,046 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 14:12:00,051 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 14:12:00,052 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 14:12:00,052 INFO L85 PathProgramCache]: Analyzing trace with hash 1067386761, now seen corresponding path program 2 times [2022-12-13 14:12:00,052 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 14:12:00,052 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [167525993] [2022-12-13 14:12:00,052 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 14:12:00,052 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 14:12:00,055 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 14:12:00,055 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 14:12:00,057 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 14:12:00,058 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 14:12:00,059 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 14:12:00,059 INFO L85 PathProgramCache]: Analyzing trace with hash 940874940, now seen corresponding path program 1 times [2022-12-13 14:12:00,059 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 14:12:00,059 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [545629372] [2022-12-13 14:12:00,059 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 14:12:00,060 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 14:12:00,066 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 14:12:00,083 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 14:12:00,083 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 14:12:00,083 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [545629372] [2022-12-13 14:12:00,084 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [545629372] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 14:12:00,084 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 14:12:00,084 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-12-13 14:12:00,084 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1985657637] [2022-12-13 14:12:00,084 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 14:12:00,141 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 14:12:00,141 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 14:12:00,141 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 14:12:00,141 INFO L87 Difference]: Start difference. First operand 3804 states and 5062 transitions. cyclomatic complexity: 1265 Second operand has 3 states, 2 states have (on average 21.0) internal successors, (42), 3 states have internal predecessors, (42), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 14:12:00,184 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 14:12:00,184 INFO L93 Difference]: Finished difference Result 6650 states and 8776 transitions. [2022-12-13 14:12:00,184 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6650 states and 8776 transitions. [2022-12-13 14:12:00,204 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 6427 [2022-12-13 14:12:00,221 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6650 states to 6650 states and 8776 transitions. [2022-12-13 14:12:00,221 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6650 [2022-12-13 14:12:00,225 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6650 [2022-12-13 14:12:00,225 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6650 states and 8776 transitions. [2022-12-13 14:12:00,229 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 14:12:00,229 INFO L218 hiAutomatonCegarLoop]: Abstraction has 6650 states and 8776 transitions. [2022-12-13 14:12:00,234 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6650 states and 8776 transitions. [2022-12-13 14:12:00,285 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6650 to 6650. [2022-12-13 14:12:00,292 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6650 states, 6650 states have (on average 1.3196992481203007) internal successors, (8776), 6649 states have internal predecessors, (8776), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 14:12:00,302 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6650 states to 6650 states and 8776 transitions. [2022-12-13 14:12:00,302 INFO L240 hiAutomatonCegarLoop]: Abstraction has 6650 states and 8776 transitions. [2022-12-13 14:12:00,302 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 14:12:00,303 INFO L428 stractBuchiCegarLoop]: Abstraction has 6650 states and 8776 transitions. [2022-12-13 14:12:00,303 INFO L335 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2022-12-13 14:12:00,303 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6650 states and 8776 transitions. [2022-12-13 14:12:00,326 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 6427 [2022-12-13 14:12:00,326 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 14:12:00,326 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 14:12:00,326 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 14:12:00,327 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 14:12:00,327 INFO L748 eck$LassoCheckResult]: Stem: 38817#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(12, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~clk~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 38818#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~clk~0 := 0;~max_loop~0 := 8;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1; 38849#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 38841#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 38842#L305 assume 1 == ~P_1_i~0;~P_1_st~0 := 0; 38877#L305-2 assume 1 == ~P_2_i~0;~P_2_st~0 := 0; 38892#L310-1 assume 1 == ~C_1_i~0;~C_1_st~0 := 0; 38893#L315-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 38915#fire_delta_events_returnLabel#1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 38914#L118 assume !(1 == ~P_1_pc~0); 38872#L118-2 is_P_1_triggered_~__retres1~0#1 := 0; 38873#L129 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 38864#is_P_1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 38728#L491 assume !(0 != activate_threads_~tmp~1#1); 38729#L491-2 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 38883#L186 assume !(1 == ~P_2_pc~0); 38749#L186-2 is_P_2_triggered_~__retres1~1#1 := 0; 38750#L197 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 38886#is_P_2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 38859#L499 assume !(0 != activate_threads_~tmp___0~1#1); 38860#L499-2 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 38795#L268 assume !(1 == ~C_1_pc~0); 38796#L268-2 assume !(2 == ~C_1_pc~0); 38923#L278-1 is_C_1_triggered_~__retres1~2#1 := 0; 38831#L289 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 38832#is_C_1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 38797#L507 assume !(0 != activate_threads_~tmp___1~1#1); 38798#L507-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 38812#reset_delta_events_returnLabel#1 assume { :end_inline_reset_delta_events } true; 38937#L561-2 assume !false; 39850#L562 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 39849#L397 [2022-12-13 14:12:00,327 INFO L750 eck$LassoCheckResult]: Loop: 39849#L397 assume !false; 39848#L358 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 39845#L328 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 39844#L345 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 39843#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 39840#L362 assume 0 != eval_~tmp___2~0#1; 39722#L362-1 assume 0 == ~P_1_st~0;eval_~tmp~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 39723#L371 assume !(0 != eval_~tmp~0#1); 39657#L367 assume 0 == ~P_2_st~0;eval_~tmp___0~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 39602#L386 assume !(0 != eval_~tmp___0~0#1); 39603#L382 assume 0 == ~C_1_st~0;eval_~tmp___1~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 39786#L401 assume !(0 != eval_~tmp___1~0#1); 39849#L397 [2022-12-13 14:12:00,327 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 14:12:00,327 INFO L85 PathProgramCache]: Analyzing trace with hash 64203950, now seen corresponding path program 3 times [2022-12-13 14:12:00,327 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 14:12:00,328 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1680195369] [2022-12-13 14:12:00,328 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 14:12:00,328 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 14:12:00,333 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 14:12:00,333 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 14:12:00,336 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 14:12:00,339 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 14:12:00,340 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 14:12:00,340 INFO L85 PathProgramCache]: Analyzing trace with hash -1270750753, now seen corresponding path program 1 times [2022-12-13 14:12:00,340 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 14:12:00,340 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1978557703] [2022-12-13 14:12:00,340 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 14:12:00,340 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 14:12:00,343 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 14:12:00,343 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 14:12:00,345 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 14:12:00,346 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 14:12:00,346 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 14:12:00,346 INFO L85 PathProgramCache]: Analyzing trace with hash -897649908, now seen corresponding path program 1 times [2022-12-13 14:12:00,347 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 14:12:00,347 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1737994497] [2022-12-13 14:12:00,347 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 14:12:00,347 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 14:12:00,353 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 14:12:00,353 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 14:12:00,356 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 14:12:00,361 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 14:12:01,110 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 14:12:01,111 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 14:12:01,119 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 14:12:01,187 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 13.12 02:12:01 BoogieIcfgContainer [2022-12-13 14:12:01,187 INFO L132 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2022-12-13 14:12:01,187 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2022-12-13 14:12:01,187 INFO L271 PluginConnector]: Initializing Witness Printer... [2022-12-13 14:12:01,187 INFO L275 PluginConnector]: Witness Printer initialized [2022-12-13 14:12:01,188 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.12 02:11:57" (3/4) ... [2022-12-13 14:12:01,190 INFO L134 WitnessPrinter]: Generating witness for non-termination counterexample [2022-12-13 14:12:01,250 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_56720457-c443-4d3f-8e29-b3fb4d49ec52/bin/uautomizer-uyxdKDjOR8/witness.graphml [2022-12-13 14:12:01,250 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2022-12-13 14:12:01,251 INFO L158 Benchmark]: Toolchain (without parser) took 4318.43ms. Allocated memory was 130.0MB in the beginning and 218.1MB in the end (delta: 88.1MB). Free memory was 93.7MB in the beginning and 166.8MB in the end (delta: -73.2MB). Peak memory consumption was 134.6MB. Max. memory is 16.1GB. [2022-12-13 14:12:01,251 INFO L158 Benchmark]: CDTParser took 0.16ms. Allocated memory is still 130.0MB. Free memory was 92.6MB in the beginning and 92.6MB in the end (delta: 24.4kB). There was no memory consumed. Max. memory is 16.1GB. [2022-12-13 14:12:01,251 INFO L158 Benchmark]: CACSL2BoogieTranslator took 276.28ms. Allocated memory is still 130.0MB. Free memory was 93.7MB in the beginning and 79.5MB in the end (delta: 14.1MB). Peak memory consumption was 14.7MB. Max. memory is 16.1GB. [2022-12-13 14:12:01,252 INFO L158 Benchmark]: Boogie Procedure Inliner took 41.73ms. Allocated memory is still 130.0MB. Free memory was 79.5MB in the beginning and 77.0MB in the end (delta: 2.6MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. [2022-12-13 14:12:01,252 INFO L158 Benchmark]: Boogie Preprocessor took 31.98ms. Allocated memory is still 130.0MB. Free memory was 77.0MB in the beginning and 74.3MB in the end (delta: 2.6MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. [2022-12-13 14:12:01,252 INFO L158 Benchmark]: RCFGBuilder took 526.99ms. Allocated memory was 130.0MB in the beginning and 180.4MB in the end (delta: 50.3MB). Free memory was 74.3MB in the beginning and 147.9MB in the end (delta: -73.5MB). Peak memory consumption was 31.6MB. Max. memory is 16.1GB. [2022-12-13 14:12:01,253 INFO L158 Benchmark]: BuchiAutomizer took 3373.61ms. Allocated memory was 180.4MB in the beginning and 218.1MB in the end (delta: 37.7MB). Free memory was 147.7MB in the beginning and 67.1MB in the end (delta: 80.6MB). Peak memory consumption was 118.8MB. Max. memory is 16.1GB. [2022-12-13 14:12:01,253 INFO L158 Benchmark]: Witness Printer took 63.10ms. Allocated memory is still 218.1MB. Free memory was 67.1MB in the beginning and 166.8MB in the end (delta: -99.8MB). Peak memory consumption was 17.7MB. Max. memory is 16.1GB. [2022-12-13 14:12:01,255 INFO L339 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.16ms. Allocated memory is still 130.0MB. Free memory was 92.6MB in the beginning and 92.6MB in the end (delta: 24.4kB). There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 276.28ms. Allocated memory is still 130.0MB. Free memory was 93.7MB in the beginning and 79.5MB in the end (delta: 14.1MB). Peak memory consumption was 14.7MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 41.73ms. Allocated memory is still 130.0MB. Free memory was 79.5MB in the beginning and 77.0MB in the end (delta: 2.6MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. * Boogie Preprocessor took 31.98ms. Allocated memory is still 130.0MB. Free memory was 77.0MB in the beginning and 74.3MB in the end (delta: 2.6MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. * RCFGBuilder took 526.99ms. Allocated memory was 130.0MB in the beginning and 180.4MB in the end (delta: 50.3MB). Free memory was 74.3MB in the beginning and 147.9MB in the end (delta: -73.5MB). Peak memory consumption was 31.6MB. Max. memory is 16.1GB. * BuchiAutomizer took 3373.61ms. Allocated memory was 180.4MB in the beginning and 218.1MB in the end (delta: 37.7MB). Free memory was 147.7MB in the beginning and 67.1MB in the end (delta: 80.6MB). Peak memory consumption was 118.8MB. Max. memory is 16.1GB. * Witness Printer took 63.10ms. Allocated memory is still 218.1MB. Free memory was 67.1MB in the beginning and 166.8MB in the end (delta: -99.8MB). Peak memory consumption was 17.7MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 11 terminating modules (11 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.11 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 6650 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 3.2s and 12 iterations. TraceHistogramMax:1. Analysis of lassos took 1.8s. Construction of modules took 0.2s. Büchi inclusion checks took 0.9s. Highest rank in rank-based complementation 0. Minimization of det autom 11. Minimization of nondet autom 0. Automata minimization 0.4s AutomataMinimizationTime, 11 MinimizatonAttempts, 1602 StatesRemovedByMinimization, 6 NontrivialMinimizations. Non-live state removal took 0.2s Buchi closure took 0.0s. Biggest automaton had -1 states and ocurred in iteration -1. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 3995 SdHoareTripleChecker+Valid, 0.3s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 3995 mSDsluCounter, 6145 SdHoareTripleChecker+Invalid, 0.3s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 3372 mSDsCounter, 115 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 282 IncrementalHoareTripleChecker+Invalid, 397 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 115 mSolverCounterUnsat, 2773 mSDtfsCounter, 282 mSolverCounterSat, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI2 SFLT0 conc2 concLT0 SILN1 SILU0 SILI6 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s InitialAbstractionConstructionTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - LassoShapedNonTerminationArgument [Line: 357]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite program execution. Stem: [L25] int max_loop ; [L26] int clk ; [L27] int num ; [L28] int i ; [L29] int e ; [L30] int timer ; [L31] char data_0 ; [L32] char data_1 ; [L75] int P_1_pc; [L76] int P_1_st ; [L77] int P_1_i ; [L78] int P_1_ev ; [L133] int P_2_pc ; [L134] int P_2_st ; [L135] int P_2_i ; [L136] int P_2_ev ; [L201] int C_1_pc ; [L202] int C_1_st ; [L203] int C_1_i ; [L204] int C_1_ev ; [L205] int C_1_pr ; VAL [C_1_ev=0, C_1_i=0, C_1_pc=0, C_1_pr=0, C_1_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=0, num=0, P_1_ev=0, P_1_i=0, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=0, P_2_pc=0, P_2_st=0, timer=0] [L617] int count ; [L618] int __retres2 ; [L622] num = 0 [L623] i = 0 [L624] clk = 0 [L625] max_loop = 8 [L627] timer = 0 [L628] P_1_pc = 0 [L629] P_2_pc = 0 [L630] C_1_pc = 0 [L632] count = 0 [L633] CALL init_model() [L609] P_1_i = 1 [L610] P_2_i = 1 [L611] C_1_i = 1 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L633] RET init_model() [L634] CALL start_simulation() [L547] int kernel_st ; [L548] int tmp ; [L549] int tmp___0 ; [L553] kernel_st = 0 [L554] FCALL update_channels() [L555] CALL init_threads() [L305] COND TRUE (int )P_1_i == 1 [L306] P_1_st = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L310] COND TRUE (int )P_2_i == 1 [L311] P_2_st = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L315] COND TRUE (int )C_1_i == 1 [L316] C_1_st = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L555] RET init_threads() [L556] FCALL fire_delta_events() [L557] CALL activate_threads() [L483] int tmp ; [L484] int tmp___0 ; [L485] int tmp___1 ; [L489] CALL, EXPR is_P_1_triggered() [L115] int __retres1 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L118] COND FALSE !((int )P_1_pc == 1) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L128] __retres1 = 0 VAL [__retres1=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L130] return (__retres1); VAL [\result=0, __retres1=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L489] RET, EXPR is_P_1_triggered() [L489] tmp = is_P_1_triggered() [L491] COND FALSE !(\read(tmp)) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0, tmp=0] [L497] CALL, EXPR is_P_2_triggered() [L183] int __retres1 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L186] COND FALSE !((int )P_2_pc == 1) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L196] __retres1 = 0 VAL [__retres1=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L198] return (__retres1); VAL [\result=0, __retres1=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L497] RET, EXPR is_P_2_triggered() [L497] tmp___0 = is_P_2_triggered() [L499] COND FALSE !(\read(tmp___0)) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0, tmp=0, tmp___0=0] [L505] CALL, EXPR is_C_1_triggered() [L265] int __retres1 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L268] COND FALSE !((int )C_1_pc == 1) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L278] COND FALSE !((int )C_1_pc == 2) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L288] __retres1 = 0 VAL [__retres1=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L290] return (__retres1); VAL [\result=0, __retres1=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L505] RET, EXPR is_C_1_triggered() [L505] tmp___1 = is_C_1_triggered() [L507] COND FALSE !(\read(tmp___1)) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0, tmp=0, tmp___0=0, tmp___1=0] [L557] RET activate_threads() [L558] FCALL reset_delta_events() [L561] COND TRUE 1 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, kernel_st=0, max_loop=8, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L564] kernel_st = 1 [L565] CALL eval() [L350] int tmp ; [L351] int tmp___0 ; [L352] int tmp___1 ; [L353] int tmp___2 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] Loop: [L357] COND TRUE 1 [L360] CALL, EXPR exists_runnable_thread() [L325] int __retres1 ; [L328] COND TRUE (int )P_1_st == 0 [L329] __retres1 = 1 [L346] return (__retres1); [L360] RET, EXPR exists_runnable_thread() [L360] tmp___2 = exists_runnable_thread() [L362] COND TRUE \read(tmp___2) [L367] COND TRUE (int )P_1_st == 0 [L369] tmp = __VERIFIER_nondet_int() [L371] COND FALSE !(\read(tmp)) [L382] COND TRUE (int )P_2_st == 0 [L384] tmp___0 = __VERIFIER_nondet_int() [L386] COND FALSE !(\read(tmp___0)) [L397] COND TRUE (int )C_1_st == 0 [L399] tmp___1 = __VERIFIER_nondet_int() [L401] COND FALSE !(\read(tmp___1)) End of lasso representation. - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 357]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L25] int max_loop ; [L26] int clk ; [L27] int num ; [L28] int i ; [L29] int e ; [L30] int timer ; [L31] char data_0 ; [L32] char data_1 ; [L75] int P_1_pc; [L76] int P_1_st ; [L77] int P_1_i ; [L78] int P_1_ev ; [L133] int P_2_pc ; [L134] int P_2_st ; [L135] int P_2_i ; [L136] int P_2_ev ; [L201] int C_1_pc ; [L202] int C_1_st ; [L203] int C_1_i ; [L204] int C_1_ev ; [L205] int C_1_pr ; VAL [C_1_ev=0, C_1_i=0, C_1_pc=0, C_1_pr=0, C_1_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=0, num=0, P_1_ev=0, P_1_i=0, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=0, P_2_pc=0, P_2_st=0, timer=0] [L617] int count ; [L618] int __retres2 ; [L622] num = 0 [L623] i = 0 [L624] clk = 0 [L625] max_loop = 8 [L627] timer = 0 [L628] P_1_pc = 0 [L629] P_2_pc = 0 [L630] C_1_pc = 0 [L632] count = 0 [L633] CALL init_model() [L609] P_1_i = 1 [L610] P_2_i = 1 [L611] C_1_i = 1 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L633] RET init_model() [L634] CALL start_simulation() [L547] int kernel_st ; [L548] int tmp ; [L549] int tmp___0 ; [L553] kernel_st = 0 [L554] FCALL update_channels() [L555] CALL init_threads() [L305] COND TRUE (int )P_1_i == 1 [L306] P_1_st = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L310] COND TRUE (int )P_2_i == 1 [L311] P_2_st = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L315] COND TRUE (int )C_1_i == 1 [L316] C_1_st = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L555] RET init_threads() [L556] FCALL fire_delta_events() [L557] CALL activate_threads() [L483] int tmp ; [L484] int tmp___0 ; [L485] int tmp___1 ; [L489] CALL, EXPR is_P_1_triggered() [L115] int __retres1 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L118] COND FALSE !((int )P_1_pc == 1) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L128] __retres1 = 0 VAL [__retres1=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L130] return (__retres1); VAL [\result=0, __retres1=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L489] RET, EXPR is_P_1_triggered() [L489] tmp = is_P_1_triggered() [L491] COND FALSE !(\read(tmp)) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0, tmp=0] [L497] CALL, EXPR is_P_2_triggered() [L183] int __retres1 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L186] COND FALSE !((int )P_2_pc == 1) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L196] __retres1 = 0 VAL [__retres1=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L198] return (__retres1); VAL [\result=0, __retres1=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L497] RET, EXPR is_P_2_triggered() [L497] tmp___0 = is_P_2_triggered() [L499] COND FALSE !(\read(tmp___0)) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0, tmp=0, tmp___0=0] [L505] CALL, EXPR is_C_1_triggered() [L265] int __retres1 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L268] COND FALSE !((int )C_1_pc == 1) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L278] COND FALSE !((int )C_1_pc == 2) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L288] __retres1 = 0 VAL [__retres1=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L290] return (__retres1); VAL [\result=0, __retres1=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L505] RET, EXPR is_C_1_triggered() [L505] tmp___1 = is_C_1_triggered() [L507] COND FALSE !(\read(tmp___1)) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0, tmp=0, tmp___0=0, tmp___1=0] [L557] RET activate_threads() [L558] FCALL reset_delta_events() [L561] COND TRUE 1 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, kernel_st=0, max_loop=8, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L564] kernel_st = 1 [L565] CALL eval() [L350] int tmp ; [L351] int tmp___0 ; [L352] int tmp___1 ; [L353] int tmp___2 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] Loop: [L357] COND TRUE 1 [L360] CALL, EXPR exists_runnable_thread() [L325] int __retres1 ; [L328] COND TRUE (int )P_1_st == 0 [L329] __retres1 = 1 [L346] return (__retres1); [L360] RET, EXPR exists_runnable_thread() [L360] tmp___2 = exists_runnable_thread() [L362] COND TRUE \read(tmp___2) [L367] COND TRUE (int )P_1_st == 0 [L369] tmp = __VERIFIER_nondet_int() [L371] COND FALSE !(\read(tmp)) [L382] COND TRUE (int )P_2_st == 0 [L384] tmp___0 = __VERIFIER_nondet_int() [L386] COND FALSE !(\read(tmp___0)) [L397] COND TRUE (int )C_1_st == 0 [L399] tmp___1 = __VERIFIER_nondet_int() [L401] COND FALSE !(\read(tmp___1)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2022-12-13 14:12:01,307 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_56720457-c443-4d3f-8e29-b3fb4d49ec52/bin/uautomizer-uyxdKDjOR8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Forceful destruction successful, exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)