./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/kundu2.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 2329fc70 Calling Ultimate with: /usr/lib/jvm/java-1.11.0-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1940d455-d36e-4055-833a-5582a5df37b0/bin/uautomizer-uyxdKDjOR8/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1940d455-d36e-4055-833a-5582a5df37b0/bin/uautomizer-uyxdKDjOR8/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1940d455-d36e-4055-833a-5582a5df37b0/bin/uautomizer-uyxdKDjOR8/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1940d455-d36e-4055-833a-5582a5df37b0/bin/uautomizer-uyxdKDjOR8/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/kundu2.cil.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1940d455-d36e-4055-833a-5582a5df37b0/bin/uautomizer-uyxdKDjOR8/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1940d455-d36e-4055-833a-5582a5df37b0/bin/uautomizer-uyxdKDjOR8 --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 87760fc84dfa44e1b5109b35af0fae7e5f68f814afbb1ba90e7b46e4e9e3b4bf --- Real Ultimate output --- [0.001s][warning][os,container] Duplicate cpuset controllers detected. Picking /sys/fs/cgroup/cpuset, skipping /sys/fs/cgroup/cpuset. This is Ultimate 0.2.2-dev-2329fc7 [2022-12-13 12:08:48,673 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-12-13 12:08:48,675 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-12-13 12:08:48,692 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-12-13 12:08:48,693 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-12-13 12:08:48,694 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-12-13 12:08:48,695 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-12-13 12:08:48,696 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-12-13 12:08:48,698 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-12-13 12:08:48,698 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-12-13 12:08:48,699 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-12-13 12:08:48,700 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-12-13 12:08:48,701 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-12-13 12:08:48,701 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-12-13 12:08:48,702 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-12-13 12:08:48,703 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-12-13 12:08:48,704 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-12-13 12:08:48,705 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-12-13 12:08:48,706 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-12-13 12:08:48,708 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-12-13 12:08:48,709 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-12-13 12:08:48,710 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-12-13 12:08:48,710 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-12-13 12:08:48,711 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-12-13 12:08:48,713 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-12-13 12:08:48,713 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-12-13 12:08:48,713 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-12-13 12:08:48,714 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-12-13 12:08:48,714 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-12-13 12:08:48,715 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-12-13 12:08:48,715 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-12-13 12:08:48,715 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-12-13 12:08:48,716 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-12-13 12:08:48,716 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-12-13 12:08:48,717 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-12-13 12:08:48,717 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-12-13 12:08:48,717 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-12-13 12:08:48,718 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-12-13 12:08:48,718 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-12-13 12:08:48,718 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-12-13 12:08:48,719 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-12-13 12:08:48,720 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1940d455-d36e-4055-833a-5582a5df37b0/bin/uautomizer-uyxdKDjOR8/config/svcomp-Termination-32bit-Automizer_Default.epf [2022-12-13 12:08:48,742 INFO L113 SettingsManager]: Loading preferences was successful [2022-12-13 12:08:48,742 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-12-13 12:08:48,743 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-12-13 12:08:48,743 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-12-13 12:08:48,744 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-12-13 12:08:48,744 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-12-13 12:08:48,744 INFO L138 SettingsManager]: * Use SBE=true [2022-12-13 12:08:48,744 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2022-12-13 12:08:48,744 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2022-12-13 12:08:48,762 INFO L138 SettingsManager]: * Use old map elimination=false [2022-12-13 12:08:48,762 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2022-12-13 12:08:48,762 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2022-12-13 12:08:48,762 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2022-12-13 12:08:48,762 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-12-13 12:08:48,763 INFO L138 SettingsManager]: * sizeof long=4 [2022-12-13 12:08:48,763 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2022-12-13 12:08:48,763 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-12-13 12:08:48,763 INFO L138 SettingsManager]: * sizeof POINTER=4 [2022-12-13 12:08:48,763 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-12-13 12:08:48,763 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2022-12-13 12:08:48,764 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2022-12-13 12:08:48,764 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2022-12-13 12:08:48,764 INFO L138 SettingsManager]: * sizeof long double=12 [2022-12-13 12:08:48,764 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-12-13 12:08:48,764 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2022-12-13 12:08:48,764 INFO L138 SettingsManager]: * Use constant arrays=true [2022-12-13 12:08:48,765 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2022-12-13 12:08:48,765 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-12-13 12:08:48,765 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-12-13 12:08:48,765 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-12-13 12:08:48,765 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-12-13 12:08:48,766 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-12-13 12:08:48,766 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1940d455-d36e-4055-833a-5582a5df37b0/bin/uautomizer-uyxdKDjOR8/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1940d455-d36e-4055-833a-5582a5df37b0/bin/uautomizer-uyxdKDjOR8 Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 87760fc84dfa44e1b5109b35af0fae7e5f68f814afbb1ba90e7b46e4e9e3b4bf [2022-12-13 12:08:48,926 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-12-13 12:08:48,942 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-12-13 12:08:48,944 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-12-13 12:08:48,945 INFO L271 PluginConnector]: Initializing CDTParser... [2022-12-13 12:08:48,945 INFO L275 PluginConnector]: CDTParser initialized [2022-12-13 12:08:48,947 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1940d455-d36e-4055-833a-5582a5df37b0/bin/uautomizer-uyxdKDjOR8/../../sv-benchmarks/c/systemc/kundu2.cil.c [2022-12-13 12:08:51,547 INFO L500 CDTParser]: Created temporary CDT project at NULL [2022-12-13 12:08:51,717 INFO L351 CDTParser]: Found 1 translation units. [2022-12-13 12:08:51,717 INFO L172 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1940d455-d36e-4055-833a-5582a5df37b0/sv-benchmarks/c/systemc/kundu2.cil.c [2022-12-13 12:08:51,725 INFO L394 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1940d455-d36e-4055-833a-5582a5df37b0/bin/uautomizer-uyxdKDjOR8/data/96d55a310/9a5ab8eb6c4d4e49b50f5af240975c99/FLAG8688f4d05 [2022-12-13 12:08:51,735 INFO L402 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1940d455-d36e-4055-833a-5582a5df37b0/bin/uautomizer-uyxdKDjOR8/data/96d55a310/9a5ab8eb6c4d4e49b50f5af240975c99 [2022-12-13 12:08:51,737 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-12-13 12:08:51,738 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-12-13 12:08:51,739 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-12-13 12:08:51,739 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-12-13 12:08:51,742 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-12-13 12:08:51,743 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.12 12:08:51" (1/1) ... [2022-12-13 12:08:51,743 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@4956e3d9 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 12:08:51, skipping insertion in model container [2022-12-13 12:08:51,743 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.12 12:08:51" (1/1) ... [2022-12-13 12:08:51,749 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-12-13 12:08:51,768 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-12-13 12:08:51,884 WARN L237 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1940d455-d36e-4055-833a-5582a5df37b0/sv-benchmarks/c/systemc/kundu2.cil.c[636,649] [2022-12-13 12:08:51,938 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-12-13 12:08:51,951 INFO L203 MainTranslator]: Completed pre-run [2022-12-13 12:08:51,960 WARN L237 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1940d455-d36e-4055-833a-5582a5df37b0/sv-benchmarks/c/systemc/kundu2.cil.c[636,649] [2022-12-13 12:08:51,990 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-12-13 12:08:52,007 INFO L208 MainTranslator]: Completed translation [2022-12-13 12:08:52,007 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 12:08:52 WrapperNode [2022-12-13 12:08:52,008 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-12-13 12:08:52,008 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-12-13 12:08:52,009 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-12-13 12:08:52,009 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-12-13 12:08:52,015 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 12:08:52" (1/1) ... [2022-12-13 12:08:52,023 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 12:08:52" (1/1) ... [2022-12-13 12:08:52,056 INFO L138 Inliner]: procedures = 34, calls = 40, calls flagged for inlining = 35, calls inlined = 45, statements flattened = 529 [2022-12-13 12:08:52,056 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-12-13 12:08:52,057 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-12-13 12:08:52,057 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-12-13 12:08:52,057 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-12-13 12:08:52,064 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 12:08:52" (1/1) ... [2022-12-13 12:08:52,064 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 12:08:52" (1/1) ... [2022-12-13 12:08:52,067 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 12:08:52" (1/1) ... [2022-12-13 12:08:52,067 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 12:08:52" (1/1) ... [2022-12-13 12:08:52,075 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 12:08:52" (1/1) ... [2022-12-13 12:08:52,082 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 12:08:52" (1/1) ... [2022-12-13 12:08:52,084 INFO L185 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 12:08:52" (1/1) ... [2022-12-13 12:08:52,086 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 12:08:52" (1/1) ... [2022-12-13 12:08:52,091 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-12-13 12:08:52,092 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-12-13 12:08:52,092 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-12-13 12:08:52,092 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-12-13 12:08:52,093 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 12:08:52" (1/1) ... [2022-12-13 12:08:52,100 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-12-13 12:08:52,111 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1940d455-d36e-4055-833a-5582a5df37b0/bin/uautomizer-uyxdKDjOR8/z3 [2022-12-13 12:08:52,123 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1940d455-d36e-4055-833a-5582a5df37b0/bin/uautomizer-uyxdKDjOR8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-12-13 12:08:52,125 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1940d455-d36e-4055-833a-5582a5df37b0/bin/uautomizer-uyxdKDjOR8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2022-12-13 12:08:52,160 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-12-13 12:08:52,160 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-12-13 12:08:52,160 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-12-13 12:08:52,160 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-12-13 12:08:52,228 INFO L235 CfgBuilder]: Building ICFG [2022-12-13 12:08:52,230 INFO L261 CfgBuilder]: Building CFG for each procedure with an implementation [2022-12-13 12:08:52,566 INFO L276 CfgBuilder]: Performing block encoding [2022-12-13 12:08:52,575 INFO L295 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-12-13 12:08:52,575 INFO L300 CfgBuilder]: Removed 5 assume(true) statements. [2022-12-13 12:08:52,577 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.12 12:08:52 BoogieIcfgContainer [2022-12-13 12:08:52,577 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-12-13 12:08:52,578 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2022-12-13 12:08:52,579 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2022-12-13 12:08:52,581 INFO L275 PluginConnector]: BuchiAutomizer initialized [2022-12-13 12:08:52,582 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-12-13 12:08:52,582 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 13.12 12:08:51" (1/3) ... [2022-12-13 12:08:52,583 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@6aa833af and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 13.12 12:08:52, skipping insertion in model container [2022-12-13 12:08:52,583 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-12-13 12:08:52,583 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 12:08:52" (2/3) ... [2022-12-13 12:08:52,583 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@6aa833af and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 13.12 12:08:52, skipping insertion in model container [2022-12-13 12:08:52,583 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-12-13 12:08:52,583 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.12 12:08:52" (3/3) ... [2022-12-13 12:08:52,585 INFO L332 chiAutomizerObserver]: Analyzing ICFG kundu2.cil.c [2022-12-13 12:08:52,626 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2022-12-13 12:08:52,626 INFO L304 stractBuchiCegarLoop]: Hoare is false [2022-12-13 12:08:52,626 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2022-12-13 12:08:52,626 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2022-12-13 12:08:52,626 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2022-12-13 12:08:52,626 INFO L308 stractBuchiCegarLoop]: Difference is false [2022-12-13 12:08:52,626 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2022-12-13 12:08:52,626 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2022-12-13 12:08:52,630 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 190 states, 189 states have (on average 1.5026455026455026) internal successors, (284), 189 states have internal predecessors, (284), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:08:52,650 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 153 [2022-12-13 12:08:52,650 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:08:52,650 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:08:52,656 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:08:52,656 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:08:52,656 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2022-12-13 12:08:52,657 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 190 states, 189 states have (on average 1.5026455026455026) internal successors, (284), 189 states have internal predecessors, (284), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:08:52,662 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 153 [2022-12-13 12:08:52,662 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:08:52,662 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:08:52,664 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:08:52,664 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:08:52,670 INFO L748 eck$LassoCheckResult]: Stem: 49#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(13, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 66#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~max_loop~0 := 2;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1; 181#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 62#update_channels_returnLabel#1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 150#L304true assume !(1 == ~P_1_i~0);~P_1_st~0 := 2; 142#L304-2true assume 1 == ~P_2_i~0;~P_2_st~0 := 0; 28#L309-1true assume !(1 == ~C_1_i~0);~C_1_st~0 := 2; 90#L314-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 140#fire_delta_events_returnLabel#1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 6#L117true assume !(1 == ~P_1_pc~0); 36#L117-2true is_P_1_triggered_~__retres1~0#1 := 0; 85#L128true is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 79#is_P_1_triggered_returnLabel#1true activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 47#L477true assume 0 != activate_threads_~tmp~1#1;~P_1_st~0 := 0; 127#L477-2true assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 151#L185true assume 1 == ~P_2_pc~0; 98#L186true assume 1 == ~P_2_ev~0;is_P_2_triggered_~__retres1~1#1 := 1; 99#L196true is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 169#is_P_2_triggered_returnLabel#1true activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 143#L485true assume !(0 != activate_threads_~tmp___0~1#1); 7#L485-2true assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 38#L267true assume 1 == ~C_1_pc~0; 34#L268true assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1; 43#L288true is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 177#is_C_1_triggered_returnLabel#1true activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 22#L493true assume !(0 != activate_threads_~tmp___1~1#1); 92#L493-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 166#reset_delta_events_returnLabel#1true assume { :end_inline_reset_delta_events } true; 81#L547-2true [2022-12-13 12:08:52,670 INFO L750 eck$LassoCheckResult]: Loop: 81#L547-2true assume !false; 96#L548true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 136#L396true assume !true; 129#eval_returnLabel#1true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 170#update_channels_returnLabel#2true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 65#fire_delta_events_returnLabel#2true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 57#L117-6true assume !(1 == ~P_1_pc~0); 67#L117-8true is_P_1_triggered_~__retres1~0#1 := 0; 188#L128-2true is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 70#is_P_1_triggered_returnLabel#3true activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 39#L477-6true assume 0 != activate_threads_~tmp~1#1;~P_1_st~0 := 0; 101#L477-8true assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 68#L185-6true assume !(1 == ~P_2_pc~0); 93#L185-8true is_P_2_triggered_~__retres1~1#1 := 0; 176#L196-2true is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 183#is_P_2_triggered_returnLabel#3true activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 77#L485-6true assume 0 != activate_threads_~tmp___0~1#1;~P_2_st~0 := 0; 175#L485-8true assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 128#L267-6true assume 1 == ~C_1_pc~0; 154#L268-2true assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1; 78#L288-2true is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 178#is_C_1_triggered_returnLabel#3true activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 80#L493-6true assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0; 52#L493-8true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 144#reset_delta_events_returnLabel#2true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 162#L327-1true assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 164#L344-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 148#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 165#L566true assume !(0 == start_simulation_~tmp~3#1); 74#L566-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 58#L327-2true assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 118#L344-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 59#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 141#L521true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 72#L528true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 184#stop_simulation_returnLabel#1true start_simulation_#t~ret14#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 15#L579true assume !(0 != start_simulation_~tmp___0~2#1); 81#L547-2true [2022-12-13 12:08:52,674 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:08:52,674 INFO L85 PathProgramCache]: Analyzing trace with hash 1332213672, now seen corresponding path program 1 times [2022-12-13 12:08:52,681 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:08:52,681 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [959324458] [2022-12-13 12:08:52,681 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:08:52,682 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:08:52,754 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:08:52,831 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:08:52,831 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:08:52,831 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [959324458] [2022-12-13 12:08:52,832 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [959324458] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:08:52,832 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:08:52,832 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:08:52,833 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1853380060] [2022-12-13 12:08:52,834 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:08:52,845 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 12:08:52,846 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:08:52,846 INFO L85 PathProgramCache]: Analyzing trace with hash 2012962880, now seen corresponding path program 1 times [2022-12-13 12:08:52,846 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:08:52,846 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1127472304] [2022-12-13 12:08:52,847 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:08:52,847 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:08:52,852 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:08:52,862 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:08:52,862 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:08:52,862 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1127472304] [2022-12-13 12:08:52,863 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1127472304] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:08:52,863 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:08:52,863 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-12-13 12:08:52,863 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1394230013] [2022-12-13 12:08:52,863 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:08:52,864 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:08:52,865 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:08:52,887 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 12:08:52,888 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 12:08:52,890 INFO L87 Difference]: Start difference. First operand has 190 states, 189 states have (on average 1.5026455026455026) internal successors, (284), 189 states have internal predecessors, (284), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 9.333333333333334) internal successors, (28), 3 states have internal predecessors, (28), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:08:52,912 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:08:52,913 INFO L93 Difference]: Finished difference Result 186 states and 268 transitions. [2022-12-13 12:08:52,914 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 186 states and 268 transitions. [2022-12-13 12:08:52,916 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 145 [2022-12-13 12:08:52,919 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 186 states to 178 states and 260 transitions. [2022-12-13 12:08:52,920 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 178 [2022-12-13 12:08:52,921 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 178 [2022-12-13 12:08:52,921 INFO L73 IsDeterministic]: Start isDeterministic. Operand 178 states and 260 transitions. [2022-12-13 12:08:52,922 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:08:52,922 INFO L218 hiAutomatonCegarLoop]: Abstraction has 178 states and 260 transitions. [2022-12-13 12:08:52,934 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 178 states and 260 transitions. [2022-12-13 12:08:52,944 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 178 to 178. [2022-12-13 12:08:52,945 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 178 states, 178 states have (on average 1.4606741573033708) internal successors, (260), 177 states have internal predecessors, (260), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:08:52,946 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 178 states to 178 states and 260 transitions. [2022-12-13 12:08:52,946 INFO L240 hiAutomatonCegarLoop]: Abstraction has 178 states and 260 transitions. [2022-12-13 12:08:52,947 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 12:08:52,951 INFO L428 stractBuchiCegarLoop]: Abstraction has 178 states and 260 transitions. [2022-12-13 12:08:52,951 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2022-12-13 12:08:52,951 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 178 states and 260 transitions. [2022-12-13 12:08:52,953 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 145 [2022-12-13 12:08:52,953 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:08:52,953 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:08:52,954 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:08:52,955 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:08:52,955 INFO L748 eck$LassoCheckResult]: Stem: 475#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(13, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 476#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~max_loop~0 := 2;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1; 499#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 494#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 495#L304 assume 1 == ~P_1_i~0;~P_1_st~0 := 0; 555#L304-2 assume 1 == ~P_2_i~0;~P_2_st~0 := 0; 444#L309-1 assume !(1 == ~C_1_i~0);~C_1_st~0 := 2; 445#L314-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 525#fire_delta_events_returnLabel#1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 394#L117 assume !(1 == ~P_1_pc~0); 395#L117-2 is_P_1_triggered_~__retres1~0#1 := 0; 457#L128 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 516#is_P_1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 472#L477 assume 0 != activate_threads_~tmp~1#1;~P_1_st~0 := 0; 473#L477-2 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 549#L185 assume 1 == ~P_2_pc~0; 531#L186 assume 1 == ~P_2_ev~0;is_P_2_triggered_~__retres1~1#1 := 1; 508#L196 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 532#is_P_2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 556#L485 assume !(0 != activate_threads_~tmp___0~1#1); 399#L485-2 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 400#L267 assume 1 == ~C_1_pc~0; 453#L268 assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1; 454#L288 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 471#is_C_1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 434#L493 assume !(0 != activate_threads_~tmp___1~1#1); 435#L493-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 526#reset_delta_events_returnLabel#1 assume { :end_inline_reset_delta_events } true; 418#L547-2 [2022-12-13 12:08:52,955 INFO L750 eck$LassoCheckResult]: Loop: 418#L547-2 assume !false; 519#L548 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 528#L396 assume !false; 523#L357 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 447#L327 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 408#L344 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 425#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 426#L361 assume !(0 != eval_~tmp___2~0#1); 544#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 552#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 498#fire_delta_events_returnLabel#2 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 488#L117-6 assume !(1 == ~P_1_pc~0); 489#L117-8 is_P_1_triggered_~__retres1~0#1 := 0; 500#L128-2 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 503#is_P_1_triggered_returnLabel#3 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 458#L477-6 assume 0 != activate_threads_~tmp~1#1;~P_1_st~0 := 0; 459#L477-8 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 501#L185-6 assume 1 == ~P_2_pc~0; 404#L186-2 assume 1 == ~P_2_ev~0;is_P_2_triggered_~__retres1~1#1 := 1; 405#L196-2 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 562#is_P_2_triggered_returnLabel#3 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 513#L485-6 assume 0 != activate_threads_~tmp___0~1#1;~P_2_st~0 := 0; 514#L485-8 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 550#L267-6 assume 1 == ~C_1_pc~0; 551#L268-2 assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1; 386#L288-2 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 515#is_C_1_triggered_returnLabel#3 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 517#L493-6 assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0; 478#L493-8 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 479#reset_delta_events_returnLabel#2 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 554#L327-1 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 468#L344-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 557#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 558#L566 assume !(0 == start_simulation_~tmp~3#1); 509#L566-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 484#L327-2 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 481#L344-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 486#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 487#L521 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 505#L528 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 506#stop_simulation_returnLabel#1 start_simulation_#t~ret14#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 417#L579 assume !(0 != start_simulation_~tmp___0~2#1); 418#L547-2 [2022-12-13 12:08:52,956 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:08:52,956 INFO L85 PathProgramCache]: Analyzing trace with hash 1466227178, now seen corresponding path program 1 times [2022-12-13 12:08:52,956 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:08:52,957 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1067979803] [2022-12-13 12:08:52,957 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:08:52,957 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:08:52,970 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:08:53,007 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:08:53,007 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:08:53,007 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1067979803] [2022-12-13 12:08:53,007 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1067979803] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:08:53,008 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:08:53,008 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:08:53,008 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [567066027] [2022-12-13 12:08:53,008 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:08:53,009 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 12:08:53,009 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:08:53,009 INFO L85 PathProgramCache]: Analyzing trace with hash -1396999590, now seen corresponding path program 1 times [2022-12-13 12:08:53,009 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:08:53,010 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1915111742] [2022-12-13 12:08:53,010 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:08:53,010 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:08:53,029 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:08:53,080 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:08:53,080 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:08:53,080 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1915111742] [2022-12-13 12:08:53,080 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1915111742] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:08:53,081 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:08:53,081 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-12-13 12:08:53,081 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1649689334] [2022-12-13 12:08:53,081 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:08:53,081 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:08:53,082 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:08:53,082 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 12:08:53,082 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 12:08:53,083 INFO L87 Difference]: Start difference. First operand 178 states and 260 transitions. cyclomatic complexity: 83 Second operand has 3 states, 3 states have (on average 9.333333333333334) internal successors, (28), 3 states have internal predecessors, (28), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:08:53,100 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:08:53,101 INFO L93 Difference]: Finished difference Result 178 states and 259 transitions. [2022-12-13 12:08:53,101 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 178 states and 259 transitions. [2022-12-13 12:08:53,102 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 145 [2022-12-13 12:08:53,104 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 178 states to 178 states and 259 transitions. [2022-12-13 12:08:53,104 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 178 [2022-12-13 12:08:53,104 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 178 [2022-12-13 12:08:53,105 INFO L73 IsDeterministic]: Start isDeterministic. Operand 178 states and 259 transitions. [2022-12-13 12:08:53,105 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:08:53,106 INFO L218 hiAutomatonCegarLoop]: Abstraction has 178 states and 259 transitions. [2022-12-13 12:08:53,106 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 178 states and 259 transitions. [2022-12-13 12:08:53,111 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 178 to 178. [2022-12-13 12:08:53,112 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 178 states, 178 states have (on average 1.4550561797752808) internal successors, (259), 177 states have internal predecessors, (259), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:08:53,112 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 178 states to 178 states and 259 transitions. [2022-12-13 12:08:53,112 INFO L240 hiAutomatonCegarLoop]: Abstraction has 178 states and 259 transitions. [2022-12-13 12:08:53,113 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 12:08:53,113 INFO L428 stractBuchiCegarLoop]: Abstraction has 178 states and 259 transitions. [2022-12-13 12:08:53,113 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2022-12-13 12:08:53,113 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 178 states and 259 transitions. [2022-12-13 12:08:53,115 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 145 [2022-12-13 12:08:53,115 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:08:53,115 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:08:53,116 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:08:53,116 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:08:53,116 INFO L748 eck$LassoCheckResult]: Stem: 840#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(13, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 841#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~max_loop~0 := 2;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1; 864#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 859#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 860#L304 assume 1 == ~P_1_i~0;~P_1_st~0 := 0; 919#L304-2 assume 1 == ~P_2_i~0;~P_2_st~0 := 0; 807#L309-1 assume 1 == ~C_1_i~0;~C_1_st~0 := 0; 808#L314-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 890#fire_delta_events_returnLabel#1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 759#L117 assume !(1 == ~P_1_pc~0); 760#L117-2 is_P_1_triggered_~__retres1~0#1 := 0; 822#L128 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 881#is_P_1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 837#L477 assume 0 != activate_threads_~tmp~1#1;~P_1_st~0 := 0; 838#L477-2 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 914#L185 assume 1 == ~P_2_pc~0; 895#L186 assume 1 == ~P_2_ev~0;is_P_2_triggered_~__retres1~1#1 := 1; 873#L196 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 896#is_P_2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 920#L485 assume !(0 != activate_threads_~tmp___0~1#1); 762#L485-2 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 763#L267 assume 1 == ~C_1_pc~0; 818#L268 assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1; 819#L288 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 831#is_C_1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 799#L493 assume !(0 != activate_threads_~tmp___1~1#1); 800#L493-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 891#reset_delta_events_returnLabel#1 assume { :end_inline_reset_delta_events } true; 783#L547-2 [2022-12-13 12:08:53,116 INFO L750 eck$LassoCheckResult]: Loop: 783#L547-2 assume !false; 883#L548 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 893#L396 assume !false; 888#L357 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 811#L327 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 773#L344 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 790#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 791#L361 assume !(0 != eval_~tmp___2~0#1); 909#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 917#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 863#fire_delta_events_returnLabel#2 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 849#L117-6 assume !(1 == ~P_1_pc~0); 850#L117-8 is_P_1_triggered_~__retres1~0#1 := 0; 865#L128-2 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 868#is_P_1_triggered_returnLabel#3 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 823#L477-6 assume 0 != activate_threads_~tmp~1#1;~P_1_st~0 := 0; 824#L477-8 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 866#L185-6 assume 1 == ~P_2_pc~0; 769#L186-2 assume 1 == ~P_2_ev~0;is_P_2_triggered_~__retres1~1#1 := 1; 770#L196-2 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 927#is_P_2_triggered_returnLabel#3 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 878#L485-6 assume 0 != activate_threads_~tmp___0~1#1;~P_2_st~0 := 0; 879#L485-8 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 915#L267-6 assume 1 == ~C_1_pc~0; 916#L268-2 assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1; 751#L288-2 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 880#is_C_1_triggered_returnLabel#3 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 882#L493-6 assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0; 843#L493-8 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 844#reset_delta_events_returnLabel#2 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 921#L327-1 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 834#L344-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 922#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 923#L566 assume !(0 == start_simulation_~tmp~3#1); 874#L566-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 852#L327-2 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 846#L344-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 854#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 855#L521 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 870#L528 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 871#stop_simulation_returnLabel#1 start_simulation_#t~ret14#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 782#L579 assume !(0 != start_simulation_~tmp___0~2#1); 783#L547-2 [2022-12-13 12:08:53,117 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:08:53,117 INFO L85 PathProgramCache]: Analyzing trace with hash 1247372460, now seen corresponding path program 1 times [2022-12-13 12:08:53,117 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:08:53,117 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1378796260] [2022-12-13 12:08:53,117 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:08:53,118 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:08:53,125 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:08:53,162 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:08:53,162 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:08:53,163 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1378796260] [2022-12-13 12:08:53,163 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1378796260] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:08:53,163 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:08:53,163 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-12-13 12:08:53,163 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [955268721] [2022-12-13 12:08:53,163 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:08:53,164 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 12:08:53,164 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:08:53,164 INFO L85 PathProgramCache]: Analyzing trace with hash -1396999590, now seen corresponding path program 2 times [2022-12-13 12:08:53,165 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:08:53,165 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1408368565] [2022-12-13 12:08:53,165 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:08:53,165 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:08:53,174 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:08:53,204 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:08:53,204 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:08:53,204 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1408368565] [2022-12-13 12:08:53,204 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1408368565] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:08:53,204 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:08:53,204 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-12-13 12:08:53,205 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [375061890] [2022-12-13 12:08:53,205 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:08:53,205 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:08:53,205 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:08:53,206 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-12-13 12:08:53,206 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-12-13 12:08:53,206 INFO L87 Difference]: Start difference. First operand 178 states and 259 transitions. cyclomatic complexity: 82 Second operand has 5 states, 5 states have (on average 5.6) internal successors, (28), 5 states have internal predecessors, (28), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:08:53,298 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:08:53,298 INFO L93 Difference]: Finished difference Result 480 states and 697 transitions. [2022-12-13 12:08:53,298 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 480 states and 697 transitions. [2022-12-13 12:08:53,301 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 408 [2022-12-13 12:08:53,303 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 480 states to 480 states and 697 transitions. [2022-12-13 12:08:53,303 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 480 [2022-12-13 12:08:53,304 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 480 [2022-12-13 12:08:53,304 INFO L73 IsDeterministic]: Start isDeterministic. Operand 480 states and 697 transitions. [2022-12-13 12:08:53,305 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:08:53,305 INFO L218 hiAutomatonCegarLoop]: Abstraction has 480 states and 697 transitions. [2022-12-13 12:08:53,305 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 480 states and 697 transitions. [2022-12-13 12:08:53,310 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 480 to 190. [2022-12-13 12:08:53,311 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 190 states, 190 states have (on average 1.4263157894736842) internal successors, (271), 189 states have internal predecessors, (271), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:08:53,312 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 190 states to 190 states and 271 transitions. [2022-12-13 12:08:53,312 INFO L240 hiAutomatonCegarLoop]: Abstraction has 190 states and 271 transitions. [2022-12-13 12:08:53,312 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-12-13 12:08:53,312 INFO L428 stractBuchiCegarLoop]: Abstraction has 190 states and 271 transitions. [2022-12-13 12:08:53,313 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2022-12-13 12:08:53,313 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 190 states and 271 transitions. [2022-12-13 12:08:53,314 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 154 [2022-12-13 12:08:53,314 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:08:53,314 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:08:53,315 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:08:53,315 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:08:53,316 INFO L748 eck$LassoCheckResult]: Stem: 1513#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(13, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 1514#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~max_loop~0 := 2;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1; 1537#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1532#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1533#L304 assume 1 == ~P_1_i~0;~P_1_st~0 := 0; 1603#L304-2 assume 1 == ~P_2_i~0;~P_2_st~0 := 0; 1482#L309-1 assume 1 == ~C_1_i~0;~C_1_st~0 := 0; 1483#L314-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1568#fire_delta_events_returnLabel#1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 1432#L117 assume !(1 == ~P_1_pc~0); 1433#L117-2 is_P_1_triggered_~__retres1~0#1 := 0; 1495#L128 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 1564#is_P_1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 1510#L477 assume !(0 != activate_threads_~tmp~1#1); 1511#L477-2 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 1594#L185 assume 1 == ~P_2_pc~0; 1574#L186 assume 1 == ~P_2_ev~0;is_P_2_triggered_~__retres1~1#1 := 1; 1547#L196 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 1575#is_P_2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 1604#L485 assume !(0 != activate_threads_~tmp___0~1#1); 1437#L485-2 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 1438#L267 assume 1 == ~C_1_pc~0; 1491#L268 assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1; 1492#L288 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 1509#is_C_1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1472#L493 assume !(0 != activate_threads_~tmp___1~1#1); 1473#L493-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1569#reset_delta_events_returnLabel#1 assume { :end_inline_reset_delta_events } true; 1456#L547-2 [2022-12-13 12:08:53,316 INFO L750 eck$LassoCheckResult]: Loop: 1456#L547-2 assume !false; 1560#L548 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 1571#L396 assume !false; 1565#L357 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 1484#L327 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 1446#L344 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 1463#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1464#L361 assume !(0 != eval_~tmp___2~0#1); 1587#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1597#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1536#fire_delta_events_returnLabel#2 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 1522#L117-6 assume !(1 == ~P_1_pc~0); 1523#L117-8 is_P_1_triggered_~__retres1~0#1 := 0; 1538#L128-2 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 1612#is_P_1_triggered_returnLabel#3 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 1496#L477-6 assume !(0 != activate_threads_~tmp~1#1); 1497#L477-8 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 1539#L185-6 assume 1 == ~P_2_pc~0; 1442#L186-2 assume 1 == ~P_2_ev~0;is_P_2_triggered_~__retres1~1#1 := 1; 1443#L196-2 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 1611#is_P_2_triggered_returnLabel#3 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 1552#L485-6 assume 0 != activate_threads_~tmp___0~1#1;~P_2_st~0 := 0; 1553#L485-8 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 1595#L267-6 assume 1 == ~C_1_pc~0; 1596#L268-2 assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1; 1424#L288-2 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 1554#is_C_1_triggered_returnLabel#3 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1557#L493-6 assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0; 1516#L493-8 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1517#reset_delta_events_returnLabel#2 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 1602#L327-1 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 1506#L344-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 1605#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 1606#L566 assume !(0 == start_simulation_~tmp~3#1); 1548#L566-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 1525#L327-2 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 1519#L344-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 1527#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 1528#L521 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1544#L528 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1545#stop_simulation_returnLabel#1 start_simulation_#t~ret14#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 1455#L579 assume !(0 != start_simulation_~tmp___0~2#1); 1456#L547-2 [2022-12-13 12:08:53,316 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:08:53,316 INFO L85 PathProgramCache]: Analyzing trace with hash -32491218, now seen corresponding path program 1 times [2022-12-13 12:08:53,317 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:08:53,317 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [736589881] [2022-12-13 12:08:53,317 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:08:53,317 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:08:53,323 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:08:53,349 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:08:53,349 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:08:53,349 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [736589881] [2022-12-13 12:08:53,350 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [736589881] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:08:53,350 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:08:53,350 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2022-12-13 12:08:53,350 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [384838484] [2022-12-13 12:08:53,350 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:08:53,350 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 12:08:53,351 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:08:53,351 INFO L85 PathProgramCache]: Analyzing trace with hash 526228444, now seen corresponding path program 1 times [2022-12-13 12:08:53,351 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:08:53,351 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1310598013] [2022-12-13 12:08:53,351 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:08:53,352 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:08:53,357 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:08:53,405 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:08:53,406 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:08:53,406 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1310598013] [2022-12-13 12:08:53,406 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1310598013] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:08:53,406 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:08:53,406 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-12-13 12:08:53,406 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1905192117] [2022-12-13 12:08:53,407 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:08:53,407 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:08:53,407 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:08:53,407 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 12:08:53,408 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 12:08:53,408 INFO L87 Difference]: Start difference. First operand 190 states and 271 transitions. cyclomatic complexity: 82 Second operand has 4 states, 4 states have (on average 7.0) internal successors, (28), 4 states have internal predecessors, (28), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:08:53,489 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:08:53,489 INFO L93 Difference]: Finished difference Result 475 states and 665 transitions. [2022-12-13 12:08:53,489 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 475 states and 665 transitions. [2022-12-13 12:08:53,493 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 412 [2022-12-13 12:08:53,496 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 475 states to 475 states and 665 transitions. [2022-12-13 12:08:53,497 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 475 [2022-12-13 12:08:53,497 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 475 [2022-12-13 12:08:53,497 INFO L73 IsDeterministic]: Start isDeterministic. Operand 475 states and 665 transitions. [2022-12-13 12:08:53,498 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:08:53,499 INFO L218 hiAutomatonCegarLoop]: Abstraction has 475 states and 665 transitions. [2022-12-13 12:08:53,499 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 475 states and 665 transitions. [2022-12-13 12:08:53,511 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 475 to 433. [2022-12-13 12:08:53,512 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 433 states, 433 states have (on average 1.4087759815242493) internal successors, (610), 432 states have internal predecessors, (610), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:08:53,514 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 433 states to 433 states and 610 transitions. [2022-12-13 12:08:53,514 INFO L240 hiAutomatonCegarLoop]: Abstraction has 433 states and 610 transitions. [2022-12-13 12:08:53,515 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 12:08:53,515 INFO L428 stractBuchiCegarLoop]: Abstraction has 433 states and 610 transitions. [2022-12-13 12:08:53,515 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2022-12-13 12:08:53,515 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 433 states and 610 transitions. [2022-12-13 12:08:53,518 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 396 [2022-12-13 12:08:53,518 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:08:53,518 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:08:53,519 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:08:53,519 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:08:53,520 INFO L748 eck$LassoCheckResult]: Stem: 2190#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(13, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 2191#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~max_loop~0 := 2;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1; 2214#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2208#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2209#L304 assume 1 == ~P_1_i~0;~P_1_st~0 := 0; 2284#L304-2 assume 1 == ~P_2_i~0;~P_2_st~0 := 0; 2156#L309-1 assume 1 == ~C_1_i~0;~C_1_st~0 := 0; 2157#L314-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2245#fire_delta_events_returnLabel#1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 2108#L117 assume !(1 == ~P_1_pc~0); 2109#L117-2 is_P_1_triggered_~__retres1~0#1 := 0; 2171#L128 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 2233#is_P_1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 2187#L477 assume !(0 != activate_threads_~tmp~1#1); 2188#L477-2 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 2274#L185 assume !(1 == ~P_2_pc~0); 2224#L185-2 is_P_2_triggered_~__retres1~1#1 := 0; 2225#L196 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 2253#is_P_2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 2285#L485 assume !(0 != activate_threads_~tmp___0~1#1); 2110#L485-2 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 2111#L267 assume 1 == ~C_1_pc~0; 2167#L268 assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1; 2168#L288 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 2182#is_C_1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 2146#L493 assume !(0 != activate_threads_~tmp___1~1#1); 2147#L493-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2248#reset_delta_events_returnLabel#1 assume { :end_inline_reset_delta_events } true; 2131#L547-2 [2022-12-13 12:08:53,520 INFO L750 eck$LassoCheckResult]: Loop: 2131#L547-2 assume !false; 2235#L548 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 2251#L396 assume !false; 2241#L357 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 2161#L327 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 2121#L344 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 2137#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 2138#L361 assume !(0 != eval_~tmp___2~0#1); 2268#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2278#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2213#fire_delta_events_returnLabel#2 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 2199#L117-6 assume !(1 == ~P_1_pc~0); 2200#L117-8 is_P_1_triggered_~__retres1~0#1 := 0; 2500#L128-2 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 2499#is_P_1_triggered_returnLabel#3 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 2498#L477-6 assume !(0 != activate_threads_~tmp~1#1); 2497#L477-8 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 2496#L185-6 assume !(1 == ~P_2_pc~0); 2494#L185-8 is_P_2_triggered_~__retres1~1#1 := 0; 2491#L196-2 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 2486#is_P_2_triggered_returnLabel#3 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 2482#L485-6 assume 0 != activate_threads_~tmp___0~1#1;~P_2_st~0 := 0; 2475#L485-8 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 2470#L267-6 assume 1 == ~C_1_pc~0; 2290#L268-2 assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1; 2102#L288-2 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 2232#is_C_1_triggered_returnLabel#3 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 2234#L493-6 assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0; 2193#L493-8 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2194#reset_delta_events_returnLabel#2 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 2286#L327-1 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 2185#L344-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 2294#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 2295#L566 assume !(0 == start_simulation_~tmp~3#1); 2296#L566-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 2504#L327-2 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 2501#L344-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 2495#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 2492#L521 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2221#L528 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2222#stop_simulation_returnLabel#1 start_simulation_#t~ret14#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 2130#L579 assume !(0 != start_simulation_~tmp___0~2#1); 2131#L547-2 [2022-12-13 12:08:53,520 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:08:53,521 INFO L85 PathProgramCache]: Analyzing trace with hash -1311815953, now seen corresponding path program 1 times [2022-12-13 12:08:53,521 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:08:53,521 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [85145254] [2022-12-13 12:08:53,521 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:08:53,521 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:08:53,530 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:08:53,557 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:08:53,558 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:08:53,558 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [85145254] [2022-12-13 12:08:53,558 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [85145254] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:08:53,558 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:08:53,558 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2022-12-13 12:08:53,558 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1674728950] [2022-12-13 12:08:53,559 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:08:53,559 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 12:08:53,559 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:08:53,559 INFO L85 PathProgramCache]: Analyzing trace with hash -1531375587, now seen corresponding path program 1 times [2022-12-13 12:08:53,560 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:08:53,560 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [806643945] [2022-12-13 12:08:53,560 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:08:53,560 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:08:53,569 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:08:53,609 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:08:53,609 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:08:53,609 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [806643945] [2022-12-13 12:08:53,609 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [806643945] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:08:53,610 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:08:53,610 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-12-13 12:08:53,610 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [111976910] [2022-12-13 12:08:53,610 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:08:53,610 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:08:53,611 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:08:53,611 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 12:08:53,611 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 12:08:53,611 INFO L87 Difference]: Start difference. First operand 433 states and 610 transitions. cyclomatic complexity: 179 Second operand has 4 states, 4 states have (on average 7.0) internal successors, (28), 4 states have internal predecessors, (28), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:08:53,721 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:08:53,721 INFO L93 Difference]: Finished difference Result 1179 states and 1624 transitions. [2022-12-13 12:08:53,721 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1179 states and 1624 transitions. [2022-12-13 12:08:53,730 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1099 [2022-12-13 12:08:53,736 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1179 states to 1179 states and 1624 transitions. [2022-12-13 12:08:53,737 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1179 [2022-12-13 12:08:53,738 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1179 [2022-12-13 12:08:53,738 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1179 states and 1624 transitions. [2022-12-13 12:08:53,740 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:08:53,740 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1179 states and 1624 transitions. [2022-12-13 12:08:53,742 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1179 states and 1624 transitions. [2022-12-13 12:08:53,759 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1179 to 1120. [2022-12-13 12:08:53,761 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1120 states, 1120 states have (on average 1.3857142857142857) internal successors, (1552), 1119 states have internal predecessors, (1552), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:08:53,765 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1120 states to 1120 states and 1552 transitions. [2022-12-13 12:08:53,766 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1120 states and 1552 transitions. [2022-12-13 12:08:53,766 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 12:08:53,767 INFO L428 stractBuchiCegarLoop]: Abstraction has 1120 states and 1552 transitions. [2022-12-13 12:08:53,767 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2022-12-13 12:08:53,767 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1120 states and 1552 transitions. [2022-12-13 12:08:53,773 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1078 [2022-12-13 12:08:53,773 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:08:53,773 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:08:53,774 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:08:53,774 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:08:53,774 INFO L748 eck$LassoCheckResult]: Stem: 3816#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(13, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 3817#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~max_loop~0 := 2;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1; 3843#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3836#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3837#L304 assume 1 == ~P_1_i~0;~P_1_st~0 := 0; 3922#L304-2 assume 1 == ~P_2_i~0;~P_2_st~0 := 0; 3783#L309-1 assume 1 == ~C_1_i~0;~C_1_st~0 := 0; 3784#L314-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3877#fire_delta_events_returnLabel#1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 3733#L117 assume !(1 == ~P_1_pc~0); 3734#L117-2 is_P_1_triggered_~__retres1~0#1 := 0; 3795#L128 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 3863#is_P_1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 3812#L477 assume !(0 != activate_threads_~tmp~1#1); 3813#L477-2 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 3913#L185 assume !(1 == ~P_2_pc~0); 3853#L185-2 is_P_2_triggered_~__retres1~1#1 := 0; 3854#L196 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 3886#is_P_2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 3923#L485 assume !(0 != activate_threads_~tmp___0~1#1); 3735#L485-2 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 3736#L267 assume !(1 == ~C_1_pc~0); 3796#L267-2 assume 2 == ~C_1_pc~0; 3916#L278 assume 1 == ~C_1_ev~0;is_C_1_triggered_~__retres1~2#1 := 1; 3806#L288 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 3807#is_C_1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 3772#L493 assume !(0 != activate_threads_~tmp___1~1#1); 3773#L493-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3881#reset_delta_events_returnLabel#1 assume { :end_inline_reset_delta_events } true; 3941#L547-2 [2022-12-13 12:08:53,774 INFO L750 eck$LassoCheckResult]: Loop: 3941#L547-2 assume !false; 4698#L548 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 4711#L396 assume !false; 4730#L357 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 4728#L327 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 4726#L344 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 4725#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 4723#L361 assume !(0 != eval_~tmp___2~0#1); 4724#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4840#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4839#fire_delta_events_returnLabel#2 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 4838#L117-6 assume !(1 == ~P_1_pc~0); 4837#L117-8 is_P_1_triggered_~__retres1~0#1 := 0; 4836#L128-2 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 4835#is_P_1_triggered_returnLabel#3 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 4834#L477-6 assume !(0 != activate_threads_~tmp~1#1); 4833#L477-8 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 4831#L185-6 assume !(1 == ~P_2_pc~0); 4829#L185-8 is_P_2_triggered_~__retres1~1#1 := 0; 4827#L196-2 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 4825#is_P_2_triggered_returnLabel#3 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 4823#L485-6 assume 0 != activate_threads_~tmp___0~1#1;~P_2_st~0 := 0; 4821#L485-8 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 4819#L267-6 assume !(1 == ~C_1_pc~0); 4818#L267-8 assume !(2 == ~C_1_pc~0); 4816#L277-5 is_C_1_triggered_~__retres1~2#1 := 0; 4813#L288-2 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 4811#is_C_1_triggered_returnLabel#3 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 4810#L493-6 assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0; 4809#L493-8 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4807#reset_delta_events_returnLabel#2 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 4772#L327-1 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 4766#L344-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 4763#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 4758#L566 assume !(0 == start_simulation_~tmp~3#1); 4754#L566-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 3827#L327-2 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 3822#L344-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 3829#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 3830#L521 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4706#L528 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4703#stop_simulation_returnLabel#1 start_simulation_#t~ret14#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 4704#L579 assume !(0 != start_simulation_~tmp___0~2#1); 3941#L547-2 [2022-12-13 12:08:53,775 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:08:53,775 INFO L85 PathProgramCache]: Analyzing trace with hash -122788309, now seen corresponding path program 1 times [2022-12-13 12:08:53,775 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:08:53,775 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2049984392] [2022-12-13 12:08:53,775 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:08:53,776 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:08:53,783 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:08:53,810 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:08:53,810 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:08:53,810 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2049984392] [2022-12-13 12:08:53,810 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2049984392] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:08:53,811 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:08:53,811 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:08:53,811 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [949262518] [2022-12-13 12:08:53,811 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:08:53,811 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 12:08:53,812 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:08:53,812 INFO L85 PathProgramCache]: Analyzing trace with hash 1212226549, now seen corresponding path program 1 times [2022-12-13 12:08:53,812 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:08:53,812 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1313057640] [2022-12-13 12:08:53,812 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:08:53,812 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:08:53,818 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:08:53,845 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:08:53,845 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:08:53,846 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1313057640] [2022-12-13 12:08:53,846 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1313057640] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:08:53,846 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:08:53,846 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-12-13 12:08:53,846 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [855847622] [2022-12-13 12:08:53,846 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:08:53,847 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:08:53,847 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:08:53,847 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 12:08:53,847 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 12:08:53,847 INFO L87 Difference]: Start difference. First operand 1120 states and 1552 transitions. cyclomatic complexity: 436 Second operand has 3 states, 3 states have (on average 9.666666666666666) internal successors, (29), 3 states have internal predecessors, (29), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:08:53,891 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:08:53,891 INFO L93 Difference]: Finished difference Result 1488 states and 2031 transitions. [2022-12-13 12:08:53,891 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1488 states and 2031 transitions. [2022-12-13 12:08:53,897 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1441 [2022-12-13 12:08:53,901 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1488 states to 1488 states and 2031 transitions. [2022-12-13 12:08:53,901 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1488 [2022-12-13 12:08:53,902 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1488 [2022-12-13 12:08:53,902 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1488 states and 2031 transitions. [2022-12-13 12:08:53,903 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:08:53,904 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1488 states and 2031 transitions. [2022-12-13 12:08:53,905 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1488 states and 2031 transitions. [2022-12-13 12:08:53,916 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1488 to 1464. [2022-12-13 12:08:53,918 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1464 states, 1464 states have (on average 1.3668032786885247) internal successors, (2001), 1463 states have internal predecessors, (2001), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:08:53,930 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1464 states to 1464 states and 2001 transitions. [2022-12-13 12:08:53,931 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1464 states and 2001 transitions. [2022-12-13 12:08:53,931 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 12:08:53,932 INFO L428 stractBuchiCegarLoop]: Abstraction has 1464 states and 2001 transitions. [2022-12-13 12:08:53,932 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2022-12-13 12:08:53,932 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1464 states and 2001 transitions. [2022-12-13 12:08:53,938 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1417 [2022-12-13 12:08:53,938 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:08:53,938 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:08:53,938 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:08:53,939 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:08:53,939 INFO L748 eck$LassoCheckResult]: Stem: 6431#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(13, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 6432#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~max_loop~0 := 2;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1; 6460#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 6453#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6454#L304 assume 1 == ~P_1_i~0;~P_1_st~0 := 0; 6538#L304-2 assume 1 == ~P_2_i~0;~P_2_st~0 := 0; 6397#L309-1 assume 1 == ~C_1_i~0;~C_1_st~0 := 0; 6398#L314-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 6491#fire_delta_events_returnLabel#1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 6350#L117 assume !(1 == ~P_1_pc~0); 6351#L117-2 is_P_1_triggered_~__retres1~0#1 := 0; 6409#L128 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 6480#is_P_1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 6427#L477 assume !(0 != activate_threads_~tmp~1#1); 6428#L477-2 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 6531#L185 assume !(1 == ~P_2_pc~0); 6469#L185-2 is_P_2_triggered_~__retres1~1#1 := 0; 6470#L196 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 6500#is_P_2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 6539#L485 assume !(0 != activate_threads_~tmp___0~1#1); 6352#L485-2 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 6353#L267 assume !(1 == ~C_1_pc~0); 6410#L267-2 assume !(2 == ~C_1_pc~0); 6499#L277-1 is_C_1_triggered_~__retres1~2#1 := 0; 6421#L288 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 6422#is_C_1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 6387#L493 assume !(0 != activate_threads_~tmp___1~1#1); 6388#L493-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6495#reset_delta_events_returnLabel#1 assume { :end_inline_reset_delta_events } true; 6562#L547-2 [2022-12-13 12:08:53,939 INFO L750 eck$LassoCheckResult]: Loop: 6562#L547-2 assume !false; 7723#L548 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 6510#L396 assume !false; 7721#L357 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 7717#L327 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 7715#L344 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 7703#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 7699#L361 assume !(0 != eval_~tmp___2~0#1); 7700#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 7803#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 7802#fire_delta_events_returnLabel#2 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 7801#L117-6 assume !(1 == ~P_1_pc~0); 7800#L117-8 is_P_1_triggered_~__retres1~0#1 := 0; 7799#L128-2 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 7798#is_P_1_triggered_returnLabel#3 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 7773#L477-6 assume !(0 != activate_threads_~tmp~1#1); 7772#L477-8 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 7771#L185-6 assume !(1 == ~P_2_pc~0); 7770#L185-8 is_P_2_triggered_~__retres1~1#1 := 0; 7769#L196-2 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 7768#is_P_2_triggered_returnLabel#3 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 6476#L485-6 assume 0 != activate_threads_~tmp___0~1#1;~P_2_st~0 := 0; 6477#L485-8 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 7665#L267-6 assume !(1 == ~C_1_pc~0); 7757#L267-8 assume !(2 == ~C_1_pc~0); 6524#L277-5 is_C_1_triggered_~__retres1~2#1 := 0; 6478#L288-2 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 6479#is_C_1_triggered_returnLabel#3 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 6481#L493-6 assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0; 6434#L493-8 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6435#reset_delta_events_returnLabel#2 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 7747#L327-1 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 7743#L344-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 6543#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 6544#L566 assume !(0 == start_simulation_~tmp~3#1); 7739#L566-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 7738#L327-2 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 7735#L344-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 7733#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 7728#L521 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 7727#L528 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 7726#stop_simulation_returnLabel#1 start_simulation_#t~ret14#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 7725#L579 assume !(0 != start_simulation_~tmp___0~2#1); 6562#L547-2 [2022-12-13 12:08:53,939 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:08:53,939 INFO L85 PathProgramCache]: Analyzing trace with hash 1966545068, now seen corresponding path program 1 times [2022-12-13 12:08:53,940 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:08:53,940 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1482578160] [2022-12-13 12:08:53,940 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:08:53,940 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:08:53,945 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 12:08:53,945 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 12:08:53,949 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 12:08:53,965 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 12:08:53,966 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:08:53,966 INFO L85 PathProgramCache]: Analyzing trace with hash 1212226549, now seen corresponding path program 2 times [2022-12-13 12:08:53,966 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:08:53,966 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [163970060] [2022-12-13 12:08:53,966 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:08:53,966 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:08:53,972 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:08:53,997 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:08:53,998 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:08:53,998 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [163970060] [2022-12-13 12:08:53,998 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [163970060] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:08:53,998 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:08:53,998 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-12-13 12:08:53,998 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [605675347] [2022-12-13 12:08:53,999 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:08:53,999 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:08:53,999 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:08:53,999 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-12-13 12:08:54,000 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-12-13 12:08:54,000 INFO L87 Difference]: Start difference. First operand 1464 states and 2001 transitions. cyclomatic complexity: 541 Second operand has 5 states, 5 states have (on average 8.6) internal successors, (43), 5 states have internal predecessors, (43), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:08:54,080 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:08:54,080 INFO L93 Difference]: Finished difference Result 2589 states and 3511 transitions. [2022-12-13 12:08:54,080 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2589 states and 3511 transitions. [2022-12-13 12:08:54,090 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2524 [2022-12-13 12:08:54,097 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2589 states to 2589 states and 3511 transitions. [2022-12-13 12:08:54,098 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2589 [2022-12-13 12:08:54,099 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2589 [2022-12-13 12:08:54,099 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2589 states and 3511 transitions. [2022-12-13 12:08:54,102 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:08:54,102 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2589 states and 3511 transitions. [2022-12-13 12:08:54,104 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2589 states and 3511 transitions. [2022-12-13 12:08:54,119 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2589 to 1500. [2022-12-13 12:08:54,121 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1500 states, 1500 states have (on average 1.358) internal successors, (2037), 1499 states have internal predecessors, (2037), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:08:54,123 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1500 states to 1500 states and 2037 transitions. [2022-12-13 12:08:54,124 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1500 states and 2037 transitions. [2022-12-13 12:08:54,124 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2022-12-13 12:08:54,124 INFO L428 stractBuchiCegarLoop]: Abstraction has 1500 states and 2037 transitions. [2022-12-13 12:08:54,124 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2022-12-13 12:08:54,125 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1500 states and 2037 transitions. [2022-12-13 12:08:54,134 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1453 [2022-12-13 12:08:54,134 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:08:54,134 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:08:54,135 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:08:54,135 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:08:54,135 INFO L748 eck$LassoCheckResult]: Stem: 10502#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(13, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 10503#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~max_loop~0 := 2;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1; 10530#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 10523#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 10524#L304 assume 1 == ~P_1_i~0;~P_1_st~0 := 0; 10609#L304-2 assume 1 == ~P_2_i~0;~P_2_st~0 := 0; 10469#L309-1 assume 1 == ~C_1_i~0;~C_1_st~0 := 0; 10470#L314-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 10566#fire_delta_events_returnLabel#1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 10419#L117 assume !(1 == ~P_1_pc~0); 10420#L117-2 is_P_1_triggered_~__retres1~0#1 := 0; 10481#L128 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 10550#is_P_1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 10497#L477 assume !(0 != activate_threads_~tmp~1#1); 10498#L477-2 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 10600#L185 assume !(1 == ~P_2_pc~0); 10540#L185-2 is_P_2_triggered_~__retres1~1#1 := 0; 10541#L196 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 10573#is_P_2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 10610#L485 assume !(0 != activate_threads_~tmp___0~1#1); 10423#L485-2 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 10424#L267 assume !(1 == ~C_1_pc~0); 10484#L267-2 assume !(2 == ~C_1_pc~0); 10571#L277-1 is_C_1_triggered_~__retres1~2#1 := 0; 10495#L288 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 10496#is_C_1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 10456#L493 assume !(0 != activate_threads_~tmp___1~1#1); 10457#L493-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10567#reset_delta_events_returnLabel#1 assume { :end_inline_reset_delta_events } true; 10442#L547-2 [2022-12-13 12:08:54,136 INFO L750 eck$LassoCheckResult]: Loop: 10442#L547-2 assume !false; 10554#L548 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 10570#L396 assume !false; 10562#L357 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 10471#L327 assume !(0 == ~P_1_st~0); 10473#L331 assume !(0 == ~P_2_st~0); 11757#L335 assume !(0 == ~C_1_st~0);exists_runnable_thread_~__retres1~3#1 := 0; 11752#L344 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 11749#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 11745#L361 assume !(0 != eval_~tmp___2~0#1); 11746#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 11911#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 11910#fire_delta_events_returnLabel#2 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 11909#L117-6 assume !(1 == ~P_1_pc~0); 11908#L117-8 is_P_1_triggered_~__retres1~0#1 := 0; 11907#L128-2 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 11906#is_P_1_triggered_returnLabel#3 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 11905#L477-6 assume !(0 != activate_threads_~tmp~1#1); 11904#L477-8 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 11903#L185-6 assume !(1 == ~P_2_pc~0); 11902#L185-8 is_P_2_triggered_~__retres1~1#1 := 0; 11901#L196-2 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 11900#is_P_2_triggered_returnLabel#3 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 11899#L485-6 assume 0 != activate_threads_~tmp___0~1#1;~P_2_st~0 := 0; 11898#L485-8 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 11897#L267-6 assume !(1 == ~C_1_pc~0); 11896#L267-8 assume !(2 == ~C_1_pc~0); 11895#L277-5 is_C_1_triggered_~__retres1~2#1 := 0; 10546#L288-2 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 10547#is_C_1_triggered_returnLabel#3 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 10551#L493-6 assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0; 10552#L493-8 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11852#reset_delta_events_returnLabel#2 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 10624#L327-1 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 10492#L344-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 10611#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 10612#L566 assume !(0 == start_simulation_~tmp~3#1); 10626#L566-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 11844#L327-2 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 10592#L344-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 10593#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 11805#L521 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 10538#L528 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 10539#stop_simulation_returnLabel#1 start_simulation_#t~ret14#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 10441#L579 assume !(0 != start_simulation_~tmp___0~2#1); 10442#L547-2 [2022-12-13 12:08:54,136 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:08:54,136 INFO L85 PathProgramCache]: Analyzing trace with hash 1966545068, now seen corresponding path program 2 times [2022-12-13 12:08:54,136 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:08:54,136 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [309970822] [2022-12-13 12:08:54,136 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:08:54,137 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:08:54,141 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 12:08:54,141 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 12:08:54,144 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 12:08:54,147 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 12:08:54,148 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:08:54,148 INFO L85 PathProgramCache]: Analyzing trace with hash 1972558684, now seen corresponding path program 1 times [2022-12-13 12:08:54,148 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:08:54,148 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [143611848] [2022-12-13 12:08:54,148 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:08:54,148 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:08:54,152 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:08:54,164 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:08:54,164 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:08:54,164 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [143611848] [2022-12-13 12:08:54,164 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [143611848] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:08:54,164 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:08:54,165 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:08:54,165 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1938827031] [2022-12-13 12:08:54,165 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:08:54,165 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:08:54,165 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:08:54,166 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 12:08:54,166 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 12:08:54,166 INFO L87 Difference]: Start difference. First operand 1500 states and 2037 transitions. cyclomatic complexity: 541 Second operand has 3 states, 3 states have (on average 15.0) internal successors, (45), 3 states have internal predecessors, (45), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:08:54,200 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:08:54,200 INFO L93 Difference]: Finished difference Result 2325 states and 3118 transitions. [2022-12-13 12:08:54,200 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2325 states and 3118 transitions. [2022-12-13 12:08:54,208 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 2228 [2022-12-13 12:08:54,215 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2325 states to 2325 states and 3118 transitions. [2022-12-13 12:08:54,215 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2325 [2022-12-13 12:08:54,216 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2325 [2022-12-13 12:08:54,217 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2325 states and 3118 transitions. [2022-12-13 12:08:54,219 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:08:54,219 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2325 states and 3118 transitions. [2022-12-13 12:08:54,221 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2325 states and 3118 transitions. [2022-12-13 12:08:54,251 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2325 to 2325. [2022-12-13 12:08:54,256 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2325 states, 2325 states have (on average 1.3410752688172043) internal successors, (3118), 2324 states have internal predecessors, (3118), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:08:54,264 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2325 states to 2325 states and 3118 transitions. [2022-12-13 12:08:54,264 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2325 states and 3118 transitions. [2022-12-13 12:08:54,264 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 12:08:54,265 INFO L428 stractBuchiCegarLoop]: Abstraction has 2325 states and 3118 transitions. [2022-12-13 12:08:54,265 INFO L335 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2022-12-13 12:08:54,265 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2325 states and 3118 transitions. [2022-12-13 12:08:54,279 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 2228 [2022-12-13 12:08:54,279 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:08:54,279 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:08:54,280 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:08:54,280 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:08:54,280 INFO L748 eck$LassoCheckResult]: Stem: 14335#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(13, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 14336#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~max_loop~0 := 2;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1; 14365#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 14358#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 14359#L304 assume 1 == ~P_1_i~0;~P_1_st~0 := 0; 14448#L304-2 assume 1 == ~P_2_i~0;~P_2_st~0 := 0; 14302#L309-1 assume 1 == ~C_1_i~0;~C_1_st~0 := 0; 14303#L314-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 14399#fire_delta_events_returnLabel#1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 14250#L117 assume !(1 == ~P_1_pc~0); 14251#L117-2 is_P_1_triggered_~__retres1~0#1 := 0; 14312#L128 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 14384#is_P_1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 14330#L477 assume !(0 != activate_threads_~tmp~1#1); 14331#L477-2 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 14437#L185 assume !(1 == ~P_2_pc~0); 14375#L185-2 is_P_2_triggered_~__retres1~1#1 := 0; 14376#L196 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 14407#is_P_2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 14449#L485 assume !(0 != activate_threads_~tmp___0~1#1); 14255#L485-2 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 14256#L267 assume !(1 == ~C_1_pc~0); 14315#L267-2 assume !(2 == ~C_1_pc~0); 14404#L277-1 is_C_1_triggered_~__retres1~2#1 := 0; 14328#L288 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 14329#is_C_1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 14288#L493 assume !(0 != activate_threads_~tmp___1~1#1); 14289#L493-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14400#reset_delta_events_returnLabel#1 assume { :end_inline_reset_delta_events } true; 14467#L547-2 assume !false; 15128#L548 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 15129#L396 [2022-12-13 12:08:54,280 INFO L750 eck$LassoCheckResult]: Loop: 15129#L396 assume !false; 16061#L357 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 16058#L327 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 16056#L344 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 16055#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 16053#L361 assume 0 != eval_~tmp___2~0#1; 16048#L361-1 assume 0 == ~P_1_st~0;eval_~tmp~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 15086#L370 assume !(0 != eval_~tmp~0#1); 15088#L366 assume !(0 == ~P_2_st~0); 16067#L381 assume !(0 == ~C_1_st~0); 15129#L396 [2022-12-13 12:08:54,281 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:08:54,281 INFO L85 PathProgramCache]: Analyzing trace with hash 64203950, now seen corresponding path program 1 times [2022-12-13 12:08:54,281 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:08:54,281 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1332332795] [2022-12-13 12:08:54,281 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:08:54,281 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:08:54,288 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 12:08:54,288 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 12:08:54,292 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 12:08:54,300 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 12:08:54,301 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:08:54,301 INFO L85 PathProgramCache]: Analyzing trace with hash -658300295, now seen corresponding path program 1 times [2022-12-13 12:08:54,301 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:08:54,301 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1752388045] [2022-12-13 12:08:54,301 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:08:54,301 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:08:54,304 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 12:08:54,305 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 12:08:54,306 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 12:08:54,309 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 12:08:54,309 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:08:54,309 INFO L85 PathProgramCache]: Analyzing trace with hash -1216570650, now seen corresponding path program 1 times [2022-12-13 12:08:54,309 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:08:54,309 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1063322834] [2022-12-13 12:08:54,310 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:08:54,310 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:08:54,317 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:08:54,335 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:08:54,335 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:08:54,335 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1063322834] [2022-12-13 12:08:54,335 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1063322834] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:08:54,335 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:08:54,335 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:08:54,335 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1318769031] [2022-12-13 12:08:54,335 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:08:54,400 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:08:54,400 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 12:08:54,401 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 12:08:54,401 INFO L87 Difference]: Start difference. First operand 2325 states and 3118 transitions. cyclomatic complexity: 800 Second operand has 3 states, 3 states have (on average 13.666666666666666) internal successors, (41), 3 states have internal predecessors, (41), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:08:54,436 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:08:54,436 INFO L93 Difference]: Finished difference Result 3877 states and 5120 transitions. [2022-12-13 12:08:54,436 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3877 states and 5120 transitions. [2022-12-13 12:08:54,450 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 3725 [2022-12-13 12:08:54,462 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3877 states to 3877 states and 5120 transitions. [2022-12-13 12:08:54,462 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3877 [2022-12-13 12:08:54,465 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3877 [2022-12-13 12:08:54,465 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3877 states and 5120 transitions. [2022-12-13 12:08:54,468 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:08:54,469 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3877 states and 5120 transitions. [2022-12-13 12:08:54,472 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3877 states and 5120 transitions. [2022-12-13 12:08:54,504 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3877 to 3793. [2022-12-13 12:08:54,508 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3793 states, 3793 states have (on average 1.3229633535460057) internal successors, (5018), 3792 states have internal predecessors, (5018), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:08:54,515 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3793 states to 3793 states and 5018 transitions. [2022-12-13 12:08:54,515 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3793 states and 5018 transitions. [2022-12-13 12:08:54,515 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 12:08:54,516 INFO L428 stractBuchiCegarLoop]: Abstraction has 3793 states and 5018 transitions. [2022-12-13 12:08:54,516 INFO L335 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2022-12-13 12:08:54,516 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3793 states and 5018 transitions. [2022-12-13 12:08:54,527 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 3641 [2022-12-13 12:08:54,527 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:08:54,528 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:08:54,528 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:08:54,528 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:08:54,528 INFO L748 eck$LassoCheckResult]: Stem: 20543#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(13, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 20544#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~max_loop~0 := 2;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1; 20574#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 20567#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 20568#L304 assume 1 == ~P_1_i~0;~P_1_st~0 := 0; 20662#L304-2 assume !(1 == ~P_2_i~0);~P_2_st~0 := 2; 20663#L309-1 assume 1 == ~C_1_i~0;~C_1_st~0 := 0; 23153#L314-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 23152#fire_delta_events_returnLabel#1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 23151#L117 assume !(1 == ~P_1_pc~0); 23150#L117-2 is_P_1_triggered_~__retres1~0#1 := 0; 23149#L128 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 23148#is_P_1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 23147#L477 assume !(0 != activate_threads_~tmp~1#1); 23146#L477-2 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 23145#L185 assume !(1 == ~P_2_pc~0); 23144#L185-2 is_P_2_triggered_~__retres1~1#1 := 0; 23143#L196 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 23142#is_P_2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 23141#L485 assume 0 != activate_threads_~tmp___0~1#1;~P_2_st~0 := 0; 20462#L485-2 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 20463#L267 assume !(1 == ~C_1_pc~0); 20524#L267-2 assume !(2 == ~C_1_pc~0); 20620#L277-1 is_C_1_triggered_~__retres1~2#1 := 0; 20533#L288 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 20534#is_C_1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 20496#L493 assume !(0 != activate_threads_~tmp___1~1#1); 20497#L493-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 20616#reset_delta_events_returnLabel#1 assume { :end_inline_reset_delta_events } true; 20685#L547-2 assume !false; 23503#L548 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 22190#L396 [2022-12-13 12:08:54,528 INFO L750 eck$LassoCheckResult]: Loop: 22190#L396 assume !false; 23164#L357 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 23163#L327 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 23162#L344 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 23160#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 23159#L361 assume 0 != eval_~tmp___2~0#1; 23095#L361-1 assume 0 == ~P_1_st~0;eval_~tmp~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 23096#L370 assume !(0 != eval_~tmp~0#1); 22203#L366 assume 0 == ~P_2_st~0;eval_~tmp___0~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 22204#L385 assume !(0 != eval_~tmp___0~0#1); 22192#L381 assume !(0 == ~C_1_st~0); 22190#L396 [2022-12-13 12:08:54,529 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:08:54,529 INFO L85 PathProgramCache]: Analyzing trace with hash -131921874, now seen corresponding path program 1 times [2022-12-13 12:08:54,529 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:08:54,529 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [882524299] [2022-12-13 12:08:54,529 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:08:54,529 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:08:54,533 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:08:54,543 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:08:54,544 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:08:54,544 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [882524299] [2022-12-13 12:08:54,544 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [882524299] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:08:54,544 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:08:54,544 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:08:54,544 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [864967668] [2022-12-13 12:08:54,544 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:08:54,545 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 12:08:54,545 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:08:54,545 INFO L85 PathProgramCache]: Analyzing trace with hash 1067386761, now seen corresponding path program 1 times [2022-12-13 12:08:54,545 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:08:54,545 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1784096725] [2022-12-13 12:08:54,545 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:08:54,546 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:08:54,549 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 12:08:54,549 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 12:08:54,551 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 12:08:54,553 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 12:08:54,620 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:08:54,621 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 12:08:54,621 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 12:08:54,621 INFO L87 Difference]: Start difference. First operand 3793 states and 5018 transitions. cyclomatic complexity: 1232 Second operand has 3 states, 3 states have (on average 10.333333333333334) internal successors, (31), 3 states have internal predecessors, (31), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:08:54,637 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:08:54,638 INFO L93 Difference]: Finished difference Result 3768 states and 4990 transitions. [2022-12-13 12:08:54,638 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3768 states and 4990 transitions. [2022-12-13 12:08:54,650 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 3641 [2022-12-13 12:08:54,661 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3768 states to 3768 states and 4990 transitions. [2022-12-13 12:08:54,662 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3768 [2022-12-13 12:08:54,664 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3768 [2022-12-13 12:08:54,664 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3768 states and 4990 transitions. [2022-12-13 12:08:54,668 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:08:54,668 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3768 states and 4990 transitions. [2022-12-13 12:08:54,671 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3768 states and 4990 transitions. [2022-12-13 12:08:54,715 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3768 to 3768. [2022-12-13 12:08:54,721 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3768 states, 3768 states have (on average 1.3243099787685775) internal successors, (4990), 3767 states have internal predecessors, (4990), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:08:54,730 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3768 states to 3768 states and 4990 transitions. [2022-12-13 12:08:54,731 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3768 states and 4990 transitions. [2022-12-13 12:08:54,731 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 12:08:54,732 INFO L428 stractBuchiCegarLoop]: Abstraction has 3768 states and 4990 transitions. [2022-12-13 12:08:54,732 INFO L335 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2022-12-13 12:08:54,732 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3768 states and 4990 transitions. [2022-12-13 12:08:54,743 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 3641 [2022-12-13 12:08:54,743 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:08:54,743 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:08:54,744 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:08:54,744 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:08:54,744 INFO L748 eck$LassoCheckResult]: Stem: 28112#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(13, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 28113#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~max_loop~0 := 2;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1; 28142#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 28135#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 28136#L304 assume 1 == ~P_1_i~0;~P_1_st~0 := 0; 28225#L304-2 assume 1 == ~P_2_i~0;~P_2_st~0 := 0; 28078#L309-1 assume 1 == ~C_1_i~0;~C_1_st~0 := 0; 28079#L314-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 28179#fire_delta_events_returnLabel#1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 28027#L117 assume !(1 == ~P_1_pc~0); 28028#L117-2 is_P_1_triggered_~__retres1~0#1 := 0; 28090#L128 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 28163#is_P_1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 28107#L477 assume !(0 != activate_threads_~tmp~1#1); 28108#L477-2 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 28215#L185 assume !(1 == ~P_2_pc~0); 28152#L185-2 is_P_2_triggered_~__retres1~1#1 := 0; 28153#L196 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 28187#is_P_2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 28226#L485 assume !(0 != activate_threads_~tmp___0~1#1); 28032#L485-2 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 28033#L267 assume !(1 == ~C_1_pc~0); 28093#L267-2 assume !(2 == ~C_1_pc~0); 28184#L277-1 is_C_1_triggered_~__retres1~2#1 := 0; 28105#L288 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 28106#is_C_1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 28064#L493 assume !(0 != activate_threads_~tmp___1~1#1); 28065#L493-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 28180#reset_delta_events_returnLabel#1 assume { :end_inline_reset_delta_events } true; 28249#L547-2 assume !false; 30228#L548 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 29958#L396 [2022-12-13 12:08:54,744 INFO L750 eck$LassoCheckResult]: Loop: 29958#L396 assume !false; 30062#L357 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 30055#L327 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 30049#L344 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 30039#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 30040#L361 assume 0 != eval_~tmp___2~0#1; 30509#L361-1 assume 0 == ~P_1_st~0;eval_~tmp~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 30506#L370 assume !(0 != eval_~tmp~0#1); 30504#L366 assume 0 == ~P_2_st~0;eval_~tmp___0~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 30501#L385 assume !(0 != eval_~tmp___0~0#1); 29968#L381 assume !(0 == ~C_1_st~0); 29958#L396 [2022-12-13 12:08:54,744 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:08:54,745 INFO L85 PathProgramCache]: Analyzing trace with hash 64203950, now seen corresponding path program 2 times [2022-12-13 12:08:54,745 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:08:54,745 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1611155748] [2022-12-13 12:08:54,745 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:08:54,745 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:08:54,751 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 12:08:54,751 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 12:08:54,755 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 12:08:54,760 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 12:08:54,761 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:08:54,761 INFO L85 PathProgramCache]: Analyzing trace with hash 1067386761, now seen corresponding path program 2 times [2022-12-13 12:08:54,761 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:08:54,761 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [832234185] [2022-12-13 12:08:54,761 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:08:54,761 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:08:54,764 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 12:08:54,764 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 12:08:54,766 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 12:08:54,768 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 12:08:54,769 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:08:54,769 INFO L85 PathProgramCache]: Analyzing trace with hash 940874940, now seen corresponding path program 1 times [2022-12-13 12:08:54,769 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:08:54,769 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [850871303] [2022-12-13 12:08:54,769 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:08:54,769 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:08:54,776 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:08:54,795 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:08:54,795 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:08:54,796 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [850871303] [2022-12-13 12:08:54,796 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [850871303] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:08:54,796 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:08:54,796 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-12-13 12:08:54,796 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [831141100] [2022-12-13 12:08:54,796 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:08:54,855 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:08:54,856 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 12:08:54,856 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 12:08:54,856 INFO L87 Difference]: Start difference. First operand 3768 states and 4990 transitions. cyclomatic complexity: 1229 Second operand has 3 states, 2 states have (on average 21.0) internal successors, (42), 3 states have internal predecessors, (42), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:08:54,908 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:08:54,908 INFO L93 Difference]: Finished difference Result 6578 states and 8632 transitions. [2022-12-13 12:08:54,908 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6578 states and 8632 transitions. [2022-12-13 12:08:54,934 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 6355 [2022-12-13 12:08:54,962 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6578 states to 6578 states and 8632 transitions. [2022-12-13 12:08:54,962 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6578 [2022-12-13 12:08:54,966 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6578 [2022-12-13 12:08:54,967 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6578 states and 8632 transitions. [2022-12-13 12:08:54,975 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:08:54,976 INFO L218 hiAutomatonCegarLoop]: Abstraction has 6578 states and 8632 transitions. [2022-12-13 12:08:54,983 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6578 states and 8632 transitions. [2022-12-13 12:08:55,079 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6578 to 6578. [2022-12-13 12:08:55,090 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6578 states, 6578 states have (on average 1.3122529644268774) internal successors, (8632), 6577 states have internal predecessors, (8632), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:08:55,109 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6578 states to 6578 states and 8632 transitions. [2022-12-13 12:08:55,109 INFO L240 hiAutomatonCegarLoop]: Abstraction has 6578 states and 8632 transitions. [2022-12-13 12:08:55,110 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 12:08:55,110 INFO L428 stractBuchiCegarLoop]: Abstraction has 6578 states and 8632 transitions. [2022-12-13 12:08:55,111 INFO L335 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2022-12-13 12:08:55,111 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6578 states and 8632 transitions. [2022-12-13 12:08:55,135 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 6355 [2022-12-13 12:08:55,135 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:08:55,135 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:08:55,135 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:08:55,135 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:08:55,135 INFO L748 eck$LassoCheckResult]: Stem: 38462#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(13, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 38463#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~max_loop~0 := 2;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1; 38493#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 38484#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 38485#L304 assume 1 == ~P_1_i~0;~P_1_st~0 := 0; 38582#L304-2 assume 1 == ~P_2_i~0;~P_2_st~0 := 0; 38432#L309-1 assume 1 == ~C_1_i~0;~C_1_st~0 := 0; 38433#L314-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 38532#fire_delta_events_returnLabel#1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 38381#L117 assume !(1 == ~P_1_pc~0); 38382#L117-2 is_P_1_triggered_~__retres1~0#1 := 0; 38443#L128 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 38514#is_P_1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 38458#L477 assume !(0 != activate_threads_~tmp~1#1); 38459#L477-2 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 38570#L185 assume !(1 == ~P_2_pc~0); 38503#L185-2 is_P_2_triggered_~__retres1~1#1 := 0; 38504#L196 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 38541#is_P_2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 38583#L485 assume !(0 != activate_threads_~tmp___0~1#1); 38386#L485-2 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 38387#L267 assume !(1 == ~C_1_pc~0); 38446#L267-2 assume !(2 == ~C_1_pc~0); 38538#L277-1 is_C_1_triggered_~__retres1~2#1 := 0; 38456#L288 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 38457#is_C_1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 38418#L493 assume !(0 != activate_threads_~tmp___1~1#1); 38419#L493-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 38533#reset_delta_events_returnLabel#1 assume { :end_inline_reset_delta_events } true; 38603#L547-2 assume !false; 44241#L548 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 40914#L396 [2022-12-13 12:08:55,136 INFO L750 eck$LassoCheckResult]: Loop: 40914#L396 assume !false; 44240#L357 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 44237#L327 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 44235#L344 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 44233#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 44231#L361 assume 0 != eval_~tmp___2~0#1; 44229#L361-1 assume 0 == ~P_1_st~0;eval_~tmp~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 44227#L370 assume !(0 != eval_~tmp~0#1); 43408#L366 assume 0 == ~P_2_st~0;eval_~tmp___0~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 43404#L385 assume !(0 != eval_~tmp___0~0#1); 43405#L381 assume 0 == ~C_1_st~0;eval_~tmp___1~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 40912#L400 assume !(0 != eval_~tmp___1~0#1); 40914#L396 [2022-12-13 12:08:55,136 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:08:55,136 INFO L85 PathProgramCache]: Analyzing trace with hash 64203950, now seen corresponding path program 3 times [2022-12-13 12:08:55,136 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:08:55,136 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1649068643] [2022-12-13 12:08:55,136 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:08:55,136 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:08:55,141 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 12:08:55,142 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 12:08:55,146 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 12:08:55,154 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 12:08:55,155 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:08:55,155 INFO L85 PathProgramCache]: Analyzing trace with hash -1270750753, now seen corresponding path program 1 times [2022-12-13 12:08:55,155 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:08:55,155 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2007785221] [2022-12-13 12:08:55,155 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:08:55,155 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:08:55,159 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 12:08:55,160 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 12:08:55,162 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 12:08:55,164 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 12:08:55,165 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:08:55,165 INFO L85 PathProgramCache]: Analyzing trace with hash -897649908, now seen corresponding path program 1 times [2022-12-13 12:08:55,165 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:08:55,165 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2082363827] [2022-12-13 12:08:55,166 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:08:55,166 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:08:55,175 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 12:08:55,175 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 12:08:55,181 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 12:08:55,190 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 12:08:55,957 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 12:08:55,957 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 12:08:55,969 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 12:08:56,028 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 13.12 12:08:56 BoogieIcfgContainer [2022-12-13 12:08:56,028 INFO L132 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2022-12-13 12:08:56,029 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2022-12-13 12:08:56,029 INFO L271 PluginConnector]: Initializing Witness Printer... [2022-12-13 12:08:56,029 INFO L275 PluginConnector]: Witness Printer initialized [2022-12-13 12:08:56,029 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.12 12:08:52" (3/4) ... [2022-12-13 12:08:56,031 INFO L134 WitnessPrinter]: Generating witness for non-termination counterexample [2022-12-13 12:08:56,068 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1940d455-d36e-4055-833a-5582a5df37b0/bin/uautomizer-uyxdKDjOR8/witness.graphml [2022-12-13 12:08:56,068 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2022-12-13 12:08:56,069 INFO L158 Benchmark]: Toolchain (without parser) took 4330.47ms. Allocated memory was 161.5MB in the beginning and 234.9MB in the end (delta: 73.4MB). Free memory was 134.9MB in the beginning and 118.0MB in the end (delta: 16.8MB). Peak memory consumption was 91.7MB. Max. memory is 16.1GB. [2022-12-13 12:08:56,069 INFO L158 Benchmark]: CDTParser took 0.18ms. Allocated memory is still 161.5MB. Free memory was 128.8MB in the beginning and 128.6MB in the end (delta: 141.2kB). There was no memory consumed. Max. memory is 16.1GB. [2022-12-13 12:08:56,069 INFO L158 Benchmark]: CACSL2BoogieTranslator took 268.66ms. Allocated memory is still 161.5MB. Free memory was 134.5MB in the beginning and 120.7MB in the end (delta: 13.8MB). Peak memory consumption was 12.6MB. Max. memory is 16.1GB. [2022-12-13 12:08:56,069 INFO L158 Benchmark]: Boogie Procedure Inliner took 47.75ms. Allocated memory is still 161.5MB. Free memory was 120.7MB in the beginning and 118.1MB in the end (delta: 2.6MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2022-12-13 12:08:56,069 INFO L158 Benchmark]: Boogie Preprocessor took 34.14ms. Allocated memory is still 161.5MB. Free memory was 117.7MB in the beginning and 115.6MB in the end (delta: 2.1MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. [2022-12-13 12:08:56,070 INFO L158 Benchmark]: RCFGBuilder took 485.91ms. Allocated memory is still 161.5MB. Free memory was 115.6MB in the beginning and 90.4MB in the end (delta: 25.2MB). Peak memory consumption was 25.2MB. Max. memory is 16.1GB. [2022-12-13 12:08:56,070 INFO L158 Benchmark]: BuchiAutomizer took 3449.82ms. Allocated memory was 161.5MB in the beginning and 234.9MB in the end (delta: 73.4MB). Free memory was 90.4MB in the beginning and 122.2MB in the end (delta: -31.8MB). Peak memory consumption was 43.5MB. Max. memory is 16.1GB. [2022-12-13 12:08:56,070 INFO L158 Benchmark]: Witness Printer took 39.79ms. Allocated memory is still 234.9MB. Free memory was 122.2MB in the beginning and 118.0MB in the end (delta: 4.2MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2022-12-13 12:08:56,071 INFO L339 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.18ms. Allocated memory is still 161.5MB. Free memory was 128.8MB in the beginning and 128.6MB in the end (delta: 141.2kB). There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 268.66ms. Allocated memory is still 161.5MB. Free memory was 134.5MB in the beginning and 120.7MB in the end (delta: 13.8MB). Peak memory consumption was 12.6MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 47.75ms. Allocated memory is still 161.5MB. Free memory was 120.7MB in the beginning and 118.1MB in the end (delta: 2.6MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * Boogie Preprocessor took 34.14ms. Allocated memory is still 161.5MB. Free memory was 117.7MB in the beginning and 115.6MB in the end (delta: 2.1MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. * RCFGBuilder took 485.91ms. Allocated memory is still 161.5MB. Free memory was 115.6MB in the beginning and 90.4MB in the end (delta: 25.2MB). Peak memory consumption was 25.2MB. Max. memory is 16.1GB. * BuchiAutomizer took 3449.82ms. Allocated memory was 161.5MB in the beginning and 234.9MB in the end (delta: 73.4MB). Free memory was 90.4MB in the beginning and 122.2MB in the end (delta: -31.8MB). Peak memory consumption was 43.5MB. Max. memory is 16.1GB. * Witness Printer took 39.79ms. Allocated memory is still 234.9MB. Free memory was 122.2MB in the beginning and 118.0MB in the end (delta: 4.2MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 11 terminating modules (11 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.11 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 6578 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 3.3s and 12 iterations. TraceHistogramMax:1. Analysis of lassos took 1.9s. Construction of modules took 0.2s. Büchi inclusion checks took 1.0s. Highest rank in rank-based complementation 0. Minimization of det autom 11. Minimization of nondet autom 0. Automata minimization 0.4s AutomataMinimizationTime, 11 MinimizatonAttempts, 1588 StatesRemovedByMinimization, 6 NontrivialMinimizations. Non-live state removal took 0.1s Buchi closure took 0.0s. Biggest automaton had -1 states and ocurred in iteration -1. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 3924 SdHoareTripleChecker+Valid, 0.3s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 3924 mSDsluCounter, 6157 SdHoareTripleChecker+Invalid, 0.3s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 3339 mSDsCounter, 115 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 282 IncrementalHoareTripleChecker+Invalid, 397 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 115 mSolverCounterUnsat, 2818 mSDtfsCounter, 282 mSolverCounterSat, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI2 SFLT0 conc2 concLT0 SILN1 SILU0 SILI6 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s InitialAbstractionConstructionTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - LassoShapedNonTerminationArgument [Line: 356]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite program execution. Stem: [L25] int max_loop ; [L26] int num ; [L27] int i ; [L28] int e ; [L29] int timer ; [L30] char data_0 ; [L31] char data_1 ; [L74] int P_1_pc; [L75] int P_1_st ; [L76] int P_1_i ; [L77] int P_1_ev ; [L132] int P_2_pc ; [L133] int P_2_st ; [L134] int P_2_i ; [L135] int P_2_ev ; [L200] int C_1_pc ; [L201] int C_1_st ; [L202] int C_1_i ; [L203] int C_1_ev ; [L204] int C_1_pr ; VAL [C_1_ev=0, C_1_i=0, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=0, num=0, P_1_ev=0, P_1_i=0, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=0, P_2_pc=0, P_2_st=0, timer=0] [L603] int count ; [L604] int __retres2 ; [L608] num = 0 [L609] i = 0 [L610] max_loop = 2 [L612] timer = 0 [L613] P_1_pc = 0 [L614] P_2_pc = 0 [L615] C_1_pc = 0 [L617] count = 0 [L618] CALL init_model() [L595] P_1_i = 1 [L596] P_2_i = 1 [L597] C_1_i = 1 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L618] RET init_model() [L619] CALL start_simulation() [L533] int kernel_st ; [L534] int tmp ; [L535] int tmp___0 ; [L539] kernel_st = 0 [L540] FCALL update_channels() [L541] CALL init_threads() [L304] COND TRUE (int )P_1_i == 1 [L305] P_1_st = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L309] COND TRUE (int )P_2_i == 1 [L310] P_2_st = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L314] COND TRUE (int )C_1_i == 1 [L315] C_1_st = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L541] RET init_threads() [L542] FCALL fire_delta_events() [L543] CALL activate_threads() [L469] int tmp ; [L470] int tmp___0 ; [L471] int tmp___1 ; [L475] CALL, EXPR is_P_1_triggered() [L114] int __retres1 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L117] COND FALSE !((int )P_1_pc == 1) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L127] __retres1 = 0 VAL [__retres1=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L129] return (__retres1); VAL [\result=0, __retres1=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L475] RET, EXPR is_P_1_triggered() [L475] tmp = is_P_1_triggered() [L477] COND FALSE !(\read(tmp)) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0, tmp=0] [L483] CALL, EXPR is_P_2_triggered() [L182] int __retres1 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L185] COND FALSE !((int )P_2_pc == 1) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L195] __retres1 = 0 VAL [__retres1=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L197] return (__retres1); VAL [\result=0, __retres1=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L483] RET, EXPR is_P_2_triggered() [L483] tmp___0 = is_P_2_triggered() [L485] COND FALSE !(\read(tmp___0)) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0, tmp=0, tmp___0=0] [L491] CALL, EXPR is_C_1_triggered() [L264] int __retres1 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L267] COND FALSE !((int )C_1_pc == 1) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L277] COND FALSE !((int )C_1_pc == 2) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L287] __retres1 = 0 VAL [__retres1=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L289] return (__retres1); VAL [\result=0, __retres1=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L491] RET, EXPR is_C_1_triggered() [L491] tmp___1 = is_C_1_triggered() [L493] COND FALSE !(\read(tmp___1)) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0, tmp=0, tmp___0=0, tmp___1=0] [L543] RET activate_threads() [L544] FCALL reset_delta_events() [L547] COND TRUE 1 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, kernel_st=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L550] kernel_st = 1 [L551] CALL eval() [L349] int tmp ; [L350] int tmp___0 ; [L351] int tmp___1 ; [L352] int tmp___2 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] Loop: [L356] COND TRUE 1 [L359] CALL, EXPR exists_runnable_thread() [L324] int __retres1 ; [L327] COND TRUE (int )P_1_st == 0 [L328] __retres1 = 1 [L345] return (__retres1); [L359] RET, EXPR exists_runnable_thread() [L359] tmp___2 = exists_runnable_thread() [L361] COND TRUE \read(tmp___2) [L366] COND TRUE (int )P_1_st == 0 [L368] tmp = __VERIFIER_nondet_int() [L370] COND FALSE !(\read(tmp)) [L381] COND TRUE (int )P_2_st == 0 [L383] tmp___0 = __VERIFIER_nondet_int() [L385] COND FALSE !(\read(tmp___0)) [L396] COND TRUE (int )C_1_st == 0 [L398] tmp___1 = __VERIFIER_nondet_int() [L400] COND FALSE !(\read(tmp___1)) End of lasso representation. - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 356]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L25] int max_loop ; [L26] int num ; [L27] int i ; [L28] int e ; [L29] int timer ; [L30] char data_0 ; [L31] char data_1 ; [L74] int P_1_pc; [L75] int P_1_st ; [L76] int P_1_i ; [L77] int P_1_ev ; [L132] int P_2_pc ; [L133] int P_2_st ; [L134] int P_2_i ; [L135] int P_2_ev ; [L200] int C_1_pc ; [L201] int C_1_st ; [L202] int C_1_i ; [L203] int C_1_ev ; [L204] int C_1_pr ; VAL [C_1_ev=0, C_1_i=0, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=0, num=0, P_1_ev=0, P_1_i=0, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=0, P_2_pc=0, P_2_st=0, timer=0] [L603] int count ; [L604] int __retres2 ; [L608] num = 0 [L609] i = 0 [L610] max_loop = 2 [L612] timer = 0 [L613] P_1_pc = 0 [L614] P_2_pc = 0 [L615] C_1_pc = 0 [L617] count = 0 [L618] CALL init_model() [L595] P_1_i = 1 [L596] P_2_i = 1 [L597] C_1_i = 1 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L618] RET init_model() [L619] CALL start_simulation() [L533] int kernel_st ; [L534] int tmp ; [L535] int tmp___0 ; [L539] kernel_st = 0 [L540] FCALL update_channels() [L541] CALL init_threads() [L304] COND TRUE (int )P_1_i == 1 [L305] P_1_st = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L309] COND TRUE (int )P_2_i == 1 [L310] P_2_st = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L314] COND TRUE (int )C_1_i == 1 [L315] C_1_st = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L541] RET init_threads() [L542] FCALL fire_delta_events() [L543] CALL activate_threads() [L469] int tmp ; [L470] int tmp___0 ; [L471] int tmp___1 ; [L475] CALL, EXPR is_P_1_triggered() [L114] int __retres1 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L117] COND FALSE !((int )P_1_pc == 1) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L127] __retres1 = 0 VAL [__retres1=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L129] return (__retres1); VAL [\result=0, __retres1=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L475] RET, EXPR is_P_1_triggered() [L475] tmp = is_P_1_triggered() [L477] COND FALSE !(\read(tmp)) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0, tmp=0] [L483] CALL, EXPR is_P_2_triggered() [L182] int __retres1 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L185] COND FALSE !((int )P_2_pc == 1) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L195] __retres1 = 0 VAL [__retres1=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L197] return (__retres1); VAL [\result=0, __retres1=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L483] RET, EXPR is_P_2_triggered() [L483] tmp___0 = is_P_2_triggered() [L485] COND FALSE !(\read(tmp___0)) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0, tmp=0, tmp___0=0] [L491] CALL, EXPR is_C_1_triggered() [L264] int __retres1 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L267] COND FALSE !((int )C_1_pc == 1) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L277] COND FALSE !((int )C_1_pc == 2) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L287] __retres1 = 0 VAL [__retres1=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L289] return (__retres1); VAL [\result=0, __retres1=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L491] RET, EXPR is_C_1_triggered() [L491] tmp___1 = is_C_1_triggered() [L493] COND FALSE !(\read(tmp___1)) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0, tmp=0, tmp___0=0, tmp___1=0] [L543] RET activate_threads() [L544] FCALL reset_delta_events() [L547] COND TRUE 1 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, kernel_st=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L550] kernel_st = 1 [L551] CALL eval() [L349] int tmp ; [L350] int tmp___0 ; [L351] int tmp___1 ; [L352] int tmp___2 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] Loop: [L356] COND TRUE 1 [L359] CALL, EXPR exists_runnable_thread() [L324] int __retres1 ; [L327] COND TRUE (int )P_1_st == 0 [L328] __retres1 = 1 [L345] return (__retres1); [L359] RET, EXPR exists_runnable_thread() [L359] tmp___2 = exists_runnable_thread() [L361] COND TRUE \read(tmp___2) [L366] COND TRUE (int )P_1_st == 0 [L368] tmp = __VERIFIER_nondet_int() [L370] COND FALSE !(\read(tmp)) [L381] COND TRUE (int )P_2_st == 0 [L383] tmp___0 = __VERIFIER_nondet_int() [L385] COND FALSE !(\read(tmp___0)) [L396] COND TRUE (int )C_1_st == 0 [L398] tmp___1 = __VERIFIER_nondet_int() [L400] COND FALSE !(\read(tmp___1)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2022-12-13 12:08:56,109 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1940d455-d36e-4055-833a-5582a5df37b0/bin/uautomizer-uyxdKDjOR8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Forceful destruction successful, exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)