./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/pc_sfifo_3.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 2329fc70 Calling Ultimate with: /usr/lib/jvm/java-1.11.0-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6c7f58a-a15b-42a2-a692-424aa31a7513/bin/uautomizer-uyxdKDjOR8/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6c7f58a-a15b-42a2-a692-424aa31a7513/bin/uautomizer-uyxdKDjOR8/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6c7f58a-a15b-42a2-a692-424aa31a7513/bin/uautomizer-uyxdKDjOR8/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6c7f58a-a15b-42a2-a692-424aa31a7513/bin/uautomizer-uyxdKDjOR8/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/pc_sfifo_3.cil.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6c7f58a-a15b-42a2-a692-424aa31a7513/bin/uautomizer-uyxdKDjOR8/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6c7f58a-a15b-42a2-a692-424aa31a7513/bin/uautomizer-uyxdKDjOR8 --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 677126e8d6773c92cc337bfe0a3ec155f49f784424155f33a8c9c24ee0a42113 --- Real Ultimate output --- [0.001s][warning][os,container] Duplicate cpuset controllers detected. Picking /sys/fs/cgroup/cpuset, skipping /sys/fs/cgroup/cpuset. This is Ultimate 0.2.2-dev-2329fc7 [2022-12-13 16:54:35,266 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-12-13 16:54:35,267 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-12-13 16:54:35,285 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-12-13 16:54:35,286 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-12-13 16:54:35,287 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-12-13 16:54:35,288 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-12-13 16:54:35,290 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-12-13 16:54:35,291 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-12-13 16:54:35,292 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-12-13 16:54:35,293 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-12-13 16:54:35,294 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-12-13 16:54:35,294 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-12-13 16:54:35,295 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-12-13 16:54:35,296 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-12-13 16:54:35,297 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-12-13 16:54:35,298 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-12-13 16:54:35,299 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-12-13 16:54:35,300 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-12-13 16:54:35,302 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-12-13 16:54:35,303 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-12-13 16:54:35,304 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-12-13 16:54:35,305 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-12-13 16:54:35,306 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-12-13 16:54:35,310 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-12-13 16:54:35,310 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-12-13 16:54:35,310 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-12-13 16:54:35,311 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-12-13 16:54:35,311 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-12-13 16:54:35,312 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-12-13 16:54:35,313 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-12-13 16:54:35,313 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-12-13 16:54:35,314 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-12-13 16:54:35,314 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-12-13 16:54:35,315 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-12-13 16:54:35,316 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-12-13 16:54:35,316 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-12-13 16:54:35,316 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-12-13 16:54:35,316 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-12-13 16:54:35,317 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-12-13 16:54:35,318 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-12-13 16:54:35,318 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6c7f58a-a15b-42a2-a692-424aa31a7513/bin/uautomizer-uyxdKDjOR8/config/svcomp-Termination-32bit-Automizer_Default.epf [2022-12-13 16:54:35,339 INFO L113 SettingsManager]: Loading preferences was successful [2022-12-13 16:54:35,340 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-12-13 16:54:35,340 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-12-13 16:54:35,340 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-12-13 16:54:35,341 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-12-13 16:54:35,341 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-12-13 16:54:35,341 INFO L138 SettingsManager]: * Use SBE=true [2022-12-13 16:54:35,341 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2022-12-13 16:54:35,342 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2022-12-13 16:54:35,342 INFO L138 SettingsManager]: * Use old map elimination=false [2022-12-13 16:54:35,342 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2022-12-13 16:54:35,342 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2022-12-13 16:54:35,342 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2022-12-13 16:54:35,342 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-12-13 16:54:35,343 INFO L138 SettingsManager]: * sizeof long=4 [2022-12-13 16:54:35,343 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2022-12-13 16:54:35,343 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-12-13 16:54:35,343 INFO L138 SettingsManager]: * sizeof POINTER=4 [2022-12-13 16:54:35,343 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-12-13 16:54:35,343 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2022-12-13 16:54:35,343 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2022-12-13 16:54:35,343 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2022-12-13 16:54:35,343 INFO L138 SettingsManager]: * sizeof long double=12 [2022-12-13 16:54:35,344 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-12-13 16:54:35,344 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2022-12-13 16:54:35,344 INFO L138 SettingsManager]: * Use constant arrays=true [2022-12-13 16:54:35,344 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2022-12-13 16:54:35,344 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-12-13 16:54:35,344 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-12-13 16:54:35,345 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-12-13 16:54:35,345 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-12-13 16:54:35,345 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-12-13 16:54:35,346 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6c7f58a-a15b-42a2-a692-424aa31a7513/bin/uautomizer-uyxdKDjOR8/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6c7f58a-a15b-42a2-a692-424aa31a7513/bin/uautomizer-uyxdKDjOR8 Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 677126e8d6773c92cc337bfe0a3ec155f49f784424155f33a8c9c24ee0a42113 [2022-12-13 16:54:35,536 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-12-13 16:54:35,553 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-12-13 16:54:35,556 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-12-13 16:54:35,557 INFO L271 PluginConnector]: Initializing CDTParser... [2022-12-13 16:54:35,557 INFO L275 PluginConnector]: CDTParser initialized [2022-12-13 16:54:35,558 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6c7f58a-a15b-42a2-a692-424aa31a7513/bin/uautomizer-uyxdKDjOR8/../../sv-benchmarks/c/systemc/pc_sfifo_3.cil.c [2022-12-13 16:54:38,106 INFO L500 CDTParser]: Created temporary CDT project at NULL [2022-12-13 16:54:38,271 INFO L351 CDTParser]: Found 1 translation units. [2022-12-13 16:54:38,272 INFO L172 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6c7f58a-a15b-42a2-a692-424aa31a7513/sv-benchmarks/c/systemc/pc_sfifo_3.cil.c [2022-12-13 16:54:38,277 INFO L394 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6c7f58a-a15b-42a2-a692-424aa31a7513/bin/uautomizer-uyxdKDjOR8/data/5ff269fe8/5c967533d74446e8b0ae763e9a8aa483/FLAGb0a198097 [2022-12-13 16:54:38,672 INFO L402 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6c7f58a-a15b-42a2-a692-424aa31a7513/bin/uautomizer-uyxdKDjOR8/data/5ff269fe8/5c967533d74446e8b0ae763e9a8aa483 [2022-12-13 16:54:38,674 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-12-13 16:54:38,675 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-12-13 16:54:38,676 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-12-13 16:54:38,677 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-12-13 16:54:38,680 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-12-13 16:54:38,680 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.12 04:54:38" (1/1) ... [2022-12-13 16:54:38,681 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@301e9616 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 04:54:38, skipping insertion in model container [2022-12-13 16:54:38,681 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.12 04:54:38" (1/1) ... [2022-12-13 16:54:38,687 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-12-13 16:54:38,707 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-12-13 16:54:38,802 WARN L237 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6c7f58a-a15b-42a2-a692-424aa31a7513/sv-benchmarks/c/systemc/pc_sfifo_3.cil.c[640,653] [2022-12-13 16:54:38,834 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-12-13 16:54:38,844 INFO L203 MainTranslator]: Completed pre-run [2022-12-13 16:54:38,852 WARN L237 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6c7f58a-a15b-42a2-a692-424aa31a7513/sv-benchmarks/c/systemc/pc_sfifo_3.cil.c[640,653] [2022-12-13 16:54:38,868 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-12-13 16:54:38,879 INFO L208 MainTranslator]: Completed translation [2022-12-13 16:54:38,879 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 04:54:38 WrapperNode [2022-12-13 16:54:38,879 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-12-13 16:54:38,880 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-12-13 16:54:38,880 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-12-13 16:54:38,880 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-12-13 16:54:38,885 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 04:54:38" (1/1) ... [2022-12-13 16:54:38,890 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 04:54:38" (1/1) ... [2022-12-13 16:54:38,908 INFO L138 Inliner]: procedures = 31, calls = 35, calls flagged for inlining = 30, calls inlined = 33, statements flattened = 406 [2022-12-13 16:54:38,908 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-12-13 16:54:38,909 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-12-13 16:54:38,909 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-12-13 16:54:38,909 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-12-13 16:54:38,915 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 04:54:38" (1/1) ... [2022-12-13 16:54:38,915 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 04:54:38" (1/1) ... [2022-12-13 16:54:38,916 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 04:54:38" (1/1) ... [2022-12-13 16:54:38,917 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 04:54:38" (1/1) ... [2022-12-13 16:54:38,920 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 04:54:38" (1/1) ... [2022-12-13 16:54:38,924 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 04:54:38" (1/1) ... [2022-12-13 16:54:38,925 INFO L185 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 04:54:38" (1/1) ... [2022-12-13 16:54:38,926 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 04:54:38" (1/1) ... [2022-12-13 16:54:38,928 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-12-13 16:54:38,929 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-12-13 16:54:38,929 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-12-13 16:54:38,929 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-12-13 16:54:38,930 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 04:54:38" (1/1) ... [2022-12-13 16:54:38,935 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-12-13 16:54:38,943 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6c7f58a-a15b-42a2-a692-424aa31a7513/bin/uautomizer-uyxdKDjOR8/z3 [2022-12-13 16:54:38,952 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6c7f58a-a15b-42a2-a692-424aa31a7513/bin/uautomizer-uyxdKDjOR8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-12-13 16:54:38,954 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6c7f58a-a15b-42a2-a692-424aa31a7513/bin/uautomizer-uyxdKDjOR8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2022-12-13 16:54:38,985 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-12-13 16:54:38,985 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-12-13 16:54:38,985 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-12-13 16:54:38,985 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-12-13 16:54:39,042 INFO L235 CfgBuilder]: Building ICFG [2022-12-13 16:54:39,043 INFO L261 CfgBuilder]: Building CFG for each procedure with an implementation [2022-12-13 16:54:39,368 INFO L769 $ProcedureCfgBuilder]: dead code at ProgramPoint $Ultimate##104: assume 1 == ~q_free~0;~c_dr_st~0 := 2;~c_dr_pc~0 := 2;~a_t~0 := do_read_c_~a~0#1; [2022-12-13 16:54:39,369 INFO L769 $ProcedureCfgBuilder]: dead code at ProgramPoint $Ultimate##105: assume !(1 == ~q_free~0); [2022-12-13 16:54:39,369 INFO L276 CfgBuilder]: Performing block encoding [2022-12-13 16:54:39,376 INFO L295 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-12-13 16:54:39,377 INFO L300 CfgBuilder]: Removed 4 assume(true) statements. [2022-12-13 16:54:39,379 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.12 04:54:39 BoogieIcfgContainer [2022-12-13 16:54:39,379 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-12-13 16:54:39,380 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2022-12-13 16:54:39,380 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2022-12-13 16:54:39,384 INFO L275 PluginConnector]: BuchiAutomizer initialized [2022-12-13 16:54:39,385 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-12-13 16:54:39,385 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 13.12 04:54:38" (1/3) ... [2022-12-13 16:54:39,386 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@1345ce3 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 13.12 04:54:39, skipping insertion in model container [2022-12-13 16:54:39,386 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-12-13 16:54:39,386 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 04:54:38" (2/3) ... [2022-12-13 16:54:39,386 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@1345ce3 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 13.12 04:54:39, skipping insertion in model container [2022-12-13 16:54:39,386 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-12-13 16:54:39,386 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.12 04:54:39" (3/3) ... [2022-12-13 16:54:39,388 INFO L332 chiAutomizerObserver]: Analyzing ICFG pc_sfifo_3.cil.c [2022-12-13 16:54:39,441 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2022-12-13 16:54:39,441 INFO L304 stractBuchiCegarLoop]: Hoare is false [2022-12-13 16:54:39,441 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2022-12-13 16:54:39,441 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2022-12-13 16:54:39,441 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2022-12-13 16:54:39,441 INFO L308 stractBuchiCegarLoop]: Difference is false [2022-12-13 16:54:39,442 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2022-12-13 16:54:39,447 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2022-12-13 16:54:39,451 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 142 states, 141 states have (on average 1.5602836879432624) internal successors, (220), 141 states have internal predecessors, (220), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 16:54:39,471 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 102 [2022-12-13 16:54:39,471 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 16:54:39,471 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 16:54:39,479 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 16:54:39,479 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 16:54:39,485 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2022-12-13 16:54:39,486 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 142 states, 141 states have (on average 1.5602836879432624) internal successors, (220), 141 states have internal predecessors, (220), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 16:54:39,491 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 102 [2022-12-13 16:54:39,492 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 16:54:39,492 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 16:54:39,493 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 16:54:39,493 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 16:54:39,498 INFO L748 eck$LassoCheckResult]: Stem: 22#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~fast_clk_edge~0 := 0;~slow_clk_edge~0 := 0;~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0;~t~0 := 0; 36#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~fast_clk_edge~0 := 2;~slow_clk_edge~0 := 2;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 138#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1, start_simulation_~tmp___0~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;havoc start_simulation_~tmp___0~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 25#L258true assume !(1 == ~q_req_up~0); 67#L258-2true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 58#L273true assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 112#L273-2true assume !(1 == ~c_dr_i~0);~c_dr_st~0 := 2; 99#L278-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 46#L311true assume !(0 == ~q_read_ev~0); 100#L311-2true assume !(0 == ~q_write_ev~0); 76#L316-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 31#L66true assume 1 == ~p_dw_pc~0; 129#L67true assume 1 == ~fast_clk_edge~0;is_do_write_p_triggered_~__retres1~0#1 := 1; 53#L87true is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 96#is_do_write_p_triggered_returnLabel#1true activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 51#L387true assume !(0 != activate_threads_~tmp~1#1); 104#L387-2true assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 84#L95true assume 1 == ~c_dr_pc~0; 118#L96true assume 1 == ~slow_clk_edge~0;is_do_read_c_triggered_~__retres1~1#1 := 1; 21#L116true is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 27#is_do_read_c_triggered_returnLabel#1true activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 77#L395true assume !(0 != activate_threads_~tmp___0~1#1); 11#L395-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 28#L329true assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2; 54#L329-2true assume !(1 == ~q_write_ev~0); 33#L334-1true assume { :end_inline_reset_delta_events } true; 126#L491-2true [2022-12-13 16:54:39,499 INFO L750 eck$LassoCheckResult]: Loop: 126#L491-2true assume !false; 127#L492true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 95#L435true assume false; 80#eval_returnLabel#1true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 57#L258-3true assume !(1 == ~q_req_up~0); 107#L258-5true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 130#L311-3true assume 0 == ~q_read_ev~0;~q_read_ev~0 := 1; 113#L311-5true assume !(0 == ~q_write_ev~0); 68#L316-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 111#L66-3true assume 1 == ~p_dw_pc~0; 92#L67-1true assume 1 == ~fast_clk_edge~0;is_do_write_p_triggered_~__retres1~0#1 := 1; 8#L87-1true is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 61#is_do_write_p_triggered_returnLabel#2true activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 122#L387-3true assume 0 != activate_threads_~tmp~1#1;~p_dw_st~0 := 0; 32#L387-5true assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 124#L95-3true assume 1 == ~c_dr_pc~0; 63#L96-1true assume 1 == ~slow_clk_edge~0;is_do_read_c_triggered_~__retres1~1#1 := 1; 102#L116-1true is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 35#is_do_read_c_triggered_returnLabel#2true activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 131#L395-3true assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 16#L395-5true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 41#L329-3true assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2; 88#L329-5true assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 140#L334-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 49#L291-1true assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 103#L303-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 98#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 78#L510true assume !(0 == start_simulation_~tmp~4#1); 6#L510-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 73#L291-2true assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 91#L303-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 30#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 141#L465true assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 29#L472true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 143#stop_simulation_returnLabel#1true start_simulation_#t~ret14#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 75#L523true assume !(0 != start_simulation_~tmp___0~3#1); 126#L491-2true [2022-12-13 16:54:39,505 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:54:39,505 INFO L85 PathProgramCache]: Analyzing trace with hash 854607455, now seen corresponding path program 1 times [2022-12-13 16:54:39,512 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:54:39,512 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1992223989] [2022-12-13 16:54:39,512 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:54:39,513 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:54:39,583 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 16:54:39,651 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 16:54:39,651 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 16:54:39,651 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1992223989] [2022-12-13 16:54:39,652 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1992223989] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 16:54:39,652 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 16:54:39,652 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 16:54:39,654 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2034599499] [2022-12-13 16:54:39,655 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 16:54:39,659 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 16:54:39,660 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:54:39,660 INFO L85 PathProgramCache]: Analyzing trace with hash -857455054, now seen corresponding path program 1 times [2022-12-13 16:54:39,660 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:54:39,660 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [395556259] [2022-12-13 16:54:39,660 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:54:39,661 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:54:39,670 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 16:54:39,682 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 16:54:39,682 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 16:54:39,682 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [395556259] [2022-12-13 16:54:39,682 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [395556259] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 16:54:39,682 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 16:54:39,682 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-12-13 16:54:39,682 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [382969132] [2022-12-13 16:54:39,682 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 16:54:39,683 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 16:54:39,684 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 16:54:39,708 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 16:54:39,708 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 16:54:39,710 INFO L87 Difference]: Start difference. First operand has 142 states, 141 states have (on average 1.5602836879432624) internal successors, (220), 141 states have internal predecessors, (220), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 8.666666666666666) internal successors, (26), 3 states have internal predecessors, (26), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 16:54:39,733 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 16:54:39,733 INFO L93 Difference]: Finished difference Result 140 states and 207 transitions. [2022-12-13 16:54:39,735 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 140 states and 207 transitions. [2022-12-13 16:54:39,736 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 98 [2022-12-13 16:54:39,740 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 140 states to 134 states and 201 transitions. [2022-12-13 16:54:39,740 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 134 [2022-12-13 16:54:39,741 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 134 [2022-12-13 16:54:39,741 INFO L73 IsDeterministic]: Start isDeterministic. Operand 134 states and 201 transitions. [2022-12-13 16:54:39,742 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 16:54:39,742 INFO L218 hiAutomatonCegarLoop]: Abstraction has 134 states and 201 transitions. [2022-12-13 16:54:39,755 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 134 states and 201 transitions. [2022-12-13 16:54:39,765 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 134 to 134. [2022-12-13 16:54:39,766 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 134 states, 134 states have (on average 1.5) internal successors, (201), 133 states have internal predecessors, (201), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 16:54:39,767 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 134 states to 134 states and 201 transitions. [2022-12-13 16:54:39,767 INFO L240 hiAutomatonCegarLoop]: Abstraction has 134 states and 201 transitions. [2022-12-13 16:54:39,768 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 16:54:39,772 INFO L428 stractBuchiCegarLoop]: Abstraction has 134 states and 201 transitions. [2022-12-13 16:54:39,772 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2022-12-13 16:54:39,773 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 134 states and 201 transitions. [2022-12-13 16:54:39,775 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 98 [2022-12-13 16:54:39,776 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 16:54:39,776 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 16:54:39,778 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 16:54:39,778 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 16:54:39,778 INFO L748 eck$LassoCheckResult]: Stem: 332#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~fast_clk_edge~0 := 0;~slow_clk_edge~0 := 0;~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0;~t~0 := 0; 333#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~fast_clk_edge~0 := 2;~slow_clk_edge~0 := 2;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 357#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1, start_simulation_~tmp___0~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;havoc start_simulation_~tmp___0~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 337#L258 assume !(1 == ~q_req_up~0); 339#L258-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 391#L273 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 392#L273-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 416#L278-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 370#L311 assume !(0 == ~q_read_ev~0); 371#L311-2 assume !(0 == ~q_write_ev~0); 403#L316-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 346#L66 assume 1 == ~p_dw_pc~0; 348#L67 assume 1 == ~fast_clk_edge~0;is_do_write_p_triggered_~__retres1~0#1 := 1; 384#L87 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 385#is_do_write_p_triggered_returnLabel#1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 380#L387 assume !(0 != activate_threads_~tmp~1#1); 381#L387-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 409#L95 assume 1 == ~c_dr_pc~0; 411#L96 assume 1 == ~slow_clk_edge~0;is_do_read_c_triggered_~__retres1~1#1 := 1; 328#L116 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 329#is_do_read_c_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 340#L395 assume !(0 != activate_threads_~tmp___0~1#1); 306#L395-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 307#L329 assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2; 343#L329-2 assume !(1 == ~q_write_ev~0); 351#L334-1 assume { :end_inline_reset_delta_events } true; 352#L491-2 [2022-12-13 16:54:39,779 INFO L750 eck$LassoCheckResult]: Loop: 352#L491-2 assume !false; 424#L492 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 353#L435 assume !false; 386#L411 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 387#L291 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 297#L303 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 310#exists_runnable_thread_returnLabel#1 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 311#L415 assume !(0 != eval_~tmp___1~0#1); 407#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 388#L258-3 assume !(1 == ~q_req_up~0); 390#L258-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 418#L311-3 assume 0 == ~q_read_ev~0;~q_read_ev~0 := 1; 422#L311-5 assume !(0 == ~q_write_ev~0); 400#L316-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 401#L66-3 assume 1 == ~p_dw_pc~0; 414#L67-1 assume 1 == ~fast_clk_edge~0;is_do_write_p_triggered_~__retres1~0#1 := 1; 301#L87-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 303#is_do_write_p_triggered_returnLabel#2 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 394#L387-3 assume 0 != activate_threads_~tmp~1#1;~p_dw_st~0 := 0; 349#L387-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 350#L95-3 assume 1 == ~c_dr_pc~0; 395#L96-1 assume 1 == ~slow_clk_edge~0;is_do_read_c_triggered_~__retres1~1#1 := 1; 396#L116-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 355#is_do_read_c_triggered_returnLabel#2 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 356#L395-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 316#L395-5 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 317#L329-3 assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2; 364#L329-5 assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 412#L334-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 377#L291-1 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 378#L303-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 415#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 404#L510 assume !(0 == start_simulation_~tmp~4#1); 298#L510-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 299#L291-2 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 331#L303-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 344#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 345#L465 assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 341#L472 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 342#stop_simulation_returnLabel#1 start_simulation_#t~ret14#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 402#L523 assume !(0 != start_simulation_~tmp___0~3#1); 352#L491-2 [2022-12-13 16:54:39,779 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:54:39,779 INFO L85 PathProgramCache]: Analyzing trace with hash 1672255905, now seen corresponding path program 1 times [2022-12-13 16:54:39,779 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:54:39,780 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1108328312] [2022-12-13 16:54:39,780 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:54:39,780 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:54:39,795 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 16:54:39,863 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 16:54:39,863 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 16:54:39,863 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1108328312] [2022-12-13 16:54:39,863 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1108328312] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 16:54:39,863 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 16:54:39,864 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2022-12-13 16:54:39,864 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [756478092] [2022-12-13 16:54:39,864 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 16:54:39,864 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 16:54:39,865 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:54:39,865 INFO L85 PathProgramCache]: Analyzing trace with hash 2119142840, now seen corresponding path program 1 times [2022-12-13 16:54:39,865 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:54:39,865 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1395927277] [2022-12-13 16:54:39,866 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:54:39,866 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:54:39,882 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 16:54:39,930 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 16:54:39,930 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 16:54:39,930 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1395927277] [2022-12-13 16:54:39,931 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1395927277] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 16:54:39,931 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 16:54:39,931 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-12-13 16:54:39,931 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [292897183] [2022-12-13 16:54:39,931 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 16:54:39,932 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 16:54:39,932 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 16:54:39,932 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-12-13 16:54:39,932 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-12-13 16:54:39,932 INFO L87 Difference]: Start difference. First operand 134 states and 201 transitions. cyclomatic complexity: 68 Second operand has 5 states, 5 states have (on average 5.2) internal successors, (26), 4 states have internal predecessors, (26), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 16:54:40,070 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 16:54:40,070 INFO L93 Difference]: Finished difference Result 479 states and 696 transitions. [2022-12-13 16:54:40,070 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 479 states and 696 transitions. [2022-12-13 16:54:40,075 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 446 [2022-12-13 16:54:40,079 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 479 states to 479 states and 696 transitions. [2022-12-13 16:54:40,079 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 479 [2022-12-13 16:54:40,080 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 479 [2022-12-13 16:54:40,080 INFO L73 IsDeterministic]: Start isDeterministic. Operand 479 states and 696 transitions. [2022-12-13 16:54:40,082 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 16:54:40,083 INFO L218 hiAutomatonCegarLoop]: Abstraction has 479 states and 696 transitions. [2022-12-13 16:54:40,084 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 479 states and 696 transitions. [2022-12-13 16:54:40,110 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 479 to 466. [2022-12-13 16:54:40,111 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 466 states, 466 states have (on average 1.4656652360515021) internal successors, (683), 465 states have internal predecessors, (683), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 16:54:40,114 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 466 states to 466 states and 683 transitions. [2022-12-13 16:54:40,114 INFO L240 hiAutomatonCegarLoop]: Abstraction has 466 states and 683 transitions. [2022-12-13 16:54:40,115 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-12-13 16:54:40,115 INFO L428 stractBuchiCegarLoop]: Abstraction has 466 states and 683 transitions. [2022-12-13 16:54:40,115 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2022-12-13 16:54:40,116 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 466 states and 683 transitions. [2022-12-13 16:54:40,119 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 435 [2022-12-13 16:54:40,119 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 16:54:40,119 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 16:54:40,120 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 16:54:40,120 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 16:54:40,121 INFO L748 eck$LassoCheckResult]: Stem: 959#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~fast_clk_edge~0 := 0;~slow_clk_edge~0 := 0;~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0;~t~0 := 0; 960#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~fast_clk_edge~0 := 2;~slow_clk_edge~0 := 2;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 984#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1, start_simulation_~tmp___0~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;havoc start_simulation_~tmp___0~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 965#L258 assume !(1 == ~q_req_up~0); 966#L258-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1018#L273 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 1019#L273-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 1057#L278-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 998#L311 assume !(0 == ~q_read_ev~0); 999#L311-2 assume !(0 == ~q_write_ev~0); 1034#L316-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 973#L66 assume !(1 == ~p_dw_pc~0); 974#L66-2 assume !(2 == ~p_dw_pc~0); 988#L76-1 is_do_write_p_triggered_~__retres1~0#1 := 0; 1012#L87 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 1013#is_do_write_p_triggered_returnLabel#1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 1008#L387 assume !(0 != activate_threads_~tmp~1#1); 1009#L387-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 1044#L95 assume 1 == ~c_dr_pc~0; 1046#L96 assume 1 == ~slow_clk_edge~0;is_do_read_c_triggered_~__retres1~1#1 := 1; 957#L116 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 958#is_do_read_c_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 967#L395 assume !(0 != activate_threads_~tmp___0~1#1); 934#L395-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 935#L329 assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2; 968#L329-2 assume !(1 == ~q_write_ev~0); 977#L334-1 assume { :end_inline_reset_delta_events } true; 978#L491-2 [2022-12-13 16:54:40,121 INFO L750 eck$LassoCheckResult]: Loop: 978#L491-2 assume !false; 1074#L492 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 980#L435 assume !false; 1014#L411 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 1015#L291 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 925#L303 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 938#exists_runnable_thread_returnLabel#1 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 939#L415 assume !(0 != eval_~tmp___1~0#1); 1039#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1040#L258-3 assume !(1 == ~q_req_up~0); 1288#L258-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1285#L311-3 assume 0 == ~q_read_ev~0;~q_read_ev~0 := 1; 1281#L311-5 assume !(0 == ~q_write_ev~0); 1279#L316-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 1276#L66-3 assume !(1 == ~p_dw_pc~0); 1003#L66-5 assume !(2 == ~p_dw_pc~0); 1004#L76-3 is_do_write_p_triggered_~__retres1~0#1 := 0; 1348#L87-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 1347#is_do_write_p_triggered_returnLabel#2 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 1346#L387-3 assume 0 != activate_threads_~tmp~1#1;~p_dw_st~0 := 0; 1345#L387-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 1344#L95-3 assume 1 == ~c_dr_pc~0; 1342#L96-1 assume 1 == ~slow_clk_edge~0;is_do_read_c_triggered_~__retres1~1#1 := 1; 1059#L116-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 982#is_do_read_c_triggered_returnLabel#2 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 983#L395-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 945#L395-5 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 946#L329-3 assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2; 989#L329-5 assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 1075#L334-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 1076#L291-1 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 1060#L303-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 1061#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 1035#L510 assume !(0 == start_simulation_~tmp~4#1); 926#L510-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 927#L291-2 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 962#L303-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 971#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 972#L465 assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 969#L472 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 970#stop_simulation_returnLabel#1 start_simulation_#t~ret14#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 1033#L523 assume !(0 != start_simulation_~tmp___0~3#1); 978#L491-2 [2022-12-13 16:54:40,122 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:54:40,122 INFO L85 PathProgramCache]: Analyzing trace with hash -841270075, now seen corresponding path program 1 times [2022-12-13 16:54:40,122 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:54:40,122 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [934441342] [2022-12-13 16:54:40,122 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:54:40,122 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:54:40,134 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 16:54:40,193 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 16:54:40,193 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 16:54:40,193 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [934441342] [2022-12-13 16:54:40,193 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [934441342] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 16:54:40,193 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 16:54:40,194 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2022-12-13 16:54:40,194 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [333075023] [2022-12-13 16:54:40,194 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 16:54:40,194 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 16:54:40,195 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:54:40,195 INFO L85 PathProgramCache]: Analyzing trace with hash 1851475893, now seen corresponding path program 1 times [2022-12-13 16:54:40,195 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:54:40,195 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1504171424] [2022-12-13 16:54:40,196 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:54:40,196 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:54:40,207 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 16:54:40,254 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 16:54:40,254 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 16:54:40,254 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1504171424] [2022-12-13 16:54:40,255 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1504171424] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 16:54:40,255 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 16:54:40,255 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-12-13 16:54:40,255 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1535343842] [2022-12-13 16:54:40,255 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 16:54:40,256 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 16:54:40,256 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 16:54:40,256 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-12-13 16:54:40,256 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-12-13 16:54:40,257 INFO L87 Difference]: Start difference. First operand 466 states and 683 transitions. cyclomatic complexity: 219 Second operand has 5 states, 5 states have (on average 5.4) internal successors, (27), 4 states have internal predecessors, (27), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 16:54:40,376 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 16:54:40,377 INFO L93 Difference]: Finished difference Result 1105 states and 1581 transitions. [2022-12-13 16:54:40,377 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1105 states and 1581 transitions. [2022-12-13 16:54:40,384 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1070 [2022-12-13 16:54:40,391 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1105 states to 1105 states and 1581 transitions. [2022-12-13 16:54:40,391 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1105 [2022-12-13 16:54:40,393 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1105 [2022-12-13 16:54:40,393 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1105 states and 1581 transitions. [2022-12-13 16:54:40,397 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 16:54:40,397 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1105 states and 1581 transitions. [2022-12-13 16:54:40,399 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1105 states and 1581 transitions. [2022-12-13 16:54:40,424 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1105 to 1072. [2022-12-13 16:54:40,426 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1072 states, 1072 states have (on average 1.4347014925373134) internal successors, (1538), 1071 states have internal predecessors, (1538), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 16:54:40,431 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1072 states to 1072 states and 1538 transitions. [2022-12-13 16:54:40,431 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1072 states and 1538 transitions. [2022-12-13 16:54:40,431 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-12-13 16:54:40,432 INFO L428 stractBuchiCegarLoop]: Abstraction has 1072 states and 1538 transitions. [2022-12-13 16:54:40,432 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2022-12-13 16:54:40,432 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1072 states and 1538 transitions. [2022-12-13 16:54:40,438 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1038 [2022-12-13 16:54:40,438 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 16:54:40,438 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 16:54:40,439 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 16:54:40,439 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 16:54:40,439 INFO L748 eck$LassoCheckResult]: Stem: 2546#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~fast_clk_edge~0 := 0;~slow_clk_edge~0 := 0;~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0;~t~0 := 0; 2547#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~fast_clk_edge~0 := 2;~slow_clk_edge~0 := 2;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 2569#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1, start_simulation_~tmp___0~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;havoc start_simulation_~tmp___0~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2550#L258 assume !(1 == ~q_req_up~0); 2551#L258-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2603#L273 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 2604#L273-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 2650#L278-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2582#L311 assume !(0 == ~q_read_ev~0); 2583#L311-2 assume !(0 == ~q_write_ev~0); 2624#L316-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 2560#L66 assume !(1 == ~p_dw_pc~0); 2561#L66-2 assume !(2 == ~p_dw_pc~0); 2573#L76-1 is_do_write_p_triggered_~__retres1~0#1 := 0; 2599#L87 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 2600#is_do_write_p_triggered_returnLabel#1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 2593#L387 assume !(0 != activate_threads_~tmp~1#1); 2594#L387-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 2636#L95 assume !(1 == ~c_dr_pc~0); 2637#L95-2 assume !(2 == ~c_dr_pc~0); 2605#L105-1 is_do_read_c_triggered_~__retres1~1#1 := 0; 2542#L116 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 2543#is_do_read_c_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 2552#L395 assume !(0 != activate_threads_~tmp___0~1#1); 2521#L395-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2522#L329 assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2; 2555#L329-2 assume !(1 == ~q_write_ev~0); 2565#L334-1 assume { :end_inline_reset_delta_events } true; 2566#L491-2 [2022-12-13 16:54:40,439 INFO L750 eck$LassoCheckResult]: Loop: 2566#L491-2 assume !false; 2672#L492 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 2563#L435 assume !false; 2597#L411 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 2598#L291 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 2510#L303 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 2523#exists_runnable_thread_returnLabel#1 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 2524#L415 assume !(0 != eval_~tmp___1~0#1); 2630#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2631#L258-3 assume !(1 == ~q_req_up~0); 3571#L258-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3572#L311-3 assume 0 == ~q_read_ev~0;~q_read_ev~0 := 1; 2661#L311-5 assume !(0 == ~q_write_ev~0); 2616#L316-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 2617#L66-3 assume !(1 == ~p_dw_pc~0); 2586#L66-5 assume !(2 == ~p_dw_pc~0); 2513#L76-3 is_do_write_p_triggered_~__retres1~0#1 := 0; 2514#L87-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 2516#is_do_write_p_triggered_returnLabel#2 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 2606#L387-3 assume 0 != activate_threads_~tmp~1#1;~p_dw_st~0 := 0; 2558#L387-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 2559#L95-3 assume !(1 == ~c_dr_pc~0); 2505#L95-5 assume !(2 == ~c_dr_pc~0); 2506#L105-3 is_do_read_c_triggered_~__retres1~1#1 := 0; 2651#L116-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 2567#is_do_read_c_triggered_returnLabel#2 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 2568#L395-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 2530#L395-5 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2531#L329-3 assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2; 2572#L329-5 assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 2641#L334-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 2590#L291-1 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 2591#L303-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 2649#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 2625#L510 assume !(0 == start_simulation_~tmp~4#1); 2511#L510-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 2512#L291-2 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 2545#L303-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 2556#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 2557#L465 assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 2553#L472 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2554#stop_simulation_returnLabel#1 start_simulation_#t~ret14#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 2623#L523 assume !(0 != start_simulation_~tmp___0~3#1); 2566#L491-2 [2022-12-13 16:54:40,440 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:54:40,440 INFO L85 PathProgramCache]: Analyzing trace with hash 156116973, now seen corresponding path program 1 times [2022-12-13 16:54:40,440 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:54:40,440 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1529458229] [2022-12-13 16:54:40,440 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:54:40,441 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:54:40,449 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 16:54:40,480 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 16:54:40,480 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 16:54:40,480 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1529458229] [2022-12-13 16:54:40,480 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1529458229] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 16:54:40,481 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 16:54:40,481 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 16:54:40,481 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [903166657] [2022-12-13 16:54:40,481 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 16:54:40,481 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 16:54:40,482 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:54:40,482 INFO L85 PathProgramCache]: Analyzing trace with hash 1021819368, now seen corresponding path program 1 times [2022-12-13 16:54:40,482 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:54:40,482 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2144090416] [2022-12-13 16:54:40,482 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:54:40,482 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:54:40,489 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 16:54:40,521 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 16:54:40,521 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 16:54:40,521 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2144090416] [2022-12-13 16:54:40,521 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2144090416] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 16:54:40,522 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 16:54:40,522 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-12-13 16:54:40,522 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1173484509] [2022-12-13 16:54:40,522 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 16:54:40,522 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 16:54:40,522 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 16:54:40,523 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 16:54:40,523 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 16:54:40,523 INFO L87 Difference]: Start difference. First operand 1072 states and 1538 transitions. cyclomatic complexity: 470 Second operand has 3 states, 3 states have (on average 9.333333333333334) internal successors, (28), 3 states have internal predecessors, (28), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 16:54:40,556 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 16:54:40,556 INFO L93 Difference]: Finished difference Result 1742 states and 2482 transitions. [2022-12-13 16:54:40,556 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1742 states and 2482 transitions. [2022-12-13 16:54:40,563 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1708 [2022-12-13 16:54:40,567 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1742 states to 1742 states and 2482 transitions. [2022-12-13 16:54:40,567 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1742 [2022-12-13 16:54:40,568 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1742 [2022-12-13 16:54:40,568 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1742 states and 2482 transitions. [2022-12-13 16:54:40,570 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 16:54:40,570 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1742 states and 2482 transitions. [2022-12-13 16:54:40,571 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1742 states and 2482 transitions. [2022-12-13 16:54:40,585 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1742 to 1742. [2022-12-13 16:54:40,587 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1742 states, 1742 states have (on average 1.4247990815154994) internal successors, (2482), 1741 states have internal predecessors, (2482), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 16:54:40,590 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1742 states to 1742 states and 2482 transitions. [2022-12-13 16:54:40,590 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1742 states and 2482 transitions. [2022-12-13 16:54:40,591 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 16:54:40,591 INFO L428 stractBuchiCegarLoop]: Abstraction has 1742 states and 2482 transitions. [2022-12-13 16:54:40,591 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2022-12-13 16:54:40,591 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1742 states and 2482 transitions. [2022-12-13 16:54:40,596 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1708 [2022-12-13 16:54:40,596 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 16:54:40,596 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 16:54:40,597 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 16:54:40,597 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 16:54:40,597 INFO L748 eck$LassoCheckResult]: Stem: 5371#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~fast_clk_edge~0 := 0;~slow_clk_edge~0 := 0;~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0;~t~0 := 0; 5372#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~fast_clk_edge~0 := 2;~slow_clk_edge~0 := 2;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 5394#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1, start_simulation_~tmp___0~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;havoc start_simulation_~tmp___0~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5375#L258 assume !(1 == ~q_req_up~0); 5376#L258-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5429#L273 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 5430#L273-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 5472#L278-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5407#L311 assume !(0 == ~q_read_ev~0); 5408#L311-2 assume !(0 == ~q_write_ev~0); 5448#L316-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 5385#L66 assume !(1 == ~p_dw_pc~0); 5386#L66-2 assume !(2 == ~p_dw_pc~0); 5399#L76-1 is_do_write_p_triggered_~__retres1~0#1 := 0; 5423#L87 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 5424#is_do_write_p_triggered_returnLabel#1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 5417#L387 assume !(0 != activate_threads_~tmp~1#1); 5418#L387-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 5460#L95 assume !(1 == ~c_dr_pc~0); 5461#L95-2 assume !(2 == ~c_dr_pc~0); 5431#L105-1 is_do_read_c_triggered_~__retres1~1#1 := 0; 5367#L116 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 5368#is_do_read_c_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 5377#L395 assume !(0 != activate_threads_~tmp___0~1#1); 5345#L395-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5346#L329 assume !(1 == ~q_read_ev~0); 5380#L329-2 assume !(1 == ~q_write_ev~0); 5390#L334-1 assume { :end_inline_reset_delta_events } true; 5391#L491-2 [2022-12-13 16:54:40,597 INFO L750 eck$LassoCheckResult]: Loop: 5391#L491-2 assume !false; 5634#L492 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 5426#L435 assume !false; 5619#L411 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 5614#L291 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 5610#L303 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 5607#exists_runnable_thread_returnLabel#1 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 5602#L415 assume !(0 != eval_~tmp___1~0#1); 5603#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5766#L258-3 assume !(1 == ~q_req_up~0); 5762#L258-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5758#L311-3 assume !(0 == ~q_read_ev~0); 5755#L311-5 assume !(0 == ~q_write_ev~0); 5750#L316-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 5745#L66-3 assume !(1 == ~p_dw_pc~0); 5744#L66-5 assume !(2 == ~p_dw_pc~0); 5743#L76-3 is_do_write_p_triggered_~__retres1~0#1 := 0; 5742#L87-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 5740#is_do_write_p_triggered_returnLabel#2 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 5738#L387-3 assume 0 != activate_threads_~tmp~1#1;~p_dw_st~0 := 0; 5736#L387-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 5734#L95-3 assume !(1 == ~c_dr_pc~0); 5732#L95-5 assume !(2 == ~c_dr_pc~0); 5730#L105-3 is_do_read_c_triggered_~__retres1~1#1 := 0; 5728#L116-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 5726#is_do_read_c_triggered_returnLabel#2 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 5724#L395-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 5722#L395-5 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5720#L329-3 assume !(1 == ~q_read_ev~0); 5718#L329-5 assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 5716#L334-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 5714#L291-1 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 5691#L303-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 5685#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 5678#L510 assume !(0 == start_simulation_~tmp~4#1); 5671#L510-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 5665#L291-2 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 5659#L303-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 5655#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 5646#L465 assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 5643#L472 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5641#stop_simulation_returnLabel#1 start_simulation_#t~ret14#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 5639#L523 assume !(0 != start_simulation_~tmp___0~3#1); 5391#L491-2 [2022-12-13 16:54:40,598 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:54:40,598 INFO L85 PathProgramCache]: Analyzing trace with hash 156118895, now seen corresponding path program 1 times [2022-12-13 16:54:40,598 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:54:40,598 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1957596425] [2022-12-13 16:54:40,598 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:54:40,598 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:54:40,612 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 16:54:40,612 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 16:54:40,618 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 16:54:40,640 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 16:54:40,641 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:54:40,641 INFO L85 PathProgramCache]: Analyzing trace with hash 16715304, now seen corresponding path program 1 times [2022-12-13 16:54:40,641 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:54:40,641 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1946692232] [2022-12-13 16:54:40,641 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:54:40,642 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:54:40,649 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 16:54:40,680 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 16:54:40,681 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 16:54:40,681 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1946692232] [2022-12-13 16:54:40,681 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1946692232] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 16:54:40,681 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 16:54:40,681 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-12-13 16:54:40,681 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [394254142] [2022-12-13 16:54:40,681 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 16:54:40,682 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 16:54:40,682 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 16:54:40,682 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-12-13 16:54:40,682 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-12-13 16:54:40,683 INFO L87 Difference]: Start difference. First operand 1742 states and 2482 transitions. cyclomatic complexity: 744 Second operand has 5 states, 5 states have (on average 8.6) internal successors, (43), 5 states have internal predecessors, (43), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 16:54:40,750 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 16:54:40,750 INFO L93 Difference]: Finished difference Result 2947 states and 4108 transitions. [2022-12-13 16:54:40,750 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2947 states and 4108 transitions. [2022-12-13 16:54:40,760 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2907 [2022-12-13 16:54:40,768 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2947 states to 2947 states and 4108 transitions. [2022-12-13 16:54:40,768 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2947 [2022-12-13 16:54:40,770 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2947 [2022-12-13 16:54:40,770 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2947 states and 4108 transitions. [2022-12-13 16:54:40,773 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 16:54:40,773 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2947 states and 4108 transitions. [2022-12-13 16:54:40,775 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2947 states and 4108 transitions. [2022-12-13 16:54:40,794 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2947 to 1805. [2022-12-13 16:54:40,796 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1805 states, 1805 states have (on average 1.4099722991689752) internal successors, (2545), 1804 states have internal predecessors, (2545), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 16:54:40,799 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1805 states to 1805 states and 2545 transitions. [2022-12-13 16:54:40,800 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1805 states and 2545 transitions. [2022-12-13 16:54:40,800 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2022-12-13 16:54:40,800 INFO L428 stractBuchiCegarLoop]: Abstraction has 1805 states and 2545 transitions. [2022-12-13 16:54:40,801 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2022-12-13 16:54:40,801 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1805 states and 2545 transitions. [2022-12-13 16:54:40,806 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1771 [2022-12-13 16:54:40,806 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 16:54:40,806 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 16:54:40,806 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 16:54:40,806 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 16:54:40,807 INFO L748 eck$LassoCheckResult]: Stem: 10078#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~fast_clk_edge~0 := 0;~slow_clk_edge~0 := 0;~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0;~t~0 := 0; 10079#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~fast_clk_edge~0 := 2;~slow_clk_edge~0 := 2;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 10100#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1, start_simulation_~tmp___0~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;havoc start_simulation_~tmp___0~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 10082#L258 assume !(1 == ~q_req_up~0); 10083#L258-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 10131#L273 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 10132#L273-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 10176#L278-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 10110#L311 assume !(0 == ~q_read_ev~0); 10111#L311-2 assume !(0 == ~q_write_ev~0); 10151#L316-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 10092#L66 assume !(1 == ~p_dw_pc~0); 10093#L66-2 assume !(2 == ~p_dw_pc~0); 10104#L76-1 is_do_write_p_triggered_~__retres1~0#1 := 0; 10126#L87 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 10127#is_do_write_p_triggered_returnLabel#1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 10120#L387 assume !(0 != activate_threads_~tmp~1#1); 10121#L387-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 10162#L95 assume !(1 == ~c_dr_pc~0); 10163#L95-2 assume !(2 == ~c_dr_pc~0); 10133#L105-1 is_do_read_c_triggered_~__retres1~1#1 := 0; 10074#L116 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 10075#is_do_read_c_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 10084#L395 assume !(0 != activate_threads_~tmp___0~1#1); 10051#L395-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10052#L329 assume !(1 == ~q_read_ev~0); 10087#L329-2 assume !(1 == ~q_write_ev~0); 10096#L334-1 assume { :end_inline_reset_delta_events } true; 10097#L491-2 [2022-12-13 16:54:40,807 INFO L750 eck$LassoCheckResult]: Loop: 10097#L491-2 assume !false; 10357#L492 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 10289#L435 assume !false; 10286#L411 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 10284#L291 assume !(0 == ~p_dw_st~0); 10280#L295 assume !(0 == ~c_dr_st~0);exists_runnable_thread_~__retres1~2#1 := 0; 10278#L303 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 10267#exists_runnable_thread_returnLabel#1 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 10265#L415 assume !(0 != eval_~tmp___1~0#1); 10264#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 10263#L258-3 assume !(1 == ~q_req_up~0); 10262#L258-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 10261#L311-3 assume !(0 == ~q_read_ev~0); 10260#L311-5 assume !(0 == ~q_write_ev~0); 10259#L316-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 10258#L66-3 assume !(1 == ~p_dw_pc~0); 10256#L66-5 assume !(2 == ~p_dw_pc~0); 10257#L76-3 is_do_write_p_triggered_~__retres1~0#1 := 0; 10232#L87-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 10233#is_do_write_p_triggered_returnLabel#2 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 10228#L387-3 assume 0 != activate_threads_~tmp~1#1;~p_dw_st~0 := 0; 10229#L387-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 10224#L95-3 assume !(1 == ~c_dr_pc~0); 10225#L95-5 assume !(2 == ~c_dr_pc~0); 10390#L105-3 is_do_read_c_triggered_~__retres1~1#1 := 0; 10389#L116-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 10388#is_do_read_c_triggered_returnLabel#2 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 10387#L395-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 10386#L395-5 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10385#L329-3 assume !(1 == ~q_read_ev~0); 10384#L329-5 assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 10383#L334-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 10382#L291-1 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 10379#L303-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 10377#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 10374#L510 assume !(0 == start_simulation_~tmp~4#1); 10372#L510-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 10371#L291-2 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 10369#L303-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 10368#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 10367#L465 assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 10366#L472 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 10365#stop_simulation_returnLabel#1 start_simulation_#t~ret14#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 10362#L523 assume !(0 != start_simulation_~tmp___0~3#1); 10097#L491-2 [2022-12-13 16:54:40,807 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:54:40,807 INFO L85 PathProgramCache]: Analyzing trace with hash 156118895, now seen corresponding path program 2 times [2022-12-13 16:54:40,807 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:54:40,808 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2111390633] [2022-12-13 16:54:40,808 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:54:40,808 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:54:40,814 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 16:54:40,814 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 16:54:40,817 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 16:54:40,821 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 16:54:40,821 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:54:40,821 INFO L85 PathProgramCache]: Analyzing trace with hash 526545300, now seen corresponding path program 1 times [2022-12-13 16:54:40,821 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:54:40,821 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [400314128] [2022-12-13 16:54:40,822 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:54:40,822 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:54:40,827 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 16:54:40,876 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 16:54:40,876 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 16:54:40,876 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [400314128] [2022-12-13 16:54:40,876 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [400314128] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 16:54:40,877 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 16:54:40,877 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-12-13 16:54:40,877 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2047354740] [2022-12-13 16:54:40,877 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 16:54:40,877 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 16:54:40,877 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 16:54:40,878 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-12-13 16:54:40,878 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-12-13 16:54:40,878 INFO L87 Difference]: Start difference. First operand 1805 states and 2545 transitions. cyclomatic complexity: 744 Second operand has 5 states, 5 states have (on average 8.8) internal successors, (44), 5 states have internal predecessors, (44), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 16:54:40,951 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 16:54:40,951 INFO L93 Difference]: Finished difference Result 4219 states and 5928 transitions. [2022-12-13 16:54:40,952 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4219 states and 5928 transitions. [2022-12-13 16:54:40,967 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4181 [2022-12-13 16:54:40,978 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4219 states to 4219 states and 5928 transitions. [2022-12-13 16:54:40,978 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4219 [2022-12-13 16:54:40,980 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4219 [2022-12-13 16:54:40,981 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4219 states and 5928 transitions. [2022-12-13 16:54:40,985 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 16:54:40,985 INFO L218 hiAutomatonCegarLoop]: Abstraction has 4219 states and 5928 transitions. [2022-12-13 16:54:40,988 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4219 states and 5928 transitions. [2022-12-13 16:54:41,032 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4219 to 1883. [2022-12-13 16:54:41,035 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1883 states, 1883 states have (on average 1.3839617631439194) internal successors, (2606), 1882 states have internal predecessors, (2606), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 16:54:41,040 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1883 states to 1883 states and 2606 transitions. [2022-12-13 16:54:41,040 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1883 states and 2606 transitions. [2022-12-13 16:54:41,041 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-12-13 16:54:41,041 INFO L428 stractBuchiCegarLoop]: Abstraction has 1883 states and 2606 transitions. [2022-12-13 16:54:41,041 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2022-12-13 16:54:41,041 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1883 states and 2606 transitions. [2022-12-13 16:54:41,046 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1849 [2022-12-13 16:54:41,046 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 16:54:41,046 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 16:54:41,046 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 16:54:41,046 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 16:54:41,047 INFO L748 eck$LassoCheckResult]: Stem: 16112#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~fast_clk_edge~0 := 0;~slow_clk_edge~0 := 0;~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0;~t~0 := 0; 16113#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~fast_clk_edge~0 := 2;~slow_clk_edge~0 := 2;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 16136#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1, start_simulation_~tmp___0~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;havoc start_simulation_~tmp___0~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 16118#L258 assume !(1 == ~q_req_up~0); 16119#L258-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 16176#L273 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 16177#L273-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 16218#L278-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 16151#L311 assume !(0 == ~q_read_ev~0); 16152#L311-2 assume !(0 == ~q_write_ev~0); 16195#L316-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 16126#L66 assume !(1 == ~p_dw_pc~0); 16127#L66-2 assume !(2 == ~p_dw_pc~0); 16140#L76-1 is_do_write_p_triggered_~__retres1~0#1 := 0; 16167#L87 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 16168#is_do_write_p_triggered_returnLabel#1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 16163#L387 assume !(0 != activate_threads_~tmp~1#1); 16164#L387-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 16208#L95 assume !(1 == ~c_dr_pc~0); 16209#L95-2 assume !(2 == ~c_dr_pc~0); 16178#L105-1 is_do_read_c_triggered_~__retres1~1#1 := 0; 16110#L116 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 16111#is_do_read_c_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 16120#L395 assume !(0 != activate_threads_~tmp___0~1#1); 16087#L395-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16088#L329 assume !(1 == ~q_read_ev~0); 16121#L329-2 assume !(1 == ~q_write_ev~0); 16130#L334-1 assume { :end_inline_reset_delta_events } true; 16131#L491-2 [2022-12-13 16:54:41,047 INFO L750 eck$LassoCheckResult]: Loop: 16131#L491-2 assume !false; 16425#L492 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 16319#L435 assume !false; 16423#L411 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 16412#L291 assume !(0 == ~p_dw_st~0); 16413#L295 assume !(0 == ~c_dr_st~0);exists_runnable_thread_~__retres1~2#1 := 0; 16414#L303 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 16408#exists_runnable_thread_returnLabel#1 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 16409#L415 assume !(0 != eval_~tmp___1~0#1); 16472#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 16471#L258-3 assume !(1 == ~q_req_up~0); 16470#L258-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 16469#L311-3 assume !(0 == ~q_read_ev~0); 16468#L311-5 assume !(0 == ~q_write_ev~0); 16467#L316-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 16224#L66-3 assume !(1 == ~p_dw_pc~0); 16155#L66-5 assume !(2 == ~p_dw_pc~0); 16156#L76-3 is_do_write_p_triggered_~__retres1~0#1 := 0; 16438#L87-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 16437#is_do_write_p_triggered_returnLabel#2 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 16434#L387-3 assume !(0 != activate_threads_~tmp~1#1); 16432#L387-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 16430#L95-3 assume !(1 == ~c_dr_pc~0); 16415#L95-5 assume !(2 == ~c_dr_pc~0); 16274#L105-3 is_do_read_c_triggered_~__retres1~1#1 := 0; 16267#L116-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 16266#is_do_read_c_triggered_returnLabel#2 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 16265#L395-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 16264#L395-5 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16263#L329-3 assume !(1 == ~q_read_ev~0); 16262#L329-5 assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 16260#L334-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 16261#L291-1 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 16256#L303-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 16255#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 16252#L510 assume !(0 == start_simulation_~tmp~4#1); 16253#L510-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 16436#L291-2 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 16433#L303-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 16431#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 16429#L465 assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 16428#L472 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 16427#stop_simulation_returnLabel#1 start_simulation_#t~ret14#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 16426#L523 assume !(0 != start_simulation_~tmp___0~3#1); 16131#L491-2 [2022-12-13 16:54:41,047 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:54:41,047 INFO L85 PathProgramCache]: Analyzing trace with hash 156118895, now seen corresponding path program 3 times [2022-12-13 16:54:41,047 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:54:41,048 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1312701587] [2022-12-13 16:54:41,048 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:54:41,048 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:54:41,054 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 16:54:41,054 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 16:54:41,057 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 16:54:41,060 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 16:54:41,061 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:54:41,061 INFO L85 PathProgramCache]: Analyzing trace with hash 392531794, now seen corresponding path program 1 times [2022-12-13 16:54:41,061 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:54:41,061 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [476525383] [2022-12-13 16:54:41,061 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:54:41,061 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:54:41,066 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 16:54:41,079 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 16:54:41,079 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 16:54:41,079 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [476525383] [2022-12-13 16:54:41,079 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [476525383] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 16:54:41,079 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 16:54:41,079 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 16:54:41,079 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1205693065] [2022-12-13 16:54:41,080 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 16:54:41,080 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 16:54:41,080 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 16:54:41,080 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 16:54:41,080 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 16:54:41,081 INFO L87 Difference]: Start difference. First operand 1883 states and 2606 transitions. cyclomatic complexity: 727 Second operand has 3 states, 3 states have (on average 14.666666666666666) internal successors, (44), 3 states have internal predecessors, (44), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 16:54:41,115 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 16:54:41,115 INFO L93 Difference]: Finished difference Result 2972 states and 4013 transitions. [2022-12-13 16:54:41,115 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2972 states and 4013 transitions. [2022-12-13 16:54:41,124 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 2910 [2022-12-13 16:54:41,131 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2972 states to 2972 states and 4013 transitions. [2022-12-13 16:54:41,131 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2972 [2022-12-13 16:54:41,133 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2972 [2022-12-13 16:54:41,133 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2972 states and 4013 transitions. [2022-12-13 16:54:41,136 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 16:54:41,136 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2972 states and 4013 transitions. [2022-12-13 16:54:41,138 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2972 states and 4013 transitions. [2022-12-13 16:54:41,160 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2972 to 2972. [2022-12-13 16:54:41,164 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2972 states, 2972 states have (on average 1.3502691790040378) internal successors, (4013), 2971 states have internal predecessors, (4013), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 16:54:41,169 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2972 states to 2972 states and 4013 transitions. [2022-12-13 16:54:41,169 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2972 states and 4013 transitions. [2022-12-13 16:54:41,169 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 16:54:41,170 INFO L428 stractBuchiCegarLoop]: Abstraction has 2972 states and 4013 transitions. [2022-12-13 16:54:41,170 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2022-12-13 16:54:41,170 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2972 states and 4013 transitions. [2022-12-13 16:54:41,177 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 2910 [2022-12-13 16:54:41,177 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 16:54:41,177 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 16:54:41,177 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 16:54:41,177 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 16:54:41,178 INFO L748 eck$LassoCheckResult]: Stem: 20974#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~fast_clk_edge~0 := 0;~slow_clk_edge~0 := 0;~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0;~t~0 := 0; 20975#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~fast_clk_edge~0 := 2;~slow_clk_edge~0 := 2;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 20999#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1, start_simulation_~tmp___0~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;havoc start_simulation_~tmp___0~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 20978#L258 assume !(1 == ~q_req_up~0); 20979#L258-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 21036#L273 assume !(1 == ~p_dw_i~0);~p_dw_st~0 := 2; 21037#L273-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 21093#L278-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 21094#L311 assume !(0 == ~q_read_ev~0); 21098#L311-2 assume !(0 == ~q_write_ev~0); 21099#L316-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 20988#L66 assume !(1 == ~p_dw_pc~0); 20989#L66-2 assume !(2 == ~p_dw_pc~0); 21124#L76-1 is_do_write_p_triggered_~__retres1~0#1 := 0; 21125#L87 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 21090#is_do_write_p_triggered_returnLabel#1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 21091#L387 assume !(0 != activate_threads_~tmp~1#1); 21100#L387-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 21101#L95 assume !(1 == ~c_dr_pc~0); 21102#L95-2 assume !(2 == ~c_dr_pc~0); 21103#L105-1 is_do_read_c_triggered_~__retres1~1#1 := 0; 20970#L116 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 20971#is_do_read_c_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 21061#L395 assume !(0 != activate_threads_~tmp___0~1#1); 21062#L395-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 20984#L329 assume !(1 == ~q_read_ev~0); 20985#L329-2 assume !(1 == ~q_write_ev~0); 20995#L334-1 assume { :end_inline_reset_delta_events } true; 20996#L491-2 [2022-12-13 16:54:41,178 INFO L750 eck$LassoCheckResult]: Loop: 20996#L491-2 assume !false; 21475#L492 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 21471#L435 assume !false; 21469#L411 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 21467#L291 assume !(0 == ~p_dw_st~0); 21165#L295 assume !(0 == ~c_dr_st~0);exists_runnable_thread_~__retres1~2#1 := 0; 21463#L303 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 21461#exists_runnable_thread_returnLabel#1 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 21458#L415 assume !(0 != eval_~tmp___1~0#1); 21455#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 21453#L258-3 assume !(1 == ~q_req_up~0); 21451#L258-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 21449#L311-3 assume !(0 == ~q_read_ev~0); 21447#L311-5 assume !(0 == ~q_write_ev~0); 21445#L316-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 21443#L66-3 assume !(1 == ~p_dw_pc~0); 21441#L66-5 assume !(2 == ~p_dw_pc~0); 21438#L76-3 is_do_write_p_triggered_~__retres1~0#1 := 0; 21439#L87-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 21434#is_do_write_p_triggered_returnLabel#2 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 21435#L387-3 assume !(0 != activate_threads_~tmp~1#1); 21235#L387-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 21236#L95-3 assume !(1 == ~c_dr_pc~0); 20931#L95-5 assume !(2 == ~c_dr_pc~0); 20932#L105-3 is_do_read_c_triggered_~__retres1~1#1 := 0; 21549#L116-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 21545#is_do_read_c_triggered_returnLabel#2 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 21541#L395-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 21537#L395-5 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21533#L329-3 assume !(1 == ~q_read_ev~0); 21529#L329-5 assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 21525#L334-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 21521#L291-1 assume !(0 == ~p_dw_st~0); 21517#L295-1 assume !(0 == ~c_dr_st~0);exists_runnable_thread_~__retres1~2#1 := 0; 21513#L303-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 21509#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 21504#L510 assume !(0 == start_simulation_~tmp~4#1); 21499#L510-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 21497#L291-2 assume !(0 == ~p_dw_st~0); 21495#L295-2 assume !(0 == ~c_dr_st~0);exists_runnable_thread_~__retres1~2#1 := 0; 21494#L303-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 21492#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 21490#L465 assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 21488#L472 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 21485#stop_simulation_returnLabel#1 start_simulation_#t~ret14#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 21481#L523 assume !(0 != start_simulation_~tmp___0~3#1); 20996#L491-2 [2022-12-13 16:54:41,178 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:54:41,178 INFO L85 PathProgramCache]: Analyzing trace with hash -1649319439, now seen corresponding path program 1 times [2022-12-13 16:54:41,178 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:54:41,178 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1477785771] [2022-12-13 16:54:41,178 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:54:41,179 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:54:41,182 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 16:54:41,192 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 16:54:41,193 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 16:54:41,193 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1477785771] [2022-12-13 16:54:41,193 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1477785771] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 16:54:41,193 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 16:54:41,193 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 16:54:41,193 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1367990157] [2022-12-13 16:54:41,193 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 16:54:41,194 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 16:54:41,194 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:54:41,194 INFO L85 PathProgramCache]: Analyzing trace with hash 2092921140, now seen corresponding path program 1 times [2022-12-13 16:54:41,194 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:54:41,194 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [652670236] [2022-12-13 16:54:41,194 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:54:41,195 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:54:41,199 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 16:54:41,208 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 16:54:41,209 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 16:54:41,209 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [652670236] [2022-12-13 16:54:41,209 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [652670236] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 16:54:41,209 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 16:54:41,209 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 16:54:41,209 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1582313606] [2022-12-13 16:54:41,209 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 16:54:41,210 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 16:54:41,210 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 16:54:41,210 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 16:54:41,210 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 16:54:41,210 INFO L87 Difference]: Start difference. First operand 2972 states and 4013 transitions. cyclomatic complexity: 1048 Second operand has 3 states, 3 states have (on average 9.333333333333334) internal successors, (28), 3 states have internal predecessors, (28), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 16:54:41,232 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 16:54:41,232 INFO L93 Difference]: Finished difference Result 2950 states and 3987 transitions. [2022-12-13 16:54:41,233 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2950 states and 3987 transitions. [2022-12-13 16:54:41,239 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 2910 [2022-12-13 16:54:41,246 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2950 states to 2950 states and 3987 transitions. [2022-12-13 16:54:41,246 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2950 [2022-12-13 16:54:41,248 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2950 [2022-12-13 16:54:41,248 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2950 states and 3987 transitions. [2022-12-13 16:54:41,250 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 16:54:41,250 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2950 states and 3987 transitions. [2022-12-13 16:54:41,253 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2950 states and 3987 transitions. [2022-12-13 16:54:41,274 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2950 to 2950. [2022-12-13 16:54:41,278 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2950 states, 2950 states have (on average 1.3515254237288135) internal successors, (3987), 2949 states have internal predecessors, (3987), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 16:54:41,283 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2950 states to 2950 states and 3987 transitions. [2022-12-13 16:54:41,283 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2950 states and 3987 transitions. [2022-12-13 16:54:41,283 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 16:54:41,284 INFO L428 stractBuchiCegarLoop]: Abstraction has 2950 states and 3987 transitions. [2022-12-13 16:54:41,284 INFO L335 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2022-12-13 16:54:41,284 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2950 states and 3987 transitions. [2022-12-13 16:54:41,290 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 2910 [2022-12-13 16:54:41,290 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 16:54:41,290 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 16:54:41,290 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 16:54:41,290 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 16:54:41,290 INFO L748 eck$LassoCheckResult]: Stem: 26902#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~fast_clk_edge~0 := 0;~slow_clk_edge~0 := 0;~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0;~t~0 := 0; 26903#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~fast_clk_edge~0 := 2;~slow_clk_edge~0 := 2;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 26924#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1, start_simulation_~tmp___0~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;havoc start_simulation_~tmp___0~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 26906#L258 assume !(1 == ~q_req_up~0); 26907#L258-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 26961#L273 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 26962#L273-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 27006#L278-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 26938#L311 assume !(0 == ~q_read_ev~0); 26939#L311-2 assume !(0 == ~q_write_ev~0); 26983#L316-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 26916#L66 assume !(1 == ~p_dw_pc~0); 26917#L66-2 assume !(2 == ~p_dw_pc~0); 26929#L76-1 is_do_write_p_triggered_~__retres1~0#1 := 0; 26954#L87 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 26955#is_do_write_p_triggered_returnLabel#1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 26948#L387 assume !(0 != activate_threads_~tmp~1#1); 26949#L387-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 26996#L95 assume !(1 == ~c_dr_pc~0); 26997#L95-2 assume !(2 == ~c_dr_pc~0); 26963#L105-1 is_do_read_c_triggered_~__retres1~1#1 := 0; 26898#L116 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 26899#is_do_read_c_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 26908#L395 assume !(0 != activate_threads_~tmp___0~1#1); 26878#L395-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 26879#L329 assume !(1 == ~q_read_ev~0); 26911#L329-2 assume !(1 == ~q_write_ev~0); 26920#L334-1 assume { :end_inline_reset_delta_events } true; 26921#L491-2 assume !false; 27821#L492 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 27413#L435 [2022-12-13 16:54:41,291 INFO L750 eck$LassoCheckResult]: Loop: 27413#L435 assume !false; 27815#L411 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 27810#L291 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 27809#L303 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 27395#exists_runnable_thread_returnLabel#1 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 27396#L415 assume 0 != eval_~tmp___1~0#1; 27388#L415-1 assume 0 == ~p_dw_st~0;eval_~tmp~2#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; 27389#L424 assume !(0 != eval_~tmp~2#1); 27414#L420 assume !(0 == ~c_dr_st~0); 27413#L435 [2022-12-13 16:54:41,291 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:54:41,291 INFO L85 PathProgramCache]: Analyzing trace with hash -293592559, now seen corresponding path program 1 times [2022-12-13 16:54:41,291 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:54:41,291 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [559865273] [2022-12-13 16:54:41,291 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:54:41,291 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:54:41,297 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 16:54:41,297 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 16:54:41,300 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 16:54:41,303 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 16:54:41,303 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:54:41,304 INFO L85 PathProgramCache]: Analyzing trace with hash 1094877037, now seen corresponding path program 1 times [2022-12-13 16:54:41,304 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:54:41,304 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1116752042] [2022-12-13 16:54:41,304 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:54:41,304 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:54:41,306 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 16:54:41,306 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 16:54:41,308 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 16:54:41,310 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 16:54:41,310 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:54:41,310 INFO L85 PathProgramCache]: Analyzing trace with hash -1470124195, now seen corresponding path program 1 times [2022-12-13 16:54:41,310 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:54:41,310 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [169565351] [2022-12-13 16:54:41,310 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:54:41,311 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:54:41,315 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 16:54:41,329 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 16:54:41,330 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 16:54:41,330 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [169565351] [2022-12-13 16:54:41,330 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [169565351] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 16:54:41,330 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 16:54:41,330 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-12-13 16:54:41,330 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1470884539] [2022-12-13 16:54:41,330 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 16:54:41,377 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 16:54:41,377 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 16:54:41,377 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 16:54:41,378 INFO L87 Difference]: Start difference. First operand 2950 states and 3987 transitions. cyclomatic complexity: 1044 Second operand has 3 states, 2 states have (on average 19.5) internal successors, (39), 3 states have internal predecessors, (39), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 16:54:41,420 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 16:54:41,420 INFO L93 Difference]: Finished difference Result 4412 states and 5918 transitions. [2022-12-13 16:54:41,420 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4412 states and 5918 transitions. [2022-12-13 16:54:41,437 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 4373 [2022-12-13 16:54:41,455 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4412 states to 4412 states and 5918 transitions. [2022-12-13 16:54:41,455 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4412 [2022-12-13 16:54:41,459 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4412 [2022-12-13 16:54:41,459 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4412 states and 5918 transitions. [2022-12-13 16:54:41,465 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 16:54:41,465 INFO L218 hiAutomatonCegarLoop]: Abstraction has 4412 states and 5918 transitions. [2022-12-13 16:54:41,469 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4412 states and 5918 transitions. [2022-12-13 16:54:41,512 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4412 to 3868. [2022-12-13 16:54:41,516 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3868 states, 3868 states have (on average 1.3495346432264737) internal successors, (5220), 3867 states have internal predecessors, (5220), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 16:54:41,522 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3868 states to 3868 states and 5220 transitions. [2022-12-13 16:54:41,522 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3868 states and 5220 transitions. [2022-12-13 16:54:41,523 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 16:54:41,523 INFO L428 stractBuchiCegarLoop]: Abstraction has 3868 states and 5220 transitions. [2022-12-13 16:54:41,523 INFO L335 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2022-12-13 16:54:41,523 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3868 states and 5220 transitions. [2022-12-13 16:54:41,532 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 3829 [2022-12-13 16:54:41,532 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 16:54:41,532 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 16:54:41,533 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 16:54:41,533 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 16:54:41,533 INFO L748 eck$LassoCheckResult]: Stem: 34273#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~fast_clk_edge~0 := 0;~slow_clk_edge~0 := 0;~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0;~t~0 := 0; 34274#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~fast_clk_edge~0 := 2;~slow_clk_edge~0 := 2;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 34295#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1, start_simulation_~tmp___0~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;havoc start_simulation_~tmp___0~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 34277#L258 assume !(1 == ~q_req_up~0); 34278#L258-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 34334#L273 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 34335#L273-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 34376#L278-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 34310#L311 assume !(0 == ~q_read_ev~0); 34311#L311-2 assume !(0 == ~q_write_ev~0); 34355#L316-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 34287#L66 assume !(1 == ~p_dw_pc~0); 34288#L66-2 assume !(2 == ~p_dw_pc~0); 34301#L76-1 is_do_write_p_triggered_~__retres1~0#1 := 0; 34327#L87 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 34328#is_do_write_p_triggered_returnLabel#1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 34321#L387 assume !(0 != activate_threads_~tmp~1#1); 34322#L387-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 34364#L95 assume !(1 == ~c_dr_pc~0); 34365#L95-2 assume !(2 == ~c_dr_pc~0); 34336#L105-1 is_do_read_c_triggered_~__retres1~1#1 := 0; 34269#L116 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 34270#is_do_read_c_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 34279#L395 assume !(0 != activate_threads_~tmp___0~1#1); 34247#L395-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 34248#L329 assume !(1 == ~q_read_ev~0); 34282#L329-2 assume !(1 == ~q_write_ev~0); 34291#L334-1 assume { :end_inline_reset_delta_events } true; 34292#L491-2 assume !false; 34537#L492 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 34508#L435 [2022-12-13 16:54:41,533 INFO L750 eck$LassoCheckResult]: Loop: 34508#L435 assume !false; 34535#L411 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 34533#L291 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 34530#L303 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 34526#exists_runnable_thread_returnLabel#1 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 34523#L415 assume 0 != eval_~tmp___1~0#1; 34518#L415-1 assume 0 == ~p_dw_st~0;eval_~tmp~2#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; 34515#L424 assume !(0 != eval_~tmp~2#1); 34512#L420 assume 0 == ~c_dr_st~0;eval_~tmp___0~2#1 := eval_#t~nondet11#1;havoc eval_#t~nondet11#1; 34507#L439 assume !(0 != eval_~tmp___0~2#1); 34508#L435 [2022-12-13 16:54:41,533 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:54:41,534 INFO L85 PathProgramCache]: Analyzing trace with hash -293592559, now seen corresponding path program 2 times [2022-12-13 16:54:41,534 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:54:41,534 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [767126021] [2022-12-13 16:54:41,534 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:54:41,534 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:54:41,539 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 16:54:41,539 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 16:54:41,542 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 16:54:41,547 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 16:54:41,548 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:54:41,548 INFO L85 PathProgramCache]: Analyzing trace with hash -418551849, now seen corresponding path program 1 times [2022-12-13 16:54:41,548 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:54:41,548 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [617032222] [2022-12-13 16:54:41,548 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:54:41,548 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:54:41,552 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 16:54:41,552 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 16:54:41,553 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 16:54:41,555 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 16:54:41,555 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:54:41,555 INFO L85 PathProgramCache]: Analyzing trace with hash 1670788583, now seen corresponding path program 1 times [2022-12-13 16:54:41,555 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:54:41,555 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1874404026] [2022-12-13 16:54:41,556 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:54:41,556 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:54:41,562 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 16:54:41,562 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 16:54:41,566 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 16:54:41,571 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 16:54:42,199 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 16:54:42,199 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 16:54:42,207 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 16:54:42,262 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 13.12 04:54:42 BoogieIcfgContainer [2022-12-13 16:54:42,262 INFO L132 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2022-12-13 16:54:42,263 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2022-12-13 16:54:42,263 INFO L271 PluginConnector]: Initializing Witness Printer... [2022-12-13 16:54:42,263 INFO L275 PluginConnector]: Witness Printer initialized [2022-12-13 16:54:42,263 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.12 04:54:39" (3/4) ... [2022-12-13 16:54:42,272 INFO L134 WitnessPrinter]: Generating witness for non-termination counterexample [2022-12-13 16:54:42,310 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6c7f58a-a15b-42a2-a692-424aa31a7513/bin/uautomizer-uyxdKDjOR8/witness.graphml [2022-12-13 16:54:42,311 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2022-12-13 16:54:42,311 INFO L158 Benchmark]: Toolchain (without parser) took 3635.78ms. Allocated memory was 130.0MB in the beginning and 188.7MB in the end (delta: 58.7MB). Free memory was 96.7MB in the beginning and 127.9MB in the end (delta: -31.1MB). Peak memory consumption was 85.2MB. Max. memory is 16.1GB. [2022-12-13 16:54:42,311 INFO L158 Benchmark]: CDTParser took 0.15ms. Allocated memory is still 90.2MB. Free memory is still 42.9MB. There was no memory consumed. Max. memory is 16.1GB. [2022-12-13 16:54:42,312 INFO L158 Benchmark]: CACSL2BoogieTranslator took 202.80ms. Allocated memory is still 130.0MB. Free memory was 96.2MB in the beginning and 82.7MB in the end (delta: 13.6MB). Peak memory consumption was 12.6MB. Max. memory is 16.1GB. [2022-12-13 16:54:42,312 INFO L158 Benchmark]: Boogie Procedure Inliner took 28.70ms. Allocated memory is still 130.0MB. Free memory was 82.7MB in the beginning and 80.1MB in the end (delta: 2.6MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. [2022-12-13 16:54:42,312 INFO L158 Benchmark]: Boogie Preprocessor took 19.83ms. Allocated memory is still 130.0MB. Free memory was 80.1MB in the beginning and 78.0MB in the end (delta: 2.1MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. [2022-12-13 16:54:42,312 INFO L158 Benchmark]: RCFGBuilder took 450.19ms. Allocated memory is still 130.0MB. Free memory was 78.0MB in the beginning and 56.9MB in the end (delta: 21.1MB). Peak memory consumption was 21.0MB. Max. memory is 16.1GB. [2022-12-13 16:54:42,313 INFO L158 Benchmark]: BuchiAutomizer took 2882.20ms. Allocated memory was 130.0MB in the beginning and 157.3MB in the end (delta: 27.3MB). Free memory was 56.4MB in the beginning and 51.5MB in the end (delta: 4.9MB). Peak memory consumption was 32.8MB. Max. memory is 16.1GB. [2022-12-13 16:54:42,313 INFO L158 Benchmark]: Witness Printer took 48.07ms. Allocated memory was 157.3MB in the beginning and 188.7MB in the end (delta: 31.5MB). Free memory was 51.5MB in the beginning and 127.9MB in the end (delta: -76.3MB). Peak memory consumption was 10.5MB. Max. memory is 16.1GB. [2022-12-13 16:54:42,315 INFO L339 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.15ms. Allocated memory is still 90.2MB. Free memory is still 42.9MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 202.80ms. Allocated memory is still 130.0MB. Free memory was 96.2MB in the beginning and 82.7MB in the end (delta: 13.6MB). Peak memory consumption was 12.6MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 28.70ms. Allocated memory is still 130.0MB. Free memory was 82.7MB in the beginning and 80.1MB in the end (delta: 2.6MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. * Boogie Preprocessor took 19.83ms. Allocated memory is still 130.0MB. Free memory was 80.1MB in the beginning and 78.0MB in the end (delta: 2.1MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. * RCFGBuilder took 450.19ms. Allocated memory is still 130.0MB. Free memory was 78.0MB in the beginning and 56.9MB in the end (delta: 21.1MB). Peak memory consumption was 21.0MB. Max. memory is 16.1GB. * BuchiAutomizer took 2882.20ms. Allocated memory was 130.0MB in the beginning and 157.3MB in the end (delta: 27.3MB). Free memory was 56.4MB in the beginning and 51.5MB in the end (delta: 4.9MB). Peak memory consumption was 32.8MB. Max. memory is 16.1GB. * Witness Printer took 48.07ms. Allocated memory was 157.3MB in the beginning and 188.7MB in the end (delta: 31.5MB). Free memory was 51.5MB in the beginning and 127.9MB in the end (delta: -76.3MB). Peak memory consumption was 10.5MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 9 terminating modules (9 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.9 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 3868 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 2.7s and 10 iterations. TraceHistogramMax:1. Analysis of lassos took 1.5s. Construction of modules took 0.2s. Büchi inclusion checks took 0.8s. Highest rank in rank-based complementation 0. Minimization of det autom 9. Minimization of nondet autom 0. Automata minimization 0.3s AutomataMinimizationTime, 9 MinimizatonAttempts, 4068 StatesRemovedByMinimization, 5 NontrivialMinimizations. Non-live state removal took 0.1s Buchi closure took 0.0s. Biggest automaton had -1 states and ocurred in iteration -1. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 3109 SdHoareTripleChecker+Valid, 0.3s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 3109 mSDsluCounter, 4252 SdHoareTripleChecker+Invalid, 0.2s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 2626 mSDsCounter, 105 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 261 IncrementalHoareTripleChecker+Invalid, 366 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 105 mSolverCounterUnsat, 1626 mSDtfsCounter, 261 mSolverCounterSat, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI3 SFLT0 conc1 concLT0 SILN0 SILU0 SILI5 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s InitialAbstractionConstructionTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - LassoShapedNonTerminationArgument [Line: 410]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite program execution. Stem: [L24] int fast_clk_edge ; [L25] int slow_clk_edge ; [L26] int q_buf_0 ; [L27] int q_free ; [L28] int q_read_ev ; [L29] int q_write_ev ; [L30] int q_req_up ; [L31] int q_ev ; [L52] int p_num_write ; [L53] int p_last_write ; [L54] int p_dw_st ; [L55] int p_dw_pc ; [L56] int p_dw_i ; [L57] int c_num_read ; [L58] int c_last_read ; [L59] int c_dr_st ; [L60] int c_dr_pc ; [L61] int c_dr_i ; [L194] static int a_t ; [L344] static int t = 0; VAL [a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=0, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0, slow_clk_edge=0, t=0] [L555] int __retres1 ; [L559] CALL init_model() [L539] fast_clk_edge = 2 [L540] slow_clk_edge = 2 [L541] q_free = 1 [L542] q_write_ev = 2 [L543] q_read_ev = q_write_ev [L544] p_num_write = 0 [L545] p_dw_pc = 0 [L546] p_dw_i = 1 [L547] c_num_read = 0 [L548] c_dr_pc = 0 [L549] c_dr_i = 1 VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L559] RET init_model() [L560] CALL start_simulation() [L477] int kernel_st ; [L478] int tmp ; [L479] int tmp___0 ; [L483] kernel_st = 0 [L484] CALL update_channels() [L258] COND FALSE !((int )q_req_up == 1) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L484] RET update_channels() [L485] CALL init_threads() [L273] COND TRUE (int )p_dw_i == 1 [L274] p_dw_st = 0 VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L278] COND TRUE (int )c_dr_i == 1 [L279] c_dr_st = 0 VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L485] RET init_threads() [L486] CALL fire_delta_events() [L311] COND FALSE !((int )q_read_ev == 0) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L316] COND FALSE !((int )q_write_ev == 0) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L486] RET fire_delta_events() [L487] CALL activate_threads() [L380] int tmp ; [L381] int tmp___0 ; [L385] CALL, EXPR is_do_write_p_triggered() [L63] int __retres1 ; VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L66] COND FALSE !((int )p_dw_pc == 1) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L76] COND FALSE !((int )p_dw_pc == 2) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L86] __retres1 = 0 VAL [__retres1=0, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L88] return (__retres1); VAL [\result=0, __retres1=0, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L385] RET, EXPR is_do_write_p_triggered() [L385] tmp = is_do_write_p_triggered() [L387] COND FALSE !(\read(tmp)) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0, tmp=0] [L393] CALL, EXPR is_do_read_c_triggered() [L92] int __retres1 ; VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L95] COND FALSE !((int )c_dr_pc == 1) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L105] COND FALSE !((int )c_dr_pc == 2) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L115] __retres1 = 0 VAL [__retres1=0, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L117] return (__retres1); VAL [\result=0, __retres1=0, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L393] RET, EXPR is_do_read_c_triggered() [L393] tmp___0 = is_do_read_c_triggered() [L395] COND FALSE !(\read(tmp___0)) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0, tmp=0, tmp___0=0] [L487] RET activate_threads() [L488] CALL reset_delta_events() [L329] COND FALSE !((int )q_read_ev == 1) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L334] COND FALSE !((int )q_write_ev == 1) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L488] RET reset_delta_events() [L491] COND TRUE 1 VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, kernel_st=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L494] kernel_st = 1 [L495] CALL eval() [L405] int tmp ; [L406] int tmp___0 ; [L407] int tmp___1 ; VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] Loop: [L410] COND TRUE 1 [L413] CALL, EXPR exists_runnable_thread() [L288] int __retres1 ; [L291] COND TRUE (int )p_dw_st == 0 [L292] __retres1 = 1 [L304] return (__retres1); [L413] RET, EXPR exists_runnable_thread() [L413] tmp___1 = exists_runnable_thread() [L415] COND TRUE \read(tmp___1) [L420] COND TRUE (int )p_dw_st == 0 [L422] tmp = __VERIFIER_nondet_int() [L424] COND FALSE !(\read(tmp)) [L435] COND TRUE (int )c_dr_st == 0 [L437] tmp___0 = __VERIFIER_nondet_int() [L439] COND FALSE !(\read(tmp___0)) End of lasso representation. - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 410]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L24] int fast_clk_edge ; [L25] int slow_clk_edge ; [L26] int q_buf_0 ; [L27] int q_free ; [L28] int q_read_ev ; [L29] int q_write_ev ; [L30] int q_req_up ; [L31] int q_ev ; [L52] int p_num_write ; [L53] int p_last_write ; [L54] int p_dw_st ; [L55] int p_dw_pc ; [L56] int p_dw_i ; [L57] int c_num_read ; [L58] int c_last_read ; [L59] int c_dr_st ; [L60] int c_dr_pc ; [L61] int c_dr_i ; [L194] static int a_t ; [L344] static int t = 0; VAL [a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=0, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0, slow_clk_edge=0, t=0] [L555] int __retres1 ; [L559] CALL init_model() [L539] fast_clk_edge = 2 [L540] slow_clk_edge = 2 [L541] q_free = 1 [L542] q_write_ev = 2 [L543] q_read_ev = q_write_ev [L544] p_num_write = 0 [L545] p_dw_pc = 0 [L546] p_dw_i = 1 [L547] c_num_read = 0 [L548] c_dr_pc = 0 [L549] c_dr_i = 1 VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L559] RET init_model() [L560] CALL start_simulation() [L477] int kernel_st ; [L478] int tmp ; [L479] int tmp___0 ; [L483] kernel_st = 0 [L484] CALL update_channels() [L258] COND FALSE !((int )q_req_up == 1) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L484] RET update_channels() [L485] CALL init_threads() [L273] COND TRUE (int )p_dw_i == 1 [L274] p_dw_st = 0 VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L278] COND TRUE (int )c_dr_i == 1 [L279] c_dr_st = 0 VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L485] RET init_threads() [L486] CALL fire_delta_events() [L311] COND FALSE !((int )q_read_ev == 0) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L316] COND FALSE !((int )q_write_ev == 0) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L486] RET fire_delta_events() [L487] CALL activate_threads() [L380] int tmp ; [L381] int tmp___0 ; [L385] CALL, EXPR is_do_write_p_triggered() [L63] int __retres1 ; VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L66] COND FALSE !((int )p_dw_pc == 1) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L76] COND FALSE !((int )p_dw_pc == 2) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L86] __retres1 = 0 VAL [__retres1=0, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L88] return (__retres1); VAL [\result=0, __retres1=0, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L385] RET, EXPR is_do_write_p_triggered() [L385] tmp = is_do_write_p_triggered() [L387] COND FALSE !(\read(tmp)) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0, tmp=0] [L393] CALL, EXPR is_do_read_c_triggered() [L92] int __retres1 ; VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L95] COND FALSE !((int )c_dr_pc == 1) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L105] COND FALSE !((int )c_dr_pc == 2) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L115] __retres1 = 0 VAL [__retres1=0, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L117] return (__retres1); VAL [\result=0, __retres1=0, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L393] RET, EXPR is_do_read_c_triggered() [L393] tmp___0 = is_do_read_c_triggered() [L395] COND FALSE !(\read(tmp___0)) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0, tmp=0, tmp___0=0] [L487] RET activate_threads() [L488] CALL reset_delta_events() [L329] COND FALSE !((int )q_read_ev == 1) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L334] COND FALSE !((int )q_write_ev == 1) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L488] RET reset_delta_events() [L491] COND TRUE 1 VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, kernel_st=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L494] kernel_st = 1 [L495] CALL eval() [L405] int tmp ; [L406] int tmp___0 ; [L407] int tmp___1 ; VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] Loop: [L410] COND TRUE 1 [L413] CALL, EXPR exists_runnable_thread() [L288] int __retres1 ; [L291] COND TRUE (int )p_dw_st == 0 [L292] __retres1 = 1 [L304] return (__retres1); [L413] RET, EXPR exists_runnable_thread() [L413] tmp___1 = exists_runnable_thread() [L415] COND TRUE \read(tmp___1) [L420] COND TRUE (int )p_dw_st == 0 [L422] tmp = __VERIFIER_nondet_int() [L424] COND FALSE !(\read(tmp)) [L435] COND TRUE (int )c_dr_st == 0 [L437] tmp___0 = __VERIFIER_nondet_int() [L439] COND FALSE !(\read(tmp___0)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2022-12-13 16:54:42,354 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6c7f58a-a15b-42a2-a692-424aa31a7513/bin/uautomizer-uyxdKDjOR8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Forceful destruction successful, exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)