./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/token_ring.04.cil-1.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 2329fc70 Calling Ultimate with: /usr/lib/jvm/java-1.11.0-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7dcf1f71-2ccc-4322-b384-52ae8173b8c8/bin/uautomizer-uyxdKDjOR8/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7dcf1f71-2ccc-4322-b384-52ae8173b8c8/bin/uautomizer-uyxdKDjOR8/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7dcf1f71-2ccc-4322-b384-52ae8173b8c8/bin/uautomizer-uyxdKDjOR8/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7dcf1f71-2ccc-4322-b384-52ae8173b8c8/bin/uautomizer-uyxdKDjOR8/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/token_ring.04.cil-1.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7dcf1f71-2ccc-4322-b384-52ae8173b8c8/bin/uautomizer-uyxdKDjOR8/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7dcf1f71-2ccc-4322-b384-52ae8173b8c8/bin/uautomizer-uyxdKDjOR8 --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash d4710f8f3a918a0191222414f5c33a367ff98c09c2e8598fa3213223c4c35dba --- Real Ultimate output --- [0.001s][warning][os,container] Duplicate cpuset controllers detected. Picking /sys/fs/cgroup/cpuset, skipping /sys/fs/cgroup/cpuset. This is Ultimate 0.2.2-dev-2329fc7 [2022-12-13 20:37:45,932 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-12-13 20:37:45,934 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-12-13 20:37:45,954 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-12-13 20:37:45,954 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-12-13 20:37:45,955 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-12-13 20:37:45,956 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-12-13 20:37:45,958 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-12-13 20:37:45,960 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-12-13 20:37:45,961 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-12-13 20:37:45,962 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-12-13 20:37:45,963 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-12-13 20:37:45,963 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-12-13 20:37:45,964 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-12-13 20:37:45,965 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-12-13 20:37:45,967 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-12-13 20:37:45,968 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-12-13 20:37:45,969 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-12-13 20:37:45,971 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-12-13 20:37:45,972 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-12-13 20:37:45,974 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-12-13 20:37:45,975 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-12-13 20:37:45,976 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-12-13 20:37:45,977 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-12-13 20:37:45,981 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-12-13 20:37:45,981 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-12-13 20:37:45,981 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-12-13 20:37:45,982 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-12-13 20:37:45,983 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-12-13 20:37:45,983 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-12-13 20:37:45,984 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-12-13 20:37:45,985 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-12-13 20:37:45,985 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-12-13 20:37:45,986 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-12-13 20:37:45,987 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-12-13 20:37:45,987 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-12-13 20:37:45,988 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-12-13 20:37:45,988 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-12-13 20:37:45,988 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-12-13 20:37:45,989 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-12-13 20:37:45,990 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-12-13 20:37:45,990 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7dcf1f71-2ccc-4322-b384-52ae8173b8c8/bin/uautomizer-uyxdKDjOR8/config/svcomp-Termination-32bit-Automizer_Default.epf [2022-12-13 20:37:46,011 INFO L113 SettingsManager]: Loading preferences was successful [2022-12-13 20:37:46,012 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-12-13 20:37:46,012 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-12-13 20:37:46,012 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-12-13 20:37:46,013 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-12-13 20:37:46,013 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-12-13 20:37:46,014 INFO L138 SettingsManager]: * Use SBE=true [2022-12-13 20:37:46,014 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2022-12-13 20:37:46,014 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2022-12-13 20:37:46,014 INFO L138 SettingsManager]: * Use old map elimination=false [2022-12-13 20:37:46,014 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2022-12-13 20:37:46,014 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2022-12-13 20:37:46,015 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2022-12-13 20:37:46,015 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-12-13 20:37:46,015 INFO L138 SettingsManager]: * sizeof long=4 [2022-12-13 20:37:46,015 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2022-12-13 20:37:46,015 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-12-13 20:37:46,016 INFO L138 SettingsManager]: * sizeof POINTER=4 [2022-12-13 20:37:46,016 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-12-13 20:37:46,016 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2022-12-13 20:37:46,016 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2022-12-13 20:37:46,016 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2022-12-13 20:37:46,016 INFO L138 SettingsManager]: * sizeof long double=12 [2022-12-13 20:37:46,017 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-12-13 20:37:46,017 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2022-12-13 20:37:46,017 INFO L138 SettingsManager]: * Use constant arrays=true [2022-12-13 20:37:46,017 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2022-12-13 20:37:46,017 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-12-13 20:37:46,017 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-12-13 20:37:46,018 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-12-13 20:37:46,018 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-12-13 20:37:46,019 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-12-13 20:37:46,019 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7dcf1f71-2ccc-4322-b384-52ae8173b8c8/bin/uautomizer-uyxdKDjOR8/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7dcf1f71-2ccc-4322-b384-52ae8173b8c8/bin/uautomizer-uyxdKDjOR8 Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> d4710f8f3a918a0191222414f5c33a367ff98c09c2e8598fa3213223c4c35dba [2022-12-13 20:37:46,213 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-12-13 20:37:46,233 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-12-13 20:37:46,235 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-12-13 20:37:46,236 INFO L271 PluginConnector]: Initializing CDTParser... [2022-12-13 20:37:46,236 INFO L275 PluginConnector]: CDTParser initialized [2022-12-13 20:37:46,237 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7dcf1f71-2ccc-4322-b384-52ae8173b8c8/bin/uautomizer-uyxdKDjOR8/../../sv-benchmarks/c/systemc/token_ring.04.cil-1.c [2022-12-13 20:37:48,694 INFO L500 CDTParser]: Created temporary CDT project at NULL [2022-12-13 20:37:48,850 INFO L351 CDTParser]: Found 1 translation units. [2022-12-13 20:37:48,850 INFO L172 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7dcf1f71-2ccc-4322-b384-52ae8173b8c8/sv-benchmarks/c/systemc/token_ring.04.cil-1.c [2022-12-13 20:37:48,856 INFO L394 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7dcf1f71-2ccc-4322-b384-52ae8173b8c8/bin/uautomizer-uyxdKDjOR8/data/52529fcf3/6e47083716544b23a9a3349eeafda1ec/FLAG2b9c2ed29 [2022-12-13 20:37:49,284 INFO L402 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7dcf1f71-2ccc-4322-b384-52ae8173b8c8/bin/uautomizer-uyxdKDjOR8/data/52529fcf3/6e47083716544b23a9a3349eeafda1ec [2022-12-13 20:37:49,287 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-12-13 20:37:49,288 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-12-13 20:37:49,289 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-12-13 20:37:49,289 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-12-13 20:37:49,292 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-12-13 20:37:49,292 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.12 08:37:49" (1/1) ... [2022-12-13 20:37:49,293 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@2338f009 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 08:37:49, skipping insertion in model container [2022-12-13 20:37:49,294 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.12 08:37:49" (1/1) ... [2022-12-13 20:37:49,300 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-12-13 20:37:49,319 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-12-13 20:37:49,410 WARN L237 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7dcf1f71-2ccc-4322-b384-52ae8173b8c8/sv-benchmarks/c/systemc/token_ring.04.cil-1.c[671,684] [2022-12-13 20:37:49,451 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-12-13 20:37:49,463 INFO L203 MainTranslator]: Completed pre-run [2022-12-13 20:37:49,471 WARN L237 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7dcf1f71-2ccc-4322-b384-52ae8173b8c8/sv-benchmarks/c/systemc/token_ring.04.cil-1.c[671,684] [2022-12-13 20:37:49,496 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-12-13 20:37:49,510 INFO L208 MainTranslator]: Completed translation [2022-12-13 20:37:49,510 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 08:37:49 WrapperNode [2022-12-13 20:37:49,510 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-12-13 20:37:49,511 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-12-13 20:37:49,511 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-12-13 20:37:49,511 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-12-13 20:37:49,517 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 08:37:49" (1/1) ... [2022-12-13 20:37:49,526 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 08:37:49" (1/1) ... [2022-12-13 20:37:49,568 INFO L138 Inliner]: procedures = 36, calls = 43, calls flagged for inlining = 38, calls inlined = 77, statements flattened = 1062 [2022-12-13 20:37:49,569 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-12-13 20:37:49,569 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-12-13 20:37:49,570 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-12-13 20:37:49,570 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-12-13 20:37:49,578 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 08:37:49" (1/1) ... [2022-12-13 20:37:49,579 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 08:37:49" (1/1) ... [2022-12-13 20:37:49,581 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 08:37:49" (1/1) ... [2022-12-13 20:37:49,581 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 08:37:49" (1/1) ... [2022-12-13 20:37:49,590 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 08:37:49" (1/1) ... [2022-12-13 20:37:49,598 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 08:37:49" (1/1) ... [2022-12-13 20:37:49,601 INFO L185 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 08:37:49" (1/1) ... [2022-12-13 20:37:49,603 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 08:37:49" (1/1) ... [2022-12-13 20:37:49,607 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-12-13 20:37:49,608 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-12-13 20:37:49,608 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-12-13 20:37:49,608 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-12-13 20:37:49,609 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 08:37:49" (1/1) ... [2022-12-13 20:37:49,614 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-12-13 20:37:49,623 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7dcf1f71-2ccc-4322-b384-52ae8173b8c8/bin/uautomizer-uyxdKDjOR8/z3 [2022-12-13 20:37:49,633 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7dcf1f71-2ccc-4322-b384-52ae8173b8c8/bin/uautomizer-uyxdKDjOR8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-12-13 20:37:49,635 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7dcf1f71-2ccc-4322-b384-52ae8173b8c8/bin/uautomizer-uyxdKDjOR8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2022-12-13 20:37:49,662 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-12-13 20:37:49,662 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-12-13 20:37:49,662 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-12-13 20:37:49,662 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-12-13 20:37:49,732 INFO L235 CfgBuilder]: Building ICFG [2022-12-13 20:37:49,734 INFO L261 CfgBuilder]: Building CFG for each procedure with an implementation [2022-12-13 20:37:50,366 INFO L276 CfgBuilder]: Performing block encoding [2022-12-13 20:37:50,376 INFO L295 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-12-13 20:37:50,376 INFO L300 CfgBuilder]: Removed 7 assume(true) statements. [2022-12-13 20:37:50,379 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.12 08:37:50 BoogieIcfgContainer [2022-12-13 20:37:50,379 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-12-13 20:37:50,380 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2022-12-13 20:37:50,380 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2022-12-13 20:37:50,384 INFO L275 PluginConnector]: BuchiAutomizer initialized [2022-12-13 20:37:50,385 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-12-13 20:37:50,385 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 13.12 08:37:49" (1/3) ... [2022-12-13 20:37:50,385 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@3315b405 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 13.12 08:37:50, skipping insertion in model container [2022-12-13 20:37:50,386 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-12-13 20:37:50,386 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 08:37:49" (2/3) ... [2022-12-13 20:37:50,386 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@3315b405 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 13.12 08:37:50, skipping insertion in model container [2022-12-13 20:37:50,386 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-12-13 20:37:50,386 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.12 08:37:50" (3/3) ... [2022-12-13 20:37:50,387 INFO L332 chiAutomizerObserver]: Analyzing ICFG token_ring.04.cil-1.c [2022-12-13 20:37:50,446 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2022-12-13 20:37:50,447 INFO L304 stractBuchiCegarLoop]: Hoare is false [2022-12-13 20:37:50,447 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2022-12-13 20:37:50,447 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2022-12-13 20:37:50,447 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2022-12-13 20:37:50,447 INFO L308 stractBuchiCegarLoop]: Difference is false [2022-12-13 20:37:50,447 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2022-12-13 20:37:50,447 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2022-12-13 20:37:50,453 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 431 states, 430 states have (on average 1.5325581395348837) internal successors, (659), 430 states have internal predecessors, (659), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 20:37:50,482 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 360 [2022-12-13 20:37:50,482 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 20:37:50,483 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 20:37:50,491 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 20:37:50,491 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 20:37:50,491 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2022-12-13 20:37:50,493 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 431 states, 430 states have (on average 1.5325581395348837) internal successors, (659), 430 states have internal predecessors, (659), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 20:37:50,501 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 360 [2022-12-13 20:37:50,501 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 20:37:50,501 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 20:37:50,503 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 20:37:50,503 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 20:37:50,510 INFO L748 eck$LassoCheckResult]: Stem: 126#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 359#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 204#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 355#update_channels_returnLabel#1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 74#L353true assume !(1 == ~m_i~0);~m_st~0 := 2; 289#L353-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 365#L358-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 44#L363-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 410#L368-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 121#L373-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 58#L514true assume !(0 == ~M_E~0); 379#L514-2true assume 0 == ~T1_E~0;~T1_E~0 := 1; 318#L519-1true assume !(0 == ~T2_E~0); 37#L524-1true assume !(0 == ~T3_E~0); 105#L529-1true assume !(0 == ~T4_E~0); 321#L534-1true assume !(0 == ~E_M~0); 254#L539-1true assume !(0 == ~E_1~0); 287#L544-1true assume !(0 == ~E_2~0); 288#L549-1true assume !(0 == ~E_3~0); 326#L554-1true assume 0 == ~E_4~0;~E_4~0 := 1; 35#L559-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 170#L250true assume 1 == ~m_pc~0; 391#L251true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 319#L261true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 114#is_master_triggered_returnLabel#1true activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 291#L637true assume !(0 != activate_threads_~tmp~1#1); 38#L637-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 49#L269true assume !(1 == ~t1_pc~0); 102#L269-2true is_transmit1_triggered_~__retres1~1#1 := 0; 176#L280true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 32#is_transmit1_triggered_returnLabel#1true activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 320#L645true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 144#L645-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 227#L288true assume 1 == ~t2_pc~0; 351#L289true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 239#L299true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 208#is_transmit2_triggered_returnLabel#1true activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 249#L653true assume !(0 != activate_threads_~tmp___1~0#1); 302#L653-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 161#L307true assume !(1 == ~t3_pc~0); 219#L307-2true is_transmit3_triggered_~__retres1~3#1 := 0; 201#L318true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10#is_transmit3_triggered_returnLabel#1true activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 297#L661true assume !(0 != activate_threads_~tmp___2~0#1); 125#L661-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 344#L326true assume 1 == ~t4_pc~0; 337#L327true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 159#L337true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 60#is_transmit4_triggered_returnLabel#1true activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 298#L669true assume !(0 != activate_threads_~tmp___3~0#1); 252#L669-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 293#L572true assume !(1 == ~M_E~0); 338#L572-2true assume !(1 == ~T1_E~0); 42#L577-1true assume !(1 == ~T2_E~0); 234#L582-1true assume !(1 == ~T3_E~0); 242#L587-1true assume !(1 == ~T4_E~0); 370#L592-1true assume !(1 == ~E_M~0); 12#L597-1true assume 1 == ~E_1~0;~E_1~0 := 2; 412#L602-1true assume !(1 == ~E_2~0); 138#L607-1true assume !(1 == ~E_3~0); 416#L612-1true assume !(1 == ~E_4~0); 104#L617-1true assume { :end_inline_reset_delta_events } true; 430#L803-2true [2022-12-13 20:37:50,512 INFO L750 eck$LassoCheckResult]: Loop: 430#L803-2true assume !false; 214#L804true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 192#L489true assume !true; 64#eval_returnLabel#1true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 303#update_channels_returnLabel#2true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 189#L514-3true assume 0 == ~M_E~0;~M_E~0 := 1; 150#L514-5true assume !(0 == ~T1_E~0); 309#L519-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 232#L524-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 86#L529-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 168#L534-3true assume 0 == ~E_M~0;~E_M~0 := 1; 7#L539-3true assume 0 == ~E_1~0;~E_1~0 := 1; 324#L544-3true assume 0 == ~E_2~0;~E_2~0 := 1; 396#L549-3true assume 0 == ~E_3~0;~E_3~0 := 1; 118#L554-3true assume !(0 == ~E_4~0); 186#L559-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 264#L250-18true assume 1 == ~m_pc~0; 224#L251-6true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 199#L261-6true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 135#is_master_triggered_returnLabel#7true activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 262#L637-18true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 91#L637-20true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 27#L269-18true assume 1 == ~t1_pc~0; 190#L270-6true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 68#L280-6true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 362#is_transmit1_triggered_returnLabel#7true activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 178#L645-18true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 281#L645-20true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 110#L288-18true assume 1 == ~t2_pc~0; 97#L289-6true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 11#L299-6true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 198#is_transmit2_triggered_returnLabel#7true activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 166#L653-18true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 95#L653-20true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 306#L307-18true assume 1 == ~t3_pc~0; 139#L308-6true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 120#L318-6true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 218#is_transmit3_triggered_returnLabel#7true activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 84#L661-18true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 341#L661-20true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 265#L326-18true assume !(1 == ~t4_pc~0); 354#L326-20true is_transmit4_triggered_~__retres1~4#1 := 0; 276#L337-6true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 151#is_transmit4_triggered_returnLabel#7true activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 5#L669-18true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 366#L669-20true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 420#L572-3true assume 1 == ~M_E~0;~M_E~0 := 2; 93#L572-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 109#L577-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 34#L582-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 369#L587-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 185#L592-3true assume 1 == ~E_M~0;~E_M~0 := 2; 240#L597-3true assume !(1 == ~E_1~0); 130#L602-3true assume 1 == ~E_2~0;~E_2~0 := 2; 314#L607-3true assume 1 == ~E_3~0;~E_3~0 := 2; 100#L612-3true assume 1 == ~E_4~0;~E_4~0 := 2; 187#L617-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 134#L386-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 123#L413-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 181#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 160#L822true assume !(0 == start_simulation_~tmp~3#1); 260#L822-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 390#L386-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 402#L413-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 31#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1; 20#L777true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 194#L784true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 315#stop_simulation_returnLabel#1true start_simulation_#t~ret18#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 307#L835true assume !(0 != start_simulation_~tmp___0~1#1); 430#L803-2true [2022-12-13 20:37:50,517 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 20:37:50,518 INFO L85 PathProgramCache]: Analyzing trace with hash 1553035642, now seen corresponding path program 1 times [2022-12-13 20:37:50,527 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 20:37:50,527 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [844229648] [2022-12-13 20:37:50,528 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:37:50,528 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 20:37:50,597 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 20:37:50,673 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 20:37:50,673 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 20:37:50,674 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [844229648] [2022-12-13 20:37:50,674 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [844229648] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 20:37:50,674 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 20:37:50,675 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 20:37:50,676 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [742622814] [2022-12-13 20:37:50,676 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 20:37:50,680 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 20:37:50,681 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 20:37:50,681 INFO L85 PathProgramCache]: Analyzing trace with hash -429228071, now seen corresponding path program 1 times [2022-12-13 20:37:50,681 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 20:37:50,681 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2086540855] [2022-12-13 20:37:50,682 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:37:50,682 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 20:37:50,689 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 20:37:50,707 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 20:37:50,707 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 20:37:50,707 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2086540855] [2022-12-13 20:37:50,708 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2086540855] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 20:37:50,708 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 20:37:50,708 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-12-13 20:37:50,708 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1728450170] [2022-12-13 20:37:50,708 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 20:37:50,709 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 20:37:50,709 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 20:37:50,732 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 20:37:50,732 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 20:37:50,734 INFO L87 Difference]: Start difference. First operand has 431 states, 430 states have (on average 1.5325581395348837) internal successors, (659), 430 states have internal predecessors, (659), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 20:37:50,768 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 20:37:50,768 INFO L93 Difference]: Finished difference Result 430 states and 642 transitions. [2022-12-13 20:37:50,769 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 430 states and 642 transitions. [2022-12-13 20:37:50,773 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 358 [2022-12-13 20:37:50,777 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 430 states to 425 states and 637 transitions. [2022-12-13 20:37:50,778 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 425 [2022-12-13 20:37:50,779 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 425 [2022-12-13 20:37:50,779 INFO L73 IsDeterministic]: Start isDeterministic. Operand 425 states and 637 transitions. [2022-12-13 20:37:50,781 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 20:37:50,781 INFO L218 hiAutomatonCegarLoop]: Abstraction has 425 states and 637 transitions. [2022-12-13 20:37:50,794 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 425 states and 637 transitions. [2022-12-13 20:37:50,809 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 425 to 425. [2022-12-13 20:37:50,810 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 425 states, 425 states have (on average 1.4988235294117647) internal successors, (637), 424 states have internal predecessors, (637), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 20:37:50,811 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 425 states to 425 states and 637 transitions. [2022-12-13 20:37:50,811 INFO L240 hiAutomatonCegarLoop]: Abstraction has 425 states and 637 transitions. [2022-12-13 20:37:50,812 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 20:37:50,815 INFO L428 stractBuchiCegarLoop]: Abstraction has 425 states and 637 transitions. [2022-12-13 20:37:50,815 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2022-12-13 20:37:50,815 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 425 states and 637 transitions. [2022-12-13 20:37:50,817 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 358 [2022-12-13 20:37:50,817 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 20:37:50,817 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 20:37:50,818 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 20:37:50,818 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 20:37:50,818 INFO L748 eck$LassoCheckResult]: Stem: 1096#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 1097#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 1195#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1196#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1015#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 1016#L353-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1262#L358-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 958#L363-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 959#L368-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1090#L373-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 986#L514 assume !(0 == ~M_E~0); 987#L514-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1276#L519-1 assume !(0 == ~T2_E~0); 946#L524-1 assume !(0 == ~T3_E~0); 947#L529-1 assume !(0 == ~T4_E~0); 1068#L534-1 assume !(0 == ~E_M~0); 1240#L539-1 assume !(0 == ~E_1~0); 1241#L544-1 assume !(0 == ~E_2~0); 1260#L549-1 assume !(0 == ~E_3~0); 1261#L554-1 assume 0 == ~E_4~0;~E_4~0 := 1; 941#L559-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 942#L250 assume 1 == ~m_pc~0; 1154#L251 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1264#L261 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1080#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1081#L637 assume !(0 != activate_threads_~tmp~1#1); 948#L637-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 949#L269 assume !(1 == ~t1_pc~0); 886#L269-2 is_transmit1_triggered_~__retres1~1#1 := 0; 885#L280 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 936#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 937#L645 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1123#L645-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1124#L288 assume 1 == ~t2_pc~0; 1216#L289 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1120#L299 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1200#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1201#L653 assume !(0 != activate_threads_~tmp___1~0#1); 1236#L653-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1144#L307 assume !(1 == ~t3_pc~0); 1083#L307-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1084#L318 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 889#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 890#L661 assume !(0 != activate_threads_~tmp___2~0#1); 1094#L661-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1095#L326 assume 1 == ~t4_pc~0; 1284#L327 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 902#L337 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 990#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 991#L669 assume !(0 != activate_threads_~tmp___3~0#1); 1237#L669-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1238#L572 assume !(1 == ~M_E~0); 1265#L572-2 assume !(1 == ~T1_E~0); 954#L577-1 assume !(1 == ~T2_E~0); 955#L582-1 assume !(1 == ~T3_E~0); 1220#L587-1 assume !(1 == ~T4_E~0); 1229#L592-1 assume !(1 == ~E_M~0); 893#L597-1 assume 1 == ~E_1~0;~E_1~0 := 2; 894#L602-1 assume !(1 == ~E_2~0); 1116#L607-1 assume !(1 == ~E_3~0); 1117#L612-1 assume !(1 == ~E_4~0); 1066#L617-1 assume { :end_inline_reset_delta_events } true; 1067#L803-2 [2022-12-13 20:37:50,819 INFO L750 eck$LassoCheckResult]: Loop: 1067#L803-2 assume !false; 1207#L804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 979#L489 assume !false; 1178#L424 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 1145#L386 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 1001#L413 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 1063#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1209#L428 assume !(0 != eval_~tmp~0#1); 996#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 997#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1177#L514-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1129#L514-5 assume !(0 == ~T1_E~0); 1130#L519-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1219#L524-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1038#L529-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1039#L534-3 assume 0 == ~E_M~0;~E_M~0 := 1; 882#L539-3 assume 0 == ~E_1~0;~E_1~0 := 1; 883#L544-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1278#L549-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1087#L554-3 assume !(0 == ~E_4~0); 1088#L559-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1176#L250-18 assume 1 == ~m_pc~0; 1214#L251-6 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1187#L261-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1112#is_master_triggered_returnLabel#7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1113#L637-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1047#L637-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 925#L269-18 assume !(1 == ~t1_pc~0); 926#L269-20 is_transmit1_triggered_~__retres1~1#1 := 0; 1003#L280-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1004#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1167#L645-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1168#L645-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1073#L288-18 assume 1 == ~t2_pc~0; 1058#L289-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 891#L299-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 892#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1153#L653-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1053#L653-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1054#L307-18 assume !(1 == ~t3_pc~0); 1024#L307-20 is_transmit3_triggered_~__retres1~3#1 := 0; 1025#L318-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1089#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1035#L661-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1036#L661-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1247#L326-18 assume 1 == ~t4_pc~0; 1248#L327-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1255#L337-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1131#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 878#L669-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 879#L669-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1290#L572-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1050#L572-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1051#L577-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 939#L582-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 940#L587-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1174#L592-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1175#L597-3 assume !(1 == ~E_1~0); 1103#L602-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1104#L607-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1061#L612-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1062#L617-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 1110#L386-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 1077#L413-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 1092#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 1142#L822 assume !(0 == start_simulation_~tmp~3#1); 1143#L822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 1244#L386-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 1182#L413-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 935#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1; 910#L777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 911#L784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1180#stop_simulation_returnLabel#1 start_simulation_#t~ret18#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 1272#L835 assume !(0 != start_simulation_~tmp___0~1#1); 1067#L803-2 [2022-12-13 20:37:50,819 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 20:37:50,819 INFO L85 PathProgramCache]: Analyzing trace with hash 1119306556, now seen corresponding path program 1 times [2022-12-13 20:37:50,819 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 20:37:50,820 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [448941583] [2022-12-13 20:37:50,820 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:37:50,820 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 20:37:50,828 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 20:37:50,862 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 20:37:50,862 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 20:37:50,862 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [448941583] [2022-12-13 20:37:50,863 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [448941583] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 20:37:50,863 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 20:37:50,863 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 20:37:50,863 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [174171019] [2022-12-13 20:37:50,863 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 20:37:50,863 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 20:37:50,864 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 20:37:50,864 INFO L85 PathProgramCache]: Analyzing trace with hash 663831791, now seen corresponding path program 1 times [2022-12-13 20:37:50,864 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 20:37:50,864 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [807672458] [2022-12-13 20:37:50,864 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:37:50,864 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 20:37:50,878 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 20:37:50,926 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 20:37:50,926 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 20:37:50,926 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [807672458] [2022-12-13 20:37:50,926 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [807672458] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 20:37:50,926 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 20:37:50,926 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 20:37:50,927 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1717835166] [2022-12-13 20:37:50,927 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 20:37:50,927 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 20:37:50,927 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 20:37:50,927 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 20:37:50,927 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 20:37:50,928 INFO L87 Difference]: Start difference. First operand 425 states and 637 transitions. cyclomatic complexity: 213 Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 20:37:50,943 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 20:37:50,943 INFO L93 Difference]: Finished difference Result 425 states and 636 transitions. [2022-12-13 20:37:50,943 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 425 states and 636 transitions. [2022-12-13 20:37:50,945 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 358 [2022-12-13 20:37:50,947 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 425 states to 425 states and 636 transitions. [2022-12-13 20:37:50,947 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 425 [2022-12-13 20:37:50,948 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 425 [2022-12-13 20:37:50,949 INFO L73 IsDeterministic]: Start isDeterministic. Operand 425 states and 636 transitions. [2022-12-13 20:37:50,951 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 20:37:50,952 INFO L218 hiAutomatonCegarLoop]: Abstraction has 425 states and 636 transitions. [2022-12-13 20:37:50,953 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 425 states and 636 transitions. [2022-12-13 20:37:50,960 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 425 to 425. [2022-12-13 20:37:50,961 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 425 states, 425 states have (on average 1.4964705882352942) internal successors, (636), 424 states have internal predecessors, (636), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 20:37:50,962 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 425 states to 425 states and 636 transitions. [2022-12-13 20:37:50,962 INFO L240 hiAutomatonCegarLoop]: Abstraction has 425 states and 636 transitions. [2022-12-13 20:37:50,962 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 20:37:50,963 INFO L428 stractBuchiCegarLoop]: Abstraction has 425 states and 636 transitions. [2022-12-13 20:37:50,963 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2022-12-13 20:37:50,963 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 425 states and 636 transitions. [2022-12-13 20:37:50,965 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 358 [2022-12-13 20:37:50,965 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 20:37:50,965 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 20:37:50,966 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 20:37:50,966 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 20:37:50,966 INFO L748 eck$LassoCheckResult]: Stem: 1953#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 1954#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 2052#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2053#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1872#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 1873#L353-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2119#L358-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1815#L363-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1816#L368-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1947#L373-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1843#L514 assume !(0 == ~M_E~0); 1844#L514-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2133#L519-1 assume !(0 == ~T2_E~0); 1803#L524-1 assume !(0 == ~T3_E~0); 1804#L529-1 assume !(0 == ~T4_E~0); 1925#L534-1 assume !(0 == ~E_M~0); 2097#L539-1 assume !(0 == ~E_1~0); 2098#L544-1 assume !(0 == ~E_2~0); 2117#L549-1 assume !(0 == ~E_3~0); 2118#L554-1 assume 0 == ~E_4~0;~E_4~0 := 1; 1798#L559-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1799#L250 assume 1 == ~m_pc~0; 2011#L251 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 2121#L261 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1937#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1938#L637 assume !(0 != activate_threads_~tmp~1#1); 1805#L637-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1806#L269 assume !(1 == ~t1_pc~0); 1743#L269-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1742#L280 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1793#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1794#L645 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1980#L645-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1981#L288 assume 1 == ~t2_pc~0; 2073#L289 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1977#L299 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2057#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2058#L653 assume !(0 != activate_threads_~tmp___1~0#1); 2093#L653-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2001#L307 assume !(1 == ~t3_pc~0); 1940#L307-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1941#L318 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1746#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1747#L661 assume !(0 != activate_threads_~tmp___2~0#1); 1951#L661-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1952#L326 assume 1 == ~t4_pc~0; 2141#L327 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1759#L337 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1847#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1848#L669 assume !(0 != activate_threads_~tmp___3~0#1); 2094#L669-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2095#L572 assume !(1 == ~M_E~0); 2122#L572-2 assume !(1 == ~T1_E~0); 1811#L577-1 assume !(1 == ~T2_E~0); 1812#L582-1 assume !(1 == ~T3_E~0); 2077#L587-1 assume !(1 == ~T4_E~0); 2086#L592-1 assume !(1 == ~E_M~0); 1750#L597-1 assume 1 == ~E_1~0;~E_1~0 := 2; 1751#L602-1 assume !(1 == ~E_2~0); 1973#L607-1 assume !(1 == ~E_3~0); 1974#L612-1 assume !(1 == ~E_4~0); 1923#L617-1 assume { :end_inline_reset_delta_events } true; 1924#L803-2 [2022-12-13 20:37:50,967 INFO L750 eck$LassoCheckResult]: Loop: 1924#L803-2 assume !false; 2064#L804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1836#L489 assume !false; 2035#L424 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 2002#L386 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 1858#L413 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 1920#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 2066#L428 assume !(0 != eval_~tmp~0#1); 1853#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1854#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2034#L514-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1986#L514-5 assume !(0 == ~T1_E~0); 1987#L519-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2076#L524-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1895#L529-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1896#L534-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1739#L539-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1740#L544-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2135#L549-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1944#L554-3 assume !(0 == ~E_4~0); 1945#L559-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2033#L250-18 assume 1 == ~m_pc~0; 2071#L251-6 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 2044#L261-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1969#is_master_triggered_returnLabel#7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1970#L637-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1904#L637-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1782#L269-18 assume !(1 == ~t1_pc~0); 1783#L269-20 is_transmit1_triggered_~__retres1~1#1 := 0; 1860#L280-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1861#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 2024#L645-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2025#L645-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1930#L288-18 assume 1 == ~t2_pc~0; 1915#L289-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1748#L299-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1749#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2010#L653-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1910#L653-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1911#L307-18 assume 1 == ~t3_pc~0; 1975#L308-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1882#L318-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1946#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1892#L661-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1893#L661-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2104#L326-18 assume 1 == ~t4_pc~0; 2105#L327-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2112#L337-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1988#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1735#L669-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1736#L669-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2147#L572-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1907#L572-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1908#L577-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1796#L582-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1797#L587-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2031#L592-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2032#L597-3 assume !(1 == ~E_1~0); 1960#L602-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1961#L607-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1918#L612-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1919#L617-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 1967#L386-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 1934#L413-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 1949#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 1999#L822 assume !(0 == start_simulation_~tmp~3#1); 2000#L822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 2101#L386-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 2039#L413-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 1792#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1; 1767#L777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1768#L784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2037#stop_simulation_returnLabel#1 start_simulation_#t~ret18#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 2129#L835 assume !(0 != start_simulation_~tmp___0~1#1); 1924#L803-2 [2022-12-13 20:37:50,967 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 20:37:50,967 INFO L85 PathProgramCache]: Analyzing trace with hash 1078631806, now seen corresponding path program 1 times [2022-12-13 20:37:50,967 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 20:37:50,967 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1873965643] [2022-12-13 20:37:50,967 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:37:50,968 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 20:37:50,975 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 20:37:50,998 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 20:37:50,998 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 20:37:50,998 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1873965643] [2022-12-13 20:37:50,998 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1873965643] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 20:37:50,998 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 20:37:50,998 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 20:37:50,999 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1511775228] [2022-12-13 20:37:50,999 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 20:37:50,999 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 20:37:51,000 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 20:37:51,000 INFO L85 PathProgramCache]: Analyzing trace with hash -387617298, now seen corresponding path program 1 times [2022-12-13 20:37:51,000 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 20:37:51,000 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [267140534] [2022-12-13 20:37:51,000 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:37:51,000 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 20:37:51,010 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 20:37:51,045 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 20:37:51,045 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 20:37:51,045 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [267140534] [2022-12-13 20:37:51,045 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [267140534] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 20:37:51,045 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 20:37:51,045 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 20:37:51,046 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1241828800] [2022-12-13 20:37:51,046 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 20:37:51,046 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 20:37:51,046 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 20:37:51,047 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 20:37:51,047 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 20:37:51,047 INFO L87 Difference]: Start difference. First operand 425 states and 636 transitions. cyclomatic complexity: 212 Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 20:37:51,056 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 20:37:51,056 INFO L93 Difference]: Finished difference Result 425 states and 635 transitions. [2022-12-13 20:37:51,056 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 425 states and 635 transitions. [2022-12-13 20:37:51,058 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 358 [2022-12-13 20:37:51,059 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 425 states to 425 states and 635 transitions. [2022-12-13 20:37:51,060 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 425 [2022-12-13 20:37:51,060 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 425 [2022-12-13 20:37:51,060 INFO L73 IsDeterministic]: Start isDeterministic. Operand 425 states and 635 transitions. [2022-12-13 20:37:51,061 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 20:37:51,061 INFO L218 hiAutomatonCegarLoop]: Abstraction has 425 states and 635 transitions. [2022-12-13 20:37:51,061 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 425 states and 635 transitions. [2022-12-13 20:37:51,066 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 425 to 425. [2022-12-13 20:37:51,067 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 425 states, 425 states have (on average 1.4941176470588236) internal successors, (635), 424 states have internal predecessors, (635), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 20:37:51,068 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 425 states to 425 states and 635 transitions. [2022-12-13 20:37:51,068 INFO L240 hiAutomatonCegarLoop]: Abstraction has 425 states and 635 transitions. [2022-12-13 20:37:51,068 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 20:37:51,069 INFO L428 stractBuchiCegarLoop]: Abstraction has 425 states and 635 transitions. [2022-12-13 20:37:51,069 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2022-12-13 20:37:51,069 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 425 states and 635 transitions. [2022-12-13 20:37:51,070 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 358 [2022-12-13 20:37:51,070 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 20:37:51,070 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 20:37:51,071 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 20:37:51,071 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 20:37:51,071 INFO L748 eck$LassoCheckResult]: Stem: 2810#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 2811#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 2909#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2910#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2729#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 2730#L353-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2976#L358-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2672#L363-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2673#L368-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2804#L373-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2700#L514 assume !(0 == ~M_E~0); 2701#L514-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2990#L519-1 assume !(0 == ~T2_E~0); 2660#L524-1 assume !(0 == ~T3_E~0); 2661#L529-1 assume !(0 == ~T4_E~0); 2782#L534-1 assume !(0 == ~E_M~0); 2954#L539-1 assume !(0 == ~E_1~0); 2955#L544-1 assume !(0 == ~E_2~0); 2974#L549-1 assume !(0 == ~E_3~0); 2975#L554-1 assume 0 == ~E_4~0;~E_4~0 := 1; 2655#L559-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2656#L250 assume 1 == ~m_pc~0; 2868#L251 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 2978#L261 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2794#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 2795#L637 assume !(0 != activate_threads_~tmp~1#1); 2662#L637-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2663#L269 assume !(1 == ~t1_pc~0); 2600#L269-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2599#L280 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2650#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 2651#L645 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2837#L645-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2838#L288 assume 1 == ~t2_pc~0; 2930#L289 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2834#L299 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2914#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2915#L653 assume !(0 != activate_threads_~tmp___1~0#1); 2950#L653-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2858#L307 assume !(1 == ~t3_pc~0); 2797#L307-2 is_transmit3_triggered_~__retres1~3#1 := 0; 2798#L318 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2603#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2604#L661 assume !(0 != activate_threads_~tmp___2~0#1); 2808#L661-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2809#L326 assume 1 == ~t4_pc~0; 2998#L327 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2616#L337 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2704#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2705#L669 assume !(0 != activate_threads_~tmp___3~0#1); 2951#L669-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2952#L572 assume !(1 == ~M_E~0); 2979#L572-2 assume !(1 == ~T1_E~0); 2668#L577-1 assume !(1 == ~T2_E~0); 2669#L582-1 assume !(1 == ~T3_E~0); 2934#L587-1 assume !(1 == ~T4_E~0); 2943#L592-1 assume !(1 == ~E_M~0); 2607#L597-1 assume 1 == ~E_1~0;~E_1~0 := 2; 2608#L602-1 assume !(1 == ~E_2~0); 2830#L607-1 assume !(1 == ~E_3~0); 2831#L612-1 assume !(1 == ~E_4~0); 2780#L617-1 assume { :end_inline_reset_delta_events } true; 2781#L803-2 [2022-12-13 20:37:51,071 INFO L750 eck$LassoCheckResult]: Loop: 2781#L803-2 assume !false; 2921#L804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2693#L489 assume !false; 2892#L424 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 2859#L386 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 2715#L413 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 2777#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 2923#L428 assume !(0 != eval_~tmp~0#1); 2710#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2711#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2891#L514-3 assume 0 == ~M_E~0;~M_E~0 := 1; 2843#L514-5 assume !(0 == ~T1_E~0); 2844#L519-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2933#L524-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2752#L529-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2753#L534-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2596#L539-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2597#L544-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2992#L549-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2801#L554-3 assume !(0 == ~E_4~0); 2802#L559-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2890#L250-18 assume 1 == ~m_pc~0; 2928#L251-6 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 2901#L261-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2826#is_master_triggered_returnLabel#7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 2827#L637-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2761#L637-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2639#L269-18 assume !(1 == ~t1_pc~0); 2640#L269-20 is_transmit1_triggered_~__retres1~1#1 := 0; 2717#L280-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2718#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 2881#L645-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2882#L645-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2787#L288-18 assume 1 == ~t2_pc~0; 2772#L289-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2605#L299-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2606#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2867#L653-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2767#L653-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2768#L307-18 assume 1 == ~t3_pc~0; 2832#L308-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 2739#L318-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2803#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2749#L661-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2750#L661-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2961#L326-18 assume 1 == ~t4_pc~0; 2962#L327-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2969#L337-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2845#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2592#L669-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 2593#L669-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3004#L572-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2764#L572-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2765#L577-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2653#L582-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2654#L587-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2888#L592-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2889#L597-3 assume !(1 == ~E_1~0); 2817#L602-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2818#L607-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2775#L612-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2776#L617-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 2824#L386-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 2791#L413-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 2806#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 2856#L822 assume !(0 == start_simulation_~tmp~3#1); 2857#L822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 2958#L386-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 2896#L413-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 2649#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1; 2624#L777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2625#L784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2894#stop_simulation_returnLabel#1 start_simulation_#t~ret18#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 2986#L835 assume !(0 != start_simulation_~tmp___0~1#1); 2781#L803-2 [2022-12-13 20:37:51,072 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 20:37:51,072 INFO L85 PathProgramCache]: Analyzing trace with hash -308153604, now seen corresponding path program 1 times [2022-12-13 20:37:51,072 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 20:37:51,072 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1551999297] [2022-12-13 20:37:51,072 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:37:51,072 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 20:37:51,079 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 20:37:51,096 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 20:37:51,096 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 20:37:51,096 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1551999297] [2022-12-13 20:37:51,097 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1551999297] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 20:37:51,097 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 20:37:51,097 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 20:37:51,097 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1585586678] [2022-12-13 20:37:51,097 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 20:37:51,097 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 20:37:51,098 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 20:37:51,098 INFO L85 PathProgramCache]: Analyzing trace with hash -387617298, now seen corresponding path program 2 times [2022-12-13 20:37:51,098 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 20:37:51,098 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [47356137] [2022-12-13 20:37:51,098 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:37:51,099 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 20:37:51,108 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 20:37:51,140 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 20:37:51,140 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 20:37:51,141 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [47356137] [2022-12-13 20:37:51,141 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [47356137] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 20:37:51,141 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 20:37:51,141 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 20:37:51,141 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1473734531] [2022-12-13 20:37:51,142 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 20:37:51,142 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 20:37:51,142 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 20:37:51,142 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 20:37:51,143 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 20:37:51,143 INFO L87 Difference]: Start difference. First operand 425 states and 635 transitions. cyclomatic complexity: 211 Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 20:37:51,156 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 20:37:51,156 INFO L93 Difference]: Finished difference Result 425 states and 634 transitions. [2022-12-13 20:37:51,156 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 425 states and 634 transitions. [2022-12-13 20:37:51,159 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 358 [2022-12-13 20:37:51,161 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 425 states to 425 states and 634 transitions. [2022-12-13 20:37:51,161 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 425 [2022-12-13 20:37:51,162 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 425 [2022-12-13 20:37:51,162 INFO L73 IsDeterministic]: Start isDeterministic. Operand 425 states and 634 transitions. [2022-12-13 20:37:51,163 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 20:37:51,163 INFO L218 hiAutomatonCegarLoop]: Abstraction has 425 states and 634 transitions. [2022-12-13 20:37:51,164 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 425 states and 634 transitions. [2022-12-13 20:37:51,169 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 425 to 425. [2022-12-13 20:37:51,170 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 425 states, 425 states have (on average 1.4917647058823529) internal successors, (634), 424 states have internal predecessors, (634), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 20:37:51,172 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 425 states to 425 states and 634 transitions. [2022-12-13 20:37:51,172 INFO L240 hiAutomatonCegarLoop]: Abstraction has 425 states and 634 transitions. [2022-12-13 20:37:51,172 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 20:37:51,173 INFO L428 stractBuchiCegarLoop]: Abstraction has 425 states and 634 transitions. [2022-12-13 20:37:51,173 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2022-12-13 20:37:51,173 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 425 states and 634 transitions. [2022-12-13 20:37:51,175 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 358 [2022-12-13 20:37:51,176 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 20:37:51,176 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 20:37:51,177 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 20:37:51,177 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 20:37:51,177 INFO L748 eck$LassoCheckResult]: Stem: 3667#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 3668#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 3766#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3767#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3586#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 3587#L353-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3834#L358-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3529#L363-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3530#L368-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 3661#L373-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3559#L514 assume !(0 == ~M_E~0); 3560#L514-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3847#L519-1 assume !(0 == ~T2_E~0); 3517#L524-1 assume !(0 == ~T3_E~0); 3518#L529-1 assume !(0 == ~T4_E~0); 3639#L534-1 assume !(0 == ~E_M~0); 3811#L539-1 assume !(0 == ~E_1~0); 3812#L544-1 assume !(0 == ~E_2~0); 3831#L549-1 assume !(0 == ~E_3~0); 3832#L554-1 assume 0 == ~E_4~0;~E_4~0 := 1; 3512#L559-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3513#L250 assume 1 == ~m_pc~0; 3728#L251 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 3836#L261 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3651#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 3652#L637 assume !(0 != activate_threads_~tmp~1#1); 3519#L637-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3520#L269 assume !(1 == ~t1_pc~0); 3457#L269-2 is_transmit1_triggered_~__retres1~1#1 := 0; 3456#L280 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3508#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 3509#L645 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3694#L645-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3695#L288 assume 1 == ~t2_pc~0; 3787#L289 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3691#L299 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3771#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3772#L653 assume !(0 != activate_threads_~tmp___1~0#1); 3807#L653-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3715#L307 assume !(1 == ~t3_pc~0); 3654#L307-2 is_transmit3_triggered_~__retres1~3#1 := 0; 3655#L318 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3460#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 3461#L661 assume !(0 != activate_threads_~tmp___2~0#1); 3665#L661-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3666#L326 assume 1 == ~t4_pc~0; 3855#L327 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3473#L337 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3561#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3562#L669 assume !(0 != activate_threads_~tmp___3~0#1); 3808#L669-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3809#L572 assume !(1 == ~M_E~0); 3835#L572-2 assume !(1 == ~T1_E~0); 3525#L577-1 assume !(1 == ~T2_E~0); 3526#L582-1 assume !(1 == ~T3_E~0); 3791#L587-1 assume !(1 == ~T4_E~0); 3800#L592-1 assume !(1 == ~E_M~0); 3464#L597-1 assume 1 == ~E_1~0;~E_1~0 := 2; 3465#L602-1 assume !(1 == ~E_2~0); 3687#L607-1 assume !(1 == ~E_3~0); 3688#L612-1 assume !(1 == ~E_4~0); 3637#L617-1 assume { :end_inline_reset_delta_events } true; 3638#L803-2 [2022-12-13 20:37:51,178 INFO L750 eck$LassoCheckResult]: Loop: 3638#L803-2 assume !false; 3778#L804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3550#L489 assume !false; 3749#L424 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 3716#L386 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 3572#L413 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 3634#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 3780#L428 assume !(0 != eval_~tmp~0#1); 3567#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3568#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3748#L514-3 assume 0 == ~M_E~0;~M_E~0 := 1; 3700#L514-5 assume !(0 == ~T1_E~0); 3701#L519-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3790#L524-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3609#L529-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3610#L534-3 assume 0 == ~E_M~0;~E_M~0 := 1; 3453#L539-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3454#L544-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3849#L549-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3658#L554-3 assume !(0 == ~E_4~0); 3659#L559-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3747#L250-18 assume 1 == ~m_pc~0; 3785#L251-6 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 3758#L261-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3683#is_master_triggered_returnLabel#7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 3684#L637-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3618#L637-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3496#L269-18 assume !(1 == ~t1_pc~0); 3497#L269-20 is_transmit1_triggered_~__retres1~1#1 := 0; 3574#L280-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3575#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 3738#L645-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3739#L645-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3644#L288-18 assume 1 == ~t2_pc~0; 3629#L289-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3462#L299-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3463#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3724#L653-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3624#L653-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3625#L307-18 assume 1 == ~t3_pc~0; 3689#L308-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3596#L318-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3660#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 3606#L661-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3607#L661-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3818#L326-18 assume 1 == ~t4_pc~0; 3819#L327-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3826#L337-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3702#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3449#L669-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 3450#L669-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3861#L572-3 assume 1 == ~M_E~0;~M_E~0 := 2; 3621#L572-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3622#L577-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3510#L582-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3511#L587-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3745#L592-3 assume 1 == ~E_M~0;~E_M~0 := 2; 3746#L597-3 assume !(1 == ~E_1~0); 3674#L602-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3675#L607-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3632#L612-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3633#L617-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 3681#L386-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 3648#L413-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 3663#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 3713#L822 assume !(0 == start_simulation_~tmp~3#1); 3714#L822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 3815#L386-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 3753#L413-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 3506#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1; 3481#L777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3482#L784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3751#stop_simulation_returnLabel#1 start_simulation_#t~ret18#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 3843#L835 assume !(0 != start_simulation_~tmp___0~1#1); 3638#L803-2 [2022-12-13 20:37:51,178 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 20:37:51,178 INFO L85 PathProgramCache]: Analyzing trace with hash -1184172610, now seen corresponding path program 1 times [2022-12-13 20:37:51,178 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 20:37:51,179 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [664563041] [2022-12-13 20:37:51,179 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:37:51,179 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 20:37:51,188 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 20:37:51,211 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 20:37:51,212 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 20:37:51,212 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [664563041] [2022-12-13 20:37:51,212 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [664563041] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 20:37:51,212 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 20:37:51,212 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-12-13 20:37:51,212 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [760492223] [2022-12-13 20:37:51,212 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 20:37:51,212 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 20:37:51,213 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 20:37:51,213 INFO L85 PathProgramCache]: Analyzing trace with hash -387617298, now seen corresponding path program 3 times [2022-12-13 20:37:51,213 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 20:37:51,213 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1611451561] [2022-12-13 20:37:51,213 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:37:51,213 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 20:37:51,219 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 20:37:51,238 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 20:37:51,238 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 20:37:51,239 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1611451561] [2022-12-13 20:37:51,239 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1611451561] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 20:37:51,239 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 20:37:51,239 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 20:37:51,239 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [132142689] [2022-12-13 20:37:51,239 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 20:37:51,239 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 20:37:51,239 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 20:37:51,240 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 20:37:51,240 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 20:37:51,240 INFO L87 Difference]: Start difference. First operand 425 states and 634 transitions. cyclomatic complexity: 210 Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 2 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 20:37:51,253 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 20:37:51,254 INFO L93 Difference]: Finished difference Result 425 states and 629 transitions. [2022-12-13 20:37:51,254 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 425 states and 629 transitions. [2022-12-13 20:37:51,256 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 358 [2022-12-13 20:37:51,257 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 425 states to 425 states and 629 transitions. [2022-12-13 20:37:51,258 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 425 [2022-12-13 20:37:51,258 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 425 [2022-12-13 20:37:51,258 INFO L73 IsDeterministic]: Start isDeterministic. Operand 425 states and 629 transitions. [2022-12-13 20:37:51,258 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 20:37:51,258 INFO L218 hiAutomatonCegarLoop]: Abstraction has 425 states and 629 transitions. [2022-12-13 20:37:51,259 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 425 states and 629 transitions. [2022-12-13 20:37:51,262 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 425 to 425. [2022-12-13 20:37:51,262 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 425 states, 425 states have (on average 1.48) internal successors, (629), 424 states have internal predecessors, (629), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 20:37:51,263 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 425 states to 425 states and 629 transitions. [2022-12-13 20:37:51,263 INFO L240 hiAutomatonCegarLoop]: Abstraction has 425 states and 629 transitions. [2022-12-13 20:37:51,264 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 20:37:51,264 INFO L428 stractBuchiCegarLoop]: Abstraction has 425 states and 629 transitions. [2022-12-13 20:37:51,264 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2022-12-13 20:37:51,264 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 425 states and 629 transitions. [2022-12-13 20:37:51,266 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 358 [2022-12-13 20:37:51,266 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 20:37:51,266 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 20:37:51,266 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 20:37:51,266 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 20:37:51,267 INFO L748 eck$LassoCheckResult]: Stem: 4524#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 4525#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 4623#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4624#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4443#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 4444#L353-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4690#L358-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4386#L363-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 4387#L368-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 4518#L373-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4414#L514 assume !(0 == ~M_E~0); 4415#L514-2 assume !(0 == ~T1_E~0); 4704#L519-1 assume !(0 == ~T2_E~0); 4374#L524-1 assume !(0 == ~T3_E~0); 4375#L529-1 assume !(0 == ~T4_E~0); 4496#L534-1 assume !(0 == ~E_M~0); 4668#L539-1 assume !(0 == ~E_1~0); 4669#L544-1 assume !(0 == ~E_2~0); 4688#L549-1 assume !(0 == ~E_3~0); 4689#L554-1 assume 0 == ~E_4~0;~E_4~0 := 1; 4369#L559-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4370#L250 assume 1 == ~m_pc~0; 4585#L251 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 4692#L261 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4508#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 4509#L637 assume !(0 != activate_threads_~tmp~1#1); 4376#L637-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4377#L269 assume !(1 == ~t1_pc~0); 4314#L269-2 is_transmit1_triggered_~__retres1~1#1 := 0; 4313#L280 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4364#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 4365#L645 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4551#L645-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4552#L288 assume 1 == ~t2_pc~0; 4644#L289 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4548#L299 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4628#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 4629#L653 assume !(0 != activate_threads_~tmp___1~0#1); 4664#L653-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4572#L307 assume !(1 == ~t3_pc~0); 4511#L307-2 is_transmit3_triggered_~__retres1~3#1 := 0; 4512#L318 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4317#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4318#L661 assume !(0 != activate_threads_~tmp___2~0#1); 4522#L661-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4523#L326 assume 1 == ~t4_pc~0; 4712#L327 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 4330#L337 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4418#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4419#L669 assume !(0 != activate_threads_~tmp___3~0#1); 4665#L669-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4666#L572 assume !(1 == ~M_E~0); 4693#L572-2 assume !(1 == ~T1_E~0); 4382#L577-1 assume !(1 == ~T2_E~0); 4383#L582-1 assume !(1 == ~T3_E~0); 4649#L587-1 assume !(1 == ~T4_E~0); 4658#L592-1 assume !(1 == ~E_M~0); 4321#L597-1 assume 1 == ~E_1~0;~E_1~0 := 2; 4322#L602-1 assume !(1 == ~E_2~0); 4544#L607-1 assume !(1 == ~E_3~0); 4545#L612-1 assume !(1 == ~E_4~0); 4494#L617-1 assume { :end_inline_reset_delta_events } true; 4495#L803-2 [2022-12-13 20:37:51,267 INFO L750 eck$LassoCheckResult]: Loop: 4495#L803-2 assume !false; 4636#L804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4409#L489 assume !false; 4606#L424 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 4573#L386 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 4429#L413 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 4491#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 4637#L428 assume !(0 != eval_~tmp~0#1); 4424#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4425#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4605#L514-3 assume 0 == ~M_E~0;~M_E~0 := 1; 4558#L514-5 assume !(0 == ~T1_E~0); 4559#L519-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4647#L524-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4466#L529-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4467#L534-3 assume 0 == ~E_M~0;~E_M~0 := 1; 4310#L539-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4311#L544-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4706#L549-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4515#L554-3 assume !(0 == ~E_4~0); 4516#L559-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4604#L250-18 assume 1 == ~m_pc~0; 4642#L251-6 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 4615#L261-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4541#is_master_triggered_returnLabel#7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 4542#L637-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4475#L637-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4353#L269-18 assume !(1 == ~t1_pc~0); 4354#L269-20 is_transmit1_triggered_~__retres1~1#1 := 0; 4431#L280-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4432#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 4595#L645-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4596#L645-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4501#L288-18 assume 1 == ~t2_pc~0; 4483#L289-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4319#L299-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4320#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 4581#L653-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4481#L653-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4482#L307-18 assume !(1 == ~t3_pc~0); 4450#L307-20 is_transmit3_triggered_~__retres1~3#1 := 0; 4451#L318-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4517#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4463#L661-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4464#L661-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4675#L326-18 assume 1 == ~t4_pc~0; 4676#L327-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 4683#L337-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4557#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4306#L669-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 4307#L669-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4718#L572-3 assume 1 == ~M_E~0;~M_E~0 := 2; 4476#L572-5 assume !(1 == ~T1_E~0); 4477#L577-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4367#L582-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4368#L587-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4602#L592-3 assume 1 == ~E_M~0;~E_M~0 := 2; 4603#L597-3 assume !(1 == ~E_1~0); 4531#L602-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4532#L607-3 assume 1 == ~E_3~0;~E_3~0 := 2; 4489#L612-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4490#L617-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 4538#L386-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 4505#L413-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 4520#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 4570#L822 assume !(0 == start_simulation_~tmp~3#1); 4571#L822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 4671#L386-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 4610#L413-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 4363#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1; 4338#L777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4339#L784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4607#stop_simulation_returnLabel#1 start_simulation_#t~ret18#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 4700#L835 assume !(0 != start_simulation_~tmp___0~1#1); 4495#L803-2 [2022-12-13 20:37:51,274 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 20:37:51,274 INFO L85 PathProgramCache]: Analyzing trace with hash 1082208576, now seen corresponding path program 1 times [2022-12-13 20:37:51,274 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 20:37:51,274 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [924023796] [2022-12-13 20:37:51,274 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:37:51,274 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 20:37:51,280 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 20:37:51,315 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 20:37:51,315 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 20:37:51,315 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [924023796] [2022-12-13 20:37:51,315 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [924023796] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 20:37:51,315 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 20:37:51,316 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 20:37:51,316 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1082131668] [2022-12-13 20:37:51,316 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 20:37:51,316 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 20:37:51,317 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 20:37:51,317 INFO L85 PathProgramCache]: Analyzing trace with hash 882686509, now seen corresponding path program 1 times [2022-12-13 20:37:51,317 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 20:37:51,317 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [145345754] [2022-12-13 20:37:51,317 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:37:51,317 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 20:37:51,326 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 20:37:51,356 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 20:37:51,356 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 20:37:51,356 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [145345754] [2022-12-13 20:37:51,356 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [145345754] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 20:37:51,356 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 20:37:51,357 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 20:37:51,357 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1834433299] [2022-12-13 20:37:51,357 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 20:37:51,357 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 20:37:51,357 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 20:37:51,358 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 20:37:51,358 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 20:37:51,358 INFO L87 Difference]: Start difference. First operand 425 states and 629 transitions. cyclomatic complexity: 205 Second operand has 4 states, 4 states have (on average 15.5) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 20:37:51,456 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 20:37:51,457 INFO L93 Difference]: Finished difference Result 710 states and 1048 transitions. [2022-12-13 20:37:51,457 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 710 states and 1048 transitions. [2022-12-13 20:37:51,461 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 632 [2022-12-13 20:37:51,464 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 710 states to 710 states and 1048 transitions. [2022-12-13 20:37:51,465 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 710 [2022-12-13 20:37:51,465 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 710 [2022-12-13 20:37:51,465 INFO L73 IsDeterministic]: Start isDeterministic. Operand 710 states and 1048 transitions. [2022-12-13 20:37:51,466 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 20:37:51,466 INFO L218 hiAutomatonCegarLoop]: Abstraction has 710 states and 1048 transitions. [2022-12-13 20:37:51,467 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 710 states and 1048 transitions. [2022-12-13 20:37:51,478 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 710 to 709. [2022-12-13 20:37:51,479 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 709 states, 709 states have (on average 1.4767277856135401) internal successors, (1047), 708 states have internal predecessors, (1047), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 20:37:51,482 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 709 states to 709 states and 1047 transitions. [2022-12-13 20:37:51,482 INFO L240 hiAutomatonCegarLoop]: Abstraction has 709 states and 1047 transitions. [2022-12-13 20:37:51,482 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 20:37:51,483 INFO L428 stractBuchiCegarLoop]: Abstraction has 709 states and 1047 transitions. [2022-12-13 20:37:51,483 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2022-12-13 20:37:51,483 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 709 states and 1047 transitions. [2022-12-13 20:37:51,486 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 632 [2022-12-13 20:37:51,487 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 20:37:51,487 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 20:37:51,488 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 20:37:51,488 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 20:37:51,488 INFO L748 eck$LassoCheckResult]: Stem: 5671#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 5672#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 5774#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5775#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5589#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 5590#L353-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5846#L358-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5531#L363-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 5532#L368-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 5665#L373-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5560#L514 assume !(0 == ~M_E~0); 5561#L514-2 assume !(0 == ~T1_E~0); 5863#L519-1 assume !(0 == ~T2_E~0); 5519#L524-1 assume !(0 == ~T3_E~0); 5520#L529-1 assume !(0 == ~T4_E~0); 5643#L534-1 assume !(0 == ~E_M~0); 5823#L539-1 assume !(0 == ~E_1~0); 5824#L544-1 assume !(0 == ~E_2~0); 5844#L549-1 assume !(0 == ~E_3~0); 5845#L554-1 assume !(0 == ~E_4~0); 5514#L559-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5515#L250 assume 1 == ~m_pc~0; 5733#L251 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 5848#L261 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5655#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 5656#L637 assume !(0 != activate_threads_~tmp~1#1); 5521#L637-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5522#L269 assume !(1 == ~t1_pc~0); 5459#L269-2 is_transmit1_triggered_~__retres1~1#1 := 0; 5458#L280 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5509#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 5510#L645 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 5698#L645-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5699#L288 assume 1 == ~t2_pc~0; 5797#L289 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5695#L299 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5779#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 5780#L653 assume !(0 != activate_threads_~tmp___1~0#1); 5818#L653-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5719#L307 assume !(1 == ~t3_pc~0); 5658#L307-2 is_transmit3_triggered_~__retres1~3#1 := 0; 5659#L318 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5462#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 5463#L661 assume !(0 != activate_threads_~tmp___2~0#1); 5669#L661-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5670#L326 assume 1 == ~t4_pc~0; 5871#L327 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5475#L337 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5564#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 5565#L669 assume !(0 != activate_threads_~tmp___3~0#1); 5820#L669-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5821#L572 assume 1 == ~M_E~0;~M_E~0 := 2; 5849#L572-2 assume !(1 == ~T1_E~0); 5527#L577-1 assume !(1 == ~T2_E~0); 5528#L582-1 assume !(1 == ~T3_E~0); 5803#L587-1 assume !(1 == ~T4_E~0); 5812#L592-1 assume !(1 == ~E_M~0); 5466#L597-1 assume 1 == ~E_1~0;~E_1~0 := 2; 5467#L602-1 assume !(1 == ~E_2~0); 5691#L607-1 assume !(1 == ~E_3~0); 5692#L612-1 assume !(1 == ~E_4~0); 5641#L617-1 assume { :end_inline_reset_delta_events } true; 5642#L803-2 [2022-12-13 20:37:51,488 INFO L750 eck$LassoCheckResult]: Loop: 5642#L803-2 assume !false; 5891#L804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5899#L489 assume !false; 5898#L424 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 5897#L386 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 5637#L413 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 5638#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 5888#L428 assume !(0 != eval_~tmp~0#1); 5889#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5856#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5857#L514-3 assume 0 == ~M_E~0;~M_E~0 := 1; 5705#L514-5 assume !(0 == ~T1_E~0); 5706#L519-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 5801#L524-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5612#L529-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5613#L534-3 assume 0 == ~E_M~0;~E_M~0 := 1; 5455#L539-3 assume 0 == ~E_1~0;~E_1~0 := 1; 5456#L544-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5865#L549-3 assume 0 == ~E_3~0;~E_3~0 := 1; 5662#L554-3 assume !(0 == ~E_4~0); 5663#L559-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5752#L250-18 assume 1 == ~m_pc~0; 5795#L251-6 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 5766#L261-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5688#is_master_triggered_returnLabel#7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 5689#L637-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 5621#L637-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5498#L269-18 assume !(1 == ~t1_pc~0); 5499#L269-20 is_transmit1_triggered_~__retres1~1#1 := 0; 5577#L280-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5578#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 5743#L645-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 5744#L645-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5648#L288-18 assume 1 == ~t2_pc~0; 5629#L289-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5464#L299-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5465#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 5728#L653-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 5627#L653-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5628#L307-18 assume !(1 == ~t3_pc~0); 5596#L307-20 is_transmit3_triggered_~__retres1~3#1 := 0; 5597#L318-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5664#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 5609#L661-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 5610#L661-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5830#L326-18 assume 1 == ~t4_pc~0; 5831#L327-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5838#L337-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5704#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 5451#L669-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 5452#L669-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5878#L572-3 assume 1 == ~M_E~0;~M_E~0 := 2; 5622#L572-5 assume !(1 == ~T1_E~0); 5623#L577-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5512#L582-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 5513#L587-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5750#L592-3 assume 1 == ~E_M~0;~E_M~0 := 2; 5751#L597-3 assume !(1 == ~E_1~0); 5678#L602-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5679#L607-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5635#L612-3 assume 1 == ~E_4~0;~E_4~0 := 2; 5636#L617-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 5753#L386-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 5974#L413-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 5973#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 5972#L822 assume !(0 == start_simulation_~tmp~3#1); 5819#L822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 5826#L386-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 5916#L413-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 5915#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1; 5914#L777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5757#L784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5758#stop_simulation_returnLabel#1 start_simulation_#t~ret18#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 5859#L835 assume !(0 != start_simulation_~tmp___0~1#1); 5642#L803-2 [2022-12-13 20:37:51,489 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 20:37:51,489 INFO L85 PathProgramCache]: Analyzing trace with hash -516249280, now seen corresponding path program 1 times [2022-12-13 20:37:51,489 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 20:37:51,489 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1273040963] [2022-12-13 20:37:51,489 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:37:51,489 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 20:37:51,497 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 20:37:51,531 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 20:37:51,531 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 20:37:51,531 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1273040963] [2022-12-13 20:37:51,532 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1273040963] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 20:37:51,532 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 20:37:51,532 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-12-13 20:37:51,532 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1459255996] [2022-12-13 20:37:51,532 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 20:37:51,532 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 20:37:51,533 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 20:37:51,533 INFO L85 PathProgramCache]: Analyzing trace with hash 882686509, now seen corresponding path program 2 times [2022-12-13 20:37:51,533 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 20:37:51,533 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1493335383] [2022-12-13 20:37:51,533 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:37:51,533 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 20:37:51,541 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 20:37:51,566 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 20:37:51,566 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 20:37:51,566 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1493335383] [2022-12-13 20:37:51,566 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1493335383] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 20:37:51,566 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 20:37:51,566 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 20:37:51,567 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [759408105] [2022-12-13 20:37:51,567 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 20:37:51,567 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 20:37:51,567 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 20:37:51,567 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 20:37:51,567 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 20:37:51,568 INFO L87 Difference]: Start difference. First operand 709 states and 1047 transitions. cyclomatic complexity: 340 Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 2 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 20:37:51,610 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 20:37:51,610 INFO L93 Difference]: Finished difference Result 1322 states and 1928 transitions. [2022-12-13 20:37:51,610 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1322 states and 1928 transitions. [2022-12-13 20:37:51,615 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1244 [2022-12-13 20:37:51,619 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1322 states to 1322 states and 1928 transitions. [2022-12-13 20:37:51,619 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1322 [2022-12-13 20:37:51,620 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1322 [2022-12-13 20:37:51,620 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1322 states and 1928 transitions. [2022-12-13 20:37:51,621 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 20:37:51,621 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1322 states and 1928 transitions. [2022-12-13 20:37:51,622 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1322 states and 1928 transitions. [2022-12-13 20:37:51,635 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1322 to 1254. [2022-12-13 20:37:51,636 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1254 states, 1254 states have (on average 1.4625199362041468) internal successors, (1834), 1253 states have internal predecessors, (1834), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 20:37:51,639 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1254 states to 1254 states and 1834 transitions. [2022-12-13 20:37:51,639 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1254 states and 1834 transitions. [2022-12-13 20:37:51,639 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 20:37:51,640 INFO L428 stractBuchiCegarLoop]: Abstraction has 1254 states and 1834 transitions. [2022-12-13 20:37:51,640 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2022-12-13 20:37:51,640 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1254 states and 1834 transitions. [2022-12-13 20:37:51,644 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1176 [2022-12-13 20:37:51,644 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 20:37:51,644 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 20:37:51,645 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 20:37:51,645 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 20:37:51,645 INFO L748 eck$LassoCheckResult]: Stem: 7714#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 7715#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 7821#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 7822#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7630#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 7631#L353-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7916#L358-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 7571#L363-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 7572#L368-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 7707#L373-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7601#L514 assume !(0 == ~M_E~0); 7602#L514-2 assume !(0 == ~T1_E~0); 7943#L519-1 assume !(0 == ~T2_E~0); 7559#L524-1 assume !(0 == ~T3_E~0); 7560#L529-1 assume !(0 == ~T4_E~0); 7685#L534-1 assume !(0 == ~E_M~0); 7879#L539-1 assume !(0 == ~E_1~0); 7880#L544-1 assume !(0 == ~E_2~0); 7914#L549-1 assume !(0 == ~E_3~0); 7915#L554-1 assume !(0 == ~E_4~0); 7554#L559-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7555#L250 assume !(1 == ~m_pc~0); 7779#L250-2 is_master_triggered_~__retres1~0#1 := 0; 7918#L261 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7697#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 7698#L637 assume !(0 != activate_threads_~tmp~1#1); 7561#L637-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7562#L269 assume !(1 == ~t1_pc~0); 7497#L269-2 is_transmit1_triggered_~__retres1~1#1 := 0; 7496#L280 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7549#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 7550#L645 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 7746#L645-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7747#L288 assume 1 == ~t2_pc~0; 7848#L289 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 7742#L299 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7826#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 7827#L653 assume !(0 != activate_threads_~tmp___1~0#1); 7873#L653-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7769#L307 assume !(1 == ~t3_pc~0); 7700#L307-2 is_transmit3_triggered_~__retres1~3#1 := 0; 7701#L318 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7500#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 7501#L661 assume !(0 != activate_threads_~tmp___2~0#1); 7712#L661-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7713#L326 assume 1 == ~t4_pc~0; 7953#L327 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 7515#L337 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7605#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 7606#L669 assume !(0 != activate_threads_~tmp___3~0#1); 7876#L669-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7877#L572 assume 1 == ~M_E~0;~M_E~0 := 2; 7919#L572-2 assume !(1 == ~T1_E~0); 7954#L577-1 assume !(1 == ~T2_E~0); 7853#L582-1 assume !(1 == ~T3_E~0); 7854#L587-1 assume !(1 == ~T4_E~0); 7864#L592-1 assume !(1 == ~E_M~0); 7504#L597-1 assume 1 == ~E_1~0;~E_1~0 := 2; 7505#L602-1 assume !(1 == ~E_2~0); 8404#L607-1 assume !(1 == ~E_3~0); 7992#L612-1 assume !(1 == ~E_4~0); 7993#L617-1 assume { :end_inline_reset_delta_events } true; 8394#L803-2 [2022-12-13 20:37:51,645 INFO L750 eck$LassoCheckResult]: Loop: 8394#L803-2 assume !false; 8389#L804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 8388#L489 assume !false; 8387#L424 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 8386#L386 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 8381#L413 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 8380#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 8041#L428 assume !(0 != eval_~tmp~0#1); 8043#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 8596#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 8595#L514-3 assume 0 == ~M_E~0;~M_E~0 := 1; 8594#L514-5 assume !(0 == ~T1_E~0); 8593#L519-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 8592#L524-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 8591#L529-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 8590#L534-3 assume 0 == ~E_M~0;~E_M~0 := 1; 8589#L539-3 assume 0 == ~E_1~0;~E_1~0 := 1; 8588#L544-3 assume 0 == ~E_2~0;~E_2~0 := 1; 8587#L549-3 assume 0 == ~E_3~0;~E_3~0 := 1; 8586#L554-3 assume !(0 == ~E_4~0); 8585#L559-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8584#L250-18 assume !(1 == ~m_pc~0); 8583#L250-20 is_master_triggered_~__retres1~0#1 := 0; 8581#L261-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8579#is_master_triggered_returnLabel#7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 8577#L637-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 8575#L637-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8573#L269-18 assume 1 == ~t1_pc~0; 8569#L270-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 8567#L280-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8565#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 8563#L645-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 8561#L645-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8559#L288-18 assume 1 == ~t2_pc~0; 8555#L289-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 8553#L299-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8551#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 8549#L653-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 8547#L653-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8545#L307-18 assume !(1 == ~t3_pc~0); 8541#L307-20 is_transmit3_triggered_~__retres1~3#1 := 0; 8539#L318-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8537#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 8535#L661-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 8533#L661-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8531#L326-18 assume !(1 == ~t4_pc~0); 8528#L326-20 is_transmit4_triggered_~__retres1~4#1 := 0; 8525#L337-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8523#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 8521#L669-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 8519#L669-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8518#L572-3 assume 1 == ~M_E~0;~M_E~0 := 2; 8516#L572-5 assume !(1 == ~T1_E~0); 8515#L577-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 8514#L582-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 8513#L587-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8512#L592-3 assume 1 == ~E_M~0;~E_M~0 := 2; 8511#L597-3 assume !(1 == ~E_1~0); 8510#L602-3 assume 1 == ~E_2~0;~E_2~0 := 2; 8509#L607-3 assume 1 == ~E_3~0;~E_3~0 := 2; 8508#L612-3 assume 1 == ~E_4~0;~E_4~0 := 2; 7678#L617-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 8506#L386-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 8502#L413-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 8501#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 8499#L822 assume !(0 == start_simulation_~tmp~3#1); 7875#L822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 8488#L386-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 8485#L413-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 8483#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1; 8481#L777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 8406#L784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 8405#stop_simulation_returnLabel#1 start_simulation_#t~ret18#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 8399#L835 assume !(0 != start_simulation_~tmp___0~1#1); 8394#L803-2 [2022-12-13 20:37:51,646 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 20:37:51,646 INFO L85 PathProgramCache]: Analyzing trace with hash -1001423999, now seen corresponding path program 1 times [2022-12-13 20:37:51,646 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 20:37:51,646 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [751186911] [2022-12-13 20:37:51,646 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:37:51,646 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 20:37:51,654 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 20:37:51,687 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 20:37:51,688 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 20:37:51,688 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [751186911] [2022-12-13 20:37:51,688 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [751186911] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 20:37:51,688 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 20:37:51,688 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-12-13 20:37:51,688 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1848585315] [2022-12-13 20:37:51,689 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 20:37:51,689 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 20:37:51,689 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 20:37:51,689 INFO L85 PathProgramCache]: Analyzing trace with hash 1530675502, now seen corresponding path program 1 times [2022-12-13 20:37:51,689 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 20:37:51,690 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2027799739] [2022-12-13 20:37:51,690 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:37:51,690 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 20:37:51,704 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 20:37:51,722 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 20:37:51,723 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 20:37:51,723 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2027799739] [2022-12-13 20:37:51,723 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2027799739] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 20:37:51,723 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 20:37:51,723 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 20:37:51,723 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2111528674] [2022-12-13 20:37:51,723 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 20:37:51,724 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 20:37:51,724 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 20:37:51,724 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-12-13 20:37:51,724 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-12-13 20:37:51,724 INFO L87 Difference]: Start difference. First operand 1254 states and 1834 transitions. cyclomatic complexity: 584 Second operand has 5 states, 5 states have (on average 12.4) internal successors, (62), 5 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 20:37:51,845 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 20:37:51,845 INFO L93 Difference]: Finished difference Result 3355 states and 4893 transitions. [2022-12-13 20:37:51,845 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3355 states and 4893 transitions. [2022-12-13 20:37:51,859 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3184 [2022-12-13 20:37:51,868 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3355 states to 3355 states and 4893 transitions. [2022-12-13 20:37:51,868 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3355 [2022-12-13 20:37:51,870 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3355 [2022-12-13 20:37:51,871 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3355 states and 4893 transitions. [2022-12-13 20:37:51,874 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 20:37:51,874 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3355 states and 4893 transitions. [2022-12-13 20:37:51,876 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3355 states and 4893 transitions. [2022-12-13 20:37:51,894 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3355 to 1323. [2022-12-13 20:37:51,895 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1323 states, 1323 states have (on average 1.438397581254724) internal successors, (1903), 1322 states have internal predecessors, (1903), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 20:37:51,898 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1323 states to 1323 states and 1903 transitions. [2022-12-13 20:37:51,898 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1323 states and 1903 transitions. [2022-12-13 20:37:51,898 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-12-13 20:37:51,899 INFO L428 stractBuchiCegarLoop]: Abstraction has 1323 states and 1903 transitions. [2022-12-13 20:37:51,899 INFO L335 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2022-12-13 20:37:51,899 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1323 states and 1903 transitions. [2022-12-13 20:37:51,903 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1242 [2022-12-13 20:37:51,903 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 20:37:51,904 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 20:37:51,904 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 20:37:51,904 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 20:37:51,904 INFO L748 eck$LassoCheckResult]: Stem: 12340#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 12341#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 12455#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 12456#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 12253#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 12254#L353-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 12542#L358-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 12194#L363-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 12195#L368-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 12334#L373-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 12224#L514 assume !(0 == ~M_E~0); 12225#L514-2 assume !(0 == ~T1_E~0); 12569#L519-1 assume !(0 == ~T2_E~0); 12182#L524-1 assume !(0 == ~T3_E~0); 12183#L529-1 assume !(0 == ~T4_E~0); 12310#L534-1 assume !(0 == ~E_M~0); 12508#L539-1 assume !(0 == ~E_1~0); 12509#L544-1 assume !(0 == ~E_2~0); 12540#L549-1 assume !(0 == ~E_3~0); 12541#L554-1 assume !(0 == ~E_4~0); 12177#L559-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12178#L250 assume !(1 == ~m_pc~0); 12406#L250-2 is_master_triggered_~__retres1~0#1 := 0; 12544#L261 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12323#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 12324#L637 assume !(0 != activate_threads_~tmp~1#1); 12184#L637-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12185#L269 assume !(1 == ~t1_pc~0); 12119#L269-2 is_transmit1_triggered_~__retres1~1#1 := 0; 12305#L280 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12416#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 12570#L645 assume !(0 != activate_threads_~tmp___0~0#1); 12372#L645-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12373#L288 assume 1 == ~t2_pc~0; 12481#L289 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 12364#L299 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12461#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 12462#L653 assume !(0 != activate_threads_~tmp___1~0#1); 12504#L653-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12396#L307 assume !(1 == ~t3_pc~0); 12326#L307-2 is_transmit3_triggered_~__retres1~3#1 := 0; 12327#L318 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12122#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 12123#L661 assume !(0 != activate_threads_~tmp___2~0#1); 12338#L661-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12339#L326 assume 1 == ~t4_pc~0; 12584#L327 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 12137#L337 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12228#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 12229#L669 assume !(0 != activate_threads_~tmp___3~0#1); 12505#L669-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12506#L572 assume 1 == ~M_E~0;~M_E~0 := 2; 12545#L572-2 assume !(1 == ~T1_E~0); 12190#L577-1 assume !(1 == ~T2_E~0); 12191#L582-1 assume !(1 == ~T3_E~0); 12488#L587-1 assume !(1 == ~T4_E~0); 12497#L592-1 assume !(1 == ~E_M~0); 12126#L597-1 assume 1 == ~E_1~0;~E_1~0 := 2; 12127#L602-1 assume !(1 == ~E_2~0); 12360#L607-1 assume !(1 == ~E_3~0); 12361#L612-1 assume !(1 == ~E_4~0); 12616#L617-1 assume { :end_inline_reset_delta_events } true; 12955#L803-2 [2022-12-13 20:37:51,905 INFO L750 eck$LassoCheckResult]: Loop: 12955#L803-2 assume !false; 12946#L804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 12943#L489 assume !false; 12940#L424 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 12937#L386 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 12929#L413 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 12923#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 12884#L428 assume !(0 != eval_~tmp~0#1); 12885#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 13166#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 13164#L514-3 assume 0 == ~M_E~0;~M_E~0 := 1; 13161#L514-5 assume !(0 == ~T1_E~0); 13159#L519-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 13157#L524-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 13155#L529-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 13153#L534-3 assume 0 == ~E_M~0;~E_M~0 := 1; 13152#L539-3 assume 0 == ~E_1~0;~E_1~0 := 1; 13148#L544-3 assume 0 == ~E_2~0;~E_2~0 := 1; 13146#L549-3 assume 0 == ~E_3~0;~E_3~0 := 1; 13144#L554-3 assume !(0 == ~E_4~0); 13143#L559-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12515#L250-18 assume !(1 == ~m_pc~0); 12516#L250-20 is_master_triggered_~__retres1~0#1 := 0; 13300#L261-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13299#is_master_triggered_returnLabel#7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 13298#L637-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 13297#L637-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 13296#L269-18 assume 1 == ~t1_pc~0; 13294#L270-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 13292#L280-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13290#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 13288#L645-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 13287#L645-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 13286#L288-18 assume 1 == ~t2_pc~0; 13281#L289-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 13279#L299-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13277#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 13274#L653-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 13272#L653-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 13270#L307-18 assume !(1 == ~t3_pc~0); 13267#L307-20 is_transmit3_triggered_~__retres1~3#1 := 0; 13265#L318-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13263#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 13262#L661-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 13260#L661-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13258#L326-18 assume 1 == ~t4_pc~0; 13255#L327-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 13253#L337-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 13251#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 13245#L669-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 13243#L669-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12699#L572-3 assume 1 == ~M_E~0;~M_E~0 := 2; 12691#L572-5 assume !(1 == ~T1_E~0); 12684#L577-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 12681#L582-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 12676#L587-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 12673#L592-3 assume 1 == ~E_M~0;~E_M~0 := 2; 12669#L597-3 assume !(1 == ~E_1~0); 12667#L602-3 assume 1 == ~E_2~0;~E_2~0 := 2; 12665#L607-3 assume 1 == ~E_3~0;~E_3~0 := 2; 12662#L612-3 assume 1 == ~E_4~0;~E_4~0 := 2; 12661#L617-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 12659#L386-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 12655#L413-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 12654#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 12394#L822 assume !(0 == start_simulation_~tmp~3#1); 12395#L822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 12512#L386-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 12440#L413-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 12170#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1; 12145#L777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 12146#L784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 12438#stop_simulation_returnLabel#1 start_simulation_#t~ret18#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 12565#L835 assume !(0 != start_simulation_~tmp___0~1#1); 12955#L803-2 [2022-12-13 20:37:51,905 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 20:37:51,905 INFO L85 PathProgramCache]: Analyzing trace with hash -299824125, now seen corresponding path program 1 times [2022-12-13 20:37:51,905 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 20:37:51,905 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1033277046] [2022-12-13 20:37:51,905 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:37:51,905 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 20:37:51,911 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 20:37:51,944 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 20:37:51,944 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 20:37:51,944 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1033277046] [2022-12-13 20:37:51,944 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1033277046] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 20:37:51,944 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 20:37:51,944 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 20:37:51,945 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1398973697] [2022-12-13 20:37:51,945 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 20:37:51,945 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 20:37:51,945 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 20:37:51,945 INFO L85 PathProgramCache]: Analyzing trace with hash -1792617107, now seen corresponding path program 1 times [2022-12-13 20:37:51,945 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 20:37:51,946 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [220379278] [2022-12-13 20:37:51,946 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:37:51,946 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 20:37:51,952 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 20:37:51,967 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 20:37:51,967 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 20:37:51,967 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [220379278] [2022-12-13 20:37:51,967 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [220379278] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 20:37:51,967 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 20:37:51,967 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 20:37:51,967 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1095303070] [2022-12-13 20:37:51,967 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 20:37:51,968 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 20:37:51,968 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 20:37:51,968 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 20:37:51,968 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 20:37:51,968 INFO L87 Difference]: Start difference. First operand 1323 states and 1903 transitions. cyclomatic complexity: 584 Second operand has 4 states, 4 states have (on average 15.5) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 20:37:52,058 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 20:37:52,058 INFO L93 Difference]: Finished difference Result 3026 states and 4300 transitions. [2022-12-13 20:37:52,058 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3026 states and 4300 transitions. [2022-12-13 20:37:52,081 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 2856 [2022-12-13 20:37:52,094 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3026 states to 3026 states and 4300 transitions. [2022-12-13 20:37:52,094 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3026 [2022-12-13 20:37:52,097 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3026 [2022-12-13 20:37:52,097 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3026 states and 4300 transitions. [2022-12-13 20:37:52,101 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 20:37:52,101 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3026 states and 4300 transitions. [2022-12-13 20:37:52,104 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3026 states and 4300 transitions. [2022-12-13 20:37:52,137 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3026 to 2378. [2022-12-13 20:37:52,141 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2378 states, 2378 states have (on average 1.430613961312027) internal successors, (3402), 2377 states have internal predecessors, (3402), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 20:37:52,148 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2378 states to 2378 states and 3402 transitions. [2022-12-13 20:37:52,148 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2378 states and 3402 transitions. [2022-12-13 20:37:52,149 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 20:37:52,149 INFO L428 stractBuchiCegarLoop]: Abstraction has 2378 states and 3402 transitions. [2022-12-13 20:37:52,149 INFO L335 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2022-12-13 20:37:52,150 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2378 states and 3402 transitions. [2022-12-13 20:37:52,160 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2296 [2022-12-13 20:37:52,160 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 20:37:52,161 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 20:37:52,162 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 20:37:52,162 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 20:37:52,162 INFO L748 eck$LassoCheckResult]: Stem: 16691#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 16692#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 16795#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 16796#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 16607#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 16608#L353-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 16880#L358-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 16551#L363-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 16552#L368-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 16685#L373-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 16578#L514 assume !(0 == ~M_E~0); 16579#L514-2 assume !(0 == ~T1_E~0); 16900#L519-1 assume !(0 == ~T2_E~0); 16539#L524-1 assume !(0 == ~T3_E~0); 16540#L529-1 assume !(0 == ~T4_E~0); 16662#L534-1 assume !(0 == ~E_M~0); 16850#L539-1 assume !(0 == ~E_1~0); 16851#L544-1 assume !(0 == ~E_2~0); 16878#L549-1 assume !(0 == ~E_3~0); 16879#L554-1 assume !(0 == ~E_4~0); 16534#L559-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16535#L250 assume !(1 == ~m_pc~0); 16754#L250-2 is_master_triggered_~__retres1~0#1 := 0; 16882#L261 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16675#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 16676#L637 assume !(0 != activate_threads_~tmp~1#1); 16541#L637-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16542#L269 assume !(1 == ~t1_pc~0); 16478#L269-2 is_transmit1_triggered_~__retres1~1#1 := 0; 16657#L280 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16952#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 16901#L645 assume !(0 != activate_threads_~tmp___0~0#1); 16720#L645-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 16721#L288 assume !(1 == ~t2_pc~0); 16713#L288-2 is_transmit2_triggered_~__retres1~2#1 := 0; 16714#L299 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 16802#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 16803#L653 assume !(0 != activate_threads_~tmp___1~0#1); 16845#L653-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16743#L307 assume !(1 == ~t3_pc~0); 16678#L307-2 is_transmit3_triggered_~__retres1~3#1 := 0; 16679#L318 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 16481#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 16482#L661 assume !(0 != activate_threads_~tmp___2~0#1); 16689#L661-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 16690#L326 assume 1 == ~t4_pc~0; 16914#L327 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 16494#L337 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 16582#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 16583#L669 assume !(0 != activate_threads_~tmp___3~0#1); 16847#L669-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16848#L572 assume 1 == ~M_E~0;~M_E~0 := 2; 16883#L572-2 assume !(1 == ~T1_E~0); 16547#L577-1 assume !(1 == ~T2_E~0); 16548#L582-1 assume !(1 == ~T3_E~0); 16837#L587-1 assume !(1 == ~T4_E~0); 16838#L592-1 assume !(1 == ~E_M~0); 16485#L597-1 assume 1 == ~E_1~0;~E_1~0 := 2; 16486#L602-1 assume !(1 == ~E_2~0); 16710#L607-1 assume !(1 == ~E_3~0); 16711#L612-1 assume !(1 == ~E_4~0); 16660#L617-1 assume { :end_inline_reset_delta_events } true; 16661#L803-2 [2022-12-13 20:37:52,162 INFO L750 eck$LassoCheckResult]: Loop: 16661#L803-2 assume !false; 16812#L804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 16573#L489 assume !false; 16777#L424 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 16744#L386 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 16593#L413 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 16656#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 16814#L428 assume !(0 != eval_~tmp~0#1); 16946#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 18815#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 18814#L514-3 assume 0 == ~M_E~0;~M_E~0 := 1; 18813#L514-5 assume !(0 == ~T1_E~0); 18812#L519-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 18811#L524-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 18810#L529-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 18809#L534-3 assume 0 == ~E_M~0;~E_M~0 := 1; 18808#L539-3 assume 0 == ~E_1~0;~E_1~0 := 1; 18807#L544-3 assume 0 == ~E_2~0;~E_2~0 := 1; 18806#L549-3 assume 0 == ~E_3~0;~E_3~0 := 1; 18805#L554-3 assume !(0 == ~E_4~0); 18804#L559-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 18803#L250-18 assume !(1 == ~m_pc~0); 18802#L250-20 is_master_triggered_~__retres1~0#1 := 0; 18801#L261-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 18800#is_master_triggered_returnLabel#7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 18799#L637-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 18798#L637-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 18797#L269-18 assume !(1 == ~t1_pc~0); 18795#L269-20 is_transmit1_triggered_~__retres1~1#1 := 0; 18793#L280-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 18791#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 18790#L645-18 assume !(0 != activate_threads_~tmp___0~0#1); 18788#L645-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 16667#L288-18 assume !(1 == ~t2_pc~0); 16668#L288-20 is_transmit2_triggered_~__retres1~2#1 := 0; 16483#L299-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 16484#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 16786#L653-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 18781#L653-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 18780#L307-18 assume !(1 == ~t3_pc~0); 16616#L307-20 is_transmit3_triggered_~__retres1~3#1 := 0; 16617#L318-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 16684#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 16627#L661-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 16628#L661-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 16860#L326-18 assume 1 == ~t4_pc~0; 16861#L327-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 16869#L337-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 16729#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 16470#L669-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 16471#L669-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16927#L572-3 assume 1 == ~M_E~0;~M_E~0 := 2; 16947#L572-5 assume !(1 == ~T1_E~0); 18681#L577-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 18679#L582-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 18677#L587-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 18675#L592-3 assume 1 == ~E_M~0;~E_M~0 := 2; 18673#L597-3 assume !(1 == ~E_1~0); 18671#L602-3 assume 1 == ~E_2~0;~E_2~0 := 2; 18668#L607-3 assume 1 == ~E_3~0;~E_3~0 := 2; 18666#L612-3 assume 1 == ~E_4~0;~E_4~0 := 2; 16654#L617-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 18660#L386-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 18648#L413-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 18647#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 18646#L822 assume !(0 == start_simulation_~tmp~3#1); 16846#L822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 18620#L386-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 18618#L413-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 18616#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1; 18614#L777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 18612#L784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 18611#stop_simulation_returnLabel#1 start_simulation_#t~ret18#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 16893#L835 assume !(0 != start_simulation_~tmp___0~1#1); 16661#L803-2 [2022-12-13 20:37:52,162 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 20:37:52,163 INFO L85 PathProgramCache]: Analyzing trace with hash -1271498812, now seen corresponding path program 1 times [2022-12-13 20:37:52,163 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 20:37:52,163 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [585857113] [2022-12-13 20:37:52,163 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:37:52,163 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 20:37:52,171 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 20:37:52,201 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 20:37:52,201 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 20:37:52,202 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [585857113] [2022-12-13 20:37:52,202 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [585857113] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 20:37:52,202 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 20:37:52,202 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-12-13 20:37:52,202 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [159576400] [2022-12-13 20:37:52,202 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 20:37:52,203 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 20:37:52,203 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 20:37:52,203 INFO L85 PathProgramCache]: Analyzing trace with hash -773659983, now seen corresponding path program 1 times [2022-12-13 20:37:52,203 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 20:37:52,203 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2128443501] [2022-12-13 20:37:52,203 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:37:52,204 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 20:37:52,212 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 20:37:52,237 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 20:37:52,238 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 20:37:52,238 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2128443501] [2022-12-13 20:37:52,238 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2128443501] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 20:37:52,238 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 20:37:52,238 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 20:37:52,238 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [674947103] [2022-12-13 20:37:52,238 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 20:37:52,239 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 20:37:52,239 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 20:37:52,239 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 20:37:52,239 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 20:37:52,239 INFO L87 Difference]: Start difference. First operand 2378 states and 3402 transitions. cyclomatic complexity: 1028 Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 2 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 20:37:52,294 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 20:37:52,294 INFO L93 Difference]: Finished difference Result 4325 states and 6159 transitions. [2022-12-13 20:37:52,295 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4325 states and 6159 transitions. [2022-12-13 20:37:52,316 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 4224 [2022-12-13 20:37:52,334 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4325 states to 4325 states and 6159 transitions. [2022-12-13 20:37:52,335 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4325 [2022-12-13 20:37:52,338 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4325 [2022-12-13 20:37:52,339 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4325 states and 6159 transitions. [2022-12-13 20:37:52,343 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 20:37:52,343 INFO L218 hiAutomatonCegarLoop]: Abstraction has 4325 states and 6159 transitions. [2022-12-13 20:37:52,346 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4325 states and 6159 transitions. [2022-12-13 20:37:52,394 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4325 to 4309. [2022-12-13 20:37:52,398 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4309 states, 4309 states have (on average 1.4256207936876306) internal successors, (6143), 4308 states have internal predecessors, (6143), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 20:37:52,405 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4309 states to 4309 states and 6143 transitions. [2022-12-13 20:37:52,405 INFO L240 hiAutomatonCegarLoop]: Abstraction has 4309 states and 6143 transitions. [2022-12-13 20:37:52,406 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 20:37:52,406 INFO L428 stractBuchiCegarLoop]: Abstraction has 4309 states and 6143 transitions. [2022-12-13 20:37:52,406 INFO L335 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2022-12-13 20:37:52,406 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4309 states and 6143 transitions. [2022-12-13 20:37:52,416 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 4208 [2022-12-13 20:37:52,416 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 20:37:52,417 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 20:37:52,417 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 20:37:52,417 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 20:37:52,417 INFO L748 eck$LassoCheckResult]: Stem: 23407#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 23408#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 23516#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 23517#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 23322#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 23323#L353-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 23599#L358-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 23263#L363-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 23264#L368-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 23401#L373-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 23291#L514 assume !(0 == ~M_E~0); 23292#L514-2 assume !(0 == ~T1_E~0); 23622#L519-1 assume !(0 == ~T2_E~0); 23249#L524-1 assume !(0 == ~T3_E~0); 23250#L529-1 assume !(0 == ~T4_E~0); 23376#L534-1 assume !(0 == ~E_M~0); 23576#L539-1 assume !(0 == ~E_1~0); 23577#L544-1 assume !(0 == ~E_2~0); 23597#L549-1 assume !(0 == ~E_3~0); 23598#L554-1 assume !(0 == ~E_4~0); 23244#L559-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 23245#L250 assume !(1 == ~m_pc~0); 23469#L250-2 is_master_triggered_~__retres1~0#1 := 0; 23601#L261 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 23389#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 23390#L637 assume !(0 != activate_threads_~tmp~1#1); 23251#L637-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 23252#L269 assume !(1 == ~t1_pc~0); 23188#L269-2 is_transmit1_triggered_~__retres1~1#1 := 0; 23371#L280 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 23689#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 23623#L645 assume !(0 != activate_threads_~tmp___0~0#1); 23437#L645-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 23438#L288 assume !(1 == ~t2_pc~0); 23430#L288-2 is_transmit2_triggered_~__retres1~2#1 := 0; 23431#L299 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 23523#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 23524#L653 assume !(0 != activate_threads_~tmp___1~0#1); 23572#L653-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 23460#L307 assume !(1 == ~t3_pc~0); 23392#L307-2 is_transmit3_triggered_~__retres1~3#1 := 0; 23393#L318 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 23191#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 23192#L661 assume !(0 != activate_threads_~tmp___2~0#1); 23405#L661-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 23406#L326 assume !(1 == ~t4_pc~0); 23203#L326-2 is_transmit4_triggered_~__retres1~4#1 := 0; 23204#L337 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 23295#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 23296#L669 assume !(0 != activate_threads_~tmp___3~0#1); 23573#L669-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 23574#L572 assume 1 == ~M_E~0;~M_E~0 := 2; 23602#L572-2 assume !(1 == ~T1_E~0); 23259#L577-1 assume !(1 == ~T2_E~0); 23260#L582-1 assume !(1 == ~T3_E~0); 23553#L587-1 assume !(1 == ~T4_E~0); 23564#L592-1 assume !(1 == ~E_M~0); 23195#L597-1 assume 1 == ~E_1~0;~E_1~0 := 2; 23196#L602-1 assume !(1 == ~E_2~0); 23427#L607-1 assume !(1 == ~E_3~0); 23428#L612-1 assume !(1 == ~E_4~0); 23374#L617-1 assume { :end_inline_reset_delta_events } true; 23375#L803-2 [2022-12-13 20:37:52,418 INFO L750 eck$LassoCheckResult]: Loop: 23375#L803-2 assume !false; 23535#L804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 23284#L489 assume !false; 23496#L424 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 23461#L386 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 23308#L413 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 23370#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 23537#L428 assume !(0 != eval_~tmp~0#1); 26870#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 27274#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 27275#L514-3 assume 0 == ~M_E~0;~M_E~0 := 1; 27268#L514-5 assume !(0 == ~T1_E~0); 27269#L519-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 27262#L524-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 27260#L529-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 27257#L534-3 assume 0 == ~E_M~0;~E_M~0 := 1; 27258#L539-3 assume 0 == ~E_1~0;~E_1~0 := 1; 27313#L544-3 assume 0 == ~E_2~0;~E_2~0 := 1; 27250#L549-3 assume 0 == ~E_3~0;~E_3~0 := 1; 27251#L554-3 assume !(0 == ~E_4~0); 27309#L559-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 27241#L250-18 assume !(1 == ~m_pc~0); 27242#L250-20 is_master_triggered_~__retres1~0#1 := 0; 27236#L261-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 27237#is_master_triggered_returnLabel#7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 27295#L637-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 27294#L637-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 27293#L269-18 assume !(1 == ~t1_pc~0); 27288#L269-20 is_transmit1_triggered_~__retres1~1#1 := 0; 27286#L280-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 27284#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 27198#L645-18 assume !(0 != activate_threads_~tmp___0~0#1); 27195#L645-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 27192#L288-18 assume !(1 == ~t2_pc~0); 27191#L288-20 is_transmit2_triggered_~__retres1~2#1 := 0; 27190#L299-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 27189#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 27188#L653-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 27187#L653-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 27186#L307-18 assume !(1 == ~t3_pc~0); 27184#L307-20 is_transmit3_triggered_~__retres1~3#1 := 0; 27183#L318-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 27182#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 27181#L661-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 27180#L661-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 27179#L326-18 assume !(1 == ~t4_pc~0); 27178#L326-20 is_transmit4_triggered_~__retres1~4#1 := 0; 27177#L337-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 27176#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 27175#L669-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 23650#L669-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 23651#L572-3 assume 1 == ~M_E~0;~M_E~0 := 2; 27031#L572-5 assume !(1 == ~T1_E~0); 27174#L577-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 27173#L582-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 23653#L587-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 23654#L592-3 assume 1 == ~E_M~0;~E_M~0 := 2; 23560#L597-3 assume !(1 == ~E_1~0); 23561#L602-3 assume 1 == ~E_2~0;~E_2~0 := 2; 23619#L607-3 assume 1 == ~E_3~0;~E_3~0 := 2; 23620#L612-3 assume 1 == ~E_4~0;~E_4~0 := 2; 27021#L617-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 27160#L386-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 27156#L413-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 23484#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 23458#L822 assume !(0 == start_simulation_~tmp~3#1); 23459#L822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 23580#L386-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 23501#L413-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 23237#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1; 23212#L777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 23213#L784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 23499#stop_simulation_returnLabel#1 start_simulation_#t~ret18#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 23614#L835 assume !(0 != start_simulation_~tmp___0~1#1); 23375#L803-2 [2022-12-13 20:37:52,418 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 20:37:52,418 INFO L85 PathProgramCache]: Analyzing trace with hash 843496709, now seen corresponding path program 1 times [2022-12-13 20:37:52,418 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 20:37:52,418 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [572240484] [2022-12-13 20:37:52,418 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:37:52,418 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 20:37:52,423 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 20:37:52,445 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 20:37:52,445 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 20:37:52,445 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [572240484] [2022-12-13 20:37:52,446 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [572240484] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 20:37:52,446 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 20:37:52,446 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-12-13 20:37:52,446 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1113644163] [2022-12-13 20:37:52,446 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 20:37:52,446 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 20:37:52,446 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 20:37:52,447 INFO L85 PathProgramCache]: Analyzing trace with hash -1745334670, now seen corresponding path program 1 times [2022-12-13 20:37:52,447 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 20:37:52,447 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1550352324] [2022-12-13 20:37:52,447 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:37:52,447 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 20:37:52,455 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 20:37:52,470 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 20:37:52,470 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 20:37:52,470 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1550352324] [2022-12-13 20:37:52,470 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1550352324] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 20:37:52,470 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 20:37:52,470 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 20:37:52,470 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1758806888] [2022-12-13 20:37:52,470 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 20:37:52,470 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 20:37:52,471 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 20:37:52,471 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 20:37:52,471 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 20:37:52,471 INFO L87 Difference]: Start difference. First operand 4309 states and 6143 transitions. cyclomatic complexity: 1842 Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 2 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 20:37:52,516 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 20:37:52,516 INFO L93 Difference]: Finished difference Result 6456 states and 9189 transitions. [2022-12-13 20:37:52,516 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6456 states and 9189 transitions. [2022-12-13 20:37:52,537 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 6352 [2022-12-13 20:37:52,556 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6456 states to 6456 states and 9189 transitions. [2022-12-13 20:37:52,557 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6456 [2022-12-13 20:37:52,561 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6456 [2022-12-13 20:37:52,561 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6456 states and 9189 transitions. [2022-12-13 20:37:52,566 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 20:37:52,566 INFO L218 hiAutomatonCegarLoop]: Abstraction has 6456 states and 9189 transitions. [2022-12-13 20:37:52,571 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6456 states and 9189 transitions. [2022-12-13 20:37:52,650 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6456 to 4687. [2022-12-13 20:37:52,656 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4687 states, 4687 states have (on average 1.421804992532537) internal successors, (6664), 4686 states have internal predecessors, (6664), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 20:37:52,666 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4687 states to 4687 states and 6664 transitions. [2022-12-13 20:37:52,666 INFO L240 hiAutomatonCegarLoop]: Abstraction has 4687 states and 6664 transitions. [2022-12-13 20:37:52,667 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 20:37:52,667 INFO L428 stractBuchiCegarLoop]: Abstraction has 4687 states and 6664 transitions. [2022-12-13 20:37:52,667 INFO L335 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2022-12-13 20:37:52,667 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4687 states and 6664 transitions. [2022-12-13 20:37:52,681 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4596 [2022-12-13 20:37:52,681 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 20:37:52,681 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 20:37:52,682 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 20:37:52,682 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 20:37:52,682 INFO L748 eck$LassoCheckResult]: Stem: 34174#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 34175#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 34280#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 34281#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 34087#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 34088#L353-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 34369#L358-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 34032#L363-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 34033#L368-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 34166#L373-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 34060#L514 assume !(0 == ~M_E~0); 34061#L514-2 assume !(0 == ~T1_E~0); 34390#L519-1 assume !(0 == ~T2_E~0); 34020#L524-1 assume !(0 == ~T3_E~0); 34021#L529-1 assume !(0 == ~T4_E~0); 34142#L534-1 assume !(0 == ~E_M~0); 34335#L539-1 assume !(0 == ~E_1~0); 34336#L544-1 assume !(0 == ~E_2~0); 34366#L549-1 assume !(0 == ~E_3~0); 34367#L554-1 assume !(0 == ~E_4~0); 34015#L559-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 34016#L250 assume !(1 == ~m_pc~0); 34238#L250-2 is_master_triggered_~__retres1~0#1 := 0; 34370#L261 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 34156#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 34157#L637 assume !(0 != activate_threads_~tmp~1#1); 34022#L637-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 34023#L269 assume !(1 == ~t1_pc~0); 33960#L269-2 is_transmit1_triggered_~__retres1~1#1 := 0; 34137#L280 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 34451#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 34391#L645 assume !(0 != activate_threads_~tmp___0~0#1); 34204#L645-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 34205#L288 assume !(1 == ~t2_pc~0); 34197#L288-2 is_transmit2_triggered_~__retres1~2#1 := 0; 34198#L299 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 34288#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 34289#L653 assume !(0 != activate_threads_~tmp___1~0#1); 34330#L653-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 34229#L307 assume !(1 == ~t3_pc~0); 34159#L307-2 is_transmit3_triggered_~__retres1~3#1 := 0; 34160#L318 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 33963#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 33964#L661 assume !(0 != activate_threads_~tmp___2~0#1); 34172#L661-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 34173#L326 assume !(1 == ~t4_pc~0); 33975#L326-2 is_transmit4_triggered_~__retres1~4#1 := 0; 33976#L337 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 34062#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 34063#L669 assume !(0 != activate_threads_~tmp___3~0#1); 34332#L669-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 34333#L572 assume !(1 == ~M_E~0); 34371#L572-2 assume !(1 == ~T1_E~0); 34028#L577-1 assume !(1 == ~T2_E~0); 34029#L582-1 assume !(1 == ~T3_E~0); 34313#L587-1 assume !(1 == ~T4_E~0); 34324#L592-1 assume !(1 == ~E_M~0); 33969#L597-1 assume 1 == ~E_1~0;~E_1~0 := 2; 33970#L602-1 assume !(1 == ~E_2~0); 34194#L607-1 assume !(1 == ~E_3~0); 34195#L612-1 assume !(1 == ~E_4~0); 34140#L617-1 assume { :end_inline_reset_delta_events } true; 34141#L803-2 [2022-12-13 20:37:52,682 INFO L750 eck$LassoCheckResult]: Loop: 34141#L803-2 assume !false; 37937#L804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 37936#L489 assume !false; 37935#L424 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 37762#L386 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 37749#L413 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 37740#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 37736#L428 assume !(0 != eval_~tmp~0#1); 34068#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 34069#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 34261#L514-3 assume !(0 == ~M_E~0); 34211#L514-5 assume !(0 == ~T1_E~0); 34212#L519-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 34311#L524-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 34113#L529-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 34114#L534-3 assume 0 == ~E_M~0;~E_M~0 := 1; 33956#L539-3 assume 0 == ~E_1~0;~E_1~0 := 1; 33957#L544-3 assume 0 == ~E_2~0;~E_2~0 := 1; 34393#L549-3 assume 0 == ~E_3~0;~E_3~0 := 1; 34163#L554-3 assume !(0 == ~E_4~0); 34164#L559-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 34349#L250-18 assume !(1 == ~m_pc~0); 34350#L250-20 is_master_triggered_~__retres1~0#1 := 0; 34272#L261-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 34189#is_master_triggered_returnLabel#7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 34190#L637-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 34120#L637-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 33999#L269-18 assume !(1 == ~t1_pc~0); 34000#L269-20 is_transmit1_triggered_~__retres1~1#1 := 0; 34075#L280-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 34076#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 34248#L645-18 assume !(0 != activate_threads_~tmp___0~0#1); 34249#L645-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 34148#L288-18 assume !(1 == ~t2_pc~0); 34149#L288-20 is_transmit2_triggered_~__retres1~2#1 := 0; 33965#L299-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 33966#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 34237#L653-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 34126#L653-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 34127#L307-18 assume 1 == ~t3_pc~0; 34196#L308-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 34095#L318-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 34165#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 34108#L661-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 34109#L661-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 34347#L326-18 assume !(1 == ~t4_pc~0); 34348#L326-20 is_transmit4_triggered_~__retres1~4#1 := 0; 34357#L337-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 34214#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 33952#L669-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 33953#L669-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 34417#L572-3 assume !(1 == ~M_E~0); 34121#L572-5 assume !(1 == ~T1_E~0); 34122#L577-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 34013#L582-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 34014#L587-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 34257#L592-3 assume 1 == ~E_M~0;~E_M~0 := 2; 34258#L597-3 assume !(1 == ~E_1~0); 34319#L602-3 assume 1 == ~E_2~0;~E_2~0 := 2; 34388#L607-3 assume 1 == ~E_3~0;~E_3~0 := 2; 34134#L612-3 assume 1 == ~E_4~0;~E_4~0 := 2; 34135#L617-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 34187#L386-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 34153#L413-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 34168#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 34253#L822 assume !(0 == start_simulation_~tmp~3#1); 34526#L822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 38016#L386-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 38014#L413-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 38011#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1; 38009#L777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 38007#L784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 38005#stop_simulation_returnLabel#1 start_simulation_#t~ret18#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 38003#L835 assume !(0 != start_simulation_~tmp___0~1#1); 34141#L803-2 [2022-12-13 20:37:52,683 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 20:37:52,683 INFO L85 PathProgramCache]: Analyzing trace with hash 1544561287, now seen corresponding path program 1 times [2022-12-13 20:37:52,683 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 20:37:52,683 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2008613756] [2022-12-13 20:37:52,683 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:37:52,683 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 20:37:52,690 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 20:37:52,719 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 20:37:52,719 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 20:37:52,719 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2008613756] [2022-12-13 20:37:52,719 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2008613756] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 20:37:52,719 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 20:37:52,719 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 20:37:52,720 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2019632062] [2022-12-13 20:37:52,720 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 20:37:52,720 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 20:37:52,720 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 20:37:52,720 INFO L85 PathProgramCache]: Analyzing trace with hash -361647695, now seen corresponding path program 1 times [2022-12-13 20:37:52,720 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 20:37:52,721 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [851762752] [2022-12-13 20:37:52,721 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:37:52,721 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 20:37:52,728 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 20:37:52,742 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 20:37:52,742 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 20:37:52,742 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [851762752] [2022-12-13 20:37:52,742 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [851762752] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 20:37:52,742 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 20:37:52,742 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 20:37:52,742 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [860243247] [2022-12-13 20:37:52,742 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 20:37:52,743 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 20:37:52,743 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 20:37:52,743 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 20:37:52,743 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 20:37:52,743 INFO L87 Difference]: Start difference. First operand 4687 states and 6664 transitions. cyclomatic complexity: 1981 Second operand has 4 states, 4 states have (on average 15.5) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 20:37:52,833 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 20:37:52,833 INFO L93 Difference]: Finished difference Result 6415 states and 8953 transitions. [2022-12-13 20:37:52,833 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6415 states and 8953 transitions. [2022-12-13 20:37:52,880 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 6230 [2022-12-13 20:37:52,894 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6415 states to 6415 states and 8953 transitions. [2022-12-13 20:37:52,894 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6415 [2022-12-13 20:37:52,898 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6415 [2022-12-13 20:37:52,898 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6415 states and 8953 transitions. [2022-12-13 20:37:52,903 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 20:37:52,903 INFO L218 hiAutomatonCegarLoop]: Abstraction has 6415 states and 8953 transitions. [2022-12-13 20:37:52,907 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6415 states and 8953 transitions. [2022-12-13 20:37:52,952 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6415 to 5274. [2022-12-13 20:37:52,958 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5274 states, 5274 states have (on average 1.403109594235874) internal successors, (7400), 5273 states have internal predecessors, (7400), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 20:37:52,967 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5274 states to 5274 states and 7400 transitions. [2022-12-13 20:37:52,967 INFO L240 hiAutomatonCegarLoop]: Abstraction has 5274 states and 7400 transitions. [2022-12-13 20:37:52,967 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 20:37:52,968 INFO L428 stractBuchiCegarLoop]: Abstraction has 5274 states and 7400 transitions. [2022-12-13 20:37:52,968 INFO L335 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2022-12-13 20:37:52,968 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5274 states and 7400 transitions. [2022-12-13 20:37:52,980 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 5140 [2022-12-13 20:37:52,980 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 20:37:52,980 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 20:37:52,981 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 20:37:52,981 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 20:37:52,981 INFO L748 eck$LassoCheckResult]: Stem: 45286#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 45287#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 45396#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 45397#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 45199#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 45200#L353-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 45490#L358-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 45143#L363-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 45144#L368-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 45279#L373-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 45171#L514 assume !(0 == ~M_E~0); 45172#L514-2 assume !(0 == ~T1_E~0); 45518#L519-1 assume !(0 == ~T2_E~0); 45131#L524-1 assume !(0 == ~T3_E~0); 45132#L529-1 assume !(0 == ~T4_E~0); 45254#L534-1 assume !(0 == ~E_M~0); 45454#L539-1 assume 0 == ~E_1~0;~E_1~0 := 1; 45455#L544-1 assume !(0 == ~E_2~0); 45487#L549-1 assume !(0 == ~E_3~0); 45525#L554-1 assume !(0 == ~E_4~0); 45526#L559-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 45349#L250 assume !(1 == ~m_pc~0); 45350#L250-2 is_master_triggered_~__retres1~0#1 := 0; 45519#L261 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 45268#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 45269#L637 assume !(0 != activate_threads_~tmp~1#1); 45133#L637-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 45134#L269 assume !(1 == ~t1_pc~0); 45153#L269-2 is_transmit1_triggered_~__retres1~1#1 := 0; 45360#L280 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 45120#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 45121#L645 assume !(0 != activate_threads_~tmp___0~0#1); 45608#L645-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 45607#L288 assume !(1 == ~t2_pc~0); 45606#L288-2 is_transmit2_triggered_~__retres1~2#1 := 0; 45605#L299 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 45604#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 45603#L653 assume !(0 != activate_threads_~tmp___1~0#1); 45602#L653-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 45601#L307 assume !(1 == ~t3_pc~0); 45599#L307-2 is_transmit3_triggered_~__retres1~3#1 := 0; 45598#L318 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 45597#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 45596#L661 assume !(0 != activate_threads_~tmp___2~0#1); 45595#L661-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 45594#L326 assume !(1 == ~t4_pc~0); 45593#L326-2 is_transmit4_triggered_~__retres1~4#1 := 0; 45592#L337 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 45591#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 45590#L669 assume !(0 != activate_threads_~tmp___3~0#1); 45589#L669-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 45588#L572 assume !(1 == ~M_E~0); 45587#L572-2 assume !(1 == ~T1_E~0); 45586#L577-1 assume !(1 == ~T2_E~0); 45585#L582-1 assume !(1 == ~T3_E~0); 45584#L587-1 assume !(1 == ~T4_E~0); 45583#L592-1 assume !(1 == ~E_M~0); 45582#L597-1 assume 1 == ~E_1~0;~E_1~0 := 2; 45080#L602-1 assume !(1 == ~E_2~0); 45306#L607-1 assume !(1 == ~E_3~0); 45307#L612-1 assume !(1 == ~E_4~0); 45252#L617-1 assume { :end_inline_reset_delta_events } true; 45253#L803-2 [2022-12-13 20:37:52,981 INFO L750 eck$LassoCheckResult]: Loop: 45253#L803-2 assume !false; 48379#L804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 48348#L489 assume !false; 48340#L424 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 48304#L386 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 48298#L413 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 48296#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 48290#L428 assume !(0 != eval_~tmp~0#1); 45181#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 45182#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 45375#L514-3 assume !(0 == ~M_E~0); 45323#L514-5 assume !(0 == ~T1_E~0); 45324#L519-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 45428#L524-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 45222#L529-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 45223#L534-3 assume 0 == ~E_M~0;~E_M~0 := 1; 45068#L539-3 assume 0 == ~E_1~0;~E_1~0 := 1; 45069#L544-3 assume 0 == ~E_2~0;~E_2~0 := 1; 50234#L549-3 assume 0 == ~E_3~0;~E_3~0 := 1; 50232#L554-3 assume !(0 == ~E_4~0); 50230#L559-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 50228#L250-18 assume !(1 == ~m_pc~0); 50226#L250-20 is_master_triggered_~__retres1~0#1 := 0; 50224#L261-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 50222#is_master_triggered_returnLabel#7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 50220#L637-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 50218#L637-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 50214#L269-18 assume 1 == ~t1_pc~0; 50211#L270-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 50212#L280-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 50325#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 50321#L645-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 45484#L645-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 45260#L288-18 assume !(1 == ~t2_pc~0); 45261#L288-20 is_transmit2_triggered_~__retres1~2#1 := 0; 45077#L299-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 45078#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 50155#L653-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 50154#L653-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 50153#L307-18 assume !(1 == ~t3_pc~0); 50151#L307-20 is_transmit3_triggered_~__retres1~3#1 := 0; 50150#L318-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 50149#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 50148#L661-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 50147#L661-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 50146#L326-18 assume !(1 == ~t4_pc~0); 50145#L326-20 is_transmit4_triggered_~__retres1~4#1 := 0; 49691#L337-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 49690#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 49689#L669-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 49688#L669-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 49687#L572-3 assume !(1 == ~M_E~0); 48763#L572-5 assume !(1 == ~T1_E~0); 49686#L577-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 49685#L582-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 49683#L587-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 49655#L592-3 assume 1 == ~E_M~0;~E_M~0 := 2; 49442#L597-3 assume !(1 == ~E_1~0); 49439#L602-3 assume 1 == ~E_2~0;~E_2~0 := 2; 49436#L607-3 assume 1 == ~E_3~0;~E_3~0 := 2; 49434#L612-3 assume 1 == ~E_4~0;~E_4~0 := 2; 49432#L617-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 49427#L386-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 49422#L413-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 48121#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 48023#L822 assume !(0 == start_simulation_~tmp~3#1); 48024#L822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 49160#L386-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 49158#L413-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 49155#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1; 49154#L777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 49151#L784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 49100#stop_simulation_returnLabel#1 start_simulation_#t~ret18#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 49095#L835 assume !(0 != start_simulation_~tmp___0~1#1); 45253#L803-2 [2022-12-13 20:37:52,982 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 20:37:52,982 INFO L85 PathProgramCache]: Analyzing trace with hash -383711415, now seen corresponding path program 1 times [2022-12-13 20:37:52,982 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 20:37:52,982 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2041154425] [2022-12-13 20:37:52,982 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:37:52,982 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 20:37:52,987 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 20:37:53,019 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 20:37:53,020 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 20:37:53,020 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2041154425] [2022-12-13 20:37:53,020 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2041154425] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 20:37:53,020 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 20:37:53,020 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 20:37:53,020 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [873687470] [2022-12-13 20:37:53,020 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 20:37:53,020 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 20:37:53,021 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 20:37:53,021 INFO L85 PathProgramCache]: Analyzing trace with hash -814330449, now seen corresponding path program 1 times [2022-12-13 20:37:53,021 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 20:37:53,021 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [201234690] [2022-12-13 20:37:53,021 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:37:53,021 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 20:37:53,028 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 20:37:53,042 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 20:37:53,042 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 20:37:53,042 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [201234690] [2022-12-13 20:37:53,042 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [201234690] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 20:37:53,042 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 20:37:53,042 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 20:37:53,042 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [715791884] [2022-12-13 20:37:53,043 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 20:37:53,043 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 20:37:53,043 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 20:37:53,043 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 20:37:53,043 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 20:37:53,043 INFO L87 Difference]: Start difference. First operand 5274 states and 7400 transitions. cyclomatic complexity: 2130 Second operand has 4 states, 4 states have (on average 15.5) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 20:37:53,094 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 20:37:53,094 INFO L93 Difference]: Finished difference Result 5366 states and 7487 transitions. [2022-12-13 20:37:53,095 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5366 states and 7487 transitions. [2022-12-13 20:37:53,109 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 5262 [2022-12-13 20:37:53,122 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5366 states to 5366 states and 7487 transitions. [2022-12-13 20:37:53,122 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5366 [2022-12-13 20:37:53,125 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5366 [2022-12-13 20:37:53,125 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5366 states and 7487 transitions. [2022-12-13 20:37:53,130 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 20:37:53,130 INFO L218 hiAutomatonCegarLoop]: Abstraction has 5366 states and 7487 transitions. [2022-12-13 20:37:53,134 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5366 states and 7487 transitions. [2022-12-13 20:37:53,180 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5366 to 4468. [2022-12-13 20:37:53,184 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4468 states, 4468 states have (on average 1.3986123545210385) internal successors, (6249), 4467 states have internal predecessors, (6249), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 20:37:53,191 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4468 states to 4468 states and 6249 transitions. [2022-12-13 20:37:53,191 INFO L240 hiAutomatonCegarLoop]: Abstraction has 4468 states and 6249 transitions. [2022-12-13 20:37:53,191 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 20:37:53,191 INFO L428 stractBuchiCegarLoop]: Abstraction has 4468 states and 6249 transitions. [2022-12-13 20:37:53,192 INFO L335 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2022-12-13 20:37:53,192 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4468 states and 6249 transitions. [2022-12-13 20:37:53,201 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4380 [2022-12-13 20:37:53,201 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 20:37:53,201 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 20:37:53,201 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 20:37:53,202 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 20:37:53,202 INFO L748 eck$LassoCheckResult]: Stem: 55932#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 55933#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 56040#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 56041#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 55847#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 55848#L353-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 56126#L358-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 55792#L363-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 55793#L368-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 55924#L373-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 55818#L514 assume !(0 == ~M_E~0); 55819#L514-2 assume !(0 == ~T1_E~0); 56145#L519-1 assume !(0 == ~T2_E~0); 55780#L524-1 assume !(0 == ~T3_E~0); 55781#L529-1 assume !(0 == ~T4_E~0); 55900#L534-1 assume !(0 == ~E_M~0); 56094#L539-1 assume !(0 == ~E_1~0); 56095#L544-1 assume !(0 == ~E_2~0); 56124#L549-1 assume !(0 == ~E_3~0); 56125#L554-1 assume !(0 == ~E_4~0); 55775#L559-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 55776#L250 assume !(1 == ~m_pc~0); 55997#L250-2 is_master_triggered_~__retres1~0#1 := 0; 56128#L261 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 55913#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 55914#L637 assume !(0 != activate_threads_~tmp~1#1); 55782#L637-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 55783#L269 assume !(1 == ~t1_pc~0); 55721#L269-2 is_transmit1_triggered_~__retres1~1#1 := 0; 55895#L280 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 55769#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 55770#L645 assume !(0 != activate_threads_~tmp___0~0#1); 55963#L645-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 55964#L288 assume !(1 == ~t2_pc~0); 55956#L288-2 is_transmit2_triggered_~__retres1~2#1 := 0; 55957#L299 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 56047#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 56048#L653 assume !(0 != activate_threads_~tmp___1~0#1); 56089#L653-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 55988#L307 assume !(1 == ~t3_pc~0); 55916#L307-2 is_transmit3_triggered_~__retres1~3#1 := 0; 55917#L318 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 55724#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 55725#L661 assume !(0 != activate_threads_~tmp___2~0#1); 55930#L661-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 55931#L326 assume !(1 == ~t4_pc~0); 55736#L326-2 is_transmit4_triggered_~__retres1~4#1 := 0; 55737#L337 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 55822#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 55823#L669 assume !(0 != activate_threads_~tmp___3~0#1); 56091#L669-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 56092#L572 assume !(1 == ~M_E~0); 56129#L572-2 assume !(1 == ~T1_E~0); 55788#L577-1 assume !(1 == ~T2_E~0); 55789#L582-1 assume !(1 == ~T3_E~0); 56072#L587-1 assume !(1 == ~T4_E~0); 56081#L592-1 assume !(1 == ~E_M~0); 55728#L597-1 assume !(1 == ~E_1~0); 55729#L602-1 assume !(1 == ~E_2~0); 55953#L607-1 assume !(1 == ~E_3~0); 55954#L612-1 assume !(1 == ~E_4~0); 55898#L617-1 assume { :end_inline_reset_delta_events } true; 55899#L803-2 [2022-12-13 20:37:53,202 INFO L750 eck$LassoCheckResult]: Loop: 55899#L803-2 assume !false; 58859#L804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 58858#L489 assume !false; 58857#L424 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 58855#L386 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 58848#L413 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 58846#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 58843#L428 assume !(0 != eval_~tmp~0#1); 58844#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 59966#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 59964#L514-3 assume !(0 == ~M_E~0); 59962#L514-5 assume !(0 == ~T1_E~0); 59960#L519-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 59958#L524-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 59956#L529-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 59953#L534-3 assume 0 == ~E_M~0;~E_M~0 := 1; 59951#L539-3 assume !(0 == ~E_1~0); 59916#L544-3 assume 0 == ~E_2~0;~E_2~0 := 1; 59913#L549-3 assume 0 == ~E_3~0;~E_3~0 := 1; 59911#L554-3 assume !(0 == ~E_4~0); 59909#L559-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 59907#L250-18 assume !(1 == ~m_pc~0); 59905#L250-20 is_master_triggered_~__retres1~0#1 := 0; 59835#L261-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 59781#is_master_triggered_returnLabel#7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 59780#L637-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 59779#L637-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 59778#L269-18 assume !(1 == ~t1_pc~0); 59776#L269-20 is_transmit1_triggered_~__retres1~1#1 := 0; 59775#L280-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 59773#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 59771#L645-18 assume !(0 != activate_threads_~tmp___0~0#1); 59769#L645-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 59767#L288-18 assume !(1 == ~t2_pc~0); 58055#L288-20 is_transmit2_triggered_~__retres1~2#1 := 0; 59763#L299-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 59761#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 59759#L653-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 59758#L653-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 59757#L307-18 assume !(1 == ~t3_pc~0); 59754#L307-20 is_transmit3_triggered_~__retres1~3#1 := 0; 59752#L318-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 59750#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 59747#L661-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 59745#L661-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 59743#L326-18 assume !(1 == ~t4_pc~0); 59741#L326-20 is_transmit4_triggered_~__retres1~4#1 := 0; 59739#L337-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 59737#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 59736#L669-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 59734#L669-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 59732#L572-3 assume !(1 == ~M_E~0); 57740#L572-5 assume !(1 == ~T1_E~0); 59729#L577-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 59726#L582-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 59719#L587-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 59715#L592-3 assume 1 == ~E_M~0;~E_M~0 := 2; 59710#L597-3 assume !(1 == ~E_1~0); 59709#L602-3 assume 1 == ~E_2~0;~E_2~0 := 2; 59701#L607-3 assume 1 == ~E_3~0;~E_3~0 := 2; 59697#L612-3 assume 1 == ~E_4~0;~E_4~0 := 2; 59694#L617-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 59638#L386-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 59430#L413-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 59398#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 59394#L822 assume !(0 == start_simulation_~tmp~3#1); 59395#L822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 59873#L386-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 59871#L413-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 59868#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1; 59866#L777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 59864#L784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 59834#stop_simulation_returnLabel#1 start_simulation_#t~ret18#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 59802#L835 assume !(0 != start_simulation_~tmp___0~1#1); 55899#L803-2 [2022-12-13 20:37:53,202 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 20:37:53,202 INFO L85 PathProgramCache]: Analyzing trace with hash 1546408329, now seen corresponding path program 1 times [2022-12-13 20:37:53,202 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 20:37:53,202 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [740489781] [2022-12-13 20:37:53,202 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:37:53,202 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 20:37:53,208 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 20:37:53,208 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 20:37:53,211 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 20:37:53,231 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 20:37:53,231 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 20:37:53,232 INFO L85 PathProgramCache]: Analyzing trace with hash 1123530480, now seen corresponding path program 1 times [2022-12-13 20:37:53,232 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 20:37:53,232 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1036842626] [2022-12-13 20:37:53,232 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:37:53,232 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 20:37:53,237 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 20:37:53,265 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 20:37:53,265 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 20:37:53,265 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1036842626] [2022-12-13 20:37:53,266 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1036842626] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 20:37:53,266 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 20:37:53,266 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-12-13 20:37:53,266 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [198866148] [2022-12-13 20:37:53,266 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 20:37:53,266 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 20:37:53,267 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 20:37:53,267 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-12-13 20:37:53,267 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-12-13 20:37:53,267 INFO L87 Difference]: Start difference. First operand 4468 states and 6249 transitions. cyclomatic complexity: 1785 Second operand has 5 states, 5 states have (on average 14.8) internal successors, (74), 5 states have internal predecessors, (74), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 20:37:53,361 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 20:37:53,361 INFO L93 Difference]: Finished difference Result 7888 states and 10869 transitions. [2022-12-13 20:37:53,362 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7888 states and 10869 transitions. [2022-12-13 20:37:53,405 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 7776 [2022-12-13 20:37:53,424 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7888 states to 7888 states and 10869 transitions. [2022-12-13 20:37:53,424 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7888 [2022-12-13 20:37:53,428 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7888 [2022-12-13 20:37:53,429 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7888 states and 10869 transitions. [2022-12-13 20:37:53,434 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 20:37:53,434 INFO L218 hiAutomatonCegarLoop]: Abstraction has 7888 states and 10869 transitions. [2022-12-13 20:37:53,439 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7888 states and 10869 transitions. [2022-12-13 20:37:53,494 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7888 to 4516. [2022-12-13 20:37:53,500 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4516 states, 4516 states have (on average 1.3943755535872453) internal successors, (6297), 4515 states have internal predecessors, (6297), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 20:37:53,508 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4516 states to 4516 states and 6297 transitions. [2022-12-13 20:37:53,509 INFO L240 hiAutomatonCegarLoop]: Abstraction has 4516 states and 6297 transitions. [2022-12-13 20:37:53,509 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2022-12-13 20:37:53,509 INFO L428 stractBuchiCegarLoop]: Abstraction has 4516 states and 6297 transitions. [2022-12-13 20:37:53,509 INFO L335 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2022-12-13 20:37:53,510 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4516 states and 6297 transitions. [2022-12-13 20:37:53,521 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4428 [2022-12-13 20:37:53,522 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 20:37:53,522 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 20:37:53,522 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 20:37:53,523 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 20:37:53,523 INFO L748 eck$LassoCheckResult]: Stem: 68303#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 68304#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 68415#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 68416#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 68219#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 68220#L353-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 68494#L358-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 68164#L363-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 68165#L368-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 68295#L373-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 68192#L514 assume !(0 == ~M_E~0); 68193#L514-2 assume !(0 == ~T1_E~0); 68517#L519-1 assume !(0 == ~T2_E~0); 68152#L524-1 assume !(0 == ~T3_E~0); 68153#L529-1 assume !(0 == ~T4_E~0); 68272#L534-1 assume !(0 == ~E_M~0); 68466#L539-1 assume !(0 == ~E_1~0); 68467#L544-1 assume !(0 == ~E_2~0); 68491#L549-1 assume !(0 == ~E_3~0); 68492#L554-1 assume !(0 == ~E_4~0); 68147#L559-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 68148#L250 assume !(1 == ~m_pc~0); 68366#L250-2 is_master_triggered_~__retres1~0#1 := 0; 68495#L261 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 68285#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 68286#L637 assume !(0 != activate_threads_~tmp~1#1); 68154#L637-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 68155#L269 assume !(1 == ~t1_pc~0); 68093#L269-2 is_transmit1_triggered_~__retres1~1#1 := 0; 68267#L280 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 68143#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 68144#L645 assume !(0 != activate_threads_~tmp___0~0#1); 68332#L645-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 68333#L288 assume !(1 == ~t2_pc~0); 68325#L288-2 is_transmit2_triggered_~__retres1~2#1 := 0; 68326#L299 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 68420#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 68421#L653 assume !(0 != activate_threads_~tmp___1~0#1); 68460#L653-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 68355#L307 assume !(1 == ~t3_pc~0); 68288#L307-2 is_transmit3_triggered_~__retres1~3#1 := 0; 68289#L318 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 68096#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 68097#L661 assume !(0 != activate_threads_~tmp___2~0#1); 68301#L661-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 68302#L326 assume !(1 == ~t4_pc~0); 68108#L326-2 is_transmit4_triggered_~__retres1~4#1 := 0; 68109#L337 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 68194#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 68195#L669 assume !(0 != activate_threads_~tmp___3~0#1); 68462#L669-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 68463#L572 assume !(1 == ~M_E~0); 68496#L572-2 assume !(1 == ~T1_E~0); 68160#L577-1 assume !(1 == ~T2_E~0); 68161#L582-1 assume !(1 == ~T3_E~0); 68445#L587-1 assume !(1 == ~T4_E~0); 68454#L592-1 assume !(1 == ~E_M~0); 68106#L597-1 assume !(1 == ~E_1~0); 68107#L602-1 assume !(1 == ~E_2~0); 68322#L607-1 assume !(1 == ~E_3~0); 68323#L612-1 assume !(1 == ~E_4~0); 68270#L617-1 assume { :end_inline_reset_delta_events } true; 68271#L803-2 [2022-12-13 20:37:53,523 INFO L750 eck$LassoCheckResult]: Loop: 68271#L803-2 assume !false; 70347#L804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 70336#L489 assume !false; 70282#L424 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 70279#L386 assume !(0 == ~m_st~0); 70276#L390 assume !(0 == ~t1_st~0); 70277#L394 assume !(0 == ~t2_st~0); 70278#L398 assume !(0 == ~t3_st~0); 70275#L402 assume !(0 == ~t4_st~0);exists_runnable_thread_~__retres1~5#1 := 0; 70272#L413 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 69948#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 69949#L428 assume !(0 != eval_~tmp~0#1); 70269#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 70268#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 70267#L514-3 assume !(0 == ~M_E~0); 70266#L514-5 assume !(0 == ~T1_E~0); 70265#L519-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 70264#L524-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 70263#L529-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 70262#L534-3 assume 0 == ~E_M~0;~E_M~0 := 1; 70261#L539-3 assume !(0 == ~E_1~0); 70260#L544-3 assume 0 == ~E_2~0;~E_2~0 := 1; 70259#L549-3 assume 0 == ~E_3~0;~E_3~0 := 1; 70258#L554-3 assume !(0 == ~E_4~0); 70257#L559-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 70256#L250-18 assume !(1 == ~m_pc~0); 70255#L250-20 is_master_triggered_~__retres1~0#1 := 0; 70254#L261-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 70253#is_master_triggered_returnLabel#7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 70252#L637-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 70251#L637-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 70250#L269-18 assume !(1 == ~t1_pc~0); 70248#L269-20 is_transmit1_triggered_~__retres1~1#1 := 0; 70247#L280-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 70246#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 70245#L645-18 assume !(0 != activate_threads_~tmp___0~0#1); 70244#L645-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 70243#L288-18 assume !(1 == ~t2_pc~0); 69606#L288-20 is_transmit2_triggered_~__retres1~2#1 := 0; 70242#L299-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 70241#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 70240#L653-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 70239#L653-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 70238#L307-18 assume 1 == ~t3_pc~0; 70237#L308-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 70235#L318-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 70234#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 70233#L661-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 70232#L661-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 70231#L326-18 assume !(1 == ~t4_pc~0); 70230#L326-20 is_transmit4_triggered_~__retres1~4#1 := 0; 70229#L337-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 70228#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 70227#L669-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 70226#L669-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 70225#L572-3 assume !(1 == ~M_E~0); 70099#L572-5 assume !(1 == ~T1_E~0); 70224#L577-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 70223#L582-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 70222#L587-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 70221#L592-3 assume 1 == ~E_M~0;~E_M~0 := 2; 70220#L597-3 assume !(1 == ~E_1~0); 70219#L602-3 assume 1 == ~E_2~0;~E_2~0 := 2; 70218#L607-3 assume 1 == ~E_3~0;~E_3~0 := 2; 70217#L612-3 assume 1 == ~E_4~0;~E_4~0 := 2; 70216#L617-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 70214#L386-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 70210#L413-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 70209#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 70207#L822 assume !(0 == start_simulation_~tmp~3#1); 70208#L822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 70367#L386-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 70365#L413-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 70363#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1; 70361#L777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 70357#L784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 70355#stop_simulation_returnLabel#1 start_simulation_#t~ret18#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 70353#L835 assume !(0 != start_simulation_~tmp___0~1#1); 68271#L803-2 [2022-12-13 20:37:53,523 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 20:37:53,523 INFO L85 PathProgramCache]: Analyzing trace with hash 1546408329, now seen corresponding path program 2 times [2022-12-13 20:37:53,524 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 20:37:53,524 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [678462991] [2022-12-13 20:37:53,524 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:37:53,524 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 20:37:53,531 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 20:37:53,531 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 20:37:53,535 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 20:37:53,544 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 20:37:53,544 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 20:37:53,544 INFO L85 PathProgramCache]: Analyzing trace with hash -1039754269, now seen corresponding path program 1 times [2022-12-13 20:37:53,544 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 20:37:53,544 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2137592415] [2022-12-13 20:37:53,544 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:37:53,545 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 20:37:53,565 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 20:37:53,639 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 20:37:53,640 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 20:37:53,640 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2137592415] [2022-12-13 20:37:53,640 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2137592415] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 20:37:53,640 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 20:37:53,640 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-12-13 20:37:53,640 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [342355136] [2022-12-13 20:37:53,640 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 20:37:53,641 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 20:37:53,641 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 20:37:53,641 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-12-13 20:37:53,641 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-12-13 20:37:53,642 INFO L87 Difference]: Start difference. First operand 4516 states and 6297 transitions. cyclomatic complexity: 1785 Second operand has 5 states, 5 states have (on average 15.6) internal successors, (78), 5 states have internal predecessors, (78), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 20:37:53,793 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 20:37:53,793 INFO L93 Difference]: Finished difference Result 8960 states and 12392 transitions. [2022-12-13 20:37:53,793 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 8960 states and 12392 transitions. [2022-12-13 20:37:53,823 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 8856 [2022-12-13 20:37:53,841 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 8960 states to 8960 states and 12392 transitions. [2022-12-13 20:37:53,841 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8960 [2022-12-13 20:37:53,846 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8960 [2022-12-13 20:37:53,846 INFO L73 IsDeterministic]: Start isDeterministic. Operand 8960 states and 12392 transitions. [2022-12-13 20:37:53,851 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 20:37:53,851 INFO L218 hiAutomatonCegarLoop]: Abstraction has 8960 states and 12392 transitions. [2022-12-13 20:37:53,857 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8960 states and 12392 transitions. [2022-12-13 20:37:53,902 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8960 to 4648. [2022-12-13 20:37:53,906 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4648 states, 4648 states have (on average 1.3752151462994837) internal successors, (6392), 4647 states have internal predecessors, (6392), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 20:37:53,939 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4648 states to 4648 states and 6392 transitions. [2022-12-13 20:37:53,939 INFO L240 hiAutomatonCegarLoop]: Abstraction has 4648 states and 6392 transitions. [2022-12-13 20:37:53,939 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-12-13 20:37:53,940 INFO L428 stractBuchiCegarLoop]: Abstraction has 4648 states and 6392 transitions. [2022-12-13 20:37:53,940 INFO L335 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2022-12-13 20:37:53,940 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4648 states and 6392 transitions. [2022-12-13 20:37:53,951 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4560 [2022-12-13 20:37:53,951 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 20:37:53,952 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 20:37:53,953 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 20:37:53,953 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 20:37:53,953 INFO L748 eck$LassoCheckResult]: Stem: 81797#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 81798#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 81911#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 81912#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 81710#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 81711#L353-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 82016#L358-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 81655#L363-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 81656#L368-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 81789#L373-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 81681#L514 assume !(0 == ~M_E~0); 81682#L514-2 assume !(0 == ~T1_E~0); 82039#L519-1 assume !(0 == ~T2_E~0); 81641#L524-1 assume !(0 == ~T3_E~0); 81642#L529-1 assume !(0 == ~T4_E~0); 81764#L534-1 assume !(0 == ~E_M~0); 81978#L539-1 assume !(0 == ~E_1~0); 81979#L544-1 assume !(0 == ~E_2~0); 82014#L549-1 assume !(0 == ~E_3~0); 82015#L554-1 assume !(0 == ~E_4~0); 81636#L559-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 81637#L250 assume !(1 == ~m_pc~0); 81865#L250-2 is_master_triggered_~__retres1~0#1 := 0; 82019#L261 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 81778#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 81779#L637 assume !(0 != activate_threads_~tmp~1#1); 81643#L637-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 81644#L269 assume !(1 == ~t1_pc~0); 81582#L269-2 is_transmit1_triggered_~__retres1~1#1 := 0; 81759#L280 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 81630#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 81631#L645 assume !(0 != activate_threads_~tmp___0~0#1); 81830#L645-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 81831#L288 assume !(1 == ~t2_pc~0); 81823#L288-2 is_transmit2_triggered_~__retres1~2#1 := 0; 81824#L299 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 81919#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 81920#L653 assume !(0 != activate_threads_~tmp___1~0#1); 81972#L653-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 81854#L307 assume !(1 == ~t3_pc~0); 81781#L307-2 is_transmit3_triggered_~__retres1~3#1 := 0; 81782#L318 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 81585#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 81586#L661 assume !(0 != activate_threads_~tmp___2~0#1); 81795#L661-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 81796#L326 assume !(1 == ~t4_pc~0); 81597#L326-2 is_transmit4_triggered_~__retres1~4#1 := 0; 81598#L337 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 81685#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 81686#L669 assume !(0 != activate_threads_~tmp___3~0#1); 81975#L669-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 81976#L572 assume !(1 == ~M_E~0); 82020#L572-2 assume !(1 == ~T1_E~0); 81651#L577-1 assume !(1 == ~T2_E~0); 81652#L582-1 assume !(1 == ~T3_E~0); 81954#L587-1 assume !(1 == ~T4_E~0); 81963#L592-1 assume !(1 == ~E_M~0); 81589#L597-1 assume !(1 == ~E_1~0); 81590#L602-1 assume !(1 == ~E_2~0); 81820#L607-1 assume !(1 == ~E_3~0); 81821#L612-1 assume !(1 == ~E_4~0); 81762#L617-1 assume { :end_inline_reset_delta_events } true; 81763#L803-2 [2022-12-13 20:37:53,953 INFO L750 eck$LassoCheckResult]: Loop: 81763#L803-2 assume !false; 82834#L804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 82833#L489 assume !false; 82832#L424 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 82831#L386 assume !(0 == ~m_st~0); 82828#L390 assume !(0 == ~t1_st~0); 82829#L394 assume !(0 == ~t2_st~0); 82830#L398 assume !(0 == ~t3_st~0); 82826#L402 assume !(0 == ~t4_st~0);exists_runnable_thread_~__retres1~5#1 := 0; 82827#L413 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 82818#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 82819#L428 assume !(0 != eval_~tmp~0#1); 83059#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 83057#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 83055#L514-3 assume !(0 == ~M_E~0); 83053#L514-5 assume !(0 == ~T1_E~0); 83050#L519-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 83047#L524-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 83044#L529-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 83041#L534-3 assume 0 == ~E_M~0;~E_M~0 := 1; 83038#L539-3 assume !(0 == ~E_1~0); 83035#L544-3 assume 0 == ~E_2~0;~E_2~0 := 1; 83032#L549-3 assume 0 == ~E_3~0;~E_3~0 := 1; 83029#L554-3 assume !(0 == ~E_4~0); 83026#L559-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 83019#L250-18 assume !(1 == ~m_pc~0); 83016#L250-20 is_master_triggered_~__retres1~0#1 := 0; 83013#L261-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 83009#is_master_triggered_returnLabel#7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 83007#L637-18 assume !(0 != activate_threads_~tmp~1#1); 83004#L637-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 83001#L269-18 assume !(1 == ~t1_pc~0); 82996#L269-20 is_transmit1_triggered_~__retres1~1#1 := 0; 82993#L280-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 82990#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 82987#L645-18 assume !(0 != activate_threads_~tmp___0~0#1); 82983#L645-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 82980#L288-18 assume !(1 == ~t2_pc~0); 82543#L288-20 is_transmit2_triggered_~__retres1~2#1 := 0; 82976#L299-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 82973#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 82970#L653-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 82967#L653-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 82965#L307-18 assume !(1 == ~t3_pc~0); 82961#L307-20 is_transmit3_triggered_~__retres1~3#1 := 0; 82956#L318-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 82952#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 82948#L661-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 82944#L661-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 82939#L326-18 assume !(1 == ~t4_pc~0); 82935#L326-20 is_transmit4_triggered_~__retres1~4#1 := 0; 82930#L337-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 82926#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 82922#L669-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 82918#L669-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 82914#L572-3 assume !(1 == ~M_E~0); 82909#L572-5 assume !(1 == ~T1_E~0); 82906#L577-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 82904#L582-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 82901#L587-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 82897#L592-3 assume 1 == ~E_M~0;~E_M~0 := 2; 82894#L597-3 assume !(1 == ~E_1~0); 82891#L602-3 assume 1 == ~E_2~0;~E_2~0 := 2; 82888#L607-3 assume 1 == ~E_3~0;~E_3~0 := 2; 82884#L612-3 assume 1 == ~E_4~0;~E_4~0 := 2; 82881#L617-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 82877#L386-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 82871#L413-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 82868#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 82864#L822 assume !(0 == start_simulation_~tmp~3#1); 82861#L822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 82855#L386-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 82853#L413-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 82851#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1; 82849#L777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 82845#L784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 82843#stop_simulation_returnLabel#1 start_simulation_#t~ret18#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 82841#L835 assume !(0 != start_simulation_~tmp___0~1#1); 81763#L803-2 [2022-12-13 20:37:53,953 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 20:37:53,954 INFO L85 PathProgramCache]: Analyzing trace with hash 1546408329, now seen corresponding path program 3 times [2022-12-13 20:37:53,954 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 20:37:53,954 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [442272831] [2022-12-13 20:37:53,954 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:37:53,954 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 20:37:53,963 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 20:37:53,963 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 20:37:53,968 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 20:37:53,979 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 20:37:53,979 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 20:37:53,979 INFO L85 PathProgramCache]: Analyzing trace with hash -3823898, now seen corresponding path program 1 times [2022-12-13 20:37:53,979 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 20:37:53,980 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2067238525] [2022-12-13 20:37:53,980 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:37:53,980 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 20:37:53,988 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 20:37:54,011 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 20:37:54,011 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 20:37:54,011 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2067238525] [2022-12-13 20:37:54,012 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2067238525] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 20:37:54,012 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 20:37:54,012 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 20:37:54,012 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2143643790] [2022-12-13 20:37:54,012 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 20:37:54,012 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 20:37:54,012 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 20:37:54,013 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 20:37:54,013 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 20:37:54,013 INFO L87 Difference]: Start difference. First operand 4648 states and 6392 transitions. cyclomatic complexity: 1748 Second operand has 3 states, 3 states have (on average 26.0) internal successors, (78), 3 states have internal predecessors, (78), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 20:37:54,054 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 20:37:54,054 INFO L93 Difference]: Finished difference Result 7304 states and 9896 transitions. [2022-12-13 20:37:54,054 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7304 states and 9896 transitions. [2022-12-13 20:37:54,073 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 7206 [2022-12-13 20:37:54,088 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7304 states to 7304 states and 9896 transitions. [2022-12-13 20:37:54,088 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7304 [2022-12-13 20:37:54,092 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7304 [2022-12-13 20:37:54,092 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7304 states and 9896 transitions. [2022-12-13 20:37:54,095 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 20:37:54,095 INFO L218 hiAutomatonCegarLoop]: Abstraction has 7304 states and 9896 transitions. [2022-12-13 20:37:54,100 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7304 states and 9896 transitions. [2022-12-13 20:37:54,167 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7304 to 7048. [2022-12-13 20:37:54,175 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7048 states, 7048 states have (on average 1.3564131668558457) internal successors, (9560), 7047 states have internal predecessors, (9560), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 20:37:54,190 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7048 states to 7048 states and 9560 transitions. [2022-12-13 20:37:54,190 INFO L240 hiAutomatonCegarLoop]: Abstraction has 7048 states and 9560 transitions. [2022-12-13 20:37:54,190 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 20:37:54,190 INFO L428 stractBuchiCegarLoop]: Abstraction has 7048 states and 9560 transitions. [2022-12-13 20:37:54,191 INFO L335 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2022-12-13 20:37:54,191 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7048 states and 9560 transitions. [2022-12-13 20:37:54,208 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 6950 [2022-12-13 20:37:54,209 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 20:37:54,209 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 20:37:54,209 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 20:37:54,209 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 20:37:54,209 INFO L748 eck$LassoCheckResult]: Stem: 93753#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 93754#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 93862#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 93863#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 93668#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 93669#L353-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 93941#L358-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 93613#L363-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 93614#L368-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 93746#L373-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 93639#L514 assume !(0 == ~M_E~0); 93640#L514-2 assume !(0 == ~T1_E~0); 93963#L519-1 assume !(0 == ~T2_E~0); 93599#L524-1 assume !(0 == ~T3_E~0); 93600#L529-1 assume !(0 == ~T4_E~0); 93723#L534-1 assume !(0 == ~E_M~0); 93915#L539-1 assume !(0 == ~E_1~0); 93916#L544-1 assume !(0 == ~E_2~0); 93939#L549-1 assume !(0 == ~E_3~0); 93940#L554-1 assume !(0 == ~E_4~0); 93594#L559-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 93595#L250 assume !(1 == ~m_pc~0); 93815#L250-2 is_master_triggered_~__retres1~0#1 := 0; 93944#L261 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 93736#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 93737#L637 assume !(0 != activate_threads_~tmp~1#1); 93601#L637-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 93602#L269 assume !(1 == ~t1_pc~0); 93540#L269-2 is_transmit1_triggered_~__retres1~1#1 := 0; 93718#L280 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 93588#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 93589#L645 assume !(0 != activate_threads_~tmp___0~0#1); 93782#L645-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 93783#L288 assume !(1 == ~t2_pc~0); 93776#L288-2 is_transmit2_triggered_~__retres1~2#1 := 0; 93777#L299 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 93869#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 93870#L653 assume !(0 != activate_threads_~tmp___1~0#1); 93909#L653-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 93803#L307 assume !(1 == ~t3_pc~0); 93739#L307-2 is_transmit3_triggered_~__retres1~3#1 := 0; 93740#L318 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 93543#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 93544#L661 assume !(0 != activate_threads_~tmp___2~0#1); 93751#L661-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 93752#L326 assume !(1 == ~t4_pc~0); 93555#L326-2 is_transmit4_triggered_~__retres1~4#1 := 0; 93556#L337 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 93643#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 93644#L669 assume !(0 != activate_threads_~tmp___3~0#1); 93911#L669-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 93912#L572 assume !(1 == ~M_E~0); 93945#L572-2 assume !(1 == ~T1_E~0); 93609#L577-1 assume !(1 == ~T2_E~0); 93610#L582-1 assume !(1 == ~T3_E~0); 93893#L587-1 assume !(1 == ~T4_E~0); 93902#L592-1 assume !(1 == ~E_M~0); 93547#L597-1 assume !(1 == ~E_1~0); 93548#L602-1 assume !(1 == ~E_2~0); 93773#L607-1 assume !(1 == ~E_3~0); 93774#L612-1 assume !(1 == ~E_4~0); 93721#L617-1 assume { :end_inline_reset_delta_events } true; 93722#L803-2 assume !false; 95446#L804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 95447#L489 [2022-12-13 20:37:54,209 INFO L750 eck$LassoCheckResult]: Loop: 95447#L489 assume !false; 95776#L424 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 95775#L386 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 95774#L413 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 95773#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 95763#L428 assume 0 != eval_~tmp~0#1; 95758#L428-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 95753#L436 assume !(0 != eval_~tmp_ndt_1~0#1); 95746#L433 assume !(0 == ~t1_st~0); 95741#L447 assume !(0 == ~t2_st~0); 95461#L461 assume !(0 == ~t3_st~0); 95450#L475 assume !(0 == ~t4_st~0); 95447#L489 [2022-12-13 20:37:54,210 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 20:37:54,210 INFO L85 PathProgramCache]: Analyzing trace with hash 39728939, now seen corresponding path program 1 times [2022-12-13 20:37:54,210 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 20:37:54,210 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [456562564] [2022-12-13 20:37:54,210 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:37:54,210 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 20:37:54,217 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 20:37:54,217 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 20:37:54,222 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 20:37:54,229 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 20:37:54,230 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 20:37:54,230 INFO L85 PathProgramCache]: Analyzing trace with hash 1577382650, now seen corresponding path program 1 times [2022-12-13 20:37:54,230 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 20:37:54,230 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [712380996] [2022-12-13 20:37:54,230 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:37:54,230 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 20:37:54,233 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 20:37:54,233 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 20:37:54,234 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 20:37:54,236 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 20:37:54,236 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 20:37:54,236 INFO L85 PathProgramCache]: Analyzing trace with hash 189250340, now seen corresponding path program 1 times [2022-12-13 20:37:54,236 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 20:37:54,237 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2030586384] [2022-12-13 20:37:54,237 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:37:54,237 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 20:37:54,244 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 20:37:54,266 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 20:37:54,266 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 20:37:54,266 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2030586384] [2022-12-13 20:37:54,266 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2030586384] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 20:37:54,266 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 20:37:54,266 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 20:37:54,267 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [101881064] [2022-12-13 20:37:54,267 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 20:37:54,336 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 20:37:54,336 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 20:37:54,336 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 20:37:54,336 INFO L87 Difference]: Start difference. First operand 7048 states and 9560 transitions. cyclomatic complexity: 2518 Second operand has 3 states, 3 states have (on average 25.333333333333332) internal successors, (76), 3 states have internal predecessors, (76), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 20:37:54,396 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 20:37:54,397 INFO L93 Difference]: Finished difference Result 11326 states and 15229 transitions. [2022-12-13 20:37:54,397 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 11326 states and 15229 transitions. [2022-12-13 20:37:54,434 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 11136 [2022-12-13 20:37:54,463 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 11326 states to 11326 states and 15229 transitions. [2022-12-13 20:37:54,464 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 11326 [2022-12-13 20:37:54,471 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11326 [2022-12-13 20:37:54,471 INFO L73 IsDeterministic]: Start isDeterministic. Operand 11326 states and 15229 transitions. [2022-12-13 20:37:54,478 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 20:37:54,479 INFO L218 hiAutomatonCegarLoop]: Abstraction has 11326 states and 15229 transitions. [2022-12-13 20:37:54,485 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11326 states and 15229 transitions. [2022-12-13 20:37:54,578 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11326 to 11326. [2022-12-13 20:37:54,588 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 11326 states, 11326 states have (on average 1.3446053328624403) internal successors, (15229), 11325 states have internal predecessors, (15229), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 20:37:54,649 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11326 states to 11326 states and 15229 transitions. [2022-12-13 20:37:54,649 INFO L240 hiAutomatonCegarLoop]: Abstraction has 11326 states and 15229 transitions. [2022-12-13 20:37:54,650 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 20:37:54,650 INFO L428 stractBuchiCegarLoop]: Abstraction has 11326 states and 15229 transitions. [2022-12-13 20:37:54,650 INFO L335 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2022-12-13 20:37:54,650 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 11326 states and 15229 transitions. [2022-12-13 20:37:54,676 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 11136 [2022-12-13 20:37:54,676 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 20:37:54,676 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 20:37:54,677 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 20:37:54,677 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 20:37:54,677 INFO L748 eck$LassoCheckResult]: Stem: 112139#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 112140#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 112241#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 112242#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 112050#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 112051#L353-2 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 112332#L358-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 111995#L363-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 111996#L368-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 112131#L373-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 112021#L514 assume !(0 == ~M_E~0); 112022#L514-2 assume !(0 == ~T1_E~0); 112355#L519-1 assume !(0 == ~T2_E~0); 111981#L524-1 assume !(0 == ~T3_E~0); 111982#L529-1 assume !(0 == ~T4_E~0); 112106#L534-1 assume !(0 == ~E_M~0); 112302#L539-1 assume !(0 == ~E_1~0); 112303#L544-1 assume !(0 == ~E_2~0); 112330#L549-1 assume !(0 == ~E_3~0); 112331#L554-1 assume !(0 == ~E_4~0); 111976#L559-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 111977#L250 assume !(1 == ~m_pc~0); 112200#L250-2 is_master_triggered_~__retres1~0#1 := 0; 112336#L261 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 112119#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 112120#L637 assume !(0 != activate_threads_~tmp~1#1); 113192#L637-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 113190#L269 assume !(1 == ~t1_pc~0); 113187#L269-2 is_transmit1_triggered_~__retres1~1#1 := 0; 113185#L280 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 113183#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 113181#L645 assume !(0 != activate_threads_~tmp___0~0#1); 112168#L645-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 112169#L288 assume !(1 == ~t2_pc~0); 112161#L288-2 is_transmit2_triggered_~__retres1~2#1 := 0; 112162#L299 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 113078#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 113076#L653 assume !(0 != activate_threads_~tmp___1~0#1); 112347#L653-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 112191#L307 assume !(1 == ~t3_pc~0); 112122#L307-2 is_transmit3_triggered_~__retres1~3#1 := 0; 112123#L318 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 111925#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 111926#L661 assume !(0 != activate_threads_~tmp___2~0#1); 112137#L661-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 112138#L326 assume !(1 == ~t4_pc~0); 111937#L326-2 is_transmit4_triggered_~__retres1~4#1 := 0; 111938#L337 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 112188#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 112340#L669 assume !(0 != activate_threads_~tmp___3~0#1); 112299#L669-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 112300#L572 assume !(1 == ~M_E~0); 112337#L572-2 assume !(1 == ~T1_E~0); 111991#L577-1 assume !(1 == ~T2_E~0); 111992#L582-1 assume !(1 == ~T3_E~0); 113009#L587-1 assume !(1 == ~T4_E~0); 113006#L592-1 assume !(1 == ~E_M~0); 113004#L597-1 assume !(1 == ~E_1~0); 113002#L602-1 assume !(1 == ~E_2~0); 112981#L607-1 assume !(1 == ~E_3~0); 112979#L612-1 assume !(1 == ~E_4~0); 112977#L617-1 assume { :end_inline_reset_delta_events } true; 112975#L803-2 assume !false; 112968#L804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 112965#L489 [2022-12-13 20:37:54,677 INFO L750 eck$LassoCheckResult]: Loop: 112965#L489 assume !false; 112963#L424 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 112960#L386 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 112958#L413 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 112955#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 112952#L428 assume 0 != eval_~tmp~0#1; 112949#L428-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 112946#L436 assume !(0 != eval_~tmp_ndt_1~0#1); 112936#L433 assume !(0 == ~t1_st~0); 112934#L447 assume !(0 == ~t2_st~0); 112932#L461 assume !(0 == ~t3_st~0); 112971#L475 assume !(0 == ~t4_st~0); 112965#L489 [2022-12-13 20:37:54,678 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 20:37:54,678 INFO L85 PathProgramCache]: Analyzing trace with hash 600428717, now seen corresponding path program 1 times [2022-12-13 20:37:54,678 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 20:37:54,678 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [58742862] [2022-12-13 20:37:54,678 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:37:54,678 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 20:37:54,685 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 20:37:54,701 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 20:37:54,701 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 20:37:54,701 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [58742862] [2022-12-13 20:37:54,702 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [58742862] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 20:37:54,702 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 20:37:54,702 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 20:37:54,702 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1173967334] [2022-12-13 20:37:54,702 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 20:37:54,702 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 20:37:54,702 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 20:37:54,703 INFO L85 PathProgramCache]: Analyzing trace with hash 1577382650, now seen corresponding path program 2 times [2022-12-13 20:37:54,703 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 20:37:54,703 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [362169064] [2022-12-13 20:37:54,703 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:37:54,703 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 20:37:54,705 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 20:37:54,705 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 20:37:54,707 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 20:37:54,708 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 20:37:54,769 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 20:37:54,769 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 20:37:54,769 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 20:37:54,769 INFO L87 Difference]: Start difference. First operand 11326 states and 15229 transitions. cyclomatic complexity: 3909 Second operand has 3 states, 3 states have (on average 21.333333333333332) internal successors, (64), 3 states have internal predecessors, (64), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 20:37:54,792 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 20:37:54,792 INFO L93 Difference]: Finished difference Result 11266 states and 15149 transitions. [2022-12-13 20:37:54,792 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 11266 states and 15149 transitions. [2022-12-13 20:37:54,820 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 11136 [2022-12-13 20:37:54,840 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 11266 states to 11266 states and 15149 transitions. [2022-12-13 20:37:54,840 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 11266 [2022-12-13 20:37:54,845 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11266 [2022-12-13 20:37:54,845 INFO L73 IsDeterministic]: Start isDeterministic. Operand 11266 states and 15149 transitions. [2022-12-13 20:37:54,850 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 20:37:54,850 INFO L218 hiAutomatonCegarLoop]: Abstraction has 11266 states and 15149 transitions. [2022-12-13 20:37:54,855 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11266 states and 15149 transitions. [2022-12-13 20:37:54,920 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11266 to 11266. [2022-12-13 20:37:54,974 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 11266 states, 11266 states have (on average 1.3446653648144862) internal successors, (15149), 11265 states have internal predecessors, (15149), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 20:37:54,989 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11266 states to 11266 states and 15149 transitions. [2022-12-13 20:37:54,989 INFO L240 hiAutomatonCegarLoop]: Abstraction has 11266 states and 15149 transitions. [2022-12-13 20:37:54,990 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 20:37:54,990 INFO L428 stractBuchiCegarLoop]: Abstraction has 11266 states and 15149 transitions. [2022-12-13 20:37:54,990 INFO L335 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2022-12-13 20:37:54,990 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 11266 states and 15149 transitions. [2022-12-13 20:37:55,010 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 11136 [2022-12-13 20:37:55,010 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 20:37:55,010 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 20:37:55,010 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 20:37:55,010 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 20:37:55,010 INFO L748 eck$LassoCheckResult]: Stem: 134732#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 134733#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 134838#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 134839#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 134648#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 134649#L353-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 134926#L358-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 134591#L363-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 134592#L368-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 134725#L373-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 134620#L514 assume !(0 == ~M_E~0); 134621#L514-2 assume !(0 == ~T1_E~0); 134944#L519-1 assume !(0 == ~T2_E~0); 134579#L524-1 assume !(0 == ~T3_E~0); 134580#L529-1 assume !(0 == ~T4_E~0); 134702#L534-1 assume !(0 == ~E_M~0); 134893#L539-1 assume !(0 == ~E_1~0); 134894#L544-1 assume !(0 == ~E_2~0); 134923#L549-1 assume !(0 == ~E_3~0); 134924#L554-1 assume !(0 == ~E_4~0); 134574#L559-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 134575#L250 assume !(1 == ~m_pc~0); 134794#L250-2 is_master_triggered_~__retres1~0#1 := 0; 134927#L261 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 134715#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 134716#L637 assume !(0 != activate_threads_~tmp~1#1); 134581#L637-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 134582#L269 assume !(1 == ~t1_pc~0); 134520#L269-2 is_transmit1_triggered_~__retres1~1#1 := 0; 134697#L280 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 134570#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 134571#L645 assume !(0 != activate_threads_~tmp___0~0#1); 134762#L645-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 134763#L288 assume !(1 == ~t2_pc~0); 134755#L288-2 is_transmit2_triggered_~__retres1~2#1 := 0; 134756#L299 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 134844#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 134845#L653 assume !(0 != activate_threads_~tmp___1~0#1); 134888#L653-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 134785#L307 assume !(1 == ~t3_pc~0); 134718#L307-2 is_transmit3_triggered_~__retres1~3#1 := 0; 134719#L318 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 134523#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 134524#L661 assume !(0 != activate_threads_~tmp___2~0#1); 134730#L661-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 134731#L326 assume !(1 == ~t4_pc~0); 134535#L326-2 is_transmit4_triggered_~__retres1~4#1 := 0; 134536#L337 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 134622#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 134623#L669 assume !(0 != activate_threads_~tmp___3~0#1); 134890#L669-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 134891#L572 assume !(1 == ~M_E~0); 134928#L572-2 assume !(1 == ~T1_E~0); 134587#L577-1 assume !(1 == ~T2_E~0); 134588#L582-1 assume !(1 == ~T3_E~0); 134873#L587-1 assume !(1 == ~T4_E~0); 134882#L592-1 assume !(1 == ~E_M~0); 134533#L597-1 assume !(1 == ~E_1~0); 134534#L602-1 assume !(1 == ~E_2~0); 134752#L607-1 assume !(1 == ~E_3~0); 134753#L612-1 assume !(1 == ~E_4~0); 134700#L617-1 assume { :end_inline_reset_delta_events } true; 134701#L803-2 assume !false; 135603#L804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 135564#L489 [2022-12-13 20:37:55,011 INFO L750 eck$LassoCheckResult]: Loop: 135564#L489 assume !false; 135560#L424 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 135555#L386 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 135553#L413 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 135551#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 135548#L428 assume 0 != eval_~tmp~0#1; 135545#L428-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 135542#L436 assume !(0 != eval_~tmp_ndt_1~0#1); 135540#L433 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 135526#L450 assume !(0 != eval_~tmp_ndt_2~0#1); 135537#L447 assume !(0 == ~t2_st~0); 135612#L461 assume !(0 == ~t3_st~0); 135606#L475 assume !(0 == ~t4_st~0); 135564#L489 [2022-12-13 20:37:55,011 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 20:37:55,011 INFO L85 PathProgramCache]: Analyzing trace with hash 39728939, now seen corresponding path program 2 times [2022-12-13 20:37:55,011 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 20:37:55,011 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1391648462] [2022-12-13 20:37:55,011 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:37:55,011 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 20:37:55,017 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 20:37:55,017 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 20:37:55,021 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 20:37:55,026 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 20:37:55,026 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 20:37:55,026 INFO L85 PathProgramCache]: Analyzing trace with hash 1507047706, now seen corresponding path program 1 times [2022-12-13 20:37:55,027 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 20:37:55,027 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1259458685] [2022-12-13 20:37:55,027 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:37:55,027 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 20:37:55,029 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 20:37:55,029 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 20:37:55,031 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 20:37:55,032 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 20:37:55,032 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 20:37:55,032 INFO L85 PathProgramCache]: Analyzing trace with hash 1424619056, now seen corresponding path program 1 times [2022-12-13 20:37:55,032 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 20:37:55,033 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2110876814] [2022-12-13 20:37:55,033 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:37:55,033 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 20:37:55,039 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 20:37:55,056 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 20:37:55,056 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 20:37:55,057 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2110876814] [2022-12-13 20:37:55,057 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2110876814] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 20:37:55,057 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 20:37:55,057 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 20:37:55,057 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2075457025] [2022-12-13 20:37:55,057 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 20:37:55,139 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 20:37:55,139 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 20:37:55,140 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 20:37:55,140 INFO L87 Difference]: Start difference. First operand 11266 states and 15149 transitions. cyclomatic complexity: 3889 Second operand has 3 states, 3 states have (on average 25.666666666666668) internal successors, (77), 3 states have internal predecessors, (77), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 20:37:55,209 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 20:37:55,209 INFO L93 Difference]: Finished difference Result 20858 states and 27889 transitions. [2022-12-13 20:37:55,209 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 20858 states and 27889 transitions. [2022-12-13 20:37:55,302 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 20664 [2022-12-13 20:37:55,331 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 20858 states to 20858 states and 27889 transitions. [2022-12-13 20:37:55,331 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 20858 [2022-12-13 20:37:55,338 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 20858 [2022-12-13 20:37:55,338 INFO L73 IsDeterministic]: Start isDeterministic. Operand 20858 states and 27889 transitions. [2022-12-13 20:37:55,346 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 20:37:55,346 INFO L218 hiAutomatonCegarLoop]: Abstraction has 20858 states and 27889 transitions. [2022-12-13 20:37:55,353 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 20858 states and 27889 transitions. [2022-12-13 20:37:55,494 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 20858 to 20368. [2022-12-13 20:37:55,510 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 20368 states, 20368 states have (on average 1.3383248232521603) internal successors, (27259), 20367 states have internal predecessors, (27259), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 20:37:55,542 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 20368 states to 20368 states and 27259 transitions. [2022-12-13 20:37:55,542 INFO L240 hiAutomatonCegarLoop]: Abstraction has 20368 states and 27259 transitions. [2022-12-13 20:37:55,543 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 20:37:55,543 INFO L428 stractBuchiCegarLoop]: Abstraction has 20368 states and 27259 transitions. [2022-12-13 20:37:55,543 INFO L335 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2022-12-13 20:37:55,544 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 20368 states and 27259 transitions. [2022-12-13 20:37:55,598 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 20174 [2022-12-13 20:37:55,598 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 20:37:55,598 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 20:37:55,599 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 20:37:55,599 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 20:37:55,599 INFO L748 eck$LassoCheckResult]: Stem: 166869#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 166870#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 166986#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 166987#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 166780#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 166781#L353-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 167083#L358-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 166723#L363-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 166724#L368-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 166860#L373-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 166751#L514 assume !(0 == ~M_E~0); 166752#L514-2 assume !(0 == ~T1_E~0); 167109#L519-1 assume !(0 == ~T2_E~0); 166711#L524-1 assume !(0 == ~T3_E~0); 166712#L529-1 assume !(0 == ~T4_E~0); 166837#L534-1 assume !(0 == ~E_M~0); 167048#L539-1 assume !(0 == ~E_1~0); 167049#L544-1 assume !(0 == ~E_2~0); 167081#L549-1 assume !(0 == ~E_3~0); 167082#L554-1 assume !(0 == ~E_4~0); 166706#L559-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 166707#L250 assume !(1 == ~m_pc~0); 166936#L250-2 is_master_triggered_~__retres1~0#1 := 0; 167085#L261 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 166850#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 166851#L637 assume !(0 != activate_threads_~tmp~1#1); 166713#L637-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 166714#L269 assume !(1 == ~t1_pc~0); 166652#L269-2 is_transmit1_triggered_~__retres1~1#1 := 0; 166832#L280 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 166700#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 166701#L645 assume !(0 != activate_threads_~tmp___0~0#1); 166900#L645-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 166901#L288 assume !(1 == ~t2_pc~0); 166894#L288-2 is_transmit2_triggered_~__retres1~2#1 := 0; 166895#L299 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 166992#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 166993#L653 assume !(0 != activate_threads_~tmp___1~0#1); 167043#L653-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 166921#L307 assume !(1 == ~t3_pc~0); 166853#L307-2 is_transmit3_triggered_~__retres1~3#1 := 0; 166854#L318 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 166655#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 166656#L661 assume !(0 != activate_threads_~tmp___2~0#1); 166867#L661-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 166868#L326 assume !(1 == ~t4_pc~0); 166667#L326-2 is_transmit4_triggered_~__retres1~4#1 := 0; 166668#L337 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 166755#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 166756#L669 assume !(0 != activate_threads_~tmp___3~0#1); 167045#L669-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 167046#L572 assume !(1 == ~M_E~0); 167086#L572-2 assume !(1 == ~T1_E~0); 166719#L577-1 assume !(1 == ~T2_E~0); 166720#L582-1 assume !(1 == ~T3_E~0); 167027#L587-1 assume !(1 == ~T4_E~0); 167037#L592-1 assume !(1 == ~E_M~0); 166659#L597-1 assume !(1 == ~E_1~0); 166660#L602-1 assume !(1 == ~E_2~0); 166891#L607-1 assume !(1 == ~E_3~0); 166892#L612-1 assume !(1 == ~E_4~0); 166835#L617-1 assume { :end_inline_reset_delta_events } true; 166836#L803-2 assume !false; 172567#L804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 172561#L489 [2022-12-13 20:37:55,599 INFO L750 eck$LassoCheckResult]: Loop: 172561#L489 assume !false; 172555#L424 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 172551#L386 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 172547#L413 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 172420#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 172415#L428 assume 0 != eval_~tmp~0#1; 172412#L428-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 172407#L436 assume !(0 != eval_~tmp_ndt_1~0#1); 172374#L433 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 172322#L450 assume !(0 != eval_~tmp_ndt_2~0#1); 172370#L447 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 171371#L464 assume !(0 != eval_~tmp_ndt_3~0#1); 172577#L461 assume !(0 == ~t3_st~0); 172570#L475 assume !(0 == ~t4_st~0); 172561#L489 [2022-12-13 20:37:55,599 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 20:37:55,599 INFO L85 PathProgramCache]: Analyzing trace with hash 39728939, now seen corresponding path program 3 times [2022-12-13 20:37:55,600 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 20:37:55,600 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [974842421] [2022-12-13 20:37:55,600 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:37:55,600 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 20:37:55,609 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 20:37:55,609 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 20:37:55,615 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 20:37:55,623 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 20:37:55,623 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 20:37:55,623 INFO L85 PathProgramCache]: Analyzing trace with hash -530907670, now seen corresponding path program 1 times [2022-12-13 20:37:55,624 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 20:37:55,624 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1950218867] [2022-12-13 20:37:55,624 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:37:55,624 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 20:37:55,627 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 20:37:55,628 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 20:37:55,629 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 20:37:55,631 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 20:37:55,631 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 20:37:55,631 INFO L85 PathProgramCache]: Analyzing trace with hash 1208771476, now seen corresponding path program 1 times [2022-12-13 20:37:55,631 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 20:37:55,631 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [729557775] [2022-12-13 20:37:55,632 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:37:55,632 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 20:37:55,639 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 20:37:55,662 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 20:37:55,662 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 20:37:55,662 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [729557775] [2022-12-13 20:37:55,662 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [729557775] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 20:37:55,663 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 20:37:55,663 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 20:37:55,663 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1209304098] [2022-12-13 20:37:55,663 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 20:37:55,749 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 20:37:55,750 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 20:37:55,750 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 20:37:55,750 INFO L87 Difference]: Start difference. First operand 20368 states and 27259 transitions. cyclomatic complexity: 6897 Second operand has 3 states, 3 states have (on average 26.0) internal successors, (78), 3 states have internal predecessors, (78), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 20:37:55,866 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 20:37:55,866 INFO L93 Difference]: Finished difference Result 35922 states and 47917 transitions. [2022-12-13 20:37:55,866 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 35922 states and 47917 transitions. [2022-12-13 20:37:55,996 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 35600 [2022-12-13 20:37:56,122 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 35922 states to 35922 states and 47917 transitions. [2022-12-13 20:37:56,122 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 35922 [2022-12-13 20:37:56,138 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 35922 [2022-12-13 20:37:56,138 INFO L73 IsDeterministic]: Start isDeterministic. Operand 35922 states and 47917 transitions. [2022-12-13 20:37:56,156 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 20:37:56,156 INFO L218 hiAutomatonCegarLoop]: Abstraction has 35922 states and 47917 transitions. [2022-12-13 20:37:56,169 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 35922 states and 47917 transitions. [2022-12-13 20:37:56,348 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 35922 to 34746. [2022-12-13 20:37:56,373 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 34746 states, 34746 states have (on average 1.3387728083808208) internal successors, (46517), 34745 states have internal predecessors, (46517), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 20:37:56,414 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 34746 states to 34746 states and 46517 transitions. [2022-12-13 20:37:56,414 INFO L240 hiAutomatonCegarLoop]: Abstraction has 34746 states and 46517 transitions. [2022-12-13 20:37:56,414 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 20:37:56,415 INFO L428 stractBuchiCegarLoop]: Abstraction has 34746 states and 46517 transitions. [2022-12-13 20:37:56,415 INFO L335 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2022-12-13 20:37:56,415 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 34746 states and 46517 transitions. [2022-12-13 20:37:56,518 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 34424 [2022-12-13 20:37:56,518 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 20:37:56,518 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 20:37:56,518 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 20:37:56,518 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 20:37:56,518 INFO L748 eck$LassoCheckResult]: Stem: 223169#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 223170#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 223289#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 223290#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 223077#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 223078#L353-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 223385#L358-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 223020#L363-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 223021#L368-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 223161#L373-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 223049#L514 assume !(0 == ~M_E~0); 223050#L514-2 assume !(0 == ~T1_E~0); 223408#L519-1 assume !(0 == ~T2_E~0); 223008#L524-1 assume !(0 == ~T3_E~0); 223009#L529-1 assume !(0 == ~T4_E~0); 223136#L534-1 assume !(0 == ~E_M~0); 223350#L539-1 assume !(0 == ~E_1~0); 223351#L544-1 assume !(0 == ~E_2~0); 223381#L549-1 assume !(0 == ~E_3~0); 223382#L554-1 assume !(0 == ~E_4~0); 223003#L559-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 223004#L250 assume !(1 == ~m_pc~0); 223240#L250-2 is_master_triggered_~__retres1~0#1 := 0; 223386#L261 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 223151#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 223152#L637 assume !(0 != activate_threads_~tmp~1#1); 223010#L637-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 223011#L269 assume !(1 == ~t1_pc~0); 222949#L269-2 is_transmit1_triggered_~__retres1~1#1 := 0; 223131#L280 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 222999#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 223000#L645 assume !(0 != activate_threads_~tmp___0~0#1); 223202#L645-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 223203#L288 assume !(1 == ~t2_pc~0); 223194#L288-2 is_transmit2_triggered_~__retres1~2#1 := 0; 223195#L299 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 223294#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 223295#L653 assume !(0 != activate_threads_~tmp___1~0#1); 223345#L653-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 223224#L307 assume !(1 == ~t3_pc~0); 223154#L307-2 is_transmit3_triggered_~__retres1~3#1 := 0; 223155#L318 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 222952#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 222953#L661 assume !(0 != activate_threads_~tmp___2~0#1); 223167#L661-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 223168#L326 assume !(1 == ~t4_pc~0); 222964#L326-2 is_transmit4_triggered_~__retres1~4#1 := 0; 222965#L337 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 223051#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 223052#L669 assume !(0 != activate_threads_~tmp___3~0#1); 223347#L669-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 223348#L572 assume !(1 == ~M_E~0); 223387#L572-2 assume !(1 == ~T1_E~0); 223016#L577-1 assume !(1 == ~T2_E~0); 223017#L582-1 assume !(1 == ~T3_E~0); 223328#L587-1 assume !(1 == ~T4_E~0); 223337#L592-1 assume !(1 == ~E_M~0); 222962#L597-1 assume !(1 == ~E_1~0); 222963#L602-1 assume !(1 == ~E_2~0); 223191#L607-1 assume !(1 == ~E_3~0); 223192#L612-1 assume !(1 == ~E_4~0); 223134#L617-1 assume { :end_inline_reset_delta_events } true; 223135#L803-2 assume !false; 234554#L804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 234315#L489 [2022-12-13 20:37:56,518 INFO L750 eck$LassoCheckResult]: Loop: 234315#L489 assume !false; 234547#L424 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 234548#L386 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 234538#L413 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 234539#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 234532#L428 assume 0 != eval_~tmp~0#1; 234533#L428-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 234959#L436 assume !(0 != eval_~tmp_ndt_1~0#1); 234319#L433 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 234312#L450 assume !(0 != eval_~tmp_ndt_2~0#1); 231404#L447 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 231402#L464 assume !(0 != eval_~tmp_ndt_3~0#1); 231403#L461 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 232874#L478 assume !(0 != eval_~tmp_ndt_4~0#1); 233717#L475 assume !(0 == ~t4_st~0); 234315#L489 [2022-12-13 20:37:56,519 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 20:37:56,519 INFO L85 PathProgramCache]: Analyzing trace with hash 39728939, now seen corresponding path program 4 times [2022-12-13 20:37:56,519 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 20:37:56,519 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1411996825] [2022-12-13 20:37:56,519 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:37:56,519 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 20:37:56,528 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 20:37:56,528 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 20:37:56,533 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 20:37:56,543 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 20:37:56,543 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 20:37:56,543 INFO L85 PathProgramCache]: Analyzing trace with hash 721579562, now seen corresponding path program 1 times [2022-12-13 20:37:56,543 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 20:37:56,543 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [65225693] [2022-12-13 20:37:56,543 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:37:56,544 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 20:37:56,547 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 20:37:56,547 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 20:37:56,548 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 20:37:56,549 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 20:37:56,549 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 20:37:56,549 INFO L85 PathProgramCache]: Analyzing trace with hash -1182941760, now seen corresponding path program 1 times [2022-12-13 20:37:56,550 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 20:37:56,550 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1124298902] [2022-12-13 20:37:56,550 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:37:56,550 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 20:37:56,555 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 20:37:56,572 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 20:37:56,572 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 20:37:56,572 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1124298902] [2022-12-13 20:37:56,572 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1124298902] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 20:37:56,573 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 20:37:56,573 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-12-13 20:37:56,573 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1281553565] [2022-12-13 20:37:56,573 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 20:37:56,671 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 20:37:56,671 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 20:37:56,671 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 20:37:56,672 INFO L87 Difference]: Start difference. First operand 34746 states and 46517 transitions. cyclomatic complexity: 11777 Second operand has 3 states, 2 states have (on average 39.5) internal successors, (79), 3 states have internal predecessors, (79), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 20:37:56,793 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 20:37:56,793 INFO L93 Difference]: Finished difference Result 39504 states and 52667 transitions. [2022-12-13 20:37:56,793 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 39504 states and 52667 transitions. [2022-12-13 20:37:56,907 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 39262 [2022-12-13 20:37:57,017 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 39504 states to 39504 states and 52667 transitions. [2022-12-13 20:37:57,017 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 39504 [2022-12-13 20:37:57,033 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 39504 [2022-12-13 20:37:57,033 INFO L73 IsDeterministic]: Start isDeterministic. Operand 39504 states and 52667 transitions. [2022-12-13 20:37:57,052 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 20:37:57,052 INFO L218 hiAutomatonCegarLoop]: Abstraction has 39504 states and 52667 transitions. [2022-12-13 20:37:57,069 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 39504 states and 52667 transitions. [2022-12-13 20:37:57,315 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 39504 to 39056. [2022-12-13 20:37:57,332 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 39056 states, 39056 states have (on average 1.3370288816058993) internal successors, (52219), 39055 states have internal predecessors, (52219), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 20:37:57,391 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 39056 states to 39056 states and 52219 transitions. [2022-12-13 20:37:57,392 INFO L240 hiAutomatonCegarLoop]: Abstraction has 39056 states and 52219 transitions. [2022-12-13 20:37:57,392 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 20:37:57,392 INFO L428 stractBuchiCegarLoop]: Abstraction has 39056 states and 52219 transitions. [2022-12-13 20:37:57,393 INFO L335 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2022-12-13 20:37:57,393 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 39056 states and 52219 transitions. [2022-12-13 20:37:57,496 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 38814 [2022-12-13 20:37:57,496 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 20:37:57,496 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 20:37:57,497 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 20:37:57,497 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 20:37:57,497 INFO L748 eck$LassoCheckResult]: Stem: 297433#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 297434#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 297555#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 297556#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 297336#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 297337#L353-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 297647#L358-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 297281#L363-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 297282#L368-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 297423#L373-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 297309#L514 assume !(0 == ~M_E~0); 297310#L514-2 assume !(0 == ~T1_E~0); 297674#L519-1 assume !(0 == ~T2_E~0); 297267#L524-1 assume !(0 == ~T3_E~0); 297268#L529-1 assume !(0 == ~T4_E~0); 297396#L534-1 assume !(0 == ~E_M~0); 297613#L539-1 assume !(0 == ~E_1~0); 297614#L544-1 assume !(0 == ~E_2~0); 297644#L549-1 assume !(0 == ~E_3~0); 297645#L554-1 assume !(0 == ~E_4~0); 297262#L559-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 297263#L250 assume !(1 == ~m_pc~0); 297504#L250-2 is_master_triggered_~__retres1~0#1 := 0; 297648#L261 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 297411#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 297412#L637 assume !(0 != activate_threads_~tmp~1#1); 297271#L637-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 297272#L269 assume !(1 == ~t1_pc~0); 297208#L269-2 is_transmit1_triggered_~__retres1~1#1 := 0; 297391#L280 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 297258#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 297259#L645 assume !(0 != activate_threads_~tmp___0~0#1); 297465#L645-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 297466#L288 assume !(1 == ~t2_pc~0); 297460#L288-2 is_transmit2_triggered_~__retres1~2#1 := 0; 297461#L299 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 297560#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 297561#L653 assume !(0 != activate_threads_~tmp___1~0#1); 297608#L653-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 297487#L307 assume !(1 == ~t3_pc~0); 297414#L307-2 is_transmit3_triggered_~__retres1~3#1 := 0; 297415#L318 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 297211#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 297212#L661 assume !(0 != activate_threads_~tmp___2~0#1); 297431#L661-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 297432#L326 assume !(1 == ~t4_pc~0); 297223#L326-2 is_transmit4_triggered_~__retres1~4#1 := 0; 297224#L337 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 297311#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 297312#L669 assume !(0 != activate_threads_~tmp___3~0#1); 297610#L669-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 297611#L572 assume !(1 == ~M_E~0); 297649#L572-2 assume !(1 == ~T1_E~0); 297277#L577-1 assume !(1 == ~T2_E~0); 297278#L582-1 assume !(1 == ~T3_E~0); 297591#L587-1 assume !(1 == ~T4_E~0); 297601#L592-1 assume !(1 == ~E_M~0); 297221#L597-1 assume !(1 == ~E_1~0); 297222#L602-1 assume !(1 == ~E_2~0); 297457#L607-1 assume !(1 == ~E_3~0); 297458#L612-1 assume !(1 == ~E_4~0); 297394#L617-1 assume { :end_inline_reset_delta_events } true; 297395#L803-2 assume !false; 308548#L804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 308099#L489 [2022-12-13 20:37:57,498 INFO L750 eck$LassoCheckResult]: Loop: 308099#L489 assume !false; 308547#L424 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 308545#L386 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 308542#L413 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 308541#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 308540#L428 assume 0 != eval_~tmp~0#1; 308538#L428-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 308536#L436 assume !(0 != eval_~tmp_ndt_1~0#1); 305557#L433 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 305554#L450 assume !(0 != eval_~tmp_ndt_2~0#1); 305552#L447 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 305111#L464 assume !(0 != eval_~tmp_ndt_3~0#1); 305548#L461 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 305472#L478 assume !(0 != eval_~tmp_ndt_4~0#1); 305546#L475 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0#1;eval_~tmp_ndt_5~0#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; 308098#L492 assume !(0 != eval_~tmp_ndt_5~0#1); 308099#L489 [2022-12-13 20:37:57,498 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 20:37:57,498 INFO L85 PathProgramCache]: Analyzing trace with hash 39728939, now seen corresponding path program 5 times [2022-12-13 20:37:57,498 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 20:37:57,498 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [634277203] [2022-12-13 20:37:57,498 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:37:57,498 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 20:37:57,506 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 20:37:57,506 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 20:37:57,510 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 20:37:57,517 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 20:37:57,517 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 20:37:57,518 INFO L85 PathProgramCache]: Analyzing trace with hash 894126298, now seen corresponding path program 1 times [2022-12-13 20:37:57,518 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 20:37:57,518 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [704028653] [2022-12-13 20:37:57,518 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:37:57,518 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 20:37:57,521 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 20:37:57,521 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 20:37:57,522 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 20:37:57,523 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 20:37:57,524 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 20:37:57,524 INFO L85 PathProgramCache]: Analyzing trace with hash 1983507460, now seen corresponding path program 1 times [2022-12-13 20:37:57,524 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 20:37:57,524 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1807637258] [2022-12-13 20:37:57,524 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:37:57,524 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 20:37:57,531 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 20:37:57,531 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 20:37:57,536 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 20:37:57,545 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 20:37:58,636 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 20:37:58,636 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 20:37:58,649 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 20:37:58,766 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 13.12 08:37:58 BoogieIcfgContainer [2022-12-13 20:37:58,766 INFO L132 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2022-12-13 20:37:58,766 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2022-12-13 20:37:58,766 INFO L271 PluginConnector]: Initializing Witness Printer... [2022-12-13 20:37:58,767 INFO L275 PluginConnector]: Witness Printer initialized [2022-12-13 20:37:58,767 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.12 08:37:50" (3/4) ... [2022-12-13 20:37:58,769 INFO L134 WitnessPrinter]: Generating witness for non-termination counterexample [2022-12-13 20:37:58,820 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7dcf1f71-2ccc-4322-b384-52ae8173b8c8/bin/uautomizer-uyxdKDjOR8/witness.graphml [2022-12-13 20:37:58,820 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2022-12-13 20:37:58,821 INFO L158 Benchmark]: Toolchain (without parser) took 9532.93ms. Allocated memory was 144.7MB in the beginning and 1.9GB in the end (delta: 1.8GB). Free memory was 109.2MB in the beginning and 1.2GB in the end (delta: -1.0GB). Peak memory consumption was 752.3MB. Max. memory is 16.1GB. [2022-12-13 20:37:58,821 INFO L158 Benchmark]: CDTParser took 0.11ms. Allocated memory is still 144.7MB. Free memory is still 86.0MB. There was no memory consumed. Max. memory is 16.1GB. [2022-12-13 20:37:58,821 INFO L158 Benchmark]: CACSL2BoogieTranslator took 222.01ms. Allocated memory is still 144.7MB. Free memory was 108.8MB in the beginning and 93.6MB in the end (delta: 15.2MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB. [2022-12-13 20:37:58,821 INFO L158 Benchmark]: Boogie Procedure Inliner took 57.73ms. Allocated memory is still 144.7MB. Free memory was 93.6MB in the beginning and 89.4MB in the end (delta: 4.2MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2022-12-13 20:37:58,821 INFO L158 Benchmark]: Boogie Preprocessor took 37.87ms. Allocated memory is still 144.7MB. Free memory was 89.4MB in the beginning and 85.2MB in the end (delta: 4.2MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2022-12-13 20:37:58,822 INFO L158 Benchmark]: RCFGBuilder took 771.41ms. Allocated memory was 144.7MB in the beginning and 174.1MB in the end (delta: 29.4MB). Free memory was 85.2MB in the beginning and 129.3MB in the end (delta: -44.1MB). Peak memory consumption was 46.6MB. Max. memory is 16.1GB. [2022-12-13 20:37:58,822 INFO L158 Benchmark]: BuchiAutomizer took 8385.64ms. Allocated memory was 174.1MB in the beginning and 1.9GB in the end (delta: 1.8GB). Free memory was 128.3MB in the beginning and 1.2GB in the end (delta: -1.0GB). Peak memory consumption was 730.9MB. Max. memory is 16.1GB. [2022-12-13 20:37:58,822 INFO L158 Benchmark]: Witness Printer took 54.06ms. Allocated memory is still 1.9GB. Free memory was 1.2GB in the beginning and 1.2GB in the end (delta: 9.4MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. [2022-12-13 20:37:58,823 INFO L339 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.11ms. Allocated memory is still 144.7MB. Free memory is still 86.0MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 222.01ms. Allocated memory is still 144.7MB. Free memory was 108.8MB in the beginning and 93.6MB in the end (delta: 15.2MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 57.73ms. Allocated memory is still 144.7MB. Free memory was 93.6MB in the beginning and 89.4MB in the end (delta: 4.2MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * Boogie Preprocessor took 37.87ms. Allocated memory is still 144.7MB. Free memory was 89.4MB in the beginning and 85.2MB in the end (delta: 4.2MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * RCFGBuilder took 771.41ms. Allocated memory was 144.7MB in the beginning and 174.1MB in the end (delta: 29.4MB). Free memory was 85.2MB in the beginning and 129.3MB in the end (delta: -44.1MB). Peak memory consumption was 46.6MB. Max. memory is 16.1GB. * BuchiAutomizer took 8385.64ms. Allocated memory was 174.1MB in the beginning and 1.9GB in the end (delta: 1.8GB). Free memory was 128.3MB in the beginning and 1.2GB in the end (delta: -1.0GB). Peak memory consumption was 730.9MB. Max. memory is 16.1GB. * Witness Printer took 54.06ms. Allocated memory is still 1.9GB. Free memory was 1.2GB in the beginning and 1.2GB in the end (delta: 9.4MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 21 terminating modules (21 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.21 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 39056 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 8.2s and 22 iterations. TraceHistogramMax:1. Analysis of lassos took 3.1s. Construction of modules took 0.4s. Büchi inclusion checks took 4.0s. Highest rank in rank-based complementation 0. Minimization of det autom 21. Minimization of nondet autom 0. Automata minimization 1.8s AutomataMinimizationTime, 21 MinimizatonAttempts, 16627 StatesRemovedByMinimization, 14 NontrivialMinimizations. Non-live state removal took 1.1s Buchi closure took 0.0s. Biggest automaton had -1 states and ocurred in iteration -1. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 17202 SdHoareTripleChecker+Valid, 0.6s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 17202 mSDsluCounter, 28224 SdHoareTripleChecker+Invalid, 0.5s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 13929 mSDsCounter, 249 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 660 IncrementalHoareTripleChecker+Invalid, 909 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 249 mSolverCounterUnsat, 14295 mSDtfsCounter, 660 mSolverCounterSat, 0.1s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI3 SFLT0 conc4 concLT0 SILN1 SILU0 SILI13 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s InitialAbstractionConstructionTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - LassoShapedNonTerminationArgument [Line: 423]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite program execution. Stem: [L24] int m_pc = 0; [L25] int t1_pc = 0; [L26] int t2_pc = 0; [L27] int t3_pc = 0; [L28] int t4_pc = 0; [L29] int m_st ; [L30] int t1_st ; [L31] int t2_st ; [L32] int t3_st ; [L33] int t4_st ; [L34] int m_i ; [L35] int t1_i ; [L36] int t2_i ; [L37] int t3_i ; [L38] int t4_i ; [L39] int M_E = 2; [L40] int T1_E = 2; [L41] int T2_E = 2; [L42] int T3_E = 2; [L43] int T4_E = 2; [L44] int E_M = 2; [L45] int E_1 = 2; [L46] int E_2 = 2; [L47] int E_3 = 2; [L48] int E_4 = 2; [L55] int token ; [L57] int local ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=0, m_pc=0, m_st=0, T1_E=2, t1_i=0, t1_pc=0, t1_st=0, T2_E=2, t2_i=0, t2_pc=0, t2_st=0, T3_E=2, t3_i=0, t3_pc=0, t3_st=0, T4_E=2, t4_i=0, t4_pc=0, t4_st=0, token=0] [L848] int __retres1 ; [L852] CALL init_model() [L760] m_i = 1 [L761] t1_i = 1 [L762] t2_i = 1 [L763] t3_i = 1 [L764] t4_i = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L852] RET init_model() [L853] CALL start_simulation() [L789] int kernel_st ; [L790] int tmp ; [L791] int tmp___0 ; [L795] kernel_st = 0 [L796] FCALL update_channels() [L797] CALL init_threads() [L353] COND TRUE m_i == 1 [L354] m_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L358] COND TRUE t1_i == 1 [L359] t1_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L363] COND TRUE t2_i == 1 [L364] t2_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L368] COND TRUE t3_i == 1 [L369] t3_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L373] COND TRUE t4_i == 1 [L374] t4_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L797] RET init_threads() [L798] CALL fire_delta_events() [L514] COND FALSE !(M_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L519] COND FALSE !(T1_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L524] COND FALSE !(T2_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L529] COND FALSE !(T3_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L534] COND FALSE !(T4_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L539] COND FALSE !(E_M == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L544] COND FALSE !(E_1 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L549] COND FALSE !(E_2 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L554] COND FALSE !(E_3 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L559] COND FALSE !(E_4 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L798] RET fire_delta_events() [L799] CALL activate_threads() [L627] int tmp ; [L628] int tmp___0 ; [L629] int tmp___1 ; [L630] int tmp___2 ; [L631] int tmp___3 ; [L635] CALL, EXPR is_master_triggered() [L247] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L250] COND FALSE !(m_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L260] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L262] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L635] RET, EXPR is_master_triggered() [L635] tmp = is_master_triggered() [L637] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, tmp=0, token=0] [L643] CALL, EXPR is_transmit1_triggered() [L266] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L269] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L279] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L281] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L643] RET, EXPR is_transmit1_triggered() [L643] tmp___0 = is_transmit1_triggered() [L645] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, tmp=0, tmp___0=0, token=0] [L651] CALL, EXPR is_transmit2_triggered() [L285] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L288] COND FALSE !(t2_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L298] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L300] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L651] RET, EXPR is_transmit2_triggered() [L651] tmp___1 = is_transmit2_triggered() [L653] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, tmp=0, tmp___0=0, tmp___1=0, token=0] [L659] CALL, EXPR is_transmit3_triggered() [L304] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L307] COND FALSE !(t3_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L317] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L319] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L659] RET, EXPR is_transmit3_triggered() [L659] tmp___2 = is_transmit3_triggered() [L661] COND FALSE !(\read(tmp___2)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, token=0] [L667] CALL, EXPR is_transmit4_triggered() [L323] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L326] COND FALSE !(t4_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L336] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L338] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L667] RET, EXPR is_transmit4_triggered() [L667] tmp___3 = is_transmit4_triggered() [L669] COND FALSE !(\read(tmp___3)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0, token=0] [L799] RET activate_threads() [L800] CALL reset_delta_events() [L572] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L577] COND FALSE !(T1_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L582] COND FALSE !(T2_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L587] COND FALSE !(T3_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L592] COND FALSE !(T4_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L597] COND FALSE !(E_M == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L602] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L607] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L612] COND FALSE !(E_3 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L617] COND FALSE !(E_4 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L800] RET reset_delta_events() [L803] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, kernel_st=0, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L806] kernel_st = 1 [L807] CALL eval() [L419] int tmp ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] Loop: [L423] COND TRUE 1 [L426] CALL, EXPR exists_runnable_thread() [L383] int __retres1 ; [L386] COND TRUE m_st == 0 [L387] __retres1 = 1 [L414] return (__retres1); [L426] RET, EXPR exists_runnable_thread() [L426] tmp = exists_runnable_thread() [L428] COND TRUE \read(tmp) [L433] COND TRUE m_st == 0 [L434] int tmp_ndt_1; [L435] tmp_ndt_1 = __VERIFIER_nondet_int() [L436] COND FALSE !(\read(tmp_ndt_1)) [L447] COND TRUE t1_st == 0 [L448] int tmp_ndt_2; [L449] tmp_ndt_2 = __VERIFIER_nondet_int() [L450] COND FALSE !(\read(tmp_ndt_2)) [L461] COND TRUE t2_st == 0 [L462] int tmp_ndt_3; [L463] tmp_ndt_3 = __VERIFIER_nondet_int() [L464] COND FALSE !(\read(tmp_ndt_3)) [L475] COND TRUE t3_st == 0 [L476] int tmp_ndt_4; [L477] tmp_ndt_4 = __VERIFIER_nondet_int() [L478] COND FALSE !(\read(tmp_ndt_4)) [L489] COND TRUE t4_st == 0 [L490] int tmp_ndt_5; [L491] tmp_ndt_5 = __VERIFIER_nondet_int() [L492] COND FALSE !(\read(tmp_ndt_5)) End of lasso representation. - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 423]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L24] int m_pc = 0; [L25] int t1_pc = 0; [L26] int t2_pc = 0; [L27] int t3_pc = 0; [L28] int t4_pc = 0; [L29] int m_st ; [L30] int t1_st ; [L31] int t2_st ; [L32] int t3_st ; [L33] int t4_st ; [L34] int m_i ; [L35] int t1_i ; [L36] int t2_i ; [L37] int t3_i ; [L38] int t4_i ; [L39] int M_E = 2; [L40] int T1_E = 2; [L41] int T2_E = 2; [L42] int T3_E = 2; [L43] int T4_E = 2; [L44] int E_M = 2; [L45] int E_1 = 2; [L46] int E_2 = 2; [L47] int E_3 = 2; [L48] int E_4 = 2; [L55] int token ; [L57] int local ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=0, m_pc=0, m_st=0, T1_E=2, t1_i=0, t1_pc=0, t1_st=0, T2_E=2, t2_i=0, t2_pc=0, t2_st=0, T3_E=2, t3_i=0, t3_pc=0, t3_st=0, T4_E=2, t4_i=0, t4_pc=0, t4_st=0, token=0] [L848] int __retres1 ; [L852] CALL init_model() [L760] m_i = 1 [L761] t1_i = 1 [L762] t2_i = 1 [L763] t3_i = 1 [L764] t4_i = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L852] RET init_model() [L853] CALL start_simulation() [L789] int kernel_st ; [L790] int tmp ; [L791] int tmp___0 ; [L795] kernel_st = 0 [L796] FCALL update_channels() [L797] CALL init_threads() [L353] COND TRUE m_i == 1 [L354] m_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L358] COND TRUE t1_i == 1 [L359] t1_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L363] COND TRUE t2_i == 1 [L364] t2_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L368] COND TRUE t3_i == 1 [L369] t3_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L373] COND TRUE t4_i == 1 [L374] t4_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L797] RET init_threads() [L798] CALL fire_delta_events() [L514] COND FALSE !(M_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L519] COND FALSE !(T1_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L524] COND FALSE !(T2_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L529] COND FALSE !(T3_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L534] COND FALSE !(T4_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L539] COND FALSE !(E_M == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L544] COND FALSE !(E_1 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L549] COND FALSE !(E_2 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L554] COND FALSE !(E_3 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L559] COND FALSE !(E_4 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L798] RET fire_delta_events() [L799] CALL activate_threads() [L627] int tmp ; [L628] int tmp___0 ; [L629] int tmp___1 ; [L630] int tmp___2 ; [L631] int tmp___3 ; [L635] CALL, EXPR is_master_triggered() [L247] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L250] COND FALSE !(m_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L260] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L262] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L635] RET, EXPR is_master_triggered() [L635] tmp = is_master_triggered() [L637] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, tmp=0, token=0] [L643] CALL, EXPR is_transmit1_triggered() [L266] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L269] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L279] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L281] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L643] RET, EXPR is_transmit1_triggered() [L643] tmp___0 = is_transmit1_triggered() [L645] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, tmp=0, tmp___0=0, token=0] [L651] CALL, EXPR is_transmit2_triggered() [L285] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L288] COND FALSE !(t2_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L298] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L300] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L651] RET, EXPR is_transmit2_triggered() [L651] tmp___1 = is_transmit2_triggered() [L653] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, tmp=0, tmp___0=0, tmp___1=0, token=0] [L659] CALL, EXPR is_transmit3_triggered() [L304] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L307] COND FALSE !(t3_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L317] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L319] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L659] RET, EXPR is_transmit3_triggered() [L659] tmp___2 = is_transmit3_triggered() [L661] COND FALSE !(\read(tmp___2)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, token=0] [L667] CALL, EXPR is_transmit4_triggered() [L323] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L326] COND FALSE !(t4_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L336] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L338] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L667] RET, EXPR is_transmit4_triggered() [L667] tmp___3 = is_transmit4_triggered() [L669] COND FALSE !(\read(tmp___3)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0, token=0] [L799] RET activate_threads() [L800] CALL reset_delta_events() [L572] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L577] COND FALSE !(T1_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L582] COND FALSE !(T2_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L587] COND FALSE !(T3_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L592] COND FALSE !(T4_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L597] COND FALSE !(E_M == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L602] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L607] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L612] COND FALSE !(E_3 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L617] COND FALSE !(E_4 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L800] RET reset_delta_events() [L803] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, kernel_st=0, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L806] kernel_st = 1 [L807] CALL eval() [L419] int tmp ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] Loop: [L423] COND TRUE 1 [L426] CALL, EXPR exists_runnable_thread() [L383] int __retres1 ; [L386] COND TRUE m_st == 0 [L387] __retres1 = 1 [L414] return (__retres1); [L426] RET, EXPR exists_runnable_thread() [L426] tmp = exists_runnable_thread() [L428] COND TRUE \read(tmp) [L433] COND TRUE m_st == 0 [L434] int tmp_ndt_1; [L435] tmp_ndt_1 = __VERIFIER_nondet_int() [L436] COND FALSE !(\read(tmp_ndt_1)) [L447] COND TRUE t1_st == 0 [L448] int tmp_ndt_2; [L449] tmp_ndt_2 = __VERIFIER_nondet_int() [L450] COND FALSE !(\read(tmp_ndt_2)) [L461] COND TRUE t2_st == 0 [L462] int tmp_ndt_3; [L463] tmp_ndt_3 = __VERIFIER_nondet_int() [L464] COND FALSE !(\read(tmp_ndt_3)) [L475] COND TRUE t3_st == 0 [L476] int tmp_ndt_4; [L477] tmp_ndt_4 = __VERIFIER_nondet_int() [L478] COND FALSE !(\read(tmp_ndt_4)) [L489] COND TRUE t4_st == 0 [L490] int tmp_ndt_5; [L491] tmp_ndt_5 = __VERIFIER_nondet_int() [L492] COND FALSE !(\read(tmp_ndt_5)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2022-12-13 20:37:58,905 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7dcf1f71-2ccc-4322-b384-52ae8173b8c8/bin/uautomizer-uyxdKDjOR8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Forceful destruction successful, exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)