./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/token_ring.04.cil-2.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 2329fc70 Calling Ultimate with: /usr/lib/jvm/java-11-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4779227a-506f-4eeb-bef1-40db864f4417/bin/uautomizer-uyxdKDjOR8/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4779227a-506f-4eeb-bef1-40db864f4417/bin/uautomizer-uyxdKDjOR8/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4779227a-506f-4eeb-bef1-40db864f4417/bin/uautomizer-uyxdKDjOR8/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4779227a-506f-4eeb-bef1-40db864f4417/bin/uautomizer-uyxdKDjOR8/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/token_ring.04.cil-2.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4779227a-506f-4eeb-bef1-40db864f4417/bin/uautomizer-uyxdKDjOR8/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4779227a-506f-4eeb-bef1-40db864f4417/bin/uautomizer-uyxdKDjOR8 --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 05d3b7d21cc48825b4a0189c75f03d768acc6241312029d3e223c1b9b2a509ea --- Real Ultimate output --- [0.001s][warning][os,container] Duplicate cpuset controllers detected. Picking /sys/fs/cgroup/cpuset, skipping /sys/fs/cgroup/cpuset. This is Ultimate 0.2.2-dev-2329fc7 [2022-12-13 14:12:44,226 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-12-13 14:12:44,227 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-12-13 14:12:44,245 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-12-13 14:12:44,246 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-12-13 14:12:44,247 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-12-13 14:12:44,248 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-12-13 14:12:44,250 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-12-13 14:12:44,251 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-12-13 14:12:44,252 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-12-13 14:12:44,253 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-12-13 14:12:44,254 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-12-13 14:12:44,254 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-12-13 14:12:44,255 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-12-13 14:12:44,256 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-12-13 14:12:44,257 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-12-13 14:12:44,258 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-12-13 14:12:44,259 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-12-13 14:12:44,260 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-12-13 14:12:44,262 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-12-13 14:12:44,263 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-12-13 14:12:44,265 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-12-13 14:12:44,266 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-12-13 14:12:44,267 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-12-13 14:12:44,270 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-12-13 14:12:44,270 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-12-13 14:12:44,270 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-12-13 14:12:44,271 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-12-13 14:12:44,272 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-12-13 14:12:44,273 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-12-13 14:12:44,273 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-12-13 14:12:44,273 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-12-13 14:12:44,274 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-12-13 14:12:44,275 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-12-13 14:12:44,276 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-12-13 14:12:44,276 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-12-13 14:12:44,276 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-12-13 14:12:44,277 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-12-13 14:12:44,277 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-12-13 14:12:44,277 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-12-13 14:12:44,278 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-12-13 14:12:44,278 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4779227a-506f-4eeb-bef1-40db864f4417/bin/uautomizer-uyxdKDjOR8/config/svcomp-Termination-32bit-Automizer_Default.epf [2022-12-13 14:12:44,300 INFO L113 SettingsManager]: Loading preferences was successful [2022-12-13 14:12:44,300 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-12-13 14:12:44,307 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-12-13 14:12:44,307 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-12-13 14:12:44,308 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-12-13 14:12:44,308 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-12-13 14:12:44,308 INFO L138 SettingsManager]: * Use SBE=true [2022-12-13 14:12:44,309 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2022-12-13 14:12:44,309 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2022-12-13 14:12:44,309 INFO L138 SettingsManager]: * Use old map elimination=false [2022-12-13 14:12:44,309 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2022-12-13 14:12:44,309 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2022-12-13 14:12:44,310 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2022-12-13 14:12:44,310 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-12-13 14:12:44,310 INFO L138 SettingsManager]: * sizeof long=4 [2022-12-13 14:12:44,310 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2022-12-13 14:12:44,310 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-12-13 14:12:44,311 INFO L138 SettingsManager]: * sizeof POINTER=4 [2022-12-13 14:12:44,311 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-12-13 14:12:44,311 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2022-12-13 14:12:44,311 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2022-12-13 14:12:44,311 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2022-12-13 14:12:44,312 INFO L138 SettingsManager]: * sizeof long double=12 [2022-12-13 14:12:44,312 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-12-13 14:12:44,312 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2022-12-13 14:12:44,312 INFO L138 SettingsManager]: * Use constant arrays=true [2022-12-13 14:12:44,312 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2022-12-13 14:12:44,313 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-12-13 14:12:44,313 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-12-13 14:12:44,313 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-12-13 14:12:44,313 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-12-13 14:12:44,314 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-12-13 14:12:44,314 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4779227a-506f-4eeb-bef1-40db864f4417/bin/uautomizer-uyxdKDjOR8/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4779227a-506f-4eeb-bef1-40db864f4417/bin/uautomizer-uyxdKDjOR8 Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 05d3b7d21cc48825b4a0189c75f03d768acc6241312029d3e223c1b9b2a509ea [2022-12-13 14:12:44,505 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-12-13 14:12:44,525 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-12-13 14:12:44,528 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-12-13 14:12:44,529 INFO L271 PluginConnector]: Initializing CDTParser... [2022-12-13 14:12:44,529 INFO L275 PluginConnector]: CDTParser initialized [2022-12-13 14:12:44,530 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4779227a-506f-4eeb-bef1-40db864f4417/bin/uautomizer-uyxdKDjOR8/../../sv-benchmarks/c/systemc/token_ring.04.cil-2.c [2022-12-13 14:12:47,032 INFO L500 CDTParser]: Created temporary CDT project at NULL [2022-12-13 14:12:47,202 INFO L351 CDTParser]: Found 1 translation units. [2022-12-13 14:12:47,203 INFO L172 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4779227a-506f-4eeb-bef1-40db864f4417/sv-benchmarks/c/systemc/token_ring.04.cil-2.c [2022-12-13 14:12:47,209 INFO L394 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4779227a-506f-4eeb-bef1-40db864f4417/bin/uautomizer-uyxdKDjOR8/data/eb6aee1c5/17a3196901464502bb1c30e53b647985/FLAG05d8008e3 [2022-12-13 14:12:47,607 INFO L402 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4779227a-506f-4eeb-bef1-40db864f4417/bin/uautomizer-uyxdKDjOR8/data/eb6aee1c5/17a3196901464502bb1c30e53b647985 [2022-12-13 14:12:47,609 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-12-13 14:12:47,610 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-12-13 14:12:47,611 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-12-13 14:12:47,611 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-12-13 14:12:47,614 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-12-13 14:12:47,615 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.12 02:12:47" (1/1) ... [2022-12-13 14:12:47,615 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@72c83614 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 02:12:47, skipping insertion in model container [2022-12-13 14:12:47,615 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.12 02:12:47" (1/1) ... [2022-12-13 14:12:47,621 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-12-13 14:12:47,640 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-12-13 14:12:47,737 WARN L237 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4779227a-506f-4eeb-bef1-40db864f4417/sv-benchmarks/c/systemc/token_ring.04.cil-2.c[671,684] [2022-12-13 14:12:47,792 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-12-13 14:12:47,802 INFO L203 MainTranslator]: Completed pre-run [2022-12-13 14:12:47,810 WARN L237 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4779227a-506f-4eeb-bef1-40db864f4417/sv-benchmarks/c/systemc/token_ring.04.cil-2.c[671,684] [2022-12-13 14:12:47,833 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-12-13 14:12:47,846 INFO L208 MainTranslator]: Completed translation [2022-12-13 14:12:47,846 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 02:12:47 WrapperNode [2022-12-13 14:12:47,846 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-12-13 14:12:47,847 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-12-13 14:12:47,847 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-12-13 14:12:47,847 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-12-13 14:12:47,852 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 02:12:47" (1/1) ... [2022-12-13 14:12:47,860 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 02:12:47" (1/1) ... [2022-12-13 14:12:47,893 INFO L138 Inliner]: procedures = 36, calls = 44, calls flagged for inlining = 39, calls inlined = 78, statements flattened = 1074 [2022-12-13 14:12:47,893 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-12-13 14:12:47,894 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-12-13 14:12:47,894 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-12-13 14:12:47,894 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-12-13 14:12:47,903 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 02:12:47" (1/1) ... [2022-12-13 14:12:47,903 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 02:12:47" (1/1) ... [2022-12-13 14:12:47,907 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 02:12:47" (1/1) ... [2022-12-13 14:12:47,907 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 02:12:47" (1/1) ... [2022-12-13 14:12:47,920 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 02:12:47" (1/1) ... [2022-12-13 14:12:47,930 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 02:12:47" (1/1) ... [2022-12-13 14:12:47,932 INFO L185 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 02:12:47" (1/1) ... [2022-12-13 14:12:47,935 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 02:12:47" (1/1) ... [2022-12-13 14:12:47,941 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-12-13 14:12:47,941 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-12-13 14:12:47,942 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-12-13 14:12:47,942 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-12-13 14:12:47,943 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 02:12:47" (1/1) ... [2022-12-13 14:12:47,950 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-12-13 14:12:47,963 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4779227a-506f-4eeb-bef1-40db864f4417/bin/uautomizer-uyxdKDjOR8/z3 [2022-12-13 14:12:47,975 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4779227a-506f-4eeb-bef1-40db864f4417/bin/uautomizer-uyxdKDjOR8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-12-13 14:12:47,977 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4779227a-506f-4eeb-bef1-40db864f4417/bin/uautomizer-uyxdKDjOR8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2022-12-13 14:12:48,012 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-12-13 14:12:48,012 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-12-13 14:12:48,012 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-12-13 14:12:48,012 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-12-13 14:12:48,086 INFO L235 CfgBuilder]: Building ICFG [2022-12-13 14:12:48,088 INFO L261 CfgBuilder]: Building CFG for each procedure with an implementation [2022-12-13 14:12:48,694 INFO L276 CfgBuilder]: Performing block encoding [2022-12-13 14:12:48,703 INFO L295 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-12-13 14:12:48,703 INFO L300 CfgBuilder]: Removed 7 assume(true) statements. [2022-12-13 14:12:48,705 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.12 02:12:48 BoogieIcfgContainer [2022-12-13 14:12:48,705 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-12-13 14:12:48,706 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2022-12-13 14:12:48,706 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2022-12-13 14:12:48,709 INFO L275 PluginConnector]: BuchiAutomizer initialized [2022-12-13 14:12:48,709 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-12-13 14:12:48,710 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 13.12 02:12:47" (1/3) ... [2022-12-13 14:12:48,710 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@cc99770 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 13.12 02:12:48, skipping insertion in model container [2022-12-13 14:12:48,710 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-12-13 14:12:48,710 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 02:12:47" (2/3) ... [2022-12-13 14:12:48,711 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@cc99770 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 13.12 02:12:48, skipping insertion in model container [2022-12-13 14:12:48,711 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-12-13 14:12:48,711 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.12 02:12:48" (3/3) ... [2022-12-13 14:12:48,712 INFO L332 chiAutomizerObserver]: Analyzing ICFG token_ring.04.cil-2.c [2022-12-13 14:12:48,759 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2022-12-13 14:12:48,760 INFO L304 stractBuchiCegarLoop]: Hoare is false [2022-12-13 14:12:48,760 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2022-12-13 14:12:48,760 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2022-12-13 14:12:48,760 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2022-12-13 14:12:48,760 INFO L308 stractBuchiCegarLoop]: Difference is false [2022-12-13 14:12:48,760 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2022-12-13 14:12:48,760 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2022-12-13 14:12:48,765 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 438 states, 437 states have (on average 1.5354691075514875) internal successors, (671), 437 states have internal predecessors, (671), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 14:12:48,792 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 367 [2022-12-13 14:12:48,793 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 14:12:48,793 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 14:12:48,801 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 14:12:48,801 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 14:12:48,802 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2022-12-13 14:12:48,803 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 438 states, 437 states have (on average 1.5354691075514875) internal successors, (671), 437 states have internal predecessors, (671), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 14:12:48,813 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 367 [2022-12-13 14:12:48,813 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 14:12:48,813 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 14:12:48,815 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 14:12:48,816 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 14:12:48,824 INFO L748 eck$LassoCheckResult]: Stem: 140#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 361#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 216#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 356#update_channels_returnLabel#1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 49#L365true assume !(1 == ~m_i~0);~m_st~0 := 2; 332#L365-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 230#L370-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 184#L375-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 339#L380-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 209#L385-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 192#L526true assume !(0 == ~M_E~0); 415#L526-2true assume 0 == ~T1_E~0;~T1_E~0 := 1; 233#L531-1true assume !(0 == ~T2_E~0); 182#L536-1true assume !(0 == ~T3_E~0); 294#L541-1true assume !(0 == ~T4_E~0); 180#L546-1true assume !(0 == ~E_M~0); 245#L551-1true assume !(0 == ~E_1~0); 162#L556-1true assume !(0 == ~E_2~0); 189#L561-1true assume !(0 == ~E_3~0); 169#L566-1true assume 0 == ~E_4~0;~E_4~0 := 1; 371#L571-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 165#L262true assume 1 == ~m_pc~0; 436#L263true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 375#L273true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 122#is_master_triggered_returnLabel#1true activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 372#L649true assume !(0 != activate_threads_~tmp~1#1); 431#L649-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 127#L281true assume !(1 == ~t1_pc~0); 389#L281-2true is_transmit1_triggered_~__retres1~1#1 := 0; 78#L292true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 32#is_transmit1_triggered_returnLabel#1true activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 114#L657true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 358#L657-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 172#L300true assume 1 == ~t2_pc~0; 306#L301true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 272#L311true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 218#is_transmit2_triggered_returnLabel#1true activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 187#L665true assume !(0 != activate_threads_~tmp___1~0#1); 38#L665-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 438#L319true assume !(1 == ~t3_pc~0); 17#L319-2true is_transmit3_triggered_~__retres1~3#1 := 0; 275#L330true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10#is_transmit3_triggered_returnLabel#1true activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 139#L673true assume !(0 != activate_threads_~tmp___2~0#1); 27#L673-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 276#L338true assume 1 == ~t4_pc~0; 111#L339true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 73#L349true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 66#is_transmit4_triggered_returnLabel#1true activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 379#L681true assume !(0 != activate_threads_~tmp___3~0#1); 2#L681-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 369#L584true assume !(1 == ~M_E~0); 112#L584-2true assume !(1 == ~T1_E~0); 87#L589-1true assume !(1 == ~T2_E~0); 260#L594-1true assume !(1 == ~T3_E~0); 142#L599-1true assume !(1 == ~T4_E~0); 16#L604-1true assume !(1 == ~E_M~0); 9#L609-1true assume 1 == ~E_1~0;~E_1~0 := 2; 72#L614-1true assume !(1 == ~E_2~0); 123#L619-1true assume !(1 == ~E_3~0); 185#L624-1true assume !(1 == ~E_4~0); 396#L629-1true assume { :end_inline_reset_delta_events } true; 203#L815-2true [2022-12-13 14:12:48,825 INFO L750 eck$LassoCheckResult]: Loop: 203#L815-2true assume !false; 383#L816true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 365#L501true assume !true; 74#eval_returnLabel#1true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 322#update_channels_returnLabel#2true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 143#L526-3true assume 0 == ~M_E~0;~M_E~0 := 1; 266#L526-5true assume !(0 == ~T1_E~0); 75#L531-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 390#L536-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 13#L541-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 186#L546-3true assume 0 == ~E_M~0;~E_M~0 := 1; 432#L551-3true assume 0 == ~E_1~0;~E_1~0 := 1; 151#L556-3true assume 0 == ~E_2~0;~E_2~0 := 1; 240#L561-3true assume 0 == ~E_3~0;~E_3~0 := 1; 315#L566-3true assume !(0 == ~E_4~0); 80#L571-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 265#L262-18true assume !(1 == ~m_pc~0); 135#L262-20true is_master_triggered_~__retres1~0#1 := 0; 290#L273-6true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 147#is_master_triggered_returnLabel#7true activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 368#L649-18true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 20#L649-20true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 160#L281-18true assume !(1 == ~t1_pc~0); 269#L281-20true is_transmit1_triggered_~__retres1~1#1 := 0; 175#L292-6true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 364#is_transmit1_triggered_returnLabel#7true activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 413#L657-18true assume !(0 != activate_threads_~tmp___0~0#1); 291#L657-20true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 331#L300-18true assume !(1 == ~t2_pc~0); 14#L300-20true is_transmit2_triggered_~__retres1~2#1 := 0; 47#L311-6true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 213#is_transmit2_triggered_returnLabel#7true activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 252#L665-18true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 316#L665-20true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 79#L319-18true assume 1 == ~t3_pc~0; 83#L320-6true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 95#L330-6true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 238#is_transmit3_triggered_returnLabel#7true activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 215#L673-18true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 200#L673-20true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 126#L338-18true assume 1 == ~t4_pc~0; 280#L339-6true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 105#L349-6true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 170#is_transmit4_triggered_returnLabel#7true activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 29#L681-18true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 176#L681-20true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 138#L584-3true assume 1 == ~M_E~0;~M_E~0 := 2; 288#L584-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 28#L589-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 133#L594-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 212#L599-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 153#L604-3true assume 1 == ~E_M~0;~E_M~0 := 2; 401#L609-3true assume !(1 == ~E_1~0); 199#L614-3true assume 1 == ~E_2~0;~E_2~0 := 2; 24#L619-3true assume 1 == ~E_3~0;~E_3~0 := 2; 210#L624-3true assume 1 == ~E_4~0;~E_4~0 := 2; 246#L629-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 254#L398-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 68#L425-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 195#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 100#L834true assume !(0 == start_simulation_~tmp~3#1); 219#L834-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 352#L398-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 214#L425-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 31#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 293#L789true assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 303#L796true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 334#stop_simulation_returnLabel#1true start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 201#L847true assume !(0 != start_simulation_~tmp___0~1#1); 203#L815-2true [2022-12-13 14:12:48,831 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 14:12:48,831 INFO L85 PathProgramCache]: Analyzing trace with hash 1553035642, now seen corresponding path program 1 times [2022-12-13 14:12:48,838 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 14:12:48,838 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [797520581] [2022-12-13 14:12:48,838 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 14:12:48,839 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 14:12:48,925 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 14:12:49,033 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 14:12:49,033 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 14:12:49,033 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [797520581] [2022-12-13 14:12:49,034 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [797520581] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 14:12:49,034 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 14:12:49,034 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 14:12:49,036 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1623879805] [2022-12-13 14:12:49,037 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 14:12:49,041 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 14:12:49,041 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 14:12:49,042 INFO L85 PathProgramCache]: Analyzing trace with hash -549880100, now seen corresponding path program 1 times [2022-12-13 14:12:49,042 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 14:12:49,042 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1820573398] [2022-12-13 14:12:49,042 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 14:12:49,042 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 14:12:49,052 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 14:12:49,076 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 14:12:49,077 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 14:12:49,077 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1820573398] [2022-12-13 14:12:49,077 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1820573398] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 14:12:49,077 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 14:12:49,077 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-12-13 14:12:49,078 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1136511110] [2022-12-13 14:12:49,078 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 14:12:49,079 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 14:12:49,080 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 14:12:49,111 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 14:12:49,111 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 14:12:49,114 INFO L87 Difference]: Start difference. First operand has 438 states, 437 states have (on average 1.5354691075514875) internal successors, (671), 437 states have internal predecessors, (671), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 14:12:49,156 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 14:12:49,156 INFO L93 Difference]: Finished difference Result 436 states and 652 transitions. [2022-12-13 14:12:49,157 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 436 states and 652 transitions. [2022-12-13 14:12:49,162 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 363 [2022-12-13 14:12:49,168 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 436 states to 430 states and 646 transitions. [2022-12-13 14:12:49,169 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 430 [2022-12-13 14:12:49,170 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 430 [2022-12-13 14:12:49,171 INFO L73 IsDeterministic]: Start isDeterministic. Operand 430 states and 646 transitions. [2022-12-13 14:12:49,173 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 14:12:49,173 INFO L218 hiAutomatonCegarLoop]: Abstraction has 430 states and 646 transitions. [2022-12-13 14:12:49,186 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 430 states and 646 transitions. [2022-12-13 14:12:49,203 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 430 to 430. [2022-12-13 14:12:49,204 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 430 states, 430 states have (on average 1.5023255813953489) internal successors, (646), 429 states have internal predecessors, (646), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 14:12:49,205 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 430 states to 430 states and 646 transitions. [2022-12-13 14:12:49,206 INFO L240 hiAutomatonCegarLoop]: Abstraction has 430 states and 646 transitions. [2022-12-13 14:12:49,207 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 14:12:49,210 INFO L428 stractBuchiCegarLoop]: Abstraction has 430 states and 646 transitions. [2022-12-13 14:12:49,210 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2022-12-13 14:12:49,210 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 430 states and 646 transitions. [2022-12-13 14:12:49,212 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 363 [2022-12-13 14:12:49,212 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 14:12:49,213 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 14:12:49,214 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 14:12:49,215 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 14:12:49,215 INFO L748 eck$LassoCheckResult]: Stem: 1126#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 1127#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 1218#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1219#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 980#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 981#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1229#L370-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 1189#L375-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1190#L380-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1213#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1199#L526 assume !(0 == ~M_E~0); 1200#L526-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1231#L531-1 assume !(0 == ~T2_E~0); 1185#L536-1 assume !(0 == ~T3_E~0); 1186#L541-1 assume !(0 == ~T4_E~0); 1181#L546-1 assume !(0 == ~E_M~0); 1182#L551-1 assume !(0 == ~E_1~0); 1157#L556-1 assume !(0 == ~E_2~0); 1158#L561-1 assume !(0 == ~E_3~0); 1168#L566-1 assume 0 == ~E_4~0;~E_4~0 := 1; 1169#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1162#L262 assume 1 == ~m_pc~0; 1163#L263 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1307#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1096#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1097#L649 assume !(0 != activate_threads_~tmp~1#1); 1306#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1106#L281 assume !(1 == ~t1_pc~0); 1107#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1030#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 947#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 948#L657 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1086#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1171#L300 assume 1 == ~t2_pc~0; 1172#L301 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1261#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1221#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1193#L665 assume !(0 != activate_threads_~tmp___1~0#1); 960#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 961#L319 assume !(1 == ~t3_pc~0); 916#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 917#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 903#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 904#L673 assume !(0 != activate_threads_~tmp___2~0#1); 937#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 938#L338 assume 1 == ~t4_pc~0; 1082#L339 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1006#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1011#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1012#L681 assume !(0 != activate_threads_~tmp___3~0#1); 883#L681-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 884#L584 assume !(1 == ~M_E~0); 1083#L584-2 assume !(1 == ~T1_E~0); 1044#L589-1 assume !(1 == ~T2_E~0); 1045#L594-1 assume !(1 == ~T3_E~0); 1130#L599-1 assume !(1 == ~T4_E~0); 915#L604-1 assume !(1 == ~E_M~0); 901#L609-1 assume 1 == ~E_1~0;~E_1~0 := 2; 902#L614-1 assume !(1 == ~E_2~0); 1020#L619-1 assume !(1 == ~E_3~0); 1098#L624-1 assume !(1 == ~E_4~0); 1191#L629-1 assume { :end_inline_reset_delta_events } true; 1209#L815-2 [2022-12-13 14:12:49,215 INFO L750 eck$LassoCheckResult]: Loop: 1209#L815-2 assume !false; 1210#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1296#L501 assume !false; 1303#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 1304#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 1026#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 1236#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1237#L440 assume !(0 != eval_~tmp~0#1); 1021#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1022#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1131#L526-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1132#L526-5 assume !(0 == ~T1_E~0); 1023#L531-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1024#L536-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 909#L541-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 910#L546-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1192#L551-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1143#L556-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1144#L561-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1240#L566-3 assume !(0 == ~E_4~0); 1034#L571-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1035#L262-18 assume 1 == ~m_pc~0; 1255#L263-6 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1120#L273-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1137#is_master_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1138#L649-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 922#L649-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 923#L281-18 assume !(1 == ~t1_pc~0); 1154#L281-20 is_transmit1_triggered_~__retres1~1#1 := 0; 1174#L292-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1175#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1305#L657-18 assume !(0 != activate_threads_~tmp___0~0#1); 1277#L657-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1278#L300-18 assume 1 == ~t2_pc~0; 1152#L301-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 912#L311-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 979#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1216#L665-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1246#L665-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1031#L319-18 assume !(1 == ~t3_pc~0); 1032#L319-20 is_transmit3_triggered_~__retres1~3#1 := 0; 1037#L330-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1058#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1217#L673-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1207#L673-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1103#L338-18 assume 1 == ~t4_pc~0; 1104#L339-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1075#L349-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1076#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 941#L681-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 942#L681-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1124#L584-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1125#L584-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 939#L589-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 940#L594-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1117#L599-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1146#L604-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1147#L609-3 assume !(1 == ~E_1~0); 1206#L614-3 assume 1 == ~E_2~0;~E_2~0 := 2; 931#L619-3 assume 1 == ~E_3~0;~E_3~0 := 2; 932#L624-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1214#L629-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 1244#L398-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 1014#L425-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 1015#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 1065#L834 assume !(0 == start_simulation_~tmp~3#1); 1066#L834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 1222#L398-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 1184#L425-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 945#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 946#L789 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 1279#L796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1283#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 1208#L847 assume !(0 != start_simulation_~tmp___0~1#1); 1209#L815-2 [2022-12-13 14:12:49,216 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 14:12:49,216 INFO L85 PathProgramCache]: Analyzing trace with hash 1119306556, now seen corresponding path program 1 times [2022-12-13 14:12:49,216 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 14:12:49,217 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1698329901] [2022-12-13 14:12:49,217 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 14:12:49,217 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 14:12:49,230 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 14:12:49,272 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 14:12:49,272 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 14:12:49,273 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1698329901] [2022-12-13 14:12:49,273 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1698329901] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 14:12:49,273 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 14:12:49,273 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 14:12:49,273 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1113062495] [2022-12-13 14:12:49,274 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 14:12:49,274 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 14:12:49,274 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 14:12:49,275 INFO L85 PathProgramCache]: Analyzing trace with hash 815600463, now seen corresponding path program 1 times [2022-12-13 14:12:49,275 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 14:12:49,275 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1744778642] [2022-12-13 14:12:49,275 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 14:12:49,275 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 14:12:49,295 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 14:12:49,342 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 14:12:49,342 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 14:12:49,342 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1744778642] [2022-12-13 14:12:49,342 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1744778642] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 14:12:49,343 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 14:12:49,343 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 14:12:49,343 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2072871368] [2022-12-13 14:12:49,343 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 14:12:49,343 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 14:12:49,343 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 14:12:49,344 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 14:12:49,344 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 14:12:49,344 INFO L87 Difference]: Start difference. First operand 430 states and 646 transitions. cyclomatic complexity: 217 Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 14:12:49,360 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 14:12:49,360 INFO L93 Difference]: Finished difference Result 430 states and 645 transitions. [2022-12-13 14:12:49,360 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 430 states and 645 transitions. [2022-12-13 14:12:49,363 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 363 [2022-12-13 14:12:49,366 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 430 states to 430 states and 645 transitions. [2022-12-13 14:12:49,367 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 430 [2022-12-13 14:12:49,367 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 430 [2022-12-13 14:12:49,368 INFO L73 IsDeterministic]: Start isDeterministic. Operand 430 states and 645 transitions. [2022-12-13 14:12:49,369 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 14:12:49,369 INFO L218 hiAutomatonCegarLoop]: Abstraction has 430 states and 645 transitions. [2022-12-13 14:12:49,370 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 430 states and 645 transitions. [2022-12-13 14:12:49,380 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 430 to 430. [2022-12-13 14:12:49,381 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 430 states, 430 states have (on average 1.5) internal successors, (645), 429 states have internal predecessors, (645), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 14:12:49,382 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 430 states to 430 states and 645 transitions. [2022-12-13 14:12:49,382 INFO L240 hiAutomatonCegarLoop]: Abstraction has 430 states and 645 transitions. [2022-12-13 14:12:49,383 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 14:12:49,383 INFO L428 stractBuchiCegarLoop]: Abstraction has 430 states and 645 transitions. [2022-12-13 14:12:49,384 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2022-12-13 14:12:49,384 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 430 states and 645 transitions. [2022-12-13 14:12:49,387 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 363 [2022-12-13 14:12:49,387 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 14:12:49,387 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 14:12:49,388 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 14:12:49,388 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 14:12:49,389 INFO L748 eck$LassoCheckResult]: Stem: 1993#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 1994#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 2085#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2086#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1847#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 1848#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2096#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2056#L375-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 2057#L380-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2080#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2066#L526 assume !(0 == ~M_E~0); 2067#L526-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2098#L531-1 assume !(0 == ~T2_E~0); 2052#L536-1 assume !(0 == ~T3_E~0); 2053#L541-1 assume !(0 == ~T4_E~0); 2048#L546-1 assume !(0 == ~E_M~0); 2049#L551-1 assume !(0 == ~E_1~0); 2024#L556-1 assume !(0 == ~E_2~0); 2025#L561-1 assume !(0 == ~E_3~0); 2035#L566-1 assume 0 == ~E_4~0;~E_4~0 := 1; 2036#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2029#L262 assume 1 == ~m_pc~0; 2030#L263 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 2174#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1963#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1964#L649 assume !(0 != activate_threads_~tmp~1#1); 2173#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1973#L281 assume !(1 == ~t1_pc~0); 1974#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1897#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1814#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1815#L657 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1953#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2038#L300 assume 1 == ~t2_pc~0; 2039#L301 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2128#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2088#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2060#L665 assume !(0 != activate_threads_~tmp___1~0#1); 1827#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1828#L319 assume !(1 == ~t3_pc~0); 1783#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1784#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1770#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1771#L673 assume !(0 != activate_threads_~tmp___2~0#1); 1804#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1805#L338 assume 1 == ~t4_pc~0; 1949#L339 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1873#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1878#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1879#L681 assume !(0 != activate_threads_~tmp___3~0#1); 1750#L681-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1751#L584 assume !(1 == ~M_E~0); 1950#L584-2 assume !(1 == ~T1_E~0); 1911#L589-1 assume !(1 == ~T2_E~0); 1912#L594-1 assume !(1 == ~T3_E~0); 1997#L599-1 assume !(1 == ~T4_E~0); 1782#L604-1 assume !(1 == ~E_M~0); 1768#L609-1 assume 1 == ~E_1~0;~E_1~0 := 2; 1769#L614-1 assume !(1 == ~E_2~0); 1887#L619-1 assume !(1 == ~E_3~0); 1965#L624-1 assume !(1 == ~E_4~0); 2058#L629-1 assume { :end_inline_reset_delta_events } true; 2076#L815-2 [2022-12-13 14:12:49,389 INFO L750 eck$LassoCheckResult]: Loop: 2076#L815-2 assume !false; 2077#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2163#L501 assume !false; 2170#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 2171#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 1893#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 2103#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 2104#L440 assume !(0 != eval_~tmp~0#1); 1888#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1889#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1998#L526-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1999#L526-5 assume !(0 == ~T1_E~0); 1890#L531-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1891#L536-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1776#L541-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1777#L546-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2059#L551-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2010#L556-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2011#L561-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2107#L566-3 assume !(0 == ~E_4~0); 1901#L571-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1902#L262-18 assume !(1 == ~m_pc~0); 1986#L262-20 is_master_triggered_~__retres1~0#1 := 0; 1987#L273-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2004#is_master_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 2005#L649-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1789#L649-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1790#L281-18 assume !(1 == ~t1_pc~0); 2021#L281-20 is_transmit1_triggered_~__retres1~1#1 := 0; 2041#L292-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2042#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2172#L657-18 assume !(0 != activate_threads_~tmp___0~0#1); 2144#L657-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2145#L300-18 assume !(1 == ~t2_pc~0); 1778#L300-20 is_transmit2_triggered_~__retres1~2#1 := 0; 1779#L311-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1846#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2083#L665-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2113#L665-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1898#L319-18 assume !(1 == ~t3_pc~0); 1899#L319-20 is_transmit3_triggered_~__retres1~3#1 := 0; 1904#L330-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1925#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2084#L673-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2074#L673-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1970#L338-18 assume 1 == ~t4_pc~0; 1971#L339-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1942#L349-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1943#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1808#L681-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1809#L681-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1991#L584-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1992#L584-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1806#L589-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1807#L594-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1984#L599-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2013#L604-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2014#L609-3 assume !(1 == ~E_1~0); 2073#L614-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1798#L619-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1799#L624-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2081#L629-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 2111#L398-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 1881#L425-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 1882#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 1932#L834 assume !(0 == start_simulation_~tmp~3#1); 1933#L834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 2089#L398-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 2051#L425-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 1812#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 1813#L789 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 2146#L796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2150#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 2075#L847 assume !(0 != start_simulation_~tmp___0~1#1); 2076#L815-2 [2022-12-13 14:12:49,390 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 14:12:49,390 INFO L85 PathProgramCache]: Analyzing trace with hash 1078631806, now seen corresponding path program 1 times [2022-12-13 14:12:49,390 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 14:12:49,390 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1655867537] [2022-12-13 14:12:49,390 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 14:12:49,391 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 14:12:49,401 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 14:12:49,427 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 14:12:49,427 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 14:12:49,428 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1655867537] [2022-12-13 14:12:49,428 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1655867537] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 14:12:49,428 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 14:12:49,428 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 14:12:49,428 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1392020249] [2022-12-13 14:12:49,428 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 14:12:49,429 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 14:12:49,429 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 14:12:49,429 INFO L85 PathProgramCache]: Analyzing trace with hash 56647249, now seen corresponding path program 1 times [2022-12-13 14:12:49,429 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 14:12:49,430 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1431076956] [2022-12-13 14:12:49,430 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 14:12:49,430 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 14:12:49,446 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 14:12:49,479 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 14:12:49,479 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 14:12:49,479 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1431076956] [2022-12-13 14:12:49,479 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1431076956] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 14:12:49,480 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 14:12:49,480 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 14:12:49,480 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1525091157] [2022-12-13 14:12:49,480 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 14:12:49,480 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 14:12:49,481 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 14:12:49,481 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 14:12:49,481 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 14:12:49,481 INFO L87 Difference]: Start difference. First operand 430 states and 645 transitions. cyclomatic complexity: 216 Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 14:12:49,494 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 14:12:49,494 INFO L93 Difference]: Finished difference Result 430 states and 644 transitions. [2022-12-13 14:12:49,494 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 430 states and 644 transitions. [2022-12-13 14:12:49,497 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 363 [2022-12-13 14:12:49,499 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 430 states to 430 states and 644 transitions. [2022-12-13 14:12:49,500 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 430 [2022-12-13 14:12:49,500 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 430 [2022-12-13 14:12:49,500 INFO L73 IsDeterministic]: Start isDeterministic. Operand 430 states and 644 transitions. [2022-12-13 14:12:49,501 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 14:12:49,501 INFO L218 hiAutomatonCegarLoop]: Abstraction has 430 states and 644 transitions. [2022-12-13 14:12:49,502 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 430 states and 644 transitions. [2022-12-13 14:12:49,508 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 430 to 430. [2022-12-13 14:12:49,509 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 430 states, 430 states have (on average 1.4976744186046511) internal successors, (644), 429 states have internal predecessors, (644), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 14:12:49,511 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 430 states to 430 states and 644 transitions. [2022-12-13 14:12:49,511 INFO L240 hiAutomatonCegarLoop]: Abstraction has 430 states and 644 transitions. [2022-12-13 14:12:49,511 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 14:12:49,512 INFO L428 stractBuchiCegarLoop]: Abstraction has 430 states and 644 transitions. [2022-12-13 14:12:49,512 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2022-12-13 14:12:49,512 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 430 states and 644 transitions. [2022-12-13 14:12:49,514 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 363 [2022-12-13 14:12:49,514 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 14:12:49,514 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 14:12:49,516 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 14:12:49,516 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 14:12:49,516 INFO L748 eck$LassoCheckResult]: Stem: 2860#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 2861#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 2952#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2953#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2714#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 2715#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2963#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2923#L375-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2924#L380-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2947#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2933#L526 assume !(0 == ~M_E~0); 2934#L526-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2965#L531-1 assume !(0 == ~T2_E~0); 2919#L536-1 assume !(0 == ~T3_E~0); 2920#L541-1 assume !(0 == ~T4_E~0); 2915#L546-1 assume !(0 == ~E_M~0); 2916#L551-1 assume !(0 == ~E_1~0); 2891#L556-1 assume !(0 == ~E_2~0); 2892#L561-1 assume !(0 == ~E_3~0); 2902#L566-1 assume 0 == ~E_4~0;~E_4~0 := 1; 2903#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2896#L262 assume 1 == ~m_pc~0; 2897#L263 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 3041#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2830#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 2831#L649 assume !(0 != activate_threads_~tmp~1#1); 3040#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2840#L281 assume !(1 == ~t1_pc~0); 2841#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2764#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2681#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2682#L657 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2820#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2905#L300 assume 1 == ~t2_pc~0; 2906#L301 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2995#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2955#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2927#L665 assume !(0 != activate_threads_~tmp___1~0#1); 2694#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2695#L319 assume !(1 == ~t3_pc~0); 2650#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 2651#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2637#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2638#L673 assume !(0 != activate_threads_~tmp___2~0#1); 2671#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2672#L338 assume 1 == ~t4_pc~0; 2816#L339 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2740#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2745#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2746#L681 assume !(0 != activate_threads_~tmp___3~0#1); 2617#L681-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2618#L584 assume !(1 == ~M_E~0); 2817#L584-2 assume !(1 == ~T1_E~0); 2778#L589-1 assume !(1 == ~T2_E~0); 2779#L594-1 assume !(1 == ~T3_E~0); 2864#L599-1 assume !(1 == ~T4_E~0); 2649#L604-1 assume !(1 == ~E_M~0); 2635#L609-1 assume 1 == ~E_1~0;~E_1~0 := 2; 2636#L614-1 assume !(1 == ~E_2~0); 2754#L619-1 assume !(1 == ~E_3~0); 2832#L624-1 assume !(1 == ~E_4~0); 2925#L629-1 assume { :end_inline_reset_delta_events } true; 2943#L815-2 [2022-12-13 14:12:49,516 INFO L750 eck$LassoCheckResult]: Loop: 2943#L815-2 assume !false; 2944#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3030#L501 assume !false; 3037#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 3038#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 2760#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 2970#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 2971#L440 assume !(0 != eval_~tmp~0#1); 2755#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2756#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2865#L526-3 assume 0 == ~M_E~0;~M_E~0 := 1; 2866#L526-5 assume !(0 == ~T1_E~0); 2757#L531-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2758#L536-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2643#L541-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2644#L546-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2926#L551-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2877#L556-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2878#L561-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2974#L566-3 assume !(0 == ~E_4~0); 2768#L571-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2769#L262-18 assume !(1 == ~m_pc~0); 2853#L262-20 is_master_triggered_~__retres1~0#1 := 0; 2854#L273-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2871#is_master_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 2872#L649-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2656#L649-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2657#L281-18 assume !(1 == ~t1_pc~0); 2888#L281-20 is_transmit1_triggered_~__retres1~1#1 := 0; 2908#L292-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2909#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3039#L657-18 assume !(0 != activate_threads_~tmp___0~0#1); 3011#L657-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3012#L300-18 assume !(1 == ~t2_pc~0); 2645#L300-20 is_transmit2_triggered_~__retres1~2#1 := 0; 2646#L311-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2713#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2950#L665-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2980#L665-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2765#L319-18 assume !(1 == ~t3_pc~0); 2766#L319-20 is_transmit3_triggered_~__retres1~3#1 := 0; 2771#L330-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2792#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2951#L673-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2941#L673-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2837#L338-18 assume 1 == ~t4_pc~0; 2838#L339-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2809#L349-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2810#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2675#L681-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 2676#L681-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2858#L584-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2859#L584-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2673#L589-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2674#L594-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2851#L599-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2880#L604-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2881#L609-3 assume !(1 == ~E_1~0); 2940#L614-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2665#L619-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2666#L624-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2948#L629-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 2978#L398-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 2748#L425-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 2749#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 2799#L834 assume !(0 == start_simulation_~tmp~3#1); 2800#L834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 2956#L398-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 2918#L425-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 2679#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 2680#L789 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 3013#L796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3017#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 2942#L847 assume !(0 != start_simulation_~tmp___0~1#1); 2943#L815-2 [2022-12-13 14:12:49,517 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 14:12:49,517 INFO L85 PathProgramCache]: Analyzing trace with hash -308153604, now seen corresponding path program 1 times [2022-12-13 14:12:49,517 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 14:12:49,517 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [545700052] [2022-12-13 14:12:49,517 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 14:12:49,518 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 14:12:49,526 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 14:12:49,549 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 14:12:49,549 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 14:12:49,550 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [545700052] [2022-12-13 14:12:49,550 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [545700052] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 14:12:49,550 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 14:12:49,550 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 14:12:49,550 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [295472756] [2022-12-13 14:12:49,550 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 14:12:49,551 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 14:12:49,551 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 14:12:49,551 INFO L85 PathProgramCache]: Analyzing trace with hash 56647249, now seen corresponding path program 2 times [2022-12-13 14:12:49,551 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 14:12:49,552 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1408008564] [2022-12-13 14:12:49,552 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 14:12:49,552 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 14:12:49,562 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 14:12:49,590 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 14:12:49,591 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 14:12:49,591 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1408008564] [2022-12-13 14:12:49,591 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1408008564] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 14:12:49,591 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 14:12:49,591 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 14:12:49,591 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1346574481] [2022-12-13 14:12:49,592 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 14:12:49,592 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 14:12:49,592 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 14:12:49,592 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 14:12:49,592 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 14:12:49,593 INFO L87 Difference]: Start difference. First operand 430 states and 644 transitions. cyclomatic complexity: 215 Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 14:12:49,605 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 14:12:49,605 INFO L93 Difference]: Finished difference Result 430 states and 643 transitions. [2022-12-13 14:12:49,605 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 430 states and 643 transitions. [2022-12-13 14:12:49,608 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 363 [2022-12-13 14:12:49,610 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 430 states to 430 states and 643 transitions. [2022-12-13 14:12:49,610 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 430 [2022-12-13 14:12:49,610 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 430 [2022-12-13 14:12:49,611 INFO L73 IsDeterministic]: Start isDeterministic. Operand 430 states and 643 transitions. [2022-12-13 14:12:49,611 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 14:12:49,611 INFO L218 hiAutomatonCegarLoop]: Abstraction has 430 states and 643 transitions. [2022-12-13 14:12:49,612 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 430 states and 643 transitions. [2022-12-13 14:12:49,617 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 430 to 430. [2022-12-13 14:12:49,617 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 430 states, 430 states have (on average 1.4953488372093022) internal successors, (643), 429 states have internal predecessors, (643), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 14:12:49,619 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 430 states to 430 states and 643 transitions. [2022-12-13 14:12:49,619 INFO L240 hiAutomatonCegarLoop]: Abstraction has 430 states and 643 transitions. [2022-12-13 14:12:49,619 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 14:12:49,620 INFO L428 stractBuchiCegarLoop]: Abstraction has 430 states and 643 transitions. [2022-12-13 14:12:49,620 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2022-12-13 14:12:49,620 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 430 states and 643 transitions. [2022-12-13 14:12:49,622 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 363 [2022-12-13 14:12:49,622 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 14:12:49,622 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 14:12:49,623 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 14:12:49,624 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 14:12:49,624 INFO L748 eck$LassoCheckResult]: Stem: 3727#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 3728#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 3819#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3820#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3581#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 3582#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3831#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3791#L375-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3792#L380-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 3815#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3801#L526 assume !(0 == ~M_E~0); 3802#L526-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3833#L531-1 assume !(0 == ~T2_E~0); 3786#L536-1 assume !(0 == ~T3_E~0); 3787#L541-1 assume !(0 == ~T4_E~0); 3782#L546-1 assume !(0 == ~E_M~0); 3783#L551-1 assume !(0 == ~E_1~0); 3758#L556-1 assume !(0 == ~E_2~0); 3759#L561-1 assume !(0 == ~E_3~0); 3769#L566-1 assume 0 == ~E_4~0;~E_4~0 := 1; 3770#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3763#L262 assume 1 == ~m_pc~0; 3764#L263 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 3908#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3697#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 3698#L649 assume !(0 != activate_threads_~tmp~1#1); 3907#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3707#L281 assume !(1 == ~t1_pc~0); 3708#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 3631#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3548#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3549#L657 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3687#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3772#L300 assume 1 == ~t2_pc~0; 3773#L301 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3862#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3822#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 3794#L665 assume !(0 != activate_threads_~tmp___1~0#1); 3561#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3562#L319 assume !(1 == ~t3_pc~0); 3517#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 3518#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3504#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3505#L673 assume !(0 != activate_threads_~tmp___2~0#1); 3538#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3539#L338 assume 1 == ~t4_pc~0; 3683#L339 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3607#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3612#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3613#L681 assume !(0 != activate_threads_~tmp___3~0#1); 3484#L681-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3485#L584 assume !(1 == ~M_E~0); 3684#L584-2 assume !(1 == ~T1_E~0); 3645#L589-1 assume !(1 == ~T2_E~0); 3646#L594-1 assume !(1 == ~T3_E~0); 3731#L599-1 assume !(1 == ~T4_E~0); 3516#L604-1 assume !(1 == ~E_M~0); 3502#L609-1 assume 1 == ~E_1~0;~E_1~0 := 2; 3503#L614-1 assume !(1 == ~E_2~0); 3621#L619-1 assume !(1 == ~E_3~0); 3699#L624-1 assume !(1 == ~E_4~0); 3790#L629-1 assume { :end_inline_reset_delta_events } true; 3810#L815-2 [2022-12-13 14:12:49,624 INFO L750 eck$LassoCheckResult]: Loop: 3810#L815-2 assume !false; 3811#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3897#L501 assume !false; 3904#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 3905#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 3627#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 3837#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 3838#L440 assume !(0 != eval_~tmp~0#1); 3622#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3623#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3732#L526-3 assume 0 == ~M_E~0;~M_E~0 := 1; 3733#L526-5 assume !(0 == ~T1_E~0); 3624#L531-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3625#L536-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3510#L541-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3511#L546-3 assume 0 == ~E_M~0;~E_M~0 := 1; 3793#L551-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3744#L556-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3745#L561-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3841#L566-3 assume !(0 == ~E_4~0); 3635#L571-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3636#L262-18 assume 1 == ~m_pc~0; 3856#L263-6 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 3721#L273-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3738#is_master_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 3739#L649-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3523#L649-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3524#L281-18 assume !(1 == ~t1_pc~0); 3755#L281-20 is_transmit1_triggered_~__retres1~1#1 := 0; 3775#L292-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3776#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3906#L657-18 assume !(0 != activate_threads_~tmp___0~0#1); 3878#L657-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3879#L300-18 assume !(1 == ~t2_pc~0); 3512#L300-20 is_transmit2_triggered_~__retres1~2#1 := 0; 3513#L311-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3580#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 3817#L665-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3847#L665-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3632#L319-18 assume !(1 == ~t3_pc~0); 3633#L319-20 is_transmit3_triggered_~__retres1~3#1 := 0; 3638#L330-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3659#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3818#L673-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3808#L673-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3704#L338-18 assume 1 == ~t4_pc~0; 3705#L339-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3676#L349-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3677#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3542#L681-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 3543#L681-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3725#L584-3 assume 1 == ~M_E~0;~M_E~0 := 2; 3726#L584-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3540#L589-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3541#L594-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3718#L599-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3747#L604-3 assume 1 == ~E_M~0;~E_M~0 := 2; 3748#L609-3 assume !(1 == ~E_1~0); 3807#L614-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3532#L619-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3533#L624-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3814#L629-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 3845#L398-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 3615#L425-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 3616#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 3666#L834 assume !(0 == start_simulation_~tmp~3#1); 3667#L834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 3823#L398-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 3785#L425-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 3546#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 3547#L789 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 3880#L796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3884#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 3809#L847 assume !(0 != start_simulation_~tmp___0~1#1); 3810#L815-2 [2022-12-13 14:12:49,625 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 14:12:49,625 INFO L85 PathProgramCache]: Analyzing trace with hash -1184172610, now seen corresponding path program 1 times [2022-12-13 14:12:49,625 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 14:12:49,625 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1043863029] [2022-12-13 14:12:49,625 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 14:12:49,625 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 14:12:49,637 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 14:12:49,667 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 14:12:49,668 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 14:12:49,668 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1043863029] [2022-12-13 14:12:49,668 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1043863029] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 14:12:49,668 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 14:12:49,668 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-12-13 14:12:49,668 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [393208714] [2022-12-13 14:12:49,669 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 14:12:49,669 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 14:12:49,669 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 14:12:49,669 INFO L85 PathProgramCache]: Analyzing trace with hash 330425744, now seen corresponding path program 1 times [2022-12-13 14:12:49,669 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 14:12:49,670 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1009207259] [2022-12-13 14:12:49,670 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 14:12:49,670 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 14:12:49,679 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 14:12:49,704 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 14:12:49,704 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 14:12:49,704 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1009207259] [2022-12-13 14:12:49,704 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1009207259] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 14:12:49,705 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 14:12:49,705 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 14:12:49,705 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [639100549] [2022-12-13 14:12:49,705 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 14:12:49,705 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 14:12:49,705 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 14:12:49,706 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 14:12:49,706 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 14:12:49,706 INFO L87 Difference]: Start difference. First operand 430 states and 643 transitions. cyclomatic complexity: 214 Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 2 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 14:12:49,724 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 14:12:49,724 INFO L93 Difference]: Finished difference Result 430 states and 638 transitions. [2022-12-13 14:12:49,724 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 430 states and 638 transitions. [2022-12-13 14:12:49,727 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 363 [2022-12-13 14:12:49,729 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 430 states to 430 states and 638 transitions. [2022-12-13 14:12:49,730 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 430 [2022-12-13 14:12:49,730 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 430 [2022-12-13 14:12:49,730 INFO L73 IsDeterministic]: Start isDeterministic. Operand 430 states and 638 transitions. [2022-12-13 14:12:49,731 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 14:12:49,731 INFO L218 hiAutomatonCegarLoop]: Abstraction has 430 states and 638 transitions. [2022-12-13 14:12:49,732 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 430 states and 638 transitions. [2022-12-13 14:12:49,737 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 430 to 430. [2022-12-13 14:12:49,738 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 430 states, 430 states have (on average 1.4837209302325582) internal successors, (638), 429 states have internal predecessors, (638), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 14:12:49,745 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 430 states to 430 states and 638 transitions. [2022-12-13 14:12:49,746 INFO L240 hiAutomatonCegarLoop]: Abstraction has 430 states and 638 transitions. [2022-12-13 14:12:49,746 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 14:12:49,747 INFO L428 stractBuchiCegarLoop]: Abstraction has 430 states and 638 transitions. [2022-12-13 14:12:49,747 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2022-12-13 14:12:49,747 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 430 states and 638 transitions. [2022-12-13 14:12:49,749 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 363 [2022-12-13 14:12:49,749 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 14:12:49,749 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 14:12:49,750 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 14:12:49,750 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 14:12:49,750 INFO L748 eck$LassoCheckResult]: Stem: 4594#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 4595#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 4686#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4687#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4448#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 4449#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4698#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4657#L375-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 4658#L380-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 4682#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4667#L526 assume !(0 == ~M_E~0); 4668#L526-2 assume !(0 == ~T1_E~0); 4700#L531-1 assume !(0 == ~T2_E~0); 4653#L536-1 assume !(0 == ~T3_E~0); 4654#L541-1 assume !(0 == ~T4_E~0); 4649#L546-1 assume !(0 == ~E_M~0); 4650#L551-1 assume !(0 == ~E_1~0); 4625#L556-1 assume !(0 == ~E_2~0); 4626#L561-1 assume !(0 == ~E_3~0); 4636#L566-1 assume 0 == ~E_4~0;~E_4~0 := 1; 4637#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4630#L262 assume 1 == ~m_pc~0; 4631#L263 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 4775#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4564#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 4565#L649 assume !(0 != activate_threads_~tmp~1#1); 4774#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4574#L281 assume !(1 == ~t1_pc~0); 4575#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 4498#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4415#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 4416#L657 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4554#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4639#L300 assume 1 == ~t2_pc~0; 4640#L301 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4729#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4689#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4661#L665 assume !(0 != activate_threads_~tmp___1~0#1); 4428#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4429#L319 assume !(1 == ~t3_pc~0); 4384#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 4385#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4371#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4372#L673 assume !(0 != activate_threads_~tmp___2~0#1); 4405#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4406#L338 assume 1 == ~t4_pc~0; 4550#L339 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 4474#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4480#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4481#L681 assume !(0 != activate_threads_~tmp___3~0#1); 4351#L681-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4352#L584 assume !(1 == ~M_E~0); 4551#L584-2 assume !(1 == ~T1_E~0); 4512#L589-1 assume !(1 == ~T2_E~0); 4513#L594-1 assume !(1 == ~T3_E~0); 4598#L599-1 assume !(1 == ~T4_E~0); 4383#L604-1 assume !(1 == ~E_M~0); 4369#L609-1 assume 1 == ~E_1~0;~E_1~0 := 2; 4370#L614-1 assume !(1 == ~E_2~0); 4488#L619-1 assume !(1 == ~E_3~0); 4566#L624-1 assume !(1 == ~E_4~0); 4659#L629-1 assume { :end_inline_reset_delta_events } true; 4677#L815-2 [2022-12-13 14:12:49,751 INFO L750 eck$LassoCheckResult]: Loop: 4677#L815-2 assume !false; 4678#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4764#L501 assume !false; 4771#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 4772#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 4494#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 4704#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 4705#L440 assume !(0 != eval_~tmp~0#1); 4489#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4490#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4599#L526-3 assume 0 == ~M_E~0;~M_E~0 := 1; 4600#L526-5 assume !(0 == ~T1_E~0); 4491#L531-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4492#L536-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4379#L541-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4380#L546-3 assume 0 == ~E_M~0;~E_M~0 := 1; 4660#L551-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4611#L556-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4612#L561-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4708#L566-3 assume !(0 == ~E_4~0); 4502#L571-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4503#L262-18 assume 1 == ~m_pc~0; 4723#L263-6 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 4587#L273-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4605#is_master_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 4606#L649-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4390#L649-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4391#L281-18 assume !(1 == ~t1_pc~0); 4622#L281-20 is_transmit1_triggered_~__retres1~1#1 := 0; 4642#L292-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4643#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 4773#L657-18 assume !(0 != activate_threads_~tmp___0~0#1); 4745#L657-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4746#L300-18 assume !(1 == ~t2_pc~0); 4377#L300-20 is_transmit2_triggered_~__retres1~2#1 := 0; 4378#L311-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4447#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4684#L665-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4714#L665-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4499#L319-18 assume !(1 == ~t3_pc~0); 4500#L319-20 is_transmit3_triggered_~__retres1~3#1 := 0; 4505#L330-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4526#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4685#L673-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4675#L673-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4571#L338-18 assume 1 == ~t4_pc~0; 4572#L339-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 4543#L349-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4544#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4409#L681-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 4410#L681-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4590#L584-3 assume 1 == ~M_E~0;~M_E~0 := 2; 4591#L584-5 assume !(1 == ~T1_E~0); 4407#L589-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4408#L594-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4585#L599-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4613#L604-3 assume 1 == ~E_M~0;~E_M~0 := 2; 4614#L609-3 assume !(1 == ~E_1~0); 4674#L614-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4399#L619-3 assume 1 == ~E_3~0;~E_3~0 := 2; 4400#L624-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4681#L629-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 4712#L398-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 4482#L425-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 4483#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 4533#L834 assume !(0 == start_simulation_~tmp~3#1); 4534#L834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 4690#L398-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 4652#L425-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 4413#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 4414#L789 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 4747#L796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4751#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 4676#L847 assume !(0 != start_simulation_~tmp___0~1#1); 4677#L815-2 [2022-12-13 14:12:49,751 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 14:12:49,751 INFO L85 PathProgramCache]: Analyzing trace with hash 1082208576, now seen corresponding path program 1 times [2022-12-13 14:12:49,751 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 14:12:49,752 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [726072387] [2022-12-13 14:12:49,752 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 14:12:49,752 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 14:12:49,760 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 14:12:49,806 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 14:12:49,806 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 14:12:49,807 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [726072387] [2022-12-13 14:12:49,807 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [726072387] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 14:12:49,807 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 14:12:49,807 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 14:12:49,807 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1917383490] [2022-12-13 14:12:49,807 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 14:12:49,808 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 14:12:49,808 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 14:12:49,808 INFO L85 PathProgramCache]: Analyzing trace with hash 549280462, now seen corresponding path program 1 times [2022-12-13 14:12:49,808 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 14:12:49,808 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [286343975] [2022-12-13 14:12:49,808 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 14:12:49,809 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 14:12:49,817 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 14:12:49,842 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 14:12:49,842 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 14:12:49,842 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [286343975] [2022-12-13 14:12:49,842 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [286343975] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 14:12:49,842 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 14:12:49,843 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 14:12:49,843 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1224636485] [2022-12-13 14:12:49,843 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 14:12:49,843 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 14:12:49,843 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 14:12:49,843 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 14:12:49,844 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 14:12:49,844 INFO L87 Difference]: Start difference. First operand 430 states and 638 transitions. cyclomatic complexity: 209 Second operand has 4 states, 4 states have (on average 15.5) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 14:12:49,939 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 14:12:49,939 INFO L93 Difference]: Finished difference Result 720 states and 1066 transitions. [2022-12-13 14:12:49,939 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 720 states and 1066 transitions. [2022-12-13 14:12:49,943 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 642 [2022-12-13 14:12:49,947 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 720 states to 720 states and 1066 transitions. [2022-12-13 14:12:49,947 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 720 [2022-12-13 14:12:49,948 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 720 [2022-12-13 14:12:49,948 INFO L73 IsDeterministic]: Start isDeterministic. Operand 720 states and 1066 transitions. [2022-12-13 14:12:49,949 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 14:12:49,949 INFO L218 hiAutomatonCegarLoop]: Abstraction has 720 states and 1066 transitions. [2022-12-13 14:12:49,950 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 720 states and 1066 transitions. [2022-12-13 14:12:49,961 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 720 to 719. [2022-12-13 14:12:49,962 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 719 states, 719 states have (on average 1.4812239221140473) internal successors, (1065), 718 states have internal predecessors, (1065), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 14:12:49,963 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 719 states to 719 states and 1065 transitions. [2022-12-13 14:12:49,963 INFO L240 hiAutomatonCegarLoop]: Abstraction has 719 states and 1065 transitions. [2022-12-13 14:12:49,963 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 14:12:49,964 INFO L428 stractBuchiCegarLoop]: Abstraction has 719 states and 1065 transitions. [2022-12-13 14:12:49,964 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2022-12-13 14:12:49,964 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 719 states and 1065 transitions. [2022-12-13 14:12:49,966 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 642 [2022-12-13 14:12:49,966 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 14:12:49,966 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 14:12:49,966 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 14:12:49,966 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 14:12:49,967 INFO L748 eck$LassoCheckResult]: Stem: 5754#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 5755#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 5847#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5848#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5608#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 5609#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5860#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5817#L375-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 5818#L380-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 5843#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5828#L526 assume !(0 == ~M_E~0); 5829#L526-2 assume !(0 == ~T1_E~0); 5862#L531-1 assume !(0 == ~T2_E~0); 5813#L536-1 assume !(0 == ~T3_E~0); 5814#L541-1 assume !(0 == ~T4_E~0); 5809#L546-1 assume !(0 == ~E_M~0); 5810#L551-1 assume !(0 == ~E_1~0); 5785#L556-1 assume !(0 == ~E_2~0); 5786#L561-1 assume !(0 == ~E_3~0); 5796#L566-1 assume !(0 == ~E_4~0); 5797#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5790#L262 assume 1 == ~m_pc~0; 5791#L263 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 5952#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5724#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 5725#L649 assume !(0 != activate_threads_~tmp~1#1); 5951#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5734#L281 assume !(1 == ~t1_pc~0); 5735#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 5658#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5575#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 5576#L657 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 5714#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5799#L300 assume 1 == ~t2_pc~0; 5800#L301 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5896#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5851#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 5822#L665 assume !(0 != activate_threads_~tmp___1~0#1); 5588#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5589#L319 assume !(1 == ~t3_pc~0); 5544#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 5545#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5531#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 5532#L673 assume !(0 != activate_threads_~tmp___2~0#1); 5565#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5566#L338 assume 1 == ~t4_pc~0; 5710#L339 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5634#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5640#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5641#L681 assume !(0 != activate_threads_~tmp___3~0#1); 5511#L681-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5512#L584 assume 1 == ~M_E~0;~M_E~0 := 2; 5950#L584-2 assume !(1 == ~T1_E~0); 6080#L589-1 assume !(1 == ~T2_E~0); 6079#L594-1 assume !(1 == ~T3_E~0); 6078#L599-1 assume !(1 == ~T4_E~0); 6077#L604-1 assume !(1 == ~E_M~0); 6072#L609-1 assume 1 == ~E_1~0;~E_1~0 := 2; 6070#L614-1 assume !(1 == ~E_2~0); 6068#L619-1 assume !(1 == ~E_3~0); 6066#L624-1 assume !(1 == ~E_4~0); 5819#L629-1 assume { :end_inline_reset_delta_events } true; 6062#L815-2 [2022-12-13 14:12:49,967 INFO L750 eck$LassoCheckResult]: Loop: 6062#L815-2 assume !false; 5953#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5936#L501 assume !false; 5974#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 5973#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 5968#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 5967#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 5965#L440 assume !(0 != eval_~tmp~0#1); 5964#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5963#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5962#L526-3 assume 0 == ~M_E~0;~M_E~0 := 1; 5890#L526-5 assume !(0 == ~T1_E~0); 5651#L531-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 5652#L536-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5539#L541-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5540#L546-3 assume 0 == ~E_M~0;~E_M~0 := 1; 5821#L551-3 assume 0 == ~E_1~0;~E_1~0 := 1; 5771#L556-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5772#L561-3 assume 0 == ~E_3~0;~E_3~0 := 1; 5871#L566-3 assume !(0 == ~E_4~0); 5662#L571-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5663#L262-18 assume 1 == ~m_pc~0; 5889#L263-6 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 5748#L273-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5765#is_master_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 5766#L649-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 5550#L649-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5551#L281-18 assume !(1 == ~t1_pc~0); 5782#L281-20 is_transmit1_triggered_~__retres1~1#1 := 0; 5802#L292-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5803#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 5948#L657-18 assume !(0 != activate_threads_~tmp___0~0#1); 5912#L657-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5913#L300-18 assume !(1 == ~t2_pc~0); 5537#L300-20 is_transmit2_triggered_~__retres1~2#1 := 0; 5538#L311-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5607#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 5845#L665-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 5880#L665-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5659#L319-18 assume !(1 == ~t3_pc~0); 5660#L319-20 is_transmit3_triggered_~__retres1~3#1 := 0; 5665#L330-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5686#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 5846#L673-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 5836#L673-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5731#L338-18 assume 1 == ~t4_pc~0; 5732#L339-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5703#L349-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5704#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5569#L681-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 5570#L681-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5750#L584-3 assume 1 == ~M_E~0;~M_E~0 := 2; 5751#L584-5 assume !(1 == ~T1_E~0); 5567#L589-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5568#L594-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 5745#L599-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5773#L604-3 assume 1 == ~E_M~0;~E_M~0 := 2; 5774#L609-3 assume !(1 == ~E_1~0); 5835#L614-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5559#L619-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5560#L624-3 assume 1 == ~E_4~0;~E_4~0 := 2; 5842#L629-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 5877#L398-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 5642#L425-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 5643#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 5693#L834 assume !(0 == start_simulation_~tmp~3#1); 5694#L834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 5852#L398-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 6071#L425-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 6069#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 6067#L789 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 6065#L796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 6064#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 6063#L847 assume !(0 != start_simulation_~tmp___0~1#1); 6062#L815-2 [2022-12-13 14:12:49,967 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 14:12:49,967 INFO L85 PathProgramCache]: Analyzing trace with hash -516249280, now seen corresponding path program 1 times [2022-12-13 14:12:49,967 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 14:12:49,968 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [607757028] [2022-12-13 14:12:49,968 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 14:12:49,968 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 14:12:49,973 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 14:12:49,996 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 14:12:49,996 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 14:12:49,996 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [607757028] [2022-12-13 14:12:49,997 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [607757028] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 14:12:49,997 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 14:12:49,997 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-12-13 14:12:49,997 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [336320912] [2022-12-13 14:12:49,997 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 14:12:49,997 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 14:12:49,998 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 14:12:49,998 INFO L85 PathProgramCache]: Analyzing trace with hash 549280462, now seen corresponding path program 2 times [2022-12-13 14:12:49,998 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 14:12:49,998 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [32931246] [2022-12-13 14:12:49,998 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 14:12:49,998 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 14:12:50,005 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 14:12:50,020 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 14:12:50,021 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 14:12:50,021 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [32931246] [2022-12-13 14:12:50,021 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [32931246] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 14:12:50,021 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 14:12:50,021 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 14:12:50,021 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1141293064] [2022-12-13 14:12:50,021 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 14:12:50,022 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 14:12:50,022 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 14:12:50,022 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 14:12:50,022 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 14:12:50,023 INFO L87 Difference]: Start difference. First operand 719 states and 1065 transitions. cyclomatic complexity: 348 Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 2 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 14:12:50,073 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 14:12:50,073 INFO L93 Difference]: Finished difference Result 1332 states and 1946 transitions. [2022-12-13 14:12:50,073 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1332 states and 1946 transitions. [2022-12-13 14:12:50,080 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1254 [2022-12-13 14:12:50,086 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1332 states to 1332 states and 1946 transitions. [2022-12-13 14:12:50,086 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1332 [2022-12-13 14:12:50,088 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1332 [2022-12-13 14:12:50,088 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1332 states and 1946 transitions. [2022-12-13 14:12:50,090 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 14:12:50,090 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1332 states and 1946 transitions. [2022-12-13 14:12:50,091 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1332 states and 1946 transitions. [2022-12-13 14:12:50,105 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1332 to 1264. [2022-12-13 14:12:50,107 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1264 states, 1264 states have (on average 1.4651898734177216) internal successors, (1852), 1263 states have internal predecessors, (1852), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 14:12:50,109 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1264 states to 1264 states and 1852 transitions. [2022-12-13 14:12:50,109 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1264 states and 1852 transitions. [2022-12-13 14:12:50,109 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 14:12:50,110 INFO L428 stractBuchiCegarLoop]: Abstraction has 1264 states and 1852 transitions. [2022-12-13 14:12:50,110 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2022-12-13 14:12:50,110 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1264 states and 1852 transitions. [2022-12-13 14:12:50,113 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1186 [2022-12-13 14:12:50,113 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 14:12:50,113 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 14:12:50,114 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 14:12:50,114 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 14:12:50,114 INFO L748 eck$LassoCheckResult]: Stem: 7823#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 7824#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 7923#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 7924#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7669#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 7670#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7940#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 7889#L375-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 7890#L380-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 7917#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7900#L526 assume !(0 == ~M_E~0); 7901#L526-2 assume !(0 == ~T1_E~0); 7942#L531-1 assume !(0 == ~T2_E~0); 7885#L536-1 assume !(0 == ~T3_E~0); 7886#L541-1 assume !(0 == ~T4_E~0); 7881#L546-1 assume !(0 == ~E_M~0); 7882#L551-1 assume !(0 == ~E_1~0); 7857#L556-1 assume !(0 == ~E_2~0); 7858#L561-1 assume !(0 == ~E_3~0); 7867#L566-1 assume !(0 == ~E_4~0); 7868#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7862#L262 assume !(1 == ~m_pc~0); 7863#L262-2 is_master_triggered_~__retres1~0#1 := 0; 8064#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7794#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 7795#L649 assume !(0 != activate_threads_~tmp~1#1); 8060#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7804#L281 assume !(1 == ~t1_pc~0); 7805#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 7721#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7634#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 7635#L657 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 7782#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7870#L300 assume 1 == ~t2_pc~0; 7871#L301 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 7983#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7927#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 7893#L665 assume !(0 != activate_threads_~tmp___1~0#1); 7647#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7648#L319 assume !(1 == ~t3_pc~0); 7602#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 7603#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7589#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 7590#L673 assume !(0 != activate_threads_~tmp___2~0#1); 7624#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7625#L338 assume 1 == ~t4_pc~0; 7778#L339 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 7695#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7701#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 7702#L681 assume !(0 != activate_threads_~tmp___3~0#1); 7569#L681-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7570#L584 assume 1 == ~M_E~0;~M_E~0 := 2; 8059#L584-2 assume !(1 == ~T1_E~0); 8703#L589-1 assume !(1 == ~T2_E~0); 8701#L594-1 assume !(1 == ~T3_E~0); 8699#L599-1 assume !(1 == ~T4_E~0); 8697#L604-1 assume !(1 == ~E_M~0); 8695#L609-1 assume 1 == ~E_1~0;~E_1~0 := 2; 7710#L614-1 assume !(1 == ~E_2~0); 7711#L619-1 assume !(1 == ~E_3~0); 7796#L624-1 assume !(1 == ~E_4~0); 7891#L629-1 assume { :end_inline_reset_delta_events } true; 7912#L815-2 [2022-12-13 14:12:50,114 INFO L750 eck$LassoCheckResult]: Loop: 7912#L815-2 assume !false; 7913#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 8611#L501 assume !false; 8610#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 8609#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 8148#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 8149#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 8134#L440 assume !(0 != eval_~tmp~0#1); 7712#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 7713#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 7828#L526-3 assume 0 == ~M_E~0;~M_E~0 := 1; 7829#L526-5 assume !(0 == ~T1_E~0); 7714#L531-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7715#L536-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 7595#L541-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 7596#L546-3 assume 0 == ~E_M~0;~E_M~0 := 1; 7892#L551-3 assume 0 == ~E_1~0;~E_1~0 := 1; 7843#L556-3 assume 0 == ~E_2~0;~E_2~0 := 1; 7844#L561-3 assume 0 == ~E_3~0;~E_3~0 := 1; 7951#L566-3 assume !(0 == ~E_4~0); 7725#L571-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7726#L262-18 assume !(1 == ~m_pc~0); 7816#L262-20 is_master_triggered_~__retres1~0#1 := 0; 7817#L273-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7837#is_master_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 7838#L649-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 7608#L649-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7609#L281-18 assume !(1 == ~t1_pc~0); 7854#L281-20 is_transmit1_triggered_~__retres1~1#1 := 0; 7873#L292-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7874#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 8053#L657-18 assume !(0 != activate_threads_~tmp___0~0#1); 8006#L657-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8007#L300-18 assume 1 == ~t2_pc~0; 7852#L301-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 7598#L311-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7668#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 7921#L665-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 7960#L665-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7722#L319-18 assume !(1 == ~t3_pc~0); 7723#L319-20 is_transmit3_triggered_~__retres1~3#1 := 0; 7728#L330-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7751#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 7922#L673-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 7910#L673-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7801#L338-18 assume 1 == ~t4_pc~0; 7802#L339-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 7771#L349-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7772#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 7628#L681-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 7629#L681-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7821#L584-3 assume 1 == ~M_E~0;~M_E~0 := 2; 7822#L584-5 assume !(1 == ~T1_E~0); 8226#L589-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 8224#L594-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 8223#L599-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8222#L604-3 assume 1 == ~E_M~0;~E_M~0 := 2; 8221#L609-3 assume !(1 == ~E_1~0); 8215#L614-3 assume 1 == ~E_2~0;~E_2~0 := 2; 8213#L619-3 assume 1 == ~E_3~0;~E_3~0 := 2; 8211#L624-3 assume 1 == ~E_4~0;~E_4~0 := 2; 8209#L629-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 8204#L398-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 7704#L425-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 7705#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 7759#L834 assume !(0 == start_simulation_~tmp~3#1); 7760#L834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 7928#L398-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 7884#L425-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 7632#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 7633#L789 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 8008#L796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 8014#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 7911#L847 assume !(0 != start_simulation_~tmp___0~1#1); 7912#L815-2 [2022-12-13 14:12:50,115 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 14:12:50,115 INFO L85 PathProgramCache]: Analyzing trace with hash -1001423999, now seen corresponding path program 1 times [2022-12-13 14:12:50,115 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 14:12:50,115 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [577731431] [2022-12-13 14:12:50,115 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 14:12:50,115 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 14:12:50,121 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 14:12:50,148 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 14:12:50,148 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 14:12:50,148 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [577731431] [2022-12-13 14:12:50,148 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [577731431] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 14:12:50,148 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 14:12:50,148 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-12-13 14:12:50,149 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [902956907] [2022-12-13 14:12:50,149 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 14:12:50,149 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 14:12:50,149 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 14:12:50,149 INFO L85 PathProgramCache]: Analyzing trace with hash 760676686, now seen corresponding path program 1 times [2022-12-13 14:12:50,150 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 14:12:50,150 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1509109796] [2022-12-13 14:12:50,150 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 14:12:50,150 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 14:12:50,158 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 14:12:50,173 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 14:12:50,173 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 14:12:50,173 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1509109796] [2022-12-13 14:12:50,173 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1509109796] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 14:12:50,174 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 14:12:50,174 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 14:12:50,174 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [511790221] [2022-12-13 14:12:50,174 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 14:12:50,174 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 14:12:50,174 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 14:12:50,175 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-12-13 14:12:50,175 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-12-13 14:12:50,175 INFO L87 Difference]: Start difference. First operand 1264 states and 1852 transitions. cyclomatic complexity: 592 Second operand has 5 states, 5 states have (on average 12.4) internal successors, (62), 5 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 14:12:50,320 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 14:12:50,320 INFO L93 Difference]: Finished difference Result 3385 states and 4947 transitions. [2022-12-13 14:12:50,320 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3385 states and 4947 transitions. [2022-12-13 14:12:50,345 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3214 [2022-12-13 14:12:50,359 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3385 states to 3385 states and 4947 transitions. [2022-12-13 14:12:50,359 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3385 [2022-12-13 14:12:50,362 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3385 [2022-12-13 14:12:50,362 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3385 states and 4947 transitions. [2022-12-13 14:12:50,367 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 14:12:50,367 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3385 states and 4947 transitions. [2022-12-13 14:12:50,370 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3385 states and 4947 transitions. [2022-12-13 14:12:50,398 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3385 to 1333. [2022-12-13 14:12:50,401 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1333 states, 1333 states have (on average 1.4411102775693923) internal successors, (1921), 1332 states have internal predecessors, (1921), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 14:12:50,404 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1333 states to 1333 states and 1921 transitions. [2022-12-13 14:12:50,404 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1333 states and 1921 transitions. [2022-12-13 14:12:50,405 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-12-13 14:12:50,405 INFO L428 stractBuchiCegarLoop]: Abstraction has 1333 states and 1921 transitions. [2022-12-13 14:12:50,406 INFO L335 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2022-12-13 14:12:50,406 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1333 states and 1921 transitions. [2022-12-13 14:12:50,411 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1252 [2022-12-13 14:12:50,412 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 14:12:50,412 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 14:12:50,413 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 14:12:50,413 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 14:12:50,413 INFO L748 eck$LassoCheckResult]: Stem: 12492#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 12493#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 12600#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 12601#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 12329#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 12330#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 12618#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 12562#L375-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 12563#L380-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 12595#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 12572#L526 assume !(0 == ~M_E~0); 12573#L526-2 assume !(0 == ~T1_E~0); 12620#L531-1 assume !(0 == ~T2_E~0); 12558#L536-1 assume !(0 == ~T3_E~0); 12559#L541-1 assume !(0 == ~T4_E~0); 12554#L546-1 assume !(0 == ~E_M~0); 12555#L551-1 assume !(0 == ~E_1~0); 12529#L556-1 assume !(0 == ~E_2~0); 12530#L561-1 assume !(0 == ~E_3~0); 12540#L566-1 assume !(0 == ~E_4~0); 12541#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12534#L262 assume !(1 == ~m_pc~0); 12535#L262-2 is_master_triggered_~__retres1~0#1 := 0; 12746#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12460#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 12461#L649 assume !(0 != activate_threads_~tmp~1#1); 12743#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12471#L281 assume !(1 == ~t1_pc~0); 12472#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 12382#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12383#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 12448#L657 assume !(0 != activate_threads_~tmp___0~0#1); 12449#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12543#L300 assume 1 == ~t2_pc~0; 12544#L301 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 12659#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12604#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 12566#L665 assume !(0 != activate_threads_~tmp___1~0#1); 12309#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12310#L319 assume !(1 == ~t3_pc~0); 12264#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 12265#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12251#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 12252#L673 assume !(0 != activate_threads_~tmp___2~0#1); 12286#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12287#L338 assume 1 == ~t4_pc~0; 12444#L339 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 12355#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12362#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 12363#L681 assume !(0 != activate_threads_~tmp___3~0#1); 12231#L681-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12232#L584 assume 1 == ~M_E~0;~M_E~0 := 2; 12445#L584-2 assume !(1 == ~T1_E~0); 12400#L589-1 assume !(1 == ~T2_E~0); 12401#L594-1 assume !(1 == ~T3_E~0); 12496#L599-1 assume !(1 == ~T4_E~0); 12263#L604-1 assume !(1 == ~E_M~0); 12249#L609-1 assume 1 == ~E_1~0;~E_1~0 := 2; 12250#L614-1 assume !(1 == ~E_2~0); 12372#L619-1 assume !(1 == ~E_3~0); 12462#L624-1 assume !(1 == ~E_4~0); 12564#L629-1 assume { :end_inline_reset_delta_events } true; 12763#L815-2 [2022-12-13 14:12:50,413 INFO L750 eck$LassoCheckResult]: Loop: 12763#L815-2 assume !false; 12889#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 12887#L501 assume !false; 12885#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 12879#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 12873#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 12871#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 12867#L440 assume !(0 != eval_~tmp~0#1); 12865#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 12863#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 12860#L526-3 assume 0 == ~M_E~0;~M_E~0 := 1; 12861#L526-5 assume !(0 == ~T1_E~0); 12851#L531-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 12852#L536-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 12842#L541-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 12843#L546-3 assume 0 == ~E_M~0;~E_M~0 := 1; 12838#L551-3 assume 0 == ~E_1~0;~E_1~0 := 1; 12839#L556-3 assume 0 == ~E_2~0;~E_2~0 := 1; 12828#L561-3 assume 0 == ~E_3~0;~E_3~0 := 1; 12829#L566-3 assume !(0 == ~E_4~0); 12387#L571-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12388#L262-18 assume !(1 == ~m_pc~0); 12650#L262-20 is_master_triggered_~__retres1~0#1 := 0; 13507#L273-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13506#is_master_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 13505#L649-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 13504#L649-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12525#L281-18 assume !(1 == ~t1_pc~0); 12526#L281-20 is_transmit1_triggered_~__retres1~1#1 := 0; 13499#L292-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13497#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 13495#L657-18 assume !(0 != activate_threads_~tmp___0~0#1); 13494#L657-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 13493#L300-18 assume 1 == ~t2_pc~0; 13491#L301-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 13490#L311-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13489#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 13488#L665-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 13487#L665-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 13486#L319-18 assume !(1 == ~t3_pc~0); 13484#L319-20 is_transmit3_triggered_~__retres1~3#1 := 0; 13483#L330-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13482#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 13451#L673-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 13450#L673-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13441#L338-18 assume 1 == ~t4_pc~0; 13428#L339-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 13426#L349-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 13424#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 13421#L681-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 12548#L681-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12490#L584-3 assume 1 == ~M_E~0;~M_E~0 := 2; 12491#L584-5 assume !(1 == ~T1_E~0); 12288#L589-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 12289#L594-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 12482#L599-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 12515#L604-3 assume 1 == ~E_M~0;~E_M~0 := 2; 12516#L609-3 assume !(1 == ~E_1~0); 12583#L614-3 assume 1 == ~E_2~0;~E_2~0 := 2; 12279#L619-3 assume 1 == ~E_3~0;~E_3~0 := 2; 12280#L624-3 assume 1 == ~E_4~0;~E_4~0 := 2; 12596#L629-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 12634#L398-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 12366#L425-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 12367#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 12422#L834 assume !(0 == start_simulation_~tmp~3#1); 12423#L834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 13024#L398-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 13015#L425-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 13009#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 13004#L789 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 12990#L796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 12989#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 12922#L847 assume !(0 != start_simulation_~tmp___0~1#1); 12763#L815-2 [2022-12-13 14:12:50,414 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 14:12:50,414 INFO L85 PathProgramCache]: Analyzing trace with hash -299824125, now seen corresponding path program 1 times [2022-12-13 14:12:50,414 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 14:12:50,414 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1123882483] [2022-12-13 14:12:50,414 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 14:12:50,414 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 14:12:50,422 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 14:12:50,457 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 14:12:50,457 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 14:12:50,457 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1123882483] [2022-12-13 14:12:50,458 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1123882483] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 14:12:50,458 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 14:12:50,458 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 14:12:50,458 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1080549762] [2022-12-13 14:12:50,458 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 14:12:50,458 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 14:12:50,458 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 14:12:50,459 INFO L85 PathProgramCache]: Analyzing trace with hash 760676686, now seen corresponding path program 2 times [2022-12-13 14:12:50,459 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 14:12:50,459 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1685355276] [2022-12-13 14:12:50,459 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 14:12:50,459 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 14:12:50,466 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 14:12:50,491 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 14:12:50,491 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 14:12:50,491 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1685355276] [2022-12-13 14:12:50,492 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1685355276] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 14:12:50,492 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 14:12:50,492 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 14:12:50,492 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [727422208] [2022-12-13 14:12:50,492 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 14:12:50,492 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 14:12:50,492 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 14:12:50,493 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 14:12:50,493 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 14:12:50,493 INFO L87 Difference]: Start difference. First operand 1333 states and 1921 transitions. cyclomatic complexity: 592 Second operand has 4 states, 4 states have (on average 15.5) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 14:12:50,607 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 14:12:50,607 INFO L93 Difference]: Finished difference Result 3046 states and 4336 transitions. [2022-12-13 14:12:50,607 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3046 states and 4336 transitions. [2022-12-13 14:12:50,620 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 2876 [2022-12-13 14:12:50,637 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3046 states to 3046 states and 4336 transitions. [2022-12-13 14:12:50,638 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3046 [2022-12-13 14:12:50,639 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3046 [2022-12-13 14:12:50,639 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3046 states and 4336 transitions. [2022-12-13 14:12:50,642 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 14:12:50,642 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3046 states and 4336 transitions. [2022-12-13 14:12:50,644 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3046 states and 4336 transitions. [2022-12-13 14:12:50,674 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3046 to 2398. [2022-12-13 14:12:50,677 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2398 states, 2398 states have (on average 1.4336947456213511) internal successors, (3438), 2397 states have internal predecessors, (3438), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 14:12:50,681 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2398 states to 2398 states and 3438 transitions. [2022-12-13 14:12:50,682 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2398 states and 3438 transitions. [2022-12-13 14:12:50,682 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 14:12:50,683 INFO L428 stractBuchiCegarLoop]: Abstraction has 2398 states and 3438 transitions. [2022-12-13 14:12:50,683 INFO L335 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2022-12-13 14:12:50,683 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2398 states and 3438 transitions. [2022-12-13 14:12:50,691 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2316 [2022-12-13 14:12:50,691 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 14:12:50,691 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 14:12:50,692 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 14:12:50,692 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 14:12:50,692 INFO L748 eck$LassoCheckResult]: Stem: 16875#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 16876#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 16977#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 16978#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 16715#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 16716#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 16990#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 16941#L375-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 16942#L380-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 16973#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 16953#L526 assume !(0 == ~M_E~0); 16954#L526-2 assume !(0 == ~T1_E~0); 16992#L531-1 assume !(0 == ~T2_E~0); 16937#L536-1 assume !(0 == ~T3_E~0); 16938#L541-1 assume !(0 == ~T4_E~0); 16933#L546-1 assume !(0 == ~E_M~0); 16934#L551-1 assume !(0 == ~E_1~0); 16911#L556-1 assume !(0 == ~E_2~0); 16912#L561-1 assume !(0 == ~E_3~0); 16921#L566-1 assume !(0 == ~E_4~0); 16922#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16916#L262 assume !(1 == ~m_pc~0); 16917#L262-2 is_master_triggered_~__retres1~0#1 := 0; 17102#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16842#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 16843#L649 assume !(0 != activate_threads_~tmp~1#1); 17098#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16854#L281 assume !(1 == ~t1_pc~0); 16855#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 16768#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16683#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 16684#L657 assume !(0 != activate_threads_~tmp___0~0#1); 16827#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 16924#L300 assume !(1 == ~t2_pc~0); 16925#L300-2 is_transmit2_triggered_~__retres1~2#1 := 0; 17028#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 16981#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 16946#L665 assume !(0 != activate_threads_~tmp___1~0#1); 16696#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16697#L319 assume !(1 == ~t3_pc~0); 16652#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 16653#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 16638#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 16639#L673 assume !(0 != activate_threads_~tmp___2~0#1); 16673#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 16674#L338 assume 1 == ~t4_pc~0; 16822#L339 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 16741#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 16747#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 16748#L681 assume !(0 != activate_threads_~tmp___3~0#1); 16620#L681-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16621#L584 assume 1 == ~M_E~0;~M_E~0 := 2; 16823#L584-2 assume !(1 == ~T1_E~0); 16824#L589-1 assume !(1 == ~T2_E~0); 17020#L594-1 assume !(1 == ~T3_E~0); 17021#L599-1 assume !(1 == ~T4_E~0); 16650#L604-1 assume !(1 == ~E_M~0); 16651#L609-1 assume 1 == ~E_1~0;~E_1~0 := 2; 16757#L614-1 assume !(1 == ~E_2~0); 16758#L619-1 assume !(1 == ~E_3~0); 16943#L624-1 assume !(1 == ~E_4~0); 16944#L629-1 assume { :end_inline_reset_delta_events } true; 18783#L815-2 [2022-12-13 14:12:50,693 INFO L750 eck$LassoCheckResult]: Loop: 18783#L815-2 assume !false; 18718#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 18716#L501 assume !false; 17091#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 17092#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 16764#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 16997#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 16998#L440 assume !(0 != eval_~tmp~0#1); 17115#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 19006#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 19004#L526-3 assume 0 == ~M_E~0;~M_E~0 := 1; 19002#L526-5 assume !(0 == ~T1_E~0); 18999#L531-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 18992#L536-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 18991#L541-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 18990#L546-3 assume 0 == ~E_M~0;~E_M~0 := 1; 18989#L551-3 assume 0 == ~E_1~0;~E_1~0 := 1; 18988#L556-3 assume 0 == ~E_2~0;~E_2~0 := 1; 18987#L561-3 assume 0 == ~E_3~0;~E_3~0 := 1; 18986#L566-3 assume !(0 == ~E_4~0); 18985#L571-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 18984#L262-18 assume !(1 == ~m_pc~0); 18983#L262-20 is_master_triggered_~__retres1~0#1 := 0; 18982#L273-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 18981#is_master_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 18980#L649-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 18979#L649-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 18978#L281-18 assume 1 == ~t1_pc~0; 18976#L282-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 18977#L292-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 18971#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 18970#L657-18 assume !(0 != activate_threads_~tmp___0~0#1); 18942#L657-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 18940#L300-18 assume !(1 == ~t2_pc~0); 18292#L300-20 is_transmit2_triggered_~__retres1~2#1 := 0; 18937#L311-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 18935#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 18933#L665-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 18930#L665-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 18928#L319-18 assume !(1 == ~t3_pc~0); 18925#L319-20 is_transmit3_triggered_~__retres1~3#1 := 0; 18923#L330-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 18921#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 18919#L673-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 18916#L673-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 18914#L338-18 assume !(1 == ~t4_pc~0); 18912#L338-20 is_transmit4_triggered_~__retres1~4#1 := 0; 18909#L349-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 18907#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 18906#L681-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 18905#L681-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 18904#L584-3 assume 1 == ~M_E~0;~M_E~0 := 2; 16873#L584-5 assume !(1 == ~T1_E~0); 18903#L589-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 18902#L594-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 18901#L599-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 18900#L604-3 assume 1 == ~E_M~0;~E_M~0 := 2; 18899#L609-3 assume !(1 == ~E_1~0); 18898#L614-3 assume 1 == ~E_2~0;~E_2~0 := 2; 18897#L619-3 assume 1 == ~E_3~0;~E_3~0 := 2; 18896#L624-3 assume 1 == ~E_4~0;~E_4~0 := 2; 16971#L629-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 18894#L398-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 18890#L425-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 18888#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 18887#L834 assume !(0 == start_simulation_~tmp~3#1); 16857#L834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 18884#L398-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 18881#L425-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 18880#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 18879#L789 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 18878#L796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 18877#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 18785#L847 assume !(0 != start_simulation_~tmp___0~1#1); 18783#L815-2 [2022-12-13 14:12:50,693 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 14:12:50,693 INFO L85 PathProgramCache]: Analyzing trace with hash -1271498812, now seen corresponding path program 1 times [2022-12-13 14:12:50,693 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 14:12:50,694 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [371891496] [2022-12-13 14:12:50,694 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 14:12:50,694 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 14:12:50,701 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 14:12:50,723 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 14:12:50,724 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 14:12:50,724 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [371891496] [2022-12-13 14:12:50,724 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [371891496] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 14:12:50,724 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 14:12:50,724 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-12-13 14:12:50,724 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [692362601] [2022-12-13 14:12:50,724 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 14:12:50,725 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 14:12:50,725 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 14:12:50,725 INFO L85 PathProgramCache]: Analyzing trace with hash 1197269455, now seen corresponding path program 1 times [2022-12-13 14:12:50,725 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 14:12:50,725 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [756418769] [2022-12-13 14:12:50,725 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 14:12:50,726 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 14:12:50,733 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 14:12:50,748 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 14:12:50,748 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 14:12:50,749 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [756418769] [2022-12-13 14:12:50,749 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [756418769] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 14:12:50,749 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 14:12:50,749 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 14:12:50,749 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [906459943] [2022-12-13 14:12:50,749 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 14:12:50,749 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 14:12:50,750 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 14:12:50,750 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 14:12:50,750 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 14:12:50,750 INFO L87 Difference]: Start difference. First operand 2398 states and 3438 transitions. cyclomatic complexity: 1044 Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 2 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 14:12:50,808 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 14:12:50,808 INFO L93 Difference]: Finished difference Result 4365 states and 6231 transitions. [2022-12-13 14:12:50,808 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4365 states and 6231 transitions. [2022-12-13 14:12:50,829 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 4264 [2022-12-13 14:12:50,847 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4365 states to 4365 states and 6231 transitions. [2022-12-13 14:12:50,847 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4365 [2022-12-13 14:12:50,850 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4365 [2022-12-13 14:12:50,850 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4365 states and 6231 transitions. [2022-12-13 14:12:50,854 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 14:12:50,854 INFO L218 hiAutomatonCegarLoop]: Abstraction has 4365 states and 6231 transitions. [2022-12-13 14:12:50,857 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4365 states and 6231 transitions. [2022-12-13 14:12:50,898 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4365 to 4349. [2022-12-13 14:12:50,903 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4349 states, 4349 states have (on average 1.4290641526787766) internal successors, (6215), 4348 states have internal predecessors, (6215), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 14:12:50,909 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4349 states to 4349 states and 6215 transitions. [2022-12-13 14:12:50,909 INFO L240 hiAutomatonCegarLoop]: Abstraction has 4349 states and 6215 transitions. [2022-12-13 14:12:50,910 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 14:12:50,910 INFO L428 stractBuchiCegarLoop]: Abstraction has 4349 states and 6215 transitions. [2022-12-13 14:12:50,910 INFO L335 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2022-12-13 14:12:50,911 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4349 states and 6215 transitions. [2022-12-13 14:12:50,926 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 4248 [2022-12-13 14:12:50,926 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 14:12:50,926 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 14:12:50,927 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 14:12:50,927 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 14:12:50,927 INFO L748 eck$LassoCheckResult]: Stem: 23642#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 23643#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 23745#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 23746#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 23488#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 23489#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 23764#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 23712#L375-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 23713#L380-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 23740#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 23723#L526 assume !(0 == ~M_E~0); 23724#L526-2 assume !(0 == ~T1_E~0); 23766#L531-1 assume !(0 == ~T2_E~0); 23708#L536-1 assume !(0 == ~T3_E~0); 23709#L541-1 assume !(0 == ~T4_E~0); 23704#L546-1 assume !(0 == ~E_M~0); 23705#L551-1 assume !(0 == ~E_1~0); 23681#L556-1 assume !(0 == ~E_2~0); 23682#L561-1 assume !(0 == ~E_3~0); 23691#L566-1 assume !(0 == ~E_4~0); 23692#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 23686#L262 assume !(1 == ~m_pc~0); 23687#L262-2 is_master_triggered_~__retres1~0#1 := 0; 23890#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 23612#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 23613#L649 assume !(0 != activate_threads_~tmp~1#1); 23888#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 23621#L281 assume !(1 == ~t1_pc~0); 23622#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 23542#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 23452#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 23453#L657 assume !(0 != activate_threads_~tmp___0~0#1); 23600#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 23694#L300 assume !(1 == ~t2_pc~0); 23695#L300-2 is_transmit2_triggered_~__retres1~2#1 := 0; 23806#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 23749#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 23717#L665 assume !(0 != activate_threads_~tmp___1~0#1); 23465#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 23466#L319 assume !(1 == ~t3_pc~0); 23421#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 23422#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 23408#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 23409#L673 assume !(0 != activate_threads_~tmp___2~0#1); 23442#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 23443#L338 assume !(1 == ~t4_pc~0); 23515#L338-2 is_transmit4_triggered_~__retres1~4#1 := 0; 23516#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 23521#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 23522#L681 assume !(0 != activate_threads_~tmp___3~0#1); 23390#L681-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 23391#L584 assume 1 == ~M_E~0;~M_E~0 := 2; 23887#L584-2 assume !(1 == ~T1_E~0); 26876#L589-1 assume !(1 == ~T2_E~0); 26875#L594-1 assume !(1 == ~T3_E~0); 26874#L599-1 assume !(1 == ~T4_E~0); 26873#L604-1 assume !(1 == ~E_M~0); 26872#L609-1 assume 1 == ~E_1~0;~E_1~0 := 2; 26871#L614-1 assume !(1 == ~E_2~0); 26870#L619-1 assume !(1 == ~E_3~0); 26869#L624-1 assume !(1 == ~E_4~0); 23714#L629-1 assume { :end_inline_reset_delta_events } true; 23906#L815-2 [2022-12-13 14:12:50,928 INFO L750 eck$LassoCheckResult]: Loop: 23906#L815-2 assume !false; 23896#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 23869#L501 assume !false; 23883#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 27052#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 27046#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 27042#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 27039#L440 assume !(0 != eval_~tmp~0#1); 27040#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 27270#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 27268#L526-3 assume 0 == ~M_E~0;~M_E~0 := 1; 27266#L526-5 assume !(0 == ~T1_E~0); 27264#L531-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 27263#L536-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 27262#L541-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 27261#L546-3 assume 0 == ~E_M~0;~E_M~0 := 1; 27259#L551-3 assume 0 == ~E_1~0;~E_1~0 := 1; 27257#L556-3 assume 0 == ~E_2~0;~E_2~0 := 1; 27255#L561-3 assume 0 == ~E_3~0;~E_3~0 := 1; 27253#L566-3 assume !(0 == ~E_4~0); 27251#L571-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 27249#L262-18 assume !(1 == ~m_pc~0); 27247#L262-20 is_master_triggered_~__retres1~0#1 := 0; 27245#L273-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 27244#is_master_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 23886#L649-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 23427#L649-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 23428#L281-18 assume !(1 == ~t1_pc~0); 23678#L281-20 is_transmit1_triggered_~__retres1~1#1 := 0; 23696#L292-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 23697#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 23919#L657-18 assume !(0 != activate_threads_~tmp___0~0#1); 23826#L657-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 23827#L300-18 assume !(1 == ~t2_pc~0); 23416#L300-20 is_transmit2_triggered_~__retres1~2#1 := 0; 23417#L311-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 23487#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 23743#L665-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 23789#L665-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 23543#L319-18 assume !(1 == ~t3_pc~0); 23544#L319-20 is_transmit3_triggered_~__retres1~3#1 := 0; 23549#L330-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 23571#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 23744#L673-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 23733#L673-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 23619#L338-18 assume !(1 == ~t4_pc~0); 23620#L338-20 is_transmit4_triggered_~__retres1~4#1 := 0; 23589#L349-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 23590#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 23446#L681-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 23447#L681-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 23640#L584-3 assume 1 == ~M_E~0;~M_E~0 := 2; 23641#L584-5 assume !(1 == ~T1_E~0); 23444#L589-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 23445#L594-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 23632#L599-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 23667#L604-3 assume 1 == ~E_M~0;~E_M~0 := 2; 23668#L609-3 assume !(1 == ~E_1~0); 23732#L614-3 assume 1 == ~E_2~0;~E_2~0 := 2; 23436#L619-3 assume 1 == ~E_3~0;~E_3~0 := 2; 23437#L624-3 assume 1 == ~E_4~0;~E_4~0 := 2; 23741#L629-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 23784#L398-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 23524#L425-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 23525#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 23579#L834 assume !(0 == start_simulation_~tmp~3#1); 23580#L834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 27176#L398-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 27172#L425-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 27169#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 27167#L789 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 27165#L796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 27163#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 27161#L847 assume !(0 != start_simulation_~tmp___0~1#1); 23906#L815-2 [2022-12-13 14:12:50,928 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 14:12:50,928 INFO L85 PathProgramCache]: Analyzing trace with hash 843496709, now seen corresponding path program 1 times [2022-12-13 14:12:50,928 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 14:12:50,928 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [656217425] [2022-12-13 14:12:50,928 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 14:12:50,928 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 14:12:50,936 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 14:12:50,962 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 14:12:50,962 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 14:12:50,963 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [656217425] [2022-12-13 14:12:50,963 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [656217425] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 14:12:50,963 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 14:12:50,963 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-12-13 14:12:50,963 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1666522230] [2022-12-13 14:12:50,963 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 14:12:50,963 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 14:12:50,964 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 14:12:50,964 INFO L85 PathProgramCache]: Analyzing trace with hash -696172720, now seen corresponding path program 1 times [2022-12-13 14:12:50,964 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 14:12:50,964 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1922658369] [2022-12-13 14:12:50,964 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 14:12:50,964 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 14:12:50,971 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 14:12:50,991 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 14:12:50,991 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 14:12:50,991 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1922658369] [2022-12-13 14:12:50,991 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1922658369] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 14:12:50,991 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 14:12:50,991 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 14:12:50,991 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [636836540] [2022-12-13 14:12:50,992 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 14:12:50,992 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 14:12:50,992 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 14:12:50,992 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 14:12:50,992 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 14:12:50,992 INFO L87 Difference]: Start difference. First operand 4349 states and 6215 transitions. cyclomatic complexity: 1874 Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 2 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 14:12:51,026 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 14:12:51,026 INFO L93 Difference]: Finished difference Result 6516 states and 9297 transitions. [2022-12-13 14:12:51,026 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6516 states and 9297 transitions. [2022-12-13 14:12:51,045 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 6412 [2022-12-13 14:12:51,064 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6516 states to 6516 states and 9297 transitions. [2022-12-13 14:12:51,082 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6516 [2022-12-13 14:12:51,084 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6516 [2022-12-13 14:12:51,085 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6516 states and 9297 transitions. [2022-12-13 14:12:51,090 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 14:12:51,090 INFO L218 hiAutomatonCegarLoop]: Abstraction has 6516 states and 9297 transitions. [2022-12-13 14:12:51,094 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6516 states and 9297 transitions. [2022-12-13 14:12:51,133 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6516 to 4727. [2022-12-13 14:12:51,139 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4727 states, 4727 states have (on average 1.4250052887666596) internal successors, (6736), 4726 states have internal predecessors, (6736), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 14:12:51,146 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4727 states to 4727 states and 6736 transitions. [2022-12-13 14:12:51,146 INFO L240 hiAutomatonCegarLoop]: Abstraction has 4727 states and 6736 transitions. [2022-12-13 14:12:51,146 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 14:12:51,147 INFO L428 stractBuchiCegarLoop]: Abstraction has 4727 states and 6736 transitions. [2022-12-13 14:12:51,147 INFO L335 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2022-12-13 14:12:51,147 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4727 states and 6736 transitions. [2022-12-13 14:12:51,157 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4636 [2022-12-13 14:12:51,157 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 14:12:51,157 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 14:12:51,158 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 14:12:51,158 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 14:12:51,158 INFO L748 eck$LassoCheckResult]: Stem: 34509#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 34510#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 34612#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 34613#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 34360#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 34361#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 34627#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 34578#L375-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 34579#L380-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 34608#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 34590#L526 assume !(0 == ~M_E~0); 34591#L526-2 assume !(0 == ~T1_E~0); 34629#L531-1 assume !(0 == ~T2_E~0); 34574#L536-1 assume !(0 == ~T3_E~0); 34575#L541-1 assume !(0 == ~T4_E~0); 34570#L546-1 assume !(0 == ~E_M~0); 34571#L551-1 assume !(0 == ~E_1~0); 34546#L556-1 assume !(0 == ~E_2~0); 34547#L561-1 assume !(0 == ~E_3~0); 34556#L566-1 assume !(0 == ~E_4~0); 34557#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 34551#L262 assume !(1 == ~m_pc~0); 34552#L262-2 is_master_triggered_~__retres1~0#1 := 0; 34741#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 34480#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 34481#L649 assume !(0 != activate_threads_~tmp~1#1); 34740#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 34489#L281 assume !(1 == ~t1_pc~0); 34490#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 34412#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 34325#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 34326#L657 assume !(0 != activate_threads_~tmp___0~0#1); 34468#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 34559#L300 assume !(1 == ~t2_pc~0); 34560#L300-2 is_transmit2_triggered_~__retres1~2#1 := 0; 34669#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 34616#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 34582#L665 assume !(0 != activate_threads_~tmp___1~0#1); 34338#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 34339#L319 assume !(1 == ~t3_pc~0); 34293#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 34294#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 34280#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 34281#L673 assume !(0 != activate_threads_~tmp___2~0#1); 34315#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 34316#L338 assume !(1 == ~t4_pc~0); 34385#L338-2 is_transmit4_triggered_~__retres1~4#1 := 0; 34386#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 34392#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 34393#L681 assume !(0 != activate_threads_~tmp___3~0#1); 34262#L681-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 34263#L584 assume !(1 == ~M_E~0); 34465#L584-2 assume !(1 == ~T1_E~0); 34428#L589-1 assume !(1 == ~T2_E~0); 34429#L594-1 assume !(1 == ~T3_E~0); 34515#L599-1 assume !(1 == ~T4_E~0); 34292#L604-1 assume !(1 == ~E_M~0); 34278#L609-1 assume 1 == ~E_1~0;~E_1~0 := 2; 34279#L614-1 assume !(1 == ~E_2~0); 34402#L619-1 assume !(1 == ~E_3~0); 34482#L624-1 assume !(1 == ~E_4~0); 34580#L629-1 assume { :end_inline_reset_delta_events } true; 34752#L815-2 [2022-12-13 14:12:51,159 INFO L750 eck$LassoCheckResult]: Loop: 34752#L815-2 assume !false; 38452#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 38450#L501 assume !false; 38448#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 38336#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 38330#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 38327#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 38323#L440 assume !(0 != eval_~tmp~0#1); 38324#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 38599#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 38597#L526-3 assume !(0 == ~M_E~0); 38596#L526-5 assume !(0 == ~T1_E~0); 38594#L531-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 38592#L536-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 38590#L541-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 38588#L546-3 assume 0 == ~E_M~0;~E_M~0 := 1; 38586#L551-3 assume 0 == ~E_1~0;~E_1~0 := 1; 38584#L556-3 assume 0 == ~E_2~0;~E_2~0 := 1; 38582#L561-3 assume 0 == ~E_3~0;~E_3~0 := 1; 38580#L566-3 assume !(0 == ~E_4~0); 38578#L571-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 38577#L262-18 assume !(1 == ~m_pc~0); 38576#L262-20 is_master_triggered_~__retres1~0#1 := 0; 38570#L273-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 38568#is_master_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 38566#L649-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 38565#L649-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 38564#L281-18 assume 1 == ~t1_pc~0; 38562#L282-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 38560#L292-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 38558#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 38557#L657-18 assume !(0 != activate_threads_~tmp___0~0#1); 38555#L657-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 37239#L300-18 assume !(1 == ~t2_pc~0); 37235#L300-20 is_transmit2_triggered_~__retres1~2#1 := 0; 37229#L311-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 37222#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 37190#L665-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 37150#L665-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 37146#L319-18 assume !(1 == ~t3_pc~0); 36781#L319-20 is_transmit3_triggered_~__retres1~3#1 := 0; 36779#L330-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 36776#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 36774#L673-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 36772#L673-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 36770#L338-18 assume !(1 == ~t4_pc~0); 36768#L338-20 is_transmit4_triggered_~__retres1~4#1 := 0; 36766#L349-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 36763#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 36761#L681-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 36759#L681-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 36756#L584-3 assume !(1 == ~M_E~0); 36583#L584-5 assume !(1 == ~T1_E~0); 36753#L589-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 36752#L594-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 36749#L599-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 36747#L604-3 assume 1 == ~E_M~0;~E_M~0 := 2; 36745#L609-3 assume !(1 == ~E_1~0); 36743#L614-3 assume 1 == ~E_2~0;~E_2~0 := 2; 36741#L619-3 assume 1 == ~E_3~0;~E_3~0 := 2; 36739#L624-3 assume 1 == ~E_4~0;~E_4~0 := 2; 36736#L629-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 36728#L398-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 36723#L425-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 36720#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 34834#L834 assume !(0 == start_simulation_~tmp~3#1); 34492#L834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 34617#L398-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 38477#L425-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 38475#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 38473#L789 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 38470#L796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 38466#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 38461#L847 assume !(0 != start_simulation_~tmp___0~1#1); 34752#L815-2 [2022-12-13 14:12:51,159 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 14:12:51,159 INFO L85 PathProgramCache]: Analyzing trace with hash 1544561287, now seen corresponding path program 1 times [2022-12-13 14:12:51,159 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 14:12:51,159 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1257611847] [2022-12-13 14:12:51,159 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 14:12:51,159 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 14:12:51,167 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 14:12:51,191 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 14:12:51,191 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 14:12:51,192 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1257611847] [2022-12-13 14:12:51,192 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1257611847] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 14:12:51,192 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 14:12:51,192 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 14:12:51,192 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [746094617] [2022-12-13 14:12:51,192 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 14:12:51,192 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 14:12:51,193 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 14:12:51,193 INFO L85 PathProgramCache]: Analyzing trace with hash -662561777, now seen corresponding path program 1 times [2022-12-13 14:12:51,193 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 14:12:51,193 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [763453982] [2022-12-13 14:12:51,193 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 14:12:51,193 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 14:12:51,198 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 14:12:51,222 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 14:12:51,223 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 14:12:51,223 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [763453982] [2022-12-13 14:12:51,223 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [763453982] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 14:12:51,223 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 14:12:51,223 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 14:12:51,223 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [669092205] [2022-12-13 14:12:51,223 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 14:12:51,224 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 14:12:51,224 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 14:12:51,224 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 14:12:51,224 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 14:12:51,224 INFO L87 Difference]: Start difference. First operand 4727 states and 6736 transitions. cyclomatic complexity: 2013 Second operand has 4 states, 4 states have (on average 15.5) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 14:12:51,323 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 14:12:51,324 INFO L93 Difference]: Finished difference Result 6455 states and 9025 transitions. [2022-12-13 14:12:51,324 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6455 states and 9025 transitions. [2022-12-13 14:12:51,343 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 6270 [2022-12-13 14:12:51,360 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6455 states to 6455 states and 9025 transitions. [2022-12-13 14:12:51,360 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6455 [2022-12-13 14:12:51,363 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6455 [2022-12-13 14:12:51,364 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6455 states and 9025 transitions. [2022-12-13 14:12:51,370 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 14:12:51,370 INFO L218 hiAutomatonCegarLoop]: Abstraction has 6455 states and 9025 transitions. [2022-12-13 14:12:51,375 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6455 states and 9025 transitions. [2022-12-13 14:12:51,445 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6455 to 5314. [2022-12-13 14:12:51,452 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5314 states, 5314 states have (on average 1.4060971019947308) internal successors, (7472), 5313 states have internal predecessors, (7472), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 14:12:51,462 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5314 states to 5314 states and 7472 transitions. [2022-12-13 14:12:51,463 INFO L240 hiAutomatonCegarLoop]: Abstraction has 5314 states and 7472 transitions. [2022-12-13 14:12:51,463 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 14:12:51,463 INFO L428 stractBuchiCegarLoop]: Abstraction has 5314 states and 7472 transitions. [2022-12-13 14:12:51,464 INFO L335 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2022-12-13 14:12:51,464 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5314 states and 7472 transitions. [2022-12-13 14:12:51,479 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 5180 [2022-12-13 14:12:51,479 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 14:12:51,479 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 14:12:51,480 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 14:12:51,480 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 14:12:51,481 INFO L748 eck$LassoCheckResult]: Stem: 45701#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 45702#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 45802#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 45803#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 45551#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 45552#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 45815#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 45767#L375-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 45768#L380-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 45797#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 45780#L526 assume !(0 == ~M_E~0); 45781#L526-2 assume !(0 == ~T1_E~0); 45818#L531-1 assume !(0 == ~T2_E~0); 45763#L536-1 assume !(0 == ~T3_E~0); 45764#L541-1 assume !(0 == ~T4_E~0); 45759#L546-1 assume !(0 == ~E_M~0); 45760#L551-1 assume 0 == ~E_1~0;~E_1~0 := 1; 45736#L556-1 assume !(0 == ~E_2~0); 45737#L561-1 assume !(0 == ~E_3~0); 45746#L566-1 assume !(0 == ~E_4~0); 45747#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 45741#L262 assume !(1 == ~m_pc~0); 45742#L262-2 is_master_triggered_~__retres1~0#1 := 0; 45926#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 45672#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 45673#L649 assume !(0 != activate_threads_~tmp~1#1); 45952#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 45681#L281 assume !(1 == ~t1_pc~0); 45682#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 45989#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 45987#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 45983#L657 assume !(0 != activate_threads_~tmp___0~0#1); 45982#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 45981#L300 assume !(1 == ~t2_pc~0); 45980#L300-2 is_transmit2_triggered_~__retres1~2#1 := 0; 45979#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 45978#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 45977#L665 assume !(0 != activate_threads_~tmp___1~0#1); 45976#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 45975#L319 assume !(1 == ~t3_pc~0); 45973#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 45972#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 45971#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 45970#L673 assume !(0 != activate_threads_~tmp___2~0#1); 45969#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 45968#L338 assume !(1 == ~t4_pc~0); 45967#L338-2 is_transmit4_triggered_~__retres1~4#1 := 0; 45966#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 45965#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 45964#L681 assume !(0 != activate_threads_~tmp___3~0#1); 45963#L681-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 45962#L584 assume !(1 == ~M_E~0); 45961#L584-2 assume !(1 == ~T1_E~0); 45960#L589-1 assume !(1 == ~T2_E~0); 45959#L594-1 assume !(1 == ~T3_E~0); 45958#L599-1 assume !(1 == ~T4_E~0); 45957#L604-1 assume !(1 == ~E_M~0); 45956#L609-1 assume 1 == ~E_1~0;~E_1~0 := 2; 45471#L614-1 assume !(1 == ~E_2~0); 45590#L619-1 assume !(1 == ~E_3~0); 45674#L624-1 assume !(1 == ~E_4~0); 45769#L629-1 assume { :end_inline_reset_delta_events } true; 45937#L815-2 [2022-12-13 14:12:51,481 INFO L750 eck$LassoCheckResult]: Loop: 45937#L815-2 assume !false; 49222#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 49221#L501 assume !false; 49220#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 49199#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 49192#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 49190#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 49188#L440 assume !(0 != eval_~tmp~0#1); 45591#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 45592#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 45706#L526-3 assume !(0 == ~M_E~0); 45707#L526-5 assume !(0 == ~T1_E~0); 45593#L531-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 45594#L536-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 45478#L541-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 45479#L546-3 assume 0 == ~E_M~0;~E_M~0 := 1; 45770#L551-3 assume 0 == ~E_1~0;~E_1~0 := 1; 45953#L556-3 assume 0 == ~E_2~0;~E_2~0 := 1; 50691#L561-3 assume 0 == ~E_3~0;~E_3~0 := 1; 50690#L566-3 assume !(0 == ~E_4~0); 50689#L571-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 50688#L262-18 assume !(1 == ~m_pc~0); 50687#L262-20 is_master_triggered_~__retres1~0#1 := 0; 50686#L273-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 50685#is_master_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 50684#L649-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 50683#L649-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 50681#L281-18 assume 1 == ~t1_pc~0; 50679#L282-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 50678#L292-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 50677#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 50676#L657-18 assume !(0 != activate_threads_~tmp___0~0#1); 50674#L657-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 50673#L300-18 assume !(1 == ~t2_pc~0); 49175#L300-20 is_transmit2_triggered_~__retres1~2#1 := 0; 50672#L311-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 50671#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 50670#L665-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 50669#L665-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 50668#L319-18 assume !(1 == ~t3_pc~0); 50666#L319-20 is_transmit3_triggered_~__retres1~3#1 := 0; 50665#L330-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 50664#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 50663#L673-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 50662#L673-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 50661#L338-18 assume !(1 == ~t4_pc~0); 50660#L338-20 is_transmit4_triggered_~__retres1~4#1 := 0; 50659#L349-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 50658#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 50657#L681-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 50656#L681-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 50655#L584-3 assume !(1 == ~M_E~0); 48750#L584-5 assume !(1 == ~T1_E~0); 50654#L589-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 50653#L594-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 50652#L599-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 50651#L604-3 assume 1 == ~E_M~0;~E_M~0 := 2; 50650#L609-3 assume !(1 == ~E_1~0); 45787#L614-3 assume 1 == ~E_2~0;~E_2~0 := 2; 45500#L619-3 assume 1 == ~E_3~0;~E_3~0 := 2; 45501#L624-3 assume 1 == ~E_4~0;~E_4~0 := 2; 45798#L629-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 45832#L398-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 45584#L425-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 45585#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 45636#L834 assume !(0 == start_simulation_~tmp~3#1); 45637#L834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 49268#L398-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 49264#L425-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 49262#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 49260#L789 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 49258#L796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 49256#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 49254#L847 assume !(0 != start_simulation_~tmp___0~1#1); 45937#L815-2 [2022-12-13 14:12:51,481 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 14:12:51,481 INFO L85 PathProgramCache]: Analyzing trace with hash -383711415, now seen corresponding path program 1 times [2022-12-13 14:12:51,482 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 14:12:51,482 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [577545150] [2022-12-13 14:12:51,482 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 14:12:51,482 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 14:12:51,489 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 14:12:51,515 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 14:12:51,515 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 14:12:51,515 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [577545150] [2022-12-13 14:12:51,515 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [577545150] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 14:12:51,515 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 14:12:51,515 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 14:12:51,515 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1704113430] [2022-12-13 14:12:51,516 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 14:12:51,516 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 14:12:51,516 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 14:12:51,516 INFO L85 PathProgramCache]: Analyzing trace with hash -662561777, now seen corresponding path program 2 times [2022-12-13 14:12:51,516 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 14:12:51,516 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1278086765] [2022-12-13 14:12:51,517 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 14:12:51,517 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 14:12:51,521 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 14:12:51,535 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 14:12:51,535 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 14:12:51,535 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1278086765] [2022-12-13 14:12:51,535 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1278086765] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 14:12:51,535 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 14:12:51,535 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 14:12:51,535 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [764695275] [2022-12-13 14:12:51,535 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 14:12:51,536 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 14:12:51,536 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 14:12:51,536 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 14:12:51,536 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 14:12:51,536 INFO L87 Difference]: Start difference. First operand 5314 states and 7472 transitions. cyclomatic complexity: 2162 Second operand has 4 states, 4 states have (on average 15.5) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 14:12:51,608 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 14:12:51,608 INFO L93 Difference]: Finished difference Result 5406 states and 7559 transitions. [2022-12-13 14:12:51,608 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5406 states and 7559 transitions. [2022-12-13 14:12:51,621 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 5302 [2022-12-13 14:12:51,631 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5406 states to 5406 states and 7559 transitions. [2022-12-13 14:12:51,632 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5406 [2022-12-13 14:12:51,634 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5406 [2022-12-13 14:12:51,634 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5406 states and 7559 transitions. [2022-12-13 14:12:51,639 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 14:12:51,639 INFO L218 hiAutomatonCegarLoop]: Abstraction has 5406 states and 7559 transitions. [2022-12-13 14:12:51,643 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5406 states and 7559 transitions. [2022-12-13 14:12:51,677 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5406 to 4508. [2022-12-13 14:12:51,682 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4508 states, 4508 states have (on average 1.4021739130434783) internal successors, (6321), 4507 states have internal predecessors, (6321), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 14:12:51,688 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4508 states to 4508 states and 6321 transitions. [2022-12-13 14:12:51,688 INFO L240 hiAutomatonCegarLoop]: Abstraction has 4508 states and 6321 transitions. [2022-12-13 14:12:51,689 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 14:12:51,689 INFO L428 stractBuchiCegarLoop]: Abstraction has 4508 states and 6321 transitions. [2022-12-13 14:12:51,689 INFO L335 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2022-12-13 14:12:51,689 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4508 states and 6321 transitions. [2022-12-13 14:12:51,709 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4420 [2022-12-13 14:12:51,709 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 14:12:51,709 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 14:12:51,710 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 14:12:51,710 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 14:12:51,711 INFO L748 eck$LassoCheckResult]: Stem: 56436#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 56437#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 56536#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 56537#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 56282#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 56283#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 56550#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 56502#L375-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 56503#L380-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 56531#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 56513#L526 assume !(0 == ~M_E~0); 56514#L526-2 assume !(0 == ~T1_E~0); 56552#L531-1 assume !(0 == ~T2_E~0); 56498#L536-1 assume !(0 == ~T3_E~0); 56499#L541-1 assume !(0 == ~T4_E~0); 56494#L546-1 assume !(0 == ~E_M~0); 56495#L551-1 assume !(0 == ~E_1~0); 56471#L556-1 assume !(0 == ~E_2~0); 56472#L561-1 assume !(0 == ~E_3~0); 56481#L566-1 assume !(0 == ~E_4~0); 56482#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 56476#L262 assume !(1 == ~m_pc~0); 56477#L262-2 is_master_triggered_~__retres1~0#1 := 0; 56664#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 56405#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 56406#L649 assume !(0 != activate_threads_~tmp~1#1); 56660#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 56415#L281 assume !(1 == ~t1_pc~0); 56416#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 56332#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 56247#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 56248#L657 assume !(0 != activate_threads_~tmp___0~0#1); 56391#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 56484#L300 assume !(1 == ~t2_pc~0); 56485#L300-2 is_transmit2_triggered_~__retres1~2#1 := 0; 56592#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 56539#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 56507#L665 assume !(0 != activate_threads_~tmp___1~0#1); 56260#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 56261#L319 assume !(1 == ~t3_pc~0); 56215#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 56216#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 56202#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 56203#L673 assume !(0 != activate_threads_~tmp___2~0#1); 56237#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 56238#L338 assume !(1 == ~t4_pc~0); 56307#L338-2 is_transmit4_triggered_~__retres1~4#1 := 0; 56308#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 56313#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 56314#L681 assume !(0 != activate_threads_~tmp___3~0#1); 56184#L681-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 56185#L584 assume !(1 == ~M_E~0); 56388#L584-2 assume !(1 == ~T1_E~0); 56347#L589-1 assume !(1 == ~T2_E~0); 56348#L594-1 assume !(1 == ~T3_E~0); 56440#L599-1 assume !(1 == ~T4_E~0); 56214#L604-1 assume !(1 == ~E_M~0); 56200#L609-1 assume !(1 == ~E_1~0); 56201#L614-1 assume !(1 == ~E_2~0); 56322#L619-1 assume !(1 == ~E_3~0); 56407#L624-1 assume !(1 == ~E_4~0); 56504#L629-1 assume { :end_inline_reset_delta_events } true; 56668#L815-2 [2022-12-13 14:12:51,711 INFO L750 eck$LassoCheckResult]: Loop: 56668#L815-2 assume !false; 58923#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 58921#L501 assume !false; 58919#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 58917#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 58910#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 58908#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 58906#L440 assume !(0 != eval_~tmp~0#1); 56323#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 56324#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 56441#L526-3 assume !(0 == ~M_E~0); 56442#L526-5 assume !(0 == ~T1_E~0); 56325#L531-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 56326#L536-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 56208#L541-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 56209#L546-3 assume 0 == ~E_M~0;~E_M~0 := 1; 60662#L551-3 assume !(0 == ~E_1~0); 60661#L556-3 assume 0 == ~E_2~0;~E_2~0 := 1; 56561#L561-3 assume 0 == ~E_3~0;~E_3~0 := 1; 56562#L566-3 assume !(0 == ~E_4~0); 56336#L571-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 56337#L262-18 assume !(1 == ~m_pc~0); 60558#L262-20 is_master_triggered_~__retres1~0#1 := 0; 60557#L273-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 60556#is_master_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 60555#L649-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 60554#L649-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 60553#L281-18 assume !(1 == ~t1_pc~0); 60551#L281-20 is_transmit1_triggered_~__retres1~1#1 := 0; 60550#L292-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 60549#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 60548#L657-18 assume !(0 != activate_threads_~tmp___0~0#1); 60547#L657-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 60314#L300-18 assume !(1 == ~t2_pc~0); 60313#L300-20 is_transmit2_triggered_~__retres1~2#1 := 0; 58932#L311-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 58927#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 58922#L665-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 58920#L665-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 58918#L319-18 assume 1 == ~t3_pc~0; 58912#L320-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 58909#L330-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 58907#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 58905#L673-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 58903#L673-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 58902#L338-18 assume !(1 == ~t4_pc~0); 58901#L338-20 is_transmit4_triggered_~__retres1~4#1 := 0; 58900#L349-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 58899#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 58897#L681-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 58895#L681-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 58893#L584-3 assume !(1 == ~M_E~0); 57846#L584-5 assume !(1 == ~T1_E~0); 58890#L589-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 58888#L594-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 58887#L599-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 58884#L604-3 assume 1 == ~E_M~0;~E_M~0 := 2; 58882#L609-3 assume !(1 == ~E_1~0); 58880#L614-3 assume 1 == ~E_2~0;~E_2~0 := 2; 58878#L619-3 assume 1 == ~E_3~0;~E_3~0 := 2; 58876#L624-3 assume 1 == ~E_4~0;~E_4~0 := 2; 58874#L629-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 58868#L398-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 58861#L425-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 58859#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 56368#L834 assume !(0 == start_simulation_~tmp~3#1); 56370#L834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 58955#L398-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 58951#L425-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 58949#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 58947#L789 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 58945#L796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 58941#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 58939#L847 assume !(0 != start_simulation_~tmp___0~1#1); 56668#L815-2 [2022-12-13 14:12:51,711 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 14:12:51,711 INFO L85 PathProgramCache]: Analyzing trace with hash 1546408329, now seen corresponding path program 1 times [2022-12-13 14:12:51,711 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 14:12:51,711 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1347888019] [2022-12-13 14:12:51,711 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 14:12:51,712 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 14:12:51,720 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 14:12:51,720 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 14:12:51,725 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 14:12:51,753 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 14:12:51,753 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 14:12:51,754 INFO L85 PathProgramCache]: Analyzing trace with hash 1121243341, now seen corresponding path program 1 times [2022-12-13 14:12:51,754 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 14:12:51,754 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1702486914] [2022-12-13 14:12:51,754 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 14:12:51,754 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 14:12:51,763 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 14:12:51,796 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 14:12:51,796 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 14:12:51,796 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1702486914] [2022-12-13 14:12:51,796 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1702486914] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 14:12:51,796 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 14:12:51,796 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-12-13 14:12:51,796 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1099133436] [2022-12-13 14:12:51,796 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 14:12:51,797 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 14:12:51,797 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 14:12:51,797 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-12-13 14:12:51,797 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-12-13 14:12:51,797 INFO L87 Difference]: Start difference. First operand 4508 states and 6321 transitions. cyclomatic complexity: 1817 Second operand has 5 states, 5 states have (on average 14.8) internal successors, (74), 5 states have internal predecessors, (74), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 14:12:51,881 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 14:12:51,881 INFO L93 Difference]: Finished difference Result 7968 states and 11013 transitions. [2022-12-13 14:12:51,882 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7968 states and 11013 transitions. [2022-12-13 14:12:51,914 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 7856 [2022-12-13 14:12:51,928 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7968 states to 7968 states and 11013 transitions. [2022-12-13 14:12:51,928 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7968 [2022-12-13 14:12:51,931 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7968 [2022-12-13 14:12:51,932 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7968 states and 11013 transitions. [2022-12-13 14:12:51,935 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 14:12:51,936 INFO L218 hiAutomatonCegarLoop]: Abstraction has 7968 states and 11013 transitions. [2022-12-13 14:12:51,940 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7968 states and 11013 transitions. [2022-12-13 14:12:51,977 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7968 to 4556. [2022-12-13 14:12:51,982 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4556 states, 4556 states have (on average 1.3979367866549606) internal successors, (6369), 4555 states have internal predecessors, (6369), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 14:12:52,007 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4556 states to 4556 states and 6369 transitions. [2022-12-13 14:12:52,007 INFO L240 hiAutomatonCegarLoop]: Abstraction has 4556 states and 6369 transitions. [2022-12-13 14:12:52,008 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2022-12-13 14:12:52,008 INFO L428 stractBuchiCegarLoop]: Abstraction has 4556 states and 6369 transitions. [2022-12-13 14:12:52,008 INFO L335 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2022-12-13 14:12:52,008 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4556 states and 6369 transitions. [2022-12-13 14:12:52,024 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4468 [2022-12-13 14:12:52,024 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 14:12:52,024 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 14:12:52,026 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 14:12:52,026 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 14:12:52,026 INFO L748 eck$LassoCheckResult]: Stem: 68928#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 68929#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 69029#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 69030#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 68772#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 68773#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 69044#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 68994#L375-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 68995#L380-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 69024#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 69005#L526 assume !(0 == ~M_E~0); 69006#L526-2 assume !(0 == ~T1_E~0); 69046#L531-1 assume !(0 == ~T2_E~0); 68990#L536-1 assume !(0 == ~T3_E~0); 68991#L541-1 assume !(0 == ~T4_E~0); 68986#L546-1 assume !(0 == ~E_M~0); 68987#L551-1 assume !(0 == ~E_1~0); 68964#L556-1 assume !(0 == ~E_2~0); 68965#L561-1 assume !(0 == ~E_3~0); 68974#L566-1 assume !(0 == ~E_4~0); 68975#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 68969#L262 assume !(1 == ~m_pc~0); 68970#L262-2 is_master_triggered_~__retres1~0#1 := 0; 69149#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 68899#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 68900#L649 assume !(0 != activate_threads_~tmp~1#1); 69148#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 68908#L281 assume !(1 == ~t1_pc~0); 68909#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 68823#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 68738#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 68739#L657 assume !(0 != activate_threads_~tmp___0~0#1); 68883#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 68977#L300 assume !(1 == ~t2_pc~0); 68978#L300-2 is_transmit2_triggered_~__retres1~2#1 := 0; 69080#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 69032#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 68998#L665 assume !(0 != activate_threads_~tmp___1~0#1); 68751#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 68752#L319 assume !(1 == ~t3_pc~0); 68707#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 68708#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 68694#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 68695#L673 assume !(0 != activate_threads_~tmp___2~0#1); 68728#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 68729#L338 assume !(1 == ~t4_pc~0); 68796#L338-2 is_transmit4_triggered_~__retres1~4#1 := 0; 68797#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 68803#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 68804#L681 assume !(0 != activate_threads_~tmp___3~0#1); 68676#L681-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 68677#L584 assume !(1 == ~M_E~0); 68880#L584-2 assume !(1 == ~T1_E~0); 68841#L589-1 assume !(1 == ~T2_E~0); 68842#L594-1 assume !(1 == ~T3_E~0); 68934#L599-1 assume !(1 == ~T4_E~0); 68706#L604-1 assume !(1 == ~E_M~0); 68692#L609-1 assume !(1 == ~E_1~0); 68693#L614-1 assume !(1 == ~E_2~0); 68813#L619-1 assume !(1 == ~E_3~0); 68901#L624-1 assume !(1 == ~E_4~0); 68996#L629-1 assume { :end_inline_reset_delta_events } true; 69154#L815-2 [2022-12-13 14:12:52,026 INFO L750 eck$LassoCheckResult]: Loop: 69154#L815-2 assume !false; 72858#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 72786#L501 assume !false; 72702#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 72700#L398 assume !(0 == ~m_st~0); 72697#L402 assume !(0 == ~t1_st~0); 72698#L406 assume !(0 == ~t2_st~0); 72699#L410 assume !(0 == ~t3_st~0); 72695#L414 assume !(0 == ~t4_st~0);exists_runnable_thread_~__retres1~5#1 := 0; 72696#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 70666#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 70667#L440 assume !(0 != eval_~tmp~0#1); 72673#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 72671#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 72669#L526-3 assume !(0 == ~M_E~0); 72664#L526-5 assume !(0 == ~T1_E~0); 72665#L531-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 72658#L536-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 72659#L541-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 72652#L546-3 assume 0 == ~E_M~0;~E_M~0 := 1; 72653#L551-3 assume !(0 == ~E_1~0); 72645#L556-3 assume 0 == ~E_2~0;~E_2~0 := 1; 72646#L561-3 assume 0 == ~E_3~0;~E_3~0 := 1; 72639#L566-3 assume !(0 == ~E_4~0); 72640#L571-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 72630#L262-18 assume !(1 == ~m_pc~0); 72631#L262-20 is_master_triggered_~__retres1~0#1 := 0; 72620#L273-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 72621#is_master_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 72613#L649-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 72614#L649-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 72585#L281-18 assume !(1 == ~t1_pc~0); 72584#L281-20 is_transmit1_triggered_~__retres1~1#1 := 0; 72555#L292-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 72556#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 72543#L657-18 assume !(0 != activate_threads_~tmp___0~0#1); 72544#L657-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 72523#L300-18 assume !(1 == ~t2_pc~0); 71499#L300-20 is_transmit2_triggered_~__retres1~2#1 := 0; 72517#L311-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 72518#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 72455#L665-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 72456#L665-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 72438#L319-18 assume !(1 == ~t3_pc~0); 72439#L319-20 is_transmit3_triggered_~__retres1~3#1 := 0; 68854#L330-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 68855#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 69027#L673-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 69028#L673-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 68906#L338-18 assume !(1 == ~t4_pc~0); 68907#L338-20 is_transmit4_triggered_~__retres1~4#1 := 0; 72952#L349-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 72950#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 72948#L681-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 72946#L681-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 72944#L584-3 assume !(1 == ~M_E~0); 72941#L584-5 assume !(1 == ~T1_E~0); 72940#L589-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 72939#L594-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 72938#L599-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 72937#L604-3 assume 1 == ~E_M~0;~E_M~0 := 2; 72936#L609-3 assume !(1 == ~E_1~0); 72935#L614-3 assume 1 == ~E_2~0;~E_2~0 := 2; 72934#L619-3 assume 1 == ~E_3~0;~E_3~0 := 2; 72933#L624-3 assume 1 == ~E_4~0;~E_4~0 := 2; 72932#L629-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 72930#L398-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 72920#L425-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 72915#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 72910#L834 assume !(0 == start_simulation_~tmp~3#1); 72897#L834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 72894#L398-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 72889#L425-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 72887#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 72885#L789 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 72883#L796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 72881#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 72879#L847 assume !(0 != start_simulation_~tmp___0~1#1); 69154#L815-2 [2022-12-13 14:12:52,027 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 14:12:52,027 INFO L85 PathProgramCache]: Analyzing trace with hash 1546408329, now seen corresponding path program 2 times [2022-12-13 14:12:52,027 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 14:12:52,027 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [374150919] [2022-12-13 14:12:52,027 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 14:12:52,028 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 14:12:52,038 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 14:12:52,038 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 14:12:52,045 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 14:12:52,059 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 14:12:52,059 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 14:12:52,059 INFO L85 PathProgramCache]: Analyzing trace with hash 1060856770, now seen corresponding path program 1 times [2022-12-13 14:12:52,060 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 14:12:52,060 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1347936550] [2022-12-13 14:12:52,060 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 14:12:52,060 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 14:12:52,071 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 14:12:52,132 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 14:12:52,132 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 14:12:52,133 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1347936550] [2022-12-13 14:12:52,133 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1347936550] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 14:12:52,133 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 14:12:52,133 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-12-13 14:12:52,133 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [112488938] [2022-12-13 14:12:52,133 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 14:12:52,134 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 14:12:52,134 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 14:12:52,134 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-12-13 14:12:52,134 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-12-13 14:12:52,135 INFO L87 Difference]: Start difference. First operand 4556 states and 6369 transitions. cyclomatic complexity: 1817 Second operand has 5 states, 5 states have (on average 15.6) internal successors, (78), 5 states have internal predecessors, (78), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 14:12:52,326 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 14:12:52,326 INFO L93 Difference]: Finished difference Result 15184 states and 20965 transitions. [2022-12-13 14:12:52,326 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 15184 states and 20965 transitions. [2022-12-13 14:12:52,425 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 15024 [2022-12-13 14:12:52,451 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 15184 states to 15184 states and 20965 transitions. [2022-12-13 14:12:52,451 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 15184 [2022-12-13 14:12:52,458 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 15184 [2022-12-13 14:12:52,458 INFO L73 IsDeterministic]: Start isDeterministic. Operand 15184 states and 20965 transitions. [2022-12-13 14:12:52,466 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 14:12:52,466 INFO L218 hiAutomatonCegarLoop]: Abstraction has 15184 states and 20965 transitions. [2022-12-13 14:12:52,476 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15184 states and 20965 transitions. [2022-12-13 14:12:52,527 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15184 to 4604. [2022-12-13 14:12:52,532 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4604 states, 4604 states have (on average 1.3937880104257168) internal successors, (6417), 4603 states have internal predecessors, (6417), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 14:12:52,538 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4604 states to 4604 states and 6417 transitions. [2022-12-13 14:12:52,538 INFO L240 hiAutomatonCegarLoop]: Abstraction has 4604 states and 6417 transitions. [2022-12-13 14:12:52,539 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2022-12-13 14:12:52,539 INFO L428 stractBuchiCegarLoop]: Abstraction has 4604 states and 6417 transitions. [2022-12-13 14:12:52,539 INFO L335 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2022-12-13 14:12:52,539 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4604 states and 6417 transitions. [2022-12-13 14:12:52,548 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4516 [2022-12-13 14:12:52,548 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 14:12:52,548 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 14:12:52,549 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 14:12:52,549 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 14:12:52,549 INFO L748 eck$LassoCheckResult]: Stem: 88681#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 88682#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 88785#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 88786#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 88531#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 88532#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 88799#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 88747#L375-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 88748#L380-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 88776#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 88758#L526 assume !(0 == ~M_E~0); 88759#L526-2 assume !(0 == ~T1_E~0); 88802#L531-1 assume !(0 == ~T2_E~0); 88743#L536-1 assume !(0 == ~T3_E~0); 88744#L541-1 assume !(0 == ~T4_E~0); 88738#L546-1 assume !(0 == ~E_M~0); 88739#L551-1 assume !(0 == ~E_1~0); 88715#L556-1 assume !(0 == ~E_2~0); 88716#L561-1 assume !(0 == ~E_3~0); 88725#L566-1 assume !(0 == ~E_4~0); 88726#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 88720#L262 assume !(1 == ~m_pc~0); 88721#L262-2 is_master_triggered_~__retres1~0#1 := 0; 88915#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 88651#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 88652#L649 assume !(0 != activate_threads_~tmp~1#1); 88911#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 88660#L281 assume !(1 == ~t1_pc~0); 88661#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 88581#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 88495#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 88496#L657 assume !(0 != activate_threads_~tmp___0~0#1); 88637#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 88729#L300 assume !(1 == ~t2_pc~0); 88730#L300-2 is_transmit2_triggered_~__retres1~2#1 := 0; 88840#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 88789#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 88752#L665 assume !(0 != activate_threads_~tmp___1~0#1); 88508#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 88509#L319 assume !(1 == ~t3_pc~0); 88464#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 88465#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 88451#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 88452#L673 assume !(0 != activate_threads_~tmp___2~0#1); 88485#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 88486#L338 assume !(1 == ~t4_pc~0); 88555#L338-2 is_transmit4_triggered_~__retres1~4#1 := 0; 88556#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 88561#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 88562#L681 assume !(0 != activate_threads_~tmp___3~0#1); 88433#L681-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 88434#L584 assume !(1 == ~M_E~0); 88634#L584-2 assume !(1 == ~T1_E~0); 88595#L589-1 assume !(1 == ~T2_E~0); 88596#L594-1 assume !(1 == ~T3_E~0); 88685#L599-1 assume !(1 == ~T4_E~0); 88463#L604-1 assume !(1 == ~E_M~0); 88449#L609-1 assume !(1 == ~E_1~0); 88450#L614-1 assume !(1 == ~E_2~0); 88571#L619-1 assume !(1 == ~E_3~0); 88653#L624-1 assume !(1 == ~E_4~0); 88749#L629-1 assume { :end_inline_reset_delta_events } true; 88923#L815-2 [2022-12-13 14:12:52,549 INFO L750 eck$LassoCheckResult]: Loop: 88923#L815-2 assume !false; 92022#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 92020#L501 assume !false; 92019#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 91757#L398 assume !(0 == ~m_st~0); 91754#L402 assume !(0 == ~t1_st~0); 91755#L406 assume !(0 == ~t2_st~0); 91756#L410 assume !(0 == ~t3_st~0); 91752#L414 assume !(0 == ~t4_st~0);exists_runnable_thread_~__retres1~5#1 := 0; 91753#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 91746#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 91747#L440 assume !(0 != eval_~tmp~0#1); 92756#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 92755#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 92754#L526-3 assume !(0 == ~M_E~0); 88830#L526-5 assume !(0 == ~T1_E~0); 88831#L531-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 88921#L536-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 88922#L541-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 88750#L546-3 assume 0 == ~E_M~0;~E_M~0 := 1; 88751#L551-3 assume !(0 == ~E_1~0); 92753#L556-3 assume 0 == ~E_2~0;~E_2~0 := 1; 88811#L561-3 assume 0 == ~E_3~0;~E_3~0 := 1; 88812#L566-3 assume !(0 == ~E_4~0); 92730#L571-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 88829#L262-18 assume !(1 == ~m_pc~0); 88673#L262-20 is_master_triggered_~__retres1~0#1 := 0; 88674#L273-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 88693#is_master_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 88694#L649-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 88470#L649-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 88471#L281-18 assume !(1 == ~t1_pc~0); 88712#L281-20 is_transmit1_triggered_~__retres1~1#1 := 0; 88835#L292-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 92855#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 92853#L657-18 assume !(0 != activate_threads_~tmp___0~0#1); 92851#L657-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 88890#L300-18 assume !(1 == ~t2_pc~0); 88891#L300-20 is_transmit2_triggered_~__retres1~2#1 := 0; 92843#L311-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 92841#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 92593#L665-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 92591#L665-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 92587#L319-18 assume 1 == ~t3_pc~0; 92589#L320-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 92580#L330-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 92581#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 92574#L673-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 92575#L673-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 88658#L338-18 assume !(1 == ~t4_pc~0); 88659#L338-20 is_transmit4_triggered_~__retres1~4#1 := 0; 92983#L349-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 92982#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 92981#L681-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 92980#L681-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 92979#L584-3 assume !(1 == ~M_E~0); 91881#L584-5 assume !(1 == ~T1_E~0); 92978#L589-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 92977#L594-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 92976#L599-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 88703#L604-3 assume 1 == ~E_M~0;~E_M~0 := 2; 88704#L609-3 assume !(1 == ~E_1~0); 88767#L614-3 assume 1 == ~E_2~0;~E_2~0 := 2; 88479#L619-3 assume 1 == ~E_3~0;~E_3~0 := 2; 88480#L624-3 assume 1 == ~E_4~0;~E_4~0 := 2; 88777#L629-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 88816#L398-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 88565#L425-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 88566#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 88616#L834 assume !(0 == start_simulation_~tmp~3#1); 88617#L834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 92037#L398-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 92034#L425-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 92032#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 92030#L789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 92028#L796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 92027#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 92026#L847 assume !(0 != start_simulation_~tmp___0~1#1); 88923#L815-2 [2022-12-13 14:12:52,550 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 14:12:52,550 INFO L85 PathProgramCache]: Analyzing trace with hash 1546408329, now seen corresponding path program 3 times [2022-12-13 14:12:52,550 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 14:12:52,550 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [145767666] [2022-12-13 14:12:52,550 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 14:12:52,550 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 14:12:52,555 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 14:12:52,555 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 14:12:52,559 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 14:12:52,565 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 14:12:52,565 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 14:12:52,565 INFO L85 PathProgramCache]: Analyzing trace with hash 9348099, now seen corresponding path program 1 times [2022-12-13 14:12:52,565 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 14:12:52,565 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [788560499] [2022-12-13 14:12:52,565 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 14:12:52,566 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 14:12:52,572 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 14:12:52,638 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 14:12:52,638 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 14:12:52,639 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [788560499] [2022-12-13 14:12:52,639 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [788560499] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 14:12:52,639 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 14:12:52,639 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-12-13 14:12:52,639 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2109803160] [2022-12-13 14:12:52,639 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 14:12:52,639 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 14:12:52,639 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 14:12:52,640 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-12-13 14:12:52,640 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-12-13 14:12:52,640 INFO L87 Difference]: Start difference. First operand 4604 states and 6417 transitions. cyclomatic complexity: 1817 Second operand has 5 states, 5 states have (on average 15.6) internal successors, (78), 5 states have internal predecessors, (78), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 14:12:52,778 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 14:12:52,778 INFO L93 Difference]: Finished difference Result 9176 states and 12704 transitions. [2022-12-13 14:12:52,778 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 9176 states and 12704 transitions. [2022-12-13 14:12:52,803 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 9072 [2022-12-13 14:12:52,821 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 9176 states to 9176 states and 12704 transitions. [2022-12-13 14:12:52,821 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9176 [2022-12-13 14:12:52,826 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9176 [2022-12-13 14:12:52,826 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9176 states and 12704 transitions. [2022-12-13 14:12:52,831 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 14:12:52,831 INFO L218 hiAutomatonCegarLoop]: Abstraction has 9176 states and 12704 transitions. [2022-12-13 14:12:52,836 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9176 states and 12704 transitions. [2022-12-13 14:12:52,903 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9176 to 4736. [2022-12-13 14:12:52,910 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4736 states, 4736 states have (on average 1.375) internal successors, (6512), 4735 states have internal predecessors, (6512), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 14:12:52,922 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4736 states to 4736 states and 6512 transitions. [2022-12-13 14:12:52,923 INFO L240 hiAutomatonCegarLoop]: Abstraction has 4736 states and 6512 transitions. [2022-12-13 14:12:52,923 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-12-13 14:12:52,923 INFO L428 stractBuchiCegarLoop]: Abstraction has 4736 states and 6512 transitions. [2022-12-13 14:12:52,923 INFO L335 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2022-12-13 14:12:52,924 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4736 states and 6512 transitions. [2022-12-13 14:12:52,935 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4648 [2022-12-13 14:12:52,935 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 14:12:52,935 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 14:12:52,936 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 14:12:52,936 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 14:12:52,936 INFO L748 eck$LassoCheckResult]: Stem: 102481#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 102482#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 102590#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 102591#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 102324#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 102325#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 102607#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 102552#L375-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 102553#L380-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 102586#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 102563#L526 assume !(0 == ~M_E~0); 102564#L526-2 assume !(0 == ~T1_E~0); 102609#L531-1 assume !(0 == ~T2_E~0); 102548#L536-1 assume !(0 == ~T3_E~0); 102549#L541-1 assume !(0 == ~T4_E~0); 102543#L546-1 assume !(0 == ~E_M~0); 102544#L551-1 assume !(0 == ~E_1~0); 102517#L556-1 assume !(0 == ~E_2~0); 102518#L561-1 assume !(0 == ~E_3~0); 102528#L566-1 assume !(0 == ~E_4~0); 102529#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 102522#L262 assume !(1 == ~m_pc~0); 102523#L262-2 is_master_triggered_~__retres1~0#1 := 0; 102727#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 102451#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 102452#L649 assume !(0 != activate_threads_~tmp~1#1); 102726#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 102460#L281 assume !(1 == ~t1_pc~0); 102461#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 102376#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 102288#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 102289#L657 assume !(0 != activate_threads_~tmp___0~0#1); 102435#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 102531#L300 assume !(1 == ~t2_pc~0); 102532#L300-2 is_transmit2_triggered_~__retres1~2#1 := 0; 102648#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 102594#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 102556#L665 assume !(0 != activate_threads_~tmp___1~0#1); 102301#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 102302#L319 assume !(1 == ~t3_pc~0); 102257#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 102258#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 102244#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 102245#L673 assume !(0 != activate_threads_~tmp___2~0#1); 102278#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 102279#L338 assume !(1 == ~t4_pc~0); 102348#L338-2 is_transmit4_triggered_~__retres1~4#1 := 0; 102349#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 102356#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 102357#L681 assume !(0 != activate_threads_~tmp___3~0#1); 102226#L681-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 102227#L584 assume !(1 == ~M_E~0); 102432#L584-2 assume !(1 == ~T1_E~0); 102392#L589-1 assume !(1 == ~T2_E~0); 102393#L594-1 assume !(1 == ~T3_E~0); 102487#L599-1 assume !(1 == ~T4_E~0); 102256#L604-1 assume !(1 == ~E_M~0); 102242#L609-1 assume !(1 == ~E_1~0); 102243#L614-1 assume !(1 == ~E_2~0); 102366#L619-1 assume !(1 == ~E_3~0); 102453#L624-1 assume !(1 == ~E_4~0); 102554#L629-1 assume { :end_inline_reset_delta_events } true; 102735#L815-2 [2022-12-13 14:12:52,937 INFO L750 eck$LassoCheckResult]: Loop: 102735#L815-2 assume !false; 104454#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 104447#L501 assume !false; 104445#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 104443#L398 assume !(0 == ~m_st~0); 104440#L402 assume !(0 == ~t1_st~0); 104441#L406 assume !(0 == ~t2_st~0); 104442#L410 assume !(0 == ~t3_st~0); 104438#L414 assume !(0 == ~t4_st~0);exists_runnable_thread_~__retres1~5#1 := 0; 104439#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 103811#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 103812#L440 assume !(0 != eval_~tmp~0#1); 104820#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 104819#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 104818#L526-3 assume !(0 == ~M_E~0); 104817#L526-5 assume !(0 == ~T1_E~0); 104816#L531-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 104815#L536-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 104814#L541-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 104813#L546-3 assume 0 == ~E_M~0;~E_M~0 := 1; 104812#L551-3 assume !(0 == ~E_1~0); 104811#L556-3 assume 0 == ~E_2~0;~E_2~0 := 1; 104810#L561-3 assume 0 == ~E_3~0;~E_3~0 := 1; 102951#L566-3 assume !(0 == ~E_4~0); 102380#L571-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 102381#L262-18 assume !(1 == ~m_pc~0); 102641#L262-20 is_master_triggered_~__retres1~0#1 := 0; 106313#L273-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 106312#is_master_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 106311#L649-18 assume !(0 != activate_threads_~tmp~1#1); 106310#L649-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 106309#L281-18 assume !(1 == ~t1_pc~0); 106307#L281-20 is_transmit1_triggered_~__retres1~1#1 := 0; 106306#L292-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 106305#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 106304#L657-18 assume !(0 != activate_threads_~tmp___0~0#1); 106303#L657-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 106302#L300-18 assume !(1 == ~t2_pc~0); 104700#L300-20 is_transmit2_triggered_~__retres1~2#1 := 0; 106301#L311-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 106300#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 106299#L665-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 106298#L665-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 106297#L319-18 assume !(1 == ~t3_pc~0); 106295#L319-20 is_transmit3_triggered_~__retres1~3#1 := 0; 106294#L330-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 106293#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 106292#L673-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 106291#L673-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 106290#L338-18 assume !(1 == ~t4_pc~0); 106289#L338-20 is_transmit4_triggered_~__retres1~4#1 := 0; 106288#L349-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 106287#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 106286#L681-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 106285#L681-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 106284#L584-3 assume !(1 == ~M_E~0); 103944#L584-5 assume !(1 == ~T1_E~0); 106283#L589-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 106282#L594-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 106281#L599-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 106280#L604-3 assume 1 == ~E_M~0;~E_M~0 := 2; 106279#L609-3 assume !(1 == ~E_1~0); 106278#L614-3 assume 1 == ~E_2~0;~E_2~0 := 2; 106277#L619-3 assume 1 == ~E_3~0;~E_3~0 := 2; 106276#L624-3 assume 1 == ~E_4~0;~E_4~0 := 2; 106275#L629-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 106273#L398-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 106269#L425-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 106268#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 102414#L834 assume !(0 == start_simulation_~tmp~3#1); 102415#L834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 104480#L398-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 104473#L425-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 104467#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 104465#L789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 104462#L796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 104461#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 104460#L847 assume !(0 != start_simulation_~tmp___0~1#1); 102735#L815-2 [2022-12-13 14:12:52,937 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 14:12:52,937 INFO L85 PathProgramCache]: Analyzing trace with hash 1546408329, now seen corresponding path program 4 times [2022-12-13 14:12:52,937 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 14:12:52,937 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1677452970] [2022-12-13 14:12:52,938 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 14:12:52,938 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 14:12:52,947 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 14:12:52,947 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 14:12:52,951 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 14:12:52,959 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 14:12:52,959 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 14:12:52,959 INFO L85 PathProgramCache]: Analyzing trace with hash 1045278470, now seen corresponding path program 1 times [2022-12-13 14:12:52,959 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 14:12:52,960 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [857103305] [2022-12-13 14:12:52,960 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 14:12:52,960 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 14:12:52,967 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 14:12:52,987 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 14:12:52,987 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 14:12:52,987 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [857103305] [2022-12-13 14:12:52,987 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [857103305] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 14:12:52,988 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 14:12:52,988 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 14:12:52,988 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1006088872] [2022-12-13 14:12:52,988 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 14:12:52,988 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 14:12:52,988 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 14:12:52,989 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 14:12:52,989 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 14:12:52,989 INFO L87 Difference]: Start difference. First operand 4736 states and 6512 transitions. cyclomatic complexity: 1780 Second operand has 3 states, 3 states have (on average 26.0) internal successors, (78), 3 states have internal predecessors, (78), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 14:12:53,051 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 14:12:53,052 INFO L93 Difference]: Finished difference Result 7392 states and 10008 transitions. [2022-12-13 14:12:53,052 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7392 states and 10008 transitions. [2022-12-13 14:12:53,077 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 7294 [2022-12-13 14:12:53,096 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7392 states to 7392 states and 10008 transitions. [2022-12-13 14:12:53,096 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7392 [2022-12-13 14:12:53,100 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7392 [2022-12-13 14:12:53,100 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7392 states and 10008 transitions. [2022-12-13 14:12:53,104 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 14:12:53,104 INFO L218 hiAutomatonCegarLoop]: Abstraction has 7392 states and 10008 transitions. [2022-12-13 14:12:53,108 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7392 states and 10008 transitions. [2022-12-13 14:12:53,166 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7392 to 7136. [2022-12-13 14:12:53,174 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7136 states, 7136 states have (on average 1.3553811659192825) internal successors, (9672), 7135 states have internal predecessors, (9672), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 14:12:53,187 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7136 states to 7136 states and 9672 transitions. [2022-12-13 14:12:53,187 INFO L240 hiAutomatonCegarLoop]: Abstraction has 7136 states and 9672 transitions. [2022-12-13 14:12:53,188 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 14:12:53,188 INFO L428 stractBuchiCegarLoop]: Abstraction has 7136 states and 9672 transitions. [2022-12-13 14:12:53,188 INFO L335 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2022-12-13 14:12:53,188 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7136 states and 9672 transitions. [2022-12-13 14:12:53,205 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 7038 [2022-12-13 14:12:53,206 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 14:12:53,206 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 14:12:53,206 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 14:12:53,206 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 14:12:53,207 INFO L748 eck$LassoCheckResult]: Stem: 114611#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 114612#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 114716#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 114717#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 114455#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 114456#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 114732#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 114678#L375-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 114679#L380-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 114709#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 114688#L526 assume !(0 == ~M_E~0); 114689#L526-2 assume !(0 == ~T1_E~0); 114735#L531-1 assume !(0 == ~T2_E~0); 114674#L536-1 assume !(0 == ~T3_E~0); 114675#L541-1 assume !(0 == ~T4_E~0); 114669#L546-1 assume !(0 == ~E_M~0); 114670#L551-1 assume !(0 == ~E_1~0); 114645#L556-1 assume !(0 == ~E_2~0); 114646#L561-1 assume !(0 == ~E_3~0); 114656#L566-1 assume !(0 == ~E_4~0); 114657#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 114650#L262 assume !(1 == ~m_pc~0); 114651#L262-2 is_master_triggered_~__retres1~0#1 := 0; 114861#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 114582#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 114583#L649 assume !(0 != activate_threads_~tmp~1#1); 114859#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 114591#L281 assume !(1 == ~t1_pc~0); 114592#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 114507#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 114422#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 114423#L657 assume !(0 != activate_threads_~tmp___0~0#1); 114566#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 114659#L300 assume !(1 == ~t2_pc~0); 114660#L300-2 is_transmit2_triggered_~__retres1~2#1 := 0; 114779#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 114721#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 114682#L665 assume !(0 != activate_threads_~tmp___1~0#1); 114435#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 114436#L319 assume !(1 == ~t3_pc~0); 114391#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 114392#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 114378#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 114379#L673 assume !(0 != activate_threads_~tmp___2~0#1); 114412#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 114413#L338 assume !(1 == ~t4_pc~0); 114480#L338-2 is_transmit4_triggered_~__retres1~4#1 := 0; 114481#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 114486#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 114487#L681 assume !(0 != activate_threads_~tmp___3~0#1); 114360#L681-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 114361#L584 assume !(1 == ~M_E~0); 114563#L584-2 assume !(1 == ~T1_E~0); 114523#L589-1 assume !(1 == ~T2_E~0); 114524#L594-1 assume !(1 == ~T3_E~0); 114615#L599-1 assume !(1 == ~T4_E~0); 114390#L604-1 assume !(1 == ~E_M~0); 114376#L609-1 assume !(1 == ~E_1~0); 114377#L614-1 assume !(1 == ~E_2~0); 114497#L619-1 assume !(1 == ~E_3~0); 114584#L624-1 assume !(1 == ~E_4~0); 114680#L629-1 assume { :end_inline_reset_delta_events } true; 114866#L815-2 assume !false; 116887#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 116689#L501 [2022-12-13 14:12:53,207 INFO L750 eck$LassoCheckResult]: Loop: 116689#L501 assume !false; 116873#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 116865#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 116859#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 116851#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 116844#L440 assume 0 != eval_~tmp~0#1; 116838#L440-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 116833#L448 assume !(0 != eval_~tmp_ndt_1~0#1); 116780#L445 assume !(0 == ~t1_st~0); 116773#L459 assume !(0 == ~t2_st~0); 116707#L473 assume !(0 == ~t3_st~0); 116690#L487 assume !(0 == ~t4_st~0); 116689#L501 [2022-12-13 14:12:53,207 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 14:12:53,207 INFO L85 PathProgramCache]: Analyzing trace with hash 39728939, now seen corresponding path program 1 times [2022-12-13 14:12:53,207 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 14:12:53,207 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1144151596] [2022-12-13 14:12:53,207 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 14:12:53,208 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 14:12:53,215 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 14:12:53,215 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 14:12:53,220 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 14:12:53,227 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 14:12:53,228 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 14:12:53,228 INFO L85 PathProgramCache]: Analyzing trace with hash 1608874715, now seen corresponding path program 1 times [2022-12-13 14:12:53,228 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 14:12:53,228 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1902104573] [2022-12-13 14:12:53,228 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 14:12:53,228 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 14:12:53,231 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 14:12:53,231 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 14:12:53,233 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 14:12:53,235 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 14:12:53,235 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 14:12:53,235 INFO L85 PathProgramCache]: Analyzing trace with hash 220742405, now seen corresponding path program 1 times [2022-12-13 14:12:53,235 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 14:12:53,236 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [759957240] [2022-12-13 14:12:53,236 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 14:12:53,236 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 14:12:53,243 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 14:12:53,265 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 14:12:53,265 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 14:12:53,265 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [759957240] [2022-12-13 14:12:53,265 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [759957240] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 14:12:53,266 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 14:12:53,266 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 14:12:53,266 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1605329026] [2022-12-13 14:12:53,266 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 14:12:53,332 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 14:12:53,333 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 14:12:53,333 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 14:12:53,333 INFO L87 Difference]: Start difference. First operand 7136 states and 9672 transitions. cyclomatic complexity: 2542 Second operand has 3 states, 3 states have (on average 25.333333333333332) internal successors, (76), 3 states have internal predecessors, (76), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 14:12:53,405 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 14:12:53,405 INFO L93 Difference]: Finished difference Result 11454 states and 15389 transitions. [2022-12-13 14:12:53,405 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 11454 states and 15389 transitions. [2022-12-13 14:12:53,470 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 11264 [2022-12-13 14:12:53,495 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 11454 states to 11454 states and 15389 transitions. [2022-12-13 14:12:53,495 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 11454 [2022-12-13 14:12:53,500 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11454 [2022-12-13 14:12:53,500 INFO L73 IsDeterministic]: Start isDeterministic. Operand 11454 states and 15389 transitions. [2022-12-13 14:12:53,506 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 14:12:53,506 INFO L218 hiAutomatonCegarLoop]: Abstraction has 11454 states and 15389 transitions. [2022-12-13 14:12:53,512 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11454 states and 15389 transitions. [2022-12-13 14:12:53,582 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11454 to 11454. [2022-12-13 14:12:53,591 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 11454 states, 11454 states have (on average 1.3435481054653395) internal successors, (15389), 11453 states have internal predecessors, (15389), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 14:12:53,603 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11454 states to 11454 states and 15389 transitions. [2022-12-13 14:12:53,603 INFO L240 hiAutomatonCegarLoop]: Abstraction has 11454 states and 15389 transitions. [2022-12-13 14:12:53,603 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 14:12:53,603 INFO L428 stractBuchiCegarLoop]: Abstraction has 11454 states and 15389 transitions. [2022-12-13 14:12:53,604 INFO L335 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2022-12-13 14:12:53,604 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 11454 states and 15389 transitions. [2022-12-13 14:12:53,625 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 11264 [2022-12-13 14:12:53,625 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 14:12:53,625 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 14:12:53,626 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 14:12:53,626 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 14:12:53,626 INFO L748 eck$LassoCheckResult]: Stem: 133218#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 133219#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 133329#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 133330#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 133056#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 133057#L365-2 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 133346#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 133347#L375-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 133458#L380-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 133459#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 133304#L526 assume !(0 == ~M_E~0); 133305#L526-2 assume !(0 == ~T1_E~0); 133349#L531-1 assume !(0 == ~T2_E~0); 133350#L536-1 assume !(0 == ~T3_E~0); 133421#L541-1 assume !(0 == ~T4_E~0); 133422#L546-1 assume !(0 == ~E_M~0); 133366#L551-1 assume !(0 == ~E_1~0); 133367#L556-1 assume !(0 == ~E_2~0); 133301#L561-1 assume !(0 == ~E_3~0); 133302#L566-1 assume !(0 == ~E_4~0); 133478#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 133479#L262 assume !(1 == ~m_pc~0); 133491#L262-2 is_master_triggered_~__retres1~0#1 := 0; 133492#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 133184#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 133185#L649 assume !(0 != activate_threads_~tmp~1#1); 133518#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 133519#L281 assume !(1 == ~t1_pc~0); 133496#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 133497#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 133021#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 133022#L657 assume !(0 != activate_threads_~tmp___0~0#1); 133472#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 133473#L300 assume !(1 == ~t2_pc~0); 133442#L300-2 is_transmit2_triggered_~__retres1~2#1 := 0; 133443#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 133333#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 133334#L665 assume !(0 != activate_threads_~tmp___1~0#1); 133034#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 133035#L319 assume !(1 == ~t3_pc~0); 132990#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 132991#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 132976#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 132977#L673 assume !(0 != activate_threads_~tmp___2~0#1); 133011#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 133012#L338 assume !(1 == ~t4_pc~0); 133080#L338-2 is_transmit4_triggered_~__retres1~4#1 := 0; 133081#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 133087#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 133088#L681 assume !(0 != activate_threads_~tmp___3~0#1); 132958#L681-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 132959#L584 assume !(1 == ~M_E~0); 133162#L584-2 assume !(1 == ~T1_E~0); 133163#L589-1 assume !(1 == ~T2_E~0); 133380#L594-1 assume !(1 == ~T3_E~0); 133381#L599-1 assume !(1 == ~T4_E~0); 132988#L604-1 assume !(1 == ~E_M~0); 132989#L609-1 assume !(1 == ~E_1~0); 133095#L614-1 assume !(1 == ~E_2~0); 133096#L619-1 assume !(1 == ~E_3~0); 133292#L624-1 assume !(1 == ~E_4~0); 133293#L629-1 assume { :end_inline_reset_delta_events } true; 140915#L815-2 assume !false; 140911#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 140866#L501 [2022-12-13 14:12:53,626 INFO L750 eck$LassoCheckResult]: Loop: 140866#L501 assume !false; 140905#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 140899#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 140895#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 140891#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 140860#L440 assume 0 != eval_~tmp~0#1; 140861#L440-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 133159#L448 assume !(0 != eval_~tmp_ndt_1~0#1); 133160#L445 assume !(0 == ~t1_st~0); 140872#L459 assume !(0 == ~t2_st~0); 140868#L473 assume !(0 == ~t3_st~0); 140867#L487 assume !(0 == ~t4_st~0); 140866#L501 [2022-12-13 14:12:53,626 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 14:12:53,627 INFO L85 PathProgramCache]: Analyzing trace with hash 600428717, now seen corresponding path program 1 times [2022-12-13 14:12:53,627 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 14:12:53,627 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2085222958] [2022-12-13 14:12:53,627 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 14:12:53,627 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 14:12:53,631 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 14:12:53,642 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 14:12:53,642 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 14:12:53,642 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2085222958] [2022-12-13 14:12:53,642 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2085222958] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 14:12:53,642 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 14:12:53,642 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 14:12:53,642 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [223185045] [2022-12-13 14:12:53,643 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 14:12:53,643 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 14:12:53,643 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 14:12:53,643 INFO L85 PathProgramCache]: Analyzing trace with hash 1608874715, now seen corresponding path program 2 times [2022-12-13 14:12:53,643 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 14:12:53,643 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1204299297] [2022-12-13 14:12:53,643 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 14:12:53,644 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 14:12:53,647 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 14:12:53,647 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 14:12:53,648 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 14:12:53,650 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 14:12:53,710 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 14:12:53,710 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 14:12:53,710 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 14:12:53,711 INFO L87 Difference]: Start difference. First operand 11454 states and 15389 transitions. cyclomatic complexity: 3941 Second operand has 3 states, 3 states have (on average 21.333333333333332) internal successors, (64), 3 states have internal predecessors, (64), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 14:12:53,734 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 14:12:53,735 INFO L93 Difference]: Finished difference Result 11394 states and 15309 transitions. [2022-12-13 14:12:53,735 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 11394 states and 15309 transitions. [2022-12-13 14:12:53,763 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 11264 [2022-12-13 14:12:53,781 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 11394 states to 11394 states and 15309 transitions. [2022-12-13 14:12:53,781 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 11394 [2022-12-13 14:12:53,786 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11394 [2022-12-13 14:12:53,786 INFO L73 IsDeterministic]: Start isDeterministic. Operand 11394 states and 15309 transitions. [2022-12-13 14:12:53,793 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 14:12:53,793 INFO L218 hiAutomatonCegarLoop]: Abstraction has 11394 states and 15309 transitions. [2022-12-13 14:12:53,799 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11394 states and 15309 transitions. [2022-12-13 14:12:53,923 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11394 to 11394. [2022-12-13 14:12:53,931 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 11394 states, 11394 states have (on average 1.3436018957345972) internal successors, (15309), 11393 states have internal predecessors, (15309), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 14:12:53,947 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11394 states to 11394 states and 15309 transitions. [2022-12-13 14:12:53,947 INFO L240 hiAutomatonCegarLoop]: Abstraction has 11394 states and 15309 transitions. [2022-12-13 14:12:53,948 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 14:12:53,948 INFO L428 stractBuchiCegarLoop]: Abstraction has 11394 states and 15309 transitions. [2022-12-13 14:12:53,948 INFO L335 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2022-12-13 14:12:53,948 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 11394 states and 15309 transitions. [2022-12-13 14:12:53,974 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 11264 [2022-12-13 14:12:53,975 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 14:12:53,975 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 14:12:53,975 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 14:12:53,975 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 14:12:53,976 INFO L748 eck$LassoCheckResult]: Stem: 156062#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 156063#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 156167#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 156168#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 155910#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 155911#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 156186#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 156132#L375-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 156133#L380-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 156160#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 156144#L526 assume !(0 == ~M_E~0); 156145#L526-2 assume !(0 == ~T1_E~0); 156188#L531-1 assume !(0 == ~T2_E~0); 156128#L536-1 assume !(0 == ~T3_E~0); 156129#L541-1 assume !(0 == ~T4_E~0); 156123#L546-1 assume !(0 == ~E_M~0); 156124#L551-1 assume !(0 == ~E_1~0); 156100#L556-1 assume !(0 == ~E_2~0); 156101#L561-1 assume !(0 == ~E_3~0); 156110#L566-1 assume !(0 == ~E_4~0); 156111#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 156105#L262 assume !(1 == ~m_pc~0); 156106#L262-2 is_master_triggered_~__retres1~0#1 := 0; 156303#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 156031#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 156032#L649 assume !(0 != activate_threads_~tmp~1#1); 156302#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 156040#L281 assume !(1 == ~t1_pc~0); 156041#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 155959#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 155874#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 155875#L657 assume !(0 != activate_threads_~tmp___0~0#1); 156019#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 156113#L300 assume !(1 == ~t2_pc~0); 156114#L300-2 is_transmit2_triggered_~__retres1~2#1 := 0; 156221#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 156171#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 156136#L665 assume !(0 != activate_threads_~tmp___1~0#1); 155887#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 155888#L319 assume !(1 == ~t3_pc~0); 155843#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 155844#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 155830#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 155831#L673 assume !(0 != activate_threads_~tmp___2~0#1); 155864#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 155865#L338 assume !(1 == ~t4_pc~0); 155935#L338-2 is_transmit4_triggered_~__retres1~4#1 := 0; 155936#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 155942#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 155943#L681 assume !(0 != activate_threads_~tmp___3~0#1); 155812#L681-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 155813#L584 assume !(1 == ~M_E~0); 156016#L584-2 assume !(1 == ~T1_E~0); 155975#L589-1 assume !(1 == ~T2_E~0); 155976#L594-1 assume !(1 == ~T3_E~0); 156068#L599-1 assume !(1 == ~T4_E~0); 155842#L604-1 assume !(1 == ~E_M~0); 155828#L609-1 assume !(1 == ~E_1~0); 155829#L614-1 assume !(1 == ~E_2~0); 155950#L619-1 assume !(1 == ~E_3~0); 156033#L624-1 assume !(1 == ~E_4~0); 156134#L629-1 assume { :end_inline_reset_delta_events } true; 156317#L815-2 assume !false; 157781#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 157779#L501 [2022-12-13 14:12:53,976 INFO L750 eck$LassoCheckResult]: Loop: 157779#L501 assume !false; 157777#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 157593#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 157595#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 157885#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 157883#L440 assume 0 != eval_~tmp~0#1; 157851#L440-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 157852#L448 assume !(0 != eval_~tmp_ndt_1~0#1); 157576#L445 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 157573#L462 assume !(0 != eval_~tmp_ndt_2~0#1); 157571#L459 assume !(0 == ~t2_st~0); 157569#L473 assume !(0 == ~t3_st~0); 157784#L487 assume !(0 == ~t4_st~0); 157779#L501 [2022-12-13 14:12:53,976 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 14:12:53,976 INFO L85 PathProgramCache]: Analyzing trace with hash 39728939, now seen corresponding path program 2 times [2022-12-13 14:12:53,976 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 14:12:53,976 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1078646608] [2022-12-13 14:12:53,977 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 14:12:53,977 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 14:12:53,986 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 14:12:53,987 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 14:12:53,991 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 14:12:53,997 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 14:12:53,997 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 14:12:53,997 INFO L85 PathProgramCache]: Analyzing trace with hash -1811665542, now seen corresponding path program 1 times [2022-12-13 14:12:53,997 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 14:12:53,997 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1671667799] [2022-12-13 14:12:53,997 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 14:12:53,998 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 14:12:54,000 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 14:12:54,000 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 14:12:54,001 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 14:12:54,002 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 14:12:54,002 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 14:12:54,002 INFO L85 PathProgramCache]: Analyzing trace with hash -1894094192, now seen corresponding path program 1 times [2022-12-13 14:12:54,002 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 14:12:54,002 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [944935250] [2022-12-13 14:12:54,002 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 14:12:54,003 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 14:12:54,010 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 14:12:54,027 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 14:12:54,027 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 14:12:54,027 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [944935250] [2022-12-13 14:12:54,027 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [944935250] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 14:12:54,027 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 14:12:54,028 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 14:12:54,028 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [541027182] [2022-12-13 14:12:54,028 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 14:12:54,099 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 14:12:54,099 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 14:12:54,099 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 14:12:54,099 INFO L87 Difference]: Start difference. First operand 11394 states and 15309 transitions. cyclomatic complexity: 3921 Second operand has 3 states, 3 states have (on average 25.666666666666668) internal successors, (77), 3 states have internal predecessors, (77), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 14:12:54,164 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 14:12:54,164 INFO L93 Difference]: Finished difference Result 21066 states and 28145 transitions. [2022-12-13 14:12:54,164 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 21066 states and 28145 transitions. [2022-12-13 14:12:54,218 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 20872 [2022-12-13 14:12:54,252 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 21066 states to 21066 states and 28145 transitions. [2022-12-13 14:12:54,252 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 21066 [2022-12-13 14:12:54,262 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 21066 [2022-12-13 14:12:54,262 INFO L73 IsDeterministic]: Start isDeterministic. Operand 21066 states and 28145 transitions. [2022-12-13 14:12:54,270 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 14:12:54,270 INFO L218 hiAutomatonCegarLoop]: Abstraction has 21066 states and 28145 transitions. [2022-12-13 14:12:54,280 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 21066 states and 28145 transitions. [2022-12-13 14:12:54,382 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 21066 to 20576. [2022-12-13 14:12:54,397 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 20576 states, 20576 states have (on average 1.3372375583203733) internal successors, (27515), 20575 states have internal predecessors, (27515), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 14:12:54,430 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 20576 states to 20576 states and 27515 transitions. [2022-12-13 14:12:54,430 INFO L240 hiAutomatonCegarLoop]: Abstraction has 20576 states and 27515 transitions. [2022-12-13 14:12:54,431 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 14:12:54,431 INFO L428 stractBuchiCegarLoop]: Abstraction has 20576 states and 27515 transitions. [2022-12-13 14:12:54,431 INFO L335 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2022-12-13 14:12:54,431 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 20576 states and 27515 transitions. [2022-12-13 14:12:54,499 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 20382 [2022-12-13 14:12:54,499 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 14:12:54,499 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 14:12:54,500 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 14:12:54,500 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 14:12:54,500 INFO L748 eck$LassoCheckResult]: Stem: 188534#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 188535#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 188639#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 188640#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 188378#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 188379#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 188654#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 188602#L375-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 188603#L380-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 188633#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 188614#L526 assume !(0 == ~M_E~0); 188615#L526-2 assume !(0 == ~T1_E~0); 188656#L531-1 assume !(0 == ~T2_E~0); 188598#L536-1 assume !(0 == ~T3_E~0); 188599#L541-1 assume !(0 == ~T4_E~0); 188593#L546-1 assume !(0 == ~E_M~0); 188594#L551-1 assume !(0 == ~E_1~0); 188570#L556-1 assume !(0 == ~E_2~0); 188571#L561-1 assume !(0 == ~E_3~0); 188581#L566-1 assume !(0 == ~E_4~0); 188582#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 188575#L262 assume !(1 == ~m_pc~0); 188576#L262-2 is_master_triggered_~__retres1~0#1 := 0; 188799#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 188504#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 188505#L649 assume !(0 != activate_threads_~tmp~1#1); 188797#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 188513#L281 assume !(1 == ~t1_pc~0); 188514#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 188431#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 188343#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 188344#L657 assume !(0 != activate_threads_~tmp___0~0#1); 188486#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 188584#L300 assume !(1 == ~t2_pc~0); 188585#L300-2 is_transmit2_triggered_~__retres1~2#1 := 0; 188700#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 188643#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 188607#L665 assume !(0 != activate_threads_~tmp___1~0#1); 188356#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 188357#L319 assume !(1 == ~t3_pc~0); 188311#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 188312#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 188298#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 188299#L673 assume !(0 != activate_threads_~tmp___2~0#1); 188333#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 188334#L338 assume !(1 == ~t4_pc~0); 188404#L338-2 is_transmit4_triggered_~__retres1~4#1 := 0; 188405#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 188411#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 188412#L681 assume !(0 != activate_threads_~tmp___3~0#1); 188280#L681-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 188281#L584 assume !(1 == ~M_E~0); 188483#L584-2 assume !(1 == ~T1_E~0); 188445#L589-1 assume !(1 == ~T2_E~0); 188446#L594-1 assume !(1 == ~T3_E~0); 188538#L599-1 assume !(1 == ~T4_E~0); 188310#L604-1 assume !(1 == ~E_M~0); 188296#L609-1 assume !(1 == ~E_1~0); 188297#L614-1 assume !(1 == ~E_2~0); 188422#L619-1 assume !(1 == ~E_3~0); 188506#L624-1 assume !(1 == ~E_4~0); 188604#L629-1 assume { :end_inline_reset_delta_events } true; 188806#L815-2 assume !false; 193153#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 193150#L501 [2022-12-13 14:12:54,500 INFO L750 eck$LassoCheckResult]: Loop: 193150#L501 assume !false; 193145#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 193141#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 193138#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 193134#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 193130#L440 assume 0 != eval_~tmp~0#1; 193124#L440-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 193119#L448 assume !(0 != eval_~tmp_ndt_1~0#1); 193116#L445 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 192560#L462 assume !(0 != eval_~tmp_ndt_2~0#1); 193113#L459 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 191692#L476 assume !(0 != eval_~tmp_ndt_3~0#1); 193159#L473 assume !(0 == ~t3_st~0); 193156#L487 assume !(0 == ~t4_st~0); 193150#L501 [2022-12-13 14:12:54,500 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 14:12:54,501 INFO L85 PathProgramCache]: Analyzing trace with hash 39728939, now seen corresponding path program 3 times [2022-12-13 14:12:54,501 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 14:12:54,501 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1290105989] [2022-12-13 14:12:54,501 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 14:12:54,501 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 14:12:54,509 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 14:12:54,510 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 14:12:54,515 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 14:12:54,524 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 14:12:54,525 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 14:12:54,525 INFO L85 PathProgramCache]: Analyzing trace with hash -331803221, now seen corresponding path program 1 times [2022-12-13 14:12:54,525 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 14:12:54,525 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2020550122] [2022-12-13 14:12:54,525 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 14:12:54,525 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 14:12:54,528 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 14:12:54,529 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 14:12:54,531 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 14:12:54,532 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 14:12:54,532 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 14:12:54,532 INFO L85 PathProgramCache]: Analyzing trace with hash 1407875925, now seen corresponding path program 1 times [2022-12-13 14:12:54,533 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 14:12:54,533 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [532960610] [2022-12-13 14:12:54,533 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 14:12:54,533 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 14:12:54,541 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 14:12:54,565 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 14:12:54,565 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 14:12:54,565 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [532960610] [2022-12-13 14:12:54,565 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [532960610] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 14:12:54,565 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 14:12:54,566 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 14:12:54,566 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1505504597] [2022-12-13 14:12:54,566 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 14:12:54,649 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 14:12:54,649 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 14:12:54,650 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 14:12:54,650 INFO L87 Difference]: Start difference. First operand 20576 states and 27515 transitions. cyclomatic complexity: 6945 Second operand has 3 states, 3 states have (on average 26.0) internal successors, (78), 3 states have internal predecessors, (78), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 14:12:54,761 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 14:12:54,761 INFO L93 Difference]: Finished difference Result 36290 states and 48365 transitions. [2022-12-13 14:12:54,762 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 36290 states and 48365 transitions. [2022-12-13 14:12:54,885 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 35968 [2022-12-13 14:12:54,948 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 36290 states to 36290 states and 48365 transitions. [2022-12-13 14:12:54,948 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 36290 [2022-12-13 14:12:54,968 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 36290 [2022-12-13 14:12:54,968 INFO L73 IsDeterministic]: Start isDeterministic. Operand 36290 states and 48365 transitions. [2022-12-13 14:12:54,983 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 14:12:54,983 INFO L218 hiAutomatonCegarLoop]: Abstraction has 36290 states and 48365 transitions. [2022-12-13 14:12:55,000 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 36290 states and 48365 transitions. [2022-12-13 14:12:55,266 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 36290 to 35114. [2022-12-13 14:12:55,287 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 35114 states, 35114 states have (on average 1.3375007119667368) internal successors, (46965), 35113 states have internal predecessors, (46965), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 14:12:55,341 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 35114 states to 35114 states and 46965 transitions. [2022-12-13 14:12:55,342 INFO L240 hiAutomatonCegarLoop]: Abstraction has 35114 states and 46965 transitions. [2022-12-13 14:12:55,343 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 14:12:55,343 INFO L428 stractBuchiCegarLoop]: Abstraction has 35114 states and 46965 transitions. [2022-12-13 14:12:55,343 INFO L335 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2022-12-13 14:12:55,343 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 35114 states and 46965 transitions. [2022-12-13 14:12:55,441 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 34792 [2022-12-13 14:12:55,441 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 14:12:55,441 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 14:12:55,442 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 14:12:55,442 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 14:12:55,443 INFO L748 eck$LassoCheckResult]: Stem: 245407#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 245408#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 245513#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 245514#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 245252#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 245253#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 245531#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 245477#L375-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 245478#L380-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 245504#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 245487#L526 assume !(0 == ~M_E~0); 245488#L526-2 assume !(0 == ~T1_E~0); 245533#L531-1 assume !(0 == ~T2_E~0); 245473#L536-1 assume !(0 == ~T3_E~0); 245474#L541-1 assume !(0 == ~T4_E~0); 245468#L546-1 assume !(0 == ~E_M~0); 245469#L551-1 assume !(0 == ~E_1~0); 245443#L556-1 assume !(0 == ~E_2~0); 245444#L561-1 assume !(0 == ~E_3~0); 245453#L566-1 assume !(0 == ~E_4~0); 245454#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 245448#L262 assume !(1 == ~m_pc~0); 245449#L262-2 is_master_triggered_~__retres1~0#1 := 0; 245675#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 245377#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 245378#L649 assume !(0 != activate_threads_~tmp~1#1); 245672#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 245387#L281 assume !(1 == ~t1_pc~0); 245388#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 245303#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 245216#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 245217#L657 assume !(0 != activate_threads_~tmp___0~0#1); 245363#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 245457#L300 assume !(1 == ~t2_pc~0); 245458#L300-2 is_transmit2_triggered_~__retres1~2#1 := 0; 245576#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 245517#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 245481#L665 assume !(0 != activate_threads_~tmp___1~0#1); 245229#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 245230#L319 assume !(1 == ~t3_pc~0); 245185#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 245186#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 245172#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 245173#L673 assume !(0 != activate_threads_~tmp___2~0#1); 245206#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 245207#L338 assume !(1 == ~t4_pc~0); 245278#L338-2 is_transmit4_triggered_~__retres1~4#1 := 0; 245279#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 245284#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 245285#L681 assume !(0 != activate_threads_~tmp___3~0#1); 245154#L681-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 245155#L584 assume !(1 == ~M_E~0); 245360#L584-2 assume !(1 == ~T1_E~0); 245317#L589-1 assume !(1 == ~T2_E~0); 245318#L594-1 assume !(1 == ~T3_E~0); 245411#L599-1 assume !(1 == ~T4_E~0); 245184#L604-1 assume !(1 == ~E_M~0); 245170#L609-1 assume !(1 == ~E_1~0); 245171#L614-1 assume !(1 == ~E_2~0); 245294#L619-1 assume !(1 == ~E_3~0); 245379#L624-1 assume !(1 == ~E_4~0); 245479#L629-1 assume { :end_inline_reset_delta_events } true; 245686#L815-2 assume !false; 254441#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 254438#L501 [2022-12-13 14:12:55,443 INFO L750 eck$LassoCheckResult]: Loop: 254438#L501 assume !false; 254437#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 254435#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 254434#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 254431#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 254430#L440 assume 0 != eval_~tmp~0#1; 254428#L440-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 254349#L448 assume !(0 != eval_~tmp_ndt_1~0#1); 253279#L445 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 253276#L462 assume !(0 != eval_~tmp_ndt_2~0#1); 253273#L459 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 250614#L476 assume !(0 != eval_~tmp_ndt_3~0#1); 253270#L473 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; 254303#L490 assume !(0 != eval_~tmp_ndt_4~0#1); 254444#L487 assume !(0 == ~t4_st~0); 254438#L501 [2022-12-13 14:12:55,444 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 14:12:55,444 INFO L85 PathProgramCache]: Analyzing trace with hash 39728939, now seen corresponding path program 4 times [2022-12-13 14:12:55,444 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 14:12:55,444 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1042596329] [2022-12-13 14:12:55,444 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 14:12:55,444 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 14:12:55,454 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 14:12:55,455 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 14:12:55,460 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 14:12:55,470 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 14:12:55,470 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 14:12:55,470 INFO L85 PathProgramCache]: Analyzing trace with hash -1696117078, now seen corresponding path program 1 times [2022-12-13 14:12:55,470 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 14:12:55,471 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2142067743] [2022-12-13 14:12:55,471 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 14:12:55,471 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 14:12:55,475 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 14:12:55,475 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 14:12:55,477 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 14:12:55,478 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 14:12:55,478 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 14:12:55,479 INFO L85 PathProgramCache]: Analyzing trace with hash 694328896, now seen corresponding path program 1 times [2022-12-13 14:12:55,479 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 14:12:55,479 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1621464260] [2022-12-13 14:12:55,479 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 14:12:55,479 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 14:12:55,487 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 14:12:55,508 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 14:12:55,508 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 14:12:55,508 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1621464260] [2022-12-13 14:12:55,509 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1621464260] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 14:12:55,509 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 14:12:55,509 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-12-13 14:12:55,509 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [624994232] [2022-12-13 14:12:55,509 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 14:12:55,607 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 14:12:55,607 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 14:12:55,607 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 14:12:55,607 INFO L87 Difference]: Start difference. First operand 35114 states and 46965 transitions. cyclomatic complexity: 11857 Second operand has 3 states, 2 states have (on average 39.5) internal successors, (79), 3 states have internal predecessors, (79), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 14:12:55,747 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 14:12:55,747 INFO L93 Difference]: Finished difference Result 39904 states and 53203 transitions. [2022-12-13 14:12:55,747 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 39904 states and 53203 transitions. [2022-12-13 14:12:55,899 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 39662 [2022-12-13 14:12:55,986 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 39904 states to 39904 states and 53203 transitions. [2022-12-13 14:12:55,986 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 39904 [2022-12-13 14:12:56,005 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 39904 [2022-12-13 14:12:56,005 INFO L73 IsDeterministic]: Start isDeterministic. Operand 39904 states and 53203 transitions. [2022-12-13 14:12:56,025 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 14:12:56,026 INFO L218 hiAutomatonCegarLoop]: Abstraction has 39904 states and 53203 transitions. [2022-12-13 14:12:56,046 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 39904 states and 53203 transitions. [2022-12-13 14:12:56,334 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 39904 to 39456. [2022-12-13 14:12:56,357 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 39456 states, 39456 states have (on average 1.33705900243309) internal successors, (52755), 39455 states have internal predecessors, (52755), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 14:12:56,403 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 39456 states to 39456 states and 52755 transitions. [2022-12-13 14:12:56,403 INFO L240 hiAutomatonCegarLoop]: Abstraction has 39456 states and 52755 transitions. [2022-12-13 14:12:56,404 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 14:12:56,404 INFO L428 stractBuchiCegarLoop]: Abstraction has 39456 states and 52755 transitions. [2022-12-13 14:12:56,404 INFO L335 stractBuchiCegarLoop]: ======== Iteration 23 ============ [2022-12-13 14:12:56,404 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 39456 states and 52755 transitions. [2022-12-13 14:12:56,494 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 39214 [2022-12-13 14:12:56,494 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 14:12:56,494 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 14:12:56,494 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 14:12:56,495 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 14:12:56,495 INFO L748 eck$LassoCheckResult]: Stem: 320432#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 320433#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 320546#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 320547#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 320277#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 320278#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 320564#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 320504#L375-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 320505#L380-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 320538#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 320515#L526 assume !(0 == ~M_E~0); 320516#L526-2 assume !(0 == ~T1_E~0); 320567#L531-1 assume !(0 == ~T2_E~0); 320500#L536-1 assume !(0 == ~T3_E~0); 320501#L541-1 assume !(0 == ~T4_E~0); 320496#L546-1 assume !(0 == ~E_M~0); 320497#L551-1 assume !(0 == ~E_1~0); 320470#L556-1 assume !(0 == ~E_2~0); 320471#L561-1 assume !(0 == ~E_3~0); 320480#L566-1 assume !(0 == ~E_4~0); 320481#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 320475#L262 assume !(1 == ~m_pc~0); 320476#L262-2 is_master_triggered_~__retres1~0#1 := 0; 320722#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 320401#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 320402#L649 assume !(0 != activate_threads_~tmp~1#1); 320719#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 320411#L281 assume !(1 == ~t1_pc~0); 320412#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 320327#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 320243#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 320244#L657 assume !(0 != activate_threads_~tmp___0~0#1); 320385#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 320484#L300 assume !(1 == ~t2_pc~0); 320485#L300-2 is_transmit2_triggered_~__retres1~2#1 := 0; 320613#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 320550#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 320508#L665 assume !(0 != activate_threads_~tmp___1~0#1); 320256#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 320257#L319 assume !(1 == ~t3_pc~0); 320211#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 320212#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 320198#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 320199#L673 assume !(0 != activate_threads_~tmp___2~0#1); 320232#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 320233#L338 assume !(1 == ~t4_pc~0); 320303#L338-2 is_transmit4_triggered_~__retres1~4#1 := 0; 320304#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 320309#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 320310#L681 assume !(0 != activate_threads_~tmp___3~0#1); 320180#L681-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 320181#L584 assume !(1 == ~M_E~0); 320382#L584-2 assume !(1 == ~T1_E~0); 320341#L589-1 assume !(1 == ~T2_E~0); 320342#L594-1 assume !(1 == ~T3_E~0); 320436#L599-1 assume !(1 == ~T4_E~0); 320210#L604-1 assume !(1 == ~E_M~0); 320196#L609-1 assume !(1 == ~E_1~0); 320197#L614-1 assume !(1 == ~E_2~0); 320318#L619-1 assume !(1 == ~E_3~0); 320403#L624-1 assume !(1 == ~E_4~0); 320506#L629-1 assume { :end_inline_reset_delta_events } true; 320737#L815-2 assume !false; 330481#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 330478#L501 [2022-12-13 14:12:56,495 INFO L750 eck$LassoCheckResult]: Loop: 330478#L501 assume !false; 330474#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 330470#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 330467#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 330461#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 330455#L440 assume 0 != eval_~tmp~0#1; 330449#L440-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 330440#L448 assume !(0 != eval_~tmp_ndt_1~0#1); 330434#L445 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 330320#L462 assume !(0 != eval_~tmp_ndt_2~0#1); 330391#L459 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 330400#L476 assume !(0 != eval_~tmp_ndt_3~0#1); 330495#L473 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; 330491#L490 assume !(0 != eval_~tmp_ndt_4~0#1); 330487#L487 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0#1;eval_~tmp_ndt_5~0#1 := eval_#t~nondet11#1;havoc eval_#t~nondet11#1; 330482#L504 assume !(0 != eval_~tmp_ndt_5~0#1); 330478#L501 [2022-12-13 14:12:56,495 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 14:12:56,496 INFO L85 PathProgramCache]: Analyzing trace with hash 39728939, now seen corresponding path program 5 times [2022-12-13 14:12:56,496 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 14:12:56,496 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [449661945] [2022-12-13 14:12:56,496 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 14:12:56,496 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 14:12:56,506 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 14:12:56,506 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 14:12:56,511 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 14:12:56,522 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 14:12:56,523 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 14:12:56,523 INFO L85 PathProgramCache]: Analyzing trace with hash -1040025477, now seen corresponding path program 1 times [2022-12-13 14:12:56,523 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 14:12:56,523 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [568767572] [2022-12-13 14:12:56,523 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 14:12:56,523 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 14:12:56,527 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 14:12:56,527 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 14:12:56,529 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 14:12:56,530 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 14:12:56,531 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 14:12:56,531 INFO L85 PathProgramCache]: Analyzing trace with hash 49355685, now seen corresponding path program 1 times [2022-12-13 14:12:56,531 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 14:12:56,531 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [853549539] [2022-12-13 14:12:56,531 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 14:12:56,531 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 14:12:56,539 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 14:12:56,540 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 14:12:56,543 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 14:12:56,551 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 14:12:57,517 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 14:12:57,518 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 14:12:57,531 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 14:12:57,621 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 13.12 02:12:57 BoogieIcfgContainer [2022-12-13 14:12:57,621 INFO L132 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2022-12-13 14:12:57,622 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2022-12-13 14:12:57,622 INFO L271 PluginConnector]: Initializing Witness Printer... [2022-12-13 14:12:57,622 INFO L275 PluginConnector]: Witness Printer initialized [2022-12-13 14:12:57,622 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.12 02:12:48" (3/4) ... [2022-12-13 14:12:57,624 INFO L134 WitnessPrinter]: Generating witness for non-termination counterexample [2022-12-13 14:12:57,742 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4779227a-506f-4eeb-bef1-40db864f4417/bin/uautomizer-uyxdKDjOR8/witness.graphml [2022-12-13 14:12:57,742 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2022-12-13 14:12:57,742 INFO L158 Benchmark]: Toolchain (without parser) took 10132.10ms. Allocated memory was 115.3MB in the beginning and 1.3GB in the end (delta: 1.2GB). Free memory was 82.0MB in the beginning and 797.2MB in the end (delta: -715.2MB). Peak memory consumption was 827.7MB. Max. memory is 16.1GB. [2022-12-13 14:12:57,742 INFO L158 Benchmark]: CDTParser took 0.18ms. Allocated memory is still 115.3MB. Free memory is still 86.7MB. There was no memory consumed. Max. memory is 16.1GB. [2022-12-13 14:12:57,743 INFO L158 Benchmark]: CACSL2BoogieTranslator took 235.33ms. Allocated memory is still 115.3MB. Free memory was 82.0MB in the beginning and 66.4MB in the end (delta: 15.6MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB. [2022-12-13 14:12:57,743 INFO L158 Benchmark]: Boogie Procedure Inliner took 46.30ms. Allocated memory is still 115.3MB. Free memory was 66.4MB in the beginning and 62.2MB in the end (delta: 4.2MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2022-12-13 14:12:57,743 INFO L158 Benchmark]: Boogie Preprocessor took 47.11ms. Allocated memory is still 115.3MB. Free memory was 62.2MB in the beginning and 58.4MB in the end (delta: 3.8MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. [2022-12-13 14:12:57,743 INFO L158 Benchmark]: RCFGBuilder took 763.79ms. Allocated memory was 115.3MB in the beginning and 140.5MB in the end (delta: 25.2MB). Free memory was 58.4MB in the beginning and 80.2MB in the end (delta: -21.8MB). Peak memory consumption was 24.3MB. Max. memory is 16.1GB. [2022-12-13 14:12:57,743 INFO L158 Benchmark]: BuchiAutomizer took 8915.65ms. Allocated memory was 140.5MB in the beginning and 1.3GB in the end (delta: 1.1GB). Free memory was 79.6MB in the beginning and 484.8MB in the end (delta: -405.2MB). Peak memory consumption was 728.9MB. Max. memory is 16.1GB. [2022-12-13 14:12:57,744 INFO L158 Benchmark]: Witness Printer took 120.18ms. Allocated memory is still 1.3GB. Free memory was 484.8MB in the beginning and 797.2MB in the end (delta: -312.5MB). Peak memory consumption was 68.2MB. Max. memory is 16.1GB. [2022-12-13 14:12:57,745 INFO L339 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.18ms. Allocated memory is still 115.3MB. Free memory is still 86.7MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 235.33ms. Allocated memory is still 115.3MB. Free memory was 82.0MB in the beginning and 66.4MB in the end (delta: 15.6MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 46.30ms. Allocated memory is still 115.3MB. Free memory was 66.4MB in the beginning and 62.2MB in the end (delta: 4.2MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * Boogie Preprocessor took 47.11ms. Allocated memory is still 115.3MB. Free memory was 62.2MB in the beginning and 58.4MB in the end (delta: 3.8MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. * RCFGBuilder took 763.79ms. Allocated memory was 115.3MB in the beginning and 140.5MB in the end (delta: 25.2MB). Free memory was 58.4MB in the beginning and 80.2MB in the end (delta: -21.8MB). Peak memory consumption was 24.3MB. Max. memory is 16.1GB. * BuchiAutomizer took 8915.65ms. Allocated memory was 140.5MB in the beginning and 1.3GB in the end (delta: 1.1GB). Free memory was 79.6MB in the beginning and 484.8MB in the end (delta: -405.2MB). Peak memory consumption was 728.9MB. Max. memory is 16.1GB. * Witness Printer took 120.18ms. Allocated memory is still 1.3GB. Free memory was 484.8MB in the beginning and 797.2MB in the end (delta: -312.5MB). Peak memory consumption was 68.2MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 22 terminating modules (22 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.22 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 39456 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 8.8s and 23 iterations. TraceHistogramMax:1. Analysis of lassos took 3.2s. Construction of modules took 0.5s. Büchi inclusion checks took 4.4s. Highest rank in rank-based complementation 0. Minimization of det autom 22. Minimization of nondet autom 0. Automata minimization 1.9s AutomataMinimizationTime, 22 MinimizatonAttempts, 27415 StatesRemovedByMinimization, 15 NontrivialMinimizations. Non-live state removal took 1.1s Buchi closure took 0.1s. Biggest automaton had -1 states and ocurred in iteration -1. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 19148 SdHoareTripleChecker+Valid, 0.7s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 19148 mSDsluCounter, 32259 SdHoareTripleChecker+Invalid, 0.5s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 16630 mSDsCounter, 265 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 715 IncrementalHoareTripleChecker+Invalid, 980 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 265 mSolverCounterUnsat, 15629 mSDtfsCounter, 715 mSolverCounterSat, 0.1s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI4 SFLT0 conc4 concLT0 SILN1 SILU0 SILI13 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s InitialAbstractionConstructionTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - LassoShapedNonTerminationArgument [Line: 435]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite program execution. Stem: [L24] int m_pc = 0; [L25] int t1_pc = 0; [L26] int t2_pc = 0; [L27] int t3_pc = 0; [L28] int t4_pc = 0; [L29] int m_st ; [L30] int t1_st ; [L31] int t2_st ; [L32] int t3_st ; [L33] int t4_st ; [L34] int m_i ; [L35] int t1_i ; [L36] int t2_i ; [L37] int t3_i ; [L38] int t4_i ; [L39] int M_E = 2; [L40] int T1_E = 2; [L41] int T2_E = 2; [L42] int T3_E = 2; [L43] int T4_E = 2; [L44] int E_M = 2; [L45] int E_1 = 2; [L46] int E_2 = 2; [L47] int E_3 = 2; [L48] int E_4 = 2; [L55] int token ; [L57] int local ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=0, m_pc=0, m_st=0, T1_E=2, t1_i=0, t1_pc=0, t1_st=0, T2_E=2, t2_i=0, t2_pc=0, t2_st=0, T3_E=2, t3_i=0, t3_pc=0, t3_st=0, T4_E=2, t4_i=0, t4_pc=0, t4_st=0, token=0] [L860] int __retres1 ; [L864] CALL init_model() [L772] m_i = 1 [L773] t1_i = 1 [L774] t2_i = 1 [L775] t3_i = 1 [L776] t4_i = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L864] RET init_model() [L865] CALL start_simulation() [L801] int kernel_st ; [L802] int tmp ; [L803] int tmp___0 ; [L807] kernel_st = 0 [L808] FCALL update_channels() [L809] CALL init_threads() [L365] COND TRUE m_i == 1 [L366] m_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L370] COND TRUE t1_i == 1 [L371] t1_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L375] COND TRUE t2_i == 1 [L376] t2_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L380] COND TRUE t3_i == 1 [L381] t3_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L385] COND TRUE t4_i == 1 [L386] t4_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L809] RET init_threads() [L810] CALL fire_delta_events() [L526] COND FALSE !(M_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L531] COND FALSE !(T1_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L536] COND FALSE !(T2_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L541] COND FALSE !(T3_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L546] COND FALSE !(T4_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L551] COND FALSE !(E_M == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L556] COND FALSE !(E_1 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L561] COND FALSE !(E_2 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L566] COND FALSE !(E_3 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L571] COND FALSE !(E_4 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L810] RET fire_delta_events() [L811] CALL activate_threads() [L639] int tmp ; [L640] int tmp___0 ; [L641] int tmp___1 ; [L642] int tmp___2 ; [L643] int tmp___3 ; [L647] CALL, EXPR is_master_triggered() [L259] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L262] COND FALSE !(m_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L272] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L274] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L647] RET, EXPR is_master_triggered() [L647] tmp = is_master_triggered() [L649] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, tmp=0, token=0] [L655] CALL, EXPR is_transmit1_triggered() [L278] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L281] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L291] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L293] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L655] RET, EXPR is_transmit1_triggered() [L655] tmp___0 = is_transmit1_triggered() [L657] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, tmp=0, tmp___0=0, token=0] [L663] CALL, EXPR is_transmit2_triggered() [L297] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L300] COND FALSE !(t2_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L310] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L312] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L663] RET, EXPR is_transmit2_triggered() [L663] tmp___1 = is_transmit2_triggered() [L665] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, tmp=0, tmp___0=0, tmp___1=0, token=0] [L671] CALL, EXPR is_transmit3_triggered() [L316] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L319] COND FALSE !(t3_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L329] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L331] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L671] RET, EXPR is_transmit3_triggered() [L671] tmp___2 = is_transmit3_triggered() [L673] COND FALSE !(\read(tmp___2)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, token=0] [L679] CALL, EXPR is_transmit4_triggered() [L335] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L338] COND FALSE !(t4_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L348] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L350] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L679] RET, EXPR is_transmit4_triggered() [L679] tmp___3 = is_transmit4_triggered() [L681] COND FALSE !(\read(tmp___3)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0, token=0] [L811] RET activate_threads() [L812] CALL reset_delta_events() [L584] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L589] COND FALSE !(T1_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L594] COND FALSE !(T2_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L599] COND FALSE !(T3_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L604] COND FALSE !(T4_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L609] COND FALSE !(E_M == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L614] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L619] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L624] COND FALSE !(E_3 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L629] COND FALSE !(E_4 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L812] RET reset_delta_events() [L815] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, kernel_st=0, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L818] kernel_st = 1 [L819] CALL eval() [L431] int tmp ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] Loop: [L435] COND TRUE 1 [L438] CALL, EXPR exists_runnable_thread() [L395] int __retres1 ; [L398] COND TRUE m_st == 0 [L399] __retres1 = 1 [L426] return (__retres1); [L438] RET, EXPR exists_runnable_thread() [L438] tmp = exists_runnable_thread() [L440] COND TRUE \read(tmp) [L445] COND TRUE m_st == 0 [L446] int tmp_ndt_1; [L447] tmp_ndt_1 = __VERIFIER_nondet_int() [L448] COND FALSE !(\read(tmp_ndt_1)) [L459] COND TRUE t1_st == 0 [L460] int tmp_ndt_2; [L461] tmp_ndt_2 = __VERIFIER_nondet_int() [L462] COND FALSE !(\read(tmp_ndt_2)) [L473] COND TRUE t2_st == 0 [L474] int tmp_ndt_3; [L475] tmp_ndt_3 = __VERIFIER_nondet_int() [L476] COND FALSE !(\read(tmp_ndt_3)) [L487] COND TRUE t3_st == 0 [L488] int tmp_ndt_4; [L489] tmp_ndt_4 = __VERIFIER_nondet_int() [L490] COND FALSE !(\read(tmp_ndt_4)) [L501] COND TRUE t4_st == 0 [L502] int tmp_ndt_5; [L503] tmp_ndt_5 = __VERIFIER_nondet_int() [L504] COND FALSE !(\read(tmp_ndt_5)) End of lasso representation. - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 435]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L24] int m_pc = 0; [L25] int t1_pc = 0; [L26] int t2_pc = 0; [L27] int t3_pc = 0; [L28] int t4_pc = 0; [L29] int m_st ; [L30] int t1_st ; [L31] int t2_st ; [L32] int t3_st ; [L33] int t4_st ; [L34] int m_i ; [L35] int t1_i ; [L36] int t2_i ; [L37] int t3_i ; [L38] int t4_i ; [L39] int M_E = 2; [L40] int T1_E = 2; [L41] int T2_E = 2; [L42] int T3_E = 2; [L43] int T4_E = 2; [L44] int E_M = 2; [L45] int E_1 = 2; [L46] int E_2 = 2; [L47] int E_3 = 2; [L48] int E_4 = 2; [L55] int token ; [L57] int local ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=0, m_pc=0, m_st=0, T1_E=2, t1_i=0, t1_pc=0, t1_st=0, T2_E=2, t2_i=0, t2_pc=0, t2_st=0, T3_E=2, t3_i=0, t3_pc=0, t3_st=0, T4_E=2, t4_i=0, t4_pc=0, t4_st=0, token=0] [L860] int __retres1 ; [L864] CALL init_model() [L772] m_i = 1 [L773] t1_i = 1 [L774] t2_i = 1 [L775] t3_i = 1 [L776] t4_i = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L864] RET init_model() [L865] CALL start_simulation() [L801] int kernel_st ; [L802] int tmp ; [L803] int tmp___0 ; [L807] kernel_st = 0 [L808] FCALL update_channels() [L809] CALL init_threads() [L365] COND TRUE m_i == 1 [L366] m_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L370] COND TRUE t1_i == 1 [L371] t1_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L375] COND TRUE t2_i == 1 [L376] t2_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L380] COND TRUE t3_i == 1 [L381] t3_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L385] COND TRUE t4_i == 1 [L386] t4_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L809] RET init_threads() [L810] CALL fire_delta_events() [L526] COND FALSE !(M_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L531] COND FALSE !(T1_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L536] COND FALSE !(T2_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L541] COND FALSE !(T3_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L546] COND FALSE !(T4_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L551] COND FALSE !(E_M == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L556] COND FALSE !(E_1 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L561] COND FALSE !(E_2 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L566] COND FALSE !(E_3 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L571] COND FALSE !(E_4 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L810] RET fire_delta_events() [L811] CALL activate_threads() [L639] int tmp ; [L640] int tmp___0 ; [L641] int tmp___1 ; [L642] int tmp___2 ; [L643] int tmp___3 ; [L647] CALL, EXPR is_master_triggered() [L259] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L262] COND FALSE !(m_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L272] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L274] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L647] RET, EXPR is_master_triggered() [L647] tmp = is_master_triggered() [L649] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, tmp=0, token=0] [L655] CALL, EXPR is_transmit1_triggered() [L278] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L281] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L291] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L293] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L655] RET, EXPR is_transmit1_triggered() [L655] tmp___0 = is_transmit1_triggered() [L657] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, tmp=0, tmp___0=0, token=0] [L663] CALL, EXPR is_transmit2_triggered() [L297] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L300] COND FALSE !(t2_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L310] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L312] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L663] RET, EXPR is_transmit2_triggered() [L663] tmp___1 = is_transmit2_triggered() [L665] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, tmp=0, tmp___0=0, tmp___1=0, token=0] [L671] CALL, EXPR is_transmit3_triggered() [L316] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L319] COND FALSE !(t3_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L329] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L331] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L671] RET, EXPR is_transmit3_triggered() [L671] tmp___2 = is_transmit3_triggered() [L673] COND FALSE !(\read(tmp___2)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, token=0] [L679] CALL, EXPR is_transmit4_triggered() [L335] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L338] COND FALSE !(t4_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L348] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L350] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L679] RET, EXPR is_transmit4_triggered() [L679] tmp___3 = is_transmit4_triggered() [L681] COND FALSE !(\read(tmp___3)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0, token=0] [L811] RET activate_threads() [L812] CALL reset_delta_events() [L584] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L589] COND FALSE !(T1_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L594] COND FALSE !(T2_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L599] COND FALSE !(T3_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L604] COND FALSE !(T4_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L609] COND FALSE !(E_M == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L614] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L619] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L624] COND FALSE !(E_3 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L629] COND FALSE !(E_4 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L812] RET reset_delta_events() [L815] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, kernel_st=0, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] [L818] kernel_st = 1 [L819] CALL eval() [L431] int tmp ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, token=0] Loop: [L435] COND TRUE 1 [L438] CALL, EXPR exists_runnable_thread() [L395] int __retres1 ; [L398] COND TRUE m_st == 0 [L399] __retres1 = 1 [L426] return (__retres1); [L438] RET, EXPR exists_runnable_thread() [L438] tmp = exists_runnable_thread() [L440] COND TRUE \read(tmp) [L445] COND TRUE m_st == 0 [L446] int tmp_ndt_1; [L447] tmp_ndt_1 = __VERIFIER_nondet_int() [L448] COND FALSE !(\read(tmp_ndt_1)) [L459] COND TRUE t1_st == 0 [L460] int tmp_ndt_2; [L461] tmp_ndt_2 = __VERIFIER_nondet_int() [L462] COND FALSE !(\read(tmp_ndt_2)) [L473] COND TRUE t2_st == 0 [L474] int tmp_ndt_3; [L475] tmp_ndt_3 = __VERIFIER_nondet_int() [L476] COND FALSE !(\read(tmp_ndt_3)) [L487] COND TRUE t3_st == 0 [L488] int tmp_ndt_4; [L489] tmp_ndt_4 = __VERIFIER_nondet_int() [L490] COND FALSE !(\read(tmp_ndt_4)) [L501] COND TRUE t4_st == 0 [L502] int tmp_ndt_5; [L503] tmp_ndt_5 = __VERIFIER_nondet_int() [L504] COND FALSE !(\read(tmp_ndt_5)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2022-12-13 14:12:57,804 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4779227a-506f-4eeb-bef1-40db864f4417/bin/uautomizer-uyxdKDjOR8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Forceful destruction successful, exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)