./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/token_ring.05.cil-1.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 2329fc70 Calling Ultimate with: /usr/lib/jvm/java-1.11.0-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_05afda94-e2e1-40bd-8d1f-ea253943d058/bin/uautomizer-uyxdKDjOR8/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_05afda94-e2e1-40bd-8d1f-ea253943d058/bin/uautomizer-uyxdKDjOR8/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_05afda94-e2e1-40bd-8d1f-ea253943d058/bin/uautomizer-uyxdKDjOR8/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_05afda94-e2e1-40bd-8d1f-ea253943d058/bin/uautomizer-uyxdKDjOR8/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/token_ring.05.cil-1.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_05afda94-e2e1-40bd-8d1f-ea253943d058/bin/uautomizer-uyxdKDjOR8/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_05afda94-e2e1-40bd-8d1f-ea253943d058/bin/uautomizer-uyxdKDjOR8 --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash a75784c0f203c4a6f14019aef9d9a89ba63a0efbe594dc5cdecfb5d06e7619f2 --- Real Ultimate output --- [0.001s][warning][os,container] Duplicate cpuset controllers detected. Picking /sys/fs/cgroup/cpuset, skipping /sys/fs/cgroup/cpuset. This is Ultimate 0.2.2-dev-2329fc7 [2022-12-13 22:01:16,708 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-12-13 22:01:16,710 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-12-13 22:01:16,734 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-12-13 22:01:16,734 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-12-13 22:01:16,735 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-12-13 22:01:16,736 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-12-13 22:01:16,738 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-12-13 22:01:16,739 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-12-13 22:01:16,740 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-12-13 22:01:16,741 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-12-13 22:01:16,742 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-12-13 22:01:16,742 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-12-13 22:01:16,743 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-12-13 22:01:16,744 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-12-13 22:01:16,746 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-12-13 22:01:16,747 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-12-13 22:01:16,748 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-12-13 22:01:16,749 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-12-13 22:01:16,751 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-12-13 22:01:16,752 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-12-13 22:01:16,753 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-12-13 22:01:16,754 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-12-13 22:01:16,755 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-12-13 22:01:16,758 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-12-13 22:01:16,758 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-12-13 22:01:16,759 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-12-13 22:01:16,760 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-12-13 22:01:16,760 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-12-13 22:01:16,761 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-12-13 22:01:16,761 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-12-13 22:01:16,762 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-12-13 22:01:16,763 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-12-13 22:01:16,763 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-12-13 22:01:16,764 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-12-13 22:01:16,764 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-12-13 22:01:16,765 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-12-13 22:01:16,765 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-12-13 22:01:16,765 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-12-13 22:01:16,766 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-12-13 22:01:16,766 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-12-13 22:01:16,767 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_05afda94-e2e1-40bd-8d1f-ea253943d058/bin/uautomizer-uyxdKDjOR8/config/svcomp-Termination-32bit-Automizer_Default.epf [2022-12-13 22:01:16,788 INFO L113 SettingsManager]: Loading preferences was successful [2022-12-13 22:01:16,788 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-12-13 22:01:16,788 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-12-13 22:01:16,788 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-12-13 22:01:16,789 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-12-13 22:01:16,790 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-12-13 22:01:16,790 INFO L138 SettingsManager]: * Use SBE=true [2022-12-13 22:01:16,790 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2022-12-13 22:01:16,790 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2022-12-13 22:01:16,790 INFO L138 SettingsManager]: * Use old map elimination=false [2022-12-13 22:01:16,790 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2022-12-13 22:01:16,791 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2022-12-13 22:01:16,791 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2022-12-13 22:01:16,791 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-12-13 22:01:16,791 INFO L138 SettingsManager]: * sizeof long=4 [2022-12-13 22:01:16,791 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2022-12-13 22:01:16,791 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-12-13 22:01:16,792 INFO L138 SettingsManager]: * sizeof POINTER=4 [2022-12-13 22:01:16,792 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-12-13 22:01:16,792 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2022-12-13 22:01:16,792 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2022-12-13 22:01:16,792 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2022-12-13 22:01:16,792 INFO L138 SettingsManager]: * sizeof long double=12 [2022-12-13 22:01:16,792 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-12-13 22:01:16,792 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2022-12-13 22:01:16,793 INFO L138 SettingsManager]: * Use constant arrays=true [2022-12-13 22:01:16,793 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2022-12-13 22:01:16,793 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-12-13 22:01:16,793 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-12-13 22:01:16,793 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-12-13 22:01:16,793 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-12-13 22:01:16,794 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-12-13 22:01:16,794 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_05afda94-e2e1-40bd-8d1f-ea253943d058/bin/uautomizer-uyxdKDjOR8/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_05afda94-e2e1-40bd-8d1f-ea253943d058/bin/uautomizer-uyxdKDjOR8 Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> a75784c0f203c4a6f14019aef9d9a89ba63a0efbe594dc5cdecfb5d06e7619f2 [2022-12-13 22:01:16,986 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-12-13 22:01:17,002 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-12-13 22:01:17,004 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-12-13 22:01:17,005 INFO L271 PluginConnector]: Initializing CDTParser... [2022-12-13 22:01:17,005 INFO L275 PluginConnector]: CDTParser initialized [2022-12-13 22:01:17,006 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_05afda94-e2e1-40bd-8d1f-ea253943d058/bin/uautomizer-uyxdKDjOR8/../../sv-benchmarks/c/systemc/token_ring.05.cil-1.c [2022-12-13 22:01:19,538 INFO L500 CDTParser]: Created temporary CDT project at NULL [2022-12-13 22:01:19,715 INFO L351 CDTParser]: Found 1 translation units. [2022-12-13 22:01:19,716 INFO L172 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_05afda94-e2e1-40bd-8d1f-ea253943d058/sv-benchmarks/c/systemc/token_ring.05.cil-1.c [2022-12-13 22:01:19,726 INFO L394 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_05afda94-e2e1-40bd-8d1f-ea253943d058/bin/uautomizer-uyxdKDjOR8/data/b1597b6b3/72c95988e1fa43748ef86508000e0cd7/FLAG373c9c523 [2022-12-13 22:01:20,098 INFO L402 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_05afda94-e2e1-40bd-8d1f-ea253943d058/bin/uautomizer-uyxdKDjOR8/data/b1597b6b3/72c95988e1fa43748ef86508000e0cd7 [2022-12-13 22:01:20,100 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-12-13 22:01:20,101 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-12-13 22:01:20,102 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-12-13 22:01:20,102 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-12-13 22:01:20,105 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-12-13 22:01:20,105 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.12 10:01:20" (1/1) ... [2022-12-13 22:01:20,106 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@6b0a32fa and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 10:01:20, skipping insertion in model container [2022-12-13 22:01:20,106 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.12 10:01:20" (1/1) ... [2022-12-13 22:01:20,111 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-12-13 22:01:20,138 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-12-13 22:01:20,258 WARN L237 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_05afda94-e2e1-40bd-8d1f-ea253943d058/sv-benchmarks/c/systemc/token_ring.05.cil-1.c[671,684] [2022-12-13 22:01:20,321 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-12-13 22:01:20,333 INFO L203 MainTranslator]: Completed pre-run [2022-12-13 22:01:20,341 WARN L237 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_05afda94-e2e1-40bd-8d1f-ea253943d058/sv-benchmarks/c/systemc/token_ring.05.cil-1.c[671,684] [2022-12-13 22:01:20,377 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-12-13 22:01:20,391 INFO L208 MainTranslator]: Completed translation [2022-12-13 22:01:20,391 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 10:01:20 WrapperNode [2022-12-13 22:01:20,391 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-12-13 22:01:20,392 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-12-13 22:01:20,392 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-12-13 22:01:20,392 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-12-13 22:01:20,398 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 10:01:20" (1/1) ... [2022-12-13 22:01:20,406 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 10:01:20" (1/1) ... [2022-12-13 22:01:20,451 INFO L138 Inliner]: procedures = 38, calls = 46, calls flagged for inlining = 41, calls inlined = 94, statements flattened = 1341 [2022-12-13 22:01:20,452 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-12-13 22:01:20,452 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-12-13 22:01:20,452 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-12-13 22:01:20,452 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-12-13 22:01:20,462 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 10:01:20" (1/1) ... [2022-12-13 22:01:20,462 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 10:01:20" (1/1) ... [2022-12-13 22:01:20,467 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 10:01:20" (1/1) ... [2022-12-13 22:01:20,468 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 10:01:20" (1/1) ... [2022-12-13 22:01:20,484 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 10:01:20" (1/1) ... [2022-12-13 22:01:20,499 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 10:01:20" (1/1) ... [2022-12-13 22:01:20,502 INFO L185 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 10:01:20" (1/1) ... [2022-12-13 22:01:20,506 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 10:01:20" (1/1) ... [2022-12-13 22:01:20,512 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-12-13 22:01:20,513 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-12-13 22:01:20,513 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-12-13 22:01:20,513 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-12-13 22:01:20,514 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 10:01:20" (1/1) ... [2022-12-13 22:01:20,521 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-12-13 22:01:20,533 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_05afda94-e2e1-40bd-8d1f-ea253943d058/bin/uautomizer-uyxdKDjOR8/z3 [2022-12-13 22:01:20,545 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_05afda94-e2e1-40bd-8d1f-ea253943d058/bin/uautomizer-uyxdKDjOR8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-12-13 22:01:20,547 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_05afda94-e2e1-40bd-8d1f-ea253943d058/bin/uautomizer-uyxdKDjOR8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2022-12-13 22:01:20,581 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-12-13 22:01:20,581 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-12-13 22:01:20,581 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-12-13 22:01:20,581 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-12-13 22:01:20,660 INFO L235 CfgBuilder]: Building ICFG [2022-12-13 22:01:20,662 INFO L261 CfgBuilder]: Building CFG for each procedure with an implementation [2022-12-13 22:01:21,369 INFO L276 CfgBuilder]: Performing block encoding [2022-12-13 22:01:21,377 INFO L295 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-12-13 22:01:21,377 INFO L300 CfgBuilder]: Removed 8 assume(true) statements. [2022-12-13 22:01:21,379 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.12 10:01:21 BoogieIcfgContainer [2022-12-13 22:01:21,379 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-12-13 22:01:21,380 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2022-12-13 22:01:21,380 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2022-12-13 22:01:21,383 INFO L275 PluginConnector]: BuchiAutomizer initialized [2022-12-13 22:01:21,383 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-12-13 22:01:21,383 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 13.12 10:01:20" (1/3) ... [2022-12-13 22:01:21,384 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@40b78a28 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 13.12 10:01:21, skipping insertion in model container [2022-12-13 22:01:21,384 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-12-13 22:01:21,384 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 10:01:20" (2/3) ... [2022-12-13 22:01:21,384 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@40b78a28 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 13.12 10:01:21, skipping insertion in model container [2022-12-13 22:01:21,384 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-12-13 22:01:21,385 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.12 10:01:21" (3/3) ... [2022-12-13 22:01:21,386 INFO L332 chiAutomizerObserver]: Analyzing ICFG token_ring.05.cil-1.c [2022-12-13 22:01:21,433 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2022-12-13 22:01:21,433 INFO L304 stractBuchiCegarLoop]: Hoare is false [2022-12-13 22:01:21,433 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2022-12-13 22:01:21,433 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2022-12-13 22:01:21,433 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2022-12-13 22:01:21,433 INFO L308 stractBuchiCegarLoop]: Difference is false [2022-12-13 22:01:21,434 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2022-12-13 22:01:21,434 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2022-12-13 22:01:21,438 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 552 states, 551 states have (on average 1.528130671506352) internal successors, (842), 551 states have internal predecessors, (842), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 22:01:21,465 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 469 [2022-12-13 22:01:21,465 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 22:01:21,465 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 22:01:21,472 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 22:01:21,472 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 22:01:21,473 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2022-12-13 22:01:21,474 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 552 states, 551 states have (on average 1.528130671506352) internal successors, (842), 551 states have internal predecessors, (842), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 22:01:21,483 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 469 [2022-12-13 22:01:21,483 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 22:01:21,483 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 22:01:21,494 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 22:01:21,494 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 22:01:21,500 INFO L748 eck$LassoCheckResult]: Stem: 172#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 459#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 263#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 455#update_channels_returnLabel#1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 545#L414true assume !(1 == ~m_i~0);~m_st~0 := 2; 218#L414-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 411#L419-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 410#L424-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 200#L429-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 403#L434-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 462#L439-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 198#L599true assume 0 == ~M_E~0;~M_E~0 := 1; 357#L599-2true assume !(0 == ~T1_E~0); 10#L604-1true assume !(0 == ~T2_E~0); 5#L609-1true assume !(0 == ~T3_E~0); 85#L614-1true assume !(0 == ~T4_E~0); 155#L619-1true assume !(0 == ~T5_E~0); 222#L624-1true assume !(0 == ~E_M~0); 501#L629-1true assume !(0 == ~E_1~0); 49#L634-1true assume 0 == ~E_2~0;~E_2~0 := 1; 324#L639-1true assume !(0 == ~E_3~0); 397#L644-1true assume !(0 == ~E_4~0); 348#L649-1true assume !(0 == ~E_5~0); 31#L654-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 92#L292true assume !(1 == ~m_pc~0); 181#L292-2true is_master_triggered_~__retres1~0#1 := 0; 256#L303true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 153#is_master_triggered_returnLabel#1true activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 480#L743true assume !(0 != activate_threads_~tmp~1#1); 64#L743-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 323#L311true assume 1 == ~t1_pc~0; 141#L312true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 227#L322true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 27#is_transmit1_triggered_returnLabel#1true activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 19#L751true assume !(0 != activate_threads_~tmp___0~0#1); 423#L751-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 326#L330true assume 1 == ~t2_pc~0; 157#L331true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 93#L341true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 266#is_transmit2_triggered_returnLabel#1true activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 449#L759true assume !(0 != activate_threads_~tmp___1~0#1); 463#L759-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 86#L349true assume !(1 == ~t3_pc~0); 505#L349-2true is_transmit3_triggered_~__retres1~3#1 := 0; 295#L360true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6#is_transmit3_triggered_returnLabel#1true activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 531#L767true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 440#L767-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 532#L368true assume 1 == ~t4_pc~0; 451#L369true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 385#L379true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 79#is_transmit4_triggered_returnLabel#1true activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 431#L775true assume !(0 != activate_threads_~tmp___3~0#1); 12#L775-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 469#L387true assume !(1 == ~t5_pc~0); 238#L387-2true is_transmit5_triggered_~__retres1~5#1 := 0; 540#L398true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 159#is_transmit5_triggered_returnLabel#1true activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 72#L783true assume !(0 != activate_threads_~tmp___4~0#1); 124#L783-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 175#L667true assume !(1 == ~M_E~0); 332#L667-2true assume !(1 == ~T1_E~0); 339#L672-1true assume !(1 == ~T2_E~0); 147#L677-1true assume !(1 == ~T3_E~0); 307#L682-1true assume !(1 == ~T4_E~0); 399#L687-1true assume !(1 == ~T5_E~0); 464#L692-1true assume !(1 == ~E_M~0); 294#L697-1true assume 1 == ~E_1~0;~E_1~0 := 2; 522#L702-1true assume !(1 == ~E_2~0); 347#L707-1true assume !(1 == ~E_3~0); 212#L712-1true assume !(1 == ~E_4~0); 331#L717-1true assume !(1 == ~E_5~0); 314#L722-1true assume { :end_inline_reset_delta_events } true; 16#L928-2true [2022-12-13 22:01:21,501 INFO L750 eck$LassoCheckResult]: Loop: 16#L928-2true assume !false; 215#L929true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 37#L574true assume !true; 87#eval_returnLabel#1true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 395#update_channels_returnLabel#2true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 253#L599-3true assume 0 == ~M_E~0;~M_E~0 := 1; 306#L599-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 187#L604-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 510#L609-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 242#L614-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 20#L619-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 251#L624-3true assume !(0 == ~E_M~0); 303#L629-3true assume 0 == ~E_1~0;~E_1~0 := 1; 394#L634-3true assume 0 == ~E_2~0;~E_2~0 := 1; 315#L639-3true assume 0 == ~E_3~0;~E_3~0 := 1; 443#L644-3true assume 0 == ~E_4~0;~E_4~0 := 1; 512#L649-3true assume 0 == ~E_5~0;~E_5~0 := 1; 193#L654-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 292#L292-21true assume !(1 == ~m_pc~0); 127#L292-23true is_master_triggered_~__retres1~0#1 := 0; 55#L303-7true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 107#is_master_triggered_returnLabel#8true activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 424#L743-21true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 184#L743-23true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 396#L311-21true assume 1 == ~t1_pc~0; 543#L312-7true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 35#L322-7true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 68#is_transmit1_triggered_returnLabel#8true activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 460#L751-21true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 91#L751-23true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 279#L330-21true assume 1 == ~t2_pc~0; 474#L331-7true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 248#L341-7true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 180#is_transmit2_triggered_returnLabel#8true activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 268#L759-21true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 60#L759-23true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 210#L349-21true assume !(1 == ~t3_pc~0); 366#L349-23true is_transmit3_triggered_~__retres1~3#1 := 0; 382#L360-7true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 471#is_transmit3_triggered_returnLabel#8true activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 318#L767-21true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 447#L767-23true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 102#L368-21true assume 1 == ~t4_pc~0; 43#L369-7true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 380#L379-7true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 434#is_transmit4_triggered_returnLabel#8true activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 359#L775-21true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 8#L775-23true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 38#L387-21true assume !(1 == ~t5_pc~0); 538#L387-23true is_transmit5_triggered_~__retres1~5#1 := 0; 335#L398-7true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 244#is_transmit5_triggered_returnLabel#8true activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 390#L783-21true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 57#L783-23true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 183#L667-3true assume !(1 == ~M_E~0); 51#L667-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 328#L672-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 90#L677-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 549#L682-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 377#L687-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 115#L692-3true assume 1 == ~E_M~0;~E_M~0 := 2; 491#L697-3true assume 1 == ~E_1~0;~E_1~0 := 2; 165#L702-3true assume !(1 == ~E_2~0); 257#L707-3true assume 1 == ~E_3~0;~E_3~0 := 2; 291#L712-3true assume 1 == ~E_4~0;~E_4~0 := 2; 54#L717-3true assume 1 == ~E_5~0;~E_5~0 := 2; 284#L722-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 446#L452-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 384#L484-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 234#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 189#L947true assume !(0 == start_simulation_~tmp~3#1); 523#L947-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 192#L452-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 320#L484-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 26#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret18#1;havoc stop_simulation_#t~ret18#1; 375#L902true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 330#L909true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 415#stop_simulation_returnLabel#1true start_simulation_#t~ret20#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 274#L960true assume !(0 != start_simulation_~tmp___0~1#1); 16#L928-2true [2022-12-13 22:01:21,505 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 22:01:21,505 INFO L85 PathProgramCache]: Analyzing trace with hash 907431560, now seen corresponding path program 1 times [2022-12-13 22:01:21,512 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 22:01:21,512 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [182826166] [2022-12-13 22:01:21,512 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 22:01:21,513 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 22:01:21,579 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 22:01:21,662 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 22:01:21,662 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 22:01:21,663 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [182826166] [2022-12-13 22:01:21,663 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [182826166] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 22:01:21,663 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 22:01:21,664 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 22:01:21,665 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2085316541] [2022-12-13 22:01:21,666 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 22:01:21,669 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 22:01:21,670 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 22:01:21,670 INFO L85 PathProgramCache]: Analyzing trace with hash 1266610875, now seen corresponding path program 1 times [2022-12-13 22:01:21,671 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 22:01:21,671 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1015733253] [2022-12-13 22:01:21,671 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 22:01:21,671 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 22:01:21,680 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 22:01:21,700 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 22:01:21,700 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 22:01:21,701 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1015733253] [2022-12-13 22:01:21,701 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1015733253] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 22:01:21,701 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 22:01:21,701 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-12-13 22:01:21,701 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [874834102] [2022-12-13 22:01:21,701 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 22:01:21,702 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 22:01:21,703 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 22:01:21,725 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 22:01:21,725 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 22:01:21,727 INFO L87 Difference]: Start difference. First operand has 552 states, 551 states have (on average 1.528130671506352) internal successors, (842), 551 states have internal predecessors, (842), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 24.333333333333332) internal successors, (73), 3 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 22:01:21,766 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 22:01:21,766 INFO L93 Difference]: Finished difference Result 551 states and 823 transitions. [2022-12-13 22:01:21,767 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 551 states and 823 transitions. [2022-12-13 22:01:21,771 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 467 [2022-12-13 22:01:21,776 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 551 states to 546 states and 818 transitions. [2022-12-13 22:01:21,777 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 546 [2022-12-13 22:01:21,778 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 546 [2022-12-13 22:01:21,778 INFO L73 IsDeterministic]: Start isDeterministic. Operand 546 states and 818 transitions. [2022-12-13 22:01:21,780 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 22:01:21,781 INFO L218 hiAutomatonCegarLoop]: Abstraction has 546 states and 818 transitions. [2022-12-13 22:01:21,794 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 546 states and 818 transitions. [2022-12-13 22:01:21,819 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 546 to 546. [2022-12-13 22:01:21,821 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 546 states, 546 states have (on average 1.4981684981684982) internal successors, (818), 545 states have internal predecessors, (818), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 22:01:21,822 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 546 states to 546 states and 818 transitions. [2022-12-13 22:01:21,823 INFO L240 hiAutomatonCegarLoop]: Abstraction has 546 states and 818 transitions. [2022-12-13 22:01:21,824 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 22:01:21,827 INFO L428 stractBuchiCegarLoop]: Abstraction has 546 states and 818 transitions. [2022-12-13 22:01:21,827 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2022-12-13 22:01:21,828 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 546 states and 818 transitions. [2022-12-13 22:01:21,831 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 467 [2022-12-13 22:01:21,831 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 22:01:21,831 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 22:01:21,833 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 22:01:21,833 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 22:01:21,834 INFO L748 eck$LassoCheckResult]: Stem: 1421#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 1422#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 1534#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1535#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1647#L414 assume 1 == ~m_i~0;~m_st~0 := 0; 1484#L414-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1485#L419-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 1631#L424-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1463#L429-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1464#L434-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 1627#L439-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1461#L599 assume 0 == ~M_E~0;~M_E~0 := 1; 1462#L599-2 assume !(0 == ~T1_E~0); 1129#L604-1 assume !(0 == ~T2_E~0); 1118#L609-1 assume !(0 == ~T3_E~0); 1119#L614-1 assume !(0 == ~T4_E~0); 1290#L619-1 assume !(0 == ~T5_E~0); 1400#L624-1 assume !(0 == ~E_M~0); 1488#L629-1 assume !(0 == ~E_1~0); 1212#L634-1 assume 0 == ~E_2~0;~E_2~0 := 1; 1213#L639-1 assume !(0 == ~E_3~0); 1589#L644-1 assume !(0 == ~E_4~0); 1604#L649-1 assume !(0 == ~E_5~0); 1173#L654-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1174#L292 assume !(1 == ~m_pc~0); 1303#L292-2 is_master_triggered_~__retres1~0#1 := 0; 1434#L303 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1396#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1397#L743 assume !(0 != activate_threads_~tmp~1#1); 1245#L743-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1246#L311 assume 1 == ~t1_pc~0; 1375#L312 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1376#L322 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1164#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1145#L751 assume !(0 != activate_threads_~tmp___0~0#1); 1146#L751-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1590#L330 assume 1 == ~t2_pc~0; 1402#L331 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1305#L341 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1306#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1539#L759 assume !(0 != activate_threads_~tmp___1~0#1); 1645#L759-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1291#L349 assume !(1 == ~t3_pc~0); 1292#L349-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1337#L360 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1120#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1121#L767 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1640#L767-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1641#L368 assume 1 == ~t4_pc~0; 1646#L369 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1366#L379 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1276#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1277#L775 assume !(0 != activate_threads_~tmp___3~0#1); 1132#L775-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1133#L387 assume !(1 == ~t5_pc~0); 1505#L387-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1506#L398 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1405#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1262#L783 assume !(0 != activate_threads_~tmp___4~0#1); 1263#L783-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1354#L667 assume !(1 == ~M_E~0); 1426#L667-2 assume !(1 == ~T1_E~0); 1596#L672-1 assume !(1 == ~T2_E~0); 1387#L677-1 assume !(1 == ~T3_E~0); 1388#L682-1 assume !(1 == ~T4_E~0); 1573#L687-1 assume !(1 == ~T5_E~0); 1624#L692-1 assume !(1 == ~E_M~0); 1563#L697-1 assume 1 == ~E_1~0;~E_1~0 := 2; 1564#L702-1 assume !(1 == ~E_2~0); 1603#L707-1 assume !(1 == ~E_3~0); 1477#L712-1 assume !(1 == ~E_4~0); 1478#L717-1 assume !(1 == ~E_5~0); 1580#L722-1 assume { :end_inline_reset_delta_events } true; 1140#L928-2 [2022-12-13 22:01:21,835 INFO L750 eck$LassoCheckResult]: Loop: 1140#L928-2 assume !false; 1141#L929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1186#L574 assume !false; 1187#L495 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 1639#L452 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 1342#L484 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 1557#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1178#L499 assume !(0 != eval_~tmp~0#1); 1179#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1294#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1528#L599-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1529#L599-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1443#L604-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1444#L609-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1512#L614-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1147#L619-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1148#L624-3 assume !(0 == ~E_M~0); 1523#L629-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1570#L634-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1581#L639-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1582#L644-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1643#L649-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1453#L654-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1454#L292-21 assume 1 == ~m_pc~0; 1531#L293-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1227#L303-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1228#is_master_triggered_returnLabel#8 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1328#L743-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1437#L743-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1438#L311-21 assume 1 == ~t1_pc~0; 1623#L312-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1182#L322-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1183#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1253#L751-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1301#L751-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1302#L330-21 assume 1 == ~t2_pc~0; 1552#L331-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1520#L341-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1432#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1433#L759-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1237#L759-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1238#L349-21 assume !(1 == ~t3_pc~0); 1474#L349-23 is_transmit3_triggered_~__retres1~3#1 := 0; 1613#L360-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1619#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1584#L767-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1585#L767-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1318#L368-21 assume 1 == ~t4_pc~0; 1200#L369-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1201#L379-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1618#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1607#L775-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1125#L775-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1126#L387-21 assume 1 == ~t5_pc~0; 1188#L388-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1504#L398-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1514#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1515#L783-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1229#L783-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1230#L667-3 assume !(1 == ~M_E~0); 1217#L667-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1218#L672-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1299#L677-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1300#L682-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1617#L687-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1338#L692-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1339#L697-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1410#L702-3 assume !(1 == ~E_2~0); 1411#L707-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1530#L712-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1221#L717-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1222#L722-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 1556#L452-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 1153#L484-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 1501#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 1446#L947 assume !(0 == start_simulation_~tmp~3#1); 1447#L947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 1450#L452-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 1414#L484-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 1162#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret18#1;havoc stop_simulation_#t~ret18#1; 1163#L902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1594#L909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1595#stop_simulation_returnLabel#1 start_simulation_#t~ret20#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 1543#L960 assume !(0 != start_simulation_~tmp___0~1#1); 1140#L928-2 [2022-12-13 22:01:21,835 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 22:01:21,835 INFO L85 PathProgramCache]: Analyzing trace with hash 1400057734, now seen corresponding path program 1 times [2022-12-13 22:01:21,836 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 22:01:21,836 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [979842637] [2022-12-13 22:01:21,836 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 22:01:21,836 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 22:01:21,852 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 22:01:21,909 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 22:01:21,909 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 22:01:21,910 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [979842637] [2022-12-13 22:01:21,910 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [979842637] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 22:01:21,910 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 22:01:21,910 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 22:01:21,910 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [71578928] [2022-12-13 22:01:21,911 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 22:01:21,911 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 22:01:21,912 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 22:01:21,912 INFO L85 PathProgramCache]: Analyzing trace with hash 354999345, now seen corresponding path program 1 times [2022-12-13 22:01:21,912 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 22:01:21,912 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [135644122] [2022-12-13 22:01:21,912 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 22:01:21,913 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 22:01:21,933 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 22:01:21,995 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 22:01:21,995 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 22:01:21,995 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [135644122] [2022-12-13 22:01:21,996 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [135644122] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 22:01:21,996 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 22:01:21,996 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 22:01:21,996 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [529471671] [2022-12-13 22:01:21,996 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 22:01:21,997 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 22:01:21,997 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 22:01:21,997 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 22:01:21,997 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 22:01:21,998 INFO L87 Difference]: Start difference. First operand 546 states and 818 transitions. cyclomatic complexity: 273 Second operand has 3 states, 3 states have (on average 24.333333333333332) internal successors, (73), 3 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 22:01:22,019 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 22:01:22,019 INFO L93 Difference]: Finished difference Result 546 states and 817 transitions. [2022-12-13 22:01:22,020 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 546 states and 817 transitions. [2022-12-13 22:01:22,022 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 467 [2022-12-13 22:01:22,026 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 546 states to 546 states and 817 transitions. [2022-12-13 22:01:22,027 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 546 [2022-12-13 22:01:22,028 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 546 [2022-12-13 22:01:22,028 INFO L73 IsDeterministic]: Start isDeterministic. Operand 546 states and 817 transitions. [2022-12-13 22:01:22,030 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 22:01:22,030 INFO L218 hiAutomatonCegarLoop]: Abstraction has 546 states and 817 transitions. [2022-12-13 22:01:22,031 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 546 states and 817 transitions. [2022-12-13 22:01:22,041 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 546 to 546. [2022-12-13 22:01:22,042 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 546 states, 546 states have (on average 1.4963369963369964) internal successors, (817), 545 states have internal predecessors, (817), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 22:01:22,045 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 546 states to 546 states and 817 transitions. [2022-12-13 22:01:22,045 INFO L240 hiAutomatonCegarLoop]: Abstraction has 546 states and 817 transitions. [2022-12-13 22:01:22,045 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 22:01:22,046 INFO L428 stractBuchiCegarLoop]: Abstraction has 546 states and 817 transitions. [2022-12-13 22:01:22,046 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2022-12-13 22:01:22,046 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 546 states and 817 transitions. [2022-12-13 22:01:22,049 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 467 [2022-12-13 22:01:22,049 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 22:01:22,049 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 22:01:22,051 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 22:01:22,051 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 22:01:22,052 INFO L748 eck$LassoCheckResult]: Stem: 2520#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 2521#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 2633#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2634#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2746#L414 assume 1 == ~m_i~0;~m_st~0 := 0; 2583#L414-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2584#L419-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2730#L424-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 2562#L429-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2563#L434-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 2726#L439-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2560#L599 assume 0 == ~M_E~0;~M_E~0 := 1; 2561#L599-2 assume !(0 == ~T1_E~0); 2230#L604-1 assume !(0 == ~T2_E~0); 2217#L609-1 assume !(0 == ~T3_E~0); 2218#L614-1 assume !(0 == ~T4_E~0); 2389#L619-1 assume !(0 == ~T5_E~0); 2499#L624-1 assume !(0 == ~E_M~0); 2587#L629-1 assume !(0 == ~E_1~0); 2311#L634-1 assume 0 == ~E_2~0;~E_2~0 := 1; 2312#L639-1 assume !(0 == ~E_3~0); 2688#L644-1 assume !(0 == ~E_4~0); 2703#L649-1 assume !(0 == ~E_5~0); 2272#L654-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2273#L292 assume !(1 == ~m_pc~0); 2402#L292-2 is_master_triggered_~__retres1~0#1 := 0; 2533#L303 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2495#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 2496#L743 assume !(0 != activate_threads_~tmp~1#1); 2344#L743-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2345#L311 assume 1 == ~t1_pc~0; 2474#L312 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2475#L322 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2263#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2244#L751 assume !(0 != activate_threads_~tmp___0~0#1); 2245#L751-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2689#L330 assume 1 == ~t2_pc~0; 2501#L331 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2404#L341 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2405#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2638#L759 assume !(0 != activate_threads_~tmp___1~0#1); 2744#L759-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2390#L349 assume !(1 == ~t3_pc~0); 2391#L349-2 is_transmit3_triggered_~__retres1~3#1 := 0; 2438#L360 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2221#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2222#L767 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2739#L767-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2740#L368 assume 1 == ~t4_pc~0; 2745#L369 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2465#L379 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2375#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2376#L775 assume !(0 != activate_threads_~tmp___3~0#1); 2231#L775-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2232#L387 assume !(1 == ~t5_pc~0); 2604#L387-2 is_transmit5_triggered_~__retres1~5#1 := 0; 2605#L398 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2504#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2361#L783 assume !(0 != activate_threads_~tmp___4~0#1); 2362#L783-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2453#L667 assume !(1 == ~M_E~0); 2525#L667-2 assume !(1 == ~T1_E~0); 2695#L672-1 assume !(1 == ~T2_E~0); 2486#L677-1 assume !(1 == ~T3_E~0); 2487#L682-1 assume !(1 == ~T4_E~0); 2672#L687-1 assume !(1 == ~T5_E~0); 2723#L692-1 assume !(1 == ~E_M~0); 2662#L697-1 assume 1 == ~E_1~0;~E_1~0 := 2; 2663#L702-1 assume !(1 == ~E_2~0); 2702#L707-1 assume !(1 == ~E_3~0); 2576#L712-1 assume !(1 == ~E_4~0); 2577#L717-1 assume !(1 == ~E_5~0); 2679#L722-1 assume { :end_inline_reset_delta_events } true; 2239#L928-2 [2022-12-13 22:01:22,052 INFO L750 eck$LassoCheckResult]: Loop: 2239#L928-2 assume !false; 2240#L929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2285#L574 assume !false; 2286#L495 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 2738#L452 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 2441#L484 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 2656#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 2277#L499 assume !(0 != eval_~tmp~0#1); 2278#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2393#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2627#L599-3 assume 0 == ~M_E~0;~M_E~0 := 1; 2628#L599-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2542#L604-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2543#L609-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2613#L614-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2246#L619-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2247#L624-3 assume !(0 == ~E_M~0); 2622#L629-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2669#L634-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2680#L639-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2681#L644-3 assume 0 == ~E_4~0;~E_4~0 := 1; 2742#L649-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2552#L654-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2553#L292-21 assume 1 == ~m_pc~0; 2630#L293-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 2326#L303-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2327#is_master_triggered_returnLabel#8 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 2427#L743-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2536#L743-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2537#L311-21 assume 1 == ~t1_pc~0; 2722#L312-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2281#L322-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2282#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2352#L751-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2400#L751-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2401#L330-21 assume 1 == ~t2_pc~0; 2651#L331-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2619#L341-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2531#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2532#L759-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2338#L759-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2339#L349-21 assume !(1 == ~t3_pc~0); 2573#L349-23 is_transmit3_triggered_~__retres1~3#1 := 0; 2712#L360-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2718#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2683#L767-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2684#L767-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2417#L368-21 assume 1 == ~t4_pc~0; 2299#L369-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2300#L379-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2717#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2706#L775-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 2219#L775-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2220#L387-21 assume !(1 == ~t5_pc~0); 2288#L387-23 is_transmit5_triggered_~__retres1~5#1 := 0; 2603#L398-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2611#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2612#L783-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 2328#L783-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2329#L667-3 assume !(1 == ~M_E~0); 2313#L667-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2314#L672-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2396#L677-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2397#L682-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2716#L687-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2436#L692-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2437#L697-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2509#L702-3 assume !(1 == ~E_2~0); 2510#L707-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2629#L712-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2322#L717-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2323#L722-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 2655#L452-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 2252#L484-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 2600#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 2545#L947 assume !(0 == start_simulation_~tmp~3#1); 2546#L947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 2549#L452-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 2513#L484-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 2261#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret18#1;havoc stop_simulation_#t~ret18#1; 2262#L902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2693#L909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2694#stop_simulation_returnLabel#1 start_simulation_#t~ret20#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 2642#L960 assume !(0 != start_simulation_~tmp___0~1#1); 2239#L928-2 [2022-12-13 22:01:22,053 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 22:01:22,053 INFO L85 PathProgramCache]: Analyzing trace with hash -1678755836, now seen corresponding path program 1 times [2022-12-13 22:01:22,053 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 22:01:22,053 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1351364855] [2022-12-13 22:01:22,053 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 22:01:22,054 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 22:01:22,065 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 22:01:22,109 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 22:01:22,109 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 22:01:22,109 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1351364855] [2022-12-13 22:01:22,109 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1351364855] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 22:01:22,110 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 22:01:22,110 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 22:01:22,110 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1819237904] [2022-12-13 22:01:22,110 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 22:01:22,110 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 22:01:22,111 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 22:01:22,111 INFO L85 PathProgramCache]: Analyzing trace with hash -1416471630, now seen corresponding path program 1 times [2022-12-13 22:01:22,111 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 22:01:22,111 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1347915642] [2022-12-13 22:01:22,112 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 22:01:22,112 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 22:01:22,122 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 22:01:22,154 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 22:01:22,154 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 22:01:22,154 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1347915642] [2022-12-13 22:01:22,154 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1347915642] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 22:01:22,155 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 22:01:22,155 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 22:01:22,155 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2074116064] [2022-12-13 22:01:22,155 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 22:01:22,156 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 22:01:22,156 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 22:01:22,156 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 22:01:22,156 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 22:01:22,157 INFO L87 Difference]: Start difference. First operand 546 states and 817 transitions. cyclomatic complexity: 272 Second operand has 3 states, 3 states have (on average 24.333333333333332) internal successors, (73), 3 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 22:01:22,170 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 22:01:22,171 INFO L93 Difference]: Finished difference Result 546 states and 816 transitions. [2022-12-13 22:01:22,171 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 546 states and 816 transitions. [2022-12-13 22:01:22,173 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 467 [2022-12-13 22:01:22,175 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 546 states to 546 states and 816 transitions. [2022-12-13 22:01:22,175 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 546 [2022-12-13 22:01:22,176 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 546 [2022-12-13 22:01:22,176 INFO L73 IsDeterministic]: Start isDeterministic. Operand 546 states and 816 transitions. [2022-12-13 22:01:22,177 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 22:01:22,177 INFO L218 hiAutomatonCegarLoop]: Abstraction has 546 states and 816 transitions. [2022-12-13 22:01:22,177 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 546 states and 816 transitions. [2022-12-13 22:01:22,183 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 546 to 546. [2022-12-13 22:01:22,184 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 546 states, 546 states have (on average 1.4945054945054945) internal successors, (816), 545 states have internal predecessors, (816), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 22:01:22,185 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 546 states to 546 states and 816 transitions. [2022-12-13 22:01:22,185 INFO L240 hiAutomatonCegarLoop]: Abstraction has 546 states and 816 transitions. [2022-12-13 22:01:22,186 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 22:01:22,186 INFO L428 stractBuchiCegarLoop]: Abstraction has 546 states and 816 transitions. [2022-12-13 22:01:22,186 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2022-12-13 22:01:22,186 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 546 states and 816 transitions. [2022-12-13 22:01:22,188 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 467 [2022-12-13 22:01:22,188 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 22:01:22,188 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 22:01:22,189 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 22:01:22,190 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 22:01:22,190 INFO L748 eck$LassoCheckResult]: Stem: 3619#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 3620#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 3732#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3733#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3845#L414 assume 1 == ~m_i~0;~m_st~0 := 0; 3682#L414-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3683#L419-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3829#L424-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3663#L429-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 3664#L434-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 3825#L439-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3659#L599 assume 0 == ~M_E~0;~M_E~0 := 1; 3660#L599-2 assume !(0 == ~T1_E~0); 3329#L604-1 assume !(0 == ~T2_E~0); 3316#L609-1 assume !(0 == ~T3_E~0); 3317#L614-1 assume !(0 == ~T4_E~0); 3488#L619-1 assume !(0 == ~T5_E~0); 3598#L624-1 assume !(0 == ~E_M~0); 3686#L629-1 assume !(0 == ~E_1~0); 3410#L634-1 assume 0 == ~E_2~0;~E_2~0 := 1; 3411#L639-1 assume !(0 == ~E_3~0); 3787#L644-1 assume !(0 == ~E_4~0); 3802#L649-1 assume !(0 == ~E_5~0); 3371#L654-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3372#L292 assume !(1 == ~m_pc~0); 3501#L292-2 is_master_triggered_~__retres1~0#1 := 0; 3632#L303 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3594#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 3595#L743 assume !(0 != activate_threads_~tmp~1#1); 3443#L743-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3444#L311 assume 1 == ~t1_pc~0; 3573#L312 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3574#L322 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3362#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3343#L751 assume !(0 != activate_threads_~tmp___0~0#1); 3344#L751-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3788#L330 assume 1 == ~t2_pc~0; 3600#L331 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3503#L341 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3504#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 3737#L759 assume !(0 != activate_threads_~tmp___1~0#1); 3843#L759-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3489#L349 assume !(1 == ~t3_pc~0); 3490#L349-2 is_transmit3_triggered_~__retres1~3#1 := 0; 3537#L360 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3323#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3324#L767 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3838#L767-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3839#L368 assume 1 == ~t4_pc~0; 3844#L369 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3564#L379 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3474#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3475#L775 assume !(0 != activate_threads_~tmp___3~0#1); 3330#L775-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3331#L387 assume !(1 == ~t5_pc~0); 3703#L387-2 is_transmit5_triggered_~__retres1~5#1 := 0; 3704#L398 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3603#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3463#L783 assume !(0 != activate_threads_~tmp___4~0#1); 3464#L783-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3554#L667 assume !(1 == ~M_E~0); 3624#L667-2 assume !(1 == ~T1_E~0); 3794#L672-1 assume !(1 == ~T2_E~0); 3585#L677-1 assume !(1 == ~T3_E~0); 3586#L682-1 assume !(1 == ~T4_E~0); 3771#L687-1 assume !(1 == ~T5_E~0); 3822#L692-1 assume !(1 == ~E_M~0); 3761#L697-1 assume 1 == ~E_1~0;~E_1~0 := 2; 3762#L702-1 assume !(1 == ~E_2~0); 3801#L707-1 assume !(1 == ~E_3~0); 3675#L712-1 assume !(1 == ~E_4~0); 3676#L717-1 assume !(1 == ~E_5~0); 3778#L722-1 assume { :end_inline_reset_delta_events } true; 3338#L928-2 [2022-12-13 22:01:22,190 INFO L750 eck$LassoCheckResult]: Loop: 3338#L928-2 assume !false; 3339#L929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3384#L574 assume !false; 3385#L495 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 3837#L452 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 3540#L484 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 3755#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 3376#L499 assume !(0 != eval_~tmp~0#1); 3377#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3492#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3726#L599-3 assume 0 == ~M_E~0;~M_E~0 := 1; 3727#L599-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3641#L604-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3642#L609-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3713#L614-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3345#L619-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 3346#L624-3 assume !(0 == ~E_M~0); 3721#L629-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3768#L634-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3779#L639-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3780#L644-3 assume 0 == ~E_4~0;~E_4~0 := 1; 3841#L649-3 assume 0 == ~E_5~0;~E_5~0 := 1; 3651#L654-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3652#L292-21 assume 1 == ~m_pc~0; 3729#L293-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 3425#L303-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3426#is_master_triggered_returnLabel#8 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 3526#L743-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3635#L743-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3636#L311-21 assume !(1 == ~t1_pc~0); 3568#L311-23 is_transmit1_triggered_~__retres1~1#1 := 0; 3380#L322-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3381#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3451#L751-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3499#L751-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3500#L330-21 assume 1 == ~t2_pc~0; 3747#L331-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3718#L341-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3629#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 3630#L759-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3432#L759-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3433#L349-21 assume !(1 == ~t3_pc~0); 3672#L349-23 is_transmit3_triggered_~__retres1~3#1 := 0; 3810#L360-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3817#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3782#L767-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3783#L767-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3516#L368-21 assume 1 == ~t4_pc~0; 3398#L369-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3399#L379-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3816#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3805#L775-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 3321#L775-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3322#L387-21 assume 1 == ~t5_pc~0; 3386#L388-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 3702#L398-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3711#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3712#L783-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 3427#L783-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3428#L667-3 assume !(1 == ~M_E~0); 3412#L667-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3413#L672-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3495#L677-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3496#L682-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3815#L687-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3535#L692-3 assume 1 == ~E_M~0;~E_M~0 := 2; 3536#L697-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3608#L702-3 assume !(1 == ~E_2~0); 3609#L707-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3728#L712-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3421#L717-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3422#L722-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 3754#L452-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 3351#L484-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 3699#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 3644#L947 assume !(0 == start_simulation_~tmp~3#1); 3645#L947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 3648#L452-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 3612#L484-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 3360#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret18#1;havoc stop_simulation_#t~ret18#1; 3361#L902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3792#L909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3793#stop_simulation_returnLabel#1 start_simulation_#t~ret20#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 3741#L960 assume !(0 != start_simulation_~tmp___0~1#1); 3338#L928-2 [2022-12-13 22:01:22,191 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 22:01:22,191 INFO L85 PathProgramCache]: Analyzing trace with hash -946788410, now seen corresponding path program 1 times [2022-12-13 22:01:22,191 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 22:01:22,191 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2015982243] [2022-12-13 22:01:22,191 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 22:01:22,191 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 22:01:22,199 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 22:01:22,220 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 22:01:22,220 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 22:01:22,221 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2015982243] [2022-12-13 22:01:22,221 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2015982243] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 22:01:22,221 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 22:01:22,221 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 22:01:22,221 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1120952714] [2022-12-13 22:01:22,221 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 22:01:22,222 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 22:01:22,222 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 22:01:22,222 INFO L85 PathProgramCache]: Analyzing trace with hash -753129294, now seen corresponding path program 1 times [2022-12-13 22:01:22,223 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 22:01:22,223 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [445938795] [2022-12-13 22:01:22,223 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 22:01:22,223 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 22:01:22,232 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 22:01:22,254 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 22:01:22,254 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 22:01:22,255 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [445938795] [2022-12-13 22:01:22,255 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [445938795] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 22:01:22,255 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 22:01:22,255 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 22:01:22,255 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2029961423] [2022-12-13 22:01:22,255 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 22:01:22,256 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 22:01:22,256 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 22:01:22,256 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 22:01:22,256 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 22:01:22,257 INFO L87 Difference]: Start difference. First operand 546 states and 816 transitions. cyclomatic complexity: 271 Second operand has 3 states, 3 states have (on average 24.333333333333332) internal successors, (73), 3 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 22:01:22,267 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 22:01:22,268 INFO L93 Difference]: Finished difference Result 546 states and 815 transitions. [2022-12-13 22:01:22,268 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 546 states and 815 transitions. [2022-12-13 22:01:22,270 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 467 [2022-12-13 22:01:22,271 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 546 states to 546 states and 815 transitions. [2022-12-13 22:01:22,271 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 546 [2022-12-13 22:01:22,271 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 546 [2022-12-13 22:01:22,271 INFO L73 IsDeterministic]: Start isDeterministic. Operand 546 states and 815 transitions. [2022-12-13 22:01:22,272 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 22:01:22,272 INFO L218 hiAutomatonCegarLoop]: Abstraction has 546 states and 815 transitions. [2022-12-13 22:01:22,272 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 546 states and 815 transitions. [2022-12-13 22:01:22,276 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 546 to 546. [2022-12-13 22:01:22,277 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 546 states, 546 states have (on average 1.4926739926739927) internal successors, (815), 545 states have internal predecessors, (815), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 22:01:22,278 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 546 states to 546 states and 815 transitions. [2022-12-13 22:01:22,278 INFO L240 hiAutomatonCegarLoop]: Abstraction has 546 states and 815 transitions. [2022-12-13 22:01:22,278 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 22:01:22,279 INFO L428 stractBuchiCegarLoop]: Abstraction has 546 states and 815 transitions. [2022-12-13 22:01:22,279 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2022-12-13 22:01:22,279 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 546 states and 815 transitions. [2022-12-13 22:01:22,280 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 467 [2022-12-13 22:01:22,280 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 22:01:22,280 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 22:01:22,281 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 22:01:22,281 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 22:01:22,281 INFO L748 eck$LassoCheckResult]: Stem: 4718#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 4719#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 4831#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4832#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4944#L414 assume 1 == ~m_i~0;~m_st~0 := 0; 4781#L414-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4782#L419-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4928#L424-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 4762#L429-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 4763#L434-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 4924#L439-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4758#L599 assume 0 == ~M_E~0;~M_E~0 := 1; 4759#L599-2 assume !(0 == ~T1_E~0); 4428#L604-1 assume !(0 == ~T2_E~0); 4415#L609-1 assume !(0 == ~T3_E~0); 4416#L614-1 assume !(0 == ~T4_E~0); 4587#L619-1 assume !(0 == ~T5_E~0); 4697#L624-1 assume !(0 == ~E_M~0); 4785#L629-1 assume !(0 == ~E_1~0); 4509#L634-1 assume 0 == ~E_2~0;~E_2~0 := 1; 4510#L639-1 assume !(0 == ~E_3~0); 4886#L644-1 assume !(0 == ~E_4~0); 4901#L649-1 assume !(0 == ~E_5~0); 4470#L654-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4471#L292 assume !(1 == ~m_pc~0); 4600#L292-2 is_master_triggered_~__retres1~0#1 := 0; 4731#L303 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4695#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 4696#L743 assume !(0 != activate_threads_~tmp~1#1); 4542#L743-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4543#L311 assume 1 == ~t1_pc~0; 4672#L312 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4673#L322 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4461#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 4442#L751 assume !(0 != activate_threads_~tmp___0~0#1); 4443#L751-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4887#L330 assume 1 == ~t2_pc~0; 4699#L331 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4602#L341 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4603#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4836#L759 assume !(0 != activate_threads_~tmp___1~0#1); 4942#L759-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4588#L349 assume !(1 == ~t3_pc~0); 4589#L349-2 is_transmit3_triggered_~__retres1~3#1 := 0; 4636#L360 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4422#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4423#L767 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4937#L767-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4938#L368 assume 1 == ~t4_pc~0; 4943#L369 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 4663#L379 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4573#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4574#L775 assume !(0 != activate_threads_~tmp___3~0#1); 4429#L775-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4430#L387 assume !(1 == ~t5_pc~0); 4802#L387-2 is_transmit5_triggered_~__retres1~5#1 := 0; 4803#L398 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4702#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4562#L783 assume !(0 != activate_threads_~tmp___4~0#1); 4563#L783-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4653#L667 assume !(1 == ~M_E~0); 4723#L667-2 assume !(1 == ~T1_E~0); 4894#L672-1 assume !(1 == ~T2_E~0); 4684#L677-1 assume !(1 == ~T3_E~0); 4685#L682-1 assume !(1 == ~T4_E~0); 4870#L687-1 assume !(1 == ~T5_E~0); 4921#L692-1 assume !(1 == ~E_M~0); 4860#L697-1 assume 1 == ~E_1~0;~E_1~0 := 2; 4861#L702-1 assume !(1 == ~E_2~0); 4900#L707-1 assume !(1 == ~E_3~0); 4774#L712-1 assume !(1 == ~E_4~0); 4775#L717-1 assume !(1 == ~E_5~0); 4877#L722-1 assume { :end_inline_reset_delta_events } true; 4437#L928-2 [2022-12-13 22:01:22,282 INFO L750 eck$LassoCheckResult]: Loop: 4437#L928-2 assume !false; 4438#L929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4483#L574 assume !false; 4484#L495 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 4936#L452 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 4639#L484 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 4854#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 4475#L499 assume !(0 != eval_~tmp~0#1); 4476#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4591#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4825#L599-3 assume 0 == ~M_E~0;~M_E~0 := 1; 4826#L599-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4740#L604-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4741#L609-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4812#L614-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4444#L619-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 4445#L624-3 assume !(0 == ~E_M~0); 4820#L629-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4867#L634-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4878#L639-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4879#L644-3 assume 0 == ~E_4~0;~E_4~0 := 1; 4940#L649-3 assume 0 == ~E_5~0;~E_5~0 := 1; 4750#L654-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4751#L292-21 assume 1 == ~m_pc~0; 4828#L293-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 4524#L303-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4525#is_master_triggered_returnLabel#8 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 4623#L743-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4734#L743-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4735#L311-21 assume 1 == ~t1_pc~0; 4920#L312-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4479#L322-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4480#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 4550#L751-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4598#L751-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4599#L330-21 assume !(1 == ~t2_pc~0); 4848#L330-23 is_transmit2_triggered_~__retres1~2#1 := 0; 4817#L341-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4728#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4729#L759-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4531#L759-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4532#L349-21 assume !(1 == ~t3_pc~0); 4771#L349-23 is_transmit3_triggered_~__retres1~3#1 := 0; 4909#L360-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4916#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4881#L767-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4882#L767-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4615#L368-21 assume 1 == ~t4_pc~0; 4497#L369-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 4498#L379-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4915#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4904#L775-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 4420#L775-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4421#L387-21 assume 1 == ~t5_pc~0; 4485#L388-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 4801#L398-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4810#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4811#L783-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 4526#L783-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4527#L667-3 assume !(1 == ~M_E~0); 4514#L667-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4515#L672-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4594#L677-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4595#L682-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4914#L687-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 4634#L692-3 assume 1 == ~E_M~0;~E_M~0 := 2; 4635#L697-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4707#L702-3 assume !(1 == ~E_2~0); 4708#L707-3 assume 1 == ~E_3~0;~E_3~0 := 2; 4827#L712-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4520#L717-3 assume 1 == ~E_5~0;~E_5~0 := 2; 4521#L722-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 4853#L452-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 4450#L484-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 4798#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 4743#L947 assume !(0 == start_simulation_~tmp~3#1); 4744#L947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 4747#L452-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 4711#L484-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 4459#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret18#1;havoc stop_simulation_#t~ret18#1; 4460#L902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4891#L909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4892#stop_simulation_returnLabel#1 start_simulation_#t~ret20#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 4840#L960 assume !(0 != start_simulation_~tmp___0~1#1); 4437#L928-2 [2022-12-13 22:01:22,282 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 22:01:22,282 INFO L85 PathProgramCache]: Analyzing trace with hash 739391428, now seen corresponding path program 1 times [2022-12-13 22:01:22,282 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 22:01:22,282 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [259414874] [2022-12-13 22:01:22,282 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 22:01:22,282 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 22:01:22,288 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 22:01:22,304 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 22:01:22,304 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 22:01:22,304 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [259414874] [2022-12-13 22:01:22,304 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [259414874] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 22:01:22,304 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 22:01:22,304 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 22:01:22,305 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [812731266] [2022-12-13 22:01:22,305 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 22:01:22,305 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 22:01:22,306 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 22:01:22,306 INFO L85 PathProgramCache]: Analyzing trace with hash 1823202674, now seen corresponding path program 1 times [2022-12-13 22:01:22,306 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 22:01:22,306 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1014914295] [2022-12-13 22:01:22,306 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 22:01:22,306 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 22:01:22,315 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 22:01:22,334 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 22:01:22,335 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 22:01:22,335 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1014914295] [2022-12-13 22:01:22,335 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1014914295] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 22:01:22,335 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 22:01:22,335 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 22:01:22,335 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1918247704] [2022-12-13 22:01:22,336 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 22:01:22,336 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 22:01:22,336 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 22:01:22,336 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 22:01:22,337 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 22:01:22,337 INFO L87 Difference]: Start difference. First operand 546 states and 815 transitions. cyclomatic complexity: 270 Second operand has 3 states, 3 states have (on average 24.333333333333332) internal successors, (73), 3 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 22:01:22,350 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 22:01:22,350 INFO L93 Difference]: Finished difference Result 546 states and 814 transitions. [2022-12-13 22:01:22,350 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 546 states and 814 transitions. [2022-12-13 22:01:22,352 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 467 [2022-12-13 22:01:22,354 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 546 states to 546 states and 814 transitions. [2022-12-13 22:01:22,354 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 546 [2022-12-13 22:01:22,354 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 546 [2022-12-13 22:01:22,354 INFO L73 IsDeterministic]: Start isDeterministic. Operand 546 states and 814 transitions. [2022-12-13 22:01:22,355 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 22:01:22,355 INFO L218 hiAutomatonCegarLoop]: Abstraction has 546 states and 814 transitions. [2022-12-13 22:01:22,355 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 546 states and 814 transitions. [2022-12-13 22:01:22,359 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 546 to 546. [2022-12-13 22:01:22,359 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 546 states, 546 states have (on average 1.4908424908424909) internal successors, (814), 545 states have internal predecessors, (814), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 22:01:22,360 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 546 states to 546 states and 814 transitions. [2022-12-13 22:01:22,360 INFO L240 hiAutomatonCegarLoop]: Abstraction has 546 states and 814 transitions. [2022-12-13 22:01:22,361 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 22:01:22,361 INFO L428 stractBuchiCegarLoop]: Abstraction has 546 states and 814 transitions. [2022-12-13 22:01:22,361 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2022-12-13 22:01:22,361 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 546 states and 814 transitions. [2022-12-13 22:01:22,363 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 467 [2022-12-13 22:01:22,363 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 22:01:22,363 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 22:01:22,364 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 22:01:22,364 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 22:01:22,364 INFO L748 eck$LassoCheckResult]: Stem: 5817#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 5818#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 5930#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5931#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6043#L414 assume 1 == ~m_i~0;~m_st~0 := 0; 5880#L414-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5881#L419-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 6027#L424-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 5861#L429-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 5862#L434-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 6023#L439-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5857#L599 assume 0 == ~M_E~0;~M_E~0 := 1; 5858#L599-2 assume !(0 == ~T1_E~0); 5527#L604-1 assume !(0 == ~T2_E~0); 5514#L609-1 assume !(0 == ~T3_E~0); 5515#L614-1 assume !(0 == ~T4_E~0); 5686#L619-1 assume !(0 == ~T5_E~0); 5796#L624-1 assume !(0 == ~E_M~0); 5884#L629-1 assume !(0 == ~E_1~0); 5608#L634-1 assume 0 == ~E_2~0;~E_2~0 := 1; 5609#L639-1 assume !(0 == ~E_3~0); 5985#L644-1 assume !(0 == ~E_4~0); 6000#L649-1 assume !(0 == ~E_5~0); 5569#L654-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5570#L292 assume !(1 == ~m_pc~0); 5699#L292-2 is_master_triggered_~__retres1~0#1 := 0; 5830#L303 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5794#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 5795#L743 assume !(0 != activate_threads_~tmp~1#1); 5641#L743-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5642#L311 assume 1 == ~t1_pc~0; 5771#L312 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 5772#L322 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5560#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 5541#L751 assume !(0 != activate_threads_~tmp___0~0#1); 5542#L751-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5986#L330 assume 1 == ~t2_pc~0; 5798#L331 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5702#L341 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5703#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 5935#L759 assume !(0 != activate_threads_~tmp___1~0#1); 6041#L759-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5687#L349 assume !(1 == ~t3_pc~0); 5688#L349-2 is_transmit3_triggered_~__retres1~3#1 := 0; 5735#L360 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5521#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 5522#L767 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 6036#L767-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6037#L368 assume 1 == ~t4_pc~0; 6042#L369 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5764#L379 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5672#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5673#L775 assume !(0 != activate_threads_~tmp___3~0#1); 5528#L775-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5529#L387 assume !(1 == ~t5_pc~0); 5901#L387-2 is_transmit5_triggered_~__retres1~5#1 := 0; 5902#L398 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5801#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 5661#L783 assume !(0 != activate_threads_~tmp___4~0#1); 5662#L783-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5752#L667 assume !(1 == ~M_E~0); 5822#L667-2 assume !(1 == ~T1_E~0); 5993#L672-1 assume !(1 == ~T2_E~0); 5783#L677-1 assume !(1 == ~T3_E~0); 5784#L682-1 assume !(1 == ~T4_E~0); 5969#L687-1 assume !(1 == ~T5_E~0); 6020#L692-1 assume !(1 == ~E_M~0); 5959#L697-1 assume 1 == ~E_1~0;~E_1~0 := 2; 5960#L702-1 assume !(1 == ~E_2~0); 5999#L707-1 assume !(1 == ~E_3~0); 5873#L712-1 assume !(1 == ~E_4~0); 5874#L717-1 assume !(1 == ~E_5~0); 5976#L722-1 assume { :end_inline_reset_delta_events } true; 5536#L928-2 [2022-12-13 22:01:22,364 INFO L750 eck$LassoCheckResult]: Loop: 5536#L928-2 assume !false; 5537#L929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5582#L574 assume !false; 5583#L495 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 6035#L452 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 5738#L484 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 5953#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 5574#L499 assume !(0 != eval_~tmp~0#1); 5575#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5690#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5924#L599-3 assume 0 == ~M_E~0;~M_E~0 := 1; 5925#L599-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 5840#L604-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 5841#L609-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5911#L614-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5543#L619-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 5544#L624-3 assume !(0 == ~E_M~0); 5919#L629-3 assume 0 == ~E_1~0;~E_1~0 := 1; 5966#L634-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5977#L639-3 assume 0 == ~E_3~0;~E_3~0 := 1; 5978#L644-3 assume 0 == ~E_4~0;~E_4~0 := 1; 6039#L649-3 assume 0 == ~E_5~0;~E_5~0 := 1; 5849#L654-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5850#L292-21 assume 1 == ~m_pc~0; 5927#L293-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 5623#L303-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5624#is_master_triggered_returnLabel#8 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 5722#L743-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 5833#L743-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5834#L311-21 assume 1 == ~t1_pc~0; 6019#L312-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 5578#L322-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5579#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 5649#L751-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 5697#L751-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5698#L330-21 assume 1 == ~t2_pc~0; 5946#L331-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5916#L341-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5828#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 5829#L759-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 5630#L759-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5631#L349-21 assume !(1 == ~t3_pc~0); 5870#L349-23 is_transmit3_triggered_~__retres1~3#1 := 0; 6008#L360-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6015#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 5980#L767-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 5981#L767-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5714#L368-21 assume 1 == ~t4_pc~0; 5596#L369-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5597#L379-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6014#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 6003#L775-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 5519#L775-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5520#L387-21 assume 1 == ~t5_pc~0; 5584#L388-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 5900#L398-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5909#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 5910#L783-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 5625#L783-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5626#L667-3 assume !(1 == ~M_E~0); 5613#L667-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5614#L672-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5695#L677-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 5696#L682-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 6013#L687-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 5733#L692-3 assume 1 == ~E_M~0;~E_M~0 := 2; 5734#L697-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5806#L702-3 assume !(1 == ~E_2~0); 5807#L707-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5926#L712-3 assume 1 == ~E_4~0;~E_4~0 := 2; 5619#L717-3 assume 1 == ~E_5~0;~E_5~0 := 2; 5620#L722-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 5952#L452-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 5549#L484-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 5897#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 5842#L947 assume !(0 == start_simulation_~tmp~3#1); 5843#L947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 5846#L452-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 5810#L484-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 5558#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret18#1;havoc stop_simulation_#t~ret18#1; 5559#L902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5990#L909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5991#stop_simulation_returnLabel#1 start_simulation_#t~ret20#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 5939#L960 assume !(0 != start_simulation_~tmp___0~1#1); 5536#L928-2 [2022-12-13 22:01:22,364 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 22:01:22,365 INFO L85 PathProgramCache]: Analyzing trace with hash 793784326, now seen corresponding path program 1 times [2022-12-13 22:01:22,365 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 22:01:22,365 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [55131453] [2022-12-13 22:01:22,365 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 22:01:22,365 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 22:01:22,372 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 22:01:22,406 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 22:01:22,406 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 22:01:22,406 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [55131453] [2022-12-13 22:01:22,407 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [55131453] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 22:01:22,407 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 22:01:22,407 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-12-13 22:01:22,407 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1188681421] [2022-12-13 22:01:22,407 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 22:01:22,407 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 22:01:22,408 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 22:01:22,408 INFO L85 PathProgramCache]: Analyzing trace with hash 354999345, now seen corresponding path program 2 times [2022-12-13 22:01:22,408 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 22:01:22,408 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2039331735] [2022-12-13 22:01:22,409 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 22:01:22,409 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 22:01:22,417 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 22:01:22,435 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 22:01:22,435 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 22:01:22,435 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2039331735] [2022-12-13 22:01:22,435 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2039331735] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 22:01:22,435 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 22:01:22,436 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 22:01:22,436 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1664888785] [2022-12-13 22:01:22,436 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 22:01:22,436 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 22:01:22,436 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 22:01:22,437 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 22:01:22,437 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 22:01:22,437 INFO L87 Difference]: Start difference. First operand 546 states and 814 transitions. cyclomatic complexity: 269 Second operand has 3 states, 3 states have (on average 24.333333333333332) internal successors, (73), 2 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 22:01:22,469 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 22:01:22,469 INFO L93 Difference]: Finished difference Result 969 states and 1439 transitions. [2022-12-13 22:01:22,469 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 969 states and 1439 transitions. [2022-12-13 22:01:22,474 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 890 [2022-12-13 22:01:22,477 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 969 states to 969 states and 1439 transitions. [2022-12-13 22:01:22,477 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 969 [2022-12-13 22:01:22,477 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 969 [2022-12-13 22:01:22,478 INFO L73 IsDeterministic]: Start isDeterministic. Operand 969 states and 1439 transitions. [2022-12-13 22:01:22,478 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 22:01:22,479 INFO L218 hiAutomatonCegarLoop]: Abstraction has 969 states and 1439 transitions. [2022-12-13 22:01:22,479 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 969 states and 1439 transitions. [2022-12-13 22:01:22,490 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 969 to 969. [2022-12-13 22:01:22,491 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 969 states, 969 states have (on average 1.4850361197110422) internal successors, (1439), 968 states have internal predecessors, (1439), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 22:01:22,493 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 969 states to 969 states and 1439 transitions. [2022-12-13 22:01:22,493 INFO L240 hiAutomatonCegarLoop]: Abstraction has 969 states and 1439 transitions. [2022-12-13 22:01:22,493 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 22:01:22,494 INFO L428 stractBuchiCegarLoop]: Abstraction has 969 states and 1439 transitions. [2022-12-13 22:01:22,494 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2022-12-13 22:01:22,494 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 969 states and 1439 transitions. [2022-12-13 22:01:22,499 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 890 [2022-12-13 22:01:22,499 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 22:01:22,500 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 22:01:22,500 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 22:01:22,500 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 22:01:22,501 INFO L748 eck$LassoCheckResult]: Stem: 7342#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 7343#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 7455#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 7456#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7584#L414 assume 1 == ~m_i~0;~m_st~0 := 0; 7405#L414-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7406#L419-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 7567#L424-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 7386#L429-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 7387#L434-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 7564#L439-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7382#L599 assume !(0 == ~M_E~0); 7383#L599-2 assume !(0 == ~T1_E~0); 7049#L604-1 assume !(0 == ~T2_E~0); 7036#L609-1 assume !(0 == ~T3_E~0); 7037#L614-1 assume !(0 == ~T4_E~0); 7209#L619-1 assume !(0 == ~T5_E~0); 7320#L624-1 assume !(0 == ~E_M~0); 7409#L629-1 assume !(0 == ~E_1~0); 7130#L634-1 assume 0 == ~E_2~0;~E_2~0 := 1; 7131#L639-1 assume !(0 == ~E_3~0); 7511#L644-1 assume !(0 == ~E_4~0); 7528#L649-1 assume !(0 == ~E_5~0); 7091#L654-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7092#L292 assume !(1 == ~m_pc~0); 7223#L292-2 is_master_triggered_~__retres1~0#1 := 0; 7355#L303 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7318#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 7319#L743 assume !(0 != activate_threads_~tmp~1#1); 7163#L743-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7164#L311 assume 1 == ~t1_pc~0; 7295#L312 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 7296#L322 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7082#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 7063#L751 assume !(0 != activate_threads_~tmp___0~0#1); 7064#L751-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7514#L330 assume 1 == ~t2_pc~0; 7322#L331 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 7226#L341 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7227#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 7460#L759 assume !(0 != activate_threads_~tmp___1~0#1); 7582#L759-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7212#L349 assume !(1 == ~t3_pc~0); 7213#L349-2 is_transmit3_triggered_~__retres1~3#1 := 0; 7259#L360 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7043#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 7044#L767 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 7577#L767-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7578#L368 assume 1 == ~t4_pc~0; 7583#L369 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 7288#L379 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7195#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 7196#L775 assume !(0 != activate_threads_~tmp___3~0#1); 7050#L775-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7051#L387 assume !(1 == ~t5_pc~0); 7426#L387-2 is_transmit5_triggered_~__retres1~5#1 := 0; 7427#L398 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7325#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 7184#L783 assume !(0 != activate_threads_~tmp___4~0#1); 7185#L783-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7276#L667 assume !(1 == ~M_E~0); 7347#L667-2 assume !(1 == ~T1_E~0); 7521#L672-1 assume !(1 == ~T2_E~0); 7307#L677-1 assume !(1 == ~T3_E~0); 7308#L682-1 assume !(1 == ~T4_E~0); 7495#L687-1 assume !(1 == ~T5_E~0); 7559#L692-1 assume !(1 == ~E_M~0); 7485#L697-1 assume 1 == ~E_1~0;~E_1~0 := 2; 7486#L702-1 assume !(1 == ~E_2~0); 7527#L707-1 assume !(1 == ~E_3~0); 7398#L712-1 assume !(1 == ~E_4~0); 7399#L717-1 assume !(1 == ~E_5~0); 7502#L722-1 assume { :end_inline_reset_delta_events } true; 7058#L928-2 [2022-12-13 22:01:22,501 INFO L750 eck$LassoCheckResult]: Loop: 7058#L928-2 assume !false; 7059#L929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 7104#L574 assume !false; 7105#L495 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 7576#L452 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 7566#L484 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 7479#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 7096#L499 assume !(0 != eval_~tmp~0#1); 7097#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 7557#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 7447#L599-3 assume !(0 == ~M_E~0); 7448#L599-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 7364#L604-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7365#L609-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 7433#L614-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 7065#L619-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 7066#L624-3 assume !(0 == ~E_M~0); 7444#L629-3 assume 0 == ~E_1~0;~E_1~0 := 1; 7492#L634-3 assume 0 == ~E_2~0;~E_2~0 := 1; 7503#L639-3 assume 0 == ~E_3~0;~E_3~0 := 1; 7504#L644-3 assume 0 == ~E_4~0;~E_4~0 := 1; 7580#L649-3 assume 0 == ~E_5~0;~E_5~0 := 1; 7374#L654-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7375#L292-21 assume 1 == ~m_pc~0; 7452#L293-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 7145#L303-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7146#is_master_triggered_returnLabel#8 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 7246#L743-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 7358#L743-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7359#L311-21 assume 1 == ~t1_pc~0; 7558#L312-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 7100#L322-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7101#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 7632#L751-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 7631#L751-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7630#L330-21 assume 1 == ~t2_pc~0; 7628#L331-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 7627#L341-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7626#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 7625#L759-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 7624#L759-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7623#L349-21 assume 1 == ~t3_pc~0; 7600#L350-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 7542#L360-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7622#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 7506#L767-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 7507#L767-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7238#L368-21 assume !(1 == ~t4_pc~0); 7120#L368-23 is_transmit4_triggered_~__retres1~4#1 := 0; 7119#L379-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7617#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 7533#L775-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 7534#L775-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7616#L387-21 assume !(1 == ~t5_pc~0); 7614#L387-23 is_transmit5_triggered_~__retres1~5#1 := 0; 7520#L398-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7435#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 7436#L783-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 7147#L783-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7148#L667-3 assume !(1 == ~M_E~0); 7135#L667-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 7136#L672-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7219#L677-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 7220#L682-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 7547#L687-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 7257#L692-3 assume 1 == ~E_M~0;~E_M~0 := 2; 7258#L697-3 assume 1 == ~E_1~0;~E_1~0 := 2; 7331#L702-3 assume !(1 == ~E_2~0); 7332#L707-3 assume 1 == ~E_3~0;~E_3~0 := 2; 7451#L712-3 assume 1 == ~E_4~0;~E_4~0 := 2; 7141#L717-3 assume 1 == ~E_5~0;~E_5~0 := 2; 7142#L722-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 7478#L452-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 7071#L484-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 7422#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 7367#L947 assume !(0 == start_simulation_~tmp~3#1); 7368#L947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 7372#L452-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 7335#L484-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 7080#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret18#1;havoc stop_simulation_#t~ret18#1; 7081#L902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 7516#L909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 7517#stop_simulation_returnLabel#1 start_simulation_#t~ret20#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 7465#L960 assume !(0 != start_simulation_~tmp___0~1#1); 7058#L928-2 [2022-12-13 22:01:22,501 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 22:01:22,501 INFO L85 PathProgramCache]: Analyzing trace with hash 1473056580, now seen corresponding path program 1 times [2022-12-13 22:01:22,501 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 22:01:22,502 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1764001413] [2022-12-13 22:01:22,502 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 22:01:22,502 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 22:01:22,507 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 22:01:22,528 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 22:01:22,528 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 22:01:22,528 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1764001413] [2022-12-13 22:01:22,528 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1764001413] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 22:01:22,529 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 22:01:22,529 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-12-13 22:01:22,529 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [459778504] [2022-12-13 22:01:22,529 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 22:01:22,529 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 22:01:22,529 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 22:01:22,529 INFO L85 PathProgramCache]: Analyzing trace with hash -1302519120, now seen corresponding path program 1 times [2022-12-13 22:01:22,530 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 22:01:22,530 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [756039715] [2022-12-13 22:01:22,530 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 22:01:22,530 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 22:01:22,537 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 22:01:22,556 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 22:01:22,556 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 22:01:22,557 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [756039715] [2022-12-13 22:01:22,557 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [756039715] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 22:01:22,557 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 22:01:22,557 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 22:01:22,557 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1055396488] [2022-12-13 22:01:22,557 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 22:01:22,557 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 22:01:22,558 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 22:01:22,558 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 22:01:22,558 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 22:01:22,558 INFO L87 Difference]: Start difference. First operand 969 states and 1439 transitions. cyclomatic complexity: 471 Second operand has 3 states, 3 states have (on average 24.333333333333332) internal successors, (73), 2 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 22:01:22,597 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 22:01:22,597 INFO L93 Difference]: Finished difference Result 969 states and 1417 transitions. [2022-12-13 22:01:22,597 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 969 states and 1417 transitions. [2022-12-13 22:01:22,601 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 890 [2022-12-13 22:01:22,604 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 969 states to 969 states and 1417 transitions. [2022-12-13 22:01:22,604 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 969 [2022-12-13 22:01:22,605 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 969 [2022-12-13 22:01:22,605 INFO L73 IsDeterministic]: Start isDeterministic. Operand 969 states and 1417 transitions. [2022-12-13 22:01:22,605 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 22:01:22,605 INFO L218 hiAutomatonCegarLoop]: Abstraction has 969 states and 1417 transitions. [2022-12-13 22:01:22,606 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 969 states and 1417 transitions. [2022-12-13 22:01:22,615 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 969 to 969. [2022-12-13 22:01:22,616 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 969 states, 969 states have (on average 1.4623323013415892) internal successors, (1417), 968 states have internal predecessors, (1417), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 22:01:22,617 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 969 states to 969 states and 1417 transitions. [2022-12-13 22:01:22,618 INFO L240 hiAutomatonCegarLoop]: Abstraction has 969 states and 1417 transitions. [2022-12-13 22:01:22,618 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 22:01:22,618 INFO L428 stractBuchiCegarLoop]: Abstraction has 969 states and 1417 transitions. [2022-12-13 22:01:22,618 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2022-12-13 22:01:22,618 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 969 states and 1417 transitions. [2022-12-13 22:01:22,624 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 890 [2022-12-13 22:01:22,624 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 22:01:22,624 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 22:01:22,625 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 22:01:22,625 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 22:01:22,625 INFO L748 eck$LassoCheckResult]: Stem: 9292#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 9293#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 9411#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 9412#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 9555#L414 assume 1 == ~m_i~0;~m_st~0 := 0; 9360#L414-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 9361#L419-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 9534#L424-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 9337#L429-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 9338#L434-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 9530#L439-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 9333#L599 assume !(0 == ~M_E~0); 9334#L599-2 assume !(0 == ~T1_E~0); 8994#L604-1 assume !(0 == ~T2_E~0); 8981#L609-1 assume !(0 == ~T3_E~0); 8982#L614-1 assume !(0 == ~T4_E~0); 9156#L619-1 assume !(0 == ~T5_E~0); 9271#L624-1 assume !(0 == ~E_M~0); 9364#L629-1 assume !(0 == ~E_1~0); 9076#L634-1 assume !(0 == ~E_2~0); 9077#L639-1 assume !(0 == ~E_3~0); 9471#L644-1 assume !(0 == ~E_4~0); 9490#L649-1 assume !(0 == ~E_5~0); 9036#L654-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9037#L292 assume !(1 == ~m_pc~0); 9170#L292-2 is_master_triggered_~__retres1~0#1 := 0; 9305#L303 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9269#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 9270#L743 assume !(0 != activate_threads_~tmp~1#1); 9109#L743-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9110#L311 assume 1 == ~t1_pc~0; 9247#L312 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 9248#L322 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9027#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 9008#L751 assume !(0 != activate_threads_~tmp___0~0#1); 9009#L751-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9474#L330 assume !(1 == ~t2_pc~0); 9274#L330-2 is_transmit2_triggered_~__retres1~2#1 := 0; 9174#L341 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9175#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 9416#L759 assume !(0 != activate_threads_~tmp___1~0#1); 9553#L759-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9159#L349 assume !(1 == ~t3_pc~0); 9160#L349-2 is_transmit3_triggered_~__retres1~3#1 := 0; 9209#L360 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8988#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 8989#L767 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 9548#L767-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9549#L368 assume 1 == ~t4_pc~0; 9554#L369 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 9240#L379 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9142#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 9143#L775 assume !(0 != activate_threads_~tmp___3~0#1); 8995#L775-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8996#L387 assume !(1 == ~t5_pc~0); 9382#L387-2 is_transmit5_triggered_~__retres1~5#1 := 0; 9383#L398 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9276#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 9129#L783 assume !(0 != activate_threads_~tmp___4~0#1); 9130#L783-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9226#L667 assume !(1 == ~M_E~0); 9297#L667-2 assume !(1 == ~T1_E~0); 9482#L672-1 assume !(1 == ~T2_E~0); 9258#L677-1 assume !(1 == ~T3_E~0); 9259#L682-1 assume !(1 == ~T4_E~0); 9455#L687-1 assume !(1 == ~T5_E~0); 9522#L692-1 assume !(1 == ~E_M~0); 9441#L697-1 assume 1 == ~E_1~0;~E_1~0 := 2; 9442#L702-1 assume !(1 == ~E_2~0); 9489#L707-1 assume !(1 == ~E_3~0); 9353#L712-1 assume !(1 == ~E_4~0); 9354#L717-1 assume !(1 == ~E_5~0); 9462#L722-1 assume { :end_inline_reset_delta_events } true; 9003#L928-2 [2022-12-13 22:01:22,625 INFO L750 eck$LassoCheckResult]: Loop: 9003#L928-2 assume !false; 9004#L929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 9051#L574 assume !false; 9052#L495 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 9545#L452 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 9533#L484 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 9435#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 9041#L499 assume !(0 != eval_~tmp~0#1); 9043#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 9519#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 9405#L599-3 assume !(0 == ~M_E~0); 9406#L599-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 9621#L604-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 9620#L609-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 9619#L614-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 9618#L619-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 9617#L624-3 assume !(0 == ~E_M~0); 9616#L629-3 assume 0 == ~E_1~0;~E_1~0 := 1; 9615#L634-3 assume !(0 == ~E_2~0); 9463#L639-3 assume 0 == ~E_3~0;~E_3~0 := 1; 9464#L644-3 assume 0 == ~E_4~0;~E_4~0 := 1; 9551#L649-3 assume 0 == ~E_5~0;~E_5~0 := 1; 9326#L654-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9327#L292-21 assume 1 == ~m_pc~0; 9408#L293-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 9091#L303-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9092#is_master_triggered_returnLabel#8 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 9196#L743-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 9308#L743-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9309#L311-21 assume !(1 == ~t1_pc~0); 9520#L311-23 is_transmit1_triggered_~__retres1~1#1 := 0; 9603#L322-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9602#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 9601#L751-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 9600#L751-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9599#L330-21 assume !(1 == ~t2_pc~0); 9535#L330-23 is_transmit2_triggered_~__retres1~2#1 := 0; 9397#L341-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9303#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 9304#L759-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 9098#L759-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9099#L349-21 assume 1 == ~t3_pc~0; 9575#L350-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 9502#L360-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9593#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 9466#L767-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 9467#L767-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9186#L368-21 assume 1 == ~t4_pc~0; 9187#L369-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 9509#L379-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9510#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 9544#L775-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 8986#L775-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8987#L387-21 assume 1 == ~t5_pc~0; 9053#L388-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 9381#L398-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9390#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 9391#L783-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 9093#L783-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9094#L667-3 assume !(1 == ~M_E~0); 9081#L667-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 9082#L672-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 9164#L677-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 9165#L682-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 9508#L687-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 9207#L692-3 assume 1 == ~E_M~0;~E_M~0 := 2; 9208#L697-3 assume 1 == ~E_1~0;~E_1~0 := 2; 9281#L702-3 assume !(1 == ~E_2~0); 9282#L707-3 assume 1 == ~E_3~0;~E_3~0 := 2; 9407#L712-3 assume 1 == ~E_4~0;~E_4~0 := 2; 9087#L717-3 assume 1 == ~E_5~0;~E_5~0 := 2; 9088#L722-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 9434#L452-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 9016#L484-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 9378#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 9319#L947 assume !(0 == start_simulation_~tmp~3#1); 9320#L947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 9323#L452-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 9285#L484-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 9025#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret18#1;havoc stop_simulation_#t~ret18#1; 9026#L902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 9476#L909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 9477#stop_simulation_returnLabel#1 start_simulation_#t~ret20#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 9420#L960 assume !(0 != start_simulation_~tmp___0~1#1); 9003#L928-2 [2022-12-13 22:01:22,626 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 22:01:22,626 INFO L85 PathProgramCache]: Analyzing trace with hash -820631741, now seen corresponding path program 1 times [2022-12-13 22:01:22,626 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 22:01:22,626 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [760468170] [2022-12-13 22:01:22,626 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 22:01:22,626 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 22:01:22,632 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 22:01:22,661 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 22:01:22,661 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 22:01:22,662 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [760468170] [2022-12-13 22:01:22,662 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [760468170] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 22:01:22,662 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 22:01:22,662 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 22:01:22,662 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1109500033] [2022-12-13 22:01:22,662 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 22:01:22,663 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 22:01:22,663 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 22:01:22,663 INFO L85 PathProgramCache]: Analyzing trace with hash -1028200850, now seen corresponding path program 1 times [2022-12-13 22:01:22,663 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 22:01:22,663 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [537507327] [2022-12-13 22:01:22,663 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 22:01:22,664 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 22:01:22,670 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 22:01:22,699 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 22:01:22,699 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 22:01:22,699 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [537507327] [2022-12-13 22:01:22,699 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [537507327] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 22:01:22,699 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 22:01:22,699 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-12-13 22:01:22,700 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [114560249] [2022-12-13 22:01:22,700 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 22:01:22,700 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 22:01:22,700 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 22:01:22,700 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 22:01:22,701 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 22:01:22,701 INFO L87 Difference]: Start difference. First operand 969 states and 1417 transitions. cyclomatic complexity: 449 Second operand has 4 states, 4 states have (on average 18.25) internal successors, (73), 3 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 22:01:22,871 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 22:01:22,871 INFO L93 Difference]: Finished difference Result 2592 states and 3726 transitions. [2022-12-13 22:01:22,871 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2592 states and 3726 transitions. [2022-12-13 22:01:22,881 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2417 [2022-12-13 22:01:22,887 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2592 states to 2592 states and 3726 transitions. [2022-12-13 22:01:22,887 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2592 [2022-12-13 22:01:22,889 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2592 [2022-12-13 22:01:22,889 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2592 states and 3726 transitions. [2022-12-13 22:01:22,891 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 22:01:22,891 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2592 states and 3726 transitions. [2022-12-13 22:01:22,893 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2592 states and 3726 transitions. [2022-12-13 22:01:22,912 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2592 to 2432. [2022-12-13 22:01:22,915 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2432 states, 2432 states have (on average 1.444078947368421) internal successors, (3512), 2431 states have internal predecessors, (3512), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 22:01:22,919 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2432 states to 2432 states and 3512 transitions. [2022-12-13 22:01:22,919 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2432 states and 3512 transitions. [2022-12-13 22:01:22,920 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 22:01:22,920 INFO L428 stractBuchiCegarLoop]: Abstraction has 2432 states and 3512 transitions. [2022-12-13 22:01:22,920 INFO L335 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2022-12-13 22:01:22,920 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2432 states and 3512 transitions. [2022-12-13 22:01:22,929 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2345 [2022-12-13 22:01:22,929 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 22:01:22,929 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 22:01:22,930 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 22:01:22,930 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 22:01:22,930 INFO L748 eck$LassoCheckResult]: Stem: 12856#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 12857#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 12981#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 12982#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 13139#L414 assume 1 == ~m_i~0;~m_st~0 := 0; 12924#L414-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 12925#L419-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 13111#L424-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 12900#L429-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 12901#L434-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 13103#L439-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 12896#L599 assume !(0 == ~M_E~0); 12897#L599-2 assume !(0 == ~T1_E~0); 12567#L604-1 assume !(0 == ~T2_E~0); 12554#L609-1 assume !(0 == ~T3_E~0); 12555#L614-1 assume !(0 == ~T4_E~0); 12726#L619-1 assume !(0 == ~T5_E~0); 12834#L624-1 assume !(0 == ~E_M~0); 12928#L629-1 assume !(0 == ~E_1~0); 12647#L634-1 assume !(0 == ~E_2~0); 12648#L639-1 assume !(0 == ~E_3~0); 13040#L644-1 assume !(0 == ~E_4~0); 13061#L649-1 assume !(0 == ~E_5~0); 12609#L654-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12610#L292 assume !(1 == ~m_pc~0); 12739#L292-2 is_master_triggered_~__retres1~0#1 := 0; 12870#L303 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12830#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 12831#L743 assume !(0 != activate_threads_~tmp~1#1); 12681#L743-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12682#L311 assume !(1 == ~t1_pc~0); 13039#L311-2 is_transmit1_triggered_~__retres1~1#1 := 0; 12937#L322 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12600#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 12581#L751 assume !(0 != activate_threads_~tmp___0~0#1); 12582#L751-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 13041#L330 assume !(1 == ~t2_pc~0); 12838#L330-2 is_transmit2_triggered_~__retres1~2#1 := 0; 12740#L341 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12741#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 12986#L759 assume !(0 != activate_threads_~tmp___1~0#1); 13135#L759-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12727#L349 assume !(1 == ~t3_pc~0); 12728#L349-2 is_transmit3_triggered_~__retres1~3#1 := 0; 12775#L360 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12558#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 12559#L767 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 13129#L767-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13130#L368 assume 1 == ~t4_pc~0; 13136#L369 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 12802#L379 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12711#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 12712#L775 assume !(0 != activate_threads_~tmp___3~0#1); 12568#L775-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 12569#L387 assume !(1 == ~t5_pc~0); 12949#L387-2 is_transmit5_triggered_~__retres1~5#1 := 0; 12950#L398 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12840#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 12698#L783 assume !(0 != activate_threads_~tmp___4~0#1); 12699#L783-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12793#L667 assume !(1 == ~M_E~0); 12862#L667-2 assume !(1 == ~T1_E~0); 13048#L672-1 assume !(1 == ~T2_E~0); 12821#L677-1 assume !(1 == ~T3_E~0); 12822#L682-1 assume !(1 == ~T4_E~0); 13023#L687-1 assume !(1 == ~T5_E~0); 13098#L692-1 assume !(1 == ~E_M~0); 13011#L697-1 assume 1 == ~E_1~0;~E_1~0 := 2; 13012#L702-1 assume !(1 == ~E_2~0); 13059#L707-1 assume !(1 == ~E_3~0); 12915#L712-1 assume !(1 == ~E_4~0); 12916#L717-1 assume !(1 == ~E_5~0); 13030#L722-1 assume { :end_inline_reset_delta_events } true; 12576#L928-2 [2022-12-13 22:01:22,930 INFO L750 eck$LassoCheckResult]: Loop: 12576#L928-2 assume !false; 12577#L929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 14698#L574 assume !false; 14697#L495 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 14693#L452 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 13107#L484 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 13005#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 12614#L499 assume !(0 != eval_~tmp~0#1); 12616#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 12730#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 14687#L599-3 assume !(0 == ~M_E~0); 14686#L599-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 14685#L604-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 14684#L609-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 14683#L614-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 14682#L619-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 14681#L624-3 assume !(0 == ~E_M~0); 14680#L629-3 assume 0 == ~E_1~0;~E_1~0 := 1; 13094#L634-3 assume !(0 == ~E_2~0); 13031#L639-3 assume 0 == ~E_3~0;~E_3~0 := 1; 13032#L644-3 assume 0 == ~E_4~0;~E_4~0 := 1; 13132#L649-3 assume 0 == ~E_5~0;~E_5~0 := 1; 13165#L654-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 14676#L292-21 assume !(1 == ~m_pc~0); 14675#L292-23 is_master_triggered_~__retres1~0#1 := 0; 14674#L303-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 14673#is_master_triggered_returnLabel#8 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 14672#L743-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 14671#L743-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 13096#L311-21 assume !(1 == ~t1_pc~0); 12805#L311-23 is_transmit1_triggered_~__retres1~1#1 := 0; 12619#L322-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12620#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 12689#L751-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 12737#L751-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12738#L330-21 assume !(1 == ~t2_pc~0); 13000#L330-23 is_transmit2_triggered_~__retres1~2#1 := 0; 14663#L341-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12867#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 12868#L759-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 12672#L759-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12673#L349-21 assume !(1 == ~t3_pc~0); 14659#L349-23 is_transmit3_triggered_~__retres1~3#1 := 0; 14658#L360-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14657#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 14656#L767-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 14655#L767-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12754#L368-21 assume 1 == ~t4_pc~0; 12636#L369-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 12637#L379-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 13084#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 13069#L775-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 12556#L775-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 12557#L387-21 assume 1 == ~t5_pc~0; 12625#L388-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 12948#L398-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12956#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 12957#L783-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 12665#L783-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12666#L667-3 assume !(1 == ~M_E~0); 12871#L667-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 14862#L672-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 14860#L677-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 14858#L682-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 14856#L687-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 14854#L692-3 assume 1 == ~E_M~0;~E_M~0 := 2; 14852#L697-3 assume 1 == ~E_1~0;~E_1~0 := 2; 14850#L702-3 assume !(1 == ~E_2~0); 14848#L707-3 assume 1 == ~E_3~0;~E_3~0 := 2; 14847#L712-3 assume 1 == ~E_4~0;~E_4~0 := 2; 14844#L717-3 assume 1 == ~E_5~0;~E_5~0 := 2; 14842#L722-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 14805#L452-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 14799#L484-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 14797#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 14795#L947 assume !(0 == start_simulation_~tmp~3#1); 14793#L947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 14787#L452-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 14781#L484-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 14779#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret18#1;havoc stop_simulation_#t~ret18#1; 13082#L902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 13046#L909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 13047#stop_simulation_returnLabel#1 start_simulation_#t~ret20#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 12991#L960 assume !(0 != start_simulation_~tmp___0~1#1); 12576#L928-2 [2022-12-13 22:01:22,931 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 22:01:22,931 INFO L85 PathProgramCache]: Analyzing trace with hash 1077898564, now seen corresponding path program 1 times [2022-12-13 22:01:22,931 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 22:01:22,931 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [916794208] [2022-12-13 22:01:22,931 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 22:01:22,931 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 22:01:22,939 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 22:01:22,968 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 22:01:22,968 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 22:01:22,968 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [916794208] [2022-12-13 22:01:22,968 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [916794208] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 22:01:22,968 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 22:01:22,969 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-12-13 22:01:22,969 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1700371446] [2022-12-13 22:01:22,969 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 22:01:22,969 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 22:01:22,969 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 22:01:22,970 INFO L85 PathProgramCache]: Analyzing trace with hash 1898861616, now seen corresponding path program 1 times [2022-12-13 22:01:22,970 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 22:01:22,970 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1141056810] [2022-12-13 22:01:22,970 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 22:01:22,970 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 22:01:22,976 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 22:01:23,004 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 22:01:23,004 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 22:01:23,004 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1141056810] [2022-12-13 22:01:23,004 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1141056810] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 22:01:23,004 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 22:01:23,004 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-12-13 22:01:23,005 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1437655011] [2022-12-13 22:01:23,005 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 22:01:23,005 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 22:01:23,005 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 22:01:23,005 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-12-13 22:01:23,005 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-12-13 22:01:23,006 INFO L87 Difference]: Start difference. First operand 2432 states and 3512 transitions. cyclomatic complexity: 1082 Second operand has 5 states, 5 states have (on average 14.6) internal successors, (73), 5 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 22:01:23,179 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 22:01:23,180 INFO L93 Difference]: Finished difference Result 6064 states and 8790 transitions. [2022-12-13 22:01:23,180 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6064 states and 8790 transitions. [2022-12-13 22:01:23,219 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 5900 [2022-12-13 22:01:23,243 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6064 states to 6064 states and 8790 transitions. [2022-12-13 22:01:23,243 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6064 [2022-12-13 22:01:23,248 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6064 [2022-12-13 22:01:23,248 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6064 states and 8790 transitions. [2022-12-13 22:01:23,257 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 22:01:23,257 INFO L218 hiAutomatonCegarLoop]: Abstraction has 6064 states and 8790 transitions. [2022-12-13 22:01:23,262 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6064 states and 8790 transitions. [2022-12-13 22:01:23,317 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6064 to 2552. [2022-12-13 22:01:23,322 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2552 states, 2552 states have (on average 1.4231974921630095) internal successors, (3632), 2551 states have internal predecessors, (3632), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 22:01:23,328 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2552 states to 2552 states and 3632 transitions. [2022-12-13 22:01:23,329 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2552 states and 3632 transitions. [2022-12-13 22:01:23,329 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-12-13 22:01:23,329 INFO L428 stractBuchiCegarLoop]: Abstraction has 2552 states and 3632 transitions. [2022-12-13 22:01:23,330 INFO L335 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2022-12-13 22:01:23,330 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2552 states and 3632 transitions. [2022-12-13 22:01:23,338 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2462 [2022-12-13 22:01:23,339 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 22:01:23,339 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 22:01:23,340 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 22:01:23,340 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 22:01:23,340 INFO L748 eck$LassoCheckResult]: Stem: 21385#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 21386#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 21524#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 21525#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 21725#L414 assume 1 == ~m_i~0;~m_st~0 := 0; 21458#L414-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 21459#L419-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 21686#L424-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 21434#L429-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 21435#L434-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 21679#L439-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 21430#L599 assume !(0 == ~M_E~0); 21431#L599-2 assume !(0 == ~T1_E~0); 21078#L604-1 assume !(0 == ~T2_E~0); 21065#L609-1 assume !(0 == ~T3_E~0); 21066#L614-1 assume !(0 == ~T4_E~0); 21240#L619-1 assume !(0 == ~T5_E~0); 21359#L624-1 assume !(0 == ~E_M~0); 21464#L629-1 assume !(0 == ~E_1~0); 21160#L634-1 assume !(0 == ~E_2~0); 21161#L639-1 assume !(0 == ~E_3~0); 21606#L644-1 assume !(0 == ~E_4~0); 21631#L649-1 assume !(0 == ~E_5~0); 21121#L654-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 21122#L292 assume !(1 == ~m_pc~0); 21253#L292-2 is_master_triggered_~__retres1~0#1 := 0; 21398#L303 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 21357#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 21358#L743 assume !(0 != activate_threads_~tmp~1#1); 21194#L743-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 21195#L311 assume !(1 == ~t1_pc~0); 21604#L311-2 is_transmit1_triggered_~__retres1~1#1 := 0; 21473#L322 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 21112#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 21093#L751 assume !(0 != activate_threads_~tmp___0~0#1); 21094#L751-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 21609#L330 assume !(1 == ~t2_pc~0); 21363#L330-2 is_transmit2_triggered_~__retres1~2#1 := 0; 21256#L341 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 21257#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 21530#L759 assume !(0 != activate_threads_~tmp___1~0#1); 21719#L759-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 21242#L349 assume !(1 == ~t3_pc~0); 21243#L349-2 is_transmit3_triggered_~__retres1~3#1 := 0; 21565#L360 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 21566#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 21790#L767 assume !(0 != activate_threads_~tmp___2~0#1); 21714#L767-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 21715#L368 assume 1 == ~t4_pc~0; 21724#L369 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 21326#L379 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 21225#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 21226#L775 assume !(0 != activate_threads_~tmp___3~0#1); 21079#L775-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 21080#L387 assume !(1 == ~t5_pc~0); 21491#L387-2 is_transmit5_triggered_~__retres1~5#1 := 0; 21492#L398 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 21365#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 21212#L783 assume !(0 != activate_threads_~tmp___4~0#1); 21213#L783-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21308#L667 assume !(1 == ~M_E~0); 21390#L667-2 assume !(1 == ~T1_E~0); 21616#L672-1 assume !(1 == ~T2_E~0); 21343#L677-1 assume !(1 == ~T3_E~0); 21344#L682-1 assume !(1 == ~T4_E~0); 21580#L687-1 assume !(1 == ~T5_E~0); 21671#L692-1 assume !(1 == ~E_M~0); 21563#L697-1 assume 1 == ~E_1~0;~E_1~0 := 2; 21564#L702-1 assume !(1 == ~E_2~0); 21628#L707-1 assume !(1 == ~E_3~0); 21450#L712-1 assume !(1 == ~E_4~0); 21451#L717-1 assume !(1 == ~E_5~0); 21590#L722-1 assume { :end_inline_reset_delta_events } true; 21087#L928-2 [2022-12-13 22:01:23,340 INFO L750 eck$LassoCheckResult]: Loop: 21087#L928-2 assume !false; 21088#L929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 21134#L574 assume !false; 21135#L495 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 21709#L452 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 21293#L484 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 21553#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 21126#L499 assume !(0 != eval_~tmp~0#1); 21127#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 21241#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 21513#L599-3 assume !(0 == ~M_E~0); 21514#L599-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 21408#L604-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 21409#L609-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 21500#L614-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 21095#L619-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 21096#L624-3 assume !(0 == ~E_M~0); 21510#L629-3 assume 0 == ~E_1~0;~E_1~0 := 1; 21576#L634-3 assume !(0 == ~E_2~0); 21591#L639-3 assume 0 == ~E_3~0;~E_3~0 := 1; 21592#L644-3 assume 0 == ~E_4~0;~E_4~0 := 1; 21717#L649-3 assume 0 == ~E_5~0;~E_5~0 := 1; 21420#L654-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 21421#L292-21 assume !(1 == ~m_pc~0); 21560#L292-23 is_master_triggered_~__retres1~0#1 := 0; 23610#L303-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 23609#is_master_triggered_returnLabel#8 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 23608#L743-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 23607#L743-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 23606#L311-21 assume !(1 == ~t1_pc~0); 23605#L311-23 is_transmit1_triggered_~__retres1~1#1 := 0; 23604#L322-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 23603#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 23602#L751-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 23601#L751-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 23600#L330-21 assume !(1 == ~t2_pc~0); 23598#L330-23 is_transmit2_triggered_~__retres1~2#1 := 0; 23597#L341-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 23596#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 23595#L759-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 23562#L759-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 21445#L349-21 assume !(1 == ~t3_pc~0); 21446#L349-23 is_transmit3_triggered_~__retres1~3#1 := 0; 21646#L360-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 21658#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 21597#L767-21 assume !(0 != activate_threads_~tmp___2~0#1); 21598#L767-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 21269#L368-21 assume 1 == ~t4_pc~0; 21149#L369-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 21150#L379-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 23544#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 23541#L775-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 23540#L775-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 21136#L387-21 assume 1 == ~t5_pc~0; 21137#L388-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 21488#L398-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 21498#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 21499#L783-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 21178#L783-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21179#L667-3 assume !(1 == ~M_E~0); 21162#L667-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 21163#L672-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 21249#L677-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 21250#L682-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 21655#L687-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 21288#L692-3 assume 1 == ~E_M~0;~E_M~0 := 2; 21289#L697-3 assume 1 == ~E_1~0;~E_1~0 := 2; 21372#L702-3 assume !(1 == ~E_2~0); 21373#L707-3 assume 1 == ~E_3~0;~E_3~0 := 2; 21519#L712-3 assume 1 == ~E_4~0;~E_4~0 := 2; 21171#L717-3 assume 1 == ~E_5~0;~E_5~0 := 2; 21172#L722-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 21552#L452-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 21101#L484-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 21659#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 22485#L947 assume !(0 == start_simulation_~tmp~3#1); 23151#L947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 23149#L452-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 23058#L484-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 23055#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret18#1;havoc stop_simulation_#t~ret18#1; 21653#L902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 21612#L909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 21613#stop_simulation_returnLabel#1 start_simulation_#t~ret20#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 21537#L960 assume !(0 != start_simulation_~tmp___0~1#1); 21087#L928-2 [2022-12-13 22:01:23,341 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 22:01:23,341 INFO L85 PathProgramCache]: Analyzing trace with hash -1293840698, now seen corresponding path program 1 times [2022-12-13 22:01:23,341 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 22:01:23,341 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [811377940] [2022-12-13 22:01:23,341 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 22:01:23,341 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 22:01:23,350 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 22:01:23,380 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 22:01:23,381 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 22:01:23,381 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [811377940] [2022-12-13 22:01:23,381 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [811377940] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 22:01:23,381 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 22:01:23,381 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-12-13 22:01:23,381 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1424308559] [2022-12-13 22:01:23,381 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 22:01:23,382 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 22:01:23,382 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 22:01:23,382 INFO L85 PathProgramCache]: Analyzing trace with hash 53494450, now seen corresponding path program 1 times [2022-12-13 22:01:23,382 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 22:01:23,382 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1215477030] [2022-12-13 22:01:23,382 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 22:01:23,383 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 22:01:23,392 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 22:01:23,433 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 22:01:23,433 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 22:01:23,433 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1215477030] [2022-12-13 22:01:23,433 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1215477030] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 22:01:23,433 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 22:01:23,433 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-12-13 22:01:23,434 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2124542173] [2022-12-13 22:01:23,434 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 22:01:23,434 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 22:01:23,434 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 22:01:23,434 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 22:01:23,434 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 22:01:23,435 INFO L87 Difference]: Start difference. First operand 2552 states and 3632 transitions. cyclomatic complexity: 1082 Second operand has 3 states, 3 states have (on average 24.333333333333332) internal successors, (73), 2 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 22:01:23,492 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 22:01:23,492 INFO L93 Difference]: Finished difference Result 4708 states and 6670 transitions. [2022-12-13 22:01:23,493 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4708 states and 6670 transitions. [2022-12-13 22:01:23,514 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4597 [2022-12-13 22:01:23,535 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4708 states to 4708 states and 6670 transitions. [2022-12-13 22:01:23,535 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4708 [2022-12-13 22:01:23,539 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4708 [2022-12-13 22:01:23,539 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4708 states and 6670 transitions. [2022-12-13 22:01:23,546 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 22:01:23,546 INFO L218 hiAutomatonCegarLoop]: Abstraction has 4708 states and 6670 transitions. [2022-12-13 22:01:23,550 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4708 states and 6670 transitions. [2022-12-13 22:01:23,615 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4708 to 4696. [2022-12-13 22:01:23,623 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4696 states, 4696 states have (on average 1.417802385008518) internal successors, (6658), 4695 states have internal predecessors, (6658), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 22:01:23,635 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4696 states to 4696 states and 6658 transitions. [2022-12-13 22:01:23,635 INFO L240 hiAutomatonCegarLoop]: Abstraction has 4696 states and 6658 transitions. [2022-12-13 22:01:23,635 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 22:01:23,636 INFO L428 stractBuchiCegarLoop]: Abstraction has 4696 states and 6658 transitions. [2022-12-13 22:01:23,636 INFO L335 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2022-12-13 22:01:23,636 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4696 states and 6658 transitions. [2022-12-13 22:01:23,651 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4585 [2022-12-13 22:01:23,651 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 22:01:23,651 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 22:01:23,652 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 22:01:23,652 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 22:01:23,653 INFO L748 eck$LassoCheckResult]: Stem: 28639#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 28640#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 28765#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 28766#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 28916#L414 assume 1 == ~m_i~0;~m_st~0 := 0; 28707#L414-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 28708#L419-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 28890#L424-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 28686#L429-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 28687#L434-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 28885#L439-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 28682#L599 assume !(0 == ~M_E~0); 28683#L599-2 assume !(0 == ~T1_E~0); 28347#L604-1 assume !(0 == ~T2_E~0); 28334#L609-1 assume !(0 == ~T3_E~0); 28335#L614-1 assume !(0 == ~T4_E~0); 28501#L619-1 assume !(0 == ~T5_E~0); 28616#L624-1 assume !(0 == ~E_M~0); 28712#L629-1 assume !(0 == ~E_1~0); 28426#L634-1 assume !(0 == ~E_2~0); 28427#L639-1 assume !(0 == ~E_3~0); 28828#L644-1 assume !(0 == ~E_4~0); 28846#L649-1 assume !(0 == ~E_5~0); 28389#L654-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 28390#L292 assume !(1 == ~m_pc~0); 28515#L292-2 is_master_triggered_~__retres1~0#1 := 0; 28652#L303 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 28614#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 28615#L743 assume !(0 != activate_threads_~tmp~1#1); 28458#L743-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 28459#L311 assume !(1 == ~t1_pc~0); 28827#L311-2 is_transmit1_triggered_~__retres1~1#1 := 0; 28721#L322 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 28380#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 28361#L751 assume !(0 != activate_threads_~tmp___0~0#1); 28362#L751-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 28831#L330 assume !(1 == ~t2_pc~0); 28620#L330-2 is_transmit2_triggered_~__retres1~2#1 := 0; 28518#L341 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 28519#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 28770#L759 assume !(0 != activate_threads_~tmp___1~0#1); 28915#L759-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 28504#L349 assume !(1 == ~t3_pc~0); 28505#L349-2 is_transmit3_triggered_~__retres1~3#1 := 0; 28944#L360 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 28341#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 28342#L767 assume !(0 != activate_threads_~tmp___2~0#1); 28910#L767-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 28911#L368 assume !(1 == ~t4_pc~0); 28586#L368-2 is_transmit4_triggered_~__retres1~4#1 := 0; 28587#L379 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 28487#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 28488#L775 assume !(0 != activate_threads_~tmp___3~0#1); 28348#L775-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 28349#L387 assume !(1 == ~t5_pc~0); 28735#L387-2 is_transmit5_triggered_~__retres1~5#1 := 0; 28736#L398 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 28622#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 28476#L783 assume !(0 != activate_threads_~tmp___4~0#1); 28477#L783-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 28571#L667 assume !(1 == ~M_E~0); 28645#L667-2 assume !(1 == ~T1_E~0); 28838#L672-1 assume !(1 == ~T2_E~0); 28603#L677-1 assume !(1 == ~T3_E~0); 28604#L682-1 assume !(1 == ~T4_E~0); 28809#L687-1 assume !(1 == ~T5_E~0); 28878#L692-1 assume !(1 == ~E_M~0); 28795#L697-1 assume 1 == ~E_1~0;~E_1~0 := 2; 28796#L702-1 assume !(1 == ~E_2~0); 28845#L707-1 assume !(1 == ~E_3~0); 28700#L712-1 assume !(1 == ~E_4~0); 28701#L717-1 assume !(1 == ~E_5~0); 28816#L722-1 assume { :end_inline_reset_delta_events } true; 28817#L928-2 [2022-12-13 22:01:23,653 INFO L750 eck$LassoCheckResult]: Loop: 28817#L928-2 assume !false; 29745#L929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 29739#L574 assume !false; 29737#L495 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 29722#L452 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 29711#L484 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 29708#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 29704#L499 assume !(0 != eval_~tmp~0#1); 29700#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 29697#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 29694#L599-3 assume !(0 == ~M_E~0); 29691#L599-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 29688#L604-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 29685#L609-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 29682#L614-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 29679#L619-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 29676#L624-3 assume !(0 == ~E_M~0); 29673#L629-3 assume 0 == ~E_1~0;~E_1~0 := 1; 29670#L634-3 assume !(0 == ~E_2~0); 29667#L639-3 assume 0 == ~E_3~0;~E_3~0 := 1; 29664#L644-3 assume 0 == ~E_4~0;~E_4~0 := 1; 29661#L649-3 assume 0 == ~E_5~0;~E_5~0 := 1; 29658#L654-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 29655#L292-21 assume !(1 == ~m_pc~0); 29652#L292-23 is_master_triggered_~__retres1~0#1 := 0; 29649#L303-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 29646#is_master_triggered_returnLabel#8 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 29643#L743-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 29640#L743-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 29637#L311-21 assume !(1 == ~t1_pc~0); 29634#L311-23 is_transmit1_triggered_~__retres1~1#1 := 0; 29631#L322-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 29628#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 29624#L751-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 29621#L751-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 29618#L330-21 assume !(1 == ~t2_pc~0); 29613#L330-23 is_transmit2_triggered_~__retres1~2#1 := 0; 29610#L341-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 29607#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 29604#L759-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 29600#L759-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 29596#L349-21 assume 1 == ~t3_pc~0; 29591#L350-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 29585#L360-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 29580#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 29575#L767-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 29570#L767-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 29567#L368-21 assume !(1 == ~t4_pc~0); 29187#L368-23 is_transmit4_triggered_~__retres1~4#1 := 0; 29182#L379-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 29180#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 29177#L775-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 29178#L775-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 29518#L387-21 assume !(1 == ~t5_pc~0); 29509#L387-23 is_transmit5_triggered_~__retres1~5#1 := 0; 29162#L398-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 29163#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 29158#L783-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 29159#L783-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 29060#L667-3 assume !(1 == ~M_E~0); 29061#L667-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 30372#L672-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 29050#L677-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 29051#L682-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 30371#L687-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 30370#L692-3 assume 1 == ~E_M~0;~E_M~0 := 2; 29036#L697-3 assume 1 == ~E_1~0;~E_1~0 := 2; 29037#L702-3 assume !(1 == ~E_2~0); 30369#L707-3 assume 1 == ~E_3~0;~E_3~0 := 2; 30368#L712-3 assume 1 == ~E_4~0;~E_4~0 := 2; 29025#L717-3 assume 1 == ~E_5~0;~E_5~0 := 2; 29023#L722-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 29018#L452-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 29014#L484-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 29532#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 29533#L947 assume !(0 == start_simulation_~tmp~3#1); 30057#L947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 29781#L452-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 29775#L484-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 29774#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret18#1;havoc stop_simulation_#t~ret18#1; 29770#L902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 29768#L909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 29766#stop_simulation_returnLabel#1 start_simulation_#t~ret20#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 29765#L960 assume !(0 != start_simulation_~tmp___0~1#1); 28817#L928-2 [2022-12-13 22:01:23,653 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 22:01:23,653 INFO L85 PathProgramCache]: Analyzing trace with hash 943522567, now seen corresponding path program 1 times [2022-12-13 22:01:23,653 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 22:01:23,654 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2028386265] [2022-12-13 22:01:23,654 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 22:01:23,654 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 22:01:23,662 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 22:01:23,705 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 22:01:23,705 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 22:01:23,705 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2028386265] [2022-12-13 22:01:23,705 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2028386265] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 22:01:23,706 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 22:01:23,706 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 22:01:23,706 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1123971706] [2022-12-13 22:01:23,706 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 22:01:23,706 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 22:01:23,706 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 22:01:23,706 INFO L85 PathProgramCache]: Analyzing trace with hash -645879695, now seen corresponding path program 1 times [2022-12-13 22:01:23,707 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 22:01:23,707 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1281877040] [2022-12-13 22:01:23,707 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 22:01:23,707 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 22:01:23,716 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 22:01:23,755 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 22:01:23,755 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 22:01:23,755 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1281877040] [2022-12-13 22:01:23,755 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1281877040] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 22:01:23,755 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 22:01:23,755 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-12-13 22:01:23,755 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [942498703] [2022-12-13 22:01:23,756 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 22:01:23,756 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 22:01:23,756 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 22:01:23,756 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 22:01:23,756 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 22:01:23,756 INFO L87 Difference]: Start difference. First operand 4696 states and 6658 transitions. cyclomatic complexity: 1966 Second operand has 4 states, 4 states have (on average 18.25) internal successors, (73), 3 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 22:01:23,853 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 22:01:23,853 INFO L93 Difference]: Finished difference Result 7486 states and 10538 transitions. [2022-12-13 22:01:23,853 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7486 states and 10538 transitions. [2022-12-13 22:01:23,883 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 7281 [2022-12-13 22:01:23,924 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7486 states to 7486 states and 10538 transitions. [2022-12-13 22:01:23,925 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7486 [2022-12-13 22:01:23,932 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7486 [2022-12-13 22:01:23,932 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7486 states and 10538 transitions. [2022-12-13 22:01:23,943 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 22:01:23,944 INFO L218 hiAutomatonCegarLoop]: Abstraction has 7486 states and 10538 transitions. [2022-12-13 22:01:23,952 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7486 states and 10538 transitions. [2022-12-13 22:01:24,012 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7486 to 5425. [2022-12-13 22:01:24,026 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5425 states, 5425 states have (on average 1.4106912442396313) internal successors, (7653), 5424 states have internal predecessors, (7653), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 22:01:24,038 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5425 states to 5425 states and 7653 transitions. [2022-12-13 22:01:24,038 INFO L240 hiAutomatonCegarLoop]: Abstraction has 5425 states and 7653 transitions. [2022-12-13 22:01:24,039 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 22:01:24,039 INFO L428 stractBuchiCegarLoop]: Abstraction has 5425 states and 7653 transitions. [2022-12-13 22:01:24,039 INFO L335 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2022-12-13 22:01:24,040 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5425 states and 7653 transitions. [2022-12-13 22:01:24,058 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 5259 [2022-12-13 22:01:24,059 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 22:01:24,059 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 22:01:24,060 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 22:01:24,060 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 22:01:24,061 INFO L748 eck$LassoCheckResult]: Stem: 40836#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 40837#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 40968#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 40969#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 41127#L414 assume 1 == ~m_i~0;~m_st~0 := 0; 40906#L414-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 40907#L419-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 41101#L424-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 40883#L429-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 40884#L434-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 41096#L439-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 40879#L599 assume !(0 == ~M_E~0); 40880#L599-2 assume !(0 == ~T1_E~0); 40539#L604-1 assume !(0 == ~T2_E~0); 40528#L609-1 assume !(0 == ~T3_E~0); 40529#L614-1 assume !(0 == ~T4_E~0); 40695#L619-1 assume !(0 == ~T5_E~0); 40811#L624-1 assume !(0 == ~E_M~0); 40910#L629-1 assume 0 == ~E_1~0;~E_1~0 := 1; 41154#L634-1 assume !(0 == ~E_2~0); 41039#L639-1 assume !(0 == ~E_3~0); 41040#L644-1 assume !(0 == ~E_4~0); 41059#L649-1 assume !(0 == ~E_5~0); 40583#L654-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 40584#L292 assume !(1 == ~m_pc~0); 40848#L292-2 is_master_triggered_~__retres1~0#1 := 0; 40849#L303 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 40961#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 41207#L743 assume !(0 != activate_threads_~tmp~1#1); 41206#L743-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 41037#L311 assume !(1 == ~t1_pc~0); 41038#L311-2 is_transmit1_triggered_~__retres1~1#1 := 0; 40918#L322 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 40919#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 41201#L751 assume !(0 != activate_threads_~tmp___0~0#1); 41200#L751-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 41199#L330 assume !(1 == ~t2_pc~0); 40994#L330-2 is_transmit2_triggered_~__retres1~2#1 := 0; 40711#L341 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 40712#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 41196#L759 assume !(0 != activate_threads_~tmp___1~0#1); 41195#L759-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 41194#L349 assume !(1 == ~t3_pc~0); 41157#L349-2 is_transmit3_triggered_~__retres1~3#1 := 0; 41006#L360 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 40530#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 40531#L767 assume !(0 != activate_threads_~tmp___2~0#1); 41189#L767-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 41164#L368 assume !(1 == ~t4_pc~0); 41165#L368-2 is_transmit4_triggered_~__retres1~4#1 := 0; 41188#L379 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 40682#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 40683#L775 assume !(0 != activate_threads_~tmp___3~0#1); 40542#L775-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 40543#L387 assume !(1 == ~t5_pc~0); 40935#L387-2 is_transmit5_triggered_~__retres1~5#1 := 0; 40936#L398 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 41182#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 40669#L783 assume !(0 != activate_threads_~tmp___4~0#1); 40670#L783-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 40764#L667 assume !(1 == ~M_E~0); 40841#L667-2 assume !(1 == ~T1_E~0); 41049#L672-1 assume !(1 == ~T2_E~0); 41053#L677-1 assume !(1 == ~T3_E~0); 41177#L682-1 assume !(1 == ~T4_E~0); 41176#L687-1 assume !(1 == ~T5_E~0); 41175#L692-1 assume !(1 == ~E_M~0); 41174#L697-1 assume 1 == ~E_1~0;~E_1~0 := 2; 41005#L702-1 assume !(1 == ~E_2~0); 41058#L707-1 assume !(1 == ~E_3~0); 40899#L712-1 assume !(1 == ~E_4~0); 40900#L717-1 assume !(1 == ~E_5~0); 41026#L722-1 assume { :end_inline_reset_delta_events } true; 41027#L928-2 [2022-12-13 22:01:24,061 INFO L750 eck$LassoCheckResult]: Loop: 41027#L928-2 assume !false; 44703#L929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 44701#L574 assume !false; 44699#L495 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 44691#L452 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 44688#L484 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 44687#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 44685#L499 assume !(0 != eval_~tmp~0#1); 44684#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 44683#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 44682#L599-3 assume !(0 == ~M_E~0); 44679#L599-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 44675#L604-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 44671#L609-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 44668#L614-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 44665#L619-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 44662#L624-3 assume !(0 == ~E_M~0); 44660#L629-3 assume 0 == ~E_1~0;~E_1~0 := 1; 44659#L634-3 assume !(0 == ~E_2~0); 44658#L639-3 assume 0 == ~E_3~0;~E_3~0 := 1; 44657#L644-3 assume 0 == ~E_4~0;~E_4~0 := 1; 44656#L649-3 assume 0 == ~E_5~0;~E_5~0 := 1; 44655#L654-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 44654#L292-21 assume !(1 == ~m_pc~0); 44653#L292-23 is_master_triggered_~__retres1~0#1 := 0; 44652#L303-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 44651#is_master_triggered_returnLabel#8 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 44650#L743-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 44649#L743-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 44648#L311-21 assume !(1 == ~t1_pc~0); 44647#L311-23 is_transmit1_triggered_~__retres1~1#1 := 0; 44646#L322-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 44645#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 44644#L751-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 44643#L751-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 44642#L330-21 assume !(1 == ~t2_pc~0); 44640#L330-23 is_transmit2_triggered_~__retres1~2#1 := 0; 44639#L341-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 44638#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 44637#L759-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 44636#L759-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 44635#L349-21 assume 1 == ~t3_pc~0; 44633#L350-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 44631#L360-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 44629#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 44627#L767-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 44626#L767-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 44625#L368-21 assume !(1 == ~t4_pc~0); 44624#L368-23 is_transmit4_triggered_~__retres1~4#1 := 0; 44623#L379-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 44622#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 44621#L775-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 44620#L775-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 44619#L387-21 assume !(1 == ~t5_pc~0); 44617#L387-23 is_transmit5_triggered_~__retres1~5#1 := 0; 44616#L398-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 44615#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 44614#L783-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 44613#L783-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 44612#L667-3 assume !(1 == ~M_E~0); 44013#L667-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 44611#L672-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 44610#L677-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 44609#L682-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 44608#L687-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 44607#L692-3 assume 1 == ~E_M~0;~E_M~0 := 2; 44605#L697-3 assume 1 == ~E_1~0;~E_1~0 := 2; 44604#L702-3 assume !(1 == ~E_2~0); 44603#L707-3 assume 1 == ~E_3~0;~E_3~0 := 2; 44601#L712-3 assume 1 == ~E_4~0;~E_4~0 := 2; 44599#L717-3 assume 1 == ~E_5~0;~E_5~0 := 2; 44597#L722-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 44592#L452-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 44586#L484-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 43895#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 43205#L947 assume !(0 == start_simulation_~tmp~3#1); 43206#L947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 44866#L452-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 44860#L484-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 44858#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret18#1;havoc stop_simulation_#t~ret18#1; 44857#L902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 44856#L909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 44855#stop_simulation_returnLabel#1 start_simulation_#t~ret20#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 44852#L960 assume !(0 != start_simulation_~tmp___0~1#1); 41027#L928-2 [2022-12-13 22:01:24,061 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 22:01:24,061 INFO L85 PathProgramCache]: Analyzing trace with hash -443262843, now seen corresponding path program 1 times [2022-12-13 22:01:24,061 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 22:01:24,061 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [333389672] [2022-12-13 22:01:24,061 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 22:01:24,062 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 22:01:24,070 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 22:01:24,106 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 22:01:24,106 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 22:01:24,106 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [333389672] [2022-12-13 22:01:24,106 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [333389672] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 22:01:24,106 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 22:01:24,106 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 22:01:24,106 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1522212641] [2022-12-13 22:01:24,106 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 22:01:24,107 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 22:01:24,107 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 22:01:24,107 INFO L85 PathProgramCache]: Analyzing trace with hash -645879695, now seen corresponding path program 2 times [2022-12-13 22:01:24,107 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 22:01:24,107 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [96798412] [2022-12-13 22:01:24,108 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 22:01:24,108 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 22:01:24,128 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 22:01:24,174 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 22:01:24,175 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 22:01:24,175 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [96798412] [2022-12-13 22:01:24,175 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [96798412] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 22:01:24,175 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 22:01:24,175 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-12-13 22:01:24,175 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1533703454] [2022-12-13 22:01:24,175 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 22:01:24,176 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 22:01:24,176 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 22:01:24,176 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 22:01:24,176 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 22:01:24,176 INFO L87 Difference]: Start difference. First operand 5425 states and 7653 transitions. cyclomatic complexity: 2232 Second operand has 4 states, 4 states have (on average 18.25) internal successors, (73), 3 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 22:01:24,270 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 22:01:24,270 INFO L93 Difference]: Finished difference Result 6610 states and 9281 transitions. [2022-12-13 22:01:24,270 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6610 states and 9281 transitions. [2022-12-13 22:01:24,293 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 6465 [2022-12-13 22:01:24,307 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6610 states to 6610 states and 9281 transitions. [2022-12-13 22:01:24,307 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6610 [2022-12-13 22:01:24,311 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6610 [2022-12-13 22:01:24,311 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6610 states and 9281 transitions. [2022-12-13 22:01:24,315 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 22:01:24,315 INFO L218 hiAutomatonCegarLoop]: Abstraction has 6610 states and 9281 transitions. [2022-12-13 22:01:24,320 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6610 states and 9281 transitions. [2022-12-13 22:01:24,355 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6610 to 4696. [2022-12-13 22:01:24,359 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4696 states, 4696 states have (on average 1.4045996592844974) internal successors, (6596), 4695 states have internal predecessors, (6596), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 22:01:24,366 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4696 states to 4696 states and 6596 transitions. [2022-12-13 22:01:24,366 INFO L240 hiAutomatonCegarLoop]: Abstraction has 4696 states and 6596 transitions. [2022-12-13 22:01:24,366 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 22:01:24,367 INFO L428 stractBuchiCegarLoop]: Abstraction has 4696 states and 6596 transitions. [2022-12-13 22:01:24,367 INFO L335 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2022-12-13 22:01:24,367 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4696 states and 6596 transitions. [2022-12-13 22:01:24,377 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4585 [2022-12-13 22:01:24,377 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 22:01:24,377 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 22:01:24,378 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 22:01:24,378 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 22:01:24,378 INFO L748 eck$LassoCheckResult]: Stem: 52871#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 52872#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 52994#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 52995#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 53155#L414 assume 1 == ~m_i~0;~m_st~0 := 0; 52937#L414-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 52938#L419-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 53131#L424-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 52916#L429-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 52917#L434-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 53122#L439-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 52912#L599 assume !(0 == ~M_E~0); 52913#L599-2 assume !(0 == ~T1_E~0); 52588#L604-1 assume !(0 == ~T2_E~0); 52575#L609-1 assume !(0 == ~T3_E~0); 52576#L614-1 assume !(0 == ~T4_E~0); 52740#L619-1 assume !(0 == ~T5_E~0); 52849#L624-1 assume !(0 == ~E_M~0); 52942#L629-1 assume !(0 == ~E_1~0); 52667#L634-1 assume !(0 == ~E_2~0); 52668#L639-1 assume !(0 == ~E_3~0); 53062#L644-1 assume !(0 == ~E_4~0); 53079#L649-1 assume !(0 == ~E_5~0); 52630#L654-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 52631#L292 assume !(1 == ~m_pc~0); 52754#L292-2 is_master_triggered_~__retres1~0#1 := 0; 52884#L303 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 52847#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 52848#L743 assume !(0 != activate_threads_~tmp~1#1); 52699#L743-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 52700#L311 assume !(1 == ~t1_pc~0); 53060#L311-2 is_transmit1_triggered_~__retres1~1#1 := 0; 52950#L322 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 52621#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 52602#L751 assume !(0 != activate_threads_~tmp___0~0#1); 52603#L751-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 53065#L330 assume !(1 == ~t2_pc~0); 52852#L330-2 is_transmit2_triggered_~__retres1~2#1 := 0; 52756#L341 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 52757#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 52999#L759 assume !(0 != activate_threads_~tmp___1~0#1); 53153#L759-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 52743#L349 assume !(1 == ~t3_pc~0); 52744#L349-2 is_transmit3_triggered_~__retres1~3#1 := 0; 53031#L360 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 53032#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 53188#L767 assume !(0 != activate_threads_~tmp___2~0#1); 53145#L767-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 53146#L368 assume !(1 == ~t4_pc~0); 52819#L368-2 is_transmit4_triggered_~__retres1~4#1 := 0; 52820#L379 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 52726#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 52727#L775 assume !(0 != activate_threads_~tmp___3~0#1); 52589#L775-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 52590#L387 assume !(1 == ~t5_pc~0); 52963#L387-2 is_transmit5_triggered_~__retres1~5#1 := 0; 52964#L398 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 52854#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 52716#L783 assume !(0 != activate_threads_~tmp___4~0#1); 52717#L783-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 52809#L667 assume !(1 == ~M_E~0); 52876#L667-2 assume !(1 == ~T1_E~0); 53071#L672-1 assume !(1 == ~T2_E~0); 52836#L677-1 assume !(1 == ~T3_E~0); 52837#L682-1 assume !(1 == ~T4_E~0); 53043#L687-1 assume !(1 == ~T5_E~0); 53116#L692-1 assume !(1 == ~E_M~0); 53029#L697-1 assume !(1 == ~E_1~0); 53030#L702-1 assume !(1 == ~E_2~0); 53078#L707-1 assume !(1 == ~E_3~0); 52929#L712-1 assume !(1 == ~E_4~0); 52930#L717-1 assume !(1 == ~E_5~0); 53050#L722-1 assume { :end_inline_reset_delta_events } true; 53051#L928-2 [2022-12-13 22:01:24,378 INFO L750 eck$LassoCheckResult]: Loop: 53051#L928-2 assume !false; 55100#L929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 55098#L574 assume !false; 55096#L495 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 55092#L452 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 55089#L484 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 55088#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 55086#L499 assume !(0 != eval_~tmp~0#1); 55085#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 55084#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 55083#L599-3 assume !(0 == ~M_E~0); 55082#L599-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 55081#L604-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 55080#L609-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 55079#L614-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 55078#L619-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 55077#L624-3 assume !(0 == ~E_M~0); 55076#L629-3 assume !(0 == ~E_1~0); 55075#L634-3 assume !(0 == ~E_2~0); 55074#L639-3 assume 0 == ~E_3~0;~E_3~0 := 1; 55073#L644-3 assume 0 == ~E_4~0;~E_4~0 := 1; 55072#L649-3 assume 0 == ~E_5~0;~E_5~0 := 1; 55071#L654-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 55070#L292-21 assume !(1 == ~m_pc~0); 55069#L292-23 is_master_triggered_~__retres1~0#1 := 0; 55068#L303-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 55067#is_master_triggered_returnLabel#8 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 55066#L743-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 55065#L743-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 55064#L311-21 assume !(1 == ~t1_pc~0); 55063#L311-23 is_transmit1_triggered_~__retres1~1#1 := 0; 55062#L322-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 55061#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 55060#L751-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 55059#L751-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 55058#L330-21 assume !(1 == ~t2_pc~0); 55056#L330-23 is_transmit2_triggered_~__retres1~2#1 := 0; 55055#L341-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 55054#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 55053#L759-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 55052#L759-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 55051#L349-21 assume 1 == ~t3_pc~0; 55049#L350-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 55047#L360-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 55045#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 55043#L767-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 55042#L767-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 55041#L368-21 assume !(1 == ~t4_pc~0); 55040#L368-23 is_transmit4_triggered_~__retres1~4#1 := 0; 55039#L379-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 55038#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 55037#L775-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 55036#L775-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 55033#L387-21 assume !(1 == ~t5_pc~0); 55030#L387-23 is_transmit5_triggered_~__retres1~5#1 := 0; 55028#L398-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 55026#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 55024#L783-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 55021#L783-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 55020#L667-3 assume !(1 == ~M_E~0); 54288#L667-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 55013#L672-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 55011#L677-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 55009#L682-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 55006#L687-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 55004#L692-3 assume 1 == ~E_M~0;~E_M~0 := 2; 55001#L697-3 assume !(1 == ~E_1~0); 54999#L702-3 assume !(1 == ~E_2~0); 54997#L707-3 assume 1 == ~E_3~0;~E_3~0 := 2; 54996#L712-3 assume 1 == ~E_4~0;~E_4~0 := 2; 54995#L717-3 assume 1 == ~E_5~0;~E_5~0 := 2; 54994#L722-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 54992#L452-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 54987#L484-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 52959#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 52896#L947 assume !(0 == start_simulation_~tmp~3#1); 52897#L947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 55196#L452-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 55191#L484-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 55140#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret18#1;havoc stop_simulation_#t~ret18#1; 55136#L902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 55135#L909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 55130#stop_simulation_returnLabel#1 start_simulation_#t~ret20#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 55118#L960 assume !(0 != start_simulation_~tmp___0~1#1); 53051#L928-2 [2022-12-13 22:01:24,378 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 22:01:24,378 INFO L85 PathProgramCache]: Analyzing trace with hash 1000780869, now seen corresponding path program 1 times [2022-12-13 22:01:24,378 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 22:01:24,378 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [514843914] [2022-12-13 22:01:24,378 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 22:01:24,379 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 22:01:24,385 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 22:01:24,385 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 22:01:24,390 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 22:01:24,423 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 22:01:24,424 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 22:01:24,424 INFO L85 PathProgramCache]: Analyzing trace with hash 438789169, now seen corresponding path program 1 times [2022-12-13 22:01:24,424 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 22:01:24,424 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [136219478] [2022-12-13 22:01:24,424 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 22:01:24,424 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 22:01:24,431 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 22:01:24,458 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 22:01:24,458 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 22:01:24,458 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [136219478] [2022-12-13 22:01:24,458 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [136219478] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 22:01:24,459 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 22:01:24,459 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-12-13 22:01:24,459 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [267523253] [2022-12-13 22:01:24,459 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 22:01:24,459 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 22:01:24,459 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 22:01:24,460 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-12-13 22:01:24,460 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-12-13 22:01:24,460 INFO L87 Difference]: Start difference. First operand 4696 states and 6596 transitions. cyclomatic complexity: 1904 Second operand has 5 states, 5 states have (on average 16.8) internal successors, (84), 5 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 22:01:24,564 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 22:01:24,564 INFO L93 Difference]: Finished difference Result 8383 states and 11605 transitions. [2022-12-13 22:01:24,564 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 8383 states and 11605 transitions. [2022-12-13 22:01:24,598 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 8240 [2022-12-13 22:01:24,624 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 8383 states to 8383 states and 11605 transitions. [2022-12-13 22:01:24,624 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8383 [2022-12-13 22:01:24,631 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8383 [2022-12-13 22:01:24,631 INFO L73 IsDeterministic]: Start isDeterministic. Operand 8383 states and 11605 transitions. [2022-12-13 22:01:24,637 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 22:01:24,638 INFO L218 hiAutomatonCegarLoop]: Abstraction has 8383 states and 11605 transitions. [2022-12-13 22:01:24,646 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8383 states and 11605 transitions. [2022-12-13 22:01:24,702 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8383 to 4732. [2022-12-13 22:01:24,707 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4732 states, 4732 states have (on average 1.4015215553677092) internal successors, (6632), 4731 states have internal predecessors, (6632), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 22:01:24,745 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4732 states to 4732 states and 6632 transitions. [2022-12-13 22:01:24,745 INFO L240 hiAutomatonCegarLoop]: Abstraction has 4732 states and 6632 transitions. [2022-12-13 22:01:24,745 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2022-12-13 22:01:24,746 INFO L428 stractBuchiCegarLoop]: Abstraction has 4732 states and 6632 transitions. [2022-12-13 22:01:24,746 INFO L335 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2022-12-13 22:01:24,746 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4732 states and 6632 transitions. [2022-12-13 22:01:24,758 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4621 [2022-12-13 22:01:24,758 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 22:01:24,758 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 22:01:24,759 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 22:01:24,759 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 22:01:24,760 INFO L748 eck$LassoCheckResult]: Stem: 65978#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 65979#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 66102#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 66103#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 66284#L414 assume 1 == ~m_i~0;~m_st~0 := 0; 66043#L414-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 66044#L419-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 66250#L424-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 66021#L429-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 66022#L434-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 66240#L439-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 66017#L599 assume !(0 == ~M_E~0); 66018#L599-2 assume !(0 == ~T1_E~0); 65681#L604-1 assume !(0 == ~T2_E~0); 65670#L609-1 assume !(0 == ~T3_E~0); 65671#L614-1 assume !(0 == ~T4_E~0); 65836#L619-1 assume !(0 == ~T5_E~0); 65954#L624-1 assume !(0 == ~E_M~0); 66047#L629-1 assume !(0 == ~E_1~0); 65763#L634-1 assume !(0 == ~E_2~0); 65764#L639-1 assume !(0 == ~E_3~0); 66175#L644-1 assume !(0 == ~E_4~0); 66195#L649-1 assume !(0 == ~E_5~0); 65726#L654-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 65727#L292 assume !(1 == ~m_pc~0); 65850#L292-2 is_master_triggered_~__retres1~0#1 := 0; 65990#L303 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 65950#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 65951#L743 assume !(0 != activate_threads_~tmp~1#1); 65795#L743-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 65796#L311 assume !(1 == ~t1_pc~0); 66174#L311-2 is_transmit1_triggered_~__retres1~1#1 := 0; 66055#L322 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 65717#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 65698#L751 assume !(0 != activate_threads_~tmp___0~0#1); 65699#L751-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 66177#L330 assume !(1 == ~t2_pc~0); 65957#L330-2 is_transmit2_triggered_~__retres1~2#1 := 0; 65851#L341 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 65852#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 66107#L759 assume !(0 != activate_threads_~tmp___1~0#1); 66280#L759-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 65837#L349 assume !(1 == ~t3_pc~0); 65838#L349-2 is_transmit3_triggered_~__retres1~3#1 := 0; 66317#L360 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 66341#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 66330#L767 assume !(0 != activate_threads_~tmp___2~0#1); 66271#L767-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 66272#L368 assume !(1 == ~t4_pc~0); 65920#L368-2 is_transmit4_triggered_~__retres1~4#1 := 0; 65921#L379 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 65822#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 65823#L775 assume !(0 != activate_threads_~tmp___3~0#1); 65684#L775-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 65685#L387 assume !(1 == ~t5_pc~0); 66070#L387-2 is_transmit5_triggered_~__retres1~5#1 := 0; 66071#L398 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 65960#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 65809#L783 assume !(0 != activate_threads_~tmp___4~0#1); 65810#L783-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 65905#L667 assume !(1 == ~M_E~0); 65983#L667-2 assume !(1 == ~T1_E~0); 66186#L672-1 assume !(1 == ~T2_E~0); 65941#L677-1 assume !(1 == ~T3_E~0); 65942#L682-1 assume !(1 == ~T4_E~0); 66156#L687-1 assume !(1 == ~T5_E~0); 66234#L692-1 assume !(1 == ~E_M~0); 66141#L697-1 assume !(1 == ~E_1~0); 66142#L702-1 assume !(1 == ~E_2~0); 66194#L707-1 assume !(1 == ~E_3~0); 66037#L712-1 assume !(1 == ~E_4~0); 66038#L717-1 assume !(1 == ~E_5~0); 66163#L722-1 assume { :end_inline_reset_delta_events } true; 66164#L928-2 [2022-12-13 22:01:24,760 INFO L750 eck$LassoCheckResult]: Loop: 66164#L928-2 assume !false; 70102#L929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 70099#L574 assume !false; 69909#L495 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 69885#L452 assume !(0 == ~m_st~0); 69886#L456 assume !(0 == ~t1_st~0); 69888#L460 assume !(0 == ~t2_st~0); 69883#L464 assume !(0 == ~t3_st~0); 69884#L468 assume !(0 == ~t4_st~0); 69887#L472 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6#1 := 0; 69889#L484 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 69138#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 69139#L499 assume !(0 != eval_~tmp~0#1); 69878#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 69877#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 69876#L599-3 assume !(0 == ~M_E~0); 69875#L599-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 69874#L604-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 69873#L609-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 69872#L614-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 69871#L619-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 69870#L624-3 assume !(0 == ~E_M~0); 69809#L629-3 assume !(0 == ~E_1~0); 69810#L634-3 assume !(0 == ~E_2~0); 69803#L639-3 assume 0 == ~E_3~0;~E_3~0 := 1; 69804#L644-3 assume 0 == ~E_4~0;~E_4~0 := 1; 69797#L649-3 assume 0 == ~E_5~0;~E_5~0 := 1; 69798#L654-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 69791#L292-21 assume !(1 == ~m_pc~0); 69792#L292-23 is_master_triggered_~__retres1~0#1 := 0; 69646#L303-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 69647#is_master_triggered_returnLabel#8 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 66259#L743-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 65993#L743-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 65994#L311-21 assume !(1 == ~t1_pc~0); 69868#L311-23 is_transmit1_triggered_~__retres1~1#1 := 0; 65734#L322-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 65735#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 65803#L751-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 66288#L751-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 67894#L330-21 assume !(1 == ~t2_pc~0); 69863#L330-23 is_transmit2_triggered_~__retres1~2#1 := 0; 66086#L341-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 65988#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 65989#L759-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 65787#L759-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 65788#L349-21 assume !(1 == ~t3_pc~0); 66033#L349-23 is_transmit3_triggered_~__retres1~3#1 := 0; 69860#L360-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 69858#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 69856#L767-21 assume !(0 != activate_threads_~tmp___2~0#1); 69854#L767-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 69853#L368-21 assume !(1 == ~t4_pc~0); 66198#L368-23 is_transmit4_triggered_~__retres1~4#1 := 0; 66199#L379-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 66222#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 66204#L775-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 66205#L775-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 65740#L387-21 assume 1 == ~t5_pc~0; 65741#L388-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 69851#L398-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 66077#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 66078#L783-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 65780#L783-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 65781#L667-3 assume !(1 == ~M_E~0); 65765#L667-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 65766#L672-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 65844#L677-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 65845#L682-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 69644#L687-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 69645#L692-3 assume 1 == ~E_M~0;~E_M~0 := 2; 69638#L697-3 assume !(1 == ~E_1~0); 69639#L702-3 assume !(1 == ~E_2~0); 69634#L707-3 assume 1 == ~E_3~0;~E_3~0 := 2; 69635#L712-3 assume 1 == ~E_4~0;~E_4~0 := 2; 69628#L717-3 assume 1 == ~E_5~0;~E_5~0 := 2; 69629#L722-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 66277#L452-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 65706#L484-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 66063#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 66064#L947 assume !(0 == start_simulation_~tmp~3#1); 70184#L947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 70182#L452-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 70176#L484-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 70174#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret18#1;havoc stop_simulation_#t~ret18#1; 70172#L902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 70170#L909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 70169#stop_simulation_returnLabel#1 start_simulation_#t~ret20#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 70165#L960 assume !(0 != start_simulation_~tmp___0~1#1); 66164#L928-2 [2022-12-13 22:01:24,760 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 22:01:24,760 INFO L85 PathProgramCache]: Analyzing trace with hash 1000780869, now seen corresponding path program 2 times [2022-12-13 22:01:24,760 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 22:01:24,761 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [573589101] [2022-12-13 22:01:24,761 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 22:01:24,761 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 22:01:24,770 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 22:01:24,771 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 22:01:24,777 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 22:01:24,793 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 22:01:24,793 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 22:01:24,793 INFO L85 PathProgramCache]: Analyzing trace with hash -2140652226, now seen corresponding path program 1 times [2022-12-13 22:01:24,793 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 22:01:24,793 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [420935022] [2022-12-13 22:01:24,794 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 22:01:24,794 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 22:01:24,806 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 22:01:24,873 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 22:01:24,873 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 22:01:24,874 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [420935022] [2022-12-13 22:01:24,874 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [420935022] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 22:01:24,874 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 22:01:24,874 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-12-13 22:01:24,874 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1783209581] [2022-12-13 22:01:24,874 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 22:01:24,875 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 22:01:24,875 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 22:01:24,875 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-12-13 22:01:24,875 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-12-13 22:01:24,876 INFO L87 Difference]: Start difference. First operand 4732 states and 6632 transitions. cyclomatic complexity: 1904 Second operand has 5 states, 5 states have (on average 17.8) internal successors, (89), 5 states have internal predecessors, (89), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 22:01:25,061 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 22:01:25,062 INFO L93 Difference]: Finished difference Result 10896 states and 15159 transitions. [2022-12-13 22:01:25,062 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 10896 states and 15159 transitions. [2022-12-13 22:01:25,087 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 10769 [2022-12-13 22:01:25,105 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 10896 states to 10896 states and 15159 transitions. [2022-12-13 22:01:25,106 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10896 [2022-12-13 22:01:25,109 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10896 [2022-12-13 22:01:25,109 INFO L73 IsDeterministic]: Start isDeterministic. Operand 10896 states and 15159 transitions. [2022-12-13 22:01:25,114 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 22:01:25,114 INFO L218 hiAutomatonCegarLoop]: Abstraction has 10896 states and 15159 transitions. [2022-12-13 22:01:25,120 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10896 states and 15159 transitions. [2022-12-13 22:01:25,161 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10896 to 4888. [2022-12-13 22:01:25,165 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4888 states, 4888 states have (on average 1.3844108019639934) internal successors, (6767), 4887 states have internal predecessors, (6767), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 22:01:25,171 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4888 states to 4888 states and 6767 transitions. [2022-12-13 22:01:25,172 INFO L240 hiAutomatonCegarLoop]: Abstraction has 4888 states and 6767 transitions. [2022-12-13 22:01:25,181 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-12-13 22:01:25,182 INFO L428 stractBuchiCegarLoop]: Abstraction has 4888 states and 6767 transitions. [2022-12-13 22:01:25,182 INFO L335 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2022-12-13 22:01:25,182 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4888 states and 6767 transitions. [2022-12-13 22:01:25,192 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4777 [2022-12-13 22:01:25,192 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 22:01:25,192 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 22:01:25,193 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 22:01:25,193 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 22:01:25,193 INFO L748 eck$LassoCheckResult]: Stem: 81613#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 81614#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 81742#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 81743#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 81907#L414 assume 1 == ~m_i~0;~m_st~0 := 0; 81684#L414-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 81685#L419-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 81873#L424-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 81659#L429-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 81660#L434-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 81866#L439-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 81655#L599 assume !(0 == ~M_E~0); 81656#L599-2 assume !(0 == ~T1_E~0); 81322#L604-1 assume !(0 == ~T2_E~0); 81311#L609-1 assume !(0 == ~T3_E~0); 81312#L614-1 assume !(0 == ~T4_E~0); 81477#L619-1 assume !(0 == ~T5_E~0); 81592#L624-1 assume !(0 == ~E_M~0); 81688#L629-1 assume !(0 == ~E_1~0); 81402#L634-1 assume !(0 == ~E_2~0); 81403#L639-1 assume !(0 == ~E_3~0); 81812#L644-1 assume !(0 == ~E_4~0); 81828#L649-1 assume !(0 == ~E_5~0); 81366#L654-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 81367#L292 assume !(1 == ~m_pc~0); 81491#L292-2 is_master_triggered_~__retres1~0#1 := 0; 81626#L303 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 81588#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 81589#L743 assume !(0 != activate_threads_~tmp~1#1); 81434#L743-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 81435#L311 assume !(1 == ~t1_pc~0); 81811#L311-2 is_transmit1_triggered_~__retres1~1#1 := 0; 81696#L322 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 81357#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 81338#L751 assume !(0 != activate_threads_~tmp___0~0#1); 81339#L751-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 81813#L330 assume !(1 == ~t2_pc~0); 81595#L330-2 is_transmit2_triggered_~__retres1~2#1 := 0; 81492#L341 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 81493#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 81747#L759 assume !(0 != activate_threads_~tmp___1~0#1); 81904#L759-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 81478#L349 assume !(1 == ~t3_pc~0); 81479#L349-2 is_transmit3_triggered_~__retres1~3#1 := 0; 81931#L360 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 81946#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 81941#L767 assume !(0 != activate_threads_~tmp___2~0#1); 81896#L767-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 81897#L368 assume !(1 == ~t4_pc~0); 81559#L368-2 is_transmit4_triggered_~__retres1~4#1 := 0; 81560#L379 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 81464#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 81465#L775 assume !(0 != activate_threads_~tmp___3~0#1); 81325#L775-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 81326#L387 assume !(1 == ~t5_pc~0); 81712#L387-2 is_transmit5_triggered_~__retres1~5#1 := 0; 81713#L398 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 81597#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 81450#L783 assume !(0 != activate_threads_~tmp___4~0#1); 81451#L783-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 81544#L667 assume !(1 == ~M_E~0); 81618#L667-2 assume !(1 == ~T1_E~0); 81820#L672-1 assume !(1 == ~T2_E~0); 81578#L677-1 assume !(1 == ~T3_E~0); 81579#L682-1 assume !(1 == ~T4_E~0); 81791#L687-1 assume !(1 == ~T5_E~0); 81862#L692-1 assume !(1 == ~E_M~0); 81777#L697-1 assume !(1 == ~E_1~0); 81778#L702-1 assume !(1 == ~E_2~0); 81827#L707-1 assume !(1 == ~E_3~0); 81677#L712-1 assume !(1 == ~E_4~0); 81678#L717-1 assume !(1 == ~E_5~0); 81798#L722-1 assume { :end_inline_reset_delta_events } true; 81799#L928-2 [2022-12-13 22:01:25,194 INFO L750 eck$LassoCheckResult]: Loop: 81799#L928-2 assume !false; 83312#L929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 83311#L574 assume !false; 83310#L495 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 83305#L452 assume !(0 == ~m_st~0); 83306#L456 assume !(0 == ~t1_st~0); 83308#L460 assume !(0 == ~t2_st~0); 83303#L464 assume !(0 == ~t3_st~0); 83304#L468 assume !(0 == ~t4_st~0); 83307#L472 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6#1 := 0; 83309#L484 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 83089#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 83090#L499 assume !(0 != eval_~tmp~0#1); 85640#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 85638#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 85636#L599-3 assume !(0 == ~M_E~0); 85634#L599-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 85632#L604-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 85630#L609-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 85627#L614-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 85624#L619-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 85619#L624-3 assume !(0 == ~E_M~0); 85615#L629-3 assume !(0 == ~E_1~0); 85612#L634-3 assume !(0 == ~E_2~0); 85609#L639-3 assume 0 == ~E_3~0;~E_3~0 := 1; 85601#L644-3 assume 0 == ~E_4~0;~E_4~0 := 1; 85548#L649-3 assume 0 == ~E_5~0;~E_5~0 := 1; 81648#L654-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 81649#L292-21 assume !(1 == ~m_pc~0); 81776#L292-23 is_master_triggered_~__retres1~0#1 := 0; 85681#L303-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 85680#is_master_triggered_returnLabel#8 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 85679#L743-21 assume !(0 != activate_threads_~tmp~1#1); 85678#L743-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 85677#L311-21 assume !(1 == ~t1_pc~0); 85676#L311-23 is_transmit1_triggered_~__retres1~1#1 := 0; 85675#L322-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 85674#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 85673#L751-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 85672#L751-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 85671#L330-21 assume !(1 == ~t2_pc~0); 85669#L330-23 is_transmit2_triggered_~__retres1~2#1 := 0; 85668#L341-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 85667#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 85666#L759-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 85665#L759-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 85664#L349-21 assume !(1 == ~t3_pc~0); 85663#L349-23 is_transmit3_triggered_~__retres1~3#1 := 0; 85661#L360-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 85659#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 85657#L767-21 assume !(0 != activate_threads_~tmp___2~0#1); 85655#L767-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 85654#L368-21 assume !(1 == ~t4_pc~0); 85653#L368-23 is_transmit4_triggered_~__retres1~4#1 := 0; 85652#L379-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 85651#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 85650#L775-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 85649#L775-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 85648#L387-21 assume 1 == ~t5_pc~0; 85647#L388-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 85645#L398-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 85644#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 85643#L783-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 85642#L783-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 85641#L667-3 assume !(1 == ~M_E~0); 83194#L667-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 85639#L672-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 85637#L677-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 85635#L682-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 85633#L687-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 85631#L692-3 assume 1 == ~E_M~0;~E_M~0 := 2; 85628#L697-3 assume !(1 == ~E_1~0); 85625#L702-3 assume !(1 == ~E_2~0); 85620#L707-3 assume 1 == ~E_3~0;~E_3~0 := 2; 85616#L712-3 assume 1 == ~E_4~0;~E_4~0 := 2; 85613#L717-3 assume 1 == ~E_5~0;~E_5~0 := 2; 85610#L722-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 85606#L452-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 85598#L484-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 85589#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 81640#L947 assume !(0 == start_simulation_~tmp~3#1); 81641#L947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 83335#L452-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 83329#L484-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 83327#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret18#1;havoc stop_simulation_#t~ret18#1; 83325#L902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 83323#L909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 83319#stop_simulation_returnLabel#1 start_simulation_#t~ret20#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 83317#L960 assume !(0 != start_simulation_~tmp___0~1#1); 81799#L928-2 [2022-12-13 22:01:25,194 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 22:01:25,194 INFO L85 PathProgramCache]: Analyzing trace with hash 1000780869, now seen corresponding path program 3 times [2022-12-13 22:01:25,195 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 22:01:25,195 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [918628899] [2022-12-13 22:01:25,195 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 22:01:25,195 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 22:01:25,208 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 22:01:25,209 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 22:01:25,217 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 22:01:25,238 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 22:01:25,238 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 22:01:25,239 INFO L85 PathProgramCache]: Analyzing trace with hash -879734976, now seen corresponding path program 1 times [2022-12-13 22:01:25,239 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 22:01:25,239 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [386425536] [2022-12-13 22:01:25,239 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 22:01:25,239 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 22:01:25,247 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 22:01:25,268 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 22:01:25,269 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 22:01:25,269 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [386425536] [2022-12-13 22:01:25,269 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [386425536] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 22:01:25,269 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 22:01:25,269 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 22:01:25,269 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1052897806] [2022-12-13 22:01:25,269 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 22:01:25,270 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 22:01:25,270 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 22:01:25,270 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 22:01:25,270 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 22:01:25,270 INFO L87 Difference]: Start difference. First operand 4888 states and 6767 transitions. cyclomatic complexity: 1883 Second operand has 3 states, 3 states have (on average 29.666666666666668) internal successors, (89), 3 states have internal predecessors, (89), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 22:01:25,339 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 22:01:25,339 INFO L93 Difference]: Finished difference Result 8269 states and 11285 transitions. [2022-12-13 22:01:25,339 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 8269 states and 11285 transitions. [2022-12-13 22:01:25,368 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 8156 [2022-12-13 22:01:25,388 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 8269 states to 8269 states and 11285 transitions. [2022-12-13 22:01:25,389 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8269 [2022-12-13 22:01:25,393 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8269 [2022-12-13 22:01:25,393 INFO L73 IsDeterministic]: Start isDeterministic. Operand 8269 states and 11285 transitions. [2022-12-13 22:01:25,398 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 22:01:25,399 INFO L218 hiAutomatonCegarLoop]: Abstraction has 8269 states and 11285 transitions. [2022-12-13 22:01:25,404 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8269 states and 11285 transitions. [2022-12-13 22:01:25,464 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8269 to 7957. [2022-12-13 22:01:25,472 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7957 states, 7957 states have (on average 1.3669724770642202) internal successors, (10877), 7956 states have internal predecessors, (10877), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 22:01:25,487 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7957 states to 7957 states and 10877 transitions. [2022-12-13 22:01:25,487 INFO L240 hiAutomatonCegarLoop]: Abstraction has 7957 states and 10877 transitions. [2022-12-13 22:01:25,488 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 22:01:25,488 INFO L428 stractBuchiCegarLoop]: Abstraction has 7957 states and 10877 transitions. [2022-12-13 22:01:25,488 INFO L335 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2022-12-13 22:01:25,488 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7957 states and 10877 transitions. [2022-12-13 22:01:25,503 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 7844 [2022-12-13 22:01:25,503 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 22:01:25,503 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 22:01:25,503 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 22:01:25,504 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 22:01:25,504 INFO L748 eck$LassoCheckResult]: Stem: 94778#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 94779#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 94914#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 94915#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 95085#L414 assume 1 == ~m_i~0;~m_st~0 := 0; 94851#L414-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 94852#L419-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 95055#L424-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 94827#L429-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 94828#L434-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 95048#L439-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 94823#L599 assume !(0 == ~M_E~0); 94824#L599-2 assume !(0 == ~T1_E~0); 94485#L604-1 assume !(0 == ~T2_E~0); 94474#L609-1 assume !(0 == ~T3_E~0); 94475#L614-1 assume !(0 == ~T4_E~0); 94642#L619-1 assume !(0 == ~T5_E~0); 94757#L624-1 assume !(0 == ~E_M~0); 94855#L629-1 assume !(0 == ~E_1~0); 94567#L634-1 assume !(0 == ~E_2~0); 94568#L639-1 assume !(0 == ~E_3~0); 94985#L644-1 assume !(0 == ~E_4~0); 95004#L649-1 assume !(0 == ~E_5~0); 94529#L654-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 94530#L292 assume !(1 == ~m_pc~0); 94656#L292-2 is_master_triggered_~__retres1~0#1 := 0; 94793#L303 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 94753#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 94754#L743 assume !(0 != activate_threads_~tmp~1#1); 94599#L743-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 94600#L311 assume !(1 == ~t1_pc~0); 94984#L311-2 is_transmit1_triggered_~__retres1~1#1 := 0; 94863#L322 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 94520#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 94501#L751 assume !(0 != activate_threads_~tmp___0~0#1); 94502#L751-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 94986#L330 assume !(1 == ~t2_pc~0); 94760#L330-2 is_transmit2_triggered_~__retres1~2#1 := 0; 94657#L341 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 94658#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 94920#L759 assume !(0 != activate_threads_~tmp___1~0#1); 95082#L759-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 94643#L349 assume !(1 == ~t3_pc~0); 94644#L349-2 is_transmit3_triggered_~__retres1~3#1 := 0; 95108#L360 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 95122#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 95114#L767 assume !(0 != activate_threads_~tmp___2~0#1); 95075#L767-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 95076#L368 assume !(1 == ~t4_pc~0); 94723#L368-2 is_transmit4_triggered_~__retres1~4#1 := 0; 94724#L379 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 94629#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 94630#L775 assume !(0 != activate_threads_~tmp___3~0#1); 94488#L775-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 94489#L387 assume !(1 == ~t5_pc~0); 94880#L387-2 is_transmit5_triggered_~__retres1~5#1 := 0; 94881#L398 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 94762#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 94616#L783 assume !(0 != activate_threads_~tmp___4~0#1); 94617#L783-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 94709#L667 assume !(1 == ~M_E~0); 94784#L667-2 assume !(1 == ~T1_E~0); 94994#L672-1 assume !(1 == ~T2_E~0); 94743#L677-1 assume !(1 == ~T3_E~0); 94744#L682-1 assume !(1 == ~T4_E~0); 94965#L687-1 assume !(1 == ~T5_E~0); 95043#L692-1 assume !(1 == ~E_M~0); 94949#L697-1 assume !(1 == ~E_1~0); 94950#L702-1 assume !(1 == ~E_2~0); 95003#L707-1 assume !(1 == ~E_3~0); 94843#L712-1 assume !(1 == ~E_4~0); 94844#L717-1 assume !(1 == ~E_5~0); 94972#L722-1 assume { :end_inline_reset_delta_events } true; 94973#L928-2 assume !false; 96568#L929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 96567#L574 [2022-12-13 22:01:25,504 INFO L750 eck$LassoCheckResult]: Loop: 96567#L574 assume !false; 96566#L495 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 96565#L452 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 96564#L484 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 96563#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 96561#L499 assume 0 != eval_~tmp~0#1; 96560#L499-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 96558#L507 assume !(0 != eval_~tmp_ndt_1~0#1); 96557#L504 assume !(0 == ~t1_st~0); 96491#L518 assume !(0 == ~t2_st~0); 96489#L532 assume !(0 == ~t3_st~0); 96476#L546 assume !(0 == ~t4_st~0); 96468#L560 assume !(0 == ~t5_st~0); 96567#L574 [2022-12-13 22:01:25,504 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 22:01:25,504 INFO L85 PathProgramCache]: Analyzing trace with hash -322248313, now seen corresponding path program 1 times [2022-12-13 22:01:25,504 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 22:01:25,504 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1944360665] [2022-12-13 22:01:25,504 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 22:01:25,504 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 22:01:25,510 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 22:01:25,510 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 22:01:25,514 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 22:01:25,522 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 22:01:25,523 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 22:01:25,523 INFO L85 PathProgramCache]: Analyzing trace with hash 878346699, now seen corresponding path program 1 times [2022-12-13 22:01:25,523 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 22:01:25,523 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [737442164] [2022-12-13 22:01:25,523 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 22:01:25,523 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 22:01:25,525 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 22:01:25,525 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 22:01:25,526 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 22:01:25,528 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 22:01:25,528 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 22:01:25,528 INFO L85 PathProgramCache]: Analyzing trace with hash 136104453, now seen corresponding path program 1 times [2022-12-13 22:01:25,528 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 22:01:25,528 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [771101030] [2022-12-13 22:01:25,528 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 22:01:25,528 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 22:01:25,534 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 22:01:25,552 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 22:01:25,552 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 22:01:25,552 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [771101030] [2022-12-13 22:01:25,553 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [771101030] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 22:01:25,553 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 22:01:25,553 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 22:01:25,553 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1816851632] [2022-12-13 22:01:25,553 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 22:01:25,620 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 22:01:25,620 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 22:01:25,620 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 22:01:25,620 INFO L87 Difference]: Start difference. First operand 7957 states and 10877 transitions. cyclomatic complexity: 2926 Second operand has 3 states, 3 states have (on average 29.333333333333332) internal successors, (88), 3 states have internal predecessors, (88), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 22:01:25,701 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 22:01:25,701 INFO L93 Difference]: Finished difference Result 15130 states and 20503 transitions. [2022-12-13 22:01:25,702 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 15130 states and 20503 transitions. [2022-12-13 22:01:25,758 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 14531 [2022-12-13 22:01:25,785 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 15130 states to 15130 states and 20503 transitions. [2022-12-13 22:01:25,785 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 15130 [2022-12-13 22:01:25,792 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 15130 [2022-12-13 22:01:25,792 INFO L73 IsDeterministic]: Start isDeterministic. Operand 15130 states and 20503 transitions. [2022-12-13 22:01:25,798 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 22:01:25,798 INFO L218 hiAutomatonCegarLoop]: Abstraction has 15130 states and 20503 transitions. [2022-12-13 22:01:25,803 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15130 states and 20503 transitions. [2022-12-13 22:01:25,921 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15130 to 14854. [2022-12-13 22:01:25,947 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 14854 states, 14854 states have (on average 1.3557964184731386) internal successors, (20139), 14853 states have internal predecessors, (20139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 22:01:25,969 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14854 states to 14854 states and 20139 transitions. [2022-12-13 22:01:25,970 INFO L240 hiAutomatonCegarLoop]: Abstraction has 14854 states and 20139 transitions. [2022-12-13 22:01:25,970 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 22:01:25,970 INFO L428 stractBuchiCegarLoop]: Abstraction has 14854 states and 20139 transitions. [2022-12-13 22:01:25,971 INFO L335 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2022-12-13 22:01:25,971 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 14854 states and 20139 transitions. [2022-12-13 22:01:26,033 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 14255 [2022-12-13 22:01:26,033 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 22:01:26,033 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 22:01:26,034 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 22:01:26,034 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 22:01:26,034 INFO L748 eck$LassoCheckResult]: Stem: 117867#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 117868#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 117997#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 117998#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 118175#L414 assume 1 == ~m_i~0;~m_st~0 := 0; 117936#L414-2 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 117937#L419-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 125041#L424-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 125040#L429-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 125039#L434-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 125038#L439-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 125037#L599 assume !(0 == ~M_E~0); 125036#L599-2 assume !(0 == ~T1_E~0); 125035#L604-1 assume !(0 == ~T2_E~0); 125034#L609-1 assume !(0 == ~T3_E~0); 125033#L614-1 assume !(0 == ~T4_E~0); 125032#L619-1 assume !(0 == ~T5_E~0); 125031#L624-1 assume !(0 == ~E_M~0); 125030#L629-1 assume !(0 == ~E_1~0); 125029#L634-1 assume !(0 == ~E_2~0); 125028#L639-1 assume !(0 == ~E_3~0); 125027#L644-1 assume !(0 == ~E_4~0); 125026#L649-1 assume !(0 == ~E_5~0); 125025#L654-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 125024#L292 assume !(1 == ~m_pc~0); 125023#L292-2 is_master_triggered_~__retres1~0#1 := 0; 125022#L303 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 125021#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 125020#L743 assume !(0 != activate_threads_~tmp~1#1); 125019#L743-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 125018#L311 assume !(1 == ~t1_pc~0); 125017#L311-2 is_transmit1_triggered_~__retres1~1#1 := 0; 117949#L322 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 117616#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 117617#L751 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 117598#L751-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 118064#L330 assume !(1 == ~t2_pc~0); 117849#L330-2 is_transmit2_triggered_~__retres1~2#1 := 0; 117750#L341 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 117751#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 118002#L759 assume !(0 != activate_threads_~tmp___1~0#1); 118174#L759-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 117736#L349 assume !(1 == ~t3_pc~0); 117737#L349-2 is_transmit3_triggered_~__retres1~3#1 := 0; 118204#L360 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 118227#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 118218#L767 assume !(0 != activate_threads_~tmp___2~0#1); 118166#L767-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 118167#L368 assume !(1 == ~t4_pc~0); 117814#L368-2 is_transmit4_triggered_~__retres1~4#1 := 0; 117815#L379 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 117722#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 117723#L775 assume !(0 != activate_threads_~tmp___3~0#1); 117583#L775-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 117584#L387 assume !(1 == ~t5_pc~0); 117964#L387-2 is_transmit5_triggered_~__retres1~5#1 := 0; 117965#L398 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 117851#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 117709#L783 assume !(0 != activate_threads_~tmp___4~0#1); 117710#L783-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 117803#L667 assume !(1 == ~M_E~0); 117872#L667-2 assume !(1 == ~T1_E~0); 118072#L672-1 assume !(1 == ~T2_E~0); 117833#L677-1 assume !(1 == ~T3_E~0); 117834#L682-1 assume !(1 == ~T4_E~0); 118043#L687-1 assume !(1 == ~T5_E~0); 118126#L692-1 assume !(1 == ~E_M~0); 118029#L697-1 assume !(1 == ~E_1~0); 118030#L702-1 assume !(1 == ~E_2~0); 118213#L707-1 assume !(1 == ~E_3~0); 124779#L712-1 assume !(1 == ~E_4~0); 118071#L717-1 assume !(1 == ~E_5~0); 118050#L722-1 assume { :end_inline_reset_delta_events } true; 118051#L928-2 assume !false; 125717#L929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 125701#L574 [2022-12-13 22:01:26,034 INFO L750 eck$LassoCheckResult]: Loop: 125701#L574 assume !false; 125702#L495 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 125626#L452 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 125627#L484 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 125611#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 125612#L499 assume 0 != eval_~tmp~0#1; 125574#L499-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 125576#L507 assume !(0 != eval_~tmp_ndt_1~0#1); 125420#L504 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 124825#L521 assume !(0 != eval_~tmp_ndt_2~0#1); 125762#L518 assume !(0 == ~t2_st~0); 125763#L532 assume !(0 == ~t3_st~0); 125723#L546 assume !(0 == ~t4_st~0); 125721#L560 assume !(0 == ~t5_st~0); 125701#L574 [2022-12-13 22:01:26,034 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 22:01:26,035 INFO L85 PathProgramCache]: Analyzing trace with hash 1162562755, now seen corresponding path program 1 times [2022-12-13 22:01:26,035 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 22:01:26,035 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [429319123] [2022-12-13 22:01:26,035 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 22:01:26,035 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 22:01:26,042 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 22:01:26,057 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 22:01:26,058 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 22:01:26,058 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [429319123] [2022-12-13 22:01:26,058 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [429319123] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 22:01:26,058 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 22:01:26,058 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 22:01:26,058 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [505439904] [2022-12-13 22:01:26,058 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 22:01:26,058 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 22:01:26,059 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 22:01:26,059 INFO L85 PathProgramCache]: Analyzing trace with hash 511053362, now seen corresponding path program 1 times [2022-12-13 22:01:26,059 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 22:01:26,059 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1057573260] [2022-12-13 22:01:26,059 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 22:01:26,059 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 22:01:26,062 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 22:01:26,062 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 22:01:26,064 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 22:01:26,066 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 22:01:26,142 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 22:01:26,142 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 22:01:26,142 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 22:01:26,142 INFO L87 Difference]: Start difference. First operand 14854 states and 20139 transitions. cyclomatic complexity: 5297 Second operand has 3 states, 3 states have (on average 25.0) internal successors, (75), 3 states have internal predecessors, (75), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 22:01:26,179 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 22:01:26,179 INFO L93 Difference]: Finished difference Result 12313 states and 16719 transitions. [2022-12-13 22:01:26,180 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 12313 states and 16719 transitions. [2022-12-13 22:01:26,222 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 12186 [2022-12-13 22:01:26,248 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 12313 states to 12313 states and 16719 transitions. [2022-12-13 22:01:26,249 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 12313 [2022-12-13 22:01:26,255 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 12313 [2022-12-13 22:01:26,255 INFO L73 IsDeterministic]: Start isDeterministic. Operand 12313 states and 16719 transitions. [2022-12-13 22:01:26,263 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 22:01:26,264 INFO L218 hiAutomatonCegarLoop]: Abstraction has 12313 states and 16719 transitions. [2022-12-13 22:01:26,269 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12313 states and 16719 transitions. [2022-12-13 22:01:26,415 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12313 to 12313. [2022-12-13 22:01:26,423 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 12313 states, 12313 states have (on average 1.3578331844392106) internal successors, (16719), 12312 states have internal predecessors, (16719), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 22:01:26,445 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12313 states to 12313 states and 16719 transitions. [2022-12-13 22:01:26,445 INFO L240 hiAutomatonCegarLoop]: Abstraction has 12313 states and 16719 transitions. [2022-12-13 22:01:26,445 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 22:01:26,446 INFO L428 stractBuchiCegarLoop]: Abstraction has 12313 states and 16719 transitions. [2022-12-13 22:01:26,446 INFO L335 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2022-12-13 22:01:26,446 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 12313 states and 16719 transitions. [2022-12-13 22:01:26,476 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 12186 [2022-12-13 22:01:26,477 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 22:01:26,477 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 22:01:26,478 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 22:01:26,478 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 22:01:26,478 INFO L748 eck$LassoCheckResult]: Stem: 145047#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 145048#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 145176#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 145177#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 145348#L414 assume 1 == ~m_i~0;~m_st~0 := 0; 145117#L414-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 145118#L419-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 145314#L424-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 145093#L429-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 145094#L434-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 145304#L439-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 145089#L599 assume !(0 == ~M_E~0); 145090#L599-2 assume !(0 == ~T1_E~0); 144753#L604-1 assume !(0 == ~T2_E~0); 144742#L609-1 assume !(0 == ~T3_E~0); 144743#L614-1 assume !(0 == ~T4_E~0); 144908#L619-1 assume !(0 == ~T5_E~0); 145024#L624-1 assume !(0 == ~E_M~0); 145121#L629-1 assume !(0 == ~E_1~0); 144834#L634-1 assume !(0 == ~E_2~0); 144835#L639-1 assume !(0 == ~E_3~0); 145243#L644-1 assume !(0 == ~E_4~0); 145262#L649-1 assume !(0 == ~E_5~0); 144797#L654-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 144798#L292 assume !(1 == ~m_pc~0); 144922#L292-2 is_master_triggered_~__retres1~0#1 := 0; 145061#L303 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 145020#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 145021#L743 assume !(0 != activate_threads_~tmp~1#1); 144866#L743-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 144867#L311 assume !(1 == ~t1_pc~0); 145242#L311-2 is_transmit1_triggered_~__retres1~1#1 := 0; 145129#L322 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 144788#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 144769#L751 assume !(0 != activate_threads_~tmp___0~0#1); 144770#L751-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 145244#L330 assume !(1 == ~t2_pc~0); 145027#L330-2 is_transmit2_triggered_~__retres1~2#1 := 0; 144923#L341 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 144924#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 145182#L759 assume !(0 != activate_threads_~tmp___1~0#1); 145345#L759-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 144909#L349 assume !(1 == ~t3_pc~0); 144910#L349-2 is_transmit3_triggered_~__retres1~3#1 := 0; 145385#L360 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 145408#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 145396#L767 assume !(0 != activate_threads_~tmp___2~0#1); 145336#L767-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 145337#L368 assume !(1 == ~t4_pc~0); 144990#L368-2 is_transmit4_triggered_~__retres1~4#1 := 0; 144991#L379 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 144894#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 144895#L775 assume !(0 != activate_threads_~tmp___3~0#1); 144756#L775-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 144757#L387 assume !(1 == ~t5_pc~0); 145144#L387-2 is_transmit5_triggered_~__retres1~5#1 := 0; 145145#L398 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 145029#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 144880#L783 assume !(0 != activate_threads_~tmp___4~0#1); 144881#L783-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 144975#L667 assume !(1 == ~M_E~0); 145053#L667-2 assume !(1 == ~T1_E~0); 145251#L672-1 assume !(1 == ~T2_E~0); 145011#L677-1 assume !(1 == ~T3_E~0); 145012#L682-1 assume !(1 == ~T4_E~0); 145223#L687-1 assume !(1 == ~T5_E~0); 145299#L692-1 assume !(1 == ~E_M~0); 145208#L697-1 assume !(1 == ~E_1~0); 145209#L702-1 assume !(1 == ~E_2~0); 145261#L707-1 assume !(1 == ~E_3~0); 145110#L712-1 assume !(1 == ~E_4~0); 145111#L717-1 assume !(1 == ~E_5~0); 145230#L722-1 assume { :end_inline_reset_delta_events } true; 145231#L928-2 assume !false; 156087#L929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 156086#L574 [2022-12-13 22:01:26,478 INFO L750 eck$LassoCheckResult]: Loop: 156086#L574 assume !false; 156085#L495 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 156082#L452 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 156081#L484 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 156079#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 156077#L499 assume 0 != eval_~tmp~0#1; 156076#L499-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 156074#L507 assume !(0 != eval_~tmp_ndt_1~0#1); 156075#L504 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 145430#L521 assume !(0 != eval_~tmp_ndt_2~0#1); 145431#L518 assume !(0 == ~t2_st~0); 156098#L532 assume !(0 == ~t3_st~0); 156094#L546 assume !(0 == ~t4_st~0); 156091#L560 assume !(0 == ~t5_st~0); 156086#L574 [2022-12-13 22:01:26,479 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 22:01:26,479 INFO L85 PathProgramCache]: Analyzing trace with hash -322248313, now seen corresponding path program 2 times [2022-12-13 22:01:26,479 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 22:01:26,479 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [12042184] [2022-12-13 22:01:26,479 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 22:01:26,479 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 22:01:26,489 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 22:01:26,489 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 22:01:26,494 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 22:01:26,503 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 22:01:26,503 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 22:01:26,503 INFO L85 PathProgramCache]: Analyzing trace with hash 511053362, now seen corresponding path program 2 times [2022-12-13 22:01:26,503 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 22:01:26,503 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1374584603] [2022-12-13 22:01:26,504 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 22:01:26,504 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 22:01:26,506 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 22:01:26,506 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 22:01:26,508 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 22:01:26,509 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 22:01:26,510 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 22:01:26,510 INFO L85 PathProgramCache]: Analyzing trace with hash -1023619784, now seen corresponding path program 1 times [2022-12-13 22:01:26,510 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 22:01:26,510 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [876864340] [2022-12-13 22:01:26,510 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 22:01:26,510 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 22:01:26,518 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 22:01:26,535 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 22:01:26,536 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 22:01:26,536 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [876864340] [2022-12-13 22:01:26,536 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [876864340] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 22:01:26,536 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 22:01:26,536 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 22:01:26,536 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1805388524] [2022-12-13 22:01:26,536 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 22:01:26,615 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 22:01:26,615 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 22:01:26,615 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 22:01:26,616 INFO L87 Difference]: Start difference. First operand 12313 states and 16719 transitions. cyclomatic complexity: 4412 Second operand has 3 states, 3 states have (on average 29.666666666666668) internal successors, (89), 3 states have internal predecessors, (89), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 22:01:26,685 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 22:01:26,685 INFO L93 Difference]: Finished difference Result 22957 states and 31085 transitions. [2022-12-13 22:01:26,686 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 22957 states and 31085 transitions. [2022-12-13 22:01:26,777 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 22784 [2022-12-13 22:01:26,820 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 22957 states to 22957 states and 31085 transitions. [2022-12-13 22:01:26,820 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 22957 [2022-12-13 22:01:26,831 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 22957 [2022-12-13 22:01:26,831 INFO L73 IsDeterministic]: Start isDeterministic. Operand 22957 states and 31085 transitions. [2022-12-13 22:01:26,842 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 22:01:26,842 INFO L218 hiAutomatonCegarLoop]: Abstraction has 22957 states and 31085 transitions. [2022-12-13 22:01:26,853 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 22957 states and 31085 transitions. [2022-12-13 22:01:27,010 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 22957 to 21967. [2022-12-13 22:01:27,029 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 21967 states, 21967 states have (on average 1.3568989848408977) internal successors, (29807), 21966 states have internal predecessors, (29807), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 22:01:27,074 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21967 states to 21967 states and 29807 transitions. [2022-12-13 22:01:27,074 INFO L240 hiAutomatonCegarLoop]: Abstraction has 21967 states and 29807 transitions. [2022-12-13 22:01:27,075 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 22:01:27,075 INFO L428 stractBuchiCegarLoop]: Abstraction has 21967 states and 29807 transitions. [2022-12-13 22:01:27,075 INFO L335 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2022-12-13 22:01:27,075 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 21967 states and 29807 transitions. [2022-12-13 22:01:27,138 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 21794 [2022-12-13 22:01:27,139 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 22:01:27,139 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 22:01:27,140 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 22:01:27,140 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 22:01:27,140 INFO L748 eck$LassoCheckResult]: Stem: 180315#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 180316#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 180446#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 180447#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 180634#L414 assume 1 == ~m_i~0;~m_st~0 := 0; 180383#L414-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 180384#L419-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 180601#L424-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 180362#L429-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 180363#L434-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 180595#L439-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 180358#L599 assume !(0 == ~M_E~0); 180359#L599-2 assume !(0 == ~T1_E~0); 180033#L604-1 assume !(0 == ~T2_E~0); 180020#L609-1 assume !(0 == ~T3_E~0); 180021#L614-1 assume !(0 == ~T4_E~0); 180185#L619-1 assume !(0 == ~T5_E~0); 180292#L624-1 assume !(0 == ~E_M~0); 180387#L629-1 assume !(0 == ~E_1~0); 180112#L634-1 assume !(0 == ~E_2~0); 180113#L639-1 assume !(0 == ~E_3~0); 180521#L644-1 assume !(0 == ~E_4~0); 180541#L649-1 assume !(0 == ~E_5~0); 180075#L654-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 180076#L292 assume !(1 == ~m_pc~0); 180199#L292-2 is_master_triggered_~__retres1~0#1 := 0; 180328#L303 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 180290#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 180291#L743 assume !(0 != activate_threads_~tmp~1#1); 180144#L743-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 180145#L311 assume !(1 == ~t1_pc~0); 180520#L311-2 is_transmit1_triggered_~__retres1~1#1 := 0; 180395#L322 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 180066#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 180047#L751 assume !(0 != activate_threads_~tmp___0~0#1); 180048#L751-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 180524#L330 assume !(1 == ~t2_pc~0); 180295#L330-2 is_transmit2_triggered_~__retres1~2#1 := 0; 180201#L341 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 180202#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 180451#L759 assume !(0 != activate_threads_~tmp___1~0#1); 180633#L759-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 180188#L349 assume !(1 == ~t3_pc~0); 180189#L349-2 is_transmit3_triggered_~__retres1~3#1 := 0; 180484#L360 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 180485#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 180680#L767 assume !(0 != activate_threads_~tmp___2~0#1); 180620#L767-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 180621#L368 assume !(1 == ~t4_pc~0); 180262#L368-2 is_transmit4_triggered_~__retres1~4#1 := 0; 180263#L379 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 180171#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 180172#L775 assume !(0 != activate_threads_~tmp___3~0#1); 180034#L775-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 180035#L387 assume !(1 == ~t5_pc~0); 180409#L387-2 is_transmit5_triggered_~__retres1~5#1 := 0; 180410#L398 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 180298#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 180161#L783 assume !(0 != activate_threads_~tmp___4~0#1); 180162#L783-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 180251#L667 assume !(1 == ~M_E~0); 180320#L667-2 assume !(1 == ~T1_E~0); 180531#L672-1 assume !(1 == ~T2_E~0); 180279#L677-1 assume !(1 == ~T3_E~0); 180280#L682-1 assume !(1 == ~T4_E~0); 180501#L687-1 assume !(1 == ~T5_E~0); 180588#L692-1 assume !(1 == ~E_M~0); 180482#L697-1 assume !(1 == ~E_1~0); 180483#L702-1 assume !(1 == ~E_2~0); 180540#L707-1 assume !(1 == ~E_3~0); 180377#L712-1 assume !(1 == ~E_4~0); 180378#L717-1 assume !(1 == ~E_5~0); 180508#L722-1 assume { :end_inline_reset_delta_events } true; 180509#L928-2 assume !false; 197460#L929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 196785#L574 [2022-12-13 22:01:27,140 INFO L750 eck$LassoCheckResult]: Loop: 196785#L574 assume !false; 196786#L495 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 196778#L452 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 196779#L484 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 196774#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 196773#L499 assume 0 != eval_~tmp~0#1; 196769#L499-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 196771#L507 assume !(0 != eval_~tmp_ndt_1~0#1); 195833#L504 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 195834#L521 assume !(0 != eval_~tmp_ndt_2~0#1); 196808#L518 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 196805#L535 assume !(0 != eval_~tmp_ndt_3~0#1); 196803#L532 assume !(0 == ~t3_st~0); 196798#L546 assume !(0 == ~t4_st~0); 196793#L560 assume !(0 == ~t5_st~0); 196785#L574 [2022-12-13 22:01:27,141 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 22:01:27,141 INFO L85 PathProgramCache]: Analyzing trace with hash -322248313, now seen corresponding path program 3 times [2022-12-13 22:01:27,141 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 22:01:27,141 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1453644238] [2022-12-13 22:01:27,141 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 22:01:27,141 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 22:01:27,148 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 22:01:27,148 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 22:01:27,153 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 22:01:27,160 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 22:01:27,160 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 22:01:27,161 INFO L85 PathProgramCache]: Analyzing trace with hash -1506337788, now seen corresponding path program 1 times [2022-12-13 22:01:27,161 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 22:01:27,161 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [814843589] [2022-12-13 22:01:27,161 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 22:01:27,161 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 22:01:27,164 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 22:01:27,164 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 22:01:27,166 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 22:01:27,168 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 22:01:27,168 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 22:01:27,169 INFO L85 PathProgramCache]: Analyzing trace with hash -1836565058, now seen corresponding path program 1 times [2022-12-13 22:01:27,169 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 22:01:27,169 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [240712635] [2022-12-13 22:01:27,169 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 22:01:27,169 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 22:01:27,179 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 22:01:27,202 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 22:01:27,203 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 22:01:27,203 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [240712635] [2022-12-13 22:01:27,203 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [240712635] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 22:01:27,203 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 22:01:27,203 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 22:01:27,203 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1138968808] [2022-12-13 22:01:27,203 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 22:01:27,309 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 22:01:27,310 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 22:01:27,310 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 22:01:27,310 INFO L87 Difference]: Start difference. First operand 21967 states and 29807 transitions. cyclomatic complexity: 7846 Second operand has 3 states, 3 states have (on average 30.0) internal successors, (90), 3 states have internal predecessors, (90), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 22:01:27,469 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 22:01:27,470 INFO L93 Difference]: Finished difference Result 39957 states and 54205 transitions. [2022-12-13 22:01:27,470 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 39957 states and 54205 transitions. [2022-12-13 22:01:27,614 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 39692 [2022-12-13 22:01:27,726 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 39957 states to 39957 states and 54205 transitions. [2022-12-13 22:01:27,726 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 39957 [2022-12-13 22:01:27,737 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 39957 [2022-12-13 22:01:27,737 INFO L73 IsDeterministic]: Start isDeterministic. Operand 39957 states and 54205 transitions. [2022-12-13 22:01:27,748 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 22:01:27,748 INFO L218 hiAutomatonCegarLoop]: Abstraction has 39957 states and 54205 transitions. [2022-12-13 22:01:27,759 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 39957 states and 54205 transitions. [2022-12-13 22:01:27,977 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 39957 to 38697. [2022-12-13 22:01:27,995 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 38697 states, 38697 states have (on average 1.358890870093289) internal successors, (52585), 38696 states have internal predecessors, (52585), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 22:01:28,038 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 38697 states to 38697 states and 52585 transitions. [2022-12-13 22:01:28,039 INFO L240 hiAutomatonCegarLoop]: Abstraction has 38697 states and 52585 transitions. [2022-12-13 22:01:28,039 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 22:01:28,039 INFO L428 stractBuchiCegarLoop]: Abstraction has 38697 states and 52585 transitions. [2022-12-13 22:01:28,040 INFO L335 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2022-12-13 22:01:28,040 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 38697 states and 52585 transitions. [2022-12-13 22:01:28,113 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 38432 [2022-12-13 22:01:28,114 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 22:01:28,114 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 22:01:28,114 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 22:01:28,114 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 22:01:28,114 INFO L748 eck$LassoCheckResult]: Stem: 242253#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 242254#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 242382#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 242383#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 242580#L414 assume 1 == ~m_i~0;~m_st~0 := 0; 242324#L414-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 242325#L419-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 242545#L424-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 242300#L429-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 242301#L434-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 242535#L439-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 242296#L599 assume !(0 == ~M_E~0); 242297#L599-2 assume !(0 == ~T1_E~0); 241963#L604-1 assume !(0 == ~T2_E~0); 241952#L609-1 assume !(0 == ~T3_E~0); 241953#L614-1 assume !(0 == ~T4_E~0); 242116#L619-1 assume !(0 == ~T5_E~0); 242230#L624-1 assume !(0 == ~E_M~0); 242328#L629-1 assume !(0 == ~E_1~0); 242043#L634-1 assume !(0 == ~E_2~0); 242044#L639-1 assume !(0 == ~E_3~0); 242460#L644-1 assume !(0 == ~E_4~0); 242485#L649-1 assume !(0 == ~E_5~0); 242006#L654-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 242007#L292 assume !(1 == ~m_pc~0); 242130#L292-2 is_master_triggered_~__retres1~0#1 := 0; 242267#L303 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 242225#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 242226#L743 assume !(0 != activate_threads_~tmp~1#1); 242075#L743-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 242076#L311 assume !(1 == ~t1_pc~0); 242459#L311-2 is_transmit1_triggered_~__retres1~1#1 := 0; 242336#L322 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 241997#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 241979#L751 assume !(0 != activate_threads_~tmp___0~0#1); 241980#L751-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 242462#L330 assume !(1 == ~t2_pc~0); 242233#L330-2 is_transmit2_triggered_~__retres1~2#1 := 0; 242131#L341 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 242132#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 242387#L759 assume !(0 != activate_threads_~tmp___1~0#1); 242578#L759-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 242117#L349 assume !(1 == ~t3_pc~0); 242118#L349-2 is_transmit3_triggered_~__retres1~3#1 := 0; 242615#L360 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 242652#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 242634#L767 assume !(0 != activate_threads_~tmp___2~0#1); 242568#L767-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 242569#L368 assume !(1 == ~t4_pc~0); 242196#L368-2 is_transmit4_triggered_~__retres1~4#1 := 0; 242197#L379 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 242103#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 242104#L775 assume !(0 != activate_threads_~tmp___3~0#1); 241966#L775-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 241967#L387 assume !(1 == ~t5_pc~0); 242348#L387-2 is_transmit5_triggered_~__retres1~5#1 := 0; 242349#L398 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 242236#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 242090#L783 assume !(0 != activate_threads_~tmp___4~0#1); 242091#L783-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 242183#L667 assume !(1 == ~M_E~0); 242258#L667-2 assume !(1 == ~T1_E~0); 242470#L672-1 assume !(1 == ~T2_E~0); 242216#L677-1 assume !(1 == ~T3_E~0); 242217#L682-1 assume !(1 == ~T4_E~0); 242440#L687-1 assume !(1 == ~T5_E~0); 242529#L692-1 assume !(1 == ~E_M~0); 242422#L697-1 assume !(1 == ~E_1~0); 242423#L702-1 assume !(1 == ~E_2~0); 242484#L707-1 assume !(1 == ~E_3~0); 242316#L712-1 assume !(1 == ~E_4~0); 242317#L717-1 assume !(1 == ~E_5~0); 242448#L722-1 assume { :end_inline_reset_delta_events } true; 242449#L928-2 assume !false; 258845#L929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 258843#L574 [2022-12-13 22:01:28,115 INFO L750 eck$LassoCheckResult]: Loop: 258843#L574 assume !false; 258841#L495 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 258838#L452 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 258836#L484 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 258834#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 258814#L499 assume 0 != eval_~tmp~0#1; 258815#L499-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 259023#L507 assume !(0 != eval_~tmp_ndt_1~0#1); 259022#L504 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 259019#L521 assume !(0 != eval_~tmp_ndt_2~0#1); 258873#L518 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 258868#L535 assume !(0 != eval_~tmp_ndt_3~0#1); 258862#L532 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 258265#L549 assume !(0 != eval_~tmp_ndt_4~0#1); 258853#L546 assume !(0 == ~t4_st~0); 258849#L560 assume !(0 == ~t5_st~0); 258843#L574 [2022-12-13 22:01:28,115 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 22:01:28,115 INFO L85 PathProgramCache]: Analyzing trace with hash -322248313, now seen corresponding path program 4 times [2022-12-13 22:01:28,115 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 22:01:28,115 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [965686762] [2022-12-13 22:01:28,115 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 22:01:28,115 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 22:01:28,122 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 22:01:28,122 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 22:01:28,126 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 22:01:28,133 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 22:01:28,134 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 22:01:28,134 INFO L85 PathProgramCache]: Analyzing trace with hash 542714873, now seen corresponding path program 1 times [2022-12-13 22:01:28,134 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 22:01:28,134 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1790445745] [2022-12-13 22:01:28,134 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 22:01:28,134 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 22:01:28,138 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 22:01:28,138 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 22:01:28,140 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 22:01:28,142 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 22:01:28,142 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 22:01:28,142 INFO L85 PathProgramCache]: Analyzing trace with hash -1104395905, now seen corresponding path program 1 times [2022-12-13 22:01:28,143 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 22:01:28,143 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1291141748] [2022-12-13 22:01:28,143 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 22:01:28,143 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 22:01:28,152 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 22:01:28,178 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 22:01:28,178 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 22:01:28,178 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1291141748] [2022-12-13 22:01:28,178 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1291141748] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 22:01:28,178 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 22:01:28,178 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 22:01:28,178 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [918430927] [2022-12-13 22:01:28,178 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 22:01:28,285 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 22:01:28,285 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 22:01:28,286 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 22:01:28,286 INFO L87 Difference]: Start difference. First operand 38697 states and 52585 transitions. cyclomatic complexity: 13894 Second operand has 3 states, 3 states have (on average 30.333333333333332) internal successors, (91), 3 states have internal predecessors, (91), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 22:01:28,408 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 22:01:28,408 INFO L93 Difference]: Finished difference Result 44799 states and 60795 transitions. [2022-12-13 22:01:28,408 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 44799 states and 60795 transitions. [2022-12-13 22:01:28,569 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 44578 [2022-12-13 22:01:28,622 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 44799 states to 44799 states and 60795 transitions. [2022-12-13 22:01:28,623 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 44799 [2022-12-13 22:01:28,637 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 44799 [2022-12-13 22:01:28,637 INFO L73 IsDeterministic]: Start isDeterministic. Operand 44799 states and 60795 transitions. [2022-12-13 22:01:28,649 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 22:01:28,649 INFO L218 hiAutomatonCegarLoop]: Abstraction has 44799 states and 60795 transitions. [2022-12-13 22:01:28,661 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 44799 states and 60795 transitions. [2022-12-13 22:01:28,955 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 44799 to 44007. [2022-12-13 22:01:28,985 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 44007 states, 44007 states have (on average 1.3585793169268525) internal successors, (59787), 44006 states have internal predecessors, (59787), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 22:01:29,054 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 44007 states to 44007 states and 59787 transitions. [2022-12-13 22:01:29,055 INFO L240 hiAutomatonCegarLoop]: Abstraction has 44007 states and 59787 transitions. [2022-12-13 22:01:29,055 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 22:01:29,055 INFO L428 stractBuchiCegarLoop]: Abstraction has 44007 states and 59787 transitions. [2022-12-13 22:01:29,055 INFO L335 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2022-12-13 22:01:29,055 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 44007 states and 59787 transitions. [2022-12-13 22:01:29,174 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 43786 [2022-12-13 22:01:29,174 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 22:01:29,174 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 22:01:29,175 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 22:01:29,175 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 22:01:29,175 INFO L748 eck$LassoCheckResult]: Stem: 325753#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 325754#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 325888#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 325889#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 326095#L414 assume 1 == ~m_i~0;~m_st~0 := 0; 325827#L414-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 325828#L419-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 326050#L424-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 325803#L429-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 325804#L434-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 326042#L439-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 325799#L599 assume !(0 == ~M_E~0); 325800#L599-2 assume !(0 == ~T1_E~0); 325467#L604-1 assume !(0 == ~T2_E~0); 325456#L609-1 assume !(0 == ~T3_E~0); 325457#L614-1 assume !(0 == ~T4_E~0); 325621#L619-1 assume !(0 == ~T5_E~0); 325732#L624-1 assume !(0 == ~E_M~0); 325832#L629-1 assume !(0 == ~E_1~0); 325548#L634-1 assume !(0 == ~E_2~0); 325549#L639-1 assume !(0 == ~E_3~0); 325968#L644-1 assume !(0 == ~E_4~0); 325988#L649-1 assume !(0 == ~E_5~0); 325510#L654-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 325511#L292 assume !(1 == ~m_pc~0); 325635#L292-2 is_master_triggered_~__retres1~0#1 := 0; 325767#L303 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 325728#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 325729#L743 assume !(0 != activate_threads_~tmp~1#1); 325580#L743-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 325581#L311 assume !(1 == ~t1_pc~0); 325967#L311-2 is_transmit1_triggered_~__retres1~1#1 := 0; 325840#L322 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 325502#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 325484#L751 assume !(0 != activate_threads_~tmp___0~0#1); 325485#L751-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 325970#L330 assume !(1 == ~t2_pc~0); 325735#L330-2 is_transmit2_triggered_~__retres1~2#1 := 0; 325636#L341 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 325637#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 325894#L759 assume !(0 != activate_threads_~tmp___1~0#1); 326092#L759-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 325622#L349 assume !(1 == ~t3_pc~0); 325623#L349-2 is_transmit3_triggered_~__retres1~3#1 := 0; 326134#L360 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 326165#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 326151#L767 assume !(0 != activate_threads_~tmp___2~0#1); 326079#L767-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 326080#L368 assume !(1 == ~t4_pc~0); 325698#L368-2 is_transmit4_triggered_~__retres1~4#1 := 0; 325699#L379 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 325607#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 325608#L775 assume !(0 != activate_threads_~tmp___3~0#1); 325470#L775-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 325471#L387 assume !(1 == ~t5_pc~0); 325852#L387-2 is_transmit5_triggered_~__retres1~5#1 := 0; 325853#L398 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 325737#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 325594#L783 assume !(0 != activate_threads_~tmp___4~0#1); 325595#L783-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 325687#L667 assume !(1 == ~M_E~0); 325758#L667-2 assume !(1 == ~T1_E~0); 325976#L672-1 assume !(1 == ~T2_E~0); 325718#L677-1 assume !(1 == ~T3_E~0); 325719#L682-1 assume !(1 == ~T4_E~0); 325947#L687-1 assume !(1 == ~T5_E~0); 326036#L692-1 assume !(1 == ~E_M~0); 325930#L697-1 assume !(1 == ~E_1~0); 325931#L702-1 assume !(1 == ~E_2~0); 325987#L707-1 assume !(1 == ~E_3~0); 325819#L712-1 assume !(1 == ~E_4~0); 325820#L717-1 assume !(1 == ~E_5~0); 325954#L722-1 assume { :end_inline_reset_delta_events } true; 325955#L928-2 assume !false; 364439#L929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 364434#L574 [2022-12-13 22:01:29,175 INFO L750 eck$LassoCheckResult]: Loop: 364434#L574 assume !false; 364432#L495 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 364429#L452 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 364427#L484 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 364425#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 364418#L499 assume 0 != eval_~tmp~0#1; 364414#L499-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 364407#L507 assume !(0 != eval_~tmp_ndt_1~0#1); 364403#L504 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 345019#L521 assume !(0 != eval_~tmp_ndt_2~0#1); 345020#L518 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 362193#L535 assume !(0 != eval_~tmp_ndt_3~0#1); 362190#L532 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 362173#L549 assume !(0 != eval_~tmp_ndt_4~0#1); 362186#L546 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0#1;eval_~tmp_ndt_5~0#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; 364448#L563 assume !(0 != eval_~tmp_ndt_5~0#1); 364443#L560 assume !(0 == ~t5_st~0); 364434#L574 [2022-12-13 22:01:29,176 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 22:01:29,176 INFO L85 PathProgramCache]: Analyzing trace with hash -322248313, now seen corresponding path program 5 times [2022-12-13 22:01:29,176 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 22:01:29,176 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1051916123] [2022-12-13 22:01:29,176 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 22:01:29,176 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 22:01:29,185 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 22:01:29,185 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 22:01:29,190 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 22:01:29,198 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 22:01:29,199 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 22:01:29,199 INFO L85 PathProgramCache]: Analyzing trace with hash -355882435, now seen corresponding path program 1 times [2022-12-13 22:01:29,199 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 22:01:29,199 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [754683052] [2022-12-13 22:01:29,199 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 22:01:29,199 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 22:01:29,202 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 22:01:29,202 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 22:01:29,204 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 22:01:29,205 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 22:01:29,205 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 22:01:29,206 INFO L85 PathProgramCache]: Analyzing trace with hash 123290999, now seen corresponding path program 1 times [2022-12-13 22:01:29,206 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 22:01:29,206 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [904201778] [2022-12-13 22:01:29,206 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 22:01:29,206 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 22:01:29,214 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 22:01:29,236 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 22:01:29,236 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 22:01:29,236 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [904201778] [2022-12-13 22:01:29,236 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [904201778] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 22:01:29,236 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 22:01:29,236 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-12-13 22:01:29,236 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [540870853] [2022-12-13 22:01:29,236 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 22:01:29,371 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 22:01:29,371 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 22:01:29,371 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 22:01:29,371 INFO L87 Difference]: Start difference. First operand 44007 states and 59787 transitions. cyclomatic complexity: 15786 Second operand has 3 states, 2 states have (on average 46.0) internal successors, (92), 3 states have internal predecessors, (92), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 22:01:29,600 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 22:01:29,600 INFO L93 Difference]: Finished difference Result 76657 states and 103983 transitions. [2022-12-13 22:01:29,600 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 76657 states and 103983 transitions. [2022-12-13 22:01:29,891 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 76296 [2022-12-13 22:01:30,143 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 76657 states to 76657 states and 103983 transitions. [2022-12-13 22:01:30,144 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 76657 [2022-12-13 22:01:30,166 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 76657 [2022-12-13 22:01:30,166 INFO L73 IsDeterministic]: Start isDeterministic. Operand 76657 states and 103983 transitions. [2022-12-13 22:01:30,188 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 22:01:30,188 INFO L218 hiAutomatonCegarLoop]: Abstraction has 76657 states and 103983 transitions. [2022-12-13 22:01:30,210 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 76657 states and 103983 transitions. [2022-12-13 22:01:30,564 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 76657 to 75921. [2022-12-13 22:01:30,615 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 75921 states, 75921 states have (on average 1.359926765980427) internal successors, (103247), 75920 states have internal predecessors, (103247), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 22:01:30,747 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 75921 states to 75921 states and 103247 transitions. [2022-12-13 22:01:30,748 INFO L240 hiAutomatonCegarLoop]: Abstraction has 75921 states and 103247 transitions. [2022-12-13 22:01:30,748 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 22:01:30,749 INFO L428 stractBuchiCegarLoop]: Abstraction has 75921 states and 103247 transitions. [2022-12-13 22:01:30,749 INFO L335 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2022-12-13 22:01:30,749 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 75921 states and 103247 transitions. [2022-12-13 22:01:30,964 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 75560 [2022-12-13 22:01:30,964 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 22:01:30,964 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 22:01:30,966 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 22:01:30,966 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 22:01:30,966 INFO L748 eck$LassoCheckResult]: Stem: 446428#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 446429#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 446572#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 446573#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 446788#L414 assume 1 == ~m_i~0;~m_st~0 := 0; 446506#L414-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 446507#L419-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 446747#L424-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 446478#L429-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 446479#L434-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 446741#L439-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 446474#L599 assume !(0 == ~M_E~0); 446475#L599-2 assume !(0 == ~T1_E~0); 446141#L604-1 assume !(0 == ~T2_E~0); 446128#L609-1 assume !(0 == ~T3_E~0); 446129#L614-1 assume !(0 == ~T4_E~0); 446290#L619-1 assume !(0 == ~T5_E~0); 446405#L624-1 assume !(0 == ~E_M~0); 446510#L629-1 assume !(0 == ~E_1~0); 446218#L634-1 assume !(0 == ~E_2~0); 446219#L639-1 assume !(0 == ~E_3~0); 446657#L644-1 assume !(0 == ~E_4~0); 446677#L649-1 assume !(0 == ~E_5~0); 446181#L654-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 446182#L292 assume !(1 == ~m_pc~0); 446304#L292-2 is_master_triggered_~__retres1~0#1 := 0; 446443#L303 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 446403#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 446404#L743 assume !(0 != activate_threads_~tmp~1#1); 446250#L743-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 446251#L311 assume !(1 == ~t1_pc~0); 446655#L311-2 is_transmit1_triggered_~__retres1~1#1 := 0; 446517#L322 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 446173#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 446155#L751 assume !(0 != activate_threads_~tmp___0~0#1); 446156#L751-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 446660#L330 assume !(1 == ~t2_pc~0); 446408#L330-2 is_transmit2_triggered_~__retres1~2#1 := 0; 446306#L341 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 446307#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 446577#L759 assume !(0 != activate_threads_~tmp___1~0#1); 446785#L759-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 446293#L349 assume !(1 == ~t3_pc~0); 446294#L349-2 is_transmit3_triggered_~__retres1~3#1 := 0; 446617#L360 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 446618#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 446846#L767 assume !(0 != activate_threads_~tmp___2~0#1); 446774#L767-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 446775#L368 assume !(1 == ~t4_pc~0); 446373#L368-2 is_transmit4_triggered_~__retres1~4#1 := 0; 446374#L379 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 446277#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 446278#L775 assume !(0 != activate_threads_~tmp___3~0#1); 446142#L775-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 446143#L387 assume !(1 == ~t5_pc~0); 446535#L387-2 is_transmit5_triggered_~__retres1~5#1 := 0; 446536#L398 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 446411#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 446267#L783 assume !(0 != activate_threads_~tmp___4~0#1); 446268#L783-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 446360#L667 assume !(1 == ~M_E~0); 446433#L667-2 assume !(1 == ~T1_E~0); 446668#L672-1 assume !(1 == ~T2_E~0); 446391#L677-1 assume !(1 == ~T3_E~0); 446392#L682-1 assume !(1 == ~T4_E~0); 446635#L687-1 assume !(1 == ~T5_E~0); 446734#L692-1 assume !(1 == ~E_M~0); 446615#L697-1 assume !(1 == ~E_1~0); 446616#L702-1 assume !(1 == ~E_2~0); 446676#L707-1 assume !(1 == ~E_3~0); 446496#L712-1 assume !(1 == ~E_4~0); 446497#L717-1 assume !(1 == ~E_5~0); 446642#L722-1 assume { :end_inline_reset_delta_events } true; 446643#L928-2 assume !false; 510826#L929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 510824#L574 [2022-12-13 22:01:30,966 INFO L750 eck$LassoCheckResult]: Loop: 510824#L574 assume !false; 510822#L495 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 510817#L452 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 510814#L484 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 510815#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 518719#L499 assume 0 != eval_~tmp~0#1; 518718#L499-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 446766#L507 assume !(0 != eval_~tmp_ndt_1~0#1); 446767#L504 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 465677#L521 assume !(0 != eval_~tmp_ndt_2~0#1); 465678#L518 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 508198#L535 assume !(0 != eval_~tmp_ndt_3~0#1); 508303#L532 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 507588#L549 assume !(0 != eval_~tmp_ndt_4~0#1); 510834#L546 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0#1;eval_~tmp_ndt_5~0#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; 510831#L563 assume !(0 != eval_~tmp_ndt_5~0#1); 510827#L560 assume 0 == ~t5_st~0;havoc eval_~tmp_ndt_6~0#1;eval_~tmp_ndt_6~0#1 := eval_#t~nondet11#1;havoc eval_#t~nondet11#1; 496921#L577 assume !(0 != eval_~tmp_ndt_6~0#1); 510824#L574 [2022-12-13 22:01:30,967 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 22:01:30,967 INFO L85 PathProgramCache]: Analyzing trace with hash -322248313, now seen corresponding path program 6 times [2022-12-13 22:01:30,967 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 22:01:30,967 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [868779713] [2022-12-13 22:01:30,967 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 22:01:30,968 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 22:01:30,979 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 22:01:30,979 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 22:01:30,986 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 22:01:31,001 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 22:01:31,002 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 22:01:31,002 INFO L85 PathProgramCache]: Analyzing trace with hash 1852542400, now seen corresponding path program 1 times [2022-12-13 22:01:31,002 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 22:01:31,002 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [500217603] [2022-12-13 22:01:31,002 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 22:01:31,002 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 22:01:31,006 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 22:01:31,007 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 22:01:31,009 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 22:01:31,011 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 22:01:31,012 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 22:01:31,012 INFO L85 PathProgramCache]: Analyzing trace with hash -472950330, now seen corresponding path program 1 times [2022-12-13 22:01:31,012 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 22:01:31,012 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1558887498] [2022-12-13 22:01:31,012 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 22:01:31,013 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 22:01:31,024 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 22:01:31,024 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 22:01:31,031 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 22:01:31,053 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 22:01:32,479 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 22:01:32,479 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 22:01:32,495 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 22:01:32,601 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 13.12 10:01:32 BoogieIcfgContainer [2022-12-13 22:01:32,601 INFO L132 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2022-12-13 22:01:32,602 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2022-12-13 22:01:32,602 INFO L271 PluginConnector]: Initializing Witness Printer... [2022-12-13 22:01:32,602 INFO L275 PluginConnector]: Witness Printer initialized [2022-12-13 22:01:32,602 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.12 10:01:21" (3/4) ... [2022-12-13 22:01:32,604 INFO L134 WitnessPrinter]: Generating witness for non-termination counterexample [2022-12-13 22:01:32,652 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_05afda94-e2e1-40bd-8d1f-ea253943d058/bin/uautomizer-uyxdKDjOR8/witness.graphml [2022-12-13 22:01:32,652 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2022-12-13 22:01:32,653 INFO L158 Benchmark]: Toolchain (without parser) took 12551.80ms. Allocated memory was 157.3MB in the beginning and 2.0GB in the end (delta: 1.9GB). Free memory was 128.2MB in the beginning and 1.2GB in the end (delta: -1.1GB). Peak memory consumption was 761.9MB. Max. memory is 16.1GB. [2022-12-13 22:01:32,653 INFO L158 Benchmark]: CDTParser took 0.13ms. Allocated memory is still 157.3MB. Free memory is still 128.0MB. There was no memory consumed. Max. memory is 16.1GB. [2022-12-13 22:01:32,653 INFO L158 Benchmark]: CACSL2BoogieTranslator took 289.58ms. Allocated memory is still 157.3MB. Free memory was 128.2MB in the beginning and 121.4MB in the end (delta: 6.7MB). Peak memory consumption was 6.3MB. Max. memory is 16.1GB. [2022-12-13 22:01:32,653 INFO L158 Benchmark]: Boogie Procedure Inliner took 59.76ms. Allocated memory is still 157.3MB. Free memory was 121.4MB in the beginning and 116.6MB in the end (delta: 4.8MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2022-12-13 22:01:32,653 INFO L158 Benchmark]: Boogie Preprocessor took 60.16ms. Allocated memory is still 157.3MB. Free memory was 116.6MB in the beginning and 111.8MB in the end (delta: 4.8MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2022-12-13 22:01:32,653 INFO L158 Benchmark]: RCFGBuilder took 866.06ms. Allocated memory is still 157.3MB. Free memory was 111.8MB in the beginning and 55.2MB in the end (delta: 56.6MB). Peak memory consumption was 56.6MB. Max. memory is 16.1GB. [2022-12-13 22:01:32,653 INFO L158 Benchmark]: BuchiAutomizer took 11221.68ms. Allocated memory was 157.3MB in the beginning and 2.0GB in the end (delta: 1.9GB). Free memory was 55.2MB in the beginning and 1.2GB in the end (delta: -1.2GB). Peak memory consumption was 679.6MB. Max. memory is 16.1GB. [2022-12-13 22:01:32,654 INFO L158 Benchmark]: Witness Printer took 50.51ms. Allocated memory is still 2.0GB. Free memory was 1.2GB in the beginning and 1.2GB in the end (delta: 11.6MB). Peak memory consumption was 12.6MB. Max. memory is 16.1GB. [2022-12-13 22:01:32,655 INFO L339 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.13ms. Allocated memory is still 157.3MB. Free memory is still 128.0MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 289.58ms. Allocated memory is still 157.3MB. Free memory was 128.2MB in the beginning and 121.4MB in the end (delta: 6.7MB). Peak memory consumption was 6.3MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 59.76ms. Allocated memory is still 157.3MB. Free memory was 121.4MB in the beginning and 116.6MB in the end (delta: 4.8MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * Boogie Preprocessor took 60.16ms. Allocated memory is still 157.3MB. Free memory was 116.6MB in the beginning and 111.8MB in the end (delta: 4.8MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * RCFGBuilder took 866.06ms. Allocated memory is still 157.3MB. Free memory was 111.8MB in the beginning and 55.2MB in the end (delta: 56.6MB). Peak memory consumption was 56.6MB. Max. memory is 16.1GB. * BuchiAutomizer took 11221.68ms. Allocated memory was 157.3MB in the beginning and 2.0GB in the end (delta: 1.9GB). Free memory was 55.2MB in the beginning and 1.2GB in the end (delta: -1.2GB). Peak memory consumption was 679.6MB. Max. memory is 16.1GB. * Witness Printer took 50.51ms. Allocated memory is still 2.0GB. Free memory was 1.2GB in the beginning and 1.2GB in the end (delta: 11.6MB). Peak memory consumption was 12.6MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 21 terminating modules (21 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.21 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 75921 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 11.1s and 22 iterations. TraceHistogramMax:1. Analysis of lassos took 3.9s. Construction of modules took 0.5s. Büchi inclusion checks took 5.8s. Highest rank in rank-based complementation 0. Minimization of det autom 21. Minimization of nondet autom 0. Automata minimization 2.5s AutomataMinimizationTime, 21 MinimizatonAttempts, 21684 StatesRemovedByMinimization, 13 NontrivialMinimizations. Non-live state removal took 1.7s Buchi closure took 0.1s. Biggest automaton had -1 states and ocurred in iteration -1. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 21647 SdHoareTripleChecker+Valid, 0.7s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 21647 mSDsluCounter, 35047 SdHoareTripleChecker+Invalid, 0.6s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 17054 mSDsCounter, 305 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 624 IncrementalHoareTripleChecker+Invalid, 929 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 305 mSolverCounterUnsat, 17993 mSDtfsCounter, 624 mSolverCounterSat, 0.1s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI3 SFLT0 conc5 concLT0 SILN1 SILU0 SILI12 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s InitialAbstractionConstructionTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - LassoShapedNonTerminationArgument [Line: 494]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite program execution. Stem: [L24] int m_pc = 0; [L25] int t1_pc = 0; [L26] int t2_pc = 0; [L27] int t3_pc = 0; [L28] int t4_pc = 0; [L29] int t5_pc = 0; [L30] int m_st ; [L31] int t1_st ; [L32] int t2_st ; [L33] int t3_st ; [L34] int t4_st ; [L35] int t5_st ; [L36] int m_i ; [L37] int t1_i ; [L38] int t2_i ; [L39] int t3_i ; [L40] int t4_i ; [L41] int t5_i ; [L42] int M_E = 2; [L43] int T1_E = 2; [L44] int T2_E = 2; [L45] int T3_E = 2; [L46] int T4_E = 2; [L47] int T5_E = 2; [L48] int E_M = 2; [L49] int E_1 = 2; [L50] int E_2 = 2; [L51] int E_3 = 2; [L52] int E_4 = 2; [L53] int E_5 = 2; [L61] int token ; [L63] int local ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=0, m_pc=0, m_st=0, T1_E=2, t1_i=0, t1_pc=0, t1_st=0, T2_E=2, t2_i=0, t2_pc=0, t2_st=0, T3_E=2, t3_i=0, t3_pc=0, t3_st=0, T4_E=2, t4_i=0, t4_pc=0, t4_st=0, T5_E=2, t5_i=0, t5_pc=0, t5_st=0, token=0] [L973] int __retres1 ; [L977] CALL init_model() [L884] m_i = 1 [L885] t1_i = 1 [L886] t2_i = 1 [L887] t3_i = 1 [L888] t4_i = 1 [L889] t5_i = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L977] RET init_model() [L978] CALL start_simulation() [L914] int kernel_st ; [L915] int tmp ; [L916] int tmp___0 ; [L920] kernel_st = 0 [L921] FCALL update_channels() [L922] CALL init_threads() [L414] COND TRUE m_i == 1 [L415] m_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L419] COND TRUE t1_i == 1 [L420] t1_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L424] COND TRUE t2_i == 1 [L425] t2_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L429] COND TRUE t3_i == 1 [L430] t3_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L434] COND TRUE t4_i == 1 [L435] t4_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L439] COND TRUE t5_i == 1 [L440] t5_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L922] RET init_threads() [L923] CALL fire_delta_events() [L599] COND FALSE !(M_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L604] COND FALSE !(T1_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L609] COND FALSE !(T2_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L614] COND FALSE !(T3_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L619] COND FALSE !(T4_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L624] COND FALSE !(T5_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L629] COND FALSE !(E_M == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L634] COND FALSE !(E_1 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L639] COND FALSE !(E_2 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L644] COND FALSE !(E_3 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L649] COND FALSE !(E_4 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L654] COND FALSE !(E_5 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L923] RET fire_delta_events() [L924] CALL activate_threads() [L732] int tmp ; [L733] int tmp___0 ; [L734] int tmp___1 ; [L735] int tmp___2 ; [L736] int tmp___3 ; [L737] int tmp___4 ; [L741] CALL, EXPR is_master_triggered() [L289] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L292] COND FALSE !(m_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L302] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L304] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L741] RET, EXPR is_master_triggered() [L741] tmp = is_master_triggered() [L743] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, tmp=0, token=0] [L749] CALL, EXPR is_transmit1_triggered() [L308] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L311] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L321] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L323] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L749] RET, EXPR is_transmit1_triggered() [L749] tmp___0 = is_transmit1_triggered() [L751] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, tmp=0, tmp___0=0, token=0] [L757] CALL, EXPR is_transmit2_triggered() [L327] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L330] COND FALSE !(t2_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L340] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L342] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L757] RET, EXPR is_transmit2_triggered() [L757] tmp___1 = is_transmit2_triggered() [L759] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, tmp=0, tmp___0=0, tmp___1=0, token=0] [L765] CALL, EXPR is_transmit3_triggered() [L346] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L349] COND FALSE !(t3_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L359] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L361] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L765] RET, EXPR is_transmit3_triggered() [L765] tmp___2 = is_transmit3_triggered() [L767] COND FALSE !(\read(tmp___2)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, token=0] [L773] CALL, EXPR is_transmit4_triggered() [L365] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L368] COND FALSE !(t4_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L378] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L380] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L773] RET, EXPR is_transmit4_triggered() [L773] tmp___3 = is_transmit4_triggered() [L775] COND FALSE !(\read(tmp___3)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0, token=0] [L781] CALL, EXPR is_transmit5_triggered() [L384] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L387] COND FALSE !(t5_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L397] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L399] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L781] RET, EXPR is_transmit5_triggered() [L781] tmp___4 = is_transmit5_triggered() [L783] COND FALSE !(\read(tmp___4)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0, tmp___4=0, token=0] [L924] RET activate_threads() [L925] CALL reset_delta_events() [L667] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L672] COND FALSE !(T1_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L677] COND FALSE !(T2_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L682] COND FALSE !(T3_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L687] COND FALSE !(T4_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L692] COND FALSE !(T5_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L697] COND FALSE !(E_M == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L702] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L707] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L712] COND FALSE !(E_3 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L717] COND FALSE !(E_4 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L722] COND FALSE !(E_5 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L925] RET reset_delta_events() [L928] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, kernel_st=0, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L931] kernel_st = 1 [L932] CALL eval() [L490] int tmp ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] Loop: [L494] COND TRUE 1 [L497] CALL, EXPR exists_runnable_thread() [L449] int __retres1 ; [L452] COND TRUE m_st == 0 [L453] __retres1 = 1 [L485] return (__retres1); [L497] RET, EXPR exists_runnable_thread() [L497] tmp = exists_runnable_thread() [L499] COND TRUE \read(tmp) [L504] COND TRUE m_st == 0 [L505] int tmp_ndt_1; [L506] tmp_ndt_1 = __VERIFIER_nondet_int() [L507] COND FALSE !(\read(tmp_ndt_1)) [L518] COND TRUE t1_st == 0 [L519] int tmp_ndt_2; [L520] tmp_ndt_2 = __VERIFIER_nondet_int() [L521] COND FALSE !(\read(tmp_ndt_2)) [L532] COND TRUE t2_st == 0 [L533] int tmp_ndt_3; [L534] tmp_ndt_3 = __VERIFIER_nondet_int() [L535] COND FALSE !(\read(tmp_ndt_3)) [L546] COND TRUE t3_st == 0 [L547] int tmp_ndt_4; [L548] tmp_ndt_4 = __VERIFIER_nondet_int() [L549] COND FALSE !(\read(tmp_ndt_4)) [L560] COND TRUE t4_st == 0 [L561] int tmp_ndt_5; [L562] tmp_ndt_5 = __VERIFIER_nondet_int() [L563] COND FALSE !(\read(tmp_ndt_5)) [L574] COND TRUE t5_st == 0 [L575] int tmp_ndt_6; [L576] tmp_ndt_6 = __VERIFIER_nondet_int() [L577] COND FALSE !(\read(tmp_ndt_6)) End of lasso representation. - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 494]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L24] int m_pc = 0; [L25] int t1_pc = 0; [L26] int t2_pc = 0; [L27] int t3_pc = 0; [L28] int t4_pc = 0; [L29] int t5_pc = 0; [L30] int m_st ; [L31] int t1_st ; [L32] int t2_st ; [L33] int t3_st ; [L34] int t4_st ; [L35] int t5_st ; [L36] int m_i ; [L37] int t1_i ; [L38] int t2_i ; [L39] int t3_i ; [L40] int t4_i ; [L41] int t5_i ; [L42] int M_E = 2; [L43] int T1_E = 2; [L44] int T2_E = 2; [L45] int T3_E = 2; [L46] int T4_E = 2; [L47] int T5_E = 2; [L48] int E_M = 2; [L49] int E_1 = 2; [L50] int E_2 = 2; [L51] int E_3 = 2; [L52] int E_4 = 2; [L53] int E_5 = 2; [L61] int token ; [L63] int local ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=0, m_pc=0, m_st=0, T1_E=2, t1_i=0, t1_pc=0, t1_st=0, T2_E=2, t2_i=0, t2_pc=0, t2_st=0, T3_E=2, t3_i=0, t3_pc=0, t3_st=0, T4_E=2, t4_i=0, t4_pc=0, t4_st=0, T5_E=2, t5_i=0, t5_pc=0, t5_st=0, token=0] [L973] int __retres1 ; [L977] CALL init_model() [L884] m_i = 1 [L885] t1_i = 1 [L886] t2_i = 1 [L887] t3_i = 1 [L888] t4_i = 1 [L889] t5_i = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L977] RET init_model() [L978] CALL start_simulation() [L914] int kernel_st ; [L915] int tmp ; [L916] int tmp___0 ; [L920] kernel_st = 0 [L921] FCALL update_channels() [L922] CALL init_threads() [L414] COND TRUE m_i == 1 [L415] m_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L419] COND TRUE t1_i == 1 [L420] t1_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L424] COND TRUE t2_i == 1 [L425] t2_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L429] COND TRUE t3_i == 1 [L430] t3_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L434] COND TRUE t4_i == 1 [L435] t4_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L439] COND TRUE t5_i == 1 [L440] t5_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L922] RET init_threads() [L923] CALL fire_delta_events() [L599] COND FALSE !(M_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L604] COND FALSE !(T1_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L609] COND FALSE !(T2_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L614] COND FALSE !(T3_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L619] COND FALSE !(T4_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L624] COND FALSE !(T5_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L629] COND FALSE !(E_M == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L634] COND FALSE !(E_1 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L639] COND FALSE !(E_2 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L644] COND FALSE !(E_3 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L649] COND FALSE !(E_4 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L654] COND FALSE !(E_5 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L923] RET fire_delta_events() [L924] CALL activate_threads() [L732] int tmp ; [L733] int tmp___0 ; [L734] int tmp___1 ; [L735] int tmp___2 ; [L736] int tmp___3 ; [L737] int tmp___4 ; [L741] CALL, EXPR is_master_triggered() [L289] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L292] COND FALSE !(m_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L302] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L304] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L741] RET, EXPR is_master_triggered() [L741] tmp = is_master_triggered() [L743] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, tmp=0, token=0] [L749] CALL, EXPR is_transmit1_triggered() [L308] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L311] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L321] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L323] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L749] RET, EXPR is_transmit1_triggered() [L749] tmp___0 = is_transmit1_triggered() [L751] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, tmp=0, tmp___0=0, token=0] [L757] CALL, EXPR is_transmit2_triggered() [L327] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L330] COND FALSE !(t2_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L340] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L342] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L757] RET, EXPR is_transmit2_triggered() [L757] tmp___1 = is_transmit2_triggered() [L759] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, tmp=0, tmp___0=0, tmp___1=0, token=0] [L765] CALL, EXPR is_transmit3_triggered() [L346] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L349] COND FALSE !(t3_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L359] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L361] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L765] RET, EXPR is_transmit3_triggered() [L765] tmp___2 = is_transmit3_triggered() [L767] COND FALSE !(\read(tmp___2)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, token=0] [L773] CALL, EXPR is_transmit4_triggered() [L365] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L368] COND FALSE !(t4_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L378] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L380] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L773] RET, EXPR is_transmit4_triggered() [L773] tmp___3 = is_transmit4_triggered() [L775] COND FALSE !(\read(tmp___3)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0, token=0] [L781] CALL, EXPR is_transmit5_triggered() [L384] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L387] COND FALSE !(t5_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L397] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L399] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L781] RET, EXPR is_transmit5_triggered() [L781] tmp___4 = is_transmit5_triggered() [L783] COND FALSE !(\read(tmp___4)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0, tmp___4=0, token=0] [L924] RET activate_threads() [L925] CALL reset_delta_events() [L667] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L672] COND FALSE !(T1_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L677] COND FALSE !(T2_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L682] COND FALSE !(T3_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L687] COND FALSE !(T4_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L692] COND FALSE !(T5_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L697] COND FALSE !(E_M == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L702] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L707] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L712] COND FALSE !(E_3 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L717] COND FALSE !(E_4 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L722] COND FALSE !(E_5 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L925] RET reset_delta_events() [L928] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, kernel_st=0, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L931] kernel_st = 1 [L932] CALL eval() [L490] int tmp ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] Loop: [L494] COND TRUE 1 [L497] CALL, EXPR exists_runnable_thread() [L449] int __retres1 ; [L452] COND TRUE m_st == 0 [L453] __retres1 = 1 [L485] return (__retres1); [L497] RET, EXPR exists_runnable_thread() [L497] tmp = exists_runnable_thread() [L499] COND TRUE \read(tmp) [L504] COND TRUE m_st == 0 [L505] int tmp_ndt_1; [L506] tmp_ndt_1 = __VERIFIER_nondet_int() [L507] COND FALSE !(\read(tmp_ndt_1)) [L518] COND TRUE t1_st == 0 [L519] int tmp_ndt_2; [L520] tmp_ndt_2 = __VERIFIER_nondet_int() [L521] COND FALSE !(\read(tmp_ndt_2)) [L532] COND TRUE t2_st == 0 [L533] int tmp_ndt_3; [L534] tmp_ndt_3 = __VERIFIER_nondet_int() [L535] COND FALSE !(\read(tmp_ndt_3)) [L546] COND TRUE t3_st == 0 [L547] int tmp_ndt_4; [L548] tmp_ndt_4 = __VERIFIER_nondet_int() [L549] COND FALSE !(\read(tmp_ndt_4)) [L560] COND TRUE t4_st == 0 [L561] int tmp_ndt_5; [L562] tmp_ndt_5 = __VERIFIER_nondet_int() [L563] COND FALSE !(\read(tmp_ndt_5)) [L574] COND TRUE t5_st == 0 [L575] int tmp_ndt_6; [L576] tmp_ndt_6 = __VERIFIER_nondet_int() [L577] COND FALSE !(\read(tmp_ndt_6)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2022-12-13 22:01:32,721 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_05afda94-e2e1-40bd-8d1f-ea253943d058/bin/uautomizer-uyxdKDjOR8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Forceful destruction successful, exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)