./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/token_ring.06.cil-1.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 2329fc70 Calling Ultimate with: /usr/lib/jvm/java-1.11.0-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2c88f091-7631-406f-9e15-c98ec6d1bb95/bin/uautomizer-uyxdKDjOR8/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2c88f091-7631-406f-9e15-c98ec6d1bb95/bin/uautomizer-uyxdKDjOR8/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2c88f091-7631-406f-9e15-c98ec6d1bb95/bin/uautomizer-uyxdKDjOR8/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2c88f091-7631-406f-9e15-c98ec6d1bb95/bin/uautomizer-uyxdKDjOR8/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/token_ring.06.cil-1.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2c88f091-7631-406f-9e15-c98ec6d1bb95/bin/uautomizer-uyxdKDjOR8/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2c88f091-7631-406f-9e15-c98ec6d1bb95/bin/uautomizer-uyxdKDjOR8 --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 4ff0d99c6257365cafb7459615c8e1194d53bcc0d71dc100705abd4bb2d65c37 --- Real Ultimate output --- [0.001s][warning][os,container] Duplicate cpuset controllers detected. Picking /sys/fs/cgroup/cpuset, skipping /sys/fs/cgroup/cpuset. This is Ultimate 0.2.2-dev-2329fc7 [2022-12-13 19:41:28,108 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-12-13 19:41:28,110 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-12-13 19:41:28,129 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-12-13 19:41:28,130 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-12-13 19:41:28,131 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-12-13 19:41:28,132 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-12-13 19:41:28,133 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-12-13 19:41:28,135 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-12-13 19:41:28,136 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-12-13 19:41:28,137 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-12-13 19:41:28,138 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-12-13 19:41:28,138 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-12-13 19:41:28,139 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-12-13 19:41:28,140 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-12-13 19:41:28,141 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-12-13 19:41:28,142 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-12-13 19:41:28,143 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-12-13 19:41:28,145 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-12-13 19:41:28,147 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-12-13 19:41:28,148 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-12-13 19:41:28,150 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-12-13 19:41:28,151 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-12-13 19:41:28,152 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-12-13 19:41:28,155 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-12-13 19:41:28,155 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-12-13 19:41:28,156 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-12-13 19:41:28,157 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-12-13 19:41:28,157 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-12-13 19:41:28,158 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-12-13 19:41:28,158 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-12-13 19:41:28,159 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-12-13 19:41:28,160 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-12-13 19:41:28,160 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-12-13 19:41:28,161 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-12-13 19:41:28,162 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-12-13 19:41:28,162 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-12-13 19:41:28,162 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-12-13 19:41:28,163 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-12-13 19:41:28,163 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-12-13 19:41:28,164 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-12-13 19:41:28,165 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2c88f091-7631-406f-9e15-c98ec6d1bb95/bin/uautomizer-uyxdKDjOR8/config/svcomp-Termination-32bit-Automizer_Default.epf [2022-12-13 19:41:28,188 INFO L113 SettingsManager]: Loading preferences was successful [2022-12-13 19:41:28,188 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-12-13 19:41:28,189 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-12-13 19:41:28,189 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-12-13 19:41:28,190 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-12-13 19:41:28,190 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-12-13 19:41:28,190 INFO L138 SettingsManager]: * Use SBE=true [2022-12-13 19:41:28,190 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2022-12-13 19:41:28,191 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2022-12-13 19:41:28,191 INFO L138 SettingsManager]: * Use old map elimination=false [2022-12-13 19:41:28,191 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2022-12-13 19:41:28,191 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2022-12-13 19:41:28,191 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2022-12-13 19:41:28,191 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-12-13 19:41:28,192 INFO L138 SettingsManager]: * sizeof long=4 [2022-12-13 19:41:28,192 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2022-12-13 19:41:28,192 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-12-13 19:41:28,192 INFO L138 SettingsManager]: * sizeof POINTER=4 [2022-12-13 19:41:28,192 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-12-13 19:41:28,193 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2022-12-13 19:41:28,193 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2022-12-13 19:41:28,193 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2022-12-13 19:41:28,193 INFO L138 SettingsManager]: * sizeof long double=12 [2022-12-13 19:41:28,193 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-12-13 19:41:28,193 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2022-12-13 19:41:28,194 INFO L138 SettingsManager]: * Use constant arrays=true [2022-12-13 19:41:28,194 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2022-12-13 19:41:28,194 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-12-13 19:41:28,194 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-12-13 19:41:28,195 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-12-13 19:41:28,195 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-12-13 19:41:28,196 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-12-13 19:41:28,196 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2c88f091-7631-406f-9e15-c98ec6d1bb95/bin/uautomizer-uyxdKDjOR8/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2c88f091-7631-406f-9e15-c98ec6d1bb95/bin/uautomizer-uyxdKDjOR8 Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 4ff0d99c6257365cafb7459615c8e1194d53bcc0d71dc100705abd4bb2d65c37 [2022-12-13 19:41:28,377 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-12-13 19:41:28,391 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-12-13 19:41:28,393 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-12-13 19:41:28,394 INFO L271 PluginConnector]: Initializing CDTParser... [2022-12-13 19:41:28,395 INFO L275 PluginConnector]: CDTParser initialized [2022-12-13 19:41:28,395 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2c88f091-7631-406f-9e15-c98ec6d1bb95/bin/uautomizer-uyxdKDjOR8/../../sv-benchmarks/c/systemc/token_ring.06.cil-1.c [2022-12-13 19:41:31,040 INFO L500 CDTParser]: Created temporary CDT project at NULL [2022-12-13 19:41:31,206 INFO L351 CDTParser]: Found 1 translation units. [2022-12-13 19:41:31,207 INFO L172 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2c88f091-7631-406f-9e15-c98ec6d1bb95/sv-benchmarks/c/systemc/token_ring.06.cil-1.c [2022-12-13 19:41:31,214 INFO L394 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2c88f091-7631-406f-9e15-c98ec6d1bb95/bin/uautomizer-uyxdKDjOR8/data/e0cf1380d/ceea7fd7ab774808a9ed153850f89601/FLAGbe01ae4f0 [2022-12-13 19:41:31,225 INFO L402 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2c88f091-7631-406f-9e15-c98ec6d1bb95/bin/uautomizer-uyxdKDjOR8/data/e0cf1380d/ceea7fd7ab774808a9ed153850f89601 [2022-12-13 19:41:31,227 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-12-13 19:41:31,228 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-12-13 19:41:31,229 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-12-13 19:41:31,229 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-12-13 19:41:31,232 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-12-13 19:41:31,233 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.12 07:41:31" (1/1) ... [2022-12-13 19:41:31,234 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@427d2f0a and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 07:41:31, skipping insertion in model container [2022-12-13 19:41:31,234 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.12 07:41:31" (1/1) ... [2022-12-13 19:41:31,241 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-12-13 19:41:31,270 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-12-13 19:41:31,376 WARN L237 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2c88f091-7631-406f-9e15-c98ec6d1bb95/sv-benchmarks/c/systemc/token_ring.06.cil-1.c[671,684] [2022-12-13 19:41:31,430 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-12-13 19:41:31,440 INFO L203 MainTranslator]: Completed pre-run [2022-12-13 19:41:31,449 WARN L237 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2c88f091-7631-406f-9e15-c98ec6d1bb95/sv-benchmarks/c/systemc/token_ring.06.cil-1.c[671,684] [2022-12-13 19:41:31,480 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-12-13 19:41:31,493 INFO L208 MainTranslator]: Completed translation [2022-12-13 19:41:31,494 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 07:41:31 WrapperNode [2022-12-13 19:41:31,494 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-12-13 19:41:31,495 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-12-13 19:41:31,495 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-12-13 19:41:31,495 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-12-13 19:41:31,501 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 07:41:31" (1/1) ... [2022-12-13 19:41:31,508 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 07:41:31" (1/1) ... [2022-12-13 19:41:31,559 INFO L138 Inliner]: procedures = 40, calls = 50, calls flagged for inlining = 45, calls inlined = 114, statements flattened = 1662 [2022-12-13 19:41:31,560 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-12-13 19:41:31,560 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-12-13 19:41:31,560 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-12-13 19:41:31,560 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-12-13 19:41:31,568 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 07:41:31" (1/1) ... [2022-12-13 19:41:31,568 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 07:41:31" (1/1) ... [2022-12-13 19:41:31,572 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 07:41:31" (1/1) ... [2022-12-13 19:41:31,572 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 07:41:31" (1/1) ... [2022-12-13 19:41:31,585 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 07:41:31" (1/1) ... [2022-12-13 19:41:31,595 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 07:41:31" (1/1) ... [2022-12-13 19:41:31,597 INFO L185 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 07:41:31" (1/1) ... [2022-12-13 19:41:31,600 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 07:41:31" (1/1) ... [2022-12-13 19:41:31,605 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-12-13 19:41:31,605 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-12-13 19:41:31,605 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-12-13 19:41:31,606 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-12-13 19:41:31,606 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 07:41:31" (1/1) ... [2022-12-13 19:41:31,611 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-12-13 19:41:31,620 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2c88f091-7631-406f-9e15-c98ec6d1bb95/bin/uautomizer-uyxdKDjOR8/z3 [2022-12-13 19:41:31,631 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2c88f091-7631-406f-9e15-c98ec6d1bb95/bin/uautomizer-uyxdKDjOR8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-12-13 19:41:31,633 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2c88f091-7631-406f-9e15-c98ec6d1bb95/bin/uautomizer-uyxdKDjOR8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2022-12-13 19:41:31,669 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-12-13 19:41:31,670 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-12-13 19:41:31,670 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-12-13 19:41:31,670 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-12-13 19:41:31,749 INFO L235 CfgBuilder]: Building ICFG [2022-12-13 19:41:31,751 INFO L261 CfgBuilder]: Building CFG for each procedure with an implementation [2022-12-13 19:41:32,546 INFO L276 CfgBuilder]: Performing block encoding [2022-12-13 19:41:32,556 INFO L295 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-12-13 19:41:32,556 INFO L300 CfgBuilder]: Removed 9 assume(true) statements. [2022-12-13 19:41:32,558 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.12 07:41:32 BoogieIcfgContainer [2022-12-13 19:41:32,558 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-12-13 19:41:32,559 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2022-12-13 19:41:32,559 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2022-12-13 19:41:32,562 INFO L275 PluginConnector]: BuchiAutomizer initialized [2022-12-13 19:41:32,562 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-12-13 19:41:32,562 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 13.12 07:41:31" (1/3) ... [2022-12-13 19:41:32,563 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@26cddb86 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 13.12 07:41:32, skipping insertion in model container [2022-12-13 19:41:32,563 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-12-13 19:41:32,563 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 07:41:31" (2/3) ... [2022-12-13 19:41:32,564 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@26cddb86 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 13.12 07:41:32, skipping insertion in model container [2022-12-13 19:41:32,564 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-12-13 19:41:32,564 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.12 07:41:32" (3/3) ... [2022-12-13 19:41:32,565 INFO L332 chiAutomizerObserver]: Analyzing ICFG token_ring.06.cil-1.c [2022-12-13 19:41:32,613 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2022-12-13 19:41:32,613 INFO L304 stractBuchiCegarLoop]: Hoare is false [2022-12-13 19:41:32,613 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2022-12-13 19:41:32,613 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2022-12-13 19:41:32,613 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2022-12-13 19:41:32,613 INFO L308 stractBuchiCegarLoop]: Difference is false [2022-12-13 19:41:32,613 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2022-12-13 19:41:32,614 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2022-12-13 19:41:32,619 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 694 states, 693 states have (on average 1.5252525252525253) internal successors, (1057), 693 states have internal predecessors, (1057), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:41:32,647 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 599 [2022-12-13 19:41:32,647 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 19:41:32,647 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 19:41:32,654 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:41:32,654 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:41:32,655 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2022-12-13 19:41:32,656 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 694 states, 693 states have (on average 1.5252525252525253) internal successors, (1057), 693 states have internal predecessors, (1057), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:41:32,667 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 599 [2022-12-13 19:41:32,668 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 19:41:32,668 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 19:41:32,670 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:41:32,670 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:41:32,677 INFO L748 eck$LassoCheckResult]: Stem: 200#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 563#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 332#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 558#update_channels_returnLabel#1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 519#L487true assume !(1 == ~m_i~0);~m_st~0 := 2; 129#L487-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 268#L492-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 41#L497-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 149#L502-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 29#L507-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 116#L512-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 536#L517-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 222#L696true assume !(0 == ~M_E~0); 530#L696-2true assume !(0 == ~T1_E~0); 533#L701-1true assume !(0 == ~T2_E~0); 561#L706-1true assume !(0 == ~T3_E~0); 304#L711-1true assume !(0 == ~T4_E~0); 151#L716-1true assume !(0 == ~T5_E~0); 580#L721-1true assume !(0 == ~T6_E~0); 273#L726-1true assume 0 == ~E_M~0;~E_M~0 := 1; 471#L731-1true assume !(0 == ~E_1~0); 247#L736-1true assume !(0 == ~E_2~0); 316#L741-1true assume !(0 == ~E_3~0); 618#L746-1true assume !(0 == ~E_4~0); 170#L751-1true assume !(0 == ~E_5~0); 232#L756-1true assume !(0 == ~E_6~0); 148#L761-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 52#L346true assume !(1 == ~m_pc~0); 180#L346-2true is_master_triggered_~__retres1~0#1 := 0; 416#L357true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 175#is_master_triggered_returnLabel#1true activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 548#L861true assume !(0 != activate_threads_~tmp~1#1); 470#L861-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 70#L365true assume 1 == ~t1_pc~0; 138#L366true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 514#L376true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 44#is_transmit1_triggered_returnLabel#1true activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 65#L869true assume !(0 != activate_threads_~tmp___0~0#1); 370#L869-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 498#L384true assume !(1 == ~t2_pc~0); 366#L384-2true is_transmit2_triggered_~__retres1~2#1 := 0; 620#L395true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 334#is_transmit2_triggered_returnLabel#1true activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 24#L877true assume !(0 != activate_threads_~tmp___1~0#1); 236#L877-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 233#L403true assume 1 == ~t3_pc~0; 152#L404true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 672#L414true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10#is_transmit3_triggered_returnLabel#1true activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 412#L885true assume !(0 != activate_threads_~tmp___2~0#1); 226#L885-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 520#L422true assume 1 == ~t4_pc~0; 22#L423true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 434#L433true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 97#is_transmit4_triggered_returnLabel#1true activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 447#L893true assume !(0 != activate_threads_~tmp___3~0#1); 291#L893-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 30#L441true assume !(1 == ~t5_pc~0); 464#L441-2true is_transmit5_triggered_~__retres1~5#1 := 0; 609#L452true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 182#is_transmit5_triggered_returnLabel#1true activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 689#L901true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 297#L901-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 420#L460true assume 1 == ~t6_pc~0; 4#L461true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 33#L471true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 318#is_transmit6_triggered_returnLabel#1true activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 417#L909true assume !(0 != activate_threads_~tmp___5~0#1); 545#L909-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 280#L774true assume !(1 == ~M_E~0); 585#L774-2true assume !(1 == ~T1_E~0); 438#L779-1true assume !(1 == ~T2_E~0); 211#L784-1true assume 1 == ~T3_E~0;~T3_E~0 := 2; 581#L789-1true assume !(1 == ~T4_E~0); 61#L794-1true assume !(1 == ~T5_E~0); 659#L799-1true assume !(1 == ~T6_E~0); 596#L804-1true assume !(1 == ~E_M~0); 651#L809-1true assume !(1 == ~E_1~0); 270#L814-1true assume !(1 == ~E_2~0); 12#L819-1true assume !(1 == ~E_3~0); 324#L824-1true assume 1 == ~E_4~0;~E_4~0 := 2; 641#L829-1true assume !(1 == ~E_5~0); 425#L834-1true assume !(1 == ~E_6~0); 139#L839-1true assume { :end_inline_reset_delta_events } true; 131#L1065-2true [2022-12-13 19:41:32,679 INFO L750 eck$LassoCheckResult]: Loop: 131#L1065-2true assume !false; 340#L1066true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 485#L671true assume false; 106#eval_returnLabel#1true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 484#update_channels_returnLabel#2true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 163#L696-3true assume 0 == ~M_E~0;~M_E~0 := 1; 575#L696-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 199#L701-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 665#L706-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 544#L711-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 531#L716-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 320#L721-3true assume !(0 == ~T6_E~0); 185#L726-3true assume 0 == ~E_M~0;~E_M~0 := 1; 308#L731-3true assume 0 == ~E_1~0;~E_1~0 := 1; 507#L736-3true assume 0 == ~E_2~0;~E_2~0 := 1; 309#L741-3true assume 0 == ~E_3~0;~E_3~0 := 1; 145#L746-3true assume 0 == ~E_4~0;~E_4~0 := 1; 228#L751-3true assume 0 == ~E_5~0;~E_5~0 := 1; 426#L756-3true assume 0 == ~E_6~0;~E_6~0 := 1; 74#L761-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 92#L346-24true assume 1 == ~m_pc~0; 409#L347-8true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 310#L357-8true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 115#is_master_triggered_returnLabel#9true activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 496#L861-24true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 435#L861-26true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 112#L365-24true assume !(1 == ~t1_pc~0); 686#L365-26true is_transmit1_triggered_~__retres1~1#1 := 0; 647#L376-8true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 523#is_transmit1_triggered_returnLabel#9true activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 390#L869-24true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 579#L869-26true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 84#L384-24true assume 1 == ~t2_pc~0; 693#L385-8true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 632#L395-8true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 667#is_transmit2_triggered_returnLabel#9true activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 300#L877-24true assume !(0 != activate_threads_~tmp___1~0#1); 100#L877-26true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 172#L403-24true assume !(1 == ~t3_pc~0); 590#L403-26true is_transmit3_triggered_~__retres1~3#1 := 0; 201#L414-8true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 369#is_transmit3_triggered_returnLabel#9true activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 266#L885-24true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 571#L885-26true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 130#L422-24true assume 1 == ~t4_pc~0; 568#L423-8true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 105#L433-8true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 476#is_transmit4_triggered_returnLabel#9true activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 535#L893-24true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 444#L893-26true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 140#L441-24true assume !(1 == ~t5_pc~0); 292#L441-26true is_transmit5_triggered_~__retres1~5#1 := 0; 286#L452-8true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 243#is_transmit5_triggered_returnLabel#9true activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 66#L901-24true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 377#L901-26true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 373#L460-24true assume 1 == ~t6_pc~0; 583#L461-8true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 678#L471-8true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 169#is_transmit6_triggered_returnLabel#9true activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 463#L909-24true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 367#L909-26true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 628#L774-3true assume 1 == ~M_E~0;~M_E~0 := 2; 298#L774-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 184#L779-3true assume !(1 == ~T2_E~0); 23#L784-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 677#L789-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 13#L794-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 71#L799-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 284#L804-3true assume 1 == ~E_M~0;~E_M~0 := 2; 517#L809-3true assume 1 == ~E_1~0;~E_1~0 := 2; 69#L814-3true assume 1 == ~E_2~0;~E_2~0 := 2; 221#L819-3true assume !(1 == ~E_3~0); 156#L824-3true assume 1 == ~E_4~0;~E_4~0 := 2; 144#L829-3true assume 1 == ~E_5~0;~E_5~0 := 2; 345#L834-3true assume 1 == ~E_6~0;~E_6~0 := 2; 60#L839-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 448#L530-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 110#L567-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 290#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 28#L1084true assume !(0 == start_simulation_~tmp~3#1); 487#L1084-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 168#L530-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 81#L567-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 43#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 171#L1039true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 77#L1046true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 497#stop_simulation_returnLabel#1true start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 176#L1097true assume !(0 != start_simulation_~tmp___0~1#1); 131#L1065-2true [2022-12-13 19:41:32,683 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:41:32,683 INFO L85 PathProgramCache]: Analyzing trace with hash -376834623, now seen corresponding path program 1 times [2022-12-13 19:41:32,689 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:41:32,689 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [268516059] [2022-12-13 19:41:32,690 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:41:32,690 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:41:32,781 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:41:32,899 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:41:32,900 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:41:32,900 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [268516059] [2022-12-13 19:41:32,901 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [268516059] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:41:32,901 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:41:32,901 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:41:32,903 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [346235686] [2022-12-13 19:41:32,903 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:41:32,907 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 19:41:32,908 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:41:32,908 INFO L85 PathProgramCache]: Analyzing trace with hash 13399679, now seen corresponding path program 1 times [2022-12-13 19:41:32,908 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:41:32,909 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1902088530] [2022-12-13 19:41:32,909 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:41:32,909 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:41:32,920 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:41:32,959 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:41:32,959 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:41:32,959 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1902088530] [2022-12-13 19:41:32,960 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1902088530] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:41:32,960 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:41:32,960 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-12-13 19:41:32,960 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [534717622] [2022-12-13 19:41:32,960 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:41:32,962 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 19:41:32,962 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 19:41:32,994 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 19:41:32,995 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 19:41:32,998 INFO L87 Difference]: Start difference. First operand has 694 states, 693 states have (on average 1.5252525252525253) internal successors, (1057), 693 states have internal predecessors, (1057), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:41:33,050 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 19:41:33,050 INFO L93 Difference]: Finished difference Result 692 states and 1034 transitions. [2022-12-13 19:41:33,051 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 692 states and 1034 transitions. [2022-12-13 19:41:33,057 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 595 [2022-12-13 19:41:33,066 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 692 states to 686 states and 1028 transitions. [2022-12-13 19:41:33,067 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 686 [2022-12-13 19:41:33,068 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 686 [2022-12-13 19:41:33,069 INFO L73 IsDeterministic]: Start isDeterministic. Operand 686 states and 1028 transitions. [2022-12-13 19:41:33,073 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 19:41:33,073 INFO L218 hiAutomatonCegarLoop]: Abstraction has 686 states and 1028 transitions. [2022-12-13 19:41:33,090 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 686 states and 1028 transitions. [2022-12-13 19:41:33,113 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 686 to 686. [2022-12-13 19:41:33,114 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 686 states, 686 states have (on average 1.498542274052478) internal successors, (1028), 685 states have internal predecessors, (1028), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:41:33,117 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 686 states to 686 states and 1028 transitions. [2022-12-13 19:41:33,118 INFO L240 hiAutomatonCegarLoop]: Abstraction has 686 states and 1028 transitions. [2022-12-13 19:41:33,119 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 19:41:33,122 INFO L428 stractBuchiCegarLoop]: Abstraction has 686 states and 1028 transitions. [2022-12-13 19:41:33,123 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2022-12-13 19:41:33,123 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 686 states and 1028 transitions. [2022-12-13 19:41:33,127 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 595 [2022-12-13 19:41:33,127 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 19:41:33,127 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 19:41:33,129 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:41:33,129 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:41:33,130 INFO L748 eck$LassoCheckResult]: Stem: 1757#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 1758#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 1912#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1913#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2046#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 1652#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1653#L492-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 1487#L497-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1488#L502-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1457#L507-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 1458#L512-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 1629#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1788#L696 assume !(0 == ~M_E~0); 1789#L696-2 assume !(0 == ~T1_E~0); 2049#L701-1 assume !(0 == ~T2_E~0); 2052#L706-1 assume !(0 == ~T3_E~0); 1891#L711-1 assume !(0 == ~T4_E~0); 1687#L716-1 assume !(0 == ~T5_E~0); 1688#L721-1 assume !(0 == ~T6_E~0); 1853#L726-1 assume 0 == ~E_M~0;~E_M~0 := 1; 1854#L731-1 assume !(0 == ~E_1~0); 1823#L736-1 assume !(0 == ~E_2~0); 1824#L741-1 assume !(0 == ~E_3~0); 1900#L746-1 assume !(0 == ~E_4~0); 1713#L751-1 assume !(0 == ~E_5~0); 1714#L756-1 assume !(0 == ~E_6~0); 1684#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1508#L346 assume !(1 == ~m_pc~0); 1509#L346-2 is_master_triggered_~__retres1~0#1 := 0; 1728#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1720#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1721#L861 assume !(0 != activate_threads_~tmp~1#1); 2027#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1541#L365 assume 1 == ~t1_pc~0; 1542#L366 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1673#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1494#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1495#L869 assume !(0 != activate_threads_~tmp___0~0#1); 1530#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1947#L384 assume !(1 == ~t2_pc~0); 1943#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1944#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1918#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1445#L877 assume !(0 != activate_threads_~tmp___1~0#1); 1446#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1803#L403 assume 1 == ~t3_pc~0; 1689#L404 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1690#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1415#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1416#L885 assume !(0 != activate_threads_~tmp___2~0#1); 1798#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1799#L422 assume 1 == ~t4_pc~0; 1442#L423 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1443#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1593#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1594#L893 assume !(0 != activate_threads_~tmp___3~0#1); 1873#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1459#L441 assume !(1 == ~t5_pc~0); 1460#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 2024#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1731#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1732#L901 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1883#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1884#L460 assume 1 == ~t6_pc~0; 1403#L461 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1404#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1467#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1902#L909 assume !(0 != activate_threads_~tmp___5~0#1); 1988#L909-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1861#L774 assume !(1 == ~M_E~0); 1862#L774-2 assume !(1 == ~T1_E~0); 2005#L779-1 assume !(1 == ~T2_E~0); 1774#L784-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1775#L789-1 assume !(1 == ~T4_E~0); 1525#L794-1 assume !(1 == ~T5_E~0); 1526#L799-1 assume !(1 == ~T6_E~0); 2069#L804-1 assume !(1 == ~E_M~0); 2070#L809-1 assume !(1 == ~E_1~0); 1851#L814-1 assume !(1 == ~E_2~0); 1421#L819-1 assume !(1 == ~E_3~0); 1422#L824-1 assume 1 == ~E_4~0;~E_4~0 := 2; 1908#L829-1 assume !(1 == ~E_5~0); 1995#L834-1 assume !(1 == ~E_6~0); 1674#L839-1 assume { :end_inline_reset_delta_events } true; 1657#L1065-2 [2022-12-13 19:41:33,130 INFO L750 eck$LassoCheckResult]: Loop: 1657#L1065-2 assume !false; 1658#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1519#L671 assume !false; 2036#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1975#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1497#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1511#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1935#L582 assume !(0 != eval_~tmp~0#1); 1609#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1610#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1703#L696-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1704#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1753#L701-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1754#L706-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2056#L711-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2050#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1904#L721-3 assume !(0 == ~T6_E~0); 1735#L726-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1736#L731-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1896#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1897#L741-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1681#L746-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1682#L751-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1800#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1548#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1549#L346-24 assume 1 == ~m_pc~0; 1586#L347-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1677#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1627#is_master_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1628#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2003#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1619#L365-24 assume 1 == ~t1_pc~0; 1620#L366-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1903#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2047#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1965#L869-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1966#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1566#L384-24 assume 1 == ~t2_pc~0; 1568#L385-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1588#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2077#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1887#L877-24 assume !(0 != activate_threads_~tmp___1~0#1); 1598#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1599#L403-24 assume 1 == ~t3_pc~0; 1715#L404-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1755#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1756#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1848#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1849#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1654#L422-24 assume !(1 == ~t4_pc~0); 1655#L422-26 is_transmit4_triggered_~__retres1~4#1 := 0; 1604#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1605#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2030#L893-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 2011#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1670#L441-24 assume 1 == ~t5_pc~0; 1671#L442-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1866#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1819#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1531#L901-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1532#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1948#L460-24 assume !(1 == ~t6_pc~0); 1949#L460-26 is_transmit6_triggered_~__retres1~6#1 := 0; 2006#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1711#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1712#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1941#L909-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1942#L774-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1882#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1734#L779-3 assume !(1 == ~T2_E~0); 1440#L784-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1441#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1419#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1420#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1540#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1865#L809-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1538#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1539#L819-3 assume !(1 == ~E_3~0); 1695#L824-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1679#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1680#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1523#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1524#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1521#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1615#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 1454#L1084 assume !(0 == start_simulation_~tmp~3#1); 1456#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1709#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1424#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1485#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 1486#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1553#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1554#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 1722#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 1657#L1065-2 [2022-12-13 19:41:33,131 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:41:33,131 INFO L85 PathProgramCache]: Analyzing trace with hash 765667843, now seen corresponding path program 1 times [2022-12-13 19:41:33,131 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:41:33,131 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1665301328] [2022-12-13 19:41:33,131 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:41:33,132 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:41:33,146 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:41:33,191 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:41:33,191 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:41:33,191 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1665301328] [2022-12-13 19:41:33,191 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1665301328] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:41:33,192 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:41:33,192 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:41:33,192 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [428729512] [2022-12-13 19:41:33,192 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:41:33,192 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 19:41:33,193 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:41:33,193 INFO L85 PathProgramCache]: Analyzing trace with hash 53365307, now seen corresponding path program 1 times [2022-12-13 19:41:33,193 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:41:33,193 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1857628842] [2022-12-13 19:41:33,193 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:41:33,194 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:41:33,215 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:41:33,268 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:41:33,268 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:41:33,268 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1857628842] [2022-12-13 19:41:33,268 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1857628842] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:41:33,268 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:41:33,269 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:41:33,269 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [198197218] [2022-12-13 19:41:33,269 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:41:33,269 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 19:41:33,269 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 19:41:33,270 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 19:41:33,270 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 19:41:33,270 INFO L87 Difference]: Start difference. First operand 686 states and 1028 transitions. cyclomatic complexity: 343 Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:41:33,288 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 19:41:33,289 INFO L93 Difference]: Finished difference Result 686 states and 1027 transitions. [2022-12-13 19:41:33,289 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 686 states and 1027 transitions. [2022-12-13 19:41:33,293 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 595 [2022-12-13 19:41:33,297 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 686 states to 686 states and 1027 transitions. [2022-12-13 19:41:33,297 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 686 [2022-12-13 19:41:33,298 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 686 [2022-12-13 19:41:33,298 INFO L73 IsDeterministic]: Start isDeterministic. Operand 686 states and 1027 transitions. [2022-12-13 19:41:33,300 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 19:41:33,301 INFO L218 hiAutomatonCegarLoop]: Abstraction has 686 states and 1027 transitions. [2022-12-13 19:41:33,302 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 686 states and 1027 transitions. [2022-12-13 19:41:33,311 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 686 to 686. [2022-12-13 19:41:33,313 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 686 states, 686 states have (on average 1.4970845481049562) internal successors, (1027), 685 states have internal predecessors, (1027), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:41:33,315 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 686 states to 686 states and 1027 transitions. [2022-12-13 19:41:33,315 INFO L240 hiAutomatonCegarLoop]: Abstraction has 686 states and 1027 transitions. [2022-12-13 19:41:33,316 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 19:41:33,317 INFO L428 stractBuchiCegarLoop]: Abstraction has 686 states and 1027 transitions. [2022-12-13 19:41:33,317 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2022-12-13 19:41:33,317 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 686 states and 1027 transitions. [2022-12-13 19:41:33,320 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 595 [2022-12-13 19:41:33,320 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 19:41:33,320 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 19:41:33,322 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:41:33,322 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:41:33,323 INFO L748 eck$LassoCheckResult]: Stem: 3134#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 3135#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 3291#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3292#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3425#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 3031#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3032#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2862#L497-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 2863#L502-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2836#L507-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 2837#L512-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 3008#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3167#L696 assume !(0 == ~M_E~0); 3168#L696-2 assume !(0 == ~T1_E~0); 3428#L701-1 assume !(0 == ~T2_E~0); 3430#L706-1 assume !(0 == ~T3_E~0); 3270#L711-1 assume !(0 == ~T4_E~0); 3066#L716-1 assume !(0 == ~T5_E~0); 3067#L721-1 assume !(0 == ~T6_E~0); 3232#L726-1 assume 0 == ~E_M~0;~E_M~0 := 1; 3233#L731-1 assume !(0 == ~E_1~0); 3202#L736-1 assume !(0 == ~E_2~0); 3203#L741-1 assume !(0 == ~E_3~0); 3279#L746-1 assume !(0 == ~E_4~0); 3092#L751-1 assume !(0 == ~E_5~0); 3093#L756-1 assume !(0 == ~E_6~0); 3063#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2885#L346 assume !(1 == ~m_pc~0); 2886#L346-2 is_master_triggered_~__retres1~0#1 := 0; 3107#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3099#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 3100#L861 assume !(0 != activate_threads_~tmp~1#1); 3406#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2919#L365 assume 1 == ~t1_pc~0; 2920#L366 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3049#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2868#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2869#L869 assume !(0 != activate_threads_~tmp___0~0#1); 2909#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3326#L384 assume !(1 == ~t2_pc~0); 3320#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 3321#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3293#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2824#L877 assume !(0 != activate_threads_~tmp___1~0#1); 2825#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3181#L403 assume 1 == ~t3_pc~0; 3068#L404 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3069#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2794#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2795#L885 assume !(0 != activate_threads_~tmp___2~0#1); 3174#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3175#L422 assume 1 == ~t4_pc~0; 2819#L423 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2820#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2972#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2973#L893 assume !(0 != activate_threads_~tmp___3~0#1); 3252#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2838#L441 assume !(1 == ~t5_pc~0); 2839#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 3402#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3110#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3111#L901 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 3261#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3262#L460 assume 1 == ~t6_pc~0; 2779#L461 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 2780#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2846#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3281#L909 assume !(0 != activate_threads_~tmp___5~0#1); 3367#L909-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3240#L774 assume !(1 == ~M_E~0); 3241#L774-2 assume !(1 == ~T1_E~0); 3384#L779-1 assume !(1 == ~T2_E~0); 3153#L784-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3154#L789-1 assume !(1 == ~T4_E~0); 2904#L794-1 assume !(1 == ~T5_E~0); 2905#L799-1 assume !(1 == ~T6_E~0); 3448#L804-1 assume !(1 == ~E_M~0); 3449#L809-1 assume !(1 == ~E_1~0); 3229#L814-1 assume !(1 == ~E_2~0); 2798#L819-1 assume !(1 == ~E_3~0); 2799#L824-1 assume 1 == ~E_4~0;~E_4~0 := 2; 3287#L829-1 assume !(1 == ~E_5~0); 3374#L834-1 assume !(1 == ~E_6~0); 3050#L839-1 assume { :end_inline_reset_delta_events } true; 3036#L1065-2 [2022-12-13 19:41:33,323 INFO L750 eck$LassoCheckResult]: Loop: 3036#L1065-2 assume !false; 3037#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2898#L671 assume !false; 3415#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 3354#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 2876#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 2890#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 3313#L582 assume !(0 != eval_~tmp~0#1); 2986#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2987#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3082#L696-3 assume 0 == ~M_E~0;~M_E~0 := 1; 3083#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3132#L701-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3133#L706-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3435#L711-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3429#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 3282#L721-3 assume !(0 == ~T6_E~0); 3114#L726-3 assume 0 == ~E_M~0;~E_M~0 := 1; 3115#L731-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3275#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3276#L741-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3060#L746-3 assume 0 == ~E_4~0;~E_4~0 := 1; 3061#L751-3 assume 0 == ~E_5~0;~E_5~0 := 1; 3179#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 2927#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2928#L346-24 assume 1 == ~m_pc~0; 2962#L347-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 3056#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3006#is_master_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 3007#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3382#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2998#L365-24 assume 1 == ~t1_pc~0; 2999#L366-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3283#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3426#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3346#L869-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3347#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2947#L384-24 assume !(1 == ~t2_pc~0); 2948#L384-26 is_transmit2_triggered_~__retres1~2#1 := 0; 2969#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3456#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3266#L877-24 assume !(0 != activate_threads_~tmp___1~0#1); 2978#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2979#L403-24 assume 1 == ~t3_pc~0; 3094#L404-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3136#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3137#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3227#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3228#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3033#L422-24 assume !(1 == ~t4_pc~0); 3034#L422-26 is_transmit4_triggered_~__retres1~4#1 := 0; 2984#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2985#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3409#L893-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 3390#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3051#L441-24 assume 1 == ~t5_pc~0; 3052#L442-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 3246#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3198#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2910#L901-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 2911#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3327#L460-24 assume !(1 == ~t6_pc~0); 3328#L460-26 is_transmit6_triggered_~__retres1~6#1 := 0; 3385#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3090#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3091#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 3322#L909-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3323#L774-3 assume 1 == ~M_E~0;~M_E~0 := 2; 3263#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3113#L779-3 assume !(1 == ~T2_E~0); 2822#L784-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2823#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2800#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2801#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 2922#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 3244#L809-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2917#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2918#L819-3 assume !(1 == ~E_3~0); 3074#L824-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3058#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3059#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 2902#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 2903#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 2900#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 2994#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 2833#L1084 assume !(0 == start_simulation_~tmp~3#1); 2835#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 3088#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 2803#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 2866#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 2867#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2933#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2934#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 3101#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 3036#L1065-2 [2022-12-13 19:41:33,323 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:41:33,324 INFO L85 PathProgramCache]: Analyzing trace with hash -73365819, now seen corresponding path program 1 times [2022-12-13 19:41:33,324 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:41:33,324 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1528699059] [2022-12-13 19:41:33,324 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:41:33,324 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:41:33,337 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:41:33,369 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:41:33,369 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:41:33,369 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1528699059] [2022-12-13 19:41:33,369 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1528699059] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:41:33,370 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:41:33,370 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:41:33,370 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1719847538] [2022-12-13 19:41:33,370 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:41:33,370 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 19:41:33,371 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:41:33,371 INFO L85 PathProgramCache]: Analyzing trace with hash 293632636, now seen corresponding path program 1 times [2022-12-13 19:41:33,371 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:41:33,371 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [819456112] [2022-12-13 19:41:33,371 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:41:33,372 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:41:33,386 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:41:33,437 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:41:33,437 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:41:33,437 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [819456112] [2022-12-13 19:41:33,438 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [819456112] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:41:33,438 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:41:33,438 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:41:33,438 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [237744419] [2022-12-13 19:41:33,438 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:41:33,438 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 19:41:33,439 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 19:41:33,439 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 19:41:33,439 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 19:41:33,439 INFO L87 Difference]: Start difference. First operand 686 states and 1027 transitions. cyclomatic complexity: 342 Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:41:33,452 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 19:41:33,453 INFO L93 Difference]: Finished difference Result 686 states and 1026 transitions. [2022-12-13 19:41:33,453 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 686 states and 1026 transitions. [2022-12-13 19:41:33,455 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 595 [2022-12-13 19:41:33,457 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 686 states to 686 states and 1026 transitions. [2022-12-13 19:41:33,457 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 686 [2022-12-13 19:41:33,458 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 686 [2022-12-13 19:41:33,458 INFO L73 IsDeterministic]: Start isDeterministic. Operand 686 states and 1026 transitions. [2022-12-13 19:41:33,458 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 19:41:33,458 INFO L218 hiAutomatonCegarLoop]: Abstraction has 686 states and 1026 transitions. [2022-12-13 19:41:33,459 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 686 states and 1026 transitions. [2022-12-13 19:41:33,464 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 686 to 686. [2022-12-13 19:41:33,465 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 686 states, 686 states have (on average 1.4956268221574345) internal successors, (1026), 685 states have internal predecessors, (1026), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:41:33,466 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 686 states to 686 states and 1026 transitions. [2022-12-13 19:41:33,466 INFO L240 hiAutomatonCegarLoop]: Abstraction has 686 states and 1026 transitions. [2022-12-13 19:41:33,466 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 19:41:33,467 INFO L428 stractBuchiCegarLoop]: Abstraction has 686 states and 1026 transitions. [2022-12-13 19:41:33,467 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2022-12-13 19:41:33,467 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 686 states and 1026 transitions. [2022-12-13 19:41:33,469 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 595 [2022-12-13 19:41:33,469 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 19:41:33,469 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 19:41:33,470 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:41:33,470 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:41:33,470 INFO L748 eck$LassoCheckResult]: Stem: 4513#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 4514#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 4670#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4671#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4804#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 4410#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4411#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4241#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 4242#L502-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 4215#L507-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 4216#L512-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 4387#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4546#L696 assume !(0 == ~M_E~0); 4547#L696-2 assume !(0 == ~T1_E~0); 4807#L701-1 assume !(0 == ~T2_E~0); 4809#L706-1 assume !(0 == ~T3_E~0); 4649#L711-1 assume !(0 == ~T4_E~0); 4445#L716-1 assume !(0 == ~T5_E~0); 4446#L721-1 assume !(0 == ~T6_E~0); 4611#L726-1 assume 0 == ~E_M~0;~E_M~0 := 1; 4612#L731-1 assume !(0 == ~E_1~0); 4581#L736-1 assume !(0 == ~E_2~0); 4582#L741-1 assume !(0 == ~E_3~0); 4658#L746-1 assume !(0 == ~E_4~0); 4471#L751-1 assume !(0 == ~E_5~0); 4472#L756-1 assume !(0 == ~E_6~0); 4442#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4264#L346 assume !(1 == ~m_pc~0); 4265#L346-2 is_master_triggered_~__retres1~0#1 := 0; 4486#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4478#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4479#L861 assume !(0 != activate_threads_~tmp~1#1); 4785#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4298#L365 assume 1 == ~t1_pc~0; 4299#L366 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4428#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4247#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4248#L869 assume !(0 != activate_threads_~tmp___0~0#1); 4288#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4705#L384 assume !(1 == ~t2_pc~0); 4699#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 4700#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4672#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4203#L877 assume !(0 != activate_threads_~tmp___1~0#1); 4204#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4560#L403 assume 1 == ~t3_pc~0; 4447#L404 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 4448#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4173#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4174#L885 assume !(0 != activate_threads_~tmp___2~0#1); 4553#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4554#L422 assume 1 == ~t4_pc~0; 4198#L423 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 4199#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4351#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4352#L893 assume !(0 != activate_threads_~tmp___3~0#1); 4631#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4217#L441 assume !(1 == ~t5_pc~0); 4218#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 4781#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4489#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4490#L901 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 4640#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4641#L460 assume 1 == ~t6_pc~0; 4158#L461 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 4159#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4225#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4660#L909 assume !(0 != activate_threads_~tmp___5~0#1); 4746#L909-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4619#L774 assume !(1 == ~M_E~0); 4620#L774-2 assume !(1 == ~T1_E~0); 4763#L779-1 assume !(1 == ~T2_E~0); 4532#L784-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4533#L789-1 assume !(1 == ~T4_E~0); 4283#L794-1 assume !(1 == ~T5_E~0); 4284#L799-1 assume !(1 == ~T6_E~0); 4827#L804-1 assume !(1 == ~E_M~0); 4828#L809-1 assume !(1 == ~E_1~0); 4608#L814-1 assume !(1 == ~E_2~0); 4177#L819-1 assume !(1 == ~E_3~0); 4178#L824-1 assume 1 == ~E_4~0;~E_4~0 := 2; 4666#L829-1 assume !(1 == ~E_5~0); 4753#L834-1 assume !(1 == ~E_6~0); 4429#L839-1 assume { :end_inline_reset_delta_events } true; 4415#L1065-2 [2022-12-13 19:41:33,470 INFO L750 eck$LassoCheckResult]: Loop: 4415#L1065-2 assume !false; 4416#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4277#L671 assume !false; 4794#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 4733#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 4255#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 4269#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 4692#L582 assume !(0 != eval_~tmp~0#1); 4365#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4366#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4461#L696-3 assume 0 == ~M_E~0;~M_E~0 := 1; 4462#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4511#L701-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4512#L706-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4814#L711-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4808#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 4661#L721-3 assume !(0 == ~T6_E~0); 4493#L726-3 assume 0 == ~E_M~0;~E_M~0 := 1; 4494#L731-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4654#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4655#L741-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4439#L746-3 assume 0 == ~E_4~0;~E_4~0 := 1; 4440#L751-3 assume 0 == ~E_5~0;~E_5~0 := 1; 4558#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 4306#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4307#L346-24 assume 1 == ~m_pc~0; 4341#L347-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 4435#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4385#is_master_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4386#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4761#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4377#L365-24 assume 1 == ~t1_pc~0; 4378#L366-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4662#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4805#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4725#L869-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4726#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4328#L384-24 assume !(1 == ~t2_pc~0); 4329#L384-26 is_transmit2_triggered_~__retres1~2#1 := 0; 4348#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4835#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4645#L877-24 assume !(0 != activate_threads_~tmp___1~0#1); 4357#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4358#L403-24 assume 1 == ~t3_pc~0; 4473#L404-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 4515#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4516#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4606#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4607#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4412#L422-24 assume !(1 == ~t4_pc~0); 4413#L422-26 is_transmit4_triggered_~__retres1~4#1 := 0; 4363#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4364#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4788#L893-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 4769#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4430#L441-24 assume !(1 == ~t5_pc~0); 4432#L441-26 is_transmit5_triggered_~__retres1~5#1 := 0; 4625#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4577#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4289#L901-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 4290#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4706#L460-24 assume !(1 == ~t6_pc~0); 4707#L460-26 is_transmit6_triggered_~__retres1~6#1 := 0; 4764#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4469#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4470#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 4701#L909-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4702#L774-3 assume 1 == ~M_E~0;~M_E~0 := 2; 4642#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4492#L779-3 assume !(1 == ~T2_E~0); 4201#L784-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4202#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4179#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 4180#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 4301#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 4623#L809-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4296#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4297#L819-3 assume !(1 == ~E_3~0); 4453#L824-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4437#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 4438#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 4281#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 4282#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 4279#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 4373#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 4212#L1084 assume !(0 == start_simulation_~tmp~3#1); 4214#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 4467#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 4182#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 4245#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 4246#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4312#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4313#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 4480#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 4415#L1065-2 [2022-12-13 19:41:33,471 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:41:33,471 INFO L85 PathProgramCache]: Analyzing trace with hash -100431421, now seen corresponding path program 1 times [2022-12-13 19:41:33,471 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:41:33,471 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1998139784] [2022-12-13 19:41:33,471 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:41:33,471 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:41:33,478 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:41:33,496 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:41:33,496 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:41:33,496 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1998139784] [2022-12-13 19:41:33,497 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1998139784] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:41:33,497 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:41:33,497 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:41:33,497 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1138654836] [2022-12-13 19:41:33,497 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:41:33,497 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 19:41:33,498 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:41:33,498 INFO L85 PathProgramCache]: Analyzing trace with hash -663295747, now seen corresponding path program 1 times [2022-12-13 19:41:33,498 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:41:33,498 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [684794692] [2022-12-13 19:41:33,498 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:41:33,499 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:41:33,511 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:41:33,534 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:41:33,535 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:41:33,535 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [684794692] [2022-12-13 19:41:33,535 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [684794692] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:41:33,535 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:41:33,535 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:41:33,535 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1644585891] [2022-12-13 19:41:33,535 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:41:33,535 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 19:41:33,535 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 19:41:33,536 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 19:41:33,536 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 19:41:33,536 INFO L87 Difference]: Start difference. First operand 686 states and 1026 transitions. cyclomatic complexity: 341 Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:41:33,548 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 19:41:33,548 INFO L93 Difference]: Finished difference Result 686 states and 1025 transitions. [2022-12-13 19:41:33,548 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 686 states and 1025 transitions. [2022-12-13 19:41:33,550 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 595 [2022-12-13 19:41:33,552 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 686 states to 686 states and 1025 transitions. [2022-12-13 19:41:33,552 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 686 [2022-12-13 19:41:33,553 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 686 [2022-12-13 19:41:33,553 INFO L73 IsDeterministic]: Start isDeterministic. Operand 686 states and 1025 transitions. [2022-12-13 19:41:33,553 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 19:41:33,554 INFO L218 hiAutomatonCegarLoop]: Abstraction has 686 states and 1025 transitions. [2022-12-13 19:41:33,554 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 686 states and 1025 transitions. [2022-12-13 19:41:33,559 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 686 to 686. [2022-12-13 19:41:33,560 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 686 states, 686 states have (on average 1.4941690962099126) internal successors, (1025), 685 states have internal predecessors, (1025), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:41:33,561 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 686 states to 686 states and 1025 transitions. [2022-12-13 19:41:33,561 INFO L240 hiAutomatonCegarLoop]: Abstraction has 686 states and 1025 transitions. [2022-12-13 19:41:33,561 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 19:41:33,562 INFO L428 stractBuchiCegarLoop]: Abstraction has 686 states and 1025 transitions. [2022-12-13 19:41:33,562 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2022-12-13 19:41:33,562 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 686 states and 1025 transitions. [2022-12-13 19:41:33,564 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 595 [2022-12-13 19:41:33,564 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 19:41:33,564 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 19:41:33,565 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:41:33,565 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:41:33,565 INFO L748 eck$LassoCheckResult]: Stem: 5894#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 5895#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 6049#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 6050#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6183#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 5789#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5790#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5624#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 5625#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 5594#L507-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 5595#L512-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 5766#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5925#L696 assume !(0 == ~M_E~0); 5926#L696-2 assume !(0 == ~T1_E~0); 6186#L701-1 assume !(0 == ~T2_E~0); 6189#L706-1 assume !(0 == ~T3_E~0); 6028#L711-1 assume !(0 == ~T4_E~0); 5824#L716-1 assume !(0 == ~T5_E~0); 5825#L721-1 assume !(0 == ~T6_E~0); 5990#L726-1 assume 0 == ~E_M~0;~E_M~0 := 1; 5991#L731-1 assume !(0 == ~E_1~0); 5960#L736-1 assume !(0 == ~E_2~0); 5961#L741-1 assume !(0 == ~E_3~0); 6037#L746-1 assume !(0 == ~E_4~0); 5850#L751-1 assume !(0 == ~E_5~0); 5851#L756-1 assume !(0 == ~E_6~0); 5821#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5645#L346 assume !(1 == ~m_pc~0); 5646#L346-2 is_master_triggered_~__retres1~0#1 := 0; 5865#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5857#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 5858#L861 assume !(0 != activate_threads_~tmp~1#1); 6164#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5678#L365 assume 1 == ~t1_pc~0; 5679#L366 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 5810#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5631#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 5632#L869 assume !(0 != activate_threads_~tmp___0~0#1); 5667#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6084#L384 assume !(1 == ~t2_pc~0); 6080#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 6081#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6055#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5584#L877 assume !(0 != activate_threads_~tmp___1~0#1); 5585#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5940#L403 assume 1 == ~t3_pc~0; 5826#L404 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 5827#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5552#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 5553#L885 assume !(0 != activate_threads_~tmp___2~0#1); 5935#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5936#L422 assume 1 == ~t4_pc~0; 5579#L423 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5580#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5730#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 5731#L893 assume !(0 != activate_threads_~tmp___3~0#1); 6010#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5596#L441 assume !(1 == ~t5_pc~0); 5597#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 6161#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5869#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 5870#L901 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 6020#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6021#L460 assume 1 == ~t6_pc~0; 5540#L461 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 5541#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5604#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 6039#L909 assume !(0 != activate_threads_~tmp___5~0#1); 6125#L909-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5998#L774 assume !(1 == ~M_E~0); 5999#L774-2 assume !(1 == ~T1_E~0); 6142#L779-1 assume !(1 == ~T2_E~0); 5911#L784-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 5912#L789-1 assume !(1 == ~T4_E~0); 5662#L794-1 assume !(1 == ~T5_E~0); 5663#L799-1 assume !(1 == ~T6_E~0); 6206#L804-1 assume !(1 == ~E_M~0); 6207#L809-1 assume !(1 == ~E_1~0); 5988#L814-1 assume !(1 == ~E_2~0); 5558#L819-1 assume !(1 == ~E_3~0); 5559#L824-1 assume 1 == ~E_4~0;~E_4~0 := 2; 6045#L829-1 assume !(1 == ~E_5~0); 6132#L834-1 assume !(1 == ~E_6~0); 5811#L839-1 assume { :end_inline_reset_delta_events } true; 5797#L1065-2 [2022-12-13 19:41:33,565 INFO L750 eck$LassoCheckResult]: Loop: 5797#L1065-2 assume !false; 5798#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5656#L671 assume !false; 6173#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 6112#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 5634#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 5648#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 6072#L582 assume !(0 != eval_~tmp~0#1); 5746#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5747#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5840#L696-3 assume 0 == ~M_E~0;~M_E~0 := 1; 5841#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 5890#L701-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 5891#L706-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 6193#L711-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 6187#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 6041#L721-3 assume !(0 == ~T6_E~0); 5872#L726-3 assume 0 == ~E_M~0;~E_M~0 := 1; 5873#L731-3 assume 0 == ~E_1~0;~E_1~0 := 1; 6033#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 6034#L741-3 assume 0 == ~E_3~0;~E_3~0 := 1; 5818#L746-3 assume 0 == ~E_4~0;~E_4~0 := 1; 5819#L751-3 assume 0 == ~E_5~0;~E_5~0 := 1; 5937#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 5685#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5686#L346-24 assume 1 == ~m_pc~0; 5723#L347-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 5812#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5764#is_master_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 5765#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 6140#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5756#L365-24 assume 1 == ~t1_pc~0; 5757#L366-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 6040#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6184#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 6102#L869-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 6103#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5705#L384-24 assume !(1 == ~t2_pc~0); 5706#L384-26 is_transmit2_triggered_~__retres1~2#1 := 0; 5725#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6214#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 6024#L877-24 assume !(0 != activate_threads_~tmp___1~0#1); 5735#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5736#L403-24 assume 1 == ~t3_pc~0; 5852#L404-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 5892#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5893#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 5985#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 5986#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5791#L422-24 assume !(1 == ~t4_pc~0); 5792#L422-26 is_transmit4_triggered_~__retres1~4#1 := 0; 5741#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5742#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6167#L893-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 6148#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5807#L441-24 assume 1 == ~t5_pc~0; 5808#L442-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 6003#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5956#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 5668#L901-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 5669#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6085#L460-24 assume !(1 == ~t6_pc~0); 6086#L460-26 is_transmit6_triggered_~__retres1~6#1 := 0; 6143#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5848#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 5849#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 6078#L909-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6079#L774-3 assume 1 == ~M_E~0;~M_E~0 := 2; 6019#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5871#L779-3 assume !(1 == ~T2_E~0); 5577#L784-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 5578#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5556#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 5557#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 5677#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 6002#L809-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5675#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5676#L819-3 assume !(1 == ~E_3~0); 5832#L824-3 assume 1 == ~E_4~0;~E_4~0 := 2; 5816#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 5817#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 5660#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 5661#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 5658#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 5752#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 5591#L1084 assume !(0 == start_simulation_~tmp~3#1); 5593#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 5846#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 5561#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 5622#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 5623#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5690#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5691#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 5859#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 5797#L1065-2 [2022-12-13 19:41:33,566 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:41:33,566 INFO L85 PathProgramCache]: Analyzing trace with hash 1976905477, now seen corresponding path program 1 times [2022-12-13 19:41:33,566 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:41:33,566 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [987775775] [2022-12-13 19:41:33,566 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:41:33,566 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:41:33,573 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:41:33,589 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:41:33,590 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:41:33,590 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [987775775] [2022-12-13 19:41:33,590 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [987775775] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:41:33,590 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:41:33,590 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:41:33,590 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [574545957] [2022-12-13 19:41:33,590 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:41:33,591 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 19:41:33,591 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:41:33,591 INFO L85 PathProgramCache]: Analyzing trace with hash 293632636, now seen corresponding path program 2 times [2022-12-13 19:41:33,591 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:41:33,591 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [796584227] [2022-12-13 19:41:33,592 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:41:33,592 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:41:33,602 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:41:33,624 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:41:33,624 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:41:33,625 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [796584227] [2022-12-13 19:41:33,625 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [796584227] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:41:33,625 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:41:33,625 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:41:33,625 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [743377605] [2022-12-13 19:41:33,625 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:41:33,626 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 19:41:33,626 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 19:41:33,626 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 19:41:33,626 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 19:41:33,627 INFO L87 Difference]: Start difference. First operand 686 states and 1025 transitions. cyclomatic complexity: 340 Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:41:33,647 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 19:41:33,647 INFO L93 Difference]: Finished difference Result 686 states and 1024 transitions. [2022-12-13 19:41:33,647 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 686 states and 1024 transitions. [2022-12-13 19:41:33,649 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 595 [2022-12-13 19:41:33,651 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 686 states to 686 states and 1024 transitions. [2022-12-13 19:41:33,651 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 686 [2022-12-13 19:41:33,651 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 686 [2022-12-13 19:41:33,651 INFO L73 IsDeterministic]: Start isDeterministic. Operand 686 states and 1024 transitions. [2022-12-13 19:41:33,652 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 19:41:33,652 INFO L218 hiAutomatonCegarLoop]: Abstraction has 686 states and 1024 transitions. [2022-12-13 19:41:33,653 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 686 states and 1024 transitions. [2022-12-13 19:41:33,657 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 686 to 686. [2022-12-13 19:41:33,658 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 686 states, 686 states have (on average 1.4927113702623906) internal successors, (1024), 685 states have internal predecessors, (1024), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:41:33,659 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 686 states to 686 states and 1024 transitions. [2022-12-13 19:41:33,659 INFO L240 hiAutomatonCegarLoop]: Abstraction has 686 states and 1024 transitions. [2022-12-13 19:41:33,660 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 19:41:33,660 INFO L428 stractBuchiCegarLoop]: Abstraction has 686 states and 1024 transitions. [2022-12-13 19:41:33,661 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2022-12-13 19:41:33,661 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 686 states and 1024 transitions. [2022-12-13 19:41:33,663 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 595 [2022-12-13 19:41:33,663 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 19:41:33,663 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 19:41:33,664 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:41:33,664 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:41:33,664 INFO L748 eck$LassoCheckResult]: Stem: 7271#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 7272#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 7428#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 7429#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7562#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 7168#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7169#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 6999#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 7000#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 6973#L507-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 6974#L512-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 7145#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7304#L696 assume !(0 == ~M_E~0); 7305#L696-2 assume !(0 == ~T1_E~0); 7565#L701-1 assume !(0 == ~T2_E~0); 7567#L706-1 assume !(0 == ~T3_E~0); 7407#L711-1 assume !(0 == ~T4_E~0); 7203#L716-1 assume !(0 == ~T5_E~0); 7204#L721-1 assume !(0 == ~T6_E~0); 7369#L726-1 assume 0 == ~E_M~0;~E_M~0 := 1; 7370#L731-1 assume !(0 == ~E_1~0); 7339#L736-1 assume !(0 == ~E_2~0); 7340#L741-1 assume !(0 == ~E_3~0); 7416#L746-1 assume !(0 == ~E_4~0); 7229#L751-1 assume !(0 == ~E_5~0); 7230#L756-1 assume !(0 == ~E_6~0); 7200#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7022#L346 assume !(1 == ~m_pc~0); 7023#L346-2 is_master_triggered_~__retres1~0#1 := 0; 7244#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7236#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 7237#L861 assume !(0 != activate_threads_~tmp~1#1); 7543#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7056#L365 assume 1 == ~t1_pc~0; 7057#L366 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 7186#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7005#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 7006#L869 assume !(0 != activate_threads_~tmp___0~0#1); 7046#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7463#L384 assume !(1 == ~t2_pc~0); 7457#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 7458#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7430#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 6961#L877 assume !(0 != activate_threads_~tmp___1~0#1); 6962#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7318#L403 assume 1 == ~t3_pc~0; 7205#L404 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 7206#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6931#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 6932#L885 assume !(0 != activate_threads_~tmp___2~0#1); 7311#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7312#L422 assume 1 == ~t4_pc~0; 6956#L423 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 6957#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7109#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 7110#L893 assume !(0 != activate_threads_~tmp___3~0#1); 7389#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6975#L441 assume !(1 == ~t5_pc~0); 6976#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 7539#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7247#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 7248#L901 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 7398#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7399#L460 assume 1 == ~t6_pc~0; 6916#L461 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 6917#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6983#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 7418#L909 assume !(0 != activate_threads_~tmp___5~0#1); 7504#L909-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7377#L774 assume !(1 == ~M_E~0); 7378#L774-2 assume !(1 == ~T1_E~0); 7521#L779-1 assume !(1 == ~T2_E~0); 7290#L784-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 7291#L789-1 assume !(1 == ~T4_E~0); 7041#L794-1 assume !(1 == ~T5_E~0); 7042#L799-1 assume !(1 == ~T6_E~0); 7585#L804-1 assume !(1 == ~E_M~0); 7586#L809-1 assume !(1 == ~E_1~0); 7366#L814-1 assume !(1 == ~E_2~0); 6935#L819-1 assume !(1 == ~E_3~0); 6936#L824-1 assume 1 == ~E_4~0;~E_4~0 := 2; 7424#L829-1 assume !(1 == ~E_5~0); 7511#L834-1 assume !(1 == ~E_6~0); 7187#L839-1 assume { :end_inline_reset_delta_events } true; 7173#L1065-2 [2022-12-13 19:41:33,664 INFO L750 eck$LassoCheckResult]: Loop: 7173#L1065-2 assume !false; 7174#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 7035#L671 assume !false; 7552#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 7491#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 7013#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 7027#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 7450#L582 assume !(0 != eval_~tmp~0#1); 7123#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 7124#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 7219#L696-3 assume 0 == ~M_E~0;~M_E~0 := 1; 7220#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 7269#L701-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7270#L706-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 7572#L711-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 7566#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 7419#L721-3 assume !(0 == ~T6_E~0); 7251#L726-3 assume 0 == ~E_M~0;~E_M~0 := 1; 7252#L731-3 assume 0 == ~E_1~0;~E_1~0 := 1; 7412#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 7413#L741-3 assume 0 == ~E_3~0;~E_3~0 := 1; 7197#L746-3 assume 0 == ~E_4~0;~E_4~0 := 1; 7198#L751-3 assume 0 == ~E_5~0;~E_5~0 := 1; 7316#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 7064#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7065#L346-24 assume 1 == ~m_pc~0; 7099#L347-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 7193#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7143#is_master_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 7144#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 7519#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7135#L365-24 assume 1 == ~t1_pc~0; 7136#L366-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 7420#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7563#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 7483#L869-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 7484#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7084#L384-24 assume !(1 == ~t2_pc~0); 7085#L384-26 is_transmit2_triggered_~__retres1~2#1 := 0; 7106#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7593#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 7403#L877-24 assume !(0 != activate_threads_~tmp___1~0#1); 7115#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7116#L403-24 assume !(1 == ~t3_pc~0); 7232#L403-26 is_transmit3_triggered_~__retres1~3#1 := 0; 7273#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7274#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 7364#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 7365#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7170#L422-24 assume !(1 == ~t4_pc~0); 7171#L422-26 is_transmit4_triggered_~__retres1~4#1 := 0; 7121#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7122#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 7546#L893-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 7527#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7188#L441-24 assume 1 == ~t5_pc~0; 7189#L442-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 7383#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7335#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 7047#L901-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 7048#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7464#L460-24 assume !(1 == ~t6_pc~0); 7465#L460-26 is_transmit6_triggered_~__retres1~6#1 := 0; 7522#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 7227#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 7228#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 7459#L909-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7460#L774-3 assume 1 == ~M_E~0;~M_E~0 := 2; 7400#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 7250#L779-3 assume !(1 == ~T2_E~0); 6959#L784-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 6960#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 6937#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 6938#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 7059#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 7381#L809-3 assume 1 == ~E_1~0;~E_1~0 := 2; 7054#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 7055#L819-3 assume !(1 == ~E_3~0); 7211#L824-3 assume 1 == ~E_4~0;~E_4~0 := 2; 7195#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 7196#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 7039#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 7040#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 7037#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 7131#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 6970#L1084 assume !(0 == start_simulation_~tmp~3#1); 6972#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 7225#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 6940#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 7003#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 7004#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 7070#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 7071#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 7238#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 7173#L1065-2 [2022-12-13 19:41:33,664 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:41:33,665 INFO L85 PathProgramCache]: Analyzing trace with hash 242801027, now seen corresponding path program 1 times [2022-12-13 19:41:33,665 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:41:33,665 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [507936283] [2022-12-13 19:41:33,665 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:41:33,665 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:41:33,671 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:41:33,689 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:41:33,689 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:41:33,689 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [507936283] [2022-12-13 19:41:33,690 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [507936283] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:41:33,690 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:41:33,690 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:41:33,690 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2096725888] [2022-12-13 19:41:33,690 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:41:33,690 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 19:41:33,691 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:41:33,691 INFO L85 PathProgramCache]: Analyzing trace with hash -1807208579, now seen corresponding path program 1 times [2022-12-13 19:41:33,691 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:41:33,691 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [209804981] [2022-12-13 19:41:33,691 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:41:33,692 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:41:33,700 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:41:33,725 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:41:33,725 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:41:33,725 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [209804981] [2022-12-13 19:41:33,725 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [209804981] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:41:33,725 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:41:33,725 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:41:33,726 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [25848929] [2022-12-13 19:41:33,726 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:41:33,726 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 19:41:33,726 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 19:41:33,727 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 19:41:33,727 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 19:41:33,727 INFO L87 Difference]: Start difference. First operand 686 states and 1024 transitions. cyclomatic complexity: 339 Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:41:33,739 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 19:41:33,739 INFO L93 Difference]: Finished difference Result 686 states and 1023 transitions. [2022-12-13 19:41:33,739 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 686 states and 1023 transitions. [2022-12-13 19:41:33,741 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 595 [2022-12-13 19:41:33,743 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 686 states to 686 states and 1023 transitions. [2022-12-13 19:41:33,743 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 686 [2022-12-13 19:41:33,744 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 686 [2022-12-13 19:41:33,744 INFO L73 IsDeterministic]: Start isDeterministic. Operand 686 states and 1023 transitions. [2022-12-13 19:41:33,744 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 19:41:33,744 INFO L218 hiAutomatonCegarLoop]: Abstraction has 686 states and 1023 transitions. [2022-12-13 19:41:33,745 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 686 states and 1023 transitions. [2022-12-13 19:41:33,750 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 686 to 686. [2022-12-13 19:41:33,751 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 686 states, 686 states have (on average 1.4912536443148687) internal successors, (1023), 685 states have internal predecessors, (1023), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:41:33,752 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 686 states to 686 states and 1023 transitions. [2022-12-13 19:41:33,752 INFO L240 hiAutomatonCegarLoop]: Abstraction has 686 states and 1023 transitions. [2022-12-13 19:41:33,752 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 19:41:33,753 INFO L428 stractBuchiCegarLoop]: Abstraction has 686 states and 1023 transitions. [2022-12-13 19:41:33,753 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2022-12-13 19:41:33,753 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 686 states and 1023 transitions. [2022-12-13 19:41:33,755 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 595 [2022-12-13 19:41:33,755 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 19:41:33,755 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 19:41:33,756 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:41:33,756 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:41:33,756 INFO L748 eck$LassoCheckResult]: Stem: 8650#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 8651#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 8807#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 8808#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 8941#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 8547#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 8548#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 8380#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 8381#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 8352#L507-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 8353#L512-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 8524#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8683#L696 assume !(0 == ~M_E~0); 8684#L696-2 assume !(0 == ~T1_E~0); 8944#L701-1 assume !(0 == ~T2_E~0); 8946#L706-1 assume !(0 == ~T3_E~0); 8786#L711-1 assume !(0 == ~T4_E~0); 8582#L716-1 assume !(0 == ~T5_E~0); 8583#L721-1 assume !(0 == ~T6_E~0); 8748#L726-1 assume 0 == ~E_M~0;~E_M~0 := 1; 8749#L731-1 assume !(0 == ~E_1~0); 8718#L736-1 assume !(0 == ~E_2~0); 8719#L741-1 assume !(0 == ~E_3~0); 8795#L746-1 assume !(0 == ~E_4~0); 8608#L751-1 assume !(0 == ~E_5~0); 8609#L756-1 assume !(0 == ~E_6~0); 8579#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8401#L346 assume !(1 == ~m_pc~0); 8402#L346-2 is_master_triggered_~__retres1~0#1 := 0; 8623#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8615#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 8616#L861 assume !(0 != activate_threads_~tmp~1#1); 8922#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8436#L365 assume 1 == ~t1_pc~0; 8437#L366 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 8565#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8384#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 8385#L869 assume !(0 != activate_threads_~tmp___0~0#1); 8425#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8842#L384 assume !(1 == ~t2_pc~0); 8836#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 8837#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8809#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 8340#L877 assume !(0 != activate_threads_~tmp___1~0#1); 8341#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8697#L403 assume 1 == ~t3_pc~0; 8584#L404 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 8585#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8310#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 8311#L885 assume !(0 != activate_threads_~tmp___2~0#1); 8690#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8691#L422 assume 1 == ~t4_pc~0; 8335#L423 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 8336#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8488#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 8489#L893 assume !(0 != activate_threads_~tmp___3~0#1); 8768#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8354#L441 assume !(1 == ~t5_pc~0); 8355#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 8918#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8626#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 8627#L901 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 8777#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8778#L460 assume 1 == ~t6_pc~0; 8295#L461 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 8296#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8362#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8797#L909 assume !(0 != activate_threads_~tmp___5~0#1); 8883#L909-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8756#L774 assume !(1 == ~M_E~0); 8757#L774-2 assume !(1 == ~T1_E~0); 8900#L779-1 assume !(1 == ~T2_E~0); 8669#L784-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 8670#L789-1 assume !(1 == ~T4_E~0); 8420#L794-1 assume !(1 == ~T5_E~0); 8421#L799-1 assume !(1 == ~T6_E~0); 8964#L804-1 assume !(1 == ~E_M~0); 8965#L809-1 assume !(1 == ~E_1~0); 8745#L814-1 assume !(1 == ~E_2~0); 8314#L819-1 assume !(1 == ~E_3~0); 8315#L824-1 assume 1 == ~E_4~0;~E_4~0 := 2; 8803#L829-1 assume !(1 == ~E_5~0); 8890#L834-1 assume !(1 == ~E_6~0); 8566#L839-1 assume { :end_inline_reset_delta_events } true; 8552#L1065-2 [2022-12-13 19:41:33,757 INFO L750 eck$LassoCheckResult]: Loop: 8552#L1065-2 assume !false; 8553#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 8414#L671 assume !false; 8931#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 8870#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 8392#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 8406#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 8829#L582 assume !(0 != eval_~tmp~0#1); 8502#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 8503#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 8598#L696-3 assume 0 == ~M_E~0;~M_E~0 := 1; 8599#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 8648#L701-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 8649#L706-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 8951#L711-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 8945#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 8798#L721-3 assume !(0 == ~T6_E~0); 8630#L726-3 assume 0 == ~E_M~0;~E_M~0 := 1; 8631#L731-3 assume 0 == ~E_1~0;~E_1~0 := 1; 8791#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 8792#L741-3 assume 0 == ~E_3~0;~E_3~0 := 1; 8576#L746-3 assume 0 == ~E_4~0;~E_4~0 := 1; 8577#L751-3 assume 0 == ~E_5~0;~E_5~0 := 1; 8695#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 8443#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8444#L346-24 assume 1 == ~m_pc~0; 8478#L347-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 8572#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8522#is_master_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 8523#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 8898#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8516#L365-24 assume 1 == ~t1_pc~0; 8517#L366-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 8799#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8942#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 8862#L869-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 8863#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8465#L384-24 assume !(1 == ~t2_pc~0); 8466#L384-26 is_transmit2_triggered_~__retres1~2#1 := 0; 8485#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8972#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 8782#L877-24 assume !(0 != activate_threads_~tmp___1~0#1); 8494#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8495#L403-24 assume 1 == ~t3_pc~0; 8610#L404-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 8652#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8653#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 8743#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 8744#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8549#L422-24 assume !(1 == ~t4_pc~0); 8550#L422-26 is_transmit4_triggered_~__retres1~4#1 := 0; 8500#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8501#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 8925#L893-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 8906#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8567#L441-24 assume 1 == ~t5_pc~0; 8568#L442-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 8762#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8714#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 8426#L901-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 8427#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8843#L460-24 assume !(1 == ~t6_pc~0); 8844#L460-26 is_transmit6_triggered_~__retres1~6#1 := 0; 8901#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8606#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8607#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 8838#L909-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8839#L774-3 assume 1 == ~M_E~0;~M_E~0 := 2; 8779#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 8629#L779-3 assume !(1 == ~T2_E~0); 8338#L784-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 8339#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8316#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 8317#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 8435#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 8760#L809-3 assume 1 == ~E_1~0;~E_1~0 := 2; 8428#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 8429#L819-3 assume !(1 == ~E_3~0); 8588#L824-3 assume 1 == ~E_4~0;~E_4~0 := 2; 8573#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 8574#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 8418#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 8419#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 8416#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 8510#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 8349#L1084 assume !(0 == start_simulation_~tmp~3#1); 8351#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 8604#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 8319#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 8378#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 8379#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 8445#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 8446#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 8617#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 8552#L1065-2 [2022-12-13 19:41:33,757 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:41:33,757 INFO L85 PathProgramCache]: Analyzing trace with hash -644421819, now seen corresponding path program 1 times [2022-12-13 19:41:33,757 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:41:33,757 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1107249615] [2022-12-13 19:41:33,757 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:41:33,757 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:41:33,765 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:41:33,806 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:41:33,806 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:41:33,806 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1107249615] [2022-12-13 19:41:33,806 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1107249615] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:41:33,806 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:41:33,807 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:41:33,807 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [988516650] [2022-12-13 19:41:33,807 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:41:33,807 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 19:41:33,807 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:41:33,807 INFO L85 PathProgramCache]: Analyzing trace with hash 293632636, now seen corresponding path program 3 times [2022-12-13 19:41:33,807 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:41:33,807 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1565604641] [2022-12-13 19:41:33,807 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:41:33,807 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:41:33,815 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:41:33,836 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:41:33,836 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:41:33,836 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1565604641] [2022-12-13 19:41:33,836 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1565604641] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:41:33,836 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:41:33,836 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:41:33,837 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [221603177] [2022-12-13 19:41:33,837 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:41:33,837 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 19:41:33,837 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 19:41:33,837 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 19:41:33,837 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 19:41:33,837 INFO L87 Difference]: Start difference. First operand 686 states and 1023 transitions. cyclomatic complexity: 338 Second operand has 4 states, 4 states have (on average 21.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:41:33,977 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 19:41:33,977 INFO L93 Difference]: Finished difference Result 1180 states and 1756 transitions. [2022-12-13 19:41:33,977 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1180 states and 1756 transitions. [2022-12-13 19:41:33,982 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1074 [2022-12-13 19:41:33,986 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1180 states to 1180 states and 1756 transitions. [2022-12-13 19:41:33,987 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1180 [2022-12-13 19:41:33,987 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1180 [2022-12-13 19:41:33,987 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1180 states and 1756 transitions. [2022-12-13 19:41:33,989 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 19:41:33,989 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1180 states and 1756 transitions. [2022-12-13 19:41:33,990 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1180 states and 1756 transitions. [2022-12-13 19:41:34,009 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1180 to 1179. [2022-12-13 19:41:34,011 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1179 states, 1179 states have (on average 1.4885496183206106) internal successors, (1755), 1178 states have internal predecessors, (1755), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:41:34,016 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1179 states to 1179 states and 1755 transitions. [2022-12-13 19:41:34,016 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1179 states and 1755 transitions. [2022-12-13 19:41:34,016 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 19:41:34,017 INFO L428 stractBuchiCegarLoop]: Abstraction has 1179 states and 1755 transitions. [2022-12-13 19:41:34,017 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2022-12-13 19:41:34,017 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1179 states and 1755 transitions. [2022-12-13 19:41:34,022 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1074 [2022-12-13 19:41:34,022 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 19:41:34,022 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 19:41:34,023 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:41:34,023 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:41:34,023 INFO L748 eck$LassoCheckResult]: Stem: 10529#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 10530#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 10696#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 10697#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 10842#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 10424#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 10425#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 10254#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 10255#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 10228#L507-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 10229#L512-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 10401#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 10562#L696 assume !(0 == ~M_E~0); 10563#L696-2 assume !(0 == ~T1_E~0); 10845#L701-1 assume !(0 == ~T2_E~0); 10847#L706-1 assume !(0 == ~T3_E~0); 10675#L711-1 assume !(0 == ~T4_E~0); 10460#L716-1 assume !(0 == ~T5_E~0); 10461#L721-1 assume !(0 == ~T6_E~0); 10632#L726-1 assume !(0 == ~E_M~0); 10633#L731-1 assume !(0 == ~E_1~0); 10598#L736-1 assume !(0 == ~E_2~0); 10599#L741-1 assume !(0 == ~E_3~0); 10684#L746-1 assume !(0 == ~E_4~0); 10487#L751-1 assume !(0 == ~E_5~0); 10488#L756-1 assume !(0 == ~E_6~0); 10457#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10277#L346 assume !(1 == ~m_pc~0); 10278#L346-2 is_master_triggered_~__retres1~0#1 := 0; 10502#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10494#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 10495#L861 assume !(0 != activate_threads_~tmp~1#1); 10819#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10312#L365 assume 1 == ~t1_pc~0; 10313#L366 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 10443#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10260#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 10261#L869 assume !(0 != activate_threads_~tmp___0~0#1); 10302#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10732#L384 assume !(1 == ~t2_pc~0); 10726#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 10727#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10698#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 10216#L877 assume !(0 != activate_threads_~tmp___1~0#1); 10217#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10577#L403 assume 1 == ~t3_pc~0; 10462#L404 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 10463#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10186#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 10187#L885 assume !(0 != activate_threads_~tmp___2~0#1); 10570#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10571#L422 assume 1 == ~t4_pc~0; 10211#L423 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 10212#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10365#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 10366#L893 assume !(0 != activate_threads_~tmp___3~0#1); 10657#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10230#L441 assume !(1 == ~t5_pc~0); 10231#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 10815#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10505#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 10506#L901 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 10666#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 10667#L460 assume 1 == ~t6_pc~0; 10171#L461 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 10172#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 10238#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 10686#L909 assume !(0 != activate_threads_~tmp___5~0#1); 10777#L909-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10642#L774 assume 1 == ~M_E~0;~M_E~0 := 2; 10643#L774-2 assume !(1 == ~T1_E~0); 10927#L779-1 assume !(1 == ~T2_E~0); 10926#L784-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 10925#L789-1 assume !(1 == ~T4_E~0); 10924#L794-1 assume !(1 == ~T5_E~0); 10923#L799-1 assume !(1 == ~T6_E~0); 10922#L804-1 assume !(1 == ~E_M~0); 10868#L809-1 assume !(1 == ~E_1~0); 10921#L814-1 assume !(1 == ~E_2~0); 10920#L819-1 assume !(1 == ~E_3~0); 10919#L824-1 assume 1 == ~E_4~0;~E_4~0 := 2; 10918#L829-1 assume !(1 == ~E_5~0); 10917#L834-1 assume !(1 == ~E_6~0); 10444#L839-1 assume { :end_inline_reset_delta_events } true; 10429#L1065-2 [2022-12-13 19:41:34,024 INFO L750 eck$LassoCheckResult]: Loop: 10429#L1065-2 assume !false; 10430#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 10291#L671 assume !false; 10830#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 10858#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 10282#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 10283#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 10888#L582 assume !(0 != eval_~tmp~0#1); 10889#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 10828#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 10829#L696-3 assume 0 == ~M_E~0;~M_E~0 := 1; 10890#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 11313#L701-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 11312#L706-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 11311#L711-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 11310#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 11309#L721-3 assume !(0 == ~T6_E~0); 11308#L726-3 assume !(0 == ~E_M~0); 11307#L731-3 assume 0 == ~E_1~0;~E_1~0 := 1; 11306#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 11305#L741-3 assume 0 == ~E_3~0;~E_3~0 := 1; 11304#L746-3 assume 0 == ~E_4~0;~E_4~0 := 1; 11303#L751-3 assume 0 == ~E_5~0;~E_5~0 := 1; 11302#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 11301#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11300#L346-24 assume 1 == ~m_pc~0; 11298#L347-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 11297#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11296#is_master_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 11295#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 11294#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11293#L365-24 assume !(1 == ~t1_pc~0); 11291#L365-26 is_transmit1_triggered_~__retres1~1#1 := 0; 11290#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11289#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 11288#L869-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 11287#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11286#L384-24 assume 1 == ~t2_pc~0; 11284#L385-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 11283#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11282#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 11281#L877-24 assume !(0 != activate_threads_~tmp___1~0#1); 11280#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11279#L403-24 assume 1 == ~t3_pc~0; 11277#L404-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 11276#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11275#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 11274#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 11273#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 11272#L422-24 assume 1 == ~t4_pc~0; 11270#L423-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 11269#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 11268#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 11267#L893-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 11266#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 11265#L441-24 assume !(1 == ~t5_pc~0); 11264#L441-26 is_transmit5_triggered_~__retres1~5#1 := 0; 11262#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 11261#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 11260#L901-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 11259#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11258#L460-24 assume !(1 == ~t6_pc~0); 11256#L460-26 is_transmit6_triggered_~__retres1~6#1 := 0; 11255#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11254#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 11253#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 11252#L909-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11251#L774-3 assume 1 == ~M_E~0;~M_E~0 := 2; 10878#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 11250#L779-3 assume !(1 == ~T2_E~0); 11249#L784-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 11248#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 11247#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 11246#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 11245#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 10648#L809-3 assume 1 == ~E_1~0;~E_1~0 := 2; 11244#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 11243#L819-3 assume !(1 == ~E_3~0); 11242#L824-3 assume 1 == ~E_4~0;~E_4~0 := 2; 11241#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 11240#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 11239#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 10803#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 10293#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 10387#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 10225#L1084 assume !(0 == start_simulation_~tmp~3#1); 10227#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 10483#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 10195#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 10258#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 10259#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 10326#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 10327#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 10496#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 10429#L1065-2 [2022-12-13 19:41:34,024 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:41:34,024 INFO L85 PathProgramCache]: Analyzing trace with hash -1050737979, now seen corresponding path program 1 times [2022-12-13 19:41:34,024 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:41:34,024 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1984905584] [2022-12-13 19:41:34,024 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:41:34,025 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:41:34,034 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:41:34,074 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:41:34,074 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:41:34,075 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1984905584] [2022-12-13 19:41:34,075 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1984905584] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:41:34,075 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:41:34,075 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:41:34,075 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1614744258] [2022-12-13 19:41:34,075 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:41:34,076 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 19:41:34,076 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:41:34,076 INFO L85 PathProgramCache]: Analyzing trace with hash 573908862, now seen corresponding path program 1 times [2022-12-13 19:41:34,076 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:41:34,077 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [421192000] [2022-12-13 19:41:34,077 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:41:34,077 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:41:34,087 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:41:34,106 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:41:34,106 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:41:34,106 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [421192000] [2022-12-13 19:41:34,107 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [421192000] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:41:34,107 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:41:34,107 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:41:34,107 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [747243476] [2022-12-13 19:41:34,107 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:41:34,107 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 19:41:34,107 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 19:41:34,108 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 19:41:34,108 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 19:41:34,108 INFO L87 Difference]: Start difference. First operand 1179 states and 1755 transitions. cyclomatic complexity: 578 Second operand has 4 states, 4 states have (on average 21.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:41:34,265 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 19:41:34,265 INFO L93 Difference]: Finished difference Result 3143 states and 4595 transitions. [2022-12-13 19:41:34,265 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3143 states and 4595 transitions. [2022-12-13 19:41:34,284 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2928 [2022-12-13 19:41:34,295 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3143 states to 3143 states and 4595 transitions. [2022-12-13 19:41:34,295 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3143 [2022-12-13 19:41:34,297 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3143 [2022-12-13 19:41:34,297 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3143 states and 4595 transitions. [2022-12-13 19:41:34,300 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 19:41:34,300 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3143 states and 4595 transitions. [2022-12-13 19:41:34,303 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3143 states and 4595 transitions. [2022-12-13 19:41:34,343 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3143 to 2955. [2022-12-13 19:41:34,348 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2955 states, 2955 states have (on average 1.4683587140439933) internal successors, (4339), 2954 states have internal predecessors, (4339), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:41:34,356 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2955 states to 2955 states and 4339 transitions. [2022-12-13 19:41:34,356 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2955 states and 4339 transitions. [2022-12-13 19:41:34,357 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 19:41:34,357 INFO L428 stractBuchiCegarLoop]: Abstraction has 2955 states and 4339 transitions. [2022-12-13 19:41:34,357 INFO L335 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2022-12-13 19:41:34,358 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2955 states and 4339 transitions. [2022-12-13 19:41:34,371 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2842 [2022-12-13 19:41:34,371 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 19:41:34,371 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 19:41:34,372 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:41:34,372 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:41:34,373 INFO L748 eck$LassoCheckResult]: Stem: 14856#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 14857#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 15033#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 15034#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 15197#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 14749#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 14750#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 14585#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 14586#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 14559#L507-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 14560#L512-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 14727#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 14890#L696 assume !(0 == ~M_E~0); 14891#L696-2 assume !(0 == ~T1_E~0); 15204#L701-1 assume !(0 == ~T2_E~0); 15206#L706-1 assume !(0 == ~T3_E~0); 15010#L711-1 assume !(0 == ~T4_E~0); 14785#L716-1 assume !(0 == ~T5_E~0); 14786#L721-1 assume !(0 == ~T6_E~0); 14966#L726-1 assume !(0 == ~E_M~0); 14967#L731-1 assume !(0 == ~E_1~0); 14926#L736-1 assume !(0 == ~E_2~0); 14927#L741-1 assume !(0 == ~E_3~0); 15019#L746-1 assume !(0 == ~E_4~0); 14811#L751-1 assume !(0 == ~E_5~0); 14812#L756-1 assume !(0 == ~E_6~0); 14782#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 14608#L346 assume !(1 == ~m_pc~0); 14609#L346-2 is_master_triggered_~__retres1~0#1 := 0; 14827#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 14819#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 14820#L861 assume !(0 != activate_threads_~tmp~1#1); 15175#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14642#L365 assume !(1 == ~t1_pc~0); 14643#L365-2 is_transmit1_triggered_~__retres1~1#1 := 0; 15189#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14591#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 14592#L869 assume !(0 != activate_threads_~tmp___0~0#1); 14632#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15074#L384 assume !(1 == ~t2_pc~0); 15068#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 15069#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 15035#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 14547#L877 assume !(0 != activate_threads_~tmp___1~0#1); 14548#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14905#L403 assume 1 == ~t3_pc~0; 14787#L404 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 14788#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14517#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 14518#L885 assume !(0 != activate_threads_~tmp___2~0#1); 14898#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 14899#L422 assume 1 == ~t4_pc~0; 14542#L423 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 14543#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 14693#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 14694#L893 assume !(0 != activate_threads_~tmp___3~0#1); 14989#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14561#L441 assume !(1 == ~t5_pc~0); 14562#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 15171#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 14830#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 14831#L901 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 14999#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 15000#L460 assume 1 == ~t6_pc~0; 14503#L461 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 14504#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 14569#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 15021#L909 assume !(0 != activate_threads_~tmp___5~0#1); 15127#L909-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14975#L774 assume 1 == ~M_E~0;~M_E~0 := 2; 14976#L774-2 assume !(1 == ~T1_E~0); 17020#L779-1 assume !(1 == ~T2_E~0); 17018#L784-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 15241#L789-1 assume !(1 == ~T4_E~0); 14627#L794-1 assume !(1 == ~T5_E~0); 14628#L799-1 assume !(1 == ~T6_E~0); 15245#L804-1 assume !(1 == ~E_M~0); 15246#L809-1 assume !(1 == ~E_1~0); 14962#L814-1 assume !(1 == ~E_2~0); 14963#L819-1 assume !(1 == ~E_3~0); 16957#L824-1 assume 1 == ~E_4~0;~E_4~0 := 2; 16955#L829-1 assume !(1 == ~E_5~0); 16954#L834-1 assume !(1 == ~E_6~0); 14768#L839-1 assume { :end_inline_reset_delta_events } true; 14754#L1065-2 [2022-12-13 19:41:34,373 INFO L750 eck$LassoCheckResult]: Loop: 14754#L1065-2 assume !false; 14755#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 14621#L671 assume !false; 15185#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 15111#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 14599#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 16918#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 16917#L582 assume !(0 != eval_~tmp~0#1); 16916#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 16915#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 16914#L696-3 assume 0 == ~M_E~0;~M_E~0 := 1; 15239#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 14854#L701-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 14855#L706-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 15215#L711-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 15205#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 15022#L721-3 assume !(0 == ~T6_E~0); 14834#L726-3 assume !(0 == ~E_M~0); 14835#L731-3 assume 0 == ~E_1~0;~E_1~0 := 1; 15014#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 15015#L741-3 assume 0 == ~E_3~0;~E_3~0 := 1; 14778#L746-3 assume 0 == ~E_4~0;~E_4~0 := 1; 14779#L751-3 assume 0 == ~E_5~0;~E_5~0 := 1; 14903#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 14649#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 14650#L346-24 assume !(1 == ~m_pc~0); 14684#L346-26 is_master_triggered_~__retres1~0#1 := 0; 14774#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 14725#is_master_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 14726#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 15145#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14720#L365-24 assume !(1 == ~t1_pc~0); 14721#L365-26 is_transmit1_triggered_~__retres1~1#1 := 0; 15268#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 15201#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 15202#L869-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 17318#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 17317#L384-24 assume 1 == ~t2_pc~0; 17315#L385-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 17314#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17313#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 17312#L877-24 assume !(0 != activate_threads_~tmp___1~0#1); 17311#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14813#L403-24 assume 1 == ~t3_pc~0; 14814#L404-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 14858#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14859#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 14956#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 14957#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 16171#L422-24 assume !(1 == ~t4_pc~0); 16172#L422-26 is_transmit4_triggered_~__retres1~4#1 := 0; 17085#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 17084#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 17083#L893-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 17082#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 17081#L441-24 assume 1 == ~t5_pc~0; 17079#L442-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 17078#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 17077#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 17076#L901-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 17075#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 17074#L460-24 assume !(1 == ~t6_pc~0); 17072#L460-26 is_transmit6_triggered_~__retres1~6#1 := 0; 17071#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 17070#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 17069#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 17068#L909-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 17067#L774-3 assume 1 == ~M_E~0;~M_E~0 := 2; 15540#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 17066#L779-3 assume !(1 == ~T2_E~0); 17065#L784-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 17064#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 17063#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 17062#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 17061#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 15525#L809-3 assume 1 == ~E_1~0;~E_1~0 := 2; 17060#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 17059#L819-3 assume !(1 == ~E_3~0); 17057#L824-3 assume 1 == ~E_4~0;~E_4~0 := 2; 17055#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 17053#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 17051#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 15375#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 15367#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 15345#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 15335#L1084 assume !(0 == start_simulation_~tmp~3#1); 15164#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 14807#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 14526#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 14589#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 14590#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 14655#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 14656#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 14821#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 14754#L1065-2 [2022-12-13 19:41:34,373 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:41:34,373 INFO L85 PathProgramCache]: Analyzing trace with hash 1143388102, now seen corresponding path program 1 times [2022-12-13 19:41:34,374 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:41:34,374 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [878272642] [2022-12-13 19:41:34,374 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:41:34,374 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:41:34,383 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:41:34,428 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:41:34,428 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:41:34,428 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [878272642] [2022-12-13 19:41:34,428 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [878272642] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:41:34,428 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:41:34,428 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:41:34,429 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [52968375] [2022-12-13 19:41:34,429 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:41:34,429 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 19:41:34,429 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:41:34,429 INFO L85 PathProgramCache]: Analyzing trace with hash 1794988415, now seen corresponding path program 1 times [2022-12-13 19:41:34,430 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:41:34,430 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [868790404] [2022-12-13 19:41:34,430 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:41:34,430 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:41:34,440 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:41:34,467 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:41:34,467 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:41:34,467 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [868790404] [2022-12-13 19:41:34,467 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [868790404] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:41:34,468 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:41:34,468 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:41:34,468 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [886535283] [2022-12-13 19:41:34,468 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:41:34,468 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 19:41:34,468 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 19:41:34,469 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 19:41:34,469 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 19:41:34,469 INFO L87 Difference]: Start difference. First operand 2955 states and 4339 transitions. cyclomatic complexity: 1388 Second operand has 4 states, 4 states have (on average 21.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:41:34,646 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 19:41:34,646 INFO L93 Difference]: Finished difference Result 8082 states and 11722 transitions. [2022-12-13 19:41:34,646 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 8082 states and 11722 transitions. [2022-12-13 19:41:34,675 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 7720 [2022-12-13 19:41:34,699 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 8082 states to 8082 states and 11722 transitions. [2022-12-13 19:41:34,699 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8082 [2022-12-13 19:41:34,705 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8082 [2022-12-13 19:41:34,705 INFO L73 IsDeterministic]: Start isDeterministic. Operand 8082 states and 11722 transitions. [2022-12-13 19:41:34,712 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 19:41:34,712 INFO L218 hiAutomatonCegarLoop]: Abstraction has 8082 states and 11722 transitions. [2022-12-13 19:41:34,718 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8082 states and 11722 transitions. [2022-12-13 19:41:34,823 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8082 to 7678. [2022-12-13 19:41:34,832 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7678 states, 7678 states have (on average 1.456629330554832) internal successors, (11184), 7677 states have internal predecessors, (11184), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:41:34,846 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7678 states to 7678 states and 11184 transitions. [2022-12-13 19:41:34,846 INFO L240 hiAutomatonCegarLoop]: Abstraction has 7678 states and 11184 transitions. [2022-12-13 19:41:34,847 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 19:41:34,847 INFO L428 stractBuchiCegarLoop]: Abstraction has 7678 states and 11184 transitions. [2022-12-13 19:41:34,847 INFO L335 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2022-12-13 19:41:34,848 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7678 states and 11184 transitions. [2022-12-13 19:41:34,873 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 7546 [2022-12-13 19:41:34,873 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 19:41:34,873 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 19:41:34,874 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:41:34,874 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:41:34,874 INFO L748 eck$LassoCheckResult]: Stem: 25901#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 25902#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 26076#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 26077#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 26236#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 25793#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 25794#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 25631#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 25632#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 25604#L507-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 25605#L512-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 25771#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 25935#L696 assume !(0 == ~M_E~0); 25936#L696-2 assume !(0 == ~T1_E~0); 26243#L701-1 assume !(0 == ~T2_E~0); 26245#L706-1 assume !(0 == ~T3_E~0); 26049#L711-1 assume !(0 == ~T4_E~0); 25828#L716-1 assume !(0 == ~T5_E~0); 25829#L721-1 assume !(0 == ~T6_E~0); 26008#L726-1 assume !(0 == ~E_M~0); 26009#L731-1 assume !(0 == ~E_1~0); 25971#L736-1 assume !(0 == ~E_2~0); 25972#L741-1 assume !(0 == ~E_3~0); 26058#L746-1 assume !(0 == ~E_4~0); 25855#L751-1 assume !(0 == ~E_5~0); 25856#L756-1 assume !(0 == ~E_6~0); 25825#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 25653#L346 assume !(1 == ~m_pc~0); 25654#L346-2 is_master_triggered_~__retres1~0#1 := 0; 25870#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 25862#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 25863#L861 assume !(0 != activate_threads_~tmp~1#1); 26210#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 25686#L365 assume !(1 == ~t1_pc~0); 25687#L365-2 is_transmit1_triggered_~__retres1~1#1 := 0; 26223#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 25637#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 25638#L869 assume !(0 != activate_threads_~tmp___0~0#1); 25676#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 26112#L384 assume !(1 == ~t2_pc~0); 26106#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 26107#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 26078#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 25592#L877 assume !(0 != activate_threads_~tmp___1~0#1); 25593#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 25950#L403 assume !(1 == ~t3_pc~0); 25951#L403-2 is_transmit3_triggered_~__retres1~3#1 := 0; 26145#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 25564#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 25565#L885 assume !(0 != activate_threads_~tmp___2~0#1); 25943#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 25944#L422 assume 1 == ~t4_pc~0; 25587#L423 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 25588#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 25737#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 25738#L893 assume !(0 != activate_threads_~tmp___3~0#1); 26032#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 25606#L441 assume !(1 == ~t5_pc~0); 25607#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 26205#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 25873#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 25874#L901 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 26040#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 26041#L460 assume 1 == ~t6_pc~0; 25550#L461 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 25551#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 25614#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 26060#L909 assume !(0 != activate_threads_~tmp___5~0#1); 26162#L909-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 26018#L774 assume 1 == ~M_E~0;~M_E~0 := 2; 26019#L774-2 assume !(1 == ~T1_E~0); 26181#L779-1 assume !(1 == ~T2_E~0); 26182#L784-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 26278#L789-1 assume !(1 == ~T4_E~0); 25671#L794-1 assume !(1 == ~T5_E~0); 25672#L799-1 assume !(1 == ~T6_E~0); 26283#L804-1 assume !(1 == ~E_M~0); 26284#L809-1 assume !(1 == ~E_1~0); 26002#L814-1 assume !(1 == ~E_2~0); 26003#L819-1 assume !(1 == ~E_3~0); 26068#L824-1 assume 1 == ~E_4~0;~E_4~0 := 2; 26069#L829-1 assume !(1 == ~E_5~0); 26170#L834-1 assume !(1 == ~E_6~0); 25810#L839-1 assume { :end_inline_reset_delta_events } true; 25811#L1065-2 [2022-12-13 19:41:34,874 INFO L750 eck$LassoCheckResult]: Loop: 25811#L1065-2 assume !false; 32037#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 32410#L671 assume !false; 32409#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 32407#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 29417#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 29418#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 29404#L582 assume !(0 != eval_~tmp~0#1); 25752#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 25753#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 25842#L696-3 assume 0 == ~M_E~0;~M_E~0 := 1; 25843#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 25899#L701-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 25900#L706-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 26255#L711-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 26244#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 26061#L721-3 assume !(0 == ~T6_E~0); 25877#L726-3 assume !(0 == ~E_M~0); 25878#L731-3 assume 0 == ~E_1~0;~E_1~0 := 1; 26053#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 26054#L741-3 assume 0 == ~E_3~0;~E_3~0 := 1; 25821#L746-3 assume 0 == ~E_4~0;~E_4~0 := 1; 25822#L751-3 assume 0 == ~E_5~0;~E_5~0 := 1; 25948#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 25693#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 25694#L346-24 assume !(1 == ~m_pc~0); 25728#L346-26 is_master_triggered_~__retres1~0#1 := 0; 25817#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 25769#is_master_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 25770#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 26179#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 25764#L365-24 assume !(1 == ~t1_pc~0); 25765#L365-26 is_transmit1_triggered_~__retres1~1#1 := 0; 26304#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 26241#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 26137#L869-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 26138#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 25713#L384-24 assume !(1 == ~t2_pc~0); 25714#L384-26 is_transmit2_triggered_~__retres1~2#1 := 0; 25734#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 26300#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 26045#L877-24 assume !(0 != activate_threads_~tmp___1~0#1); 25744#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 25745#L403-24 assume !(1 == ~t3_pc~0); 25857#L403-26 is_transmit3_triggered_~__retres1~3#1 := 0; 25903#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 25904#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 25996#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 25997#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 25795#L422-24 assume !(1 == ~t4_pc~0); 25796#L422-26 is_transmit4_triggered_~__retres1~4#1 := 0; 25750#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 25751#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 26213#L893-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 26190#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 25812#L441-24 assume 1 == ~t5_pc~0; 25813#L442-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 26026#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 25967#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 25677#L901-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 25678#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 26113#L460-24 assume !(1 == ~t6_pc~0); 26114#L460-26 is_transmit6_triggered_~__retres1~6#1 := 0; 26183#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 25853#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 25854#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 26108#L909-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 26109#L774-3 assume 1 == ~M_E~0;~M_E~0 := 2; 26042#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 25876#L779-3 assume !(1 == ~T2_E~0); 25590#L784-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 25591#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 26324#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 32507#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 32506#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 32504#L809-3 assume 1 == ~E_1~0;~E_1~0 := 2; 32503#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 32502#L819-3 assume !(1 == ~E_3~0); 32501#L824-3 assume 1 == ~E_4~0;~E_4~0 := 2; 32500#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 32499#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 32498#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 32496#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 32490#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 32489#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 32487#L1084 assume !(0 == start_simulation_~tmp~3#1); 32486#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 32481#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 32478#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 32477#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 32476#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 32475#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 32474#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 32473#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 25811#L1065-2 [2022-12-13 19:41:34,875 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:41:34,875 INFO L85 PathProgramCache]: Analyzing trace with hash 186459719, now seen corresponding path program 1 times [2022-12-13 19:41:34,875 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:41:34,875 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1659178493] [2022-12-13 19:41:34,875 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:41:34,875 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:41:34,884 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:41:34,910 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:41:34,910 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:41:34,910 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1659178493] [2022-12-13 19:41:34,910 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1659178493] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:41:34,910 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:41:34,910 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-12-13 19:41:34,910 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [715833528] [2022-12-13 19:41:34,911 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:41:34,911 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 19:41:34,911 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:41:34,911 INFO L85 PathProgramCache]: Analyzing trace with hash -65585471, now seen corresponding path program 1 times [2022-12-13 19:41:34,911 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:41:34,911 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [526708094] [2022-12-13 19:41:34,911 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:41:34,912 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:41:34,920 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:41:34,961 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:41:34,961 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:41:34,961 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [526708094] [2022-12-13 19:41:34,961 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [526708094] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:41:34,961 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:41:34,961 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:41:34,961 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [402918545] [2022-12-13 19:41:34,961 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:41:34,962 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 19:41:34,962 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 19:41:34,962 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 19:41:34,962 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 19:41:34,962 INFO L87 Difference]: Start difference. First operand 7678 states and 11184 transitions. cyclomatic complexity: 3514 Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 2 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:41:35,069 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 19:41:35,069 INFO L93 Difference]: Finished difference Result 14259 states and 20702 transitions. [2022-12-13 19:41:35,069 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 14259 states and 20702 transitions. [2022-12-13 19:41:35,129 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 14062 [2022-12-13 19:41:35,226 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 14259 states to 14259 states and 20702 transitions. [2022-12-13 19:41:35,226 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 14259 [2022-12-13 19:41:35,234 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 14259 [2022-12-13 19:41:35,235 INFO L73 IsDeterministic]: Start isDeterministic. Operand 14259 states and 20702 transitions. [2022-12-13 19:41:35,247 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 19:41:35,248 INFO L218 hiAutomatonCegarLoop]: Abstraction has 14259 states and 20702 transitions. [2022-12-13 19:41:35,260 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 14259 states and 20702 transitions. [2022-12-13 19:41:35,409 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 14259 to 14223. [2022-12-13 19:41:35,428 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 14223 states, 14223 states have (on average 1.452998664135555) internal successors, (20666), 14222 states have internal predecessors, (20666), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:41:35,454 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14223 states to 14223 states and 20666 transitions. [2022-12-13 19:41:35,455 INFO L240 hiAutomatonCegarLoop]: Abstraction has 14223 states and 20666 transitions. [2022-12-13 19:41:35,455 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 19:41:35,456 INFO L428 stractBuchiCegarLoop]: Abstraction has 14223 states and 20666 transitions. [2022-12-13 19:41:35,456 INFO L335 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2022-12-13 19:41:35,456 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 14223 states and 20666 transitions. [2022-12-13 19:41:35,525 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 14026 [2022-12-13 19:41:35,525 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 19:41:35,525 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 19:41:35,526 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:41:35,526 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:41:35,527 INFO L748 eck$LassoCheckResult]: Stem: 47840#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 47841#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 48024#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 48025#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 48200#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 47735#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 47736#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 47569#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 47570#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 47543#L507-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 47544#L512-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 47713#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 47876#L696 assume !(0 == ~M_E~0); 47877#L696-2 assume !(0 == ~T1_E~0); 48209#L701-1 assume !(0 == ~T2_E~0); 48211#L706-1 assume !(0 == ~T3_E~0); 47997#L711-1 assume !(0 == ~T4_E~0); 47768#L716-1 assume !(0 == ~T5_E~0); 47769#L721-1 assume !(0 == ~T6_E~0); 47952#L726-1 assume !(0 == ~E_M~0); 47953#L731-1 assume !(0 == ~E_1~0); 47914#L736-1 assume !(0 == ~E_2~0); 47915#L741-1 assume !(0 == ~E_3~0); 48005#L746-1 assume !(0 == ~E_4~0); 47796#L751-1 assume !(0 == ~E_5~0); 47797#L756-1 assume !(0 == ~E_6~0); 47765#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 47591#L346 assume !(1 == ~m_pc~0); 47592#L346-2 is_master_triggered_~__retres1~0#1 := 0; 47811#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 47803#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 47804#L861 assume !(0 != activate_threads_~tmp~1#1); 48167#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 47624#L365 assume !(1 == ~t1_pc~0); 47625#L365-2 is_transmit1_triggered_~__retres1~1#1 := 0; 48184#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 47575#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 47576#L869 assume !(0 != activate_threads_~tmp___0~0#1); 47614#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 48062#L384 assume !(1 == ~t2_pc~0); 48055#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 48056#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 48026#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 47532#L877 assume !(0 != activate_threads_~tmp___1~0#1); 47533#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 47892#L403 assume !(1 == ~t3_pc~0); 47893#L403-2 is_transmit3_triggered_~__retres1~3#1 := 0; 48101#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 47507#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 47508#L885 assume !(0 != activate_threads_~tmp___2~0#1); 47885#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 47886#L422 assume !(1 == ~t4_pc~0); 48022#L422-2 is_transmit4_triggered_~__retres1~4#1 := 0; 48023#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 47675#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 47676#L893 assume !(0 != activate_threads_~tmp___3~0#1); 47979#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 47545#L441 assume !(1 == ~t5_pc~0); 47546#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 48162#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 47814#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 47815#L901 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 47987#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 47988#L460 assume 1 == ~t6_pc~0; 47494#L461 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 47495#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 47553#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 48007#L909 assume !(0 != activate_threads_~tmp___5~0#1); 48119#L909-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 47963#L774 assume 1 == ~M_E~0;~M_E~0 := 2; 47964#L774-2 assume !(1 == ~T1_E~0); 48138#L779-1 assume !(1 == ~T2_E~0); 47859#L784-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 47860#L789-1 assume !(1 == ~T4_E~0); 47609#L794-1 assume !(1 == ~T5_E~0); 47610#L799-1 assume !(1 == ~T6_E~0); 48257#L804-1 assume !(1 == ~E_M~0); 48258#L809-1 assume !(1 == ~E_1~0); 47947#L814-1 assume !(1 == ~E_2~0); 47511#L819-1 assume !(1 == ~E_3~0); 47512#L824-1 assume 1 == ~E_4~0;~E_4~0 := 2; 48015#L829-1 assume !(1 == ~E_5~0); 48127#L834-1 assume !(1 == ~E_6~0); 47751#L839-1 assume { :end_inline_reset_delta_events } true; 47752#L1065-2 [2022-12-13 19:41:35,527 INFO L750 eck$LassoCheckResult]: Loop: 47752#L1065-2 assume !false; 60640#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 47786#L671 assume !false; 48237#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 48102#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 47582#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 47595#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 48048#L582 assume !(0 != eval_~tmp~0#1); 48296#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 61459#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 61457#L696-3 assume 0 == ~M_E~0;~M_E~0 := 1; 61455#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 61453#L701-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 61451#L706-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 61449#L711-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 61447#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 61445#L721-3 assume !(0 == ~T6_E~0); 61443#L726-3 assume !(0 == ~E_M~0); 61441#L731-3 assume 0 == ~E_1~0;~E_1~0 := 1; 61440#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 61437#L741-3 assume 0 == ~E_3~0;~E_3~0 := 1; 61435#L746-3 assume 0 == ~E_4~0;~E_4~0 := 1; 61433#L751-3 assume 0 == ~E_5~0;~E_5~0 := 1; 61431#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 61429#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 61427#L346-24 assume !(1 == ~m_pc~0); 61426#L346-26 is_master_triggered_~__retres1~0#1 := 0; 61424#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 61422#is_master_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 61420#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 61418#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 61416#L365-24 assume !(1 == ~t1_pc~0); 61413#L365-26 is_transmit1_triggered_~__retres1~1#1 := 0; 61411#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 61409#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 61407#L869-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 61405#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 61403#L384-24 assume 1 == ~t2_pc~0; 61399#L385-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 61397#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 61395#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 61393#L877-24 assume !(0 != activate_threads_~tmp___1~0#1); 61391#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 61389#L403-24 assume !(1 == ~t3_pc~0); 61386#L403-26 is_transmit3_triggered_~__retres1~3#1 := 0; 61312#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 61309#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 61283#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 61282#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 47737#L422-24 assume !(1 == ~t4_pc~0); 47738#L422-26 is_transmit4_triggered_~__retres1~4#1 := 0; 47690#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 47691#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 48171#L893-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 48146#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 47753#L441-24 assume 1 == ~t5_pc~0; 47754#L442-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 47972#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 47910#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 47615#L901-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 47616#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 61507#L460-24 assume !(1 == ~t6_pc~0); 61504#L460-26 is_transmit6_triggered_~__retres1~6#1 := 0; 61502#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 61500#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 61498#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 61496#L909-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 61494#L774-3 assume 1 == ~M_E~0;~M_E~0 := 2; 59347#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 61491#L779-3 assume !(1 == ~T2_E~0); 61489#L784-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 61487#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 61485#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 61483#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 61481#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 59332#L809-3 assume 1 == ~E_1~0;~E_1~0 := 2; 61480#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 61479#L819-3 assume !(1 == ~E_3~0); 61478#L824-3 assume 1 == ~E_4~0;~E_4~0 := 2; 61477#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 61476#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 61475#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 61473#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 47700#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 47701#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 47978#L1084 assume !(0 == start_simulation_~tmp~3#1); 48156#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 60706#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 60703#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 60701#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 60692#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 60688#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 60644#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 60643#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 47752#L1065-2 [2022-12-13 19:41:35,527 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:41:35,527 INFO L85 PathProgramCache]: Analyzing trace with hash -1390098040, now seen corresponding path program 1 times [2022-12-13 19:41:35,528 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:41:35,528 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1418766178] [2022-12-13 19:41:35,528 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:41:35,528 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:41:35,539 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:41:35,614 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:41:35,614 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:41:35,614 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1418766178] [2022-12-13 19:41:35,614 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1418766178] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:41:35,615 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:41:35,615 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-12-13 19:41:35,615 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1058890451] [2022-12-13 19:41:35,615 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:41:35,615 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 19:41:35,616 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:41:35,616 INFO L85 PathProgramCache]: Analyzing trace with hash -305852800, now seen corresponding path program 1 times [2022-12-13 19:41:35,616 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:41:35,616 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1170330423] [2022-12-13 19:41:35,617 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:41:35,617 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:41:35,626 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:41:35,653 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:41:35,654 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:41:35,654 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1170330423] [2022-12-13 19:41:35,654 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1170330423] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:41:35,654 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:41:35,654 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:41:35,654 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1462540654] [2022-12-13 19:41:35,654 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:41:35,654 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 19:41:35,655 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 19:41:35,655 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-12-13 19:41:35,655 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-12-13 19:41:35,655 INFO L87 Difference]: Start difference. First operand 14223 states and 20666 transitions. cyclomatic complexity: 6459 Second operand has 5 states, 5 states have (on average 16.8) internal successors, (84), 5 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:41:35,964 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 19:41:35,965 INFO L93 Difference]: Finished difference Result 34082 states and 49999 transitions. [2022-12-13 19:41:35,965 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 34082 states and 49999 transitions. [2022-12-13 19:41:36,171 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 33628 [2022-12-13 19:41:36,240 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 34082 states to 34082 states and 49999 transitions. [2022-12-13 19:41:36,240 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 34082 [2022-12-13 19:41:36,253 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 34082 [2022-12-13 19:41:36,253 INFO L73 IsDeterministic]: Start isDeterministic. Operand 34082 states and 49999 transitions. [2022-12-13 19:41:36,269 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 19:41:36,269 INFO L218 hiAutomatonCegarLoop]: Abstraction has 34082 states and 49999 transitions. [2022-12-13 19:41:36,296 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 34082 states and 49999 transitions. [2022-12-13 19:41:36,496 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 34082 to 14832. [2022-12-13 19:41:36,511 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 14832 states, 14832 states have (on average 1.434398597626753) internal successors, (21275), 14831 states have internal predecessors, (21275), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:41:36,547 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14832 states to 14832 states and 21275 transitions. [2022-12-13 19:41:36,547 INFO L240 hiAutomatonCegarLoop]: Abstraction has 14832 states and 21275 transitions. [2022-12-13 19:41:36,548 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-12-13 19:41:36,548 INFO L428 stractBuchiCegarLoop]: Abstraction has 14832 states and 21275 transitions. [2022-12-13 19:41:36,548 INFO L335 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2022-12-13 19:41:36,548 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 14832 states and 21275 transitions. [2022-12-13 19:41:36,587 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 14632 [2022-12-13 19:41:36,587 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 19:41:36,587 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 19:41:36,588 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:41:36,588 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:41:36,588 INFO L748 eck$LassoCheckResult]: Stem: 96168#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 96169#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 96364#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 96365#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 96550#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 96052#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 96053#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 95891#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 95892#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 95861#L507-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 95862#L512-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 96030#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 96207#L696 assume !(0 == ~M_E~0); 96208#L696-2 assume !(0 == ~T1_E~0); 96563#L701-1 assume !(0 == ~T2_E~0); 96565#L706-1 assume !(0 == ~T3_E~0); 96336#L711-1 assume !(0 == ~T4_E~0); 96086#L716-1 assume !(0 == ~T5_E~0); 96087#L721-1 assume !(0 == ~T6_E~0); 96286#L726-1 assume !(0 == ~E_M~0); 96287#L731-1 assume !(0 == ~E_1~0); 96245#L736-1 assume !(0 == ~E_2~0); 96246#L741-1 assume !(0 == ~E_3~0); 96345#L746-1 assume !(0 == ~E_4~0); 96116#L751-1 assume !(0 == ~E_5~0); 96117#L756-1 assume !(0 == ~E_6~0); 96083#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 95911#L346 assume !(1 == ~m_pc~0); 95912#L346-2 is_master_triggered_~__retres1~0#1 := 0; 96133#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 96123#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 96124#L861 assume !(0 != activate_threads_~tmp~1#1); 96514#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 95945#L365 assume !(1 == ~t1_pc~0); 95946#L365-2 is_transmit1_triggered_~__retres1~1#1 := 0; 96537#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 95897#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 95898#L869 assume !(0 != activate_threads_~tmp___0~0#1); 95934#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 96405#L384 assume !(1 == ~t2_pc~0); 96402#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 96403#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 96370#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 95852#L877 assume !(0 != activate_threads_~tmp___1~0#1); 95853#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 96224#L403 assume !(1 == ~t3_pc~0); 96225#L403-2 is_transmit3_triggered_~__retres1~3#1 := 0; 96444#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 95825#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 95826#L885 assume !(0 != activate_threads_~tmp___2~0#1); 96216#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 96217#L422 assume !(1 == ~t4_pc~0); 96362#L422-2 is_transmit4_triggered_~__retres1~4#1 := 0; 96363#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 95995#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 95996#L893 assume !(0 != activate_threads_~tmp___3~0#1); 96314#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 95863#L441 assume !(1 == ~t5_pc~0); 95864#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 96510#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 96643#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 96691#L901 assume !(0 != activate_threads_~tmp___4~0#1); 96326#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 96327#L460 assume 1 == ~t6_pc~0; 95814#L461 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 95815#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 95873#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 96347#L909 assume !(0 != activate_threads_~tmp___5~0#1); 96464#L909-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 96298#L774 assume 1 == ~M_E~0;~M_E~0 := 2; 96299#L774-2 assume !(1 == ~T1_E~0); 110215#L779-1 assume !(1 == ~T2_E~0); 110213#L784-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 110205#L789-1 assume !(1 == ~T4_E~0); 110203#L794-1 assume !(1 == ~T5_E~0); 110201#L799-1 assume !(1 == ~T6_E~0); 110199#L804-1 assume !(1 == ~E_M~0); 96624#L809-1 assume !(1 == ~E_1~0); 110196#L814-1 assume !(1 == ~E_2~0); 110195#L819-1 assume !(1 == ~E_3~0); 110194#L824-1 assume 1 == ~E_4~0;~E_4~0 := 2; 110193#L829-1 assume !(1 == ~E_5~0); 110192#L834-1 assume !(1 == ~E_6~0); 96071#L839-1 assume { :end_inline_reset_delta_events } true; 96061#L1065-2 [2022-12-13 19:41:36,588 INFO L750 eck$LassoCheckResult]: Loop: 96061#L1065-2 assume !false; 96062#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 95922#L671 assume !false; 96530#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 96445#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 95900#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 95916#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 96393#L582 assume !(0 != eval_~tmp~0#1); 96011#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 96012#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 96102#L696-3 assume 0 == ~M_E~0;~M_E~0 := 1; 96103#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 96164#L701-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 96165#L706-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 96578#L711-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 96562#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 96348#L721-3 assume !(0 == ~T6_E~0); 96139#L726-3 assume !(0 == ~E_M~0); 96140#L731-3 assume 0 == ~E_1~0;~E_1~0 := 1; 96340#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 96341#L741-3 assume 0 == ~E_3~0;~E_3~0 := 1; 96079#L746-3 assume 0 == ~E_4~0;~E_4~0 := 1; 96080#L751-3 assume 0 == ~E_5~0;~E_5~0 := 1; 96218#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 95951#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 95952#L346-24 assume !(1 == ~m_pc~0); 95985#L346-26 is_master_triggered_~__retres1~0#1 := 0; 96072#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 96028#is_master_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 96029#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 96482#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 96023#L365-24 assume !(1 == ~t1_pc~0); 96024#L365-26 is_transmit1_triggered_~__retres1~1#1 := 0; 96662#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 96555#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 96431#L869-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 96432#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 96614#L384-24 assume 1 == ~t2_pc~0; 96693#L385-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 95992#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 96654#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 110628#L877-24 assume !(0 != activate_threads_~tmp___1~0#1); 110627#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 110626#L403-24 assume !(1 == ~t3_pc~0); 110625#L403-26 is_transmit3_triggered_~__retres1~3#1 := 0; 110624#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 110623#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 110622#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 110621#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 110620#L422-24 assume !(1 == ~t4_pc~0); 110619#L422-26 is_transmit4_triggered_~__retres1~4#1 := 0; 96009#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 96010#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 110618#L893-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 96492#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 96493#L441-24 assume 1 == ~t5_pc~0; 96406#L442-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 96306#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 96240#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 96241#L901-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 95936#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 96407#L460-24 assume 1 == ~t6_pc~0; 96409#L461-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 96485#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 96682#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 110606#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 110605#L909-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 110604#L774-3 assume 1 == ~M_E~0;~M_E~0 := 2; 110385#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 110603#L779-3 assume !(1 == ~T2_E~0); 95848#L784-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 95849#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 95829#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 95830#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 95944#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 96305#L809-3 assume 1 == ~E_1~0;~E_1~0 := 2; 95942#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 95943#L819-3 assume !(1 == ~E_3~0); 96093#L824-3 assume 1 == ~E_4~0;~E_4~0 := 2; 96077#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 96078#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 95926#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 95927#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 95924#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 96019#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 95858#L1084 assume !(0 == start_simulation_~tmp~3#1); 95860#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 96531#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 110549#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 110546#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 110545#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 110352#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 96538#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 96125#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 96061#L1065-2 [2022-12-13 19:41:36,589 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:41:36,589 INFO L85 PathProgramCache]: Analyzing trace with hash 1099430922, now seen corresponding path program 1 times [2022-12-13 19:41:36,589 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:41:36,589 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1913024954] [2022-12-13 19:41:36,589 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:41:36,589 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:41:36,597 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:41:36,633 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:41:36,633 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:41:36,633 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1913024954] [2022-12-13 19:41:36,633 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1913024954] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:41:36,634 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:41:36,634 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:41:36,634 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [325065350] [2022-12-13 19:41:36,634 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:41:36,634 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 19:41:36,634 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:41:36,635 INFO L85 PathProgramCache]: Analyzing trace with hash 1270704959, now seen corresponding path program 1 times [2022-12-13 19:41:36,635 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:41:36,635 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1399620153] [2022-12-13 19:41:36,635 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:41:36,635 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:41:36,642 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:41:36,660 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:41:36,660 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:41:36,660 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1399620153] [2022-12-13 19:41:36,661 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1399620153] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:41:36,661 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:41:36,661 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:41:36,661 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1122285211] [2022-12-13 19:41:36,661 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:41:36,661 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 19:41:36,661 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 19:41:36,661 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 19:41:36,661 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 19:41:36,662 INFO L87 Difference]: Start difference. First operand 14832 states and 21275 transitions. cyclomatic complexity: 6459 Second operand has 4 states, 4 states have (on average 21.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:41:36,923 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 19:41:36,923 INFO L93 Difference]: Finished difference Result 41853 states and 59428 transitions. [2022-12-13 19:41:36,924 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 41853 states and 59428 transitions. [2022-12-13 19:41:37,091 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 40462 [2022-12-13 19:41:37,209 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 41853 states to 41853 states and 59428 transitions. [2022-12-13 19:41:37,209 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 41853 [2022-12-13 19:41:37,226 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 41853 [2022-12-13 19:41:37,226 INFO L73 IsDeterministic]: Start isDeterministic. Operand 41853 states and 59428 transitions. [2022-12-13 19:41:37,266 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 19:41:37,266 INFO L218 hiAutomatonCegarLoop]: Abstraction has 41853 states and 59428 transitions. [2022-12-13 19:41:37,291 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 41853 states and 59428 transitions. [2022-12-13 19:41:37,605 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 41853 to 40669. [2022-12-13 19:41:37,645 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 40669 states, 40669 states have (on average 1.4247215323710936) internal successors, (57942), 40668 states have internal predecessors, (57942), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:41:37,697 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 40669 states to 40669 states and 57942 transitions. [2022-12-13 19:41:37,697 INFO L240 hiAutomatonCegarLoop]: Abstraction has 40669 states and 57942 transitions. [2022-12-13 19:41:37,697 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 19:41:37,698 INFO L428 stractBuchiCegarLoop]: Abstraction has 40669 states and 57942 transitions. [2022-12-13 19:41:37,698 INFO L335 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2022-12-13 19:41:37,698 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 40669 states and 57942 transitions. [2022-12-13 19:41:37,846 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 40318 [2022-12-13 19:41:37,846 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 19:41:37,846 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 19:41:37,848 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:41:37,848 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:41:37,848 INFO L748 eck$LassoCheckResult]: Stem: 152859#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 152860#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 153040#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 153041#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 153226#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 152750#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 152751#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 152583#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 152584#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 152554#L507-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 152555#L512-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 152728#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 152893#L696 assume !(0 == ~M_E~0); 152894#L696-2 assume !(0 == ~T1_E~0); 153234#L701-1 assume !(0 == ~T2_E~0); 153235#L706-1 assume !(0 == ~T3_E~0); 153006#L711-1 assume !(0 == ~T4_E~0); 152785#L716-1 assume !(0 == ~T5_E~0); 152786#L721-1 assume !(0 == ~T6_E~0); 152964#L726-1 assume !(0 == ~E_M~0); 152965#L731-1 assume !(0 == ~E_1~0); 152928#L736-1 assume !(0 == ~E_2~0); 152929#L741-1 assume !(0 == ~E_3~0); 153017#L746-1 assume !(0 == ~E_4~0); 152809#L751-1 assume !(0 == ~E_5~0); 152810#L756-1 assume !(0 == ~E_6~0); 152782#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 152603#L346 assume !(1 == ~m_pc~0); 152604#L346-2 is_master_triggered_~__retres1~0#1 := 0; 152828#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 152818#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 152819#L861 assume !(0 != activate_threads_~tmp~1#1); 153195#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 152638#L365 assume !(1 == ~t1_pc~0); 152639#L365-2 is_transmit1_triggered_~__retres1~1#1 := 0; 153211#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 152589#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 152590#L869 assume !(0 != activate_threads_~tmp___0~0#1); 152626#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 153083#L384 assume !(1 == ~t2_pc~0); 153080#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 153081#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 153046#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 152544#L877 assume !(0 != activate_threads_~tmp___1~0#1); 152545#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 152908#L403 assume !(1 == ~t3_pc~0); 152909#L403-2 is_transmit3_triggered_~__retres1~3#1 := 0; 153121#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 152517#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 152518#L885 assume !(0 != activate_threads_~tmp___2~0#1); 152899#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 152900#L422 assume !(1 == ~t4_pc~0); 153038#L422-2 is_transmit4_triggered_~__retres1~4#1 := 0; 153039#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 152691#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 152692#L893 assume !(0 != activate_threads_~tmp___3~0#1); 152987#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 152556#L441 assume !(1 == ~t5_pc~0); 152557#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 153190#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 152830#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 152831#L901 assume !(0 != activate_threads_~tmp___4~0#1); 152997#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 152998#L460 assume !(1 == ~t6_pc~0); 153147#L460-2 is_transmit6_triggered_~__retres1~6#1 := 0; 152565#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 152566#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 153020#L909 assume !(0 != activate_threads_~tmp___5~0#1); 153142#L909-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 152972#L774 assume 1 == ~M_E~0;~M_E~0 := 2; 152973#L774-2 assume !(1 == ~T1_E~0); 153280#L779-1 assume !(1 == ~T2_E~0); 152875#L784-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 152876#L789-1 assume !(1 == ~T4_E~0); 152619#L794-1 assume !(1 == ~T5_E~0); 152620#L799-1 assume !(1 == ~T6_E~0); 153287#L804-1 assume !(1 == ~E_M~0); 153288#L809-1 assume !(1 == ~E_1~0); 152959#L814-1 assume !(1 == ~E_2~0); 152960#L819-1 assume !(1 == ~E_3~0); 153028#L824-1 assume 1 == ~E_4~0;~E_4~0 := 2; 153029#L829-1 assume !(1 == ~E_5~0); 153150#L834-1 assume !(1 == ~E_6~0); 153151#L839-1 assume { :end_inline_reset_delta_events } true; 157795#L1065-2 [2022-12-13 19:41:37,848 INFO L750 eck$LassoCheckResult]: Loop: 157795#L1065-2 assume !false; 157793#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 157789#L671 assume !false; 157788#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 157611#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 157604#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 157602#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 157598#L582 assume !(0 != eval_~tmp~0#1); 157600#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 159293#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 159290#L696-3 assume 0 == ~M_E~0;~M_E~0 := 1; 159286#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 159283#L701-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 159280#L706-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 159277#L711-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 159275#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 159273#L721-3 assume !(0 == ~T6_E~0); 159271#L726-3 assume !(0 == ~E_M~0); 159268#L731-3 assume 0 == ~E_1~0;~E_1~0 := 1; 159264#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 159262#L741-3 assume 0 == ~E_3~0;~E_3~0 := 1; 159260#L746-3 assume 0 == ~E_4~0;~E_4~0 := 1; 159256#L751-3 assume 0 == ~E_5~0;~E_5~0 := 1; 159252#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 159249#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 159246#L346-24 assume !(1 == ~m_pc~0); 159243#L346-26 is_master_triggered_~__retres1~0#1 := 0; 159240#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 159237#is_master_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 159235#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 159232#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 159229#L365-24 assume !(1 == ~t1_pc~0); 159226#L365-26 is_transmit1_triggered_~__retres1~1#1 := 0; 159222#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 159217#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 159212#L869-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 159208#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 159205#L384-24 assume 1 == ~t2_pc~0; 159200#L385-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 159196#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 159193#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 159188#L877-24 assume !(0 != activate_threads_~tmp___1~0#1); 159182#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 159176#L403-24 assume !(1 == ~t3_pc~0); 159172#L403-26 is_transmit3_triggered_~__retres1~3#1 := 0; 159169#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 159166#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 159163#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 159160#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 159157#L422-24 assume !(1 == ~t4_pc~0); 159154#L422-26 is_transmit4_triggered_~__retres1~4#1 := 0; 159151#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 159145#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 159141#L893-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 159136#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 159129#L441-24 assume 1 == ~t5_pc~0; 159120#L442-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 159114#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 159095#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 159090#L901-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 159084#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 159079#L460-24 assume !(1 == ~t6_pc~0); 159074#L460-26 is_transmit6_triggered_~__retres1~6#1 := 0; 159068#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 159061#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 159057#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 159053#L909-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 159050#L774-3 assume 1 == ~M_E~0;~M_E~0 := 2; 158867#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 159044#L779-3 assume !(1 == ~T2_E~0); 159039#L784-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 159034#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 159029#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 159024#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 159018#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 159012#L809-3 assume 1 == ~E_1~0;~E_1~0 := 2; 159007#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 159002#L819-3 assume !(1 == ~E_3~0); 158997#L824-3 assume 1 == ~E_4~0;~E_4~0 := 2; 158991#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 158985#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 158980#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 158134#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 158126#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 158124#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 158101#L1084 assume !(0 == start_simulation_~tmp~3#1); 158098#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 158075#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 158063#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 158055#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 158045#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 158041#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 158037#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 157800#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 157795#L1065-2 [2022-12-13 19:41:37,849 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:41:37,849 INFO L85 PathProgramCache]: Analyzing trace with hash 125941963, now seen corresponding path program 1 times [2022-12-13 19:41:37,849 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:41:37,849 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [328609864] [2022-12-13 19:41:37,849 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:41:37,849 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:41:37,861 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:41:37,901 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:41:37,902 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:41:37,902 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [328609864] [2022-12-13 19:41:37,902 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [328609864] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:41:37,902 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:41:37,902 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-12-13 19:41:37,902 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1392416168] [2022-12-13 19:41:37,902 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:41:37,903 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 19:41:37,903 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:41:37,903 INFO L85 PathProgramCache]: Analyzing trace with hash -305852800, now seen corresponding path program 2 times [2022-12-13 19:41:37,903 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:41:37,903 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [393608551] [2022-12-13 19:41:37,903 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:41:37,903 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:41:37,914 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:41:37,933 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:41:37,933 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:41:37,933 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [393608551] [2022-12-13 19:41:37,934 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [393608551] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:41:37,934 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:41:37,934 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:41:37,934 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1211010604] [2022-12-13 19:41:37,934 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:41:37,934 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 19:41:37,934 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 19:41:37,935 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 19:41:37,935 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 19:41:37,935 INFO L87 Difference]: Start difference. First operand 40669 states and 57942 transitions. cyclomatic complexity: 17305 Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 2 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:41:38,164 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 19:41:38,165 INFO L93 Difference]: Finished difference Result 60416 states and 86233 transitions. [2022-12-13 19:41:38,165 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 60416 states and 86233 transitions. [2022-12-13 19:41:38,360 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 59948 [2022-12-13 19:41:38,562 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 60416 states to 60416 states and 86233 transitions. [2022-12-13 19:41:38,562 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 60416 [2022-12-13 19:41:38,591 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 60416 [2022-12-13 19:41:38,592 INFO L73 IsDeterministic]: Start isDeterministic. Operand 60416 states and 86233 transitions. [2022-12-13 19:41:38,630 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 19:41:38,630 INFO L218 hiAutomatonCegarLoop]: Abstraction has 60416 states and 86233 transitions. [2022-12-13 19:41:38,658 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 60416 states and 86233 transitions. [2022-12-13 19:41:39,073 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 60416 to 42340. [2022-12-13 19:41:39,111 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 42340 states, 42340 states have (on average 1.4298299480396788) internal successors, (60539), 42339 states have internal predecessors, (60539), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:41:39,205 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 42340 states to 42340 states and 60539 transitions. [2022-12-13 19:41:39,205 INFO L240 hiAutomatonCegarLoop]: Abstraction has 42340 states and 60539 transitions. [2022-12-13 19:41:39,206 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 19:41:39,206 INFO L428 stractBuchiCegarLoop]: Abstraction has 42340 states and 60539 transitions. [2022-12-13 19:41:39,206 INFO L335 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2022-12-13 19:41:39,206 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 42340 states and 60539 transitions. [2022-12-13 19:41:39,338 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 42003 [2022-12-13 19:41:39,338 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 19:41:39,339 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 19:41:39,341 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:41:39,341 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:41:39,341 INFO L748 eck$LassoCheckResult]: Stem: 253945#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 253946#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 254132#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 254133#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 254319#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 253837#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 253838#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 253672#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 253673#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 253645#L507-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 253646#L512-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 253815#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 253980#L696 assume !(0 == ~M_E~0); 253981#L696-2 assume !(0 == ~T1_E~0); 254329#L701-1 assume !(0 == ~T2_E~0); 254332#L706-1 assume !(0 == ~T3_E~0); 254099#L711-1 assume !(0 == ~T4_E~0); 253873#L716-1 assume !(0 == ~T5_E~0); 253874#L721-1 assume !(0 == ~T6_E~0); 254054#L726-1 assume !(0 == ~E_M~0); 254055#L731-1 assume !(0 == ~E_1~0); 254019#L736-1 assume !(0 == ~E_2~0); 254020#L741-1 assume !(0 == ~E_3~0); 254111#L746-1 assume !(0 == ~E_4~0); 253899#L751-1 assume !(0 == ~E_5~0); 253900#L756-1 assume !(0 == ~E_6~0); 253870#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 253693#L346 assume !(1 == ~m_pc~0); 253694#L346-2 is_master_triggered_~__retres1~0#1 := 0; 253914#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 253906#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 253907#L861 assume !(0 != activate_threads_~tmp~1#1); 254289#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 253727#L365 assume !(1 == ~t1_pc~0); 253728#L365-2 is_transmit1_triggered_~__retres1~1#1 := 0; 254307#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 253677#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 253678#L869 assume !(0 != activate_threads_~tmp___0~0#1); 253717#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 254176#L384 assume !(1 == ~t2_pc~0); 254170#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 254171#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 254136#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 253634#L877 assume !(0 != activate_threads_~tmp___1~0#1); 253635#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 253998#L403 assume !(1 == ~t3_pc~0); 253999#L403-2 is_transmit3_triggered_~__retres1~3#1 := 0; 254216#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 253609#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 253610#L885 assume !(0 != activate_threads_~tmp___2~0#1); 253989#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 253990#L422 assume !(1 == ~t4_pc~0); 254130#L422-2 is_transmit4_triggered_~__retres1~4#1 := 0; 254131#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 253780#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 253781#L893 assume !(0 != activate_threads_~tmp___3~0#1); 254082#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 253647#L441 assume !(1 == ~t5_pc~0); 253648#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 254283#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 253917#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 253918#L901 assume !(0 != activate_threads_~tmp___4~0#1); 254090#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 254091#L460 assume !(1 == ~t6_pc~0); 254241#L460-2 is_transmit6_triggered_~__retres1~6#1 := 0; 253654#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 253655#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 254114#L909 assume !(0 != activate_threads_~tmp___5~0#1); 254238#L909-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 254066#L774 assume !(1 == ~M_E~0); 254067#L774-2 assume !(1 == ~T1_E~0); 254260#L779-1 assume !(1 == ~T2_E~0); 253963#L784-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 253964#L789-1 assume !(1 == ~T4_E~0); 253711#L794-1 assume !(1 == ~T5_E~0); 253712#L799-1 assume !(1 == ~T6_E~0); 254382#L804-1 assume !(1 == ~E_M~0); 254383#L809-1 assume !(1 == ~E_1~0); 254049#L814-1 assume !(1 == ~E_2~0); 253613#L819-1 assume !(1 == ~E_3~0); 253614#L824-1 assume 1 == ~E_4~0;~E_4~0 := 2; 254123#L829-1 assume !(1 == ~E_5~0); 254247#L834-1 assume !(1 == ~E_6~0); 253855#L839-1 assume { :end_inline_reset_delta_events } true; 253856#L1065-2 [2022-12-13 19:41:39,342 INFO L750 eck$LassoCheckResult]: Loop: 253856#L1065-2 assume !false; 274131#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 274104#L671 assume !false; 274096#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 274072#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 274065#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 274063#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 273993#L582 assume !(0 != eval_~tmp~0#1); 273994#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 275363#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 275361#L696-3 assume !(0 == ~M_E~0); 275359#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 275357#L701-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 275355#L706-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 275351#L711-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 275349#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 275347#L721-3 assume !(0 == ~T6_E~0); 275345#L726-3 assume !(0 == ~E_M~0); 274810#L731-3 assume 0 == ~E_1~0;~E_1~0 := 1; 274808#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 274806#L741-3 assume 0 == ~E_3~0;~E_3~0 := 1; 274804#L746-3 assume 0 == ~E_4~0;~E_4~0 := 1; 274802#L751-3 assume 0 == ~E_5~0;~E_5~0 := 1; 274800#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 274798#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 274796#L346-24 assume !(1 == ~m_pc~0); 274794#L346-26 is_master_triggered_~__retres1~0#1 := 0; 274792#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 274790#is_master_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 274787#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 274785#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 274783#L365-24 assume !(1 == ~t1_pc~0); 274781#L365-26 is_transmit1_triggered_~__retres1~1#1 := 0; 274779#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 274777#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 274776#L869-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 274773#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 274771#L384-24 assume 1 == ~t2_pc~0; 274768#L385-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 274766#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 274764#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 274762#L877-24 assume !(0 != activate_threads_~tmp___1~0#1); 274760#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 274758#L403-24 assume !(1 == ~t3_pc~0); 274756#L403-26 is_transmit3_triggered_~__retres1~3#1 := 0; 274754#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 274752#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 274748#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 274746#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 274744#L422-24 assume !(1 == ~t4_pc~0); 274742#L422-26 is_transmit4_triggered_~__retres1~4#1 := 0; 274739#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 274737#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 274735#L893-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 274734#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 274731#L441-24 assume !(1 == ~t5_pc~0); 274727#L441-26 is_transmit5_triggered_~__retres1~5#1 := 0; 274725#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 274723#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 274721#L901-24 assume !(0 != activate_threads_~tmp___4~0#1); 274716#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 274714#L460-24 assume !(1 == ~t6_pc~0); 274713#L460-26 is_transmit6_triggered_~__retres1~6#1 := 0; 274712#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 274710#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 274709#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 274708#L909-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 274707#L774-3 assume !(1 == ~M_E~0); 273499#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 274706#L779-3 assume !(1 == ~T2_E~0); 274704#L784-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 274702#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 274700#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 274698#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 274696#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 274694#L809-3 assume 1 == ~E_1~0;~E_1~0 := 2; 274692#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 274690#L819-3 assume !(1 == ~E_3~0); 274688#L824-3 assume 1 == ~E_4~0;~E_4~0 := 2; 274686#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 274684#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 274682#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 274383#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 274376#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 274375#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 274374#L1084 assume !(0 == start_simulation_~tmp~3#1); 274372#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 274332#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 274318#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 274311#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 274307#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 274303#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 274242#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 274240#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 253856#L1065-2 [2022-12-13 19:41:39,342 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:41:39,342 INFO L85 PathProgramCache]: Analyzing trace with hash -1153921715, now seen corresponding path program 1 times [2022-12-13 19:41:39,342 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:41:39,343 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [825465466] [2022-12-13 19:41:39,343 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:41:39,343 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:41:39,357 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:41:39,408 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:41:39,408 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:41:39,408 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [825465466] [2022-12-13 19:41:39,408 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [825465466] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:41:39,408 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:41:39,408 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:41:39,408 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1810214291] [2022-12-13 19:41:39,409 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:41:39,409 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 19:41:39,409 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:41:39,409 INFO L85 PathProgramCache]: Analyzing trace with hash -2062689597, now seen corresponding path program 1 times [2022-12-13 19:41:39,410 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:41:39,410 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [221035973] [2022-12-13 19:41:39,410 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:41:39,410 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:41:39,422 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:41:39,450 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:41:39,450 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:41:39,450 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [221035973] [2022-12-13 19:41:39,450 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [221035973] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:41:39,451 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:41:39,451 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:41:39,451 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1833963201] [2022-12-13 19:41:39,451 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:41:39,451 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 19:41:39,452 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 19:41:39,452 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 19:41:39,452 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 19:41:39,452 INFO L87 Difference]: Start difference. First operand 42340 states and 60539 transitions. cyclomatic complexity: 18215 Second operand has 4 states, 4 states have (on average 21.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:41:39,697 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 19:41:39,697 INFO L93 Difference]: Finished difference Result 68301 states and 97092 transitions. [2022-12-13 19:41:39,697 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 68301 states and 97092 transitions. [2022-12-13 19:41:39,893 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 67767 [2022-12-13 19:41:40,015 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 68301 states to 68301 states and 97092 transitions. [2022-12-13 19:41:40,016 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 68301 [2022-12-13 19:41:40,044 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 68301 [2022-12-13 19:41:40,044 INFO L73 IsDeterministic]: Start isDeterministic. Operand 68301 states and 97092 transitions. [2022-12-13 19:41:40,070 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 19:41:40,071 INFO L218 hiAutomatonCegarLoop]: Abstraction has 68301 states and 97092 transitions. [2022-12-13 19:41:40,100 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 68301 states and 97092 transitions. [2022-12-13 19:41:40,467 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 68301 to 49292. [2022-12-13 19:41:40,500 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 49292 states, 49292 states have (on average 1.4246328004544349) internal successors, (70223), 49291 states have internal predecessors, (70223), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:41:40,708 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 49292 states to 49292 states and 70223 transitions. [2022-12-13 19:41:40,708 INFO L240 hiAutomatonCegarLoop]: Abstraction has 49292 states and 70223 transitions. [2022-12-13 19:41:40,708 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 19:41:40,709 INFO L428 stractBuchiCegarLoop]: Abstraction has 49292 states and 70223 transitions. [2022-12-13 19:41:40,709 INFO L335 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2022-12-13 19:41:40,709 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 49292 states and 70223 transitions. [2022-12-13 19:41:40,822 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 48893 [2022-12-13 19:41:40,822 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 19:41:40,822 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 19:41:40,823 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:41:40,823 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:41:40,823 INFO L748 eck$LassoCheckResult]: Stem: 364600#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 364601#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 364790#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 364791#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 364974#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 364487#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 364488#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 364322#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 364323#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 364296#L507-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 364297#L512-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 364465#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 364635#L696 assume !(0 == ~M_E~0); 364636#L696-2 assume !(0 == ~T1_E~0); 364983#L701-1 assume !(0 == ~T2_E~0); 364985#L706-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 365013#L711-1 assume !(0 == ~T4_E~0); 364523#L716-1 assume !(0 == ~T5_E~0); 364524#L721-1 assume !(0 == ~T6_E~0); 364708#L726-1 assume !(0 == ~E_M~0); 364709#L731-1 assume !(0 == ~E_1~0); 364674#L736-1 assume !(0 == ~E_2~0); 364675#L741-1 assume !(0 == ~E_3~0); 365061#L746-1 assume !(0 == ~E_4~0); 365062#L751-1 assume !(0 == ~E_5~0); 365147#L756-1 assume !(0 == ~E_6~0); 364520#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 364343#L346 assume !(1 == ~m_pc~0); 364344#L346-2 is_master_triggered_~__retres1~0#1 := 0; 365145#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 364559#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 364560#L861 assume !(0 != activate_threads_~tmp~1#1); 365144#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 364376#L365 assume !(1 == ~t1_pc~0); 364377#L365-2 is_transmit1_triggered_~__retres1~1#1 := 0; 364959#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 364972#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 365141#L869 assume !(0 != activate_threads_~tmp___0~0#1); 365140#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 365139#L384 assume !(1 == ~t2_pc~0); 365137#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 365066#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 365067#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 364285#L877 assume !(0 != activate_threads_~tmp___1~0#1); 364286#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 364651#L403 assume !(1 == ~t3_pc~0); 364652#L403-2 is_transmit3_triggered_~__retres1~3#1 := 0; 364874#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 364260#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 364261#L885 assume !(0 != activate_threads_~tmp___2~0#1); 364643#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 364644#L422 assume !(1 == ~t4_pc~0); 364975#L422-2 is_transmit4_triggered_~__retres1~4#1 := 0; 365128#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 365127#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 365126#L893 assume !(0 != activate_threads_~tmp___3~0#1); 364736#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 364298#L441 assume !(1 == ~t5_pc~0); 364299#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 364937#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 364571#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 364572#L901 assume !(0 != activate_threads_~tmp___4~0#1); 365106#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 365117#L460 assume !(1 == ~t6_pc~0); 364981#L460-2 is_transmit6_triggered_~__retres1~6#1 := 0; 364305#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 364306#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 364772#L909 assume !(0 != activate_threads_~tmp___5~0#1); 364893#L909-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 364720#L774 assume !(1 == ~M_E~0); 364721#L774-2 assume !(1 == ~T1_E~0); 365113#L779-1 assume !(1 == ~T2_E~0); 365112#L784-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 364619#L789-1 assume !(1 == ~T4_E~0); 364361#L794-1 assume !(1 == ~T5_E~0); 364362#L799-1 assume !(1 == ~T6_E~0); 365043#L804-1 assume !(1 == ~E_M~0); 365044#L809-1 assume !(1 == ~E_1~0); 364703#L814-1 assume !(1 == ~E_2~0); 364264#L819-1 assume !(1 == ~E_3~0); 364265#L824-1 assume 1 == ~E_4~0;~E_4~0 := 2; 364780#L829-1 assume !(1 == ~E_5~0); 364901#L834-1 assume !(1 == ~E_6~0); 364504#L839-1 assume { :end_inline_reset_delta_events } true; 364505#L1065-2 [2022-12-13 19:41:40,823 INFO L750 eck$LassoCheckResult]: Loop: 364505#L1065-2 assume !false; 387358#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 387355#L671 assume !false; 387354#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 387272#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 387266#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 387265#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 387263#L582 assume !(0 != eval_~tmp~0#1); 387255#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 387253#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 387251#L696-3 assume !(0 == ~M_E~0); 387249#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 387247#L701-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 387244#L706-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 387245#L711-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 390089#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 390086#L721-3 assume !(0 == ~T6_E~0); 390083#L726-3 assume !(0 == ~E_M~0); 390080#L731-3 assume 0 == ~E_1~0;~E_1~0 := 1; 390077#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 390074#L741-3 assume 0 == ~E_3~0;~E_3~0 := 1; 390071#L746-3 assume 0 == ~E_4~0;~E_4~0 := 1; 390069#L751-3 assume 0 == ~E_5~0;~E_5~0 := 1; 390067#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 390065#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 390063#L346-24 assume !(1 == ~m_pc~0); 390061#L346-26 is_master_triggered_~__retres1~0#1 := 0; 390059#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 390057#is_master_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 390054#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 390052#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 390050#L365-24 assume !(1 == ~t1_pc~0); 390048#L365-26 is_transmit1_triggered_~__retres1~1#1 := 0; 390046#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 390044#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 390042#L869-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 390040#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 390037#L384-24 assume 1 == ~t2_pc~0; 390033#L385-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 390030#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 390027#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 390024#L877-24 assume !(0 != activate_threads_~tmp___1~0#1); 390021#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 390018#L403-24 assume !(1 == ~t3_pc~0); 390015#L403-26 is_transmit3_triggered_~__retres1~3#1 := 0; 390012#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 390010#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 383981#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 383980#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 383978#L422-24 assume !(1 == ~t4_pc~0); 383976#L422-26 is_transmit4_triggered_~__retres1~4#1 := 0; 383975#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 383974#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 383972#L893-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 383970#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 383969#L441-24 assume 1 == ~t5_pc~0; 383968#L442-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 383966#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 383964#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 383961#L901-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 383960#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 383958#L460-24 assume !(1 == ~t6_pc~0); 383957#L460-26 is_transmit6_triggered_~__retres1~6#1 := 0; 383955#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 383952#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 383950#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 383948#L909-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 383946#L774-3 assume !(1 == ~M_E~0); 383039#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 383943#L779-3 assume !(1 == ~T2_E~0); 383721#L784-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 383719#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 383717#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 383715#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 383713#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 383710#L809-3 assume 1 == ~E_1~0;~E_1~0 := 2; 383708#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 383706#L819-3 assume !(1 == ~E_3~0); 383704#L824-3 assume 1 == ~E_4~0;~E_4~0 := 2; 383702#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 383700#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 383698#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 383540#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 383533#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 383531#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 383260#L1084 assume !(0 == start_simulation_~tmp~3#1); 383261#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 387380#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 387376#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 387374#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 387372#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 387368#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 387366#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 387364#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 364505#L1065-2 [2022-12-13 19:41:40,823 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:41:40,824 INFO L85 PathProgramCache]: Analyzing trace with hash -661295541, now seen corresponding path program 1 times [2022-12-13 19:41:40,824 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:41:40,824 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1207489671] [2022-12-13 19:41:40,824 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:41:40,824 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:41:40,830 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:41:40,853 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:41:40,853 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:41:40,853 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1207489671] [2022-12-13 19:41:40,853 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1207489671] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:41:40,854 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:41:40,854 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:41:40,854 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1039488818] [2022-12-13 19:41:40,854 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:41:40,854 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 19:41:40,854 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:41:40,854 INFO L85 PathProgramCache]: Analyzing trace with hash -261755712, now seen corresponding path program 1 times [2022-12-13 19:41:40,855 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:41:40,855 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1611146240] [2022-12-13 19:41:40,855 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:41:40,855 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:41:40,863 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:41:40,884 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:41:40,884 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:41:40,884 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1611146240] [2022-12-13 19:41:40,884 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1611146240] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:41:40,884 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:41:40,884 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:41:40,884 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [422064746] [2022-12-13 19:41:40,884 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:41:40,885 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 19:41:40,885 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 19:41:40,885 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 19:41:40,885 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 19:41:40,885 INFO L87 Difference]: Start difference. First operand 49292 states and 70223 transitions. cyclomatic complexity: 20947 Second operand has 4 states, 4 states have (on average 21.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:41:41,067 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 19:41:41,067 INFO L93 Difference]: Finished difference Result 61338 states and 87007 transitions. [2022-12-13 19:41:41,067 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 61338 states and 87007 transitions. [2022-12-13 19:41:41,257 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 60877 [2022-12-13 19:41:41,374 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 61338 states to 61338 states and 87007 transitions. [2022-12-13 19:41:41,375 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 61338 [2022-12-13 19:41:41,403 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 61338 [2022-12-13 19:41:41,404 INFO L73 IsDeterministic]: Start isDeterministic. Operand 61338 states and 87007 transitions. [2022-12-13 19:41:41,429 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 19:41:41,429 INFO L218 hiAutomatonCegarLoop]: Abstraction has 61338 states and 87007 transitions. [2022-12-13 19:41:41,456 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 61338 states and 87007 transitions. [2022-12-13 19:41:41,818 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 61338 to 42340. [2022-12-13 19:41:41,843 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 42340 states, 42340 states have (on average 1.4221303731695796) internal successors, (60213), 42339 states have internal predecessors, (60213), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:41:41,894 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 42340 states to 42340 states and 60213 transitions. [2022-12-13 19:41:41,894 INFO L240 hiAutomatonCegarLoop]: Abstraction has 42340 states and 60213 transitions. [2022-12-13 19:41:41,895 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 19:41:41,895 INFO L428 stractBuchiCegarLoop]: Abstraction has 42340 states and 60213 transitions. [2022-12-13 19:41:41,895 INFO L335 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2022-12-13 19:41:41,895 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 42340 states and 60213 transitions. [2022-12-13 19:41:41,988 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 42003 [2022-12-13 19:41:41,988 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 19:41:41,988 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 19:41:41,989 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:41:41,989 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:41:41,990 INFO L748 eck$LassoCheckResult]: Stem: 475233#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 475234#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 475409#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 475410#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 475601#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 475129#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 475130#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 474965#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 474966#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 474938#L507-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 474939#L512-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 475107#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 475268#L696 assume !(0 == ~M_E~0); 475269#L696-2 assume !(0 == ~T1_E~0); 475605#L701-1 assume !(0 == ~T2_E~0); 475607#L706-1 assume !(0 == ~T3_E~0); 475381#L711-1 assume !(0 == ~T4_E~0); 475164#L716-1 assume !(0 == ~T5_E~0); 475165#L721-1 assume !(0 == ~T6_E~0); 475339#L726-1 assume !(0 == ~E_M~0); 475340#L731-1 assume !(0 == ~E_1~0); 475304#L736-1 assume !(0 == ~E_2~0); 475305#L741-1 assume !(0 == ~E_3~0); 475391#L746-1 assume !(0 == ~E_4~0); 475188#L751-1 assume !(0 == ~E_5~0); 475189#L756-1 assume !(0 == ~E_6~0); 475161#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 474986#L346 assume !(1 == ~m_pc~0); 474987#L346-2 is_master_triggered_~__retres1~0#1 := 0; 475204#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 475196#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 475197#L861 assume !(0 != activate_threads_~tmp~1#1); 475567#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 475019#L365 assume !(1 == ~t1_pc~0); 475020#L365-2 is_transmit1_triggered_~__retres1~1#1 := 0; 475588#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 474970#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 474971#L869 assume !(0 != activate_threads_~tmp___0~0#1); 475009#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 475451#L384 assume !(1 == ~t2_pc~0); 475445#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 475446#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 475411#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 474926#L877 assume !(0 != activate_threads_~tmp___1~0#1); 474927#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 475283#L403 assume !(1 == ~t3_pc~0); 475284#L403-2 is_transmit3_triggered_~__retres1~3#1 := 0; 475492#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 474901#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 474902#L885 assume !(0 != activate_threads_~tmp___2~0#1); 475276#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 475277#L422 assume !(1 == ~t4_pc~0); 475407#L422-2 is_transmit4_triggered_~__retres1~4#1 := 0; 475408#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 475072#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 475073#L893 assume !(0 != activate_threads_~tmp___3~0#1); 475363#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 474940#L441 assume !(1 == ~t5_pc~0); 474941#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 475562#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 475207#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 475208#L901 assume !(0 != activate_threads_~tmp___4~0#1); 475371#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 475372#L460 assume !(1 == ~t6_pc~0); 475517#L460-2 is_transmit6_triggered_~__retres1~6#1 := 0; 474947#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 474948#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 475393#L909 assume !(0 != activate_threads_~tmp___5~0#1); 475514#L909-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 475348#L774 assume !(1 == ~M_E~0); 475349#L774-2 assume !(1 == ~T1_E~0); 475537#L779-1 assume !(1 == ~T2_E~0); 475253#L784-1 assume !(1 == ~T3_E~0); 475254#L789-1 assume !(1 == ~T4_E~0); 475004#L794-1 assume !(1 == ~T5_E~0); 475005#L799-1 assume !(1 == ~T6_E~0); 475644#L804-1 assume !(1 == ~E_M~0); 475645#L809-1 assume !(1 == ~E_1~0); 475334#L814-1 assume !(1 == ~E_2~0); 474905#L819-1 assume !(1 == ~E_3~0); 474906#L824-1 assume 1 == ~E_4~0;~E_4~0 := 2; 475401#L829-1 assume !(1 == ~E_5~0); 475523#L834-1 assume !(1 == ~E_6~0); 475146#L839-1 assume { :end_inline_reset_delta_events } true; 475147#L1065-2 [2022-12-13 19:41:41,990 INFO L750 eck$LassoCheckResult]: Loop: 475147#L1065-2 assume !false; 495124#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 495094#L671 assume !false; 495091#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 495072#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 495065#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 495063#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 495060#L582 assume !(0 != eval_~tmp~0#1); 495058#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 495056#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 495054#L696-3 assume !(0 == ~M_E~0); 495052#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 495050#L701-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 495048#L706-3 assume !(0 == ~T3_E~0); 495046#L711-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 495044#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 495000#L721-3 assume !(0 == ~T6_E~0); 494984#L726-3 assume !(0 == ~E_M~0); 494974#L731-3 assume 0 == ~E_1~0;~E_1~0 := 1; 494888#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 494887#L741-3 assume 0 == ~E_3~0;~E_3~0 := 1; 494886#L746-3 assume 0 == ~E_4~0;~E_4~0 := 1; 494753#L751-3 assume 0 == ~E_5~0;~E_5~0 := 1; 494739#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 494723#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 494711#L346-24 assume !(1 == ~m_pc~0); 494700#L346-26 is_master_triggered_~__retres1~0#1 := 0; 494695#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 494690#is_master_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 494568#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 494567#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 494566#L365-24 assume !(1 == ~t1_pc~0); 494564#L365-26 is_transmit1_triggered_~__retres1~1#1 := 0; 494562#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 494561#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 494560#L869-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 494559#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 494557#L384-24 assume !(1 == ~t2_pc~0); 494509#L384-26 is_transmit2_triggered_~__retres1~2#1 := 0; 494505#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 494503#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 494500#L877-24 assume !(0 != activate_threads_~tmp___1~0#1); 494499#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 494496#L403-24 assume !(1 == ~t3_pc~0); 494488#L403-26 is_transmit3_triggered_~__retres1~3#1 := 0; 494486#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 494484#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 494481#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 494479#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 494477#L422-24 assume !(1 == ~t4_pc~0); 494475#L422-26 is_transmit4_triggered_~__retres1~4#1 := 0; 494473#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 494461#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 494455#L893-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 494449#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 494420#L441-24 assume 1 == ~t5_pc~0; 494418#L442-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 494419#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 494442#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 494409#L901-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 494407#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 494405#L460-24 assume !(1 == ~t6_pc~0); 494404#L460-26 is_transmit6_triggered_~__retres1~6#1 := 0; 494402#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 494400#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 494398#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 494396#L909-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 494394#L774-3 assume !(1 == ~M_E~0); 493554#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 494391#L779-3 assume !(1 == ~T2_E~0); 494389#L784-3 assume !(1 == ~T3_E~0); 494387#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 494385#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 494383#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 494381#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 494380#L809-3 assume 1 == ~E_1~0;~E_1~0 := 2; 494311#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 494301#L819-3 assume !(1 == ~E_3~0); 494295#L824-3 assume 1 == ~E_4~0;~E_4~0 := 2; 494290#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 494279#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 494274#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 494260#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 494245#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 494241#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 493691#L1084 assume !(0 == start_simulation_~tmp~3#1); 493692#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 495237#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 495234#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 495190#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 495183#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 495170#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 495159#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 495150#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 475147#L1065-2 [2022-12-13 19:41:41,990 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:41:41,990 INFO L85 PathProgramCache]: Analyzing trace with hash -895756277, now seen corresponding path program 1 times [2022-12-13 19:41:41,990 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:41:41,990 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1873092296] [2022-12-13 19:41:41,990 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:41:41,991 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:41:41,999 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:41:42,029 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:41:42,030 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:41:42,030 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1873092296] [2022-12-13 19:41:42,030 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1873092296] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:41:42,030 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:41:42,030 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:41:42,030 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1820735521] [2022-12-13 19:41:42,030 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:41:42,031 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 19:41:42,031 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:41:42,031 INFO L85 PathProgramCache]: Analyzing trace with hash -1213339967, now seen corresponding path program 1 times [2022-12-13 19:41:42,031 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:41:42,031 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [602771078] [2022-12-13 19:41:42,031 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:41:42,031 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:41:42,040 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:41:42,060 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:41:42,060 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:41:42,060 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [602771078] [2022-12-13 19:41:42,060 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [602771078] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:41:42,060 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:41:42,060 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:41:42,061 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1906718623] [2022-12-13 19:41:42,061 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:41:42,061 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 19:41:42,061 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 19:41:42,061 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 19:41:42,061 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 19:41:42,062 INFO L87 Difference]: Start difference. First operand 42340 states and 60213 transitions. cyclomatic complexity: 17889 Second operand has 4 states, 4 states have (on average 21.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:41:42,444 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 19:41:42,444 INFO L93 Difference]: Finished difference Result 67784 states and 95514 transitions. [2022-12-13 19:41:42,444 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 67784 states and 95514 transitions. [2022-12-13 19:41:42,690 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 67240 [2022-12-13 19:41:42,833 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 67784 states to 67784 states and 95514 transitions. [2022-12-13 19:41:42,834 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 67784 [2022-12-13 19:41:42,862 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 67784 [2022-12-13 19:41:42,862 INFO L73 IsDeterministic]: Start isDeterministic. Operand 67784 states and 95514 transitions. [2022-12-13 19:41:42,895 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 19:41:42,895 INFO L218 hiAutomatonCegarLoop]: Abstraction has 67784 states and 95514 transitions. [2022-12-13 19:41:42,925 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 67784 states and 95514 transitions. [2022-12-13 19:41:43,384 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 67784 to 49292. [2022-12-13 19:41:43,416 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 49292 states, 49292 states have (on average 1.4120344072060376) internal successors, (69602), 49291 states have internal predecessors, (69602), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:41:43,507 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 49292 states to 49292 states and 69602 transitions. [2022-12-13 19:41:43,508 INFO L240 hiAutomatonCegarLoop]: Abstraction has 49292 states and 69602 transitions. [2022-12-13 19:41:43,508 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 19:41:43,509 INFO L428 stractBuchiCegarLoop]: Abstraction has 49292 states and 69602 transitions. [2022-12-13 19:41:43,509 INFO L335 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2022-12-13 19:41:43,509 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 49292 states and 69602 transitions. [2022-12-13 19:41:43,695 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 48893 [2022-12-13 19:41:43,695 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 19:41:43,695 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 19:41:43,696 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:41:43,696 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:41:43,696 INFO L748 eck$LassoCheckResult]: Stem: 585376#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 585377#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 585562#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 585563#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 585752#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 585262#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 585263#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 585101#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 585102#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 585072#L507-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 585073#L512-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 585240#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 585411#L696 assume !(0 == ~M_E~0); 585412#L696-2 assume !(0 == ~T1_E~0); 585761#L701-1 assume !(0 == ~T2_E~0); 585763#L706-1 assume !(0 == ~T3_E~0); 585527#L711-1 assume !(0 == ~T4_E~0); 585300#L716-1 assume !(0 == ~T5_E~0); 585301#L721-1 assume !(0 == ~T6_E~0); 585483#L726-1 assume !(0 == ~E_M~0); 585484#L731-1 assume !(0 == ~E_1~0); 585446#L736-1 assume !(0 == ~E_2~0); 585447#L741-1 assume !(0 == ~E_3~0); 585539#L746-1 assume 0 == ~E_4~0;~E_4~0 := 1; 585324#L751-1 assume !(0 == ~E_5~0); 585325#L756-1 assume !(0 == ~E_6~0); 585426#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 585921#L346 assume !(1 == ~m_pc~0); 585341#L346-2 is_master_triggered_~__retres1~0#1 := 0; 585342#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 585662#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 585780#L861 assume !(0 != activate_threads_~tmp~1#1); 585715#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 585716#L365 assume !(1 == ~t1_pc~0); 585918#L365-2 is_transmit1_triggered_~__retres1~1#1 := 0; 585917#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 585107#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 585108#L869 assume !(0 != activate_threads_~tmp___0~0#1); 585143#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 585604#L384 assume !(1 == ~t2_pc~0); 585600#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 585601#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 585568#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 585569#L877 assume !(0 != activate_threads_~tmp___1~0#1); 585911#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 585910#L403 assume !(1 == ~t3_pc~0); 585909#L403-2 is_transmit3_triggered_~__retres1~3#1 := 0; 585872#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 585035#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 585036#L885 assume !(0 != activate_threads_~tmp___2~0#1); 585420#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 585421#L422 assume !(1 == ~t4_pc~0); 585756#L422-2 is_transmit4_triggered_~__retres1~4#1 := 0; 585904#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 585903#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 585902#L893 assume !(0 != activate_threads_~tmp___3~0#1); 585509#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 585074#L441 assume !(1 == ~t5_pc~0); 585075#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 585828#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 585344#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 585345#L901 assume !(0 != activate_threads_~tmp___4~0#1); 585883#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 585894#L460 assume !(1 == ~t6_pc~0); 585758#L460-2 is_transmit6_triggered_~__retres1~6#1 := 0; 585083#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 585084#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 585892#L909 assume !(0 != activate_threads_~tmp___5~0#1); 585774#L909-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 585775#L774 assume !(1 == ~M_E~0); 585809#L774-2 assume !(1 == ~T1_E~0); 585684#L779-1 assume !(1 == ~T2_E~0); 585395#L784-1 assume !(1 == ~T3_E~0); 585396#L789-1 assume !(1 == ~T4_E~0); 585889#L794-1 assume !(1 == ~T5_E~0); 585863#L799-1 assume !(1 == ~T6_E~0); 585864#L804-1 assume !(1 == ~E_M~0); 585856#L809-1 assume !(1 == ~E_1~0); 585857#L814-1 assume !(1 == ~E_2~0); 585041#L819-1 assume !(1 == ~E_3~0); 585042#L824-1 assume 1 == ~E_4~0;~E_4~0 := 2; 585553#L829-1 assume !(1 == ~E_5~0); 585672#L834-1 assume !(1 == ~E_6~0); 585282#L839-1 assume { :end_inline_reset_delta_events } true; 585283#L1065-2 [2022-12-13 19:41:43,696 INFO L750 eck$LassoCheckResult]: Loop: 585283#L1065-2 assume !false; 608284#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 607657#L671 assume !false; 608277#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 608126#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 608116#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 608087#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 608084#L582 assume !(0 != eval_~tmp~0#1); 608082#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 608080#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 608078#L696-3 assume !(0 == ~M_E~0); 608074#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 608072#L701-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 608070#L706-3 assume !(0 == ~T3_E~0); 608068#L711-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 608065#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 608063#L721-3 assume !(0 == ~T6_E~0); 608051#L726-3 assume !(0 == ~E_M~0); 608044#L731-3 assume 0 == ~E_1~0;~E_1~0 := 1; 608035#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 608025#L741-3 assume 0 == ~E_3~0;~E_3~0 := 1; 607953#L746-3 assume 0 == ~E_4~0;~E_4~0 := 1; 607952#L751-3 assume 0 == ~E_5~0;~E_5~0 := 1; 607951#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 607950#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 607949#L346-24 assume !(1 == ~m_pc~0); 607948#L346-26 is_master_triggered_~__retres1~0#1 := 0; 607947#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 607946#is_master_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 607945#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 607944#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 607943#L365-24 assume !(1 == ~t1_pc~0); 607942#L365-26 is_transmit1_triggered_~__retres1~1#1 := 0; 607941#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 607940#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 607939#L869-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 607938#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 607937#L384-24 assume 1 == ~t2_pc~0; 607935#L385-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 607934#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 607933#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 607932#L877-24 assume !(0 != activate_threads_~tmp___1~0#1); 607931#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 607930#L403-24 assume !(1 == ~t3_pc~0); 607929#L403-26 is_transmit3_triggered_~__retres1~3#1 := 0; 607928#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 607927#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 607926#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 607925#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 607924#L422-24 assume !(1 == ~t4_pc~0); 607923#L422-26 is_transmit4_triggered_~__retres1~4#1 := 0; 607922#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 607921#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 607920#L893-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 607919#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 607918#L441-24 assume !(1 == ~t5_pc~0); 607917#L441-26 is_transmit5_triggered_~__retres1~5#1 := 0; 607915#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 607913#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 607911#L901-24 assume !(0 != activate_threads_~tmp___4~0#1); 607909#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 607908#L460-24 assume !(1 == ~t6_pc~0); 607907#L460-26 is_transmit6_triggered_~__retres1~6#1 := 0; 607906#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 607905#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 607904#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 607903#L909-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 607902#L774-3 assume !(1 == ~M_E~0); 590914#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 607901#L779-3 assume !(1 == ~T2_E~0); 607900#L784-3 assume !(1 == ~T3_E~0); 607899#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 607898#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 607897#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 607896#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 607895#L809-3 assume 1 == ~E_1~0;~E_1~0 := 2; 607894#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 607893#L819-3 assume !(1 == ~E_3~0); 607891#L824-3 assume 1 == ~E_4~0;~E_4~0 := 2; 607885#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 607881#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 607869#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 607665#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 607655#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 607640#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 607638#L1084 assume !(0 == start_simulation_~tmp~3#1); 607639#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 608405#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 608395#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 608379#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 608365#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 608358#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 608352#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 608347#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 585283#L1065-2 [2022-12-13 19:41:43,697 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:41:43,697 INFO L85 PathProgramCache]: Analyzing trace with hash 1437636361, now seen corresponding path program 1 times [2022-12-13 19:41:43,697 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:41:43,697 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [640475766] [2022-12-13 19:41:43,697 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:41:43,697 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:41:43,703 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:41:43,727 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:41:43,727 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:41:43,727 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [640475766] [2022-12-13 19:41:43,727 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [640475766] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:41:43,727 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:41:43,727 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:41:43,727 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1444328120] [2022-12-13 19:41:43,728 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:41:43,728 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 19:41:43,728 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:41:43,728 INFO L85 PathProgramCache]: Analyzing trace with hash 1040426115, now seen corresponding path program 1 times [2022-12-13 19:41:43,728 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:41:43,728 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1268935054] [2022-12-13 19:41:43,728 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:41:43,729 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:41:43,737 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:41:43,755 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:41:43,755 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:41:43,755 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1268935054] [2022-12-13 19:41:43,756 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1268935054] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:41:43,756 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:41:43,756 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:41:43,756 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1758014039] [2022-12-13 19:41:43,756 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:41:43,756 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 19:41:43,756 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 19:41:43,757 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 19:41:43,757 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 19:41:43,757 INFO L87 Difference]: Start difference. First operand 49292 states and 69602 transitions. cyclomatic complexity: 20326 Second operand has 4 states, 4 states have (on average 21.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:41:43,948 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 19:41:43,949 INFO L93 Difference]: Finished difference Result 60427 states and 84941 transitions. [2022-12-13 19:41:43,949 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 60427 states and 84941 transitions. [2022-12-13 19:41:44,135 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 59948 [2022-12-13 19:41:44,248 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 60427 states to 60427 states and 84941 transitions. [2022-12-13 19:41:44,248 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 60427 [2022-12-13 19:41:44,276 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 60427 [2022-12-13 19:41:44,276 INFO L73 IsDeterministic]: Start isDeterministic. Operand 60427 states and 84941 transitions. [2022-12-13 19:41:44,302 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 19:41:44,302 INFO L218 hiAutomatonCegarLoop]: Abstraction has 60427 states and 84941 transitions. [2022-12-13 19:41:44,328 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 60427 states and 84941 transitions. [2022-12-13 19:41:44,612 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 60427 to 42340. [2022-12-13 19:41:44,636 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 42340 states, 42340 states have (on average 1.4074633915918753) internal successors, (59592), 42339 states have internal predecessors, (59592), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:41:44,697 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 42340 states to 42340 states and 59592 transitions. [2022-12-13 19:41:44,697 INFO L240 hiAutomatonCegarLoop]: Abstraction has 42340 states and 59592 transitions. [2022-12-13 19:41:44,698 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 19:41:44,698 INFO L428 stractBuchiCegarLoop]: Abstraction has 42340 states and 59592 transitions. [2022-12-13 19:41:44,698 INFO L335 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2022-12-13 19:41:44,698 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 42340 states and 59592 transitions. [2022-12-13 19:41:44,819 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 42003 [2022-12-13 19:41:44,819 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 19:41:44,819 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 19:41:44,820 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:41:44,820 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:41:44,821 INFO L748 eck$LassoCheckResult]: Stem: 695097#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 695098#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 695271#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 695272#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 695467#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 694989#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 694990#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 694829#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 694830#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 694799#L507-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 694800#L512-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 694967#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 695131#L696 assume !(0 == ~M_E~0); 695132#L696-2 assume !(0 == ~T1_E~0); 695478#L701-1 assume !(0 == ~T2_E~0); 695480#L706-1 assume !(0 == ~T3_E~0); 695244#L711-1 assume !(0 == ~T4_E~0); 695025#L716-1 assume !(0 == ~T5_E~0); 695026#L721-1 assume !(0 == ~T6_E~0); 695200#L726-1 assume !(0 == ~E_M~0); 695201#L731-1 assume !(0 == ~E_1~0); 695165#L736-1 assume !(0 == ~E_2~0); 695166#L741-1 assume !(0 == ~E_3~0); 695254#L746-1 assume !(0 == ~E_4~0); 695050#L751-1 assume !(0 == ~E_5~0); 695051#L756-1 assume !(0 == ~E_6~0); 695022#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 694849#L346 assume !(1 == ~m_pc~0); 694850#L346-2 is_master_triggered_~__retres1~0#1 := 0; 695067#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 695057#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 695058#L861 assume !(0 != activate_threads_~tmp~1#1); 695431#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 694882#L365 assume !(1 == ~t1_pc~0); 694883#L365-2 is_transmit1_triggered_~__retres1~1#1 := 0; 695451#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 694835#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 694836#L869 assume !(0 != activate_threads_~tmp___0~0#1); 694871#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 695313#L384 assume !(1 == ~t2_pc~0); 695309#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 695310#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 695276#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 694790#L877 assume !(0 != activate_threads_~tmp___1~0#1); 694791#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 695146#L403 assume !(1 == ~t3_pc~0); 695147#L403-2 is_transmit3_triggered_~__retres1~3#1 := 0; 695355#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 694763#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 694764#L885 assume !(0 != activate_threads_~tmp___2~0#1); 695140#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 695141#L422 assume !(1 == ~t4_pc~0); 695269#L422-2 is_transmit4_triggered_~__retres1~4#1 := 0; 695270#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 694933#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 694934#L893 assume !(0 != activate_threads_~tmp___3~0#1); 695226#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 694801#L441 assume !(1 == ~t5_pc~0); 694802#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 695425#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 695069#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 695070#L901 assume !(0 != activate_threads_~tmp___4~0#1); 695235#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 695236#L460 assume !(1 == ~t6_pc~0); 695380#L460-2 is_transmit6_triggered_~__retres1~6#1 := 0; 694810#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 694811#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 695256#L909 assume !(0 != activate_threads_~tmp___5~0#1); 695374#L909-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 695210#L774 assume !(1 == ~M_E~0); 695211#L774-2 assume !(1 == ~T1_E~0); 695396#L779-1 assume !(1 == ~T2_E~0); 695113#L784-1 assume !(1 == ~T3_E~0); 695114#L789-1 assume !(1 == ~T4_E~0); 694865#L794-1 assume !(1 == ~T5_E~0); 694866#L799-1 assume !(1 == ~T6_E~0); 695538#L804-1 assume !(1 == ~E_M~0); 695539#L809-1 assume !(1 == ~E_1~0); 695196#L814-1 assume !(1 == ~E_2~0); 694769#L819-1 assume !(1 == ~E_3~0); 694770#L824-1 assume !(1 == ~E_4~0); 695264#L829-1 assume !(1 == ~E_5~0); 695384#L834-1 assume !(1 == ~E_6~0); 695009#L839-1 assume { :end_inline_reset_delta_events } true; 695010#L1065-2 [2022-12-13 19:41:44,821 INFO L750 eck$LassoCheckResult]: Loop: 695010#L1065-2 assume !false; 724729#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 721899#L671 assume !false; 724726#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 721483#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 721476#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 721474#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 721472#L582 assume !(0 != eval_~tmp~0#1); 721470#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 720855#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 720851#L696-3 assume !(0 == ~M_E~0); 720848#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 720845#L701-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 720842#L706-3 assume !(0 == ~T3_E~0); 720839#L711-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 720838#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 720830#L721-3 assume !(0 == ~T6_E~0); 720828#L726-3 assume !(0 == ~E_M~0); 720826#L731-3 assume 0 == ~E_1~0;~E_1~0 := 1; 720823#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 720821#L741-3 assume 0 == ~E_3~0;~E_3~0 := 1; 720819#L746-3 assume !(0 == ~E_4~0); 720817#L751-3 assume 0 == ~E_5~0;~E_5~0 := 1; 720815#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 720813#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 720811#L346-24 assume !(1 == ~m_pc~0); 720809#L346-26 is_master_triggered_~__retres1~0#1 := 0; 720807#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 720805#is_master_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 720803#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 720801#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 720799#L365-24 assume !(1 == ~t1_pc~0); 720797#L365-26 is_transmit1_triggered_~__retres1~1#1 := 0; 720795#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 720793#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 720791#L869-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 720789#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 720787#L384-24 assume 1 == ~t2_pc~0; 720784#L385-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 720782#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 720780#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 720778#L877-24 assume !(0 != activate_threads_~tmp___1~0#1); 720776#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 720774#L403-24 assume !(1 == ~t3_pc~0); 720772#L403-26 is_transmit3_triggered_~__retres1~3#1 := 0; 720770#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 720768#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 720766#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 720764#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 720762#L422-24 assume !(1 == ~t4_pc~0); 720759#L422-26 is_transmit4_triggered_~__retres1~4#1 := 0; 720757#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 720755#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 720753#L893-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 720751#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 720749#L441-24 assume 1 == ~t5_pc~0; 720747#L442-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 720748#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 724759#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 720738#L901-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 720736#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 720734#L460-24 assume !(1 == ~t6_pc~0); 720732#L460-26 is_transmit6_triggered_~__retres1~6#1 := 0; 720730#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 720728#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 720726#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 720724#L909-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 720720#L774-3 assume !(1 == ~M_E~0); 711646#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 720717#L779-3 assume !(1 == ~T2_E~0); 720715#L784-3 assume !(1 == ~T3_E~0); 720712#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 720710#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 720708#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 720705#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 720703#L809-3 assume 1 == ~E_1~0;~E_1~0 := 2; 720701#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 720699#L819-3 assume !(1 == ~E_3~0); 720697#L824-3 assume !(1 == ~E_4~0); 720695#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 720694#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 720692#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 720687#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 720680#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 720678#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 712031#L1084 assume !(0 == start_simulation_~tmp~3#1); 712032#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 724746#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 724742#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 724739#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 724737#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 724735#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 724733#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 724731#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 695010#L1065-2 [2022-12-13 19:41:44,821 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:41:44,821 INFO L85 PathProgramCache]: Analyzing trace with hash -895696695, now seen corresponding path program 1 times [2022-12-13 19:41:44,822 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:41:44,822 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [69633417] [2022-12-13 19:41:44,822 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:41:44,822 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:41:44,831 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 19:41:44,831 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 19:41:44,838 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 19:41:44,892 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 19:41:44,893 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:41:44,893 INFO L85 PathProgramCache]: Analyzing trace with hash -90750912, now seen corresponding path program 1 times [2022-12-13 19:41:44,893 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:41:44,893 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2032667966] [2022-12-13 19:41:44,893 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:41:44,894 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:41:44,905 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:41:44,931 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:41:44,931 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:41:44,931 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2032667966] [2022-12-13 19:41:44,931 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2032667966] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:41:44,931 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:41:44,931 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:41:44,931 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [428888151] [2022-12-13 19:41:44,932 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:41:44,932 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 19:41:44,932 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 19:41:44,932 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 19:41:44,933 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 19:41:44,933 INFO L87 Difference]: Start difference. First operand 42340 states and 59592 transitions. cyclomatic complexity: 17268 Second operand has 3 states, 3 states have (on average 31.333333333333332) internal successors, (94), 3 states have internal predecessors, (94), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:41:45,107 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 19:41:45,107 INFO L93 Difference]: Finished difference Result 49292 states and 69112 transitions. [2022-12-13 19:41:45,107 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 49292 states and 69112 transitions. [2022-12-13 19:41:45,267 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 48893 [2022-12-13 19:41:45,367 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 49292 states to 49292 states and 69112 transitions. [2022-12-13 19:41:45,367 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 49292 [2022-12-13 19:41:45,390 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 49292 [2022-12-13 19:41:45,390 INFO L73 IsDeterministic]: Start isDeterministic. Operand 49292 states and 69112 transitions. [2022-12-13 19:41:45,409 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 19:41:45,410 INFO L218 hiAutomatonCegarLoop]: Abstraction has 49292 states and 69112 transitions. [2022-12-13 19:41:45,431 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 49292 states and 69112 transitions. [2022-12-13 19:41:45,697 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 49292 to 49292. [2022-12-13 19:41:45,727 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 49292 states, 49292 states have (on average 1.4020936460277529) internal successors, (69112), 49291 states have internal predecessors, (69112), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:41:45,796 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 49292 states to 49292 states and 69112 transitions. [2022-12-13 19:41:45,796 INFO L240 hiAutomatonCegarLoop]: Abstraction has 49292 states and 69112 transitions. [2022-12-13 19:41:45,797 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 19:41:45,797 INFO L428 stractBuchiCegarLoop]: Abstraction has 49292 states and 69112 transitions. [2022-12-13 19:41:45,797 INFO L335 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2022-12-13 19:41:45,797 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 49292 states and 69112 transitions. [2022-12-13 19:41:45,914 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 48893 [2022-12-13 19:41:45,914 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 19:41:45,914 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 19:41:45,915 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:41:45,915 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:41:45,916 INFO L748 eck$LassoCheckResult]: Stem: 786737#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 786738#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 786915#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 786916#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 787106#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 786628#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 786629#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 786464#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 786465#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 786438#L507-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 786439#L512-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 786606#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 786769#L696 assume !(0 == ~M_E~0); 786770#L696-2 assume !(0 == ~T1_E~0); 787117#L701-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 787119#L706-1 assume !(0 == ~T3_E~0); 786884#L711-1 assume !(0 == ~T4_E~0); 786885#L716-1 assume !(0 == ~T5_E~0); 787292#L721-1 assume !(0 == ~T6_E~0); 786841#L726-1 assume !(0 == ~E_M~0); 786842#L731-1 assume !(0 == ~E_1~0); 786806#L736-1 assume !(0 == ~E_2~0); 786807#L741-1 assume !(0 == ~E_3~0); 787200#L746-1 assume !(0 == ~E_4~0); 786688#L751-1 assume !(0 == ~E_5~0); 786689#L756-1 assume !(0 == ~E_6~0); 786785#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 787287#L346 assume !(1 == ~m_pc~0); 787286#L346-2 is_master_triggered_~__retres1~0#1 := 0; 787285#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 787284#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 787139#L861 assume !(0 != activate_threads_~tmp~1#1); 787076#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 786518#L365 assume !(1 == ~t1_pc~0); 786519#L365-2 is_transmit1_triggered_~__retres1~1#1 := 0; 787093#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 786469#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 786470#L869 assume !(0 != activate_threads_~tmp___0~0#1); 786508#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 786957#L384 assume !(1 == ~t2_pc~0); 786952#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 786953#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 787273#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 787272#L877 assume !(0 != activate_threads_~tmp___1~0#1); 787271#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 787270#L403 assume !(1 == ~t3_pc~0); 787269#L403-2 is_transmit3_triggered_~__retres1~3#1 := 0; 787268#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 787267#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 787266#L885 assume !(0 != activate_threads_~tmp___2~0#1); 787265#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 787264#L422 assume !(1 == ~t4_pc~0); 786913#L422-2 is_transmit4_triggered_~__retres1~4#1 := 0; 786914#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 786571#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 786572#L893 assume !(0 != activate_threads_~tmp___3~0#1); 787053#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 787260#L441 assume !(1 == ~t5_pc~0); 787071#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 787072#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 786708#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 786709#L901 assume !(0 != activate_threads_~tmp___4~0#1); 786872#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 786873#L460 assume !(1 == ~t6_pc~0); 787025#L460-2 is_transmit6_triggered_~__retres1~6#1 := 0; 786447#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 786448#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 786898#L909 assume !(0 != activate_threads_~tmp___5~0#1); 787020#L909-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 786851#L774 assume !(1 == ~M_E~0); 786852#L774-2 assume !(1 == ~T1_E~0); 787043#L779-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 786756#L784-1 assume !(1 == ~T3_E~0); 786757#L789-1 assume !(1 == ~T4_E~0); 786503#L794-1 assume !(1 == ~T5_E~0); 786504#L799-1 assume !(1 == ~T6_E~0); 787181#L804-1 assume !(1 == ~E_M~0); 787182#L809-1 assume !(1 == ~E_1~0); 786836#L814-1 assume !(1 == ~E_2~0); 786405#L819-1 assume !(1 == ~E_3~0); 786406#L824-1 assume !(1 == ~E_4~0); 786906#L829-1 assume !(1 == ~E_5~0); 787031#L834-1 assume !(1 == ~E_6~0); 786644#L839-1 assume { :end_inline_reset_delta_events } true; 786645#L1065-2 [2022-12-13 19:41:45,916 INFO L750 eck$LassoCheckResult]: Loop: 786645#L1065-2 assume !false; 819260#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 801115#L671 assume !false; 819256#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 809898#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 809890#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 809886#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 809884#L582 assume !(0 != eval_~tmp~0#1); 809885#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 817564#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 817563#L696-3 assume !(0 == ~M_E~0); 817562#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 817561#L701-3 assume !(0 == ~T2_E~0); 817560#L706-3 assume !(0 == ~T3_E~0); 817558#L711-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 817556#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 817554#L721-3 assume !(0 == ~T6_E~0); 817552#L726-3 assume !(0 == ~E_M~0); 817550#L731-3 assume 0 == ~E_1~0;~E_1~0 := 1; 817548#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 817546#L741-3 assume 0 == ~E_3~0;~E_3~0 := 1; 817544#L746-3 assume !(0 == ~E_4~0); 817542#L751-3 assume 0 == ~E_5~0;~E_5~0 := 1; 817540#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 817538#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 817536#L346-24 assume !(1 == ~m_pc~0); 817534#L346-26 is_master_triggered_~__retres1~0#1 := 0; 817532#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 817530#is_master_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 817528#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 817526#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 817524#L365-24 assume !(1 == ~t1_pc~0); 817522#L365-26 is_transmit1_triggered_~__retres1~1#1 := 0; 817520#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 817518#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 817516#L869-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 817514#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 817512#L384-24 assume 1 == ~t2_pc~0; 817509#L385-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 817506#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 817504#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 817502#L877-24 assume !(0 != activate_threads_~tmp___1~0#1); 817500#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 817498#L403-24 assume !(1 == ~t3_pc~0); 817496#L403-26 is_transmit3_triggered_~__retres1~3#1 := 0; 817494#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 817492#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 817490#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 817488#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 817486#L422-24 assume !(1 == ~t4_pc~0); 817484#L422-26 is_transmit4_triggered_~__retres1~4#1 := 0; 817482#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 817480#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 817478#L893-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 817476#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 817474#L441-24 assume !(1 == ~t5_pc~0); 817468#L441-26 is_transmit5_triggered_~__retres1~5#1 := 0; 817466#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 817464#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 817462#L901-24 assume !(0 != activate_threads_~tmp___4~0#1); 817458#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 817456#L460-24 assume !(1 == ~t6_pc~0); 817454#L460-26 is_transmit6_triggered_~__retres1~6#1 := 0; 817452#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 817450#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 817448#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 817446#L909-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 817444#L774-3 assume !(1 == ~M_E~0); 817190#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 817441#L779-3 assume !(1 == ~T2_E~0); 817440#L784-3 assume !(1 == ~T3_E~0); 817439#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 817438#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 817436#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 817435#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 817434#L809-3 assume 1 == ~E_1~0;~E_1~0 := 2; 817433#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 817431#L819-3 assume !(1 == ~E_3~0); 817430#L824-3 assume !(1 == ~E_4~0); 817429#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 817428#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 817427#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 817425#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 817418#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 817417#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 817415#L1084 assume !(0 == start_simulation_~tmp~3#1); 817416#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 819277#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 819273#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 819271#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 819269#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 819267#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 819265#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 819263#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 786645#L1065-2 [2022-12-13 19:41:45,916 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:41:45,916 INFO L85 PathProgramCache]: Analyzing trace with hash 2077618825, now seen corresponding path program 1 times [2022-12-13 19:41:45,916 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:41:45,916 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1737986962] [2022-12-13 19:41:45,917 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:41:45,917 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:41:45,925 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:41:45,950 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:41:45,950 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:41:45,950 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1737986962] [2022-12-13 19:41:45,950 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1737986962] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:41:45,950 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:41:45,950 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:41:45,950 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1033432754] [2022-12-13 19:41:45,950 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:41:45,951 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 19:41:45,951 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:41:45,951 INFO L85 PathProgramCache]: Analyzing trace with hash -324926847, now seen corresponding path program 1 times [2022-12-13 19:41:45,951 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:41:45,951 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [974509747] [2022-12-13 19:41:45,951 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:41:45,952 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:41:45,957 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:41:45,970 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:41:45,970 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:41:45,970 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [974509747] [2022-12-13 19:41:45,970 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [974509747] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:41:45,970 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:41:45,970 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:41:45,971 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1479995647] [2022-12-13 19:41:45,971 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:41:45,971 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 19:41:45,971 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 19:41:45,971 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 19:41:45,971 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 19:41:45,971 INFO L87 Difference]: Start difference. First operand 49292 states and 69112 transitions. cyclomatic complexity: 19836 Second operand has 4 states, 4 states have (on average 21.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:41:46,134 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 19:41:46,135 INFO L93 Difference]: Finished difference Result 61350 states and 86002 transitions. [2022-12-13 19:41:46,135 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 61350 states and 86002 transitions. [2022-12-13 19:41:46,336 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 60877 [2022-12-13 19:41:46,488 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 61350 states to 61350 states and 86002 transitions. [2022-12-13 19:41:46,488 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 61350 [2022-12-13 19:41:46,521 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 61350 [2022-12-13 19:41:46,521 INFO L73 IsDeterministic]: Start isDeterministic. Operand 61350 states and 86002 transitions. [2022-12-13 19:41:46,555 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 19:41:46,555 INFO L218 hiAutomatonCegarLoop]: Abstraction has 61350 states and 86002 transitions. [2022-12-13 19:41:46,586 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 61350 states and 86002 transitions. [2022-12-13 19:41:46,947 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 61350 to 42340. [2022-12-13 19:41:46,979 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 42340 states, 42340 states have (on average 1.4048889938592348) internal successors, (59483), 42339 states have internal predecessors, (59483), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:41:47,076 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 42340 states to 42340 states and 59483 transitions. [2022-12-13 19:41:47,076 INFO L240 hiAutomatonCegarLoop]: Abstraction has 42340 states and 59483 transitions. [2022-12-13 19:41:47,077 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 19:41:47,077 INFO L428 stractBuchiCegarLoop]: Abstraction has 42340 states and 59483 transitions. [2022-12-13 19:41:47,077 INFO L335 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2022-12-13 19:41:47,078 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 42340 states and 59483 transitions. [2022-12-13 19:41:47,202 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 42003 [2022-12-13 19:41:47,202 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 19:41:47,203 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 19:41:47,203 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:41:47,204 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:41:47,204 INFO L748 eck$LassoCheckResult]: Stem: 897388#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 897389#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 897564#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 897565#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 897741#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 897280#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 897281#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 897115#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 897116#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 897089#L507-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 897090#L512-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 897258#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 897423#L696 assume !(0 == ~M_E~0); 897424#L696-2 assume !(0 == ~T1_E~0); 897753#L701-1 assume !(0 == ~T2_E~0); 897755#L706-1 assume !(0 == ~T3_E~0); 897538#L711-1 assume !(0 == ~T4_E~0); 897315#L716-1 assume !(0 == ~T5_E~0); 897316#L721-1 assume !(0 == ~T6_E~0); 897497#L726-1 assume !(0 == ~E_M~0); 897498#L731-1 assume !(0 == ~E_1~0); 897460#L736-1 assume !(0 == ~E_2~0); 897461#L741-1 assume !(0 == ~E_3~0); 897547#L746-1 assume !(0 == ~E_4~0); 897342#L751-1 assume !(0 == ~E_5~0); 897343#L756-1 assume !(0 == ~E_6~0); 897312#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 897137#L346 assume !(1 == ~m_pc~0); 897138#L346-2 is_master_triggered_~__retres1~0#1 := 0; 897357#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 897349#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 897350#L861 assume !(0 != activate_threads_~tmp~1#1); 897711#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 897170#L365 assume !(1 == ~t1_pc~0); 897171#L365-2 is_transmit1_triggered_~__retres1~1#1 := 0; 897727#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 897121#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 897122#L869 assume !(0 != activate_threads_~tmp___0~0#1); 897160#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 897607#L384 assume !(1 == ~t2_pc~0); 897601#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 897602#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 897567#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 897078#L877 assume !(0 != activate_threads_~tmp___1~0#1); 897079#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 897439#L403 assume !(1 == ~t3_pc~0); 897440#L403-2 is_transmit3_triggered_~__retres1~3#1 := 0; 897641#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 897053#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 897054#L885 assume !(0 != activate_threads_~tmp___2~0#1); 897432#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 897433#L422 assume !(1 == ~t4_pc~0); 897562#L422-2 is_transmit4_triggered_~__retres1~4#1 := 0; 897563#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 897223#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 897224#L893 assume !(0 != activate_threads_~tmp___3~0#1); 897520#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 897091#L441 assume !(1 == ~t5_pc~0); 897092#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 897706#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 897360#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 897361#L901 assume !(0 != activate_threads_~tmp___4~0#1); 897528#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 897529#L460 assume !(1 == ~t6_pc~0); 897662#L460-2 is_transmit6_triggered_~__retres1~6#1 := 0; 897098#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 897099#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 897549#L909 assume !(0 != activate_threads_~tmp___5~0#1); 897659#L909-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 897506#L774 assume !(1 == ~M_E~0); 897507#L774-2 assume !(1 == ~T1_E~0); 897680#L779-1 assume !(1 == ~T2_E~0); 897408#L784-1 assume !(1 == ~T3_E~0); 897409#L789-1 assume !(1 == ~T4_E~0); 897155#L794-1 assume !(1 == ~T5_E~0); 897156#L799-1 assume !(1 == ~T6_E~0); 897800#L804-1 assume !(1 == ~E_M~0); 897801#L809-1 assume !(1 == ~E_1~0); 897492#L814-1 assume !(1 == ~E_2~0); 897057#L819-1 assume !(1 == ~E_3~0); 897058#L824-1 assume !(1 == ~E_4~0); 897557#L829-1 assume !(1 == ~E_5~0); 897668#L834-1 assume !(1 == ~E_6~0); 897297#L839-1 assume { :end_inline_reset_delta_events } true; 897298#L1065-2 [2022-12-13 19:41:47,204 INFO L750 eck$LassoCheckResult]: Loop: 897298#L1065-2 assume !false; 917420#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 917417#L671 assume !false; 917416#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 917414#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 917408#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 917407#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 917405#L582 assume !(0 != eval_~tmp~0#1); 917403#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 917402#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 917401#L696-3 assume !(0 == ~M_E~0); 917400#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 917398#L701-3 assume !(0 == ~T2_E~0); 917397#L706-3 assume !(0 == ~T3_E~0); 917396#L711-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 917395#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 917394#L721-3 assume !(0 == ~T6_E~0); 917393#L726-3 assume !(0 == ~E_M~0); 917391#L731-3 assume 0 == ~E_1~0;~E_1~0 := 1; 917389#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 917387#L741-3 assume 0 == ~E_3~0;~E_3~0 := 1; 917385#L746-3 assume !(0 == ~E_4~0); 917383#L751-3 assume 0 == ~E_5~0;~E_5~0 := 1; 917381#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 917379#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 917377#L346-24 assume !(1 == ~m_pc~0); 917375#L346-26 is_master_triggered_~__retres1~0#1 := 0; 917373#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 917371#is_master_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 917369#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 917367#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 917364#L365-24 assume !(1 == ~t1_pc~0); 917362#L365-26 is_transmit1_triggered_~__retres1~1#1 := 0; 917360#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 917358#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 917356#L869-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 917354#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 917352#L384-24 assume 1 == ~t2_pc~0; 917349#L385-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 917347#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 917345#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 917343#L877-24 assume !(0 != activate_threads_~tmp___1~0#1); 917341#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 917339#L403-24 assume !(1 == ~t3_pc~0); 917337#L403-26 is_transmit3_triggered_~__retres1~3#1 := 0; 917335#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 917333#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 917331#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 917327#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 917325#L422-24 assume !(1 == ~t4_pc~0); 917323#L422-26 is_transmit4_triggered_~__retres1~4#1 := 0; 917321#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 917318#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 917316#L893-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 917314#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 917312#L441-24 assume !(1 == ~t5_pc~0); 917308#L441-26 is_transmit5_triggered_~__retres1~5#1 := 0; 917306#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 917304#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 917302#L901-24 assume !(0 != activate_threads_~tmp___4~0#1); 917297#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 917295#L460-24 assume !(1 == ~t6_pc~0); 917293#L460-26 is_transmit6_triggered_~__retres1~6#1 := 0; 917289#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 917288#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 917287#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 917286#L909-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 917284#L774-3 assume !(1 == ~M_E~0); 917141#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 917283#L779-3 assume !(1 == ~T2_E~0); 917282#L784-3 assume !(1 == ~T3_E~0); 917280#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 917279#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 917278#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 917277#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 917276#L809-3 assume 1 == ~E_1~0;~E_1~0 := 2; 917275#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 917274#L819-3 assume !(1 == ~E_3~0); 917273#L824-3 assume !(1 == ~E_4~0); 917272#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 917271#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 917269#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 917264#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 917257#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 917255#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 917252#L1084 assume !(0 == start_simulation_~tmp~3#1); 917253#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 917442#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 917438#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 917436#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 917434#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 917430#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 917428#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 917426#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 897298#L1065-2 [2022-12-13 19:41:47,204 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:41:47,205 INFO L85 PathProgramCache]: Analyzing trace with hash -895696695, now seen corresponding path program 2 times [2022-12-13 19:41:47,205 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:41:47,205 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1524842674] [2022-12-13 19:41:47,205 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:41:47,205 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:41:47,214 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 19:41:47,214 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 19:41:47,222 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 19:41:47,259 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 19:41:47,259 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:41:47,260 INFO L85 PathProgramCache]: Analyzing trace with hash -324926847, now seen corresponding path program 2 times [2022-12-13 19:41:47,260 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:41:47,260 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1529964377] [2022-12-13 19:41:47,260 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:41:47,260 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:41:47,270 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:41:47,293 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:41:47,294 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:41:47,294 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1529964377] [2022-12-13 19:41:47,294 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1529964377] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:41:47,294 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:41:47,294 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:41:47,294 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1595217072] [2022-12-13 19:41:47,294 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:41:47,295 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 19:41:47,295 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 19:41:47,295 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 19:41:47,295 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 19:41:47,295 INFO L87 Difference]: Start difference. First operand 42340 states and 59483 transitions. cyclomatic complexity: 17159 Second operand has 3 states, 3 states have (on average 31.333333333333332) internal successors, (94), 3 states have internal predecessors, (94), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:41:47,571 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 19:41:47,572 INFO L93 Difference]: Finished difference Result 66423 states and 92904 transitions. [2022-12-13 19:41:47,572 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 66423 states and 92904 transitions. [2022-12-13 19:41:47,857 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 65832 [2022-12-13 19:41:48,052 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 66423 states to 66423 states and 92904 transitions. [2022-12-13 19:41:48,053 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 66423 [2022-12-13 19:41:48,097 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 66423 [2022-12-13 19:41:48,097 INFO L73 IsDeterministic]: Start isDeterministic. Operand 66423 states and 92904 transitions. [2022-12-13 19:41:48,136 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 19:41:48,137 INFO L218 hiAutomatonCegarLoop]: Abstraction has 66423 states and 92904 transitions. [2022-12-13 19:41:48,179 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 66423 states and 92904 transitions. [2022-12-13 19:41:48,679 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 66423 to 66351. [2022-12-13 19:41:48,718 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 66351 states, 66351 states have (on average 1.3991047610435412) internal successors, (92832), 66350 states have internal predecessors, (92832), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:41:48,839 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 66351 states to 66351 states and 92832 transitions. [2022-12-13 19:41:48,839 INFO L240 hiAutomatonCegarLoop]: Abstraction has 66351 states and 92832 transitions. [2022-12-13 19:41:48,840 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 19:41:48,840 INFO L428 stractBuchiCegarLoop]: Abstraction has 66351 states and 92832 transitions. [2022-12-13 19:41:48,840 INFO L335 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2022-12-13 19:41:48,840 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 66351 states and 92832 transitions. [2022-12-13 19:41:49,039 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 65760 [2022-12-13 19:41:49,039 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 19:41:49,039 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 19:41:49,040 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:41:49,040 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:41:49,041 INFO L748 eck$LassoCheckResult]: Stem: 1006162#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 1006163#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 1006347#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1006348#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1006536#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 1006051#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1006052#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1005884#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1005885#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1005858#L507-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1005859#L512-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1006029#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1006197#L696 assume !(0 == ~M_E~0); 1006198#L696-2 assume !(0 == ~T1_E~0); 1006544#L701-1 assume !(0 == ~T2_E~0); 1006546#L706-1 assume !(0 == ~T3_E~0); 1006313#L711-1 assume !(0 == ~T4_E~0); 1006085#L716-1 assume !(0 == ~T5_E~0); 1006086#L721-1 assume !(0 == ~T6_E~0); 1006269#L726-1 assume !(0 == ~E_M~0); 1006270#L731-1 assume !(0 == ~E_1~0); 1006234#L736-1 assume !(0 == ~E_2~0); 1006235#L741-1 assume 0 == ~E_3~0;~E_3~0 := 1; 1006325#L746-1 assume !(0 == ~E_4~0); 1006113#L751-1 assume !(0 == ~E_5~0); 1006114#L756-1 assume !(0 == ~E_6~0); 1006213#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1006713#L346 assume !(1 == ~m_pc~0); 1006131#L346-2 is_master_triggered_~__retres1~0#1 := 0; 1006132#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1006449#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1006566#L861 assume !(0 != activate_threads_~tmp~1#1); 1006505#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1006506#L365 assume !(1 == ~t1_pc~0); 1006710#L365-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1006709#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1005890#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1005891#L869 assume !(0 != activate_threads_~tmp___0~0#1); 1005931#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1006389#L384 assume !(1 == ~t2_pc~0); 1006384#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1006385#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1006349#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1006350#L877 assume !(0 != activate_threads_~tmp___1~0#1); 1006703#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1006702#L403 assume !(1 == ~t3_pc~0); 1006701#L403-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1006700#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1006699#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1006698#L885 assume !(0 != activate_threads_~tmp___2~0#1); 1006697#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1006696#L422 assume !(1 == ~t4_pc~0); 1006695#L422-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1006694#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1006693#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1006692#L893 assume !(0 != activate_threads_~tmp___3~0#1); 1006294#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1005860#L441 assume !(1 == ~t5_pc~0); 1005861#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1006499#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1006689#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1006687#L901 assume !(0 != activate_threads_~tmp___4~0#1); 1006303#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1006304#L460 assume !(1 == ~t6_pc~0); 1006453#L460-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1006685#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1006329#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1006330#L909 assume !(0 != activate_threads_~tmp___5~0#1); 1006450#L909-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1006680#L774 assume !(1 == ~M_E~0); 1006679#L774-2 assume !(1 == ~T1_E~0); 1006678#L779-1 assume !(1 == ~T2_E~0); 1006677#L784-1 assume !(1 == ~T3_E~0); 1006676#L789-1 assume !(1 == ~T4_E~0); 1006675#L794-1 assume !(1 == ~T5_E~0); 1006674#L799-1 assume !(1 == ~T6_E~0); 1006673#L804-1 assume !(1 == ~E_M~0); 1006672#L809-1 assume !(1 == ~E_1~0); 1006671#L814-1 assume !(1 == ~E_2~0); 1005826#L819-1 assume 1 == ~E_3~0;~E_3~0 := 2; 1005827#L824-1 assume !(1 == ~E_4~0); 1006338#L829-1 assume !(1 == ~E_5~0); 1006458#L834-1 assume !(1 == ~E_6~0); 1006067#L839-1 assume { :end_inline_reset_delta_events } true; 1006068#L1065-2 [2022-12-13 19:41:49,041 INFO L750 eck$LassoCheckResult]: Loop: 1006068#L1065-2 assume !false; 1032257#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1032254#L671 assume !false; 1032253#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1032251#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1032245#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1032244#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1032242#L582 assume !(0 != eval_~tmp~0#1); 1032243#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1032623#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1032621#L696-3 assume !(0 == ~M_E~0); 1032619#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1032617#L701-3 assume !(0 == ~T2_E~0); 1032615#L706-3 assume !(0 == ~T3_E~0); 1032613#L711-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1032611#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1032609#L721-3 assume !(0 == ~T6_E~0); 1032607#L726-3 assume !(0 == ~E_M~0); 1032605#L731-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1032603#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1032600#L741-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1032601#L746-3 assume !(0 == ~E_4~0); 1068723#L751-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1068721#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1068719#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1068717#L346-24 assume !(1 == ~m_pc~0); 1068715#L346-26 is_master_triggered_~__retres1~0#1 := 0; 1068713#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1068711#is_master_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1068709#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1033504#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1033503#L365-24 assume !(1 == ~t1_pc~0); 1033502#L365-26 is_transmit1_triggered_~__retres1~1#1 := 0; 1033500#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1033499#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1033498#L869-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1033496#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1033468#L384-24 assume !(1 == ~t2_pc~0); 1033462#L384-26 is_transmit2_triggered_~__retres1~2#1 := 0; 1033453#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1033437#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1033436#L877-24 assume !(0 != activate_threads_~tmp___1~0#1); 1033435#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1033433#L403-24 assume !(1 == ~t3_pc~0); 1033431#L403-26 is_transmit3_triggered_~__retres1~3#1 := 0; 1033429#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1033427#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1033425#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1033423#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1033421#L422-24 assume !(1 == ~t4_pc~0); 1033420#L422-26 is_transmit4_triggered_~__retres1~4#1 := 0; 1033419#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1033418#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1033417#L893-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1033415#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1033414#L441-24 assume 1 == ~t5_pc~0; 1033413#L442-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1033411#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1033409#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1033406#L901-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1033405#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1033404#L460-24 assume !(1 == ~t6_pc~0); 1033402#L460-26 is_transmit6_triggered_~__retres1~6#1 := 0; 1033399#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1033397#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1033395#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1033393#L909-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1032349#L774-3 assume !(1 == ~M_E~0); 1032345#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1032343#L779-3 assume !(1 == ~T2_E~0); 1032341#L784-3 assume !(1 == ~T3_E~0); 1032339#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1032337#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1032334#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1032332#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1032330#L809-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1032328#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1032326#L819-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1032323#L824-3 assume !(1 == ~E_4~0); 1032321#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1032319#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1032317#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1032312#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1032305#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1032303#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 1032300#L1084 assume !(0 == start_simulation_~tmp~3#1); 1032297#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1032278#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1032274#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1032272#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 1032270#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1032266#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1032264#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 1032262#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 1006068#L1065-2 [2022-12-13 19:41:49,041 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:41:49,041 INFO L85 PathProgramCache]: Analyzing trace with hash -1576815991, now seen corresponding path program 1 times [2022-12-13 19:41:49,041 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:41:49,042 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2038127637] [2022-12-13 19:41:49,042 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:41:49,042 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:41:49,049 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:41:49,085 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:41:49,085 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:41:49,085 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2038127637] [2022-12-13 19:41:49,085 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2038127637] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:41:49,085 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:41:49,086 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:41:49,086 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [228624809] [2022-12-13 19:41:49,086 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:41:49,086 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 19:41:49,086 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:41:49,087 INFO L85 PathProgramCache]: Analyzing trace with hash -990345027, now seen corresponding path program 1 times [2022-12-13 19:41:49,087 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:41:49,087 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [449628386] [2022-12-13 19:41:49,087 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:41:49,087 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:41:49,097 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:41:49,135 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:41:49,135 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:41:49,135 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [449628386] [2022-12-13 19:41:49,135 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [449628386] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:41:49,135 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:41:49,136 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-12-13 19:41:49,136 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1033552260] [2022-12-13 19:41:49,136 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:41:49,136 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 19:41:49,136 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 19:41:49,137 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 19:41:49,137 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 19:41:49,137 INFO L87 Difference]: Start difference. First operand 66351 states and 92832 transitions. cyclomatic complexity: 26497 Second operand has 4 states, 4 states have (on average 21.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:41:49,468 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 19:41:49,468 INFO L93 Difference]: Finished difference Result 90753 states and 126954 transitions. [2022-12-13 19:41:49,468 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 90753 states and 126954 transitions. [2022-12-13 19:41:49,810 INFO L131 ngComponentsAnalysis]: Automaton has 40 accepting balls. 87188 [2022-12-13 19:41:50,021 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 90753 states to 90753 states and 126954 transitions. [2022-12-13 19:41:50,021 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 90753 [2022-12-13 19:41:50,186 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 90753 [2022-12-13 19:41:50,186 INFO L73 IsDeterministic]: Start isDeterministic. Operand 90753 states and 126954 transitions. [2022-12-13 19:41:50,208 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 19:41:50,208 INFO L218 hiAutomatonCegarLoop]: Abstraction has 90753 states and 126954 transitions. [2022-12-13 19:41:50,238 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 90753 states and 126954 transitions. [2022-12-13 19:41:50,650 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 90753 to 64015. [2022-12-13 19:41:50,688 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 64015 states, 64015 states have (on average 1.3985159728188705) internal successors, (89526), 64014 states have internal predecessors, (89526), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:41:50,772 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 64015 states to 64015 states and 89526 transitions. [2022-12-13 19:41:50,773 INFO L240 hiAutomatonCegarLoop]: Abstraction has 64015 states and 89526 transitions. [2022-12-13 19:41:50,773 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 19:41:50,774 INFO L428 stractBuchiCegarLoop]: Abstraction has 64015 states and 89526 transitions. [2022-12-13 19:41:50,774 INFO L335 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2022-12-13 19:41:50,774 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 64015 states and 89526 transitions. [2022-12-13 19:41:50,926 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 63486 [2022-12-13 19:41:50,926 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 19:41:50,926 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 19:41:50,927 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:41:50,927 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:41:50,927 INFO L748 eck$LassoCheckResult]: Stem: 1163275#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 1163276#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 1163452#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1163453#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1163646#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 1163166#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1163167#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1163002#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1163003#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1162976#L507-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1162977#L512-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1163144#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1163309#L696 assume !(0 == ~M_E~0); 1163310#L696-2 assume !(0 == ~T1_E~0); 1163652#L701-1 assume !(0 == ~T2_E~0); 1163655#L706-1 assume !(0 == ~T3_E~0); 1163425#L711-1 assume !(0 == ~T4_E~0); 1163203#L716-1 assume !(0 == ~T5_E~0); 1163204#L721-1 assume !(0 == ~T6_E~0); 1163385#L726-1 assume !(0 == ~E_M~0); 1163386#L731-1 assume !(0 == ~E_1~0); 1163349#L736-1 assume !(0 == ~E_2~0); 1163350#L741-1 assume !(0 == ~E_3~0); 1163435#L746-1 assume !(0 == ~E_4~0); 1163226#L751-1 assume !(0 == ~E_5~0); 1163227#L756-1 assume !(0 == ~E_6~0); 1163200#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1163023#L346 assume !(1 == ~m_pc~0); 1163024#L346-2 is_master_triggered_~__retres1~0#1 := 0; 1163242#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1163234#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1163235#L861 assume !(0 != activate_threads_~tmp~1#1); 1163616#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1163056#L365 assume !(1 == ~t1_pc~0); 1163057#L365-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1163630#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1163007#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1163008#L869 assume !(0 != activate_threads_~tmp___0~0#1); 1163046#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1163496#L384 assume !(1 == ~t2_pc~0); 1163490#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1163491#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1163455#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1162964#L877 assume !(0 != activate_threads_~tmp___1~0#1); 1162965#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1163327#L403 assume !(1 == ~t3_pc~0); 1163328#L403-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1163539#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1162939#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1162940#L885 assume !(0 != activate_threads_~tmp___2~0#1); 1163318#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1163319#L422 assume !(1 == ~t4_pc~0); 1163450#L422-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1163451#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1163108#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1163109#L893 assume !(0 != activate_threads_~tmp___3~0#1); 1163408#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1162978#L441 assume !(1 == ~t5_pc~0); 1162979#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1163609#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1163245#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1163246#L901 assume !(0 != activate_threads_~tmp___4~0#1); 1163416#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1163417#L460 assume !(1 == ~t6_pc~0); 1163562#L460-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1162985#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1162986#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1163437#L909 assume !(0 != activate_threads_~tmp___5~0#1); 1163559#L909-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1163393#L774 assume !(1 == ~M_E~0); 1163394#L774-2 assume !(1 == ~T1_E~0); 1163580#L779-1 assume !(1 == ~T2_E~0); 1163294#L784-1 assume !(1 == ~T3_E~0); 1163295#L789-1 assume !(1 == ~T4_E~0); 1163041#L794-1 assume !(1 == ~T5_E~0); 1163042#L799-1 assume !(1 == ~T6_E~0); 1163698#L804-1 assume !(1 == ~E_M~0); 1163699#L809-1 assume !(1 == ~E_1~0); 1163380#L814-1 assume !(1 == ~E_2~0); 1162943#L819-1 assume !(1 == ~E_3~0); 1162944#L824-1 assume !(1 == ~E_4~0); 1163445#L829-1 assume !(1 == ~E_5~0); 1163567#L834-1 assume !(1 == ~E_6~0); 1163184#L839-1 assume { :end_inline_reset_delta_events } true; 1163185#L1065-2 [2022-12-13 19:41:50,927 INFO L750 eck$LassoCheckResult]: Loop: 1163185#L1065-2 assume !false; 1205652#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1205641#L671 assume !false; 1205637#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1205633#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1205626#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1205622#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1205620#L582 assume !(0 != eval_~tmp~0#1); 1205589#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1205554#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1205545#L696-3 assume !(0 == ~M_E~0); 1205537#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1205443#L701-3 assume !(0 == ~T2_E~0); 1205433#L706-3 assume !(0 == ~T3_E~0); 1205399#L711-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1205397#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1205370#L721-3 assume !(0 == ~T6_E~0); 1205360#L726-3 assume !(0 == ~E_M~0); 1205352#L731-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1205346#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1205333#L741-3 assume !(0 == ~E_3~0); 1205329#L746-3 assume !(0 == ~E_4~0); 1205326#L751-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1205324#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1205322#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1205320#L346-24 assume !(1 == ~m_pc~0); 1205318#L346-26 is_master_triggered_~__retres1~0#1 := 0; 1205316#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1205314#is_master_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1205312#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1205310#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1205308#L365-24 assume !(1 == ~t1_pc~0); 1205148#L365-26 is_transmit1_triggered_~__retres1~1#1 := 0; 1205146#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1205144#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1205142#L869-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1205140#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1205138#L384-24 assume 1 == ~t2_pc~0; 1205078#L385-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1205076#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1205074#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1205072#L877-24 assume !(0 != activate_threads_~tmp___1~0#1); 1205070#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1205068#L403-24 assume !(1 == ~t3_pc~0); 1205066#L403-26 is_transmit3_triggered_~__retres1~3#1 := 0; 1205064#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1205062#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1205060#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1205058#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1205056#L422-24 assume !(1 == ~t4_pc~0); 1205054#L422-26 is_transmit4_triggered_~__retres1~4#1 := 0; 1205052#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1205050#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1205048#L893-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1205046#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1205043#L441-24 assume 1 == ~t5_pc~0; 1205041#L442-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1205042#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1205288#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1205032#L901-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1205029#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1205026#L460-24 assume !(1 == ~t6_pc~0); 1205024#L460-26 is_transmit6_triggered_~__retres1~6#1 := 0; 1205022#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1205020#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1205018#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1205016#L909-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1205013#L774-3 assume !(1 == ~M_E~0); 1199650#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1205010#L779-3 assume !(1 == ~T2_E~0); 1205008#L784-3 assume !(1 == ~T3_E~0); 1205006#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1205004#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1204963#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1204955#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1204954#L809-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1204953#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1204951#L819-3 assume !(1 == ~E_3~0); 1204908#L824-3 assume !(1 == ~E_4~0); 1204899#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1204803#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1204772#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1204751#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1204742#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1204737#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 1204735#L1084 assume !(0 == start_simulation_~tmp~3#1); 1204736#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1205807#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1205803#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1205710#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 1205702#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1205694#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1205683#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 1205676#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 1163185#L1065-2 [2022-12-13 19:41:50,928 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:41:50,928 INFO L85 PathProgramCache]: Analyzing trace with hash -895696695, now seen corresponding path program 3 times [2022-12-13 19:41:50,928 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:41:50,928 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [278419626] [2022-12-13 19:41:50,928 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:41:50,928 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:41:50,934 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 19:41:50,935 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 19:41:50,939 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 19:41:50,949 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 19:41:50,949 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:41:50,949 INFO L85 PathProgramCache]: Analyzing trace with hash -1931737412, now seen corresponding path program 1 times [2022-12-13 19:41:50,949 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:41:50,949 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1598451954] [2022-12-13 19:41:50,949 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:41:50,949 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:41:50,955 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:41:50,984 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:41:50,984 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:41:50,984 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1598451954] [2022-12-13 19:41:50,984 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1598451954] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:41:50,984 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:41:50,984 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-12-13 19:41:50,984 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2141800349] [2022-12-13 19:41:50,984 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:41:50,985 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 19:41:50,985 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 19:41:50,985 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-12-13 19:41:50,985 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-12-13 19:41:50,985 INFO L87 Difference]: Start difference. First operand 64015 states and 89526 transitions. cyclomatic complexity: 25527 Second operand has 5 states, 5 states have (on average 18.8) internal successors, (94), 5 states have internal predecessors, (94), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:41:51,357 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 19:41:51,357 INFO L93 Difference]: Finished difference Result 113123 states and 156492 transitions. [2022-12-13 19:41:51,358 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 113123 states and 156492 transitions. [2022-12-13 19:41:51,802 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 112154 [2022-12-13 19:41:52,048 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 113123 states to 113123 states and 156492 transitions. [2022-12-13 19:41:52,048 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 113123 [2022-12-13 19:41:52,123 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 113123 [2022-12-13 19:41:52,123 INFO L73 IsDeterministic]: Start isDeterministic. Operand 113123 states and 156492 transitions. [2022-12-13 19:41:52,177 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 19:41:52,177 INFO L218 hiAutomatonCegarLoop]: Abstraction has 113123 states and 156492 transitions. [2022-12-13 19:41:52,249 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 113123 states and 156492 transitions. [2022-12-13 19:41:52,818 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 113123 to 64555. [2022-12-13 19:41:52,857 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 64555 states, 64555 states have (on average 1.395182402602432) internal successors, (90066), 64554 states have internal predecessors, (90066), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:41:52,947 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 64555 states to 64555 states and 90066 transitions. [2022-12-13 19:41:52,947 INFO L240 hiAutomatonCegarLoop]: Abstraction has 64555 states and 90066 transitions. [2022-12-13 19:41:52,947 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2022-12-13 19:41:52,948 INFO L428 stractBuchiCegarLoop]: Abstraction has 64555 states and 90066 transitions. [2022-12-13 19:41:52,948 INFO L335 stractBuchiCegarLoop]: ======== Iteration 23 ============ [2022-12-13 19:41:52,948 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 64555 states and 90066 transitions. [2022-12-13 19:41:53,097 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 64026 [2022-12-13 19:41:53,097 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 19:41:53,098 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 19:41:53,098 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:41:53,098 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:41:53,099 INFO L748 eck$LassoCheckResult]: Stem: 1340429#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 1340430#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 1340613#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1340614#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1340799#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 1340319#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1340320#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1340155#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1340156#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1340128#L507-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1340129#L512-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1340297#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1340466#L696 assume !(0 == ~M_E~0); 1340467#L696-2 assume !(0 == ~T1_E~0); 1340811#L701-1 assume !(0 == ~T2_E~0); 1340813#L706-1 assume !(0 == ~T3_E~0); 1340584#L711-1 assume !(0 == ~T4_E~0); 1340354#L716-1 assume !(0 == ~T5_E~0); 1340355#L721-1 assume !(0 == ~T6_E~0); 1340539#L726-1 assume !(0 == ~E_M~0); 1340540#L731-1 assume !(0 == ~E_1~0); 1340502#L736-1 assume !(0 == ~E_2~0); 1340503#L741-1 assume !(0 == ~E_3~0); 1340595#L746-1 assume !(0 == ~E_4~0); 1340381#L751-1 assume !(0 == ~E_5~0); 1340382#L756-1 assume !(0 == ~E_6~0); 1340351#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1340177#L346 assume !(1 == ~m_pc~0); 1340178#L346-2 is_master_triggered_~__retres1~0#1 := 0; 1340397#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1340389#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1340390#L861 assume !(0 != activate_threads_~tmp~1#1); 1340766#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1340210#L365 assume !(1 == ~t1_pc~0); 1340211#L365-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1340785#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1340163#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1340164#L869 assume !(0 != activate_threads_~tmp___0~0#1); 1340198#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1340660#L384 assume !(1 == ~t2_pc~0); 1340656#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1340657#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1340620#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1340119#L877 assume !(0 != activate_threads_~tmp___1~0#1); 1340120#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1340481#L403 assume !(1 == ~t3_pc~0); 1340482#L403-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1340698#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1340092#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1340093#L885 assume !(0 != activate_threads_~tmp___2~0#1); 1340476#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1340477#L422 assume !(1 == ~t4_pc~0); 1340611#L422-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1340612#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1340263#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1340264#L893 assume !(0 != activate_threads_~tmp___3~0#1); 1340563#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1340130#L441 assume !(1 == ~t5_pc~0); 1340131#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1340762#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1340401#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1340402#L901 assume !(0 != activate_threads_~tmp___4~0#1); 1340576#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1340577#L460 assume !(1 == ~t6_pc~0); 1340721#L460-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1340139#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1340140#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1340597#L909 assume !(0 != activate_threads_~tmp___5~0#1); 1340716#L909-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1340549#L774 assume !(1 == ~M_E~0); 1340550#L774-2 assume !(1 == ~T1_E~0); 1340736#L779-1 assume !(1 == ~T2_E~0); 1340446#L784-1 assume !(1 == ~T3_E~0); 1340447#L789-1 assume !(1 == ~T4_E~0); 1340193#L794-1 assume !(1 == ~T5_E~0); 1340194#L799-1 assume !(1 == ~T6_E~0); 1340864#L804-1 assume !(1 == ~E_M~0); 1340865#L809-1 assume !(1 == ~E_1~0); 1340536#L814-1 assume !(1 == ~E_2~0); 1340098#L819-1 assume !(1 == ~E_3~0); 1340099#L824-1 assume !(1 == ~E_4~0); 1340606#L829-1 assume !(1 == ~E_5~0); 1340724#L834-1 assume !(1 == ~E_6~0); 1340338#L839-1 assume { :end_inline_reset_delta_events } true; 1340339#L1065-2 [2022-12-13 19:41:53,099 INFO L750 eck$LassoCheckResult]: Loop: 1340339#L1065-2 assume !false; 1357861#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1356997#L671 assume !false; 1356545#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1356244#L530 assume !(0 == ~m_st~0); 1356245#L534 assume !(0 == ~t1_st~0); 1356240#L538 assume !(0 == ~t2_st~0); 1356241#L542 assume !(0 == ~t3_st~0); 1356243#L546 assume !(0 == ~t4_st~0); 1356238#L550 assume !(0 == ~t5_st~0); 1356239#L554 assume !(0 == ~t6_st~0);exists_runnable_thread_~__retres1~7#1 := 0; 1356242#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1355497#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1355498#L582 assume !(0 != eval_~tmp~0#1); 1377250#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1385344#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1385343#L696-3 assume !(0 == ~M_E~0); 1385342#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1385341#L701-3 assume !(0 == ~T2_E~0); 1385340#L706-3 assume !(0 == ~T3_E~0); 1385339#L711-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1385338#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1385337#L721-3 assume !(0 == ~T6_E~0); 1385336#L726-3 assume !(0 == ~E_M~0); 1385335#L731-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1385334#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1385333#L741-3 assume !(0 == ~E_3~0); 1385332#L746-3 assume !(0 == ~E_4~0); 1385331#L751-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1385330#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1385329#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1385328#L346-24 assume !(1 == ~m_pc~0); 1385327#L346-26 is_master_triggered_~__retres1~0#1 := 0; 1385326#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1385325#is_master_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1385324#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1385323#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1385322#L365-24 assume !(1 == ~t1_pc~0); 1385321#L365-26 is_transmit1_triggered_~__retres1~1#1 := 0; 1385320#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1385319#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1385318#L869-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1385317#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1385316#L384-24 assume !(1 == ~t2_pc~0); 1385315#L384-26 is_transmit2_triggered_~__retres1~2#1 := 0; 1385313#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1385312#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1385311#L877-24 assume !(0 != activate_threads_~tmp___1~0#1); 1385310#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1385309#L403-24 assume !(1 == ~t3_pc~0); 1385308#L403-26 is_transmit3_triggered_~__retres1~3#1 := 0; 1385307#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1385306#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1385305#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1385304#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1385303#L422-24 assume !(1 == ~t4_pc~0); 1385302#L422-26 is_transmit4_triggered_~__retres1~4#1 := 0; 1385301#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1385300#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1385299#L893-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1385298#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1385297#L441-24 assume 1 == ~t5_pc~0; 1385296#L442-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1385295#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1357994#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1357995#L901-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1357982#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1357983#L460-24 assume !(1 == ~t6_pc~0); 1357974#L460-26 is_transmit6_triggered_~__retres1~6#1 := 0; 1357975#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1357966#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1357967#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1357958#L909-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1357959#L774-3 assume !(1 == ~M_E~0); 1357950#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1357951#L779-3 assume !(1 == ~T2_E~0); 1357946#L784-3 assume !(1 == ~T3_E~0); 1357947#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1357942#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1357943#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1357938#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1357939#L809-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1357934#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1357935#L819-3 assume !(1 == ~E_3~0); 1357930#L824-3 assume !(1 == ~E_4~0); 1357931#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1357926#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1357927#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1357922#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1357912#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1357909#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 1357904#L1084 assume !(0 == start_simulation_~tmp~3#1); 1357903#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1357895#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1357892#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1357885#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 1357886#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1357879#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1357880#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 1357872#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 1340339#L1065-2 [2022-12-13 19:41:53,099 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:41:53,099 INFO L85 PathProgramCache]: Analyzing trace with hash -895696695, now seen corresponding path program 4 times [2022-12-13 19:41:53,099 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:41:53,100 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [535449733] [2022-12-13 19:41:53,100 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:41:53,100 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:41:53,107 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 19:41:53,108 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 19:41:53,111 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 19:41:53,120 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 19:41:53,121 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:41:53,121 INFO L85 PathProgramCache]: Analyzing trace with hash 335406220, now seen corresponding path program 1 times [2022-12-13 19:41:53,121 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:41:53,121 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [125957022] [2022-12-13 19:41:53,121 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:41:53,121 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:41:53,128 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:41:53,177 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:41:53,177 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:41:53,177 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [125957022] [2022-12-13 19:41:53,178 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [125957022] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:41:53,178 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:41:53,178 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-12-13 19:41:53,178 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [626065321] [2022-12-13 19:41:53,178 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:41:53,178 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 19:41:53,178 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 19:41:53,179 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-12-13 19:41:53,179 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-12-13 19:41:53,179 INFO L87 Difference]: Start difference. First operand 64555 states and 90066 transitions. cyclomatic complexity: 25527 Second operand has 5 states, 5 states have (on average 20.0) internal successors, (100), 5 states have internal predecessors, (100), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:41:53,587 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 19:41:53,588 INFO L93 Difference]: Finished difference Result 114443 states and 158821 transitions. [2022-12-13 19:41:53,588 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 114443 states and 158821 transitions. [2022-12-13 19:41:54,019 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 113786 [2022-12-13 19:41:54,596 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 114443 states to 114443 states and 158821 transitions. [2022-12-13 19:41:54,596 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 114443 [2022-12-13 19:41:54,635 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 114443 [2022-12-13 19:41:54,636 INFO L73 IsDeterministic]: Start isDeterministic. Operand 114443 states and 158821 transitions. [2022-12-13 19:41:54,675 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 19:41:54,675 INFO L218 hiAutomatonCegarLoop]: Abstraction has 114443 states and 158821 transitions. [2022-12-13 19:41:54,715 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 114443 states and 158821 transitions. [2022-12-13 19:41:55,482 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 114443 to 65659. [2022-12-13 19:41:55,528 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 65659 states, 65659 states have (on average 1.3809074155865912) internal successors, (90669), 65658 states have internal predecessors, (90669), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:41:55,686 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 65659 states to 65659 states and 90669 transitions. [2022-12-13 19:41:55,687 INFO L240 hiAutomatonCegarLoop]: Abstraction has 65659 states and 90669 transitions. [2022-12-13 19:41:55,687 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-12-13 19:41:55,688 INFO L428 stractBuchiCegarLoop]: Abstraction has 65659 states and 90669 transitions. [2022-12-13 19:41:55,688 INFO L335 stractBuchiCegarLoop]: ======== Iteration 24 ============ [2022-12-13 19:41:55,688 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 65659 states and 90669 transitions. [2022-12-13 19:41:55,881 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 65130 [2022-12-13 19:41:55,881 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 19:41:55,882 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 19:41:55,883 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:41:55,883 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:41:55,883 INFO L748 eck$LassoCheckResult]: Stem: 1519443#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 1519444#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 1519629#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1519630#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1519825#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 1519333#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1519334#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1519165#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1519166#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1519139#L507-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1519140#L512-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1519311#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1519481#L696 assume !(0 == ~M_E~0); 1519482#L696-2 assume !(0 == ~T1_E~0); 1519835#L701-1 assume !(0 == ~T2_E~0); 1519837#L706-1 assume !(0 == ~T3_E~0); 1519600#L711-1 assume !(0 == ~T4_E~0); 1519368#L716-1 assume !(0 == ~T5_E~0); 1519369#L721-1 assume !(0 == ~T6_E~0); 1519554#L726-1 assume !(0 == ~E_M~0); 1519555#L731-1 assume !(0 == ~E_1~0); 1519518#L736-1 assume !(0 == ~E_2~0); 1519519#L741-1 assume !(0 == ~E_3~0); 1519611#L746-1 assume !(0 == ~E_4~0); 1519393#L751-1 assume !(0 == ~E_5~0); 1519394#L756-1 assume !(0 == ~E_6~0); 1519365#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1519187#L346 assume !(1 == ~m_pc~0); 1519188#L346-2 is_master_triggered_~__retres1~0#1 := 0; 1519410#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1519402#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1519403#L861 assume !(0 != activate_threads_~tmp~1#1); 1519791#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1519222#L365 assume !(1 == ~t1_pc~0); 1519223#L365-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1519809#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1519171#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1519172#L869 assume !(0 != activate_threads_~tmp___0~0#1); 1519212#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1519674#L384 assume !(1 == ~t2_pc~0); 1519669#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1519670#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1519632#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1519128#L877 assume !(0 != activate_threads_~tmp___1~0#1); 1519129#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1519497#L403 assume !(1 == ~t3_pc~0); 1519498#L403-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1519717#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1519103#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1519104#L885 assume !(0 != activate_threads_~tmp___2~0#1); 1519490#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1519491#L422 assume !(1 == ~t4_pc~0); 1519627#L422-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1519628#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1519276#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1519277#L893 assume !(0 != activate_threads_~tmp___3~0#1); 1519582#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1519141#L441 assume !(1 == ~t5_pc~0); 1519142#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1519784#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1519413#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1519414#L901 assume !(0 != activate_threads_~tmp___4~0#1); 1519590#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1519591#L460 assume !(1 == ~t6_pc~0); 1519740#L460-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1519148#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1519149#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1519613#L909 assume !(0 != activate_threads_~tmp___5~0#1); 1519735#L909-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1519566#L774 assume !(1 == ~M_E~0); 1519567#L774-2 assume !(1 == ~T1_E~0); 1519756#L779-1 assume !(1 == ~T2_E~0); 1519464#L784-1 assume !(1 == ~T3_E~0); 1519465#L789-1 assume !(1 == ~T4_E~0); 1519207#L794-1 assume !(1 == ~T5_E~0); 1519208#L799-1 assume !(1 == ~T6_E~0); 1519889#L804-1 assume !(1 == ~E_M~0); 1519890#L809-1 assume !(1 == ~E_1~0); 1519549#L814-1 assume !(1 == ~E_2~0); 1519107#L819-1 assume !(1 == ~E_3~0); 1519108#L824-1 assume !(1 == ~E_4~0); 1519621#L829-1 assume !(1 == ~E_5~0); 1519745#L834-1 assume !(1 == ~E_6~0); 1519349#L839-1 assume { :end_inline_reset_delta_events } true; 1519350#L1065-2 [2022-12-13 19:41:55,883 INFO L750 eck$LassoCheckResult]: Loop: 1519350#L1065-2 assume !false; 1542502#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1542499#L671 assume !false; 1542498#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1542497#L530 assume !(0 == ~m_st~0); 1542496#L534 assume !(0 == ~t1_st~0); 1542495#L538 assume !(0 == ~t2_st~0); 1542494#L542 assume !(0 == ~t3_st~0); 1542493#L546 assume !(0 == ~t4_st~0); 1542492#L550 assume !(0 == ~t5_st~0); 1542490#L554 assume !(0 == ~t6_st~0);exists_runnable_thread_~__retres1~7#1 := 0; 1542489#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1542488#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1542487#L582 assume !(0 != eval_~tmp~0#1); 1531411#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1531409#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1531407#L696-3 assume !(0 == ~M_E~0); 1531405#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1531403#L701-3 assume !(0 == ~T2_E~0); 1531401#L706-3 assume !(0 == ~T3_E~0); 1531399#L711-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1531397#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1531395#L721-3 assume !(0 == ~T6_E~0); 1531393#L726-3 assume !(0 == ~E_M~0); 1531391#L731-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1531389#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1531387#L741-3 assume !(0 == ~E_3~0); 1531385#L746-3 assume !(0 == ~E_4~0); 1531383#L751-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1531381#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1531371#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1531367#L346-24 assume !(1 == ~m_pc~0); 1531363#L346-26 is_master_triggered_~__retres1~0#1 := 0; 1531358#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1531354#is_master_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1531350#L861-24 assume !(0 != activate_threads_~tmp~1#1); 1531346#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1531342#L365-24 assume !(1 == ~t1_pc~0); 1531338#L365-26 is_transmit1_triggered_~__retres1~1#1 := 0; 1531335#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1531331#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1531327#L869-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1531324#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1531320#L384-24 assume !(1 == ~t2_pc~0); 1531316#L384-26 is_transmit2_triggered_~__retres1~2#1 := 0; 1531310#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1531306#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1531300#L877-24 assume !(0 != activate_threads_~tmp___1~0#1); 1531295#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1531291#L403-24 assume !(1 == ~t3_pc~0); 1531287#L403-26 is_transmit3_triggered_~__retres1~3#1 := 0; 1531283#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1531277#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1531271#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1531265#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1531259#L422-24 assume !(1 == ~t4_pc~0); 1531253#L422-26 is_transmit4_triggered_~__retres1~4#1 := 0; 1531247#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1531240#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1531234#L893-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1531229#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1531223#L441-24 assume !(1 == ~t5_pc~0); 1531217#L441-26 is_transmit5_triggered_~__retres1~5#1 := 0; 1531207#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1531198#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1531188#L901-24 assume !(0 != activate_threads_~tmp___4~0#1); 1531177#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1531169#L460-24 assume !(1 == ~t6_pc~0); 1531160#L460-26 is_transmit6_triggered_~__retres1~6#1 := 0; 1531152#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1531144#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1531137#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1531130#L909-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1531123#L774-3 assume !(1 == ~M_E~0); 1531114#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1531108#L779-3 assume !(1 == ~T2_E~0); 1531099#L784-3 assume !(1 == ~T3_E~0); 1531089#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1531081#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1531074#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1531068#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1531062#L809-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1531056#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1530903#L819-3 assume !(1 == ~E_3~0); 1530895#L824-3 assume !(1 == ~E_4~0); 1530887#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1530879#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1530871#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1530872#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1535763#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1535762#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 1535759#L1084 assume !(0 == start_simulation_~tmp~3#1); 1535761#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1542511#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1542508#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1542507#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 1542506#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1542505#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1542504#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 1542503#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 1519350#L1065-2 [2022-12-13 19:41:55,884 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:41:55,884 INFO L85 PathProgramCache]: Analyzing trace with hash -895696695, now seen corresponding path program 5 times [2022-12-13 19:41:55,884 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:41:55,884 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1748707026] [2022-12-13 19:41:55,884 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:41:55,884 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:41:55,894 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 19:41:55,895 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 19:41:55,901 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 19:41:55,911 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 19:41:55,912 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:41:55,912 INFO L85 PathProgramCache]: Analyzing trace with hash 1143259793, now seen corresponding path program 1 times [2022-12-13 19:41:55,912 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:41:55,912 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [598846983] [2022-12-13 19:41:55,912 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:41:55,912 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:41:55,921 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:41:55,940 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:41:55,940 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:41:55,941 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [598846983] [2022-12-13 19:41:55,941 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [598846983] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:41:55,941 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:41:55,941 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:41:55,941 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1182342651] [2022-12-13 19:41:55,941 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:41:55,941 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 19:41:55,941 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 19:41:55,941 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 19:41:55,942 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 19:41:55,942 INFO L87 Difference]: Start difference. First operand 65659 states and 90669 transitions. cyclomatic complexity: 25026 Second operand has 3 states, 3 states have (on average 33.333333333333336) internal successors, (100), 3 states have internal predecessors, (100), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:41:56,271 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 19:41:56,271 INFO L93 Difference]: Finished difference Result 100149 states and 136496 transitions. [2022-12-13 19:41:56,271 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 100149 states and 136496 transitions. [2022-12-13 19:41:56,596 INFO L131 ngComponentsAnalysis]: Automaton has 30 accepting balls. 99626 [2022-12-13 19:41:56,794 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 100149 states to 100149 states and 136496 transitions. [2022-12-13 19:41:56,794 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 100149 [2022-12-13 19:41:56,838 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 100149 [2022-12-13 19:41:56,838 INFO L73 IsDeterministic]: Start isDeterministic. Operand 100149 states and 136496 transitions. [2022-12-13 19:41:56,877 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 19:41:56,877 INFO L218 hiAutomatonCegarLoop]: Abstraction has 100149 states and 136496 transitions. [2022-12-13 19:41:56,922 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 100149 states and 136496 transitions. [2022-12-13 19:41:57,586 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 100149 to 97285. [2022-12-13 19:41:57,642 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 97285 states, 97285 states have (on average 1.3648969522536876) internal successors, (132784), 97284 states have internal predecessors, (132784), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:41:57,762 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 97285 states to 97285 states and 132784 transitions. [2022-12-13 19:41:57,762 INFO L240 hiAutomatonCegarLoop]: Abstraction has 97285 states and 132784 transitions. [2022-12-13 19:41:57,762 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 19:41:57,763 INFO L428 stractBuchiCegarLoop]: Abstraction has 97285 states and 132784 transitions. [2022-12-13 19:41:57,763 INFO L335 stractBuchiCegarLoop]: ======== Iteration 25 ============ [2022-12-13 19:41:57,763 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 97285 states and 132784 transitions. [2022-12-13 19:41:57,983 INFO L131 ngComponentsAnalysis]: Automaton has 30 accepting balls. 96762 [2022-12-13 19:41:57,983 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 19:41:57,983 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 19:41:57,983 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:41:57,983 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:41:57,984 INFO L748 eck$LassoCheckResult]: Stem: 1685261#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 1685262#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 1685447#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1685448#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1685641#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 1685150#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1685151#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1684982#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1684983#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1684955#L507-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1684956#L512-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1685128#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1685296#L696 assume !(0 == ~M_E~0); 1685297#L696-2 assume !(0 == ~T1_E~0); 1685645#L701-1 assume !(0 == ~T2_E~0); 1685647#L706-1 assume !(0 == ~T3_E~0); 1685412#L711-1 assume !(0 == ~T4_E~0); 1685189#L716-1 assume !(0 == ~T5_E~0); 1685190#L721-1 assume !(0 == ~T6_E~0); 1685367#L726-1 assume !(0 == ~E_M~0); 1685368#L731-1 assume !(0 == ~E_1~0); 1685334#L736-1 assume !(0 == ~E_2~0); 1685335#L741-1 assume !(0 == ~E_3~0); 1685425#L746-1 assume !(0 == ~E_4~0); 1685213#L751-1 assume !(0 == ~E_5~0); 1685214#L756-1 assume !(0 == ~E_6~0); 1685186#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1685003#L346 assume !(1 == ~m_pc~0); 1685004#L346-2 is_master_triggered_~__retres1~0#1 := 0; 1685230#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1685222#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1685223#L861 assume !(0 != activate_threads_~tmp~1#1); 1685604#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1685038#L365 assume !(1 == ~t1_pc~0); 1685039#L365-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1685623#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1684987#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1684988#L869 assume !(0 != activate_threads_~tmp___0~0#1); 1685028#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1685492#L384 assume !(1 == ~t2_pc~0); 1685486#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1685487#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1685449#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1684943#L877 assume !(0 != activate_threads_~tmp___1~0#1); 1684944#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1685312#L403 assume !(1 == ~t3_pc~0); 1685313#L403-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1685530#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1684918#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1684919#L885 assume !(0 != activate_threads_~tmp___2~0#1); 1685305#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1685306#L422 assume !(1 == ~t4_pc~0); 1685445#L422-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1685446#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1685091#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1685092#L893 assume !(0 != activate_threads_~tmp___3~0#1); 1685392#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1684957#L441 assume !(1 == ~t5_pc~0); 1684958#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1685597#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1685233#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1685234#L901 assume !(0 != activate_threads_~tmp___4~0#1); 1685402#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1685403#L460 assume !(1 == ~t6_pc~0); 1685552#L460-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1684964#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1684965#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1685427#L909 assume !(0 != activate_threads_~tmp___5~0#1); 1685549#L909-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1685377#L774 assume !(1 == ~M_E~0); 1685378#L774-2 assume !(1 == ~T1_E~0); 1685569#L779-1 assume !(1 == ~T2_E~0); 1685281#L784-1 assume !(1 == ~T3_E~0); 1685282#L789-1 assume !(1 == ~T4_E~0); 1685022#L794-1 assume !(1 == ~T5_E~0); 1685023#L799-1 assume !(1 == ~T6_E~0); 1685690#L804-1 assume !(1 == ~E_M~0); 1685691#L809-1 assume !(1 == ~E_1~0); 1685363#L814-1 assume !(1 == ~E_2~0); 1684922#L819-1 assume !(1 == ~E_3~0); 1684923#L824-1 assume !(1 == ~E_4~0); 1685435#L829-1 assume !(1 == ~E_5~0); 1685558#L834-1 assume !(1 == ~E_6~0); 1685167#L839-1 assume { :end_inline_reset_delta_events } true; 1685168#L1065-2 assume !false; 1699518#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1699511#L671 [2022-12-13 19:41:57,984 INFO L750 eck$LassoCheckResult]: Loop: 1699511#L671 assume !false; 1699507#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1699502#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1699498#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1699494#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1699489#L582 assume 0 != eval_~tmp~0#1; 1699477#L582-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 1699478#L590 assume !(0 != eval_~tmp_ndt_1~0#1); 1699459#L587 assume !(0 == ~t1_st~0); 1693877#L601 assume !(0 == ~t2_st~0); 1699447#L615 assume !(0 == ~t3_st~0); 1692561#L629 assume !(0 == ~t4_st~0); 1704366#L643 assume !(0 == ~t5_st~0); 1714465#L657 assume !(0 == ~t6_st~0); 1699511#L671 [2022-12-13 19:41:57,984 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:41:57,984 INFO L85 PathProgramCache]: Analyzing trace with hash -1771052117, now seen corresponding path program 1 times [2022-12-13 19:41:57,984 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:41:57,984 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1543972977] [2022-12-13 19:41:57,984 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:41:57,985 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:41:58,131 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 19:41:58,132 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 19:41:58,136 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 19:41:58,149 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 19:41:58,150 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:41:58,150 INFO L85 PathProgramCache]: Analyzing trace with hash -919284357, now seen corresponding path program 1 times [2022-12-13 19:41:58,150 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:41:58,150 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [89983181] [2022-12-13 19:41:58,150 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:41:58,151 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:41:58,153 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 19:41:58,153 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 19:41:58,157 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 19:41:58,160 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 19:41:58,161 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:41:58,161 INFO L85 PathProgramCache]: Analyzing trace with hash 743442341, now seen corresponding path program 1 times [2022-12-13 19:41:58,161 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:41:58,161 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1956203663] [2022-12-13 19:41:58,161 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:41:58,162 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:41:58,170 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:41:58,187 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:41:58,187 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:41:58,187 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1956203663] [2022-12-13 19:41:58,187 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1956203663] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:41:58,187 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:41:58,187 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:41:58,188 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1685561789] [2022-12-13 19:41:58,188 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:41:58,264 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 19:41:58,265 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 19:41:58,265 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 19:41:58,265 INFO L87 Difference]: Start difference. First operand 97285 states and 132784 transitions. cyclomatic complexity: 35529 Second operand has 3 states, 3 states have (on average 33.333333333333336) internal successors, (100), 3 states have internal predecessors, (100), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:41:58,620 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 19:41:58,620 INFO L93 Difference]: Finished difference Result 183806 states and 248665 transitions. [2022-12-13 19:41:58,621 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 183806 states and 248665 transitions. [2022-12-13 19:41:59,322 INFO L131 ngComponentsAnalysis]: Automaton has 54 accepting balls. 177470 [2022-12-13 19:41:59,641 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 183806 states to 183806 states and 248665 transitions. [2022-12-13 19:41:59,641 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 183806 [2022-12-13 19:41:59,708 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 183806 [2022-12-13 19:41:59,708 INFO L73 IsDeterministic]: Start isDeterministic. Operand 183806 states and 248665 transitions. [2022-12-13 19:41:59,786 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 19:41:59,786 INFO L218 hiAutomatonCegarLoop]: Abstraction has 183806 states and 248665 transitions. [2022-12-13 19:41:59,862 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 183806 states and 248665 transitions. [2022-12-13 19:42:01,114 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 183806 to 179559. [2022-12-13 19:42:01,216 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 179559 states, 179559 states have (on average 1.3548137381027963) internal successors, (243269), 179558 states have internal predecessors, (243269), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:42:01,625 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 179559 states to 179559 states and 243269 transitions. [2022-12-13 19:42:01,625 INFO L240 hiAutomatonCegarLoop]: Abstraction has 179559 states and 243269 transitions. [2022-12-13 19:42:01,626 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 19:42:01,626 INFO L428 stractBuchiCegarLoop]: Abstraction has 179559 states and 243269 transitions. [2022-12-13 19:42:01,626 INFO L335 stractBuchiCegarLoop]: ======== Iteration 26 ============ [2022-12-13 19:42:01,626 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 179559 states and 243269 transitions. [2022-12-13 19:42:01,998 INFO L131 ngComponentsAnalysis]: Automaton has 54 accepting balls. 173223 [2022-12-13 19:42:01,999 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 19:42:01,999 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 19:42:01,999 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:42:01,999 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:42:01,999 INFO L748 eck$LassoCheckResult]: Stem: 1966369#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 1966370#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 1966569#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1966570#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1966796#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 1966247#L487-2 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 1966248#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1966470#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1966287#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1966288#L507-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1966224#L512-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1966225#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1966403#L696 assume !(0 == ~M_E~0); 1966404#L696-2 assume !(0 == ~T1_E~0); 1966819#L701-1 assume !(0 == ~T2_E~0); 1966820#L706-1 assume !(0 == ~T3_E~0); 1966530#L711-1 assume !(0 == ~T4_E~0); 1966531#L716-1 assume !(0 == ~T5_E~0); 1966874#L721-1 assume !(0 == ~T6_E~0); 1966875#L726-1 assume !(0 == ~E_M~0); 1966753#L731-1 assume !(0 == ~E_1~0); 1966754#L736-1 assume !(0 == ~E_2~0); 1966544#L741-1 assume !(0 == ~E_3~0); 1966545#L746-1 assume !(0 == ~E_4~0); 1966316#L751-1 assume !(0 == ~E_5~0); 1966317#L756-1 assume !(0 == ~E_6~0); 1966283#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1966284#L346 assume !(1 == ~m_pc~0); 1966336#L346-2 is_master_triggered_~__retres1~0#1 := 0; 1966337#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1966325#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1966326#L861 assume !(0 != activate_threads_~tmp~1#1); 1966751#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1966752#L365 assume !(1 == ~t1_pc~0); 1966772#L365-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1966773#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1966089#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1966090#L869 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1966126#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1966777#L384 assume !(1 == ~t2_pc~0); 1966778#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1966911#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1966912#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1966043#L877 assume !(0 != activate_threads_~tmp___1~0#1); 1966044#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1966419#L403 assume !(1 == ~t3_pc~0); 1966420#L403-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1966954#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1966955#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1966675#L885 assume !(0 != activate_threads_~tmp___2~0#1); 1966676#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1966803#L422 assume !(1 == ~t4_pc~0); 1966804#L422-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1966706#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1966707#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1966725#L893 assume !(0 != activate_threads_~tmp___3~0#1); 1966726#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1966055#L441 assume !(1 == ~t5_pc~0); 1966056#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1966902#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1966903#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1966968#L901 assume !(0 != activate_threads_~tmp___4~0#1); 1966969#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1966687#L460 assume !(1 == ~t6_pc~0); 1966688#L460-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1966064#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1966065#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1966680#L909 assume !(0 != activate_threads_~tmp___5~0#1); 1966681#L909-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1966490#L774 assume !(1 == ~M_E~0); 1966491#L774-2 assume !(1 == ~T1_E~0); 1966711#L779-1 assume !(1 == ~T2_E~0); 1966712#L784-1 assume !(1 == ~T3_E~0); 1966876#L789-1 assume !(1 == ~T4_E~0); 1966877#L794-1 assume !(1 == ~T5_E~0); 1966943#L799-1 assume !(1 == ~T6_E~0); 1966944#L804-1 assume !(1 == ~E_M~0); 1966936#L809-1 assume !(1 == ~E_1~0); 1966937#L814-1 assume !(1 == ~E_2~0); 1966022#L819-1 assume !(1 == ~E_3~0); 1966023#L824-1 assume !(1 == ~E_4~0); 1966930#L829-1 assume !(1 == ~E_5~0); 1966931#L834-1 assume !(1 == ~E_6~0); 1966269#L839-1 assume { :end_inline_reset_delta_events } true; 1966270#L1065-2 assume !false; 1983174#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1983175#L671 [2022-12-13 19:42:02,000 INFO L750 eck$LassoCheckResult]: Loop: 1983175#L671 assume !false; 2098550#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 2098549#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 2098548#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 2098547#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 2098546#L582 assume 0 != eval_~tmp~0#1; 2098545#L582-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 2098544#L590 assume !(0 != eval_~tmp_ndt_1~0#1); 2098543#L587 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 1995530#L604 assume !(0 != eval_~tmp_ndt_2~0#1); 2098488#L601 assume !(0 == ~t2_st~0); 2098487#L615 assume !(0 == ~t3_st~0); 2098486#L629 assume !(0 == ~t4_st~0); 2098556#L643 assume !(0 == ~t5_st~0); 2098551#L657 assume !(0 == ~t6_st~0); 1983175#L671 [2022-12-13 19:42:02,000 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:42:02,000 INFO L85 PathProgramCache]: Analyzing trace with hash 1481595819, now seen corresponding path program 1 times [2022-12-13 19:42:02,000 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:42:02,000 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [348342571] [2022-12-13 19:42:02,000 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:42:02,000 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:42:02,005 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:42:02,017 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:42:02,017 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:42:02,017 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [348342571] [2022-12-13 19:42:02,017 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [348342571] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:42:02,017 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:42:02,017 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:42:02,018 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [187991050] [2022-12-13 19:42:02,018 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:42:02,018 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 19:42:02,018 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:42:02,018 INFO L85 PathProgramCache]: Analyzing trace with hash -1666064116, now seen corresponding path program 1 times [2022-12-13 19:42:02,018 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:42:02,019 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [646801840] [2022-12-13 19:42:02,019 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:42:02,019 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:42:02,022 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 19:42:02,022 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 19:42:02,024 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 19:42:02,026 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 19:42:02,102 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 19:42:02,103 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 19:42:02,103 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 19:42:02,103 INFO L87 Difference]: Start difference. First operand 179559 states and 243269 transitions. cyclomatic complexity: 63764 Second operand has 3 states, 3 states have (on average 28.666666666666668) internal successors, (86), 3 states have internal predecessors, (86), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:42:02,529 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 19:42:02,530 INFO L93 Difference]: Finished difference Result 144694 states and 196264 transitions. [2022-12-13 19:42:02,530 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 144694 states and 196264 transitions. [2022-12-13 19:42:02,975 INFO L131 ngComponentsAnalysis]: Automaton has 30 accepting balls. 143889 [2022-12-13 19:42:03,358 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 144694 states to 144694 states and 196264 transitions. [2022-12-13 19:42:03,358 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 144694 [2022-12-13 19:42:03,412 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 144694 [2022-12-13 19:42:03,412 INFO L73 IsDeterministic]: Start isDeterministic. Operand 144694 states and 196264 transitions. [2022-12-13 19:42:03,461 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 19:42:03,462 INFO L218 hiAutomatonCegarLoop]: Abstraction has 144694 states and 196264 transitions. [2022-12-13 19:42:03,520 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 144694 states and 196264 transitions. [2022-12-13 19:42:04,491 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 144694 to 144694. [2022-12-13 19:42:04,580 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 144694 states, 144694 states have (on average 1.3564073147469833) internal successors, (196264), 144693 states have internal predecessors, (196264), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:42:04,837 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 144694 states to 144694 states and 196264 transitions. [2022-12-13 19:42:04,837 INFO L240 hiAutomatonCegarLoop]: Abstraction has 144694 states and 196264 transitions. [2022-12-13 19:42:04,837 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 19:42:04,838 INFO L428 stractBuchiCegarLoop]: Abstraction has 144694 states and 196264 transitions. [2022-12-13 19:42:04,838 INFO L335 stractBuchiCegarLoop]: ======== Iteration 27 ============ [2022-12-13 19:42:04,838 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 144694 states and 196264 transitions. [2022-12-13 19:42:05,199 INFO L131 ngComponentsAnalysis]: Automaton has 30 accepting balls. 143889 [2022-12-13 19:42:05,199 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 19:42:05,199 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 19:42:05,200 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:42:05,200 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:42:05,200 INFO L748 eck$LassoCheckResult]: Stem: 2290618#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 2290619#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 2290808#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2290809#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2291001#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 2290508#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2290509#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2290339#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2290340#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 2290313#L507-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 2290314#L512-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 2290486#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2290651#L696 assume !(0 == ~M_E~0); 2290652#L696-2 assume !(0 == ~T1_E~0); 2291009#L701-1 assume !(0 == ~T2_E~0); 2291012#L706-1 assume !(0 == ~T3_E~0); 2290775#L711-1 assume !(0 == ~T4_E~0); 2290544#L716-1 assume !(0 == ~T5_E~0); 2290545#L721-1 assume !(0 == ~T6_E~0); 2290727#L726-1 assume !(0 == ~E_M~0); 2290728#L731-1 assume !(0 == ~E_1~0); 2290691#L736-1 assume !(0 == ~E_2~0); 2290692#L741-1 assume !(0 == ~E_3~0); 2290786#L746-1 assume !(0 == ~E_4~0); 2290568#L751-1 assume !(0 == ~E_5~0); 2290569#L756-1 assume !(0 == ~E_6~0); 2290541#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2290361#L346 assume !(1 == ~m_pc~0); 2290362#L346-2 is_master_triggered_~__retres1~0#1 := 0; 2290586#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2290578#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2290579#L861 assume !(0 != activate_threads_~tmp~1#1); 2290966#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2290398#L365 assume !(1 == ~t1_pc~0); 2290399#L365-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2290985#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2290344#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2290345#L869 assume !(0 != activate_threads_~tmp___0~0#1); 2290388#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2290852#L384 assume !(1 == ~t2_pc~0); 2290845#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2290846#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2290810#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2290301#L877 assume !(0 != activate_threads_~tmp___1~0#1); 2290302#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2290669#L403 assume !(1 == ~t3_pc~0); 2290670#L403-2 is_transmit3_triggered_~__retres1~3#1 := 0; 2290892#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2290276#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2290277#L885 assume !(0 != activate_threads_~tmp___2~0#1); 2290661#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2290662#L422 assume !(1 == ~t4_pc~0); 2290806#L422-2 is_transmit4_triggered_~__retres1~4#1 := 0; 2290807#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2290451#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2290452#L893 assume !(0 != activate_threads_~tmp___3~0#1); 2290755#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2290315#L441 assume !(1 == ~t5_pc~0); 2290316#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 2290961#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2290589#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2290590#L901 assume !(0 != activate_threads_~tmp___4~0#1); 2290763#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2290764#L460 assume !(1 == ~t6_pc~0); 2290917#L460-2 is_transmit6_triggered_~__retres1~6#1 := 0; 2290322#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2290323#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2290788#L909 assume !(0 != activate_threads_~tmp___5~0#1); 2290914#L909-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2290737#L774 assume !(1 == ~M_E~0); 2290738#L774-2 assume !(1 == ~T1_E~0); 2290935#L779-1 assume !(1 == ~T2_E~0); 2290637#L784-1 assume !(1 == ~T3_E~0); 2290638#L789-1 assume !(1 == ~T4_E~0); 2290380#L794-1 assume !(1 == ~T5_E~0); 2290381#L799-1 assume !(1 == ~T6_E~0); 2291067#L804-1 assume !(1 == ~E_M~0); 2291068#L809-1 assume !(1 == ~E_1~0); 2290723#L814-1 assume !(1 == ~E_2~0); 2290280#L819-1 assume !(1 == ~E_3~0); 2290281#L824-1 assume !(1 == ~E_4~0); 2290797#L829-1 assume !(1 == ~E_5~0); 2290923#L834-1 assume !(1 == ~E_6~0); 2290526#L839-1 assume { :end_inline_reset_delta_events } true; 2290527#L1065-2 assume !false; 2352062#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2352058#L671 [2022-12-13 19:42:05,200 INFO L750 eck$LassoCheckResult]: Loop: 2352058#L671 assume !false; 2352056#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 2352051#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 2352048#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 2352049#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 2352041#L582 assume 0 != eval_~tmp~0#1; 2352042#L582-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 2354393#L590 assume !(0 != eval_~tmp_ndt_1~0#1); 2354014#L587 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 2341447#L604 assume !(0 != eval_~tmp_ndt_2~0#1); 2341448#L601 assume !(0 == ~t2_st~0); 2344622#L615 assume !(0 == ~t3_st~0); 2344615#L629 assume !(0 == ~t4_st~0); 2352075#L643 assume !(0 == ~t5_st~0); 2352060#L657 assume !(0 == ~t6_st~0); 2352058#L671 [2022-12-13 19:42:05,201 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:42:05,201 INFO L85 PathProgramCache]: Analyzing trace with hash -1771052117, now seen corresponding path program 2 times [2022-12-13 19:42:05,201 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:42:05,201 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1722334663] [2022-12-13 19:42:05,201 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:42:05,201 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:42:05,207 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 19:42:05,207 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 19:42:05,211 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 19:42:05,219 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 19:42:05,220 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:42:05,220 INFO L85 PathProgramCache]: Analyzing trace with hash -1666064116, now seen corresponding path program 2 times [2022-12-13 19:42:05,220 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:42:05,220 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [832608451] [2022-12-13 19:42:05,220 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:42:05,220 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:42:05,222 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 19:42:05,222 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 19:42:05,223 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 19:42:05,225 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 19:42:05,225 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:42:05,225 INFO L85 PathProgramCache]: Analyzing trace with hash -1661144030, now seen corresponding path program 1 times [2022-12-13 19:42:05,225 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:42:05,225 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [387130086] [2022-12-13 19:42:05,225 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:42:05,225 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:42:05,231 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:42:05,389 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:42:05,389 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:42:05,390 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [387130086] [2022-12-13 19:42:05,390 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [387130086] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:42:05,390 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:42:05,390 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:42:05,390 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [141010379] [2022-12-13 19:42:05,390 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:42:05,483 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 19:42:05,483 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 19:42:05,484 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 19:42:05,484 INFO L87 Difference]: Start difference. First operand 144694 states and 196264 transitions. cyclomatic complexity: 51600 Second operand has 3 states, 3 states have (on average 33.666666666666664) internal successors, (101), 3 states have internal predecessors, (101), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:42:06,221 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 19:42:06,221 INFO L93 Difference]: Finished difference Result 272845 states and 368128 transitions. [2022-12-13 19:42:06,221 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 272845 states and 368128 transitions. [2022-12-13 19:42:07,043 INFO L131 ngComponentsAnalysis]: Automaton has 30 accepting balls. 271326 [2022-12-13 19:42:07,641 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 272845 states to 272845 states and 368128 transitions. [2022-12-13 19:42:07,641 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 272845 [2022-12-13 19:42:07,727 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 272845 [2022-12-13 19:42:07,727 INFO L73 IsDeterministic]: Start isDeterministic. Operand 272845 states and 368128 transitions. [2022-12-13 19:42:07,814 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 19:42:07,814 INFO L218 hiAutomatonCegarLoop]: Abstraction has 272845 states and 368128 transitions. [2022-12-13 19:42:07,904 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 272845 states and 368128 transitions. [2022-12-13 19:42:09,827 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 272845 to 263515. [2022-12-13 19:42:09,972 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 263515 states, 263515 states have (on average 1.3534409805893404) internal successors, (356652), 263514 states have internal predecessors, (356652), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:42:10,358 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 263515 states to 263515 states and 356652 transitions. [2022-12-13 19:42:10,358 INFO L240 hiAutomatonCegarLoop]: Abstraction has 263515 states and 356652 transitions. [2022-12-13 19:42:10,359 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 19:42:10,359 INFO L428 stractBuchiCegarLoop]: Abstraction has 263515 states and 356652 transitions. [2022-12-13 19:42:10,359 INFO L335 stractBuchiCegarLoop]: ======== Iteration 28 ============ [2022-12-13 19:42:10,359 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 263515 states and 356652 transitions. [2022-12-13 19:42:11,159 INFO L131 ngComponentsAnalysis]: Automaton has 30 accepting balls. 261996 [2022-12-13 19:42:11,159 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 19:42:11,160 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 19:42:11,160 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:42:11,160 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:42:11,160 INFO L748 eck$LassoCheckResult]: Stem: 2708171#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 2708172#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 2708369#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2708370#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2708574#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 2708056#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2708057#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2707887#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2707888#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 2707859#L507-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 2707860#L512-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 2708034#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2708209#L696 assume !(0 == ~M_E~0); 2708210#L696-2 assume !(0 == ~T1_E~0); 2708582#L701-1 assume !(0 == ~T2_E~0); 2708585#L706-1 assume !(0 == ~T3_E~0); 2708335#L711-1 assume !(0 == ~T4_E~0); 2708094#L716-1 assume !(0 == ~T5_E~0); 2708095#L721-1 assume !(0 == ~T6_E~0); 2708283#L726-1 assume !(0 == ~E_M~0); 2708284#L731-1 assume !(0 == ~E_1~0); 2708248#L736-1 assume !(0 == ~E_2~0); 2708249#L741-1 assume !(0 == ~E_3~0); 2708345#L746-1 assume !(0 == ~E_4~0); 2708122#L751-1 assume !(0 == ~E_5~0); 2708123#L756-1 assume !(0 == ~E_6~0); 2708091#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2707909#L346 assume !(1 == ~m_pc~0); 2707910#L346-2 is_master_triggered_~__retres1~0#1 := 0; 2708137#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2708129#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2708130#L861 assume !(0 != activate_threads_~tmp~1#1); 2708537#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2707944#L365 assume !(1 == ~t1_pc~0); 2707945#L365-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2708556#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2707895#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2707896#L869 assume !(0 != activate_threads_~tmp___0~0#1); 2707933#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2708415#L384 assume !(1 == ~t2_pc~0); 2708411#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2708412#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2708374#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2707850#L877 assume !(0 != activate_threads_~tmp___1~0#1); 2707851#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2708225#L403 assume !(1 == ~t3_pc~0); 2708226#L403-2 is_transmit3_triggered_~__retres1~3#1 := 0; 2708456#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2707822#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2707823#L885 assume !(0 != activate_threads_~tmp___2~0#1); 2708219#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2708220#L422 assume !(1 == ~t4_pc~0); 2708367#L422-2 is_transmit4_triggered_~__retres1~4#1 := 0; 2708368#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2707998#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2707999#L893 assume !(0 != activate_threads_~tmp___3~0#1); 2708311#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2707861#L441 assume !(1 == ~t5_pc~0); 2707862#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 2708532#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2708141#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2708142#L901 assume !(0 != activate_threads_~tmp___4~0#1); 2708323#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2708324#L460 assume !(1 == ~t6_pc~0); 2708485#L460-2 is_transmit6_triggered_~__retres1~6#1 := 0; 2707870#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2707871#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2708347#L909 assume !(0 != activate_threads_~tmp___5~0#1); 2708479#L909-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2708294#L774 assume !(1 == ~M_E~0); 2708295#L774-2 assume !(1 == ~T1_E~0); 2708498#L779-1 assume !(1 == ~T2_E~0); 2708189#L784-1 assume !(1 == ~T3_E~0); 2708190#L789-1 assume !(1 == ~T4_E~0); 2707927#L794-1 assume !(1 == ~T5_E~0); 2707928#L799-1 assume !(1 == ~T6_E~0); 2708645#L804-1 assume !(1 == ~E_M~0); 2708646#L809-1 assume !(1 == ~E_1~0); 2708280#L814-1 assume !(1 == ~E_2~0); 2707828#L819-1 assume !(1 == ~E_3~0); 2707829#L824-1 assume !(1 == ~E_4~0); 2708358#L829-1 assume !(1 == ~E_5~0); 2708488#L834-1 assume !(1 == ~E_6~0); 2708076#L839-1 assume { :end_inline_reset_delta_events } true; 2708077#L1065-2 assume !false; 2712952#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2712953#L671 [2022-12-13 19:42:11,160 INFO L750 eck$LassoCheckResult]: Loop: 2712953#L671 assume !false; 2866954#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 2866952#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 2866951#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 2866950#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 2866949#L582 assume 0 != eval_~tmp~0#1; 2866947#L582-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 2866946#L590 assume !(0 != eval_~tmp_ndt_1~0#1); 2866945#L587 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 2866944#L604 assume !(0 != eval_~tmp_ndt_2~0#1); 2866943#L601 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 2735164#L618 assume !(0 != eval_~tmp_ndt_3~0#1); 2866941#L615 assume !(0 == ~t3_st~0); 2866939#L629 assume !(0 == ~t4_st~0); 2866938#L643 assume !(0 == ~t5_st~0); 2866955#L657 assume !(0 == ~t6_st~0); 2712953#L671 [2022-12-13 19:42:11,161 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:42:11,161 INFO L85 PathProgramCache]: Analyzing trace with hash -1771052117, now seen corresponding path program 3 times [2022-12-13 19:42:11,161 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:42:11,161 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [545243942] [2022-12-13 19:42:11,161 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:42:11,161 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:42:11,169 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 19:42:11,169 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 19:42:11,175 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 19:42:11,189 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 19:42:11,189 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:42:11,189 INFO L85 PathProgramCache]: Analyzing trace with hash -1736689607, now seen corresponding path program 1 times [2022-12-13 19:42:11,190 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:42:11,190 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [562325463] [2022-12-13 19:42:11,190 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:42:11,190 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:42:11,193 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 19:42:11,193 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 19:42:11,194 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 19:42:11,196 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 19:42:11,196 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:42:11,196 INFO L85 PathProgramCache]: Analyzing trace with hash -1584166941, now seen corresponding path program 1 times [2022-12-13 19:42:11,196 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:42:11,197 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [894887471] [2022-12-13 19:42:11,197 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:42:11,197 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:42:11,204 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:42:11,224 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:42:11,224 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:42:11,224 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [894887471] [2022-12-13 19:42:11,224 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [894887471] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:42:11,225 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:42:11,225 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:42:11,225 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1916211476] [2022-12-13 19:42:11,225 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:42:11,316 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 19:42:11,316 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 19:42:11,316 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 19:42:11,316 INFO L87 Difference]: Start difference. First operand 263515 states and 356652 transitions. cyclomatic complexity: 93167 Second operand has 3 states, 3 states have (on average 34.0) internal successors, (102), 3 states have internal predecessors, (102), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:42:12,616 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 19:42:12,616 INFO L93 Difference]: Finished difference Result 444541 states and 600176 transitions. [2022-12-13 19:42:12,616 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 444541 states and 600176 transitions. [2022-12-13 19:42:14,409 INFO L131 ngComponentsAnalysis]: Automaton has 30 accepting balls. 441870 [2022-12-13 19:42:15,257 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 444541 states to 444541 states and 600176 transitions. [2022-12-13 19:42:15,257 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 444541 [2022-12-13 19:42:15,391 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 444541 [2022-12-13 19:42:15,391 INFO L73 IsDeterministic]: Start isDeterministic. Operand 444541 states and 600176 transitions. [2022-12-13 19:42:15,511 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 19:42:15,511 INFO L218 hiAutomatonCegarLoop]: Abstraction has 444541 states and 600176 transitions. [2022-12-13 19:42:15,654 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 444541 states and 600176 transitions. [2022-12-13 19:42:18,754 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 444541 to 433797. [2022-12-13 19:42:18,900 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 433797 states, 433797 states have (on average 1.3525773576119706) internal successors, (586744), 433796 states have internal predecessors, (586744), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:42:19,620 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 433797 states to 433797 states and 586744 transitions. [2022-12-13 19:42:19,620 INFO L240 hiAutomatonCegarLoop]: Abstraction has 433797 states and 586744 transitions. [2022-12-13 19:42:19,620 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 19:42:19,621 INFO L428 stractBuchiCegarLoop]: Abstraction has 433797 states and 586744 transitions. [2022-12-13 19:42:19,621 INFO L335 stractBuchiCegarLoop]: ======== Iteration 29 ============ [2022-12-13 19:42:19,621 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 433797 states and 586744 transitions. [2022-12-13 19:42:20,770 INFO L131 ngComponentsAnalysis]: Automaton has 30 accepting balls. 431126 [2022-12-13 19:42:20,770 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 19:42:20,770 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 19:42:20,771 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:42:20,771 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:42:20,771 INFO L748 eck$LassoCheckResult]: Stem: 3416232#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 3416233#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 3416432#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3416433#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3416646#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 3416123#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3416124#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3415954#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3415955#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 3415924#L507-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 3415925#L512-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 3416101#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3416270#L696 assume !(0 == ~M_E~0); 3416271#L696-2 assume !(0 == ~T1_E~0); 3416652#L701-1 assume !(0 == ~T2_E~0); 3416654#L706-1 assume !(0 == ~T3_E~0); 3416397#L711-1 assume !(0 == ~T4_E~0); 3416158#L716-1 assume !(0 == ~T5_E~0); 3416159#L721-1 assume !(0 == ~T6_E~0); 3416348#L726-1 assume !(0 == ~E_M~0); 3416349#L731-1 assume !(0 == ~E_1~0); 3416307#L736-1 assume !(0 == ~E_2~0); 3416308#L741-1 assume !(0 == ~E_3~0); 3416410#L746-1 assume !(0 == ~E_4~0); 3416184#L751-1 assume !(0 == ~E_5~0); 3416185#L756-1 assume !(0 == ~E_6~0); 3416155#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3415974#L346 assume !(1 == ~m_pc~0); 3415975#L346-2 is_master_triggered_~__retres1~0#1 := 0; 3416201#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3416191#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 3416192#L861 assume !(0 != activate_threads_~tmp~1#1); 3416608#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3416010#L365 assume !(1 == ~t1_pc~0); 3416011#L365-2 is_transmit1_triggered_~__retres1~1#1 := 0; 3416628#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3415960#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3415961#L869 assume !(0 != activate_threads_~tmp___0~0#1); 3415999#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3416485#L384 assume !(1 == ~t2_pc~0); 3416479#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 3416480#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3416439#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3415914#L877 assume !(0 != activate_threads_~tmp___1~0#1); 3415915#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3416284#L403 assume !(1 == ~t3_pc~0); 3416285#L403-2 is_transmit3_triggered_~__retres1~3#1 := 0; 3416523#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3415887#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3415888#L885 assume !(0 != activate_threads_~tmp___2~0#1); 3416279#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3416280#L422 assume !(1 == ~t4_pc~0); 3416430#L422-2 is_transmit4_triggered_~__retres1~4#1 := 0; 3416431#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3416063#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3416064#L893 assume !(0 != activate_threads_~tmp___3~0#1); 3416374#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3415926#L441 assume !(1 == ~t5_pc~0); 3415927#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 3416603#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3416203#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3416204#L901 assume !(0 != activate_threads_~tmp___4~0#1); 3416386#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3416387#L460 assume !(1 == ~t6_pc~0); 3416555#L460-2 is_transmit6_triggered_~__retres1~6#1 := 0; 3415935#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3415936#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3416412#L909 assume !(0 != activate_threads_~tmp___5~0#1); 3416550#L909-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3416359#L774 assume !(1 == ~M_E~0); 3416360#L774-2 assume !(1 == ~T1_E~0); 3416572#L779-1 assume !(1 == ~T2_E~0); 3416250#L784-1 assume !(1 == ~T3_E~0); 3416251#L789-1 assume !(1 == ~T4_E~0); 3415991#L794-1 assume !(1 == ~T5_E~0); 3415992#L799-1 assume !(1 == ~T6_E~0); 3416705#L804-1 assume !(1 == ~E_M~0); 3416706#L809-1 assume !(1 == ~E_1~0); 3416345#L814-1 assume !(1 == ~E_2~0); 3415893#L819-1 assume !(1 == ~E_3~0); 3415894#L824-1 assume !(1 == ~E_4~0); 3416420#L829-1 assume !(1 == ~E_5~0); 3416559#L834-1 assume !(1 == ~E_6~0); 3416143#L839-1 assume { :end_inline_reset_delta_events } true; 3416144#L1065-2 assume !false; 3671328#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3671323#L671 [2022-12-13 19:42:20,771 INFO L750 eck$LassoCheckResult]: Loop: 3671323#L671 assume !false; 3671319#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 3671315#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 3671313#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 3671312#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 3671307#L582 assume 0 != eval_~tmp~0#1; 3671303#L582-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 3671304#L590 assume !(0 != eval_~tmp_ndt_1~0#1); 3712867#L587 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 3712863#L604 assume !(0 != eval_~tmp_ndt_2~0#1); 3712862#L601 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 3712858#L618 assume !(0 != eval_~tmp_ndt_3~0#1); 3712856#L615 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; 3712854#L632 assume !(0 != eval_~tmp_ndt_4~0#1); 3712851#L629 assume !(0 == ~t4_st~0); 3712845#L643 assume !(0 == ~t5_st~0); 3671326#L657 assume !(0 == ~t6_st~0); 3671323#L671 [2022-12-13 19:42:20,771 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:42:20,771 INFO L85 PathProgramCache]: Analyzing trace with hash -1771052117, now seen corresponding path program 4 times [2022-12-13 19:42:20,771 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:42:20,771 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1844895095] [2022-12-13 19:42:20,771 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:42:20,772 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:42:20,777 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 19:42:20,777 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 19:42:20,780 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 19:42:20,788 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 19:42:20,789 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:42:20,789 INFO L85 PathProgramCache]: Analyzing trace with hash 1806125646, now seen corresponding path program 1 times [2022-12-13 19:42:20,789 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:42:20,789 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1313627737] [2022-12-13 19:42:20,789 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:42:20,789 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:42:20,791 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 19:42:20,791 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 19:42:20,792 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 19:42:20,793 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 19:42:20,793 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:42:20,793 INFO L85 PathProgramCache]: Analyzing trace with hash -2055606300, now seen corresponding path program 1 times [2022-12-13 19:42:20,793 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:42:20,793 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [832871984] [2022-12-13 19:42:20,793 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:42:20,793 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:42:20,798 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:42:20,812 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:42:20,812 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:42:20,812 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [832871984] [2022-12-13 19:42:20,812 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [832871984] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:42:20,812 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:42:20,812 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:42:20,813 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1663245103] [2022-12-13 19:42:20,813 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:42:20,905 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 19:42:20,905 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 19:42:20,905 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 19:42:20,905 INFO L87 Difference]: Start difference. First operand 433797 states and 586744 transitions. cyclomatic complexity: 152977 Second operand has 3 states, 3 states have (on average 34.333333333333336) internal successors, (103), 3 states have internal predecessors, (103), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:42:22,443 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 19:42:22,443 INFO L93 Difference]: Finished difference Result 526307 states and 707582 transitions. [2022-12-13 19:42:22,443 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 526307 states and 707582 transitions. [2022-12-13 19:42:24,534 INFO L131 ngComponentsAnalysis]: Automaton has 30 accepting balls. 523846 [2022-12-13 19:42:25,493 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 526307 states to 526307 states and 707582 transitions. [2022-12-13 19:42:25,493 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 526307 [2022-12-13 19:42:25,665 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 526307 [2022-12-13 19:42:25,665 INFO L73 IsDeterministic]: Start isDeterministic. Operand 526307 states and 707582 transitions. [2022-12-13 19:42:25,818 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 19:42:25,818 INFO L218 hiAutomatonCegarLoop]: Abstraction has 526307 states and 707582 transitions. [2022-12-13 19:42:25,994 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 526307 states and 707582 transitions. [2022-12-13 19:42:29,587 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 526307 to 508799. [2022-12-13 19:42:29,788 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 508799 states, 508799 states have (on average 1.348308467587397) internal successors, (686018), 508798 states have internal predecessors, (686018), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:42:30,797 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 508799 states to 508799 states and 686018 transitions. [2022-12-13 19:42:30,797 INFO L240 hiAutomatonCegarLoop]: Abstraction has 508799 states and 686018 transitions. [2022-12-13 19:42:30,797 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 19:42:30,798 INFO L428 stractBuchiCegarLoop]: Abstraction has 508799 states and 686018 transitions. [2022-12-13 19:42:30,798 INFO L335 stractBuchiCegarLoop]: ======== Iteration 30 ============ [2022-12-13 19:42:30,798 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 508799 states and 686018 transitions. [2022-12-13 19:42:32,049 INFO L131 ngComponentsAnalysis]: Automaton has 30 accepting balls. 506338 [2022-12-13 19:42:32,049 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 19:42:32,049 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 19:42:32,050 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:42:32,050 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:42:32,050 INFO L748 eck$LassoCheckResult]: Stem: 4376347#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 4376348#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 4376535#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4376536#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4376754#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 4376231#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4376232#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4376064#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 4376065#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 4376035#L507-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 4376036#L512-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 4376209#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4376380#L696 assume !(0 == ~M_E~0); 4376381#L696-2 assume !(0 == ~T1_E~0); 4376763#L701-1 assume !(0 == ~T2_E~0); 4376765#L706-1 assume !(0 == ~T3_E~0); 4376504#L711-1 assume !(0 == ~T4_E~0); 4376270#L716-1 assume !(0 == ~T5_E~0); 4376271#L721-1 assume !(0 == ~T6_E~0); 4376455#L726-1 assume !(0 == ~E_M~0); 4376456#L731-1 assume !(0 == ~E_1~0); 4376416#L736-1 assume !(0 == ~E_2~0); 4376417#L741-1 assume !(0 == ~E_3~0); 4376515#L746-1 assume !(0 == ~E_4~0); 4376296#L751-1 assume !(0 == ~E_5~0); 4376297#L756-1 assume !(0 == ~E_6~0); 4376267#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4376083#L346 assume !(1 == ~m_pc~0); 4376084#L346-2 is_master_triggered_~__retres1~0#1 := 0; 4376313#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4376303#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4376304#L861 assume !(0 != activate_threads_~tmp~1#1); 4376711#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4376119#L365 assume !(1 == ~t1_pc~0); 4376120#L365-2 is_transmit1_triggered_~__retres1~1#1 := 0; 4376732#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4376070#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4376071#L869 assume !(0 != activate_threads_~tmp___0~0#1); 4376107#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4376586#L384 assume !(1 == ~t2_pc~0); 4376581#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 4376582#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4376543#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4376025#L877 assume !(0 != activate_threads_~tmp___1~0#1); 4376026#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4376395#L403 assume !(1 == ~t3_pc~0); 4376396#L403-2 is_transmit3_triggered_~__retres1~3#1 := 0; 4376629#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4375998#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4375999#L885 assume !(0 != activate_threads_~tmp___2~0#1); 4376390#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4376391#L422 assume !(1 == ~t4_pc~0); 4376533#L422-2 is_transmit4_triggered_~__retres1~4#1 := 0; 4376534#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4376171#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4376172#L893 assume !(0 != activate_threads_~tmp___3~0#1); 4376483#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4376037#L441 assume !(1 == ~t5_pc~0); 4376038#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 4376706#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4376315#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4376316#L901 assume !(0 != activate_threads_~tmp___4~0#1); 4376493#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4376494#L460 assume !(1 == ~t6_pc~0); 4376660#L460-2 is_transmit6_triggered_~__retres1~6#1 := 0; 4376046#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4376047#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4376518#L909 assume !(0 != activate_threads_~tmp___5~0#1); 4376653#L909-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4376467#L774 assume !(1 == ~M_E~0); 4376468#L774-2 assume !(1 == ~T1_E~0); 4376674#L779-1 assume !(1 == ~T2_E~0); 4376363#L784-1 assume !(1 == ~T3_E~0); 4376364#L789-1 assume !(1 == ~T4_E~0); 4376101#L794-1 assume !(1 == ~T5_E~0); 4376102#L799-1 assume !(1 == ~T6_E~0); 4376824#L804-1 assume !(1 == ~E_M~0); 4376825#L809-1 assume !(1 == ~E_1~0); 4376452#L814-1 assume !(1 == ~E_2~0); 4376004#L819-1 assume !(1 == ~E_3~0); 4376005#L824-1 assume !(1 == ~E_4~0); 4376527#L829-1 assume !(1 == ~E_5~0); 4376662#L834-1 assume !(1 == ~E_6~0); 4376252#L839-1 assume { :end_inline_reset_delta_events } true; 4376253#L1065-2 assume !false; 4465741#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4465742#L671 [2022-12-13 19:42:32,050 INFO L750 eck$LassoCheckResult]: Loop: 4465742#L671 assume !false; 4804705#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 4804703#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 4804702#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 4804701#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 4804700#L582 assume 0 != eval_~tmp~0#1; 4465714#L582-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 4465715#L590 assume !(0 != eval_~tmp_ndt_1~0#1); 4465705#L587 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 4465706#L604 assume !(0 != eval_~tmp_ndt_2~0#1); 4804447#L601 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 4804796#L618 assume !(0 != eval_~tmp_ndt_3~0#1); 4804804#L615 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; 4804901#L632 assume !(0 != eval_~tmp_ndt_4~0#1); 4804900#L629 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0#1;eval_~tmp_ndt_5~0#1 := eval_#t~nondet11#1;havoc eval_#t~nondet11#1; 4804898#L646 assume !(0 != eval_~tmp_ndt_5~0#1); 4804711#L643 assume !(0 == ~t5_st~0); 4804706#L657 assume !(0 == ~t6_st~0); 4465742#L671 [2022-12-13 19:42:32,050 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:42:32,050 INFO L85 PathProgramCache]: Analyzing trace with hash -1771052117, now seen corresponding path program 5 times [2022-12-13 19:42:32,050 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:42:32,050 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [935976761] [2022-12-13 19:42:32,051 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:42:32,051 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:42:32,056 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 19:42:32,056 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 19:42:32,059 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 19:42:32,068 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 19:42:32,068 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:42:32,068 INFO L85 PathProgramCache]: Analyzing trace with hash 149158647, now seen corresponding path program 1 times [2022-12-13 19:42:32,068 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:42:32,068 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1691002745] [2022-12-13 19:42:32,068 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:42:32,069 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:42:32,070 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 19:42:32,071 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 19:42:32,072 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 19:42:32,073 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 19:42:32,073 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:42:32,073 INFO L85 PathProgramCache]: Analyzing trace with hash 694552609, now seen corresponding path program 1 times [2022-12-13 19:42:32,073 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:42:32,073 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [681243441] [2022-12-13 19:42:32,073 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:42:32,074 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:42:32,078 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:42:32,092 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:42:32,092 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:42:32,092 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [681243441] [2022-12-13 19:42:32,092 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [681243441] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:42:32,092 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:42:32,092 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:42:32,093 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1113859587] [2022-12-13 19:42:32,093 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:42:32,203 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 19:42:32,203 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 19:42:32,203 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 19:42:32,203 INFO L87 Difference]: Start difference. First operand 508799 states and 686018 transitions. cyclomatic complexity: 177249 Second operand has 3 states, 3 states have (on average 34.666666666666664) internal successors, (104), 3 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:42:34,824 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 19:42:34,824 INFO L93 Difference]: Finished difference Result 885135 states and 1194044 transitions. [2022-12-13 19:42:34,824 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 885135 states and 1194044 transitions. [2022-12-13 19:42:38,038 INFO L131 ngComponentsAnalysis]: Automaton has 30 accepting balls. 880304 [2022-12-13 19:42:39,865 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 885135 states to 885135 states and 1194044 transitions. [2022-12-13 19:42:39,865 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 885135 [2022-12-13 19:42:40,177 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 885135 [2022-12-13 19:42:40,177 INFO L73 IsDeterministic]: Start isDeterministic. Operand 885135 states and 1194044 transitions. [2022-12-13 19:42:40,493 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 19:42:40,493 INFO L218 hiAutomatonCegarLoop]: Abstraction has 885135 states and 1194044 transitions. [2022-12-13 19:42:40,795 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 885135 states and 1194044 transitions. [2022-12-13 19:42:46,855 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 885135 to 861739. [2022-12-13 19:42:47,200 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 861739 states, 861739 states have (on average 1.3540016176591751) internal successors, (1166796), 861738 states have internal predecessors, (1166796), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:42:49,007 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 861739 states to 861739 states and 1166796 transitions. [2022-12-13 19:42:49,007 INFO L240 hiAutomatonCegarLoop]: Abstraction has 861739 states and 1166796 transitions. [2022-12-13 19:42:49,008 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 19:42:49,009 INFO L428 stractBuchiCegarLoop]: Abstraction has 861739 states and 1166796 transitions. [2022-12-13 19:42:49,009 INFO L335 stractBuchiCegarLoop]: ======== Iteration 31 ============ [2022-12-13 19:42:49,009 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 861739 states and 1166796 transitions. [2022-12-13 19:42:51,818 INFO L131 ngComponentsAnalysis]: Automaton has 30 accepting balls. 856908 [2022-12-13 19:42:51,818 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 19:42:51,818 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 19:42:51,819 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:42:51,819 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:42:51,819 INFO L748 eck$LassoCheckResult]: Stem: 5770288#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 5770289#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 5770493#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5770494#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5770727#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 5770173#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5770174#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5770004#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 5770005#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 5769978#L507-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 5769979#L512-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 5770151#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5770323#L696 assume !(0 == ~M_E~0); 5770324#L696-2 assume !(0 == ~T1_E~0); 5770736#L701-1 assume !(0 == ~T2_E~0); 5770741#L706-1 assume !(0 == ~T3_E~0); 5770456#L711-1 assume !(0 == ~T4_E~0); 5770213#L716-1 assume !(0 == ~T5_E~0); 5770214#L721-1 assume !(0 == ~T6_E~0); 5770402#L726-1 assume !(0 == ~E_M~0); 5770403#L731-1 assume !(0 == ~E_1~0); 5770363#L736-1 assume !(0 == ~E_2~0); 5770364#L741-1 assume !(0 == ~E_3~0); 5770468#L746-1 assume !(0 == ~E_4~0); 5770240#L751-1 assume !(0 == ~E_5~0); 5770241#L756-1 assume !(0 == ~E_6~0); 5770210#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5770024#L346 assume !(1 == ~m_pc~0); 5770025#L346-2 is_master_triggered_~__retres1~0#1 := 0; 5770256#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5770248#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 5770249#L861 assume !(0 != activate_threads_~tmp~1#1); 5770679#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5770060#L365 assume !(1 == ~t1_pc~0); 5770061#L365-2 is_transmit1_triggered_~__retres1~1#1 := 0; 5770700#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5770009#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 5770010#L869 assume !(0 != activate_threads_~tmp___0~0#1); 5770050#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5770547#L384 assume !(1 == ~t2_pc~0); 5770541#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 5770542#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5770496#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5769966#L877 assume !(0 != activate_threads_~tmp___1~0#1); 5769967#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5770340#L403 assume !(1 == ~t3_pc~0); 5770341#L403-2 is_transmit3_triggered_~__retres1~3#1 := 0; 5770589#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5769941#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 5769942#L885 assume !(0 != activate_threads_~tmp___2~0#1); 5770332#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5770333#L422 assume !(1 == ~t4_pc~0); 5770491#L422-2 is_transmit4_triggered_~__retres1~4#1 := 0; 5770492#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5770113#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 5770114#L893 assume !(0 != activate_threads_~tmp___3~0#1); 5770431#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5769980#L441 assume !(1 == ~t5_pc~0); 5769981#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 5770672#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5770259#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 5770260#L901 assume !(0 != activate_threads_~tmp___4~0#1); 5770442#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 5770443#L460 assume !(1 == ~t6_pc~0); 5770619#L460-2 is_transmit6_triggered_~__retres1~6#1 := 0; 5769987#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5769988#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 5770471#L909 assume !(0 != activate_threads_~tmp___5~0#1); 5770615#L909-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5770415#L774 assume !(1 == ~M_E~0); 5770416#L774-2 assume !(1 == ~T1_E~0); 5770637#L779-1 assume !(1 == ~T2_E~0); 5770309#L784-1 assume !(1 == ~T3_E~0); 5770310#L789-1 assume !(1 == ~T4_E~0); 5770043#L794-1 assume !(1 == ~T5_E~0); 5770044#L799-1 assume !(1 == ~T6_E~0); 5770803#L804-1 assume !(1 == ~E_M~0); 5770804#L809-1 assume !(1 == ~E_1~0); 5770397#L814-1 assume !(1 == ~E_2~0); 5769945#L819-1 assume !(1 == ~E_3~0); 5769946#L824-1 assume !(1 == ~E_4~0); 5770480#L829-1 assume !(1 == ~E_5~0); 5770625#L834-1 assume !(1 == ~E_6~0); 5770192#L839-1 assume { :end_inline_reset_delta_events } true; 5770193#L1065-2 assume !false; 5918327#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5918328#L671 [2022-12-13 19:42:51,819 INFO L750 eck$LassoCheckResult]: Loop: 5918328#L671 assume !false; 6193436#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 6193435#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 6193434#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 6193433#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 6193432#L582 assume 0 != eval_~tmp~0#1; 6193431#L582-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 6193430#L590 assume !(0 != eval_~tmp_ndt_1~0#1); 6193429#L587 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 6193428#L604 assume !(0 != eval_~tmp_ndt_2~0#1); 6193427#L601 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 6193418#L618 assume !(0 != eval_~tmp_ndt_3~0#1); 6193426#L615 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; 6193446#L632 assume !(0 != eval_~tmp_ndt_4~0#1); 6193445#L629 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0#1;eval_~tmp_ndt_5~0#1 := eval_#t~nondet11#1;havoc eval_#t~nondet11#1; 6193443#L646 assume !(0 != eval_~tmp_ndt_5~0#1); 6193442#L643 assume 0 == ~t5_st~0;havoc eval_~tmp_ndt_6~0#1;eval_~tmp_ndt_6~0#1 := eval_#t~nondet12#1;havoc eval_#t~nondet12#1; 6193440#L660 assume !(0 != eval_~tmp_ndt_6~0#1); 6193437#L657 assume !(0 == ~t6_st~0); 5918328#L671 [2022-12-13 19:42:51,819 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:42:51,819 INFO L85 PathProgramCache]: Analyzing trace with hash -1771052117, now seen corresponding path program 6 times [2022-12-13 19:42:51,819 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:42:51,819 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1552037600] [2022-12-13 19:42:51,820 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:42:51,820 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:42:51,826 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 19:42:51,826 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 19:42:51,830 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 19:42:51,842 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 19:42:51,842 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:42:51,843 INFO L85 PathProgramCache]: Analyzing trace with hash 328754064, now seen corresponding path program 1 times [2022-12-13 19:42:51,843 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:42:51,843 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2112824651] [2022-12-13 19:42:51,843 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:42:51,843 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:42:51,846 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 19:42:51,846 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 19:42:51,847 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 19:42:51,849 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 19:42:51,849 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:42:51,849 INFO L85 PathProgramCache]: Analyzing trace with hash 56097702, now seen corresponding path program 1 times [2022-12-13 19:42:51,849 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:42:51,849 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [365762217] [2022-12-13 19:42:51,850 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:42:51,850 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:42:51,857 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:42:51,875 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:42:51,875 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:42:51,876 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [365762217] [2022-12-13 19:42:51,876 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [365762217] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:42:51,876 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:42:51,876 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-12-13 19:42:51,876 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [852950738] [2022-12-13 19:42:51,876 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:42:52,032 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 19:42:52,033 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 19:42:52,033 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 19:42:52,033 INFO L87 Difference]: Start difference. First operand 861739 states and 1166796 transitions. cyclomatic complexity: 305087 Second operand has 3 states, 2 states have (on average 52.5) internal successors, (105), 3 states have internal predecessors, (105), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:42:55,355 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 19:42:55,355 INFO L93 Difference]: Finished difference Result 1355795 states and 1835604 transitions. [2022-12-13 19:42:55,355 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1355795 states and 1835604 transitions.