./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/token_ring.07.cil-1.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 2329fc70 Calling Ultimate with: /usr/lib/jvm/java-11-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_67969b45-2fb3-4f9e-b865-5e7c88aeec8b/bin/uautomizer-uyxdKDjOR8/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_67969b45-2fb3-4f9e-b865-5e7c88aeec8b/bin/uautomizer-uyxdKDjOR8/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_67969b45-2fb3-4f9e-b865-5e7c88aeec8b/bin/uautomizer-uyxdKDjOR8/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_67969b45-2fb3-4f9e-b865-5e7c88aeec8b/bin/uautomizer-uyxdKDjOR8/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/token_ring.07.cil-1.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_67969b45-2fb3-4f9e-b865-5e7c88aeec8b/bin/uautomizer-uyxdKDjOR8/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_67969b45-2fb3-4f9e-b865-5e7c88aeec8b/bin/uautomizer-uyxdKDjOR8 --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash a6baa92d18991a792383fc99c5c300f37f700ba00714b15a3dbe7d2191a67ca9 --- Real Ultimate output --- [0.001s][warning][os,container] Duplicate cpuset controllers detected. Picking /sys/fs/cgroup/cpuset, skipping /sys/fs/cgroup/cpuset. This is Ultimate 0.2.2-dev-2329fc7 [2022-12-13 12:19:10,804 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-12-13 12:19:10,806 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-12-13 12:19:10,825 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-12-13 12:19:10,825 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-12-13 12:19:10,826 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-12-13 12:19:10,827 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-12-13 12:19:10,829 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-12-13 12:19:10,830 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-12-13 12:19:10,831 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-12-13 12:19:10,832 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-12-13 12:19:10,833 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-12-13 12:19:10,833 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-12-13 12:19:10,834 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-12-13 12:19:10,835 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-12-13 12:19:10,836 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-12-13 12:19:10,837 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-12-13 12:19:10,838 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-12-13 12:19:10,840 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-12-13 12:19:10,841 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-12-13 12:19:10,843 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-12-13 12:19:10,844 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-12-13 12:19:10,845 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-12-13 12:19:10,846 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-12-13 12:19:10,850 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-12-13 12:19:10,850 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-12-13 12:19:10,850 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-12-13 12:19:10,851 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-12-13 12:19:10,852 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-12-13 12:19:10,853 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-12-13 12:19:10,853 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-12-13 12:19:10,854 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-12-13 12:19:10,855 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-12-13 12:19:10,855 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-12-13 12:19:10,856 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-12-13 12:19:10,857 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-12-13 12:19:10,857 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-12-13 12:19:10,857 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-12-13 12:19:10,858 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-12-13 12:19:10,858 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-12-13 12:19:10,859 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-12-13 12:19:10,860 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_67969b45-2fb3-4f9e-b865-5e7c88aeec8b/bin/uautomizer-uyxdKDjOR8/config/svcomp-Termination-32bit-Automizer_Default.epf [2022-12-13 12:19:10,882 INFO L113 SettingsManager]: Loading preferences was successful [2022-12-13 12:19:10,882 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-12-13 12:19:10,882 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-12-13 12:19:10,882 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-12-13 12:19:10,883 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-12-13 12:19:10,884 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-12-13 12:19:10,884 INFO L138 SettingsManager]: * Use SBE=true [2022-12-13 12:19:10,884 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2022-12-13 12:19:10,884 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2022-12-13 12:19:10,884 INFO L138 SettingsManager]: * Use old map elimination=false [2022-12-13 12:19:10,885 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2022-12-13 12:19:10,885 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2022-12-13 12:19:10,885 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2022-12-13 12:19:10,885 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-12-13 12:19:10,885 INFO L138 SettingsManager]: * sizeof long=4 [2022-12-13 12:19:10,886 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2022-12-13 12:19:10,886 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-12-13 12:19:10,886 INFO L138 SettingsManager]: * sizeof POINTER=4 [2022-12-13 12:19:10,886 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-12-13 12:19:10,886 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2022-12-13 12:19:10,886 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2022-12-13 12:19:10,887 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2022-12-13 12:19:10,887 INFO L138 SettingsManager]: * sizeof long double=12 [2022-12-13 12:19:10,887 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-12-13 12:19:10,887 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2022-12-13 12:19:10,887 INFO L138 SettingsManager]: * Use constant arrays=true [2022-12-13 12:19:10,887 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2022-12-13 12:19:10,888 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-12-13 12:19:10,888 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-12-13 12:19:10,888 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-12-13 12:19:10,888 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-12-13 12:19:10,889 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-12-13 12:19:10,889 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_67969b45-2fb3-4f9e-b865-5e7c88aeec8b/bin/uautomizer-uyxdKDjOR8/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_67969b45-2fb3-4f9e-b865-5e7c88aeec8b/bin/uautomizer-uyxdKDjOR8 Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> a6baa92d18991a792383fc99c5c300f37f700ba00714b15a3dbe7d2191a67ca9 [2022-12-13 12:19:11,093 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-12-13 12:19:11,112 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-12-13 12:19:11,114 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-12-13 12:19:11,115 INFO L271 PluginConnector]: Initializing CDTParser... [2022-12-13 12:19:11,115 INFO L275 PluginConnector]: CDTParser initialized [2022-12-13 12:19:11,116 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_67969b45-2fb3-4f9e-b865-5e7c88aeec8b/bin/uautomizer-uyxdKDjOR8/../../sv-benchmarks/c/systemc/token_ring.07.cil-1.c [2022-12-13 12:19:13,642 INFO L500 CDTParser]: Created temporary CDT project at NULL [2022-12-13 12:19:13,806 INFO L351 CDTParser]: Found 1 translation units. [2022-12-13 12:19:13,807 INFO L172 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_67969b45-2fb3-4f9e-b865-5e7c88aeec8b/sv-benchmarks/c/systemc/token_ring.07.cil-1.c [2022-12-13 12:19:13,814 INFO L394 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_67969b45-2fb3-4f9e-b865-5e7c88aeec8b/bin/uautomizer-uyxdKDjOR8/data/94baae59f/ef95c1e2d7204135a5408b20e67d1f2b/FLAGd137508d2 [2022-12-13 12:19:14,243 INFO L402 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_67969b45-2fb3-4f9e-b865-5e7c88aeec8b/bin/uautomizer-uyxdKDjOR8/data/94baae59f/ef95c1e2d7204135a5408b20e67d1f2b [2022-12-13 12:19:14,248 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-12-13 12:19:14,251 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-12-13 12:19:14,253 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-12-13 12:19:14,253 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-12-13 12:19:14,258 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-12-13 12:19:14,258 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.12 12:19:14" (1/1) ... [2022-12-13 12:19:14,260 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@6458fb5e and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 12:19:14, skipping insertion in model container [2022-12-13 12:19:14,260 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.12 12:19:14" (1/1) ... [2022-12-13 12:19:14,268 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-12-13 12:19:14,296 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-12-13 12:19:14,393 WARN L237 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_67969b45-2fb3-4f9e-b865-5e7c88aeec8b/sv-benchmarks/c/systemc/token_ring.07.cil-1.c[671,684] [2022-12-13 12:19:14,448 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-12-13 12:19:14,459 INFO L203 MainTranslator]: Completed pre-run [2022-12-13 12:19:14,467 WARN L237 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_67969b45-2fb3-4f9e-b865-5e7c88aeec8b/sv-benchmarks/c/systemc/token_ring.07.cil-1.c[671,684] [2022-12-13 12:19:14,499 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-12-13 12:19:14,511 INFO L208 MainTranslator]: Completed translation [2022-12-13 12:19:14,511 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 12:19:14 WrapperNode [2022-12-13 12:19:14,511 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-12-13 12:19:14,512 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-12-13 12:19:14,512 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-12-13 12:19:14,512 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-12-13 12:19:14,517 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 12:19:14" (1/1) ... [2022-12-13 12:19:14,525 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 12:19:14" (1/1) ... [2022-12-13 12:19:14,567 INFO L138 Inliner]: procedures = 42, calls = 52, calls flagged for inlining = 47, calls inlined = 134, statements flattened = 1989 [2022-12-13 12:19:14,568 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-12-13 12:19:14,568 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-12-13 12:19:14,568 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-12-13 12:19:14,568 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-12-13 12:19:14,576 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 12:19:14" (1/1) ... [2022-12-13 12:19:14,576 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 12:19:14" (1/1) ... [2022-12-13 12:19:14,580 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 12:19:14" (1/1) ... [2022-12-13 12:19:14,581 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 12:19:14" (1/1) ... [2022-12-13 12:19:14,596 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 12:19:14" (1/1) ... [2022-12-13 12:19:14,608 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 12:19:14" (1/1) ... [2022-12-13 12:19:14,612 INFO L185 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 12:19:14" (1/1) ... [2022-12-13 12:19:14,616 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 12:19:14" (1/1) ... [2022-12-13 12:19:14,622 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-12-13 12:19:14,622 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-12-13 12:19:14,622 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-12-13 12:19:14,623 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-12-13 12:19:14,623 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 12:19:14" (1/1) ... [2022-12-13 12:19:14,628 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-12-13 12:19:14,637 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_67969b45-2fb3-4f9e-b865-5e7c88aeec8b/bin/uautomizer-uyxdKDjOR8/z3 [2022-12-13 12:19:14,649 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_67969b45-2fb3-4f9e-b865-5e7c88aeec8b/bin/uautomizer-uyxdKDjOR8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-12-13 12:19:14,651 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_67969b45-2fb3-4f9e-b865-5e7c88aeec8b/bin/uautomizer-uyxdKDjOR8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2022-12-13 12:19:14,686 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-12-13 12:19:14,686 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-12-13 12:19:14,686 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-12-13 12:19:14,686 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-12-13 12:19:14,762 INFO L235 CfgBuilder]: Building ICFG [2022-12-13 12:19:14,764 INFO L261 CfgBuilder]: Building CFG for each procedure with an implementation [2022-12-13 12:19:15,689 INFO L276 CfgBuilder]: Performing block encoding [2022-12-13 12:19:15,698 INFO L295 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-12-13 12:19:15,698 INFO L300 CfgBuilder]: Removed 10 assume(true) statements. [2022-12-13 12:19:15,700 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.12 12:19:15 BoogieIcfgContainer [2022-12-13 12:19:15,700 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-12-13 12:19:15,701 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2022-12-13 12:19:15,701 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2022-12-13 12:19:15,703 INFO L275 PluginConnector]: BuchiAutomizer initialized [2022-12-13 12:19:15,704 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-12-13 12:19:15,704 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 13.12 12:19:14" (1/3) ... [2022-12-13 12:19:15,705 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@2ea084a5 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 13.12 12:19:15, skipping insertion in model container [2022-12-13 12:19:15,705 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-12-13 12:19:15,705 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 12:19:14" (2/3) ... [2022-12-13 12:19:15,705 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@2ea084a5 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 13.12 12:19:15, skipping insertion in model container [2022-12-13 12:19:15,705 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-12-13 12:19:15,705 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.12 12:19:15" (3/3) ... [2022-12-13 12:19:15,706 INFO L332 chiAutomizerObserver]: Analyzing ICFG token_ring.07.cil-1.c [2022-12-13 12:19:15,752 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2022-12-13 12:19:15,752 INFO L304 stractBuchiCegarLoop]: Hoare is false [2022-12-13 12:19:15,752 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2022-12-13 12:19:15,752 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2022-12-13 12:19:15,752 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2022-12-13 12:19:15,752 INFO L308 stractBuchiCegarLoop]: Difference is false [2022-12-13 12:19:15,752 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2022-12-13 12:19:15,752 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2022-12-13 12:19:15,757 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 836 states, 835 states have (on average 1.518562874251497) internal successors, (1268), 835 states have internal predecessors, (1268), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:19:15,789 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 729 [2022-12-13 12:19:15,789 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:19:15,789 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:19:15,797 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:19:15,797 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:19:15,797 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2022-12-13 12:19:15,799 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 836 states, 835 states have (on average 1.518562874251497) internal successors, (1268), 835 states have internal predecessors, (1268), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:19:15,808 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 729 [2022-12-13 12:19:15,808 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:19:15,808 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:19:15,810 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:19:15,810 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:19:15,816 INFO L748 eck$LassoCheckResult]: Stem: 108#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 757#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 618#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 753#update_channels_returnLabel#1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 576#L536true assume !(1 == ~m_i~0);~m_st~0 := 2; 785#L536-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 261#L541-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 147#L546-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 644#L551-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 136#L556-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 594#L561-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 573#L566-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 372#L571-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 664#L769true assume !(0 == ~M_E~0); 389#L769-2true assume !(0 == ~T1_E~0); 414#L774-1true assume !(0 == ~T2_E~0); 682#L779-1true assume !(0 == ~T3_E~0); 554#L784-1true assume !(0 == ~T4_E~0); 370#L789-1true assume !(0 == ~T5_E~0); 470#L794-1true assume 0 == ~T6_E~0;~T6_E~0 := 1; 817#L799-1true assume !(0 == ~T7_E~0); 374#L804-1true assume !(0 == ~E_M~0); 407#L809-1true assume !(0 == ~E_1~0); 587#L814-1true assume !(0 == ~E_2~0); 9#L819-1true assume !(0 == ~E_3~0); 186#L824-1true assume !(0 == ~E_4~0); 807#L829-1true assume !(0 == ~E_5~0); 677#L834-1true assume 0 == ~E_6~0;~E_6~0 := 1; 72#L839-1true assume !(0 == ~E_7~0); 476#L844-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 326#L376true assume !(1 == ~m_pc~0); 324#L376-2true is_master_triggered_~__retres1~0#1 := 0; 767#L387true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 534#is_master_triggered_returnLabel#1true activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 42#L955true assume !(0 != activate_threads_~tmp~1#1); 253#L955-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 390#L395true assume 1 == ~t1_pc~0; 60#L396true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 555#L406true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 22#is_transmit1_triggered_returnLabel#1true activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 601#L963true assume !(0 != activate_threads_~tmp___0~0#1); 332#L963-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 827#L414true assume !(1 == ~t2_pc~0); 585#L414-2true is_transmit2_triggered_~__retres1~2#1 := 0; 815#L425true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 193#is_transmit2_triggered_returnLabel#1true activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 583#L971true assume !(0 != activate_threads_~tmp___1~0#1); 693#L971-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 258#L433true assume 1 == ~t3_pc~0; 217#L434true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 703#L444true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8#is_transmit3_triggered_returnLabel#1true activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 519#L979true assume !(0 != activate_threads_~tmp___2~0#1); 54#L979-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 786#L452true assume !(1 == ~t4_pc~0); 134#L452-2true is_transmit4_triggered_~__retres1~4#1 := 0; 359#L463true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 51#is_transmit4_triggered_returnLabel#1true activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 700#L987true assume !(0 != activate_threads_~tmp___3~0#1); 152#L987-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 454#L471true assume 1 == ~t5_pc~0; 748#L472true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 142#L482true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 538#is_transmit5_triggered_returnLabel#1true activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 813#L995true assume !(0 != activate_threads_~tmp___4~0#1); 666#L995-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 734#L490true assume 1 == ~t6_pc~0; 625#L491true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 364#L501true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 183#is_transmit6_triggered_returnLabel#1true activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 367#L1003true assume !(0 != activate_threads_~tmp___5~0#1); 266#L1003-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 241#L509true assume !(1 == ~t7_pc~0); 588#L509-2true is_transmit7_triggered_~__retres1~7#1 := 0; 120#L520true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 770#is_transmit7_triggered_returnLabel#1true activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 155#L1011true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 702#L1011-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 598#L857true assume !(1 == ~M_E~0); 45#L857-2true assume !(1 == ~T1_E~0); 195#L862-1true assume !(1 == ~T2_E~0); 200#L867-1true assume !(1 == ~T3_E~0); 259#L872-1true assume 1 == ~T4_E~0;~T4_E~0 := 2; 432#L877-1true assume !(1 == ~T5_E~0); 624#L882-1true assume !(1 == ~T6_E~0); 741#L887-1true assume !(1 == ~T7_E~0); 494#L892-1true assume !(1 == ~E_M~0); 708#L897-1true assume !(1 == ~E_1~0); 210#L902-1true assume !(1 == ~E_2~0); 511#L907-1true assume !(1 == ~E_3~0); 444#L912-1true assume 1 == ~E_4~0;~E_4~0 := 2; 438#L917-1true assume !(1 == ~E_5~0); 686#L922-1true assume !(1 == ~E_6~0); 793#L927-1true assume !(1 == ~E_7~0); 429#L932-1true assume { :end_inline_reset_delta_events } true; 721#L1178-2true [2022-12-13 12:19:15,818 INFO L750 eck$LassoCheckResult]: Loop: 721#L1178-2true assume !false; 417#L1179true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 235#L744true assume !true; 497#eval_returnLabel#1true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 302#update_channels_returnLabel#2true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 662#L769-3true assume 0 == ~M_E~0;~M_E~0 := 1; 256#L769-5true assume !(0 == ~T1_E~0); 395#L774-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 96#L779-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 14#L784-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 828#L789-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 10#L794-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 31#L799-3true assume 0 == ~T7_E~0;~T7_E~0 := 1; 159#L804-3true assume 0 == ~E_M~0;~E_M~0 := 1; 328#L809-3true assume !(0 == ~E_1~0); 29#L814-3true assume 0 == ~E_2~0;~E_2~0 := 1; 565#L819-3true assume 0 == ~E_3~0;~E_3~0 := 1; 522#L824-3true assume 0 == ~E_4~0;~E_4~0 := 1; 515#L829-3true assume 0 == ~E_5~0;~E_5~0 := 1; 196#L834-3true assume 0 == ~E_6~0;~E_6~0 := 1; 469#L839-3true assume 0 == ~E_7~0;~E_7~0 := 1; 595#L844-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 733#L376-27true assume 1 == ~m_pc~0; 442#L377-9true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 393#L387-9true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 460#is_master_triggered_returnLabel#10true activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 695#L955-27true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 823#L955-29true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 808#L395-27true assume !(1 == ~t1_pc~0); 271#L395-29true is_transmit1_triggered_~__retres1~1#1 := 0; 197#L406-9true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 362#is_transmit1_triggered_returnLabel#10true activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 388#L963-27true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 262#L963-29true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 658#L414-27true assume !(1 == ~t2_pc~0); 750#L414-29true is_transmit2_triggered_~__retres1~2#1 := 0; 437#L425-9true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 435#is_transmit2_triggered_returnLabel#10true activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 315#L971-27true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 35#L971-29true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 83#L433-27true assume !(1 == ~t3_pc~0); 319#L433-29true is_transmit3_triggered_~__retres1~3#1 := 0; 268#L444-9true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 298#is_transmit3_triggered_returnLabel#10true activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 122#L979-27true assume !(0 != activate_threads_~tmp___2~0#1); 758#L979-29true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 744#L452-27true assume !(1 == ~t4_pc~0); 405#L452-29true is_transmit4_triggered_~__retres1~4#1 := 0; 558#L463-9true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 240#is_transmit4_triggered_returnLabel#10true activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 653#L987-27true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 665#L987-29true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 32#L471-27true assume !(1 == ~t5_pc~0); 206#L471-29true is_transmit5_triggered_~__retres1~5#1 := 0; 824#L482-9true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 550#is_transmit5_triggered_returnLabel#10true activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 457#L995-27true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 391#L995-29true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 325#L490-27true assume 1 == ~t6_pc~0; 236#L491-9true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 128#L501-9true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 678#is_transmit6_triggered_returnLabel#10true activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 443#L1003-27true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 716#L1003-29true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 18#L509-27true assume 1 == ~t7_pc~0; 351#L510-9true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 547#L520-9true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 163#is_transmit7_triggered_returnLabel#10true activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 345#L1011-27true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 803#L1011-29true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 355#L857-3true assume 1 == ~M_E~0;~M_E~0 := 2; 385#L857-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 790#L862-3true assume !(1 == ~T2_E~0); 735#L867-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 269#L872-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 350#L877-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 768#L882-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 382#L887-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 106#L892-3true assume 1 == ~E_M~0;~E_M~0 := 2; 545#L897-3true assume 1 == ~E_1~0;~E_1~0 := 2; 826#L902-3true assume !(1 == ~E_2~0); 209#L907-3true assume 1 == ~E_3~0;~E_3~0 := 2; 306#L912-3true assume 1 == ~E_4~0;~E_4~0 := 2; 580#L917-3true assume 1 == ~E_5~0;~E_5~0 := 2; 272#L922-3true assume 1 == ~E_6~0;~E_6~0 := 2; 135#L927-3true assume 1 == ~E_7~0;~E_7~0 := 2; 218#L932-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 59#L584-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 473#L626-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 167#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 248#L1197true assume !(0 == start_simulation_~tmp~3#1); 526#L1197-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 86#L584-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 255#L626-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 21#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 746#L1152true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 541#L1159true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 317#stop_simulation_returnLabel#1true start_simulation_#t~ret24#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 23#L1210true assume !(0 != start_simulation_~tmp___0~1#1); 721#L1178-2true [2022-12-13 12:19:15,822 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:19:15,822 INFO L85 PathProgramCache]: Analyzing trace with hash 1617538625, now seen corresponding path program 1 times [2022-12-13 12:19:15,828 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:19:15,828 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1430727657] [2022-12-13 12:19:15,829 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:19:15,829 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:19:15,898 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:19:16,003 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:19:16,004 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:19:16,004 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1430727657] [2022-12-13 12:19:16,005 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1430727657] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:19:16,005 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:19:16,005 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:19:16,006 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [934019642] [2022-12-13 12:19:16,007 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:19:16,012 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 12:19:16,012 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:19:16,013 INFO L85 PathProgramCache]: Analyzing trace with hash -412646089, now seen corresponding path program 1 times [2022-12-13 12:19:16,013 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:19:16,013 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [370809928] [2022-12-13 12:19:16,013 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:19:16,013 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:19:16,025 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:19:16,059 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:19:16,060 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:19:16,060 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [370809928] [2022-12-13 12:19:16,060 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [370809928] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:19:16,060 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:19:16,060 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-12-13 12:19:16,061 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1220419321] [2022-12-13 12:19:16,061 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:19:16,062 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:19:16,063 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:19:16,090 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 12:19:16,090 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 12:19:16,093 INFO L87 Difference]: Start difference. First operand has 836 states, 835 states have (on average 1.518562874251497) internal successors, (1268), 835 states have internal predecessors, (1268), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:19:16,139 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:19:16,139 INFO L93 Difference]: Finished difference Result 835 states and 1245 transitions. [2022-12-13 12:19:16,140 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 835 states and 1245 transitions. [2022-12-13 12:19:16,145 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 727 [2022-12-13 12:19:16,152 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 835 states to 830 states and 1240 transitions. [2022-12-13 12:19:16,152 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 830 [2022-12-13 12:19:16,153 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 830 [2022-12-13 12:19:16,154 INFO L73 IsDeterministic]: Start isDeterministic. Operand 830 states and 1240 transitions. [2022-12-13 12:19:16,157 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:19:16,157 INFO L218 hiAutomatonCegarLoop]: Abstraction has 830 states and 1240 transitions. [2022-12-13 12:19:16,171 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 830 states and 1240 transitions. [2022-12-13 12:19:16,201 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 830 to 830. [2022-12-13 12:19:16,203 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 830 states, 830 states have (on average 1.4939759036144578) internal successors, (1240), 829 states have internal predecessors, (1240), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:19:16,206 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 830 states to 830 states and 1240 transitions. [2022-12-13 12:19:16,207 INFO L240 hiAutomatonCegarLoop]: Abstraction has 830 states and 1240 transitions. [2022-12-13 12:19:16,208 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 12:19:16,212 INFO L428 stractBuchiCegarLoop]: Abstraction has 830 states and 1240 transitions. [2022-12-13 12:19:16,212 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2022-12-13 12:19:16,212 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 830 states and 1240 transitions. [2022-12-13 12:19:16,217 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 727 [2022-12-13 12:19:16,217 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:19:16,218 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:19:16,220 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:19:16,220 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:19:16,221 INFO L748 eck$LassoCheckResult]: Stem: 1903#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 1904#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 2455#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2456#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2435#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 2436#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2148#L541-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 1970#L546-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1971#L551-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1954#L556-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 1955#L561-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 2434#L566-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 2262#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2263#L769 assume !(0 == ~M_E~0); 2283#L769-2 assume !(0 == ~T1_E~0); 2284#L774-1 assume !(0 == ~T2_E~0); 2311#L779-1 assume !(0 == ~T3_E~0); 2424#L784-1 assume !(0 == ~T4_E~0); 2260#L789-1 assume !(0 == ~T5_E~0); 2261#L794-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 2364#L799-1 assume !(0 == ~T7_E~0); 2265#L804-1 assume !(0 == ~E_M~0); 2266#L809-1 assume !(0 == ~E_1~0); 2306#L814-1 assume !(0 == ~E_2~0); 1695#L819-1 assume !(0 == ~E_3~0); 1696#L824-1 assume !(0 == ~E_4~0); 2044#L829-1 assume !(0 == ~E_5~0); 2484#L834-1 assume 0 == ~E_6~0;~E_6~0 := 1; 1833#L839-1 assume !(0 == ~E_7~0); 1834#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2218#L376 assume !(1 == ~m_pc~0); 2207#L376-2 is_master_triggered_~__retres1~0#1 := 0; 2206#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2410#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1771#L955 assume !(0 != activate_threads_~tmp~1#1); 1772#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2141#L395 assume 1 == ~t1_pc~0; 1807#L396 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1808#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1725#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1726#L963 assume !(0 != activate_threads_~tmp___0~0#1); 2222#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2223#L414 assume !(1 == ~t2_pc~0); 1836#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1837#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2050#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2051#L971 assume !(0 != activate_threads_~tmp___1~0#1); 2439#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2145#L433 assume 1 == ~t3_pc~0; 2087#L434 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1943#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1693#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1694#L979 assume !(0 != activate_threads_~tmp___2~0#1); 1796#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1797#L452 assume !(1 == ~t4_pc~0); 1950#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1951#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1790#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1791#L987 assume !(0 != activate_threads_~tmp___3~0#1); 1981#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1982#L471 assume 1 == ~t5_pc~0; 2350#L472 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1965#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1966#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2413#L995 assume !(0 != activate_threads_~tmp___4~0#1); 2475#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2476#L490 assume 1 == ~t6_pc~0; 2460#L491 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 2221#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2037#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2038#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 2154#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2123#L509 assume !(1 == ~t7_pc~0); 2124#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1925#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1926#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1988#L1011 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1989#L1011-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2445#L857 assume !(1 == ~M_E~0); 1778#L857-2 assume !(1 == ~T1_E~0); 1779#L862-1 assume !(1 == ~T2_E~0); 2054#L867-1 assume !(1 == ~T3_E~0); 2059#L872-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2146#L877-1 assume !(1 == ~T5_E~0); 2328#L882-1 assume !(1 == ~T6_E~0); 2459#L887-1 assume !(1 == ~T7_E~0); 2380#L892-1 assume !(1 == ~E_M~0); 2381#L897-1 assume !(1 == ~E_1~0); 2075#L902-1 assume !(1 == ~E_2~0); 2076#L907-1 assume !(1 == ~E_3~0); 2342#L912-1 assume 1 == ~E_4~0;~E_4~0 := 2; 2334#L917-1 assume !(1 == ~E_5~0); 2335#L922-1 assume !(1 == ~E_6~0); 2486#L927-1 assume !(1 == ~E_7~0); 2323#L932-1 assume { :end_inline_reset_delta_events } true; 1728#L1178-2 [2022-12-13 12:19:16,221 INFO L750 eck$LassoCheckResult]: Loop: 1728#L1178-2 assume !false; 2312#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2102#L744 assume !false; 2117#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 2186#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1763#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1968#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 2072#L641 assume !(0 != eval_~tmp~0#1); 2382#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2193#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2194#L769-3 assume 0 == ~M_E~0;~M_E~0 := 1; 2143#L769-5 assume !(0 == ~T1_E~0); 2144#L774-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1882#L779-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1706#L784-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1707#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1697#L794-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1698#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1745#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1997#L809-3 assume !(0 == ~E_1~0); 1741#L814-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1742#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2401#L824-3 assume 0 == ~E_4~0;~E_4~0 := 1; 2396#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2055#L834-3 assume 0 == ~E_6~0;~E_6~0 := 1; 2056#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 2363#L844-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2443#L376-27 assume 1 == ~m_pc~0; 2338#L377-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 2289#L387-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2290#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2357#L955-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2488#L955-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2509#L395-27 assume !(1 == ~t1_pc~0); 2162#L395-29 is_transmit1_triggered_~__retres1~1#1 := 0; 2057#L406-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2058#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2253#L963-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2149#L963-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2150#L414-27 assume 1 == ~t2_pc~0; 2472#L415-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2333#L425-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2332#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2209#L971-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1753#L971-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1754#L433-27 assume !(1 == ~t3_pc~0); 1854#L433-29 is_transmit3_triggered_~__retres1~3#1 := 0; 2156#L444-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2157#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1928#L979-27 assume !(0 != activate_threads_~tmp___2~0#1); 1929#L979-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2500#L452-27 assume 1 == ~t4_pc~0; 2501#L453-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2304#L463-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2121#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2122#L987-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 2469#L987-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1746#L471-27 assume !(1 == ~t5_pc~0); 1747#L471-29 is_transmit5_triggered_~__retres1~5#1 := 0; 2069#L482-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2421#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2354#L995-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 2285#L995-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2217#L490-27 assume 1 == ~t6_pc~0; 2118#L491-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1939#L501-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1940#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2340#L1003-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 2341#L1003-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1715#L509-27 assume !(1 == ~t7_pc~0); 1716#L509-29 is_transmit7_triggered_~__retres1~7#1 := 0; 2120#L520-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2001#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2002#L1011-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 2237#L1011-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2249#L857-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2250#L857-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2281#L862-3 assume !(1 == ~T2_E~0); 2499#L867-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2158#L872-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2159#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2244#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 2275#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1899#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1900#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2419#L902-3 assume !(1 == ~E_2~0); 2073#L907-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2074#L912-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2197#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2163#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1952#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1953#L932-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1805#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1705#L626-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 2010#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 2011#L1197 assume !(0 == start_simulation_~tmp~3#1); 2132#L1197-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1862#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1831#L626-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1723#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 1724#L1152 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2416#L1159 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2211#stop_simulation_returnLabel#1 start_simulation_#t~ret24#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 1727#L1210 assume !(0 != start_simulation_~tmp___0~1#1); 1728#L1178-2 [2022-12-13 12:19:16,222 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:19:16,222 INFO L85 PathProgramCache]: Analyzing trace with hash -736846657, now seen corresponding path program 1 times [2022-12-13 12:19:16,222 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:19:16,222 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [568536903] [2022-12-13 12:19:16,222 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:19:16,223 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:19:16,246 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:19:16,285 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:19:16,285 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:19:16,285 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [568536903] [2022-12-13 12:19:16,286 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [568536903] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:19:16,286 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:19:16,286 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:19:16,286 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1206079926] [2022-12-13 12:19:16,286 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:19:16,287 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 12:19:16,287 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:19:16,288 INFO L85 PathProgramCache]: Analyzing trace with hash -1833724246, now seen corresponding path program 1 times [2022-12-13 12:19:16,288 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:19:16,288 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1684268712] [2022-12-13 12:19:16,288 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:19:16,288 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:19:16,307 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:19:16,353 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:19:16,353 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:19:16,354 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1684268712] [2022-12-13 12:19:16,354 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1684268712] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:19:16,354 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:19:16,354 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:19:16,354 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1557719191] [2022-12-13 12:19:16,354 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:19:16,355 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:19:16,355 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:19:16,355 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 12:19:16,356 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 12:19:16,356 INFO L87 Difference]: Start difference. First operand 830 states and 1240 transitions. cyclomatic complexity: 411 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:19:16,380 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:19:16,380 INFO L93 Difference]: Finished difference Result 830 states and 1239 transitions. [2022-12-13 12:19:16,380 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 830 states and 1239 transitions. [2022-12-13 12:19:16,387 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 727 [2022-12-13 12:19:16,392 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 830 states to 830 states and 1239 transitions. [2022-12-13 12:19:16,393 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 830 [2022-12-13 12:19:16,393 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 830 [2022-12-13 12:19:16,393 INFO L73 IsDeterministic]: Start isDeterministic. Operand 830 states and 1239 transitions. [2022-12-13 12:19:16,395 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:19:16,395 INFO L218 hiAutomatonCegarLoop]: Abstraction has 830 states and 1239 transitions. [2022-12-13 12:19:16,396 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 830 states and 1239 transitions. [2022-12-13 12:19:16,403 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 830 to 830. [2022-12-13 12:19:16,404 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 830 states, 830 states have (on average 1.4927710843373494) internal successors, (1239), 829 states have internal predecessors, (1239), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:19:16,405 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 830 states to 830 states and 1239 transitions. [2022-12-13 12:19:16,406 INFO L240 hiAutomatonCegarLoop]: Abstraction has 830 states and 1239 transitions. [2022-12-13 12:19:16,406 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 12:19:16,407 INFO L428 stractBuchiCegarLoop]: Abstraction has 830 states and 1239 transitions. [2022-12-13 12:19:16,407 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2022-12-13 12:19:16,407 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 830 states and 1239 transitions. [2022-12-13 12:19:16,409 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 727 [2022-12-13 12:19:16,409 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:19:16,409 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:19:16,411 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:19:16,411 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:19:16,411 INFO L748 eck$LassoCheckResult]: Stem: 3570#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 3571#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 4122#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4123#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4102#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 4103#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3815#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3637#L546-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 3638#L551-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 3621#L556-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 3622#L561-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 4101#L566-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 3929#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3930#L769 assume !(0 == ~M_E~0); 3950#L769-2 assume !(0 == ~T1_E~0); 3951#L774-1 assume !(0 == ~T2_E~0); 3978#L779-1 assume !(0 == ~T3_E~0); 4091#L784-1 assume !(0 == ~T4_E~0); 3927#L789-1 assume !(0 == ~T5_E~0); 3928#L794-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 4031#L799-1 assume !(0 == ~T7_E~0); 3932#L804-1 assume !(0 == ~E_M~0); 3933#L809-1 assume !(0 == ~E_1~0); 3973#L814-1 assume !(0 == ~E_2~0); 3362#L819-1 assume !(0 == ~E_3~0); 3363#L824-1 assume !(0 == ~E_4~0); 3711#L829-1 assume !(0 == ~E_5~0); 4151#L834-1 assume 0 == ~E_6~0;~E_6~0 := 1; 3500#L839-1 assume !(0 == ~E_7~0); 3501#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3885#L376 assume !(1 == ~m_pc~0); 3874#L376-2 is_master_triggered_~__retres1~0#1 := 0; 3873#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4077#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 3438#L955 assume !(0 != activate_threads_~tmp~1#1); 3439#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3808#L395 assume 1 == ~t1_pc~0; 3474#L396 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3475#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3392#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3393#L963 assume !(0 != activate_threads_~tmp___0~0#1); 3889#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3890#L414 assume !(1 == ~t2_pc~0); 3503#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 3504#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3717#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3718#L971 assume !(0 != activate_threads_~tmp___1~0#1); 4106#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3812#L433 assume 1 == ~t3_pc~0; 3754#L434 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3610#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3360#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3361#L979 assume !(0 != activate_threads_~tmp___2~0#1); 3463#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3464#L452 assume !(1 == ~t4_pc~0); 3617#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 3618#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3457#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3458#L987 assume !(0 != activate_threads_~tmp___3~0#1); 3648#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3649#L471 assume 1 == ~t5_pc~0; 4017#L472 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 3632#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3633#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4080#L995 assume !(0 != activate_threads_~tmp___4~0#1); 4142#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4143#L490 assume 1 == ~t6_pc~0; 4127#L491 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 3888#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3704#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3705#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 3821#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3790#L509 assume !(1 == ~t7_pc~0); 3791#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 3592#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3593#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3655#L1011 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 3656#L1011-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4112#L857 assume !(1 == ~M_E~0); 3445#L857-2 assume !(1 == ~T1_E~0); 3446#L862-1 assume !(1 == ~T2_E~0); 3721#L867-1 assume !(1 == ~T3_E~0); 3726#L872-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3813#L877-1 assume !(1 == ~T5_E~0); 3995#L882-1 assume !(1 == ~T6_E~0); 4126#L887-1 assume !(1 == ~T7_E~0); 4047#L892-1 assume !(1 == ~E_M~0); 4048#L897-1 assume !(1 == ~E_1~0); 3742#L902-1 assume !(1 == ~E_2~0); 3743#L907-1 assume !(1 == ~E_3~0); 4009#L912-1 assume 1 == ~E_4~0;~E_4~0 := 2; 4001#L917-1 assume !(1 == ~E_5~0); 4002#L922-1 assume !(1 == ~E_6~0); 4153#L927-1 assume !(1 == ~E_7~0); 3990#L932-1 assume { :end_inline_reset_delta_events } true; 3395#L1178-2 [2022-12-13 12:19:16,411 INFO L750 eck$LassoCheckResult]: Loop: 3395#L1178-2 assume !false; 3979#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3769#L744 assume !false; 3784#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 3853#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 3430#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 3635#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 3739#L641 assume !(0 != eval_~tmp~0#1); 4049#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3860#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3861#L769-3 assume 0 == ~M_E~0;~M_E~0 := 1; 3810#L769-5 assume !(0 == ~T1_E~0); 3811#L774-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3549#L779-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3373#L784-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3374#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 3364#L794-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 3365#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 3412#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 3664#L809-3 assume !(0 == ~E_1~0); 3408#L814-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3409#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4068#L824-3 assume 0 == ~E_4~0;~E_4~0 := 1; 4063#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 3722#L834-3 assume 0 == ~E_6~0;~E_6~0 := 1; 3723#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 4030#L844-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4110#L376-27 assume 1 == ~m_pc~0; 4005#L377-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 3956#L387-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3957#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4024#L955-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4155#L955-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4176#L395-27 assume !(1 == ~t1_pc~0); 3829#L395-29 is_transmit1_triggered_~__retres1~1#1 := 0; 3724#L406-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3725#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3920#L963-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3816#L963-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3817#L414-27 assume 1 == ~t2_pc~0; 4139#L415-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4000#L425-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3999#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3876#L971-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3420#L971-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3421#L433-27 assume !(1 == ~t3_pc~0); 3521#L433-29 is_transmit3_triggered_~__retres1~3#1 := 0; 3823#L444-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3824#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3595#L979-27 assume !(0 != activate_threads_~tmp___2~0#1); 3596#L979-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4167#L452-27 assume !(1 == ~t4_pc~0); 3970#L452-29 is_transmit4_triggered_~__retres1~4#1 := 0; 3971#L463-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3788#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3789#L987-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 4136#L987-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3413#L471-27 assume !(1 == ~t5_pc~0); 3414#L471-29 is_transmit5_triggered_~__retres1~5#1 := 0; 3736#L482-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4088#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4021#L995-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 3952#L995-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3884#L490-27 assume 1 == ~t6_pc~0; 3785#L491-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 3606#L501-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3607#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4007#L1003-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 4008#L1003-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3382#L509-27 assume !(1 == ~t7_pc~0); 3383#L509-29 is_transmit7_triggered_~__retres1~7#1 := 0; 3787#L520-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3668#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3669#L1011-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 3904#L1011-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3916#L857-3 assume 1 == ~M_E~0;~M_E~0 := 2; 3917#L857-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3948#L862-3 assume !(1 == ~T2_E~0); 4166#L867-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3825#L872-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3826#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3911#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 3942#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 3566#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 3567#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4086#L902-3 assume !(1 == ~E_2~0); 3740#L907-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3741#L912-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3864#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3830#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 3619#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 3620#L932-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 3472#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 3372#L626-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 3677#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 3678#L1197 assume !(0 == start_simulation_~tmp~3#1); 3799#L1197-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 3529#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 3498#L626-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 3390#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 3391#L1152 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4083#L1159 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3878#stop_simulation_returnLabel#1 start_simulation_#t~ret24#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 3394#L1210 assume !(0 != start_simulation_~tmp___0~1#1); 3395#L1178-2 [2022-12-13 12:19:16,412 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:19:16,412 INFO L85 PathProgramCache]: Analyzing trace with hash 33886909, now seen corresponding path program 1 times [2022-12-13 12:19:16,412 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:19:16,412 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1413912593] [2022-12-13 12:19:16,412 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:19:16,412 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:19:16,420 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:19:16,442 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:19:16,442 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:19:16,443 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1413912593] [2022-12-13 12:19:16,443 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1413912593] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:19:16,443 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:19:16,443 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:19:16,443 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1479264633] [2022-12-13 12:19:16,443 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:19:16,444 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 12:19:16,444 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:19:16,445 INFO L85 PathProgramCache]: Analyzing trace with hash -2107502741, now seen corresponding path program 1 times [2022-12-13 12:19:16,445 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:19:16,445 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [292561551] [2022-12-13 12:19:16,445 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:19:16,445 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:19:16,458 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:19:16,489 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:19:16,489 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:19:16,489 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [292561551] [2022-12-13 12:19:16,489 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [292561551] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:19:16,489 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:19:16,490 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:19:16,490 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [618550606] [2022-12-13 12:19:16,490 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:19:16,490 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:19:16,490 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:19:16,491 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 12:19:16,491 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 12:19:16,491 INFO L87 Difference]: Start difference. First operand 830 states and 1239 transitions. cyclomatic complexity: 410 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:19:16,508 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:19:16,508 INFO L93 Difference]: Finished difference Result 830 states and 1238 transitions. [2022-12-13 12:19:16,508 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 830 states and 1238 transitions. [2022-12-13 12:19:16,511 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 727 [2022-12-13 12:19:16,514 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 830 states to 830 states and 1238 transitions. [2022-12-13 12:19:16,514 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 830 [2022-12-13 12:19:16,514 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 830 [2022-12-13 12:19:16,514 INFO L73 IsDeterministic]: Start isDeterministic. Operand 830 states and 1238 transitions. [2022-12-13 12:19:16,515 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:19:16,515 INFO L218 hiAutomatonCegarLoop]: Abstraction has 830 states and 1238 transitions. [2022-12-13 12:19:16,516 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 830 states and 1238 transitions. [2022-12-13 12:19:16,530 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 830 to 830. [2022-12-13 12:19:16,531 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 830 states, 830 states have (on average 1.491566265060241) internal successors, (1238), 829 states have internal predecessors, (1238), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:19:16,533 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 830 states to 830 states and 1238 transitions. [2022-12-13 12:19:16,533 INFO L240 hiAutomatonCegarLoop]: Abstraction has 830 states and 1238 transitions. [2022-12-13 12:19:16,533 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 12:19:16,534 INFO L428 stractBuchiCegarLoop]: Abstraction has 830 states and 1238 transitions. [2022-12-13 12:19:16,534 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2022-12-13 12:19:16,534 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 830 states and 1238 transitions. [2022-12-13 12:19:16,536 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 727 [2022-12-13 12:19:16,536 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:19:16,536 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:19:16,537 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:19:16,537 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:19:16,538 INFO L748 eck$LassoCheckResult]: Stem: 5237#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 5238#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 5789#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5790#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5769#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 5770#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5482#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5304#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 5305#L551-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 5288#L556-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 5289#L561-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 5768#L566-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 5596#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5597#L769 assume !(0 == ~M_E~0); 5617#L769-2 assume !(0 == ~T1_E~0); 5618#L774-1 assume !(0 == ~T2_E~0); 5645#L779-1 assume !(0 == ~T3_E~0); 5758#L784-1 assume !(0 == ~T4_E~0); 5594#L789-1 assume !(0 == ~T5_E~0); 5595#L794-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 5698#L799-1 assume !(0 == ~T7_E~0); 5599#L804-1 assume !(0 == ~E_M~0); 5600#L809-1 assume !(0 == ~E_1~0); 5640#L814-1 assume !(0 == ~E_2~0); 5029#L819-1 assume !(0 == ~E_3~0); 5030#L824-1 assume !(0 == ~E_4~0); 5378#L829-1 assume !(0 == ~E_5~0); 5818#L834-1 assume 0 == ~E_6~0;~E_6~0 := 1; 5167#L839-1 assume !(0 == ~E_7~0); 5168#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5552#L376 assume !(1 == ~m_pc~0); 5541#L376-2 is_master_triggered_~__retres1~0#1 := 0; 5540#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5744#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 5105#L955 assume !(0 != activate_threads_~tmp~1#1); 5106#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5475#L395 assume 1 == ~t1_pc~0; 5141#L396 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 5142#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5059#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 5060#L963 assume !(0 != activate_threads_~tmp___0~0#1); 5556#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5557#L414 assume !(1 == ~t2_pc~0); 5170#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 5171#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5384#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5385#L971 assume !(0 != activate_threads_~tmp___1~0#1); 5773#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5479#L433 assume 1 == ~t3_pc~0; 5421#L434 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 5277#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5027#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 5028#L979 assume !(0 != activate_threads_~tmp___2~0#1); 5130#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5131#L452 assume !(1 == ~t4_pc~0); 5284#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 5285#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5124#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 5125#L987 assume !(0 != activate_threads_~tmp___3~0#1); 5315#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5316#L471 assume 1 == ~t5_pc~0; 5684#L472 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 5299#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5300#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 5747#L995 assume !(0 != activate_threads_~tmp___4~0#1); 5809#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 5810#L490 assume 1 == ~t6_pc~0; 5794#L491 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 5555#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5371#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 5372#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 5488#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5457#L509 assume !(1 == ~t7_pc~0); 5458#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 5259#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5260#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 5322#L1011 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 5323#L1011-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5779#L857 assume !(1 == ~M_E~0); 5112#L857-2 assume !(1 == ~T1_E~0); 5113#L862-1 assume !(1 == ~T2_E~0); 5388#L867-1 assume !(1 == ~T3_E~0); 5393#L872-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5480#L877-1 assume !(1 == ~T5_E~0); 5662#L882-1 assume !(1 == ~T6_E~0); 5793#L887-1 assume !(1 == ~T7_E~0); 5714#L892-1 assume !(1 == ~E_M~0); 5715#L897-1 assume !(1 == ~E_1~0); 5409#L902-1 assume !(1 == ~E_2~0); 5410#L907-1 assume !(1 == ~E_3~0); 5676#L912-1 assume 1 == ~E_4~0;~E_4~0 := 2; 5668#L917-1 assume !(1 == ~E_5~0); 5669#L922-1 assume !(1 == ~E_6~0); 5820#L927-1 assume !(1 == ~E_7~0); 5657#L932-1 assume { :end_inline_reset_delta_events } true; 5062#L1178-2 [2022-12-13 12:19:16,538 INFO L750 eck$LassoCheckResult]: Loop: 5062#L1178-2 assume !false; 5646#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5436#L744 assume !false; 5451#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 5520#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 5097#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 5302#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 5406#L641 assume !(0 != eval_~tmp~0#1); 5716#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5527#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5528#L769-3 assume 0 == ~M_E~0;~M_E~0 := 1; 5477#L769-5 assume !(0 == ~T1_E~0); 5478#L774-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 5216#L779-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5040#L784-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5041#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 5031#L794-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 5032#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 5079#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 5331#L809-3 assume !(0 == ~E_1~0); 5075#L814-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5076#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 5735#L824-3 assume 0 == ~E_4~0;~E_4~0 := 1; 5730#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 5389#L834-3 assume 0 == ~E_6~0;~E_6~0 := 1; 5390#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 5697#L844-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5777#L376-27 assume 1 == ~m_pc~0; 5672#L377-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 5623#L387-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5624#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 5691#L955-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 5822#L955-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5843#L395-27 assume !(1 == ~t1_pc~0); 5496#L395-29 is_transmit1_triggered_~__retres1~1#1 := 0; 5391#L406-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5392#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 5587#L963-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 5483#L963-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5484#L414-27 assume 1 == ~t2_pc~0; 5806#L415-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5667#L425-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5666#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5543#L971-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 5087#L971-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5088#L433-27 assume !(1 == ~t3_pc~0); 5188#L433-29 is_transmit3_triggered_~__retres1~3#1 := 0; 5490#L444-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5491#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 5262#L979-27 assume !(0 != activate_threads_~tmp___2~0#1); 5263#L979-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5834#L452-27 assume !(1 == ~t4_pc~0); 5637#L452-29 is_transmit4_triggered_~__retres1~4#1 := 0; 5638#L463-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5455#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 5456#L987-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 5803#L987-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5080#L471-27 assume !(1 == ~t5_pc~0); 5081#L471-29 is_transmit5_triggered_~__retres1~5#1 := 0; 5403#L482-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5755#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 5688#L995-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 5619#L995-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 5551#L490-27 assume 1 == ~t6_pc~0; 5452#L491-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 5273#L501-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5274#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 5674#L1003-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 5675#L1003-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5049#L509-27 assume !(1 == ~t7_pc~0); 5050#L509-29 is_transmit7_triggered_~__retres1~7#1 := 0; 5454#L520-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5335#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 5336#L1011-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 5571#L1011-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5583#L857-3 assume 1 == ~M_E~0;~M_E~0 := 2; 5584#L857-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5615#L862-3 assume !(1 == ~T2_E~0); 5833#L867-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 5492#L872-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5493#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 5578#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 5609#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 5233#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 5234#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5753#L902-3 assume !(1 == ~E_2~0); 5407#L907-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5408#L912-3 assume 1 == ~E_4~0;~E_4~0 := 2; 5531#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 5497#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 5286#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 5287#L932-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 5139#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 5039#L626-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 5344#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 5345#L1197 assume !(0 == start_simulation_~tmp~3#1); 5466#L1197-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 5196#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 5165#L626-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 5057#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 5058#L1152 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5750#L1159 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5545#stop_simulation_returnLabel#1 start_simulation_#t~ret24#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 5061#L1210 assume !(0 != start_simulation_~tmp___0~1#1); 5062#L1178-2 [2022-12-13 12:19:16,538 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:19:16,538 INFO L85 PathProgramCache]: Analyzing trace with hash 1028580607, now seen corresponding path program 1 times [2022-12-13 12:19:16,538 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:19:16,539 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1572860722] [2022-12-13 12:19:16,539 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:19:16,539 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:19:16,546 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:19:16,566 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:19:16,566 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:19:16,566 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1572860722] [2022-12-13 12:19:16,566 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1572860722] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:19:16,566 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:19:16,566 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:19:16,567 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1292310700] [2022-12-13 12:19:16,567 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:19:16,567 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 12:19:16,568 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:19:16,568 INFO L85 PathProgramCache]: Analyzing trace with hash -2107502741, now seen corresponding path program 2 times [2022-12-13 12:19:16,568 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:19:16,568 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1507740041] [2022-12-13 12:19:16,568 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:19:16,569 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:19:16,580 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:19:16,606 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:19:16,606 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:19:16,606 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1507740041] [2022-12-13 12:19:16,606 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1507740041] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:19:16,606 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:19:16,606 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:19:16,606 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [440872755] [2022-12-13 12:19:16,606 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:19:16,607 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:19:16,607 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:19:16,607 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 12:19:16,607 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 12:19:16,607 INFO L87 Difference]: Start difference. First operand 830 states and 1238 transitions. cyclomatic complexity: 409 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:19:16,621 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:19:16,621 INFO L93 Difference]: Finished difference Result 830 states and 1237 transitions. [2022-12-13 12:19:16,621 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 830 states and 1237 transitions. [2022-12-13 12:19:16,624 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 727 [2022-12-13 12:19:16,626 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 830 states to 830 states and 1237 transitions. [2022-12-13 12:19:16,626 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 830 [2022-12-13 12:19:16,626 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 830 [2022-12-13 12:19:16,627 INFO L73 IsDeterministic]: Start isDeterministic. Operand 830 states and 1237 transitions. [2022-12-13 12:19:16,627 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:19:16,627 INFO L218 hiAutomatonCegarLoop]: Abstraction has 830 states and 1237 transitions. [2022-12-13 12:19:16,628 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 830 states and 1237 transitions. [2022-12-13 12:19:16,634 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 830 to 830. [2022-12-13 12:19:16,635 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 830 states, 830 states have (on average 1.4903614457831325) internal successors, (1237), 829 states have internal predecessors, (1237), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:19:16,637 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 830 states to 830 states and 1237 transitions. [2022-12-13 12:19:16,637 INFO L240 hiAutomatonCegarLoop]: Abstraction has 830 states and 1237 transitions. [2022-12-13 12:19:16,638 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 12:19:16,638 INFO L428 stractBuchiCegarLoop]: Abstraction has 830 states and 1237 transitions. [2022-12-13 12:19:16,638 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2022-12-13 12:19:16,638 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 830 states and 1237 transitions. [2022-12-13 12:19:16,640 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 727 [2022-12-13 12:19:16,641 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:19:16,641 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:19:16,642 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:19:16,642 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:19:16,642 INFO L748 eck$LassoCheckResult]: Stem: 6906#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 6907#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 7456#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 7457#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7436#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 7437#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7149#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 6971#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 6972#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 6955#L556-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 6956#L561-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 7435#L566-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 7263#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7264#L769 assume !(0 == ~M_E~0); 7284#L769-2 assume !(0 == ~T1_E~0); 7285#L774-1 assume !(0 == ~T2_E~0); 7312#L779-1 assume !(0 == ~T3_E~0); 7425#L784-1 assume !(0 == ~T4_E~0); 7261#L789-1 assume !(0 == ~T5_E~0); 7262#L794-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 7365#L799-1 assume !(0 == ~T7_E~0); 7266#L804-1 assume !(0 == ~E_M~0); 7267#L809-1 assume !(0 == ~E_1~0); 7307#L814-1 assume !(0 == ~E_2~0); 6698#L819-1 assume !(0 == ~E_3~0); 6699#L824-1 assume !(0 == ~E_4~0); 7045#L829-1 assume !(0 == ~E_5~0); 7485#L834-1 assume 0 == ~E_6~0;~E_6~0 := 1; 6834#L839-1 assume !(0 == ~E_7~0); 6835#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7219#L376 assume !(1 == ~m_pc~0); 7212#L376-2 is_master_triggered_~__retres1~0#1 := 0; 7211#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7411#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 6774#L955 assume !(0 != activate_threads_~tmp~1#1); 6775#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7142#L395 assume 1 == ~t1_pc~0; 6808#L396 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 6809#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6726#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 6727#L963 assume !(0 != activate_threads_~tmp___0~0#1); 7224#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7225#L414 assume !(1 == ~t2_pc~0); 6837#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 6838#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7051#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 7052#L971 assume !(0 != activate_threads_~tmp___1~0#1); 7440#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7146#L433 assume 1 == ~t3_pc~0; 7088#L434 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 6946#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6694#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 6695#L979 assume !(0 != activate_threads_~tmp___2~0#1); 6797#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6798#L452 assume !(1 == ~t4_pc~0); 6951#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 6952#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6791#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6792#L987 assume !(0 != activate_threads_~tmp___3~0#1); 6982#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6983#L471 assume 1 == ~t5_pc~0; 7351#L472 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 6966#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6967#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 7414#L995 assume !(0 != activate_threads_~tmp___4~0#1); 7476#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7477#L490 assume 1 == ~t6_pc~0; 7462#L491 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 7222#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 7038#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 7039#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 7157#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 7124#L509 assume !(1 == ~t7_pc~0); 7125#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 6931#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 6932#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 6989#L1011 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 6990#L1011-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7446#L857 assume !(1 == ~M_E~0); 6779#L857-2 assume !(1 == ~T1_E~0); 6780#L862-1 assume !(1 == ~T2_E~0); 7055#L867-1 assume !(1 == ~T3_E~0); 7060#L872-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 7147#L877-1 assume !(1 == ~T5_E~0); 7329#L882-1 assume !(1 == ~T6_E~0); 7460#L887-1 assume !(1 == ~T7_E~0); 7381#L892-1 assume !(1 == ~E_M~0); 7382#L897-1 assume !(1 == ~E_1~0); 7078#L902-1 assume !(1 == ~E_2~0); 7079#L907-1 assume !(1 == ~E_3~0); 7345#L912-1 assume 1 == ~E_4~0;~E_4~0 := 2; 7335#L917-1 assume !(1 == ~E_5~0); 7336#L922-1 assume !(1 == ~E_6~0); 7487#L927-1 assume !(1 == ~E_7~0); 7324#L932-1 assume { :end_inline_reset_delta_events } true; 6729#L1178-2 [2022-12-13 12:19:16,642 INFO L750 eck$LassoCheckResult]: Loop: 6729#L1178-2 assume !false; 7313#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 7103#L744 assume !false; 7118#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 7187#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 6764#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 6969#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 7075#L641 assume !(0 != eval_~tmp~0#1); 7383#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 7194#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 7195#L769-3 assume 0 == ~M_E~0;~M_E~0 := 1; 7144#L769-5 assume !(0 == ~T1_E~0); 7145#L774-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 6885#L779-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 6707#L784-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 6708#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 6700#L794-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 6701#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 6746#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 6999#L809-3 assume !(0 == ~E_1~0); 6744#L814-3 assume 0 == ~E_2~0;~E_2~0 := 1; 6745#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 7403#L824-3 assume 0 == ~E_4~0;~E_4~0 := 1; 7397#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 7058#L834-3 assume 0 == ~E_6~0;~E_6~0 := 1; 7059#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 7364#L844-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7444#L376-27 assume 1 == ~m_pc~0; 7339#L377-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 7290#L387-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7291#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 7358#L955-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 7489#L955-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7510#L395-27 assume 1 == ~t1_pc~0; 7506#L396-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 7056#L406-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7057#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 7254#L963-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 7150#L963-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7151#L414-27 assume 1 == ~t2_pc~0; 7473#L415-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 7334#L425-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7333#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 7207#L971-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 6754#L971-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6755#L433-27 assume !(1 == ~t3_pc~0); 6855#L433-29 is_transmit3_triggered_~__retres1~3#1 := 0; 7155#L444-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7156#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 6927#L979-27 assume !(0 != activate_threads_~tmp___2~0#1); 6928#L979-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7501#L452-27 assume !(1 == ~t4_pc~0); 7304#L452-29 is_transmit4_triggered_~__retres1~4#1 := 0; 7305#L463-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7122#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 7123#L987-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 7470#L987-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6747#L471-27 assume !(1 == ~t5_pc~0); 6748#L471-29 is_transmit5_triggered_~__retres1~5#1 := 0; 7066#L482-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7422#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 7355#L995-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 7286#L995-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7218#L490-27 assume !(1 == ~t6_pc~0); 7120#L490-29 is_transmit6_triggered_~__retres1~6#1 := 0; 6940#L501-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6941#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 7341#L1003-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 7342#L1003-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6716#L509-27 assume !(1 == ~t7_pc~0); 6717#L509-29 is_transmit7_triggered_~__retres1~7#1 := 0; 7121#L520-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 7002#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 7003#L1011-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 7238#L1011-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7250#L857-3 assume 1 == ~M_E~0;~M_E~0 := 2; 7251#L857-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 7282#L862-3 assume !(1 == ~T2_E~0); 7500#L867-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 7159#L872-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 7160#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 7245#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 7276#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 6898#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 6899#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 7420#L902-3 assume !(1 == ~E_2~0); 7073#L907-3 assume 1 == ~E_3~0;~E_3~0 := 2; 7074#L912-3 assume 1 == ~E_4~0;~E_4~0 := 2; 7198#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 7164#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 6953#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 6954#L932-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 6806#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 6706#L626-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 7011#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 7012#L1197 assume !(0 == start_simulation_~tmp~3#1); 7132#L1197-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 6863#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 6832#L626-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 6724#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 6725#L1152 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 7417#L1159 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 7209#stop_simulation_returnLabel#1 start_simulation_#t~ret24#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 6728#L1210 assume !(0 != start_simulation_~tmp___0~1#1); 6729#L1178-2 [2022-12-13 12:19:16,643 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:19:16,643 INFO L85 PathProgramCache]: Analyzing trace with hash 1614856829, now seen corresponding path program 1 times [2022-12-13 12:19:16,643 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:19:16,643 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [853747455] [2022-12-13 12:19:16,643 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:19:16,643 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:19:16,650 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:19:16,671 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:19:16,671 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:19:16,671 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [853747455] [2022-12-13 12:19:16,672 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [853747455] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:19:16,672 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:19:16,672 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:19:16,672 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1507947213] [2022-12-13 12:19:16,672 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:19:16,673 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 12:19:16,673 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:19:16,673 INFO L85 PathProgramCache]: Analyzing trace with hash -637356245, now seen corresponding path program 1 times [2022-12-13 12:19:16,673 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:19:16,673 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [928433208] [2022-12-13 12:19:16,674 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:19:16,674 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:19:16,683 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:19:16,706 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:19:16,706 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:19:16,707 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [928433208] [2022-12-13 12:19:16,707 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [928433208] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:19:16,707 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:19:16,707 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:19:16,707 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1109610915] [2022-12-13 12:19:16,707 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:19:16,708 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:19:16,708 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:19:16,708 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 12:19:16,708 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 12:19:16,709 INFO L87 Difference]: Start difference. First operand 830 states and 1237 transitions. cyclomatic complexity: 408 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:19:16,734 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:19:16,734 INFO L93 Difference]: Finished difference Result 830 states and 1236 transitions. [2022-12-13 12:19:16,734 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 830 states and 1236 transitions. [2022-12-13 12:19:16,737 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 727 [2022-12-13 12:19:16,740 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 830 states to 830 states and 1236 transitions. [2022-12-13 12:19:16,740 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 830 [2022-12-13 12:19:16,741 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 830 [2022-12-13 12:19:16,741 INFO L73 IsDeterministic]: Start isDeterministic. Operand 830 states and 1236 transitions. [2022-12-13 12:19:16,742 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:19:16,742 INFO L218 hiAutomatonCegarLoop]: Abstraction has 830 states and 1236 transitions. [2022-12-13 12:19:16,743 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 830 states and 1236 transitions. [2022-12-13 12:19:16,750 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 830 to 830. [2022-12-13 12:19:16,752 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 830 states, 830 states have (on average 1.489156626506024) internal successors, (1236), 829 states have internal predecessors, (1236), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:19:16,754 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 830 states to 830 states and 1236 transitions. [2022-12-13 12:19:16,754 INFO L240 hiAutomatonCegarLoop]: Abstraction has 830 states and 1236 transitions. [2022-12-13 12:19:16,754 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 12:19:16,755 INFO L428 stractBuchiCegarLoop]: Abstraction has 830 states and 1236 transitions. [2022-12-13 12:19:16,755 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2022-12-13 12:19:16,755 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 830 states and 1236 transitions. [2022-12-13 12:19:16,758 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 727 [2022-12-13 12:19:16,758 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:19:16,758 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:19:16,759 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:19:16,759 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:19:16,760 INFO L748 eck$LassoCheckResult]: Stem: 8571#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 8572#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 9123#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 9124#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 9103#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 9104#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 8816#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 8638#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 8639#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 8622#L556-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 8623#L561-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 9102#L566-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 8930#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8931#L769 assume !(0 == ~M_E~0); 8951#L769-2 assume !(0 == ~T1_E~0); 8952#L774-1 assume !(0 == ~T2_E~0); 8979#L779-1 assume !(0 == ~T3_E~0); 9092#L784-1 assume !(0 == ~T4_E~0); 8928#L789-1 assume !(0 == ~T5_E~0); 8929#L794-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 9032#L799-1 assume !(0 == ~T7_E~0); 8933#L804-1 assume !(0 == ~E_M~0); 8934#L809-1 assume !(0 == ~E_1~0); 8974#L814-1 assume !(0 == ~E_2~0); 8365#L819-1 assume !(0 == ~E_3~0); 8366#L824-1 assume !(0 == ~E_4~0); 8712#L829-1 assume !(0 == ~E_5~0); 9152#L834-1 assume 0 == ~E_6~0;~E_6~0 := 1; 8501#L839-1 assume !(0 == ~E_7~0); 8502#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8886#L376 assume !(1 == ~m_pc~0); 8876#L376-2 is_master_triggered_~__retres1~0#1 := 0; 8875#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9078#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 8439#L955 assume !(0 != activate_threads_~tmp~1#1); 8440#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8809#L395 assume 1 == ~t1_pc~0; 8475#L396 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 8476#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8393#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 8394#L963 assume !(0 != activate_threads_~tmp___0~0#1); 8890#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8891#L414 assume !(1 == ~t2_pc~0); 8504#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 8505#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8718#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 8719#L971 assume !(0 != activate_threads_~tmp___1~0#1); 9107#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8813#L433 assume 1 == ~t3_pc~0; 8755#L434 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 8613#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8361#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 8362#L979 assume !(0 != activate_threads_~tmp___2~0#1); 8464#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8465#L452 assume !(1 == ~t4_pc~0); 8618#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 8619#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8458#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 8459#L987 assume !(0 != activate_threads_~tmp___3~0#1); 8649#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8650#L471 assume 1 == ~t5_pc~0; 9018#L472 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 8633#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8634#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 9081#L995 assume !(0 != activate_threads_~tmp___4~0#1); 9143#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 9144#L490 assume 1 == ~t6_pc~0; 9128#L491 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 8889#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8705#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8706#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 8822#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8791#L509 assume !(1 == ~t7_pc~0); 8792#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 8595#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8596#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8656#L1011 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 8657#L1011-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9113#L857 assume !(1 == ~M_E~0); 8446#L857-2 assume !(1 == ~T1_E~0); 8447#L862-1 assume !(1 == ~T2_E~0); 8722#L867-1 assume !(1 == ~T3_E~0); 8727#L872-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8814#L877-1 assume !(1 == ~T5_E~0); 8996#L882-1 assume !(1 == ~T6_E~0); 9127#L887-1 assume !(1 == ~T7_E~0); 9048#L892-1 assume !(1 == ~E_M~0); 9049#L897-1 assume !(1 == ~E_1~0); 8743#L902-1 assume !(1 == ~E_2~0); 8744#L907-1 assume !(1 == ~E_3~0); 9012#L912-1 assume 1 == ~E_4~0;~E_4~0 := 2; 9002#L917-1 assume !(1 == ~E_5~0); 9003#L922-1 assume !(1 == ~E_6~0); 9154#L927-1 assume !(1 == ~E_7~0); 8991#L932-1 assume { :end_inline_reset_delta_events } true; 8396#L1178-2 [2022-12-13 12:19:16,760 INFO L750 eck$LassoCheckResult]: Loop: 8396#L1178-2 assume !false; 8980#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 8770#L744 assume !false; 8785#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 8854#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 8431#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 8636#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 8742#L641 assume !(0 != eval_~tmp~0#1); 9050#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 8861#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 8862#L769-3 assume 0 == ~M_E~0;~M_E~0 := 1; 8811#L769-5 assume !(0 == ~T1_E~0); 8812#L774-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 8550#L779-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 8374#L784-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 8375#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 8367#L794-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 8368#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 8413#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 8666#L809-3 assume !(0 == ~E_1~0); 8409#L814-3 assume 0 == ~E_2~0;~E_2~0 := 1; 8410#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 9069#L824-3 assume 0 == ~E_4~0;~E_4~0 := 1; 9064#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 8723#L834-3 assume 0 == ~E_6~0;~E_6~0 := 1; 8724#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 9031#L844-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9111#L376-27 assume 1 == ~m_pc~0; 9006#L377-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 8957#L387-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8958#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 9025#L955-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 9156#L955-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9177#L395-27 assume 1 == ~t1_pc~0; 9173#L396-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 8725#L406-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8726#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 8921#L963-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 8817#L963-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8818#L414-27 assume 1 == ~t2_pc~0; 9140#L415-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 9001#L425-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9000#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 8878#L971-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 8421#L971-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8422#L433-27 assume !(1 == ~t3_pc~0); 8522#L433-29 is_transmit3_triggered_~__retres1~3#1 := 0; 8824#L444-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8825#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 8598#L979-27 assume !(0 != activate_threads_~tmp___2~0#1); 8599#L979-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9168#L452-27 assume 1 == ~t4_pc~0; 9169#L453-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 8972#L463-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8789#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 8790#L987-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 9137#L987-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8414#L471-27 assume 1 == ~t5_pc~0; 8416#L472-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 8737#L482-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9089#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 9022#L995-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 8953#L995-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8885#L490-27 assume 1 == ~t6_pc~0; 8786#L491-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 8607#L501-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8608#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 9008#L1003-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 9009#L1003-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8383#L509-27 assume !(1 == ~t7_pc~0); 8384#L509-29 is_transmit7_triggered_~__retres1~7#1 := 0; 8788#L520-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8669#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8670#L1011-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 8904#L1011-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8917#L857-3 assume 1 == ~M_E~0;~M_E~0 := 2; 8918#L857-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 8947#L862-3 assume !(1 == ~T2_E~0); 9167#L867-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 8826#L872-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8827#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 8912#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 8942#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 8565#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 8566#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 9087#L902-3 assume !(1 == ~E_2~0); 8740#L907-3 assume 1 == ~E_3~0;~E_3~0 := 2; 8741#L912-3 assume 1 == ~E_4~0;~E_4~0 := 2; 8865#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 8830#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 8620#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 8621#L932-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 8473#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 8371#L626-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 8678#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 8679#L1197 assume !(0 == start_simulation_~tmp~3#1); 8798#L1197-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 8527#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 8499#L626-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 8391#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 8392#L1152 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 9084#L1159 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 8873#stop_simulation_returnLabel#1 start_simulation_#t~ret24#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 8395#L1210 assume !(0 != start_simulation_~tmp___0~1#1); 8396#L1178-2 [2022-12-13 12:19:16,760 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:19:16,760 INFO L85 PathProgramCache]: Analyzing trace with hash -721535681, now seen corresponding path program 1 times [2022-12-13 12:19:16,761 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:19:16,761 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [820488557] [2022-12-13 12:19:16,761 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:19:16,761 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:19:16,769 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:19:16,789 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:19:16,789 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:19:16,790 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [820488557] [2022-12-13 12:19:16,790 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [820488557] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:19:16,790 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:19:16,790 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:19:16,790 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1501624468] [2022-12-13 12:19:16,791 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:19:16,791 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 12:19:16,791 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:19:16,791 INFO L85 PathProgramCache]: Analyzing trace with hash 2015039144, now seen corresponding path program 1 times [2022-12-13 12:19:16,792 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:19:16,792 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2020285399] [2022-12-13 12:19:16,792 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:19:16,792 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:19:16,804 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:19:16,829 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:19:16,830 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:19:16,830 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2020285399] [2022-12-13 12:19:16,830 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2020285399] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:19:16,830 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:19:16,830 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:19:16,830 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1943060111] [2022-12-13 12:19:16,830 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:19:16,831 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:19:16,831 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:19:16,831 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 12:19:16,831 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 12:19:16,831 INFO L87 Difference]: Start difference. First operand 830 states and 1236 transitions. cyclomatic complexity: 407 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:19:16,844 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:19:16,844 INFO L93 Difference]: Finished difference Result 830 states and 1235 transitions. [2022-12-13 12:19:16,844 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 830 states and 1235 transitions. [2022-12-13 12:19:16,847 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 727 [2022-12-13 12:19:16,849 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 830 states to 830 states and 1235 transitions. [2022-12-13 12:19:16,849 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 830 [2022-12-13 12:19:16,850 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 830 [2022-12-13 12:19:16,850 INFO L73 IsDeterministic]: Start isDeterministic. Operand 830 states and 1235 transitions. [2022-12-13 12:19:16,850 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:19:16,850 INFO L218 hiAutomatonCegarLoop]: Abstraction has 830 states and 1235 transitions. [2022-12-13 12:19:16,851 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 830 states and 1235 transitions. [2022-12-13 12:19:16,857 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 830 to 830. [2022-12-13 12:19:16,858 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 830 states, 830 states have (on average 1.4879518072289157) internal successors, (1235), 829 states have internal predecessors, (1235), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:19:16,859 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 830 states to 830 states and 1235 transitions. [2022-12-13 12:19:16,859 INFO L240 hiAutomatonCegarLoop]: Abstraction has 830 states and 1235 transitions. [2022-12-13 12:19:16,859 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 12:19:16,860 INFO L428 stractBuchiCegarLoop]: Abstraction has 830 states and 1235 transitions. [2022-12-13 12:19:16,860 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2022-12-13 12:19:16,860 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 830 states and 1235 transitions. [2022-12-13 12:19:16,862 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 727 [2022-12-13 12:19:16,862 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:19:16,862 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:19:16,863 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:19:16,863 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:19:16,863 INFO L748 eck$LassoCheckResult]: Stem: 10238#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 10239#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 10790#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 10791#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 10770#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 10771#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 10483#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 10305#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 10306#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 10289#L556-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 10290#L561-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 10769#L566-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 10597#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 10598#L769 assume !(0 == ~M_E~0); 10618#L769-2 assume !(0 == ~T1_E~0); 10619#L774-1 assume !(0 == ~T2_E~0); 10646#L779-1 assume !(0 == ~T3_E~0); 10759#L784-1 assume !(0 == ~T4_E~0); 10595#L789-1 assume !(0 == ~T5_E~0); 10596#L794-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 10699#L799-1 assume !(0 == ~T7_E~0); 10600#L804-1 assume !(0 == ~E_M~0); 10601#L809-1 assume !(0 == ~E_1~0); 10641#L814-1 assume !(0 == ~E_2~0); 10030#L819-1 assume !(0 == ~E_3~0); 10031#L824-1 assume !(0 == ~E_4~0); 10379#L829-1 assume !(0 == ~E_5~0); 10819#L834-1 assume 0 == ~E_6~0;~E_6~0 := 1; 10168#L839-1 assume !(0 == ~E_7~0); 10169#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10553#L376 assume !(1 == ~m_pc~0); 10542#L376-2 is_master_triggered_~__retres1~0#1 := 0; 10541#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10745#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 10106#L955 assume !(0 != activate_threads_~tmp~1#1); 10107#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10476#L395 assume 1 == ~t1_pc~0; 10142#L396 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 10143#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10060#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 10061#L963 assume !(0 != activate_threads_~tmp___0~0#1); 10557#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10558#L414 assume !(1 == ~t2_pc~0); 10171#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 10172#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10385#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 10386#L971 assume !(0 != activate_threads_~tmp___1~0#1); 10774#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10480#L433 assume 1 == ~t3_pc~0; 10422#L434 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 10278#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10028#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 10029#L979 assume !(0 != activate_threads_~tmp___2~0#1); 10131#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10132#L452 assume !(1 == ~t4_pc~0); 10285#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 10286#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10125#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 10126#L987 assume !(0 != activate_threads_~tmp___3~0#1); 10316#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10317#L471 assume 1 == ~t5_pc~0; 10685#L472 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 10300#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10301#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 10748#L995 assume !(0 != activate_threads_~tmp___4~0#1); 10810#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 10811#L490 assume 1 == ~t6_pc~0; 10795#L491 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 10556#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 10372#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 10373#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 10489#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 10458#L509 assume !(1 == ~t7_pc~0); 10459#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 10260#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 10261#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 10323#L1011 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 10324#L1011-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10780#L857 assume !(1 == ~M_E~0); 10113#L857-2 assume !(1 == ~T1_E~0); 10114#L862-1 assume !(1 == ~T2_E~0); 10389#L867-1 assume !(1 == ~T3_E~0); 10394#L872-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 10481#L877-1 assume !(1 == ~T5_E~0); 10663#L882-1 assume !(1 == ~T6_E~0); 10794#L887-1 assume !(1 == ~T7_E~0); 10715#L892-1 assume !(1 == ~E_M~0); 10716#L897-1 assume !(1 == ~E_1~0); 10410#L902-1 assume !(1 == ~E_2~0); 10411#L907-1 assume !(1 == ~E_3~0); 10677#L912-1 assume 1 == ~E_4~0;~E_4~0 := 2; 10669#L917-1 assume !(1 == ~E_5~0); 10670#L922-1 assume !(1 == ~E_6~0); 10821#L927-1 assume !(1 == ~E_7~0); 10658#L932-1 assume { :end_inline_reset_delta_events } true; 10063#L1178-2 [2022-12-13 12:19:16,863 INFO L750 eck$LassoCheckResult]: Loop: 10063#L1178-2 assume !false; 10647#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 10437#L744 assume !false; 10452#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 10521#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 10098#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 10303#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 10407#L641 assume !(0 != eval_~tmp~0#1); 10717#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 10528#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 10529#L769-3 assume 0 == ~M_E~0;~M_E~0 := 1; 10478#L769-5 assume !(0 == ~T1_E~0); 10479#L774-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 10217#L779-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 10041#L784-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 10042#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 10032#L794-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 10033#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 10080#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 10332#L809-3 assume !(0 == ~E_1~0); 10076#L814-3 assume 0 == ~E_2~0;~E_2~0 := 1; 10077#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 10736#L824-3 assume 0 == ~E_4~0;~E_4~0 := 1; 10731#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 10390#L834-3 assume 0 == ~E_6~0;~E_6~0 := 1; 10391#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 10698#L844-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10778#L376-27 assume 1 == ~m_pc~0; 10673#L377-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 10624#L387-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10625#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 10692#L955-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 10823#L955-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10844#L395-27 assume !(1 == ~t1_pc~0); 10497#L395-29 is_transmit1_triggered_~__retres1~1#1 := 0; 10392#L406-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10393#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 10588#L963-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 10484#L963-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10485#L414-27 assume 1 == ~t2_pc~0; 10807#L415-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 10668#L425-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10667#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 10544#L971-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 10088#L971-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10089#L433-27 assume !(1 == ~t3_pc~0); 10189#L433-29 is_transmit3_triggered_~__retres1~3#1 := 0; 10491#L444-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10492#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 10263#L979-27 assume !(0 != activate_threads_~tmp___2~0#1); 10264#L979-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10835#L452-27 assume 1 == ~t4_pc~0; 10836#L453-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 10639#L463-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10456#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 10457#L987-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 10804#L987-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10081#L471-27 assume !(1 == ~t5_pc~0); 10082#L471-29 is_transmit5_triggered_~__retres1~5#1 := 0; 10404#L482-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10756#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 10689#L995-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 10620#L995-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 10552#L490-27 assume 1 == ~t6_pc~0; 10453#L491-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 10274#L501-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 10275#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 10675#L1003-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 10676#L1003-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 10050#L509-27 assume !(1 == ~t7_pc~0); 10051#L509-29 is_transmit7_triggered_~__retres1~7#1 := 0; 10455#L520-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 10336#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 10337#L1011-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 10572#L1011-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10584#L857-3 assume 1 == ~M_E~0;~M_E~0 := 2; 10585#L857-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 10616#L862-3 assume !(1 == ~T2_E~0); 10834#L867-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 10493#L872-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 10494#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 10579#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 10610#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 10234#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 10235#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 10754#L902-3 assume !(1 == ~E_2~0); 10408#L907-3 assume 1 == ~E_3~0;~E_3~0 := 2; 10409#L912-3 assume 1 == ~E_4~0;~E_4~0 := 2; 10532#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 10498#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 10287#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 10288#L932-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 10140#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 10040#L626-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 10345#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 10346#L1197 assume !(0 == start_simulation_~tmp~3#1); 10467#L1197-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 10197#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 10166#L626-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 10058#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 10059#L1152 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 10751#L1159 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 10546#stop_simulation_returnLabel#1 start_simulation_#t~ret24#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 10062#L1210 assume !(0 != start_simulation_~tmp___0~1#1); 10063#L1178-2 [2022-12-13 12:19:16,864 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:19:16,864 INFO L85 PathProgramCache]: Analyzing trace with hash 1696948797, now seen corresponding path program 1 times [2022-12-13 12:19:16,864 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:19:16,864 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [862171465] [2022-12-13 12:19:16,864 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:19:16,864 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:19:16,870 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:19:16,885 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:19:16,885 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:19:16,885 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [862171465] [2022-12-13 12:19:16,885 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [862171465] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:19:16,886 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:19:16,886 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:19:16,886 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [915409035] [2022-12-13 12:19:16,886 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:19:16,886 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 12:19:16,886 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:19:16,887 INFO L85 PathProgramCache]: Analyzing trace with hash -1833724246, now seen corresponding path program 2 times [2022-12-13 12:19:16,887 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:19:16,887 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [673891008] [2022-12-13 12:19:16,887 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:19:16,887 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:19:16,897 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:19:16,917 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:19:16,917 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:19:16,917 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [673891008] [2022-12-13 12:19:16,917 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [673891008] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:19:16,917 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:19:16,917 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:19:16,918 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1012180179] [2022-12-13 12:19:16,918 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:19:16,918 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:19:16,918 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:19:16,918 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 12:19:16,919 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 12:19:16,919 INFO L87 Difference]: Start difference. First operand 830 states and 1235 transitions. cyclomatic complexity: 406 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:19:16,933 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:19:16,933 INFO L93 Difference]: Finished difference Result 830 states and 1234 transitions. [2022-12-13 12:19:16,933 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 830 states and 1234 transitions. [2022-12-13 12:19:16,936 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 727 [2022-12-13 12:19:16,938 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 830 states to 830 states and 1234 transitions. [2022-12-13 12:19:16,938 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 830 [2022-12-13 12:19:16,939 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 830 [2022-12-13 12:19:16,939 INFO L73 IsDeterministic]: Start isDeterministic. Operand 830 states and 1234 transitions. [2022-12-13 12:19:16,940 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:19:16,940 INFO L218 hiAutomatonCegarLoop]: Abstraction has 830 states and 1234 transitions. [2022-12-13 12:19:16,940 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 830 states and 1234 transitions. [2022-12-13 12:19:16,956 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 830 to 830. [2022-12-13 12:19:16,957 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 830 states, 830 states have (on average 1.4867469879518072) internal successors, (1234), 829 states have internal predecessors, (1234), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:19:16,958 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 830 states to 830 states and 1234 transitions. [2022-12-13 12:19:16,958 INFO L240 hiAutomatonCegarLoop]: Abstraction has 830 states and 1234 transitions. [2022-12-13 12:19:16,959 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 12:19:16,959 INFO L428 stractBuchiCegarLoop]: Abstraction has 830 states and 1234 transitions. [2022-12-13 12:19:16,959 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2022-12-13 12:19:16,959 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 830 states and 1234 transitions. [2022-12-13 12:19:16,963 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 727 [2022-12-13 12:19:16,963 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:19:16,963 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:19:16,964 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:19:16,964 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:19:16,965 INFO L748 eck$LassoCheckResult]: Stem: 11905#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 11906#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 12457#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 12458#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 12437#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 12438#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 12150#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 11972#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 11973#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 11956#L556-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 11957#L561-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 12436#L566-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 12264#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 12265#L769 assume !(0 == ~M_E~0); 12285#L769-2 assume !(0 == ~T1_E~0); 12286#L774-1 assume !(0 == ~T2_E~0); 12313#L779-1 assume !(0 == ~T3_E~0); 12426#L784-1 assume !(0 == ~T4_E~0); 12262#L789-1 assume !(0 == ~T5_E~0); 12263#L794-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 12366#L799-1 assume !(0 == ~T7_E~0); 12267#L804-1 assume !(0 == ~E_M~0); 12268#L809-1 assume !(0 == ~E_1~0); 12308#L814-1 assume !(0 == ~E_2~0); 11697#L819-1 assume !(0 == ~E_3~0); 11698#L824-1 assume !(0 == ~E_4~0); 12046#L829-1 assume !(0 == ~E_5~0); 12486#L834-1 assume 0 == ~E_6~0;~E_6~0 := 1; 11835#L839-1 assume !(0 == ~E_7~0); 11836#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12220#L376 assume !(1 == ~m_pc~0); 12209#L376-2 is_master_triggered_~__retres1~0#1 := 0; 12208#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12412#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 11773#L955 assume !(0 != activate_threads_~tmp~1#1); 11774#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12143#L395 assume 1 == ~t1_pc~0; 11809#L396 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 11810#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11727#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 11728#L963 assume !(0 != activate_threads_~tmp___0~0#1); 12224#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12225#L414 assume !(1 == ~t2_pc~0); 11838#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 11839#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12052#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 12053#L971 assume !(0 != activate_threads_~tmp___1~0#1); 12441#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12147#L433 assume 1 == ~t3_pc~0; 12089#L434 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 11945#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11695#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 11696#L979 assume !(0 != activate_threads_~tmp___2~0#1); 11798#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 11799#L452 assume !(1 == ~t4_pc~0); 11952#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 11953#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 11792#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 11793#L987 assume !(0 != activate_threads_~tmp___3~0#1); 11983#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 11984#L471 assume 1 == ~t5_pc~0; 12352#L472 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 11967#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 11968#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 12415#L995 assume !(0 != activate_threads_~tmp___4~0#1); 12477#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 12478#L490 assume 1 == ~t6_pc~0; 12462#L491 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 12223#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12039#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 12040#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 12156#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12125#L509 assume !(1 == ~t7_pc~0); 12126#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 11927#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 11928#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 11990#L1011 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 11991#L1011-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12447#L857 assume !(1 == ~M_E~0); 11780#L857-2 assume !(1 == ~T1_E~0); 11781#L862-1 assume !(1 == ~T2_E~0); 12056#L867-1 assume !(1 == ~T3_E~0); 12061#L872-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 12148#L877-1 assume !(1 == ~T5_E~0); 12330#L882-1 assume !(1 == ~T6_E~0); 12461#L887-1 assume !(1 == ~T7_E~0); 12382#L892-1 assume !(1 == ~E_M~0); 12383#L897-1 assume !(1 == ~E_1~0); 12077#L902-1 assume !(1 == ~E_2~0); 12078#L907-1 assume !(1 == ~E_3~0); 12344#L912-1 assume 1 == ~E_4~0;~E_4~0 := 2; 12336#L917-1 assume !(1 == ~E_5~0); 12337#L922-1 assume !(1 == ~E_6~0); 12488#L927-1 assume !(1 == ~E_7~0); 12325#L932-1 assume { :end_inline_reset_delta_events } true; 11730#L1178-2 [2022-12-13 12:19:16,965 INFO L750 eck$LassoCheckResult]: Loop: 11730#L1178-2 assume !false; 12314#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 12104#L744 assume !false; 12119#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 12188#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 11765#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 11970#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 12074#L641 assume !(0 != eval_~tmp~0#1); 12384#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 12195#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 12196#L769-3 assume 0 == ~M_E~0;~M_E~0 := 1; 12145#L769-5 assume !(0 == ~T1_E~0); 12146#L774-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 11884#L779-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 11708#L784-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 11709#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 11699#L794-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 11700#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 11747#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 11999#L809-3 assume !(0 == ~E_1~0); 11743#L814-3 assume 0 == ~E_2~0;~E_2~0 := 1; 11744#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 12403#L824-3 assume 0 == ~E_4~0;~E_4~0 := 1; 12398#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 12057#L834-3 assume 0 == ~E_6~0;~E_6~0 := 1; 12058#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 12365#L844-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12445#L376-27 assume 1 == ~m_pc~0; 12340#L377-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 12291#L387-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12292#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 12359#L955-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 12490#L955-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12511#L395-27 assume !(1 == ~t1_pc~0); 12164#L395-29 is_transmit1_triggered_~__retres1~1#1 := 0; 12059#L406-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12060#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 12255#L963-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 12151#L963-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12152#L414-27 assume 1 == ~t2_pc~0; 12474#L415-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 12335#L425-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12334#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 12211#L971-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 11755#L971-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11756#L433-27 assume !(1 == ~t3_pc~0); 11856#L433-29 is_transmit3_triggered_~__retres1~3#1 := 0; 12158#L444-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12159#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 11930#L979-27 assume !(0 != activate_threads_~tmp___2~0#1); 11931#L979-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12502#L452-27 assume !(1 == ~t4_pc~0); 12305#L452-29 is_transmit4_triggered_~__retres1~4#1 := 0; 12306#L463-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12123#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 12124#L987-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 12471#L987-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 11748#L471-27 assume !(1 == ~t5_pc~0); 11749#L471-29 is_transmit5_triggered_~__retres1~5#1 := 0; 12071#L482-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12423#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 12356#L995-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 12287#L995-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 12219#L490-27 assume 1 == ~t6_pc~0; 12120#L491-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 11941#L501-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11942#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 12342#L1003-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 12343#L1003-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 11717#L509-27 assume !(1 == ~t7_pc~0); 11718#L509-29 is_transmit7_triggered_~__retres1~7#1 := 0; 12122#L520-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 12003#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 12004#L1011-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 12239#L1011-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12251#L857-3 assume 1 == ~M_E~0;~M_E~0 := 2; 12252#L857-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 12283#L862-3 assume !(1 == ~T2_E~0); 12501#L867-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 12160#L872-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 12161#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 12246#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 12277#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 11901#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 11902#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 12421#L902-3 assume !(1 == ~E_2~0); 12075#L907-3 assume 1 == ~E_3~0;~E_3~0 := 2; 12076#L912-3 assume 1 == ~E_4~0;~E_4~0 := 2; 12199#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 12165#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 11954#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 11955#L932-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 11807#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 11707#L626-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 12012#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 12013#L1197 assume !(0 == start_simulation_~tmp~3#1); 12134#L1197-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 11864#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 11833#L626-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 11725#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 11726#L1152 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 12418#L1159 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 12213#stop_simulation_returnLabel#1 start_simulation_#t~ret24#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 11729#L1210 assume !(0 != start_simulation_~tmp___0~1#1); 11730#L1178-2 [2022-12-13 12:19:16,965 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:19:16,965 INFO L85 PathProgramCache]: Analyzing trace with hash -718887553, now seen corresponding path program 1 times [2022-12-13 12:19:16,965 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:19:16,966 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1338219979] [2022-12-13 12:19:16,966 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:19:16,966 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:19:16,975 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:19:17,011 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:19:17,012 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:19:17,012 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1338219979] [2022-12-13 12:19:17,012 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1338219979] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:19:17,012 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:19:17,012 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:19:17,012 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [531153368] [2022-12-13 12:19:17,012 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:19:17,013 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 12:19:17,013 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:19:17,013 INFO L85 PathProgramCache]: Analyzing trace with hash -2107502741, now seen corresponding path program 3 times [2022-12-13 12:19:17,013 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:19:17,013 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1171947800] [2022-12-13 12:19:17,013 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:19:17,013 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:19:17,020 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:19:17,040 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:19:17,041 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:19:17,041 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1171947800] [2022-12-13 12:19:17,041 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1171947800] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:19:17,041 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:19:17,041 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:19:17,041 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1930629873] [2022-12-13 12:19:17,041 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:19:17,042 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:19:17,042 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:19:17,042 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 12:19:17,042 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 12:19:17,042 INFO L87 Difference]: Start difference. First operand 830 states and 1234 transitions. cyclomatic complexity: 405 Second operand has 4 states, 4 states have (on average 23.75) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:19:17,125 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:19:17,125 INFO L93 Difference]: Finished difference Result 1499 states and 2220 transitions. [2022-12-13 12:19:17,125 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1499 states and 2220 transitions. [2022-12-13 12:19:17,131 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1380 [2022-12-13 12:19:17,135 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1499 states to 1499 states and 2220 transitions. [2022-12-13 12:19:17,135 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1499 [2022-12-13 12:19:17,136 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1499 [2022-12-13 12:19:17,136 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1499 states and 2220 transitions. [2022-12-13 12:19:17,137 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:19:17,138 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1499 states and 2220 transitions. [2022-12-13 12:19:17,139 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1499 states and 2220 transitions. [2022-12-13 12:19:17,154 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1499 to 1499. [2022-12-13 12:19:17,156 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1499 states, 1499 states have (on average 1.4809873248832555) internal successors, (2220), 1498 states have internal predecessors, (2220), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:19:17,159 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1499 states to 1499 states and 2220 transitions. [2022-12-13 12:19:17,159 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1499 states and 2220 transitions. [2022-12-13 12:19:17,160 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 12:19:17,160 INFO L428 stractBuchiCegarLoop]: Abstraction has 1499 states and 2220 transitions. [2022-12-13 12:19:17,160 INFO L335 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2022-12-13 12:19:17,161 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1499 states and 2220 transitions. [2022-12-13 12:19:17,168 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1380 [2022-12-13 12:19:17,168 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:19:17,168 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:19:17,169 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:19:17,169 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:19:17,170 INFO L748 eck$LassoCheckResult]: Stem: 14244#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 14245#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 14823#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 14824#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 14802#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 14803#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 14495#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 14314#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 14315#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 14296#L556-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 14297#L561-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 14801#L566-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 14614#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 14615#L769 assume !(0 == ~M_E~0); 14635#L769-2 assume !(0 == ~T1_E~0); 14636#L774-1 assume !(0 == ~T2_E~0); 14664#L779-1 assume !(0 == ~T3_E~0); 14787#L784-1 assume !(0 == ~T4_E~0); 14612#L789-1 assume !(0 == ~T5_E~0); 14613#L794-1 assume !(0 == ~T6_E~0); 14721#L799-1 assume !(0 == ~T7_E~0); 14617#L804-1 assume !(0 == ~E_M~0); 14618#L809-1 assume !(0 == ~E_1~0); 14659#L814-1 assume !(0 == ~E_2~0); 14036#L819-1 assume !(0 == ~E_3~0); 14037#L824-1 assume !(0 == ~E_4~0); 14390#L829-1 assume !(0 == ~E_5~0); 14856#L834-1 assume 0 == ~E_6~0;~E_6~0 := 1; 14174#L839-1 assume !(0 == ~E_7~0); 14175#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 14566#L376 assume !(1 == ~m_pc~0); 14555#L376-2 is_master_triggered_~__retres1~0#1 := 0; 14554#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 14770#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 14112#L955 assume !(0 != activate_threads_~tmp~1#1); 14113#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14488#L395 assume 1 == ~t1_pc~0; 14148#L396 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 14149#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14066#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 14067#L963 assume !(0 != activate_threads_~tmp___0~0#1); 14570#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14571#L414 assume !(1 == ~t2_pc~0); 14177#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 14178#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14396#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 14397#L971 assume !(0 != activate_threads_~tmp___1~0#1); 14806#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14492#L433 assume 1 == ~t3_pc~0; 14433#L434 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 14285#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14034#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 14035#L979 assume !(0 != activate_threads_~tmp___2~0#1); 14137#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 14138#L452 assume !(1 == ~t4_pc~0); 14292#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 14293#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 14131#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 14132#L987 assume !(0 != activate_threads_~tmp___3~0#1); 14325#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14326#L471 assume 1 == ~t5_pc~0; 14706#L472 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 14307#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 14308#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 14774#L995 assume !(0 != activate_threads_~tmp___4~0#1); 14846#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14847#L490 assume 1 == ~t6_pc~0; 14829#L491 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 14569#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 14383#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 14384#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 14501#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 14470#L509 assume !(1 == ~t7_pc~0); 14471#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 14267#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 14268#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 14332#L1011 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 14333#L1011-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14812#L857 assume 1 == ~M_E~0;~M_E~0 := 2; 14813#L857-2 assume !(1 == ~T1_E~0); 15078#L862-1 assume !(1 == ~T2_E~0); 15077#L867-1 assume !(1 == ~T3_E~0); 15076#L872-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 15075#L877-1 assume !(1 == ~T5_E~0); 15073#L882-1 assume !(1 == ~T6_E~0); 14827#L887-1 assume !(1 == ~T7_E~0); 15072#L892-1 assume !(1 == ~E_M~0); 15070#L897-1 assume !(1 == ~E_1~0); 15069#L902-1 assume !(1 == ~E_2~0); 15068#L907-1 assume !(1 == ~E_3~0); 15067#L912-1 assume 1 == ~E_4~0;~E_4~0 := 2; 15066#L917-1 assume !(1 == ~E_5~0); 15065#L922-1 assume !(1 == ~E_6~0); 14912#L927-1 assume !(1 == ~E_7~0); 14679#L932-1 assume { :end_inline_reset_delta_events } true; 14069#L1178-2 [2022-12-13 12:19:17,170 INFO L750 eck$LassoCheckResult]: Loop: 14069#L1178-2 assume !false; 14665#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 14448#L744 assume !false; 14463#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 14534#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 14104#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 14889#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 14791#L641 assume !(0 != eval_~tmp~0#1); 14793#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 14541#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 14542#L769-3 assume 0 == ~M_E~0;~M_E~0 := 1; 14888#L769-5 assume !(0 == ~T1_E~0); 15463#L774-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 15462#L779-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 15461#L784-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 15460#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 15459#L794-3 assume !(0 == ~T6_E~0); 15458#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 15457#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 15456#L809-3 assume !(0 == ~E_1~0); 15455#L814-3 assume 0 == ~E_2~0;~E_2~0 := 1; 15454#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 15453#L824-3 assume 0 == ~E_4~0;~E_4~0 := 1; 15452#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 15451#L834-3 assume 0 == ~E_6~0;~E_6~0 := 1; 15450#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 15449#L844-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 15448#L376-27 assume !(1 == ~m_pc~0); 15446#L376-29 is_master_triggered_~__retres1~0#1 := 0; 15445#L387-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 15444#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 15443#L955-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 15442#L955-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 15441#L395-27 assume !(1 == ~t1_pc~0); 15440#L395-29 is_transmit1_triggered_~__retres1~1#1 := 0; 15438#L406-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 15437#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 15436#L963-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 15435#L963-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15434#L414-27 assume !(1 == ~t2_pc~0); 15432#L414-29 is_transmit2_triggered_~__retres1~2#1 := 0; 15431#L425-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 15430#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 15429#L971-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 15428#L971-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 15427#L433-27 assume 1 == ~t3_pc~0; 15425#L434-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 15424#L444-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 15423#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 15422#L979-27 assume !(0 != activate_threads_~tmp___2~0#1); 15421#L979-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 15420#L452-27 assume 1 == ~t4_pc~0; 15418#L453-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 15417#L463-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 15416#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 15415#L987-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 15414#L987-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 15413#L471-27 assume 1 == ~t5_pc~0; 15411#L472-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 15410#L482-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 15409#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 15408#L995-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 15407#L995-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 15406#L490-27 assume 1 == ~t6_pc~0; 15404#L491-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 15403#L501-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 15402#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 15401#L1003-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 15400#L1003-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 15399#L509-27 assume !(1 == ~t7_pc~0); 15397#L509-29 is_transmit7_triggered_~__retres1~7#1 := 0; 15396#L520-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 15395#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 15394#L1011-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 15357#L1011-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 15356#L857-3 assume 1 == ~M_E~0;~M_E~0 := 2; 14599#L857-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 15355#L862-3 assume !(1 == ~T2_E~0); 15354#L867-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 15353#L872-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 15352#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 15351#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 14877#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 15350#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 15349#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 15348#L902-3 assume !(1 == ~E_2~0); 15347#L907-3 assume 1 == ~E_3~0;~E_3~0 := 2; 15346#L912-3 assume 1 == ~E_4~0;~E_4~0 := 2; 15345#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 15344#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 15343#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 15342#L932-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 15338#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 15333#L626-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 15332#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 15331#L1197 assume !(0 == start_simulation_~tmp~3#1); 14880#L1197-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 14923#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 14917#L626-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 14916#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 14915#L1152 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 14914#L1159 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 14559#stop_simulation_returnLabel#1 start_simulation_#t~ret24#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 14068#L1210 assume !(0 != start_simulation_~tmp___0~1#1); 14069#L1178-2 [2022-12-13 12:19:17,170 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:19:17,170 INFO L85 PathProgramCache]: Analyzing trace with hash -1207876549, now seen corresponding path program 1 times [2022-12-13 12:19:17,170 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:19:17,171 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1436769292] [2022-12-13 12:19:17,171 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:19:17,171 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:19:17,177 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:19:17,207 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:19:17,208 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:19:17,208 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1436769292] [2022-12-13 12:19:17,208 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1436769292] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:19:17,208 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:19:17,208 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:19:17,208 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1882480570] [2022-12-13 12:19:17,208 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:19:17,209 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 12:19:17,209 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:19:17,209 INFO L85 PathProgramCache]: Analyzing trace with hash -1368315928, now seen corresponding path program 1 times [2022-12-13 12:19:17,209 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:19:17,209 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1910741992] [2022-12-13 12:19:17,209 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:19:17,210 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:19:17,216 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:19:17,243 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:19:17,244 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:19:17,244 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1910741992] [2022-12-13 12:19:17,244 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1910741992] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:19:17,244 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:19:17,244 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:19:17,244 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [252076887] [2022-12-13 12:19:17,244 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:19:17,245 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:19:17,245 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:19:17,245 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 12:19:17,245 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 12:19:17,245 INFO L87 Difference]: Start difference. First operand 1499 states and 2220 transitions. cyclomatic complexity: 723 Second operand has 4 states, 4 states have (on average 23.75) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:19:17,344 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:19:17,344 INFO L93 Difference]: Finished difference Result 2703 states and 3991 transitions. [2022-12-13 12:19:17,344 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2703 states and 3991 transitions. [2022-12-13 12:19:17,359 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2570 [2022-12-13 12:19:17,366 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2703 states to 2703 states and 3991 transitions. [2022-12-13 12:19:17,366 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2703 [2022-12-13 12:19:17,368 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2703 [2022-12-13 12:19:17,368 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2703 states and 3991 transitions. [2022-12-13 12:19:17,370 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:19:17,370 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2703 states and 3991 transitions. [2022-12-13 12:19:17,373 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2703 states and 3991 transitions. [2022-12-13 12:19:17,401 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2703 to 2701. [2022-12-13 12:19:17,404 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2701 states, 2701 states have (on average 1.4768604220659016) internal successors, (3989), 2700 states have internal predecessors, (3989), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:19:17,409 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2701 states to 2701 states and 3989 transitions. [2022-12-13 12:19:17,409 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2701 states and 3989 transitions. [2022-12-13 12:19:17,409 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 12:19:17,410 INFO L428 stractBuchiCegarLoop]: Abstraction has 2701 states and 3989 transitions. [2022-12-13 12:19:17,410 INFO L335 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2022-12-13 12:19:17,410 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2701 states and 3989 transitions. [2022-12-13 12:19:17,417 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2570 [2022-12-13 12:19:17,418 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:19:17,418 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:19:17,418 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:19:17,419 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:19:17,419 INFO L748 eck$LassoCheckResult]: Stem: 18458#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 18459#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 19039#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 19040#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 19013#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 19014#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 18706#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 18524#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 18525#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 18508#L556-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 18509#L561-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 19012#L566-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 18825#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 18826#L769 assume !(0 == ~M_E~0); 18847#L769-2 assume !(0 == ~T1_E~0); 18848#L774-1 assume !(0 == ~T2_E~0); 18877#L779-1 assume !(0 == ~T3_E~0); 19000#L784-1 assume !(0 == ~T4_E~0); 18823#L789-1 assume !(0 == ~T5_E~0); 18824#L794-1 assume !(0 == ~T6_E~0); 18935#L799-1 assume !(0 == ~T7_E~0); 18828#L804-1 assume !(0 == ~E_M~0); 18829#L809-1 assume !(0 == ~E_1~0); 18871#L814-1 assume !(0 == ~E_2~0); 18250#L819-1 assume !(0 == ~E_3~0); 18251#L824-1 assume !(0 == ~E_4~0); 18601#L829-1 assume !(0 == ~E_5~0); 19076#L834-1 assume !(0 == ~E_6~0); 18386#L839-1 assume !(0 == ~E_7~0); 18387#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 18779#L376 assume !(1 == ~m_pc~0); 18771#L376-2 is_master_triggered_~__retres1~0#1 := 0; 18770#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 18985#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 18326#L955 assume !(0 != activate_threads_~tmp~1#1); 18327#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 18699#L395 assume 1 == ~t1_pc~0; 18360#L396 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 18361#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 18278#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 18279#L963 assume !(0 != activate_threads_~tmp___0~0#1); 18784#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 18785#L414 assume !(1 == ~t2_pc~0); 18389#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 18390#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 18607#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 18608#L971 assume !(0 != activate_threads_~tmp___1~0#1); 19018#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 18703#L433 assume 1 == ~t3_pc~0; 18644#L434 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 18499#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 18246#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 18247#L979 assume !(0 != activate_threads_~tmp___2~0#1); 18349#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 18350#L452 assume !(1 == ~t4_pc~0); 18504#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 18505#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 18343#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 18344#L987 assume !(0 != activate_threads_~tmp___3~0#1); 18535#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 18536#L471 assume 1 == ~t5_pc~0; 18920#L472 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 18519#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 18520#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 18989#L995 assume !(0 != activate_threads_~tmp___4~0#1); 19067#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 19068#L490 assume 1 == ~t6_pc~0; 19046#L491 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 18782#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 18594#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 18595#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 18714#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 18681#L509 assume !(1 == ~t7_pc~0); 18682#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 18484#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 18485#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 18542#L1011 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 18543#L1011-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19025#L857 assume 1 == ~M_E~0;~M_E~0 := 2; 19026#L857-2 assume !(1 == ~T1_E~0); 19253#L862-1 assume !(1 == ~T2_E~0); 19252#L867-1 assume !(1 == ~T3_E~0); 19251#L872-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 19250#L877-1 assume !(1 == ~T5_E~0); 19043#L882-1 assume !(1 == ~T6_E~0); 19044#L887-1 assume !(1 == ~T7_E~0); 19098#L892-1 assume !(1 == ~E_M~0); 19205#L897-1 assume !(1 == ~E_1~0); 19187#L902-1 assume !(1 == ~E_2~0); 19185#L907-1 assume !(1 == ~E_3~0); 19183#L912-1 assume 1 == ~E_4~0;~E_4~0 := 2; 18903#L917-1 assume !(1 == ~E_5~0); 18904#L922-1 assume !(1 == ~E_6~0); 19156#L927-1 assume !(1 == ~E_7~0); 19148#L932-1 assume { :end_inline_reset_delta_events } true; 19142#L1178-2 [2022-12-13 12:19:17,419 INFO L750 eck$LassoCheckResult]: Loop: 19142#L1178-2 assume !false; 19137#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 19136#L744 assume !false; 19135#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 19134#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 19126#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 19125#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 19123#L641 assume !(0 != eval_~tmp~0#1); 19122#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 19121#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 19119#L769-3 assume 0 == ~M_E~0;~M_E~0 := 1; 19120#L769-5 assume !(0 == ~T1_E~0); 19960#L774-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 19873#L779-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 19869#L784-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 19867#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 19854#L794-3 assume !(0 == ~T6_E~0); 19841#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 18552#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 18553#L809-3 assume !(0 == ~E_1~0); 18296#L814-3 assume 0 == ~E_2~0;~E_2~0 := 1; 18297#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 18976#L824-3 assume 0 == ~E_4~0;~E_4~0 := 1; 18969#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 18614#L834-3 assume !(0 == ~E_6~0); 18615#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 18934#L844-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 19023#L376-27 assume 1 == ~m_pc~0; 18907#L377-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 18853#L387-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 18854#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 18927#L955-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 19082#L955-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 19114#L395-27 assume !(1 == ~t1_pc~0); 18720#L395-29 is_transmit1_triggered_~__retres1~1#1 := 0; 18612#L406-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 18613#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 18816#L963-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 18707#L963-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 18708#L414-27 assume 1 == ~t2_pc~0; 19064#L415-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 18902#L425-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 18901#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 18766#L971-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 18306#L971-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 18307#L433-27 assume !(1 == ~t3_pc~0); 18407#L433-29 is_transmit3_triggered_~__retres1~3#1 := 0; 18712#L444-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 18713#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 18480#L979-27 assume !(0 != activate_threads_~tmp___2~0#1); 18481#L979-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19099#L452-27 assume 1 == ~t4_pc~0; 19100#L453-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 19607#L463-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 19605#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 19603#L987-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 19601#L987-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 19600#L471-27 assume 1 == ~t5_pc~0; 19579#L472-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 19563#L482-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 19561#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 19560#L995-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 19558#L995-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 19556#L490-27 assume 1 == ~t6_pc~0; 19538#L491-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 19536#L501-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 19534#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 19532#L1003-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 19529#L1003-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 19527#L509-27 assume !(1 == ~t7_pc~0); 19524#L509-29 is_transmit7_triggered_~__retres1~7#1 := 0; 19522#L520-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 19520#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 19498#L1011-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 19495#L1011-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19474#L857-3 assume 1 == ~M_E~0;~M_E~0 := 2; 18811#L857-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 19433#L862-3 assume !(1 == ~T2_E~0); 19431#L867-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 19428#L872-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 19394#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 19392#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 19366#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 19364#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 19347#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 19327#L902-3 assume !(1 == ~E_2~0); 19325#L907-3 assume 1 == ~E_3~0;~E_3~0 := 2; 19323#L912-3 assume 1 == ~E_4~0;~E_4~0 := 2; 19321#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 19319#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 19297#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 19294#L932-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 19261#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 19256#L626-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 19255#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 19254#L1197 assume !(0 == start_simulation_~tmp~3#1); 19109#L1197-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 19210#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 19204#L626-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 19184#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 19182#L1152 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 19169#L1159 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 19157#stop_simulation_returnLabel#1 start_simulation_#t~ret24#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 19149#L1210 assume !(0 != start_simulation_~tmp___0~1#1); 19142#L1178-2 [2022-12-13 12:19:17,419 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:19:17,419 INFO L85 PathProgramCache]: Analyzing trace with hash -253936391, now seen corresponding path program 1 times [2022-12-13 12:19:17,419 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:19:17,419 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1850945411] [2022-12-13 12:19:17,420 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:19:17,420 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:19:17,426 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:19:17,457 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:19:17,457 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:19:17,457 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1850945411] [2022-12-13 12:19:17,458 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1850945411] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:19:17,458 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:19:17,458 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:19:17,458 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1282627158] [2022-12-13 12:19:17,458 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:19:17,458 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 12:19:17,459 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:19:17,459 INFO L85 PathProgramCache]: Analyzing trace with hash -2077478235, now seen corresponding path program 1 times [2022-12-13 12:19:17,459 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:19:17,459 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [46278849] [2022-12-13 12:19:17,459 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:19:17,459 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:19:17,471 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:19:17,500 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:19:17,501 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:19:17,501 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [46278849] [2022-12-13 12:19:17,501 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [46278849] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:19:17,501 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:19:17,501 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:19:17,501 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [653212783] [2022-12-13 12:19:17,501 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:19:17,501 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:19:17,502 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:19:17,502 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 12:19:17,502 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 12:19:17,502 INFO L87 Difference]: Start difference. First operand 2701 states and 3989 transitions. cyclomatic complexity: 1292 Second operand has 4 states, 4 states have (on average 23.75) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:19:17,722 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:19:17,722 INFO L93 Difference]: Finished difference Result 7458 states and 10846 transitions. [2022-12-13 12:19:17,722 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7458 states and 10846 transitions. [2022-12-13 12:19:17,744 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 7077 [2022-12-13 12:19:17,764 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7458 states to 7458 states and 10846 transitions. [2022-12-13 12:19:17,764 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7458 [2022-12-13 12:19:17,768 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7458 [2022-12-13 12:19:17,768 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7458 states and 10846 transitions. [2022-12-13 12:19:17,774 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:19:17,774 INFO L218 hiAutomatonCegarLoop]: Abstraction has 7458 states and 10846 transitions. [2022-12-13 12:19:17,779 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7458 states and 10846 transitions. [2022-12-13 12:19:17,848 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7458 to 7026. [2022-12-13 12:19:17,856 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7026 states, 7026 states have (on average 1.4594363791631084) internal successors, (10254), 7025 states have internal predecessors, (10254), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:19:17,867 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7026 states to 7026 states and 10254 transitions. [2022-12-13 12:19:17,867 INFO L240 hiAutomatonCegarLoop]: Abstraction has 7026 states and 10254 transitions. [2022-12-13 12:19:17,867 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 12:19:17,868 INFO L428 stractBuchiCegarLoop]: Abstraction has 7026 states and 10254 transitions. [2022-12-13 12:19:17,868 INFO L335 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2022-12-13 12:19:17,868 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7026 states and 10254 transitions. [2022-12-13 12:19:17,887 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 6877 [2022-12-13 12:19:17,887 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:19:17,887 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:19:17,888 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:19:17,888 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:19:17,888 INFO L748 eck$LassoCheckResult]: Stem: 28622#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 28623#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 29259#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 29260#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 29230#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 29231#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 28876#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 28692#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 28693#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 28675#L556-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 28676#L561-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 29227#L566-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 29005#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 29006#L769 assume !(0 == ~M_E~0); 29031#L769-2 assume !(0 == ~T1_E~0); 29032#L774-1 assume !(0 == ~T2_E~0); 29064#L779-1 assume !(0 == ~T3_E~0); 29208#L784-1 assume !(0 == ~T4_E~0); 29003#L789-1 assume !(0 == ~T5_E~0); 29004#L794-1 assume !(0 == ~T6_E~0); 29128#L799-1 assume !(0 == ~T7_E~0); 29009#L804-1 assume !(0 == ~E_M~0); 29010#L809-1 assume !(0 == ~E_1~0); 29055#L814-1 assume !(0 == ~E_2~0); 28417#L819-1 assume !(0 == ~E_3~0); 28418#L824-1 assume !(0 == ~E_4~0); 28767#L829-1 assume !(0 == ~E_5~0); 29308#L834-1 assume !(0 == ~E_6~0); 28551#L839-1 assume !(0 == ~E_7~0); 28552#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 28956#L376 assume !(1 == ~m_pc~0); 28953#L376-2 is_master_triggered_~__retres1~0#1 := 0; 28954#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 29188#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 28490#L955 assume !(0 != activate_threads_~tmp~1#1); 28491#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 28869#L395 assume !(1 == ~t1_pc~0); 29033#L395-2 is_transmit1_triggered_~__retres1~1#1 := 0; 29189#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 28446#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 28447#L963 assume !(0 != activate_threads_~tmp___0~0#1); 28960#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 28961#L414 assume !(1 == ~t2_pc~0); 28554#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 28555#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 28776#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 28777#L971 assume !(0 != activate_threads_~tmp___1~0#1); 29235#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 28873#L433 assume 1 == ~t3_pc~0; 28814#L434 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 28664#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 28415#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 28416#L979 assume !(0 != activate_threads_~tmp___2~0#1); 28516#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 28517#L452 assume !(1 == ~t4_pc~0); 28671#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 28672#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 28510#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 28511#L987 assume !(0 != activate_threads_~tmp___3~0#1); 28703#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 28704#L471 assume 1 == ~t5_pc~0; 29111#L472 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 28686#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 28687#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 29192#L995 assume !(0 != activate_threads_~tmp___4~0#1); 29297#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 29298#L490 assume 1 == ~t6_pc~0; 29267#L491 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 28959#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 28761#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 28762#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 28882#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 28851#L509 assume !(1 == ~t7_pc~0); 28852#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 28643#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 28644#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 28710#L1011 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 28711#L1011-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 29245#L857 assume 1 == ~M_E~0;~M_E~0 := 2; 28497#L857-2 assume !(1 == ~T1_E~0); 28498#L862-1 assume !(1 == ~T2_E~0); 28780#L867-1 assume !(1 == ~T3_E~0); 28785#L872-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 28874#L877-1 assume !(1 == ~T5_E~0); 29084#L882-1 assume !(1 == ~T6_E~0); 29266#L887-1 assume !(1 == ~T7_E~0); 29147#L892-1 assume !(1 == ~E_M~0); 29148#L897-1 assume !(1 == ~E_1~0); 32604#L902-1 assume !(1 == ~E_2~0); 32602#L907-1 assume !(1 == ~E_3~0); 32601#L912-1 assume 1 == ~E_4~0;~E_4~0 := 2; 32600#L917-1 assume !(1 == ~E_5~0); 32599#L922-1 assume !(1 == ~E_6~0); 29313#L927-1 assume !(1 == ~E_7~0); 32239#L932-1 assume { :end_inline_reset_delta_events } true; 32127#L1178-2 [2022-12-13 12:19:17,889 INFO L750 eck$LassoCheckResult]: Loop: 32127#L1178-2 assume !false; 32069#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 32067#L744 assume !false; 32049#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 32025#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 32017#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 32016#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 31951#L641 assume !(0 != eval_~tmp~0#1); 29149#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 28927#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 28928#L769-3 assume 0 == ~M_E~0;~M_E~0 := 1; 28871#L769-5 assume !(0 == ~T1_E~0); 28872#L774-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 28600#L779-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 28428#L784-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 28429#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 28419#L794-3 assume !(0 == ~T6_E~0); 28420#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 28465#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 28720#L809-3 assume !(0 == ~E_1~0); 28461#L814-3 assume 0 == ~E_2~0;~E_2~0 := 1; 28462#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 29174#L824-3 assume 0 == ~E_4~0;~E_4~0 := 1; 29168#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 28781#L834-3 assume !(0 == ~E_6~0); 28782#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 29127#L844-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 29243#L376-27 assume !(1 == ~m_pc~0); 29337#L376-29 is_master_triggered_~__retres1~0#1 := 0; 35088#L387-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 35087#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 35086#L955-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 35085#L955-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 35084#L395-27 assume !(1 == ~t1_pc~0); 35083#L395-29 is_transmit1_triggered_~__retres1~1#1 := 0; 35082#L406-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 35081#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 35080#L963-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 28877#L963-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 28878#L414-27 assume 1 == ~t2_pc~0; 29289#L415-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 29090#L425-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 29091#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 35066#L971-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 35063#L971-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 35061#L433-27 assume !(1 == ~t3_pc~0); 28946#L433-29 is_transmit3_triggered_~__retres1~3#1 := 0; 28947#L444-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 35051#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 35050#L979-27 assume !(0 != activate_threads_~tmp___2~0#1); 29345#L979-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 29346#L452-27 assume 1 == ~t4_pc~0; 35048#L453-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 35030#L463-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 35029#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 29284#L987-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 29285#L987-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 35020#L471-27 assume 1 == ~t5_pc~0; 35018#L472-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 35017#L482-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 35009#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 34828#L995-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 34827#L995-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 34826#L490-27 assume 1 == ~t6_pc~0; 34824#L491-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 34823#L501-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 34822#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 34821#L1003-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 34820#L1003-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 34819#L509-27 assume !(1 == ~t7_pc~0); 34817#L509-29 is_transmit7_triggered_~__retres1~7#1 := 0; 34816#L520-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 34815#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 34814#L1011-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 34813#L1011-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 28987#L857-3 assume 1 == ~M_E~0;~M_E~0 := 2; 28988#L857-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 29028#L862-3 assume !(1 == ~T2_E~0); 29338#L867-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 28887#L872-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 28888#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 28982#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 29356#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 34605#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 34599#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 34592#L902-3 assume !(1 == ~E_2~0); 34585#L907-3 assume 1 == ~E_3~0;~E_3~0 := 2; 34580#L912-3 assume 1 == ~E_4~0;~E_4~0 := 2; 34574#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 33904#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 33900#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 32598#L932-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 32389#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 32383#L626-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 32382#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 32381#L1197 assume !(0 == start_simulation_~tmp~3#1); 29359#L1197-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 32257#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 32251#L626-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 32249#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 32246#L1152 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 32244#L1159 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 32242#stop_simulation_returnLabel#1 start_simulation_#t~ret24#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 32240#L1210 assume !(0 != start_simulation_~tmp___0~1#1); 32127#L1178-2 [2022-12-13 12:19:17,889 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:19:17,889 INFO L85 PathProgramCache]: Analyzing trace with hash -1285267206, now seen corresponding path program 1 times [2022-12-13 12:19:17,889 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:19:17,889 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1823999270] [2022-12-13 12:19:17,889 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:19:17,889 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:19:17,906 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:19:17,946 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:19:17,946 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:19:17,946 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1823999270] [2022-12-13 12:19:17,946 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1823999270] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:19:17,946 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:19:17,946 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:19:17,946 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1913191444] [2022-12-13 12:19:17,946 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:19:17,947 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 12:19:17,947 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:19:17,947 INFO L85 PathProgramCache]: Analyzing trace with hash 375175270, now seen corresponding path program 1 times [2022-12-13 12:19:17,947 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:19:17,947 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [581278614] [2022-12-13 12:19:17,947 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:19:17,947 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:19:17,956 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:19:17,981 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:19:17,981 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:19:17,981 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [581278614] [2022-12-13 12:19:17,981 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [581278614] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:19:17,982 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:19:17,982 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:19:17,982 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [516976860] [2022-12-13 12:19:17,982 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:19:17,982 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:19:17,982 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:19:17,983 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 12:19:17,983 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 12:19:17,983 INFO L87 Difference]: Start difference. First operand 7026 states and 10254 transitions. cyclomatic complexity: 3236 Second operand has 4 states, 4 states have (on average 23.75) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:19:18,211 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:19:18,211 INFO L93 Difference]: Finished difference Result 19599 states and 28287 transitions. [2022-12-13 12:19:18,211 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 19599 states and 28287 transitions. [2022-12-13 12:19:18,271 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 18895 [2022-12-13 12:19:18,352 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 19599 states to 19599 states and 28287 transitions. [2022-12-13 12:19:18,353 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 19599 [2022-12-13 12:19:18,361 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 19599 [2022-12-13 12:19:18,362 INFO L73 IsDeterministic]: Start isDeterministic. Operand 19599 states and 28287 transitions. [2022-12-13 12:19:18,377 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:19:18,377 INFO L218 hiAutomatonCegarLoop]: Abstraction has 19599 states and 28287 transitions. [2022-12-13 12:19:18,389 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 19599 states and 28287 transitions. [2022-12-13 12:19:18,580 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 19599 to 18651. [2022-12-13 12:19:18,602 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 18651 states, 18651 states have (on average 1.4482333386949762) internal successors, (27011), 18650 states have internal predecessors, (27011), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:19:18,633 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 18651 states to 18651 states and 27011 transitions. [2022-12-13 12:19:18,633 INFO L240 hiAutomatonCegarLoop]: Abstraction has 18651 states and 27011 transitions. [2022-12-13 12:19:18,633 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 12:19:18,634 INFO L428 stractBuchiCegarLoop]: Abstraction has 18651 states and 27011 transitions. [2022-12-13 12:19:18,634 INFO L335 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2022-12-13 12:19:18,634 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 18651 states and 27011 transitions. [2022-12-13 12:19:18,700 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 18463 [2022-12-13 12:19:18,700 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:19:18,700 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:19:18,701 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:19:18,701 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:19:18,701 INFO L748 eck$LassoCheckResult]: Stem: 55260#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 55261#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 55926#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 55927#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 55896#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 55897#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 55526#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 55329#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 55330#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 55312#L556-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 55313#L561-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 55893#L566-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 55669#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 55670#L769 assume !(0 == ~M_E~0); 55691#L769-2 assume !(0 == ~T1_E~0); 55692#L774-1 assume !(0 == ~T2_E~0); 55723#L779-1 assume !(0 == ~T3_E~0); 55877#L784-1 assume !(0 == ~T4_E~0); 55667#L789-1 assume !(0 == ~T5_E~0); 55668#L794-1 assume !(0 == ~T6_E~0); 55798#L799-1 assume !(0 == ~T7_E~0); 55672#L804-1 assume !(0 == ~E_M~0); 55673#L809-1 assume !(0 == ~E_1~0); 55714#L814-1 assume !(0 == ~E_2~0); 55052#L819-1 assume !(0 == ~E_3~0); 55053#L824-1 assume !(0 == ~E_4~0); 55412#L829-1 assume !(0 == ~E_5~0); 55978#L834-1 assume !(0 == ~E_6~0); 55187#L839-1 assume !(0 == ~E_7~0); 55188#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 55611#L376 assume !(1 == ~m_pc~0); 55608#L376-2 is_master_triggered_~__retres1~0#1 := 0; 55609#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 55859#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 55126#L955 assume !(0 != activate_threads_~tmp~1#1); 55127#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 55518#L395 assume !(1 == ~t1_pc~0); 55693#L395-2 is_transmit1_triggered_~__retres1~1#1 := 0; 55860#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 55082#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 55083#L963 assume !(0 != activate_threads_~tmp___0~0#1); 55616#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 55617#L414 assume !(1 == ~t2_pc~0); 55190#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 55191#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 55419#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 55420#L971 assume !(0 != activate_threads_~tmp___1~0#1); 55903#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 55522#L433 assume !(1 == ~t3_pc~0); 55300#L433-2 is_transmit3_triggered_~__retres1~3#1 := 0; 55301#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 55050#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 55051#L979 assume !(0 != activate_threads_~tmp___2~0#1); 55151#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 55152#L452 assume !(1 == ~t4_pc~0); 55308#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 55309#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 55145#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 55146#L987 assume !(0 != activate_threads_~tmp___3~0#1); 55340#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 55341#L471 assume 1 == ~t5_pc~0; 55776#L472 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 55323#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 55324#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 55864#L995 assume !(0 != activate_threads_~tmp___4~0#1); 55966#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 55967#L490 assume 1 == ~t6_pc~0; 55934#L491 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 55615#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 55406#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 55407#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 55534#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 55499#L509 assume !(1 == ~t7_pc~0); 55500#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 55281#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 55282#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 55347#L1011 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 55348#L1011-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 55912#L857 assume 1 == ~M_E~0;~M_E~0 := 2; 55913#L857-2 assume !(1 == ~T1_E~0); 55423#L862-1 assume !(1 == ~T2_E~0); 55424#L867-1 assume !(1 == ~T3_E~0); 55523#L872-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 55524#L877-1 assume !(1 == ~T5_E~0); 55932#L882-1 assume !(1 == ~T6_E~0); 55933#L887-1 assume !(1 == ~T7_E~0); 56015#L892-1 assume !(1 == ~E_M~0); 55999#L897-1 assume !(1 == ~E_1~0); 56000#L902-1 assume !(1 == ~E_2~0); 55833#L907-1 assume !(1 == ~E_3~0); 55834#L912-1 assume 1 == ~E_4~0;~E_4~0 := 2; 55752#L917-1 assume !(1 == ~E_5~0); 55753#L922-1 assume !(1 == ~E_6~0); 58427#L927-1 assume !(1 == ~E_7~0); 59330#L932-1 assume { :end_inline_reset_delta_events } true; 59331#L1178-2 [2022-12-13 12:19:18,701 INFO L750 eck$LassoCheckResult]: Loop: 59331#L1178-2 assume !false; 59290#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 59291#L744 assume !false; 59270#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 59271#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 73057#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 73056#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 57989#L641 assume !(0 != eval_~tmp~0#1); 57991#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 60983#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 60984#L769-3 assume 0 == ~M_E~0;~M_E~0 := 1; 60967#L769-5 assume !(0 == ~T1_E~0); 60968#L774-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 60952#L779-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 60953#L784-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 60936#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 60937#L794-3 assume !(0 == ~T6_E~0); 60921#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 60922#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 60906#L809-3 assume !(0 == ~E_1~0); 60907#L814-3 assume 0 == ~E_2~0;~E_2~0 := 1; 60892#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 60893#L824-3 assume 0 == ~E_4~0;~E_4~0 := 1; 60874#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 60875#L834-3 assume !(0 == ~E_6~0); 60860#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 60861#L844-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 60846#L376-27 assume !(1 == ~m_pc~0); 60847#L376-29 is_master_triggered_~__retres1~0#1 := 0; 60832#L387-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 60833#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 60817#L955-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 60818#L955-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 60803#L395-27 assume !(1 == ~t1_pc~0); 60804#L395-29 is_transmit1_triggered_~__retres1~1#1 := 0; 60786#L406-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 60787#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 60771#L963-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 60772#L963-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 60756#L414-27 assume 1 == ~t2_pc~0; 60757#L415-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 73234#L425-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 73233#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 73232#L971-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 73231#L971-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 73230#L433-27 assume !(1 == ~t3_pc~0); 73229#L433-29 is_transmit3_triggered_~__retres1~3#1 := 0; 73228#L444-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 73227#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 73226#L979-27 assume !(0 != activate_threads_~tmp___2~0#1); 73225#L979-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 73224#L452-27 assume !(1 == ~t4_pc~0); 73223#L452-29 is_transmit4_triggered_~__retres1~4#1 := 0; 73221#L463-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 73220#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 73219#L987-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 73218#L987-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 73217#L471-27 assume !(1 == ~t5_pc~0); 73216#L471-29 is_transmit5_triggered_~__retres1~5#1 := 0; 73214#L482-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 73213#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 73212#L995-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 73211#L995-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 73210#L490-27 assume !(1 == ~t6_pc~0); 73209#L490-29 is_transmit6_triggered_~__retres1~6#1 := 0; 73207#L501-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 73206#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 73205#L1003-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 73204#L1003-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 73203#L509-27 assume !(1 == ~t7_pc~0); 73201#L509-29 is_transmit7_triggered_~__retres1~7#1 := 0; 73200#L520-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 73199#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 73198#L1011-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 73197#L1011-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 73196#L857-3 assume 1 == ~M_E~0;~M_E~0 := 2; 72088#L857-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 73195#L862-3 assume !(1 == ~T2_E~0); 73194#L867-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 73193#L872-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 73192#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 73191#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 72081#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 73190#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 73189#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 73188#L902-3 assume !(1 == ~E_2~0); 73187#L907-3 assume 1 == ~E_3~0;~E_3~0 := 2; 73186#L912-3 assume 1 == ~E_4~0;~E_4~0 := 2; 73185#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 73184#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 72844#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 73183#L932-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 73179#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 73174#L626-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 59831#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 59731#L1197 assume !(0 == start_simulation_~tmp~3#1); 59728#L1197-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 59729#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 73072#L626-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 73071#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 73070#L1152 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 73069#L1159 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 73068#stop_simulation_returnLabel#1 start_simulation_#t~ret24#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 73067#L1210 assume !(0 != start_simulation_~tmp___0~1#1); 59331#L1178-2 [2022-12-13 12:19:18,702 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:19:18,702 INFO L85 PathProgramCache]: Analyzing trace with hash 1116257915, now seen corresponding path program 1 times [2022-12-13 12:19:18,702 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:19:18,702 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1400797133] [2022-12-13 12:19:18,702 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:19:18,702 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:19:18,708 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:19:18,734 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:19:18,734 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:19:18,734 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1400797133] [2022-12-13 12:19:18,734 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1400797133] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:19:18,734 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:19:18,734 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-12-13 12:19:18,735 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1334576144] [2022-12-13 12:19:18,735 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:19:18,735 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 12:19:18,735 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:19:18,735 INFO L85 PathProgramCache]: Analyzing trace with hash 2017747177, now seen corresponding path program 1 times [2022-12-13 12:19:18,735 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:19:18,735 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1536673706] [2022-12-13 12:19:18,736 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:19:18,736 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:19:18,745 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:19:18,780 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:19:18,781 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:19:18,781 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1536673706] [2022-12-13 12:19:18,781 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1536673706] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:19:18,781 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:19:18,781 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:19:18,781 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [143780021] [2022-12-13 12:19:18,781 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:19:18,782 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:19:18,782 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:19:18,782 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 12:19:18,782 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 12:19:18,782 INFO L87 Difference]: Start difference. First operand 18651 states and 27011 transitions. cyclomatic complexity: 8376 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 2 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:19:18,958 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:19:18,959 INFO L93 Difference]: Finished difference Result 35898 states and 51685 transitions. [2022-12-13 12:19:18,959 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 35898 states and 51685 transitions. [2022-12-13 12:19:19,094 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 35579 [2022-12-13 12:19:19,167 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 35898 states to 35898 states and 51685 transitions. [2022-12-13 12:19:19,167 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 35898 [2022-12-13 12:19:19,186 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 35898 [2022-12-13 12:19:19,186 INFO L73 IsDeterministic]: Start isDeterministic. Operand 35898 states and 51685 transitions. [2022-12-13 12:19:19,205 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:19:19,205 INFO L218 hiAutomatonCegarLoop]: Abstraction has 35898 states and 51685 transitions. [2022-12-13 12:19:19,230 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 35898 states and 51685 transitions. [2022-12-13 12:19:19,544 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 35898 to 35826. [2022-12-13 12:19:19,584 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 35826 states, 35826 states have (on average 1.4406576229553956) internal successors, (51613), 35825 states have internal predecessors, (51613), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:19:19,660 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 35826 states to 35826 states and 51613 transitions. [2022-12-13 12:19:19,660 INFO L240 hiAutomatonCegarLoop]: Abstraction has 35826 states and 51613 transitions. [2022-12-13 12:19:19,660 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 12:19:19,661 INFO L428 stractBuchiCegarLoop]: Abstraction has 35826 states and 51613 transitions. [2022-12-13 12:19:19,661 INFO L335 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2022-12-13 12:19:19,661 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 35826 states and 51613 transitions. [2022-12-13 12:19:19,751 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 35507 [2022-12-13 12:19:19,751 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:19:19,751 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:19:19,753 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:19:19,753 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:19:19,753 INFO L748 eck$LassoCheckResult]: Stem: 109811#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 109812#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 110439#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 110440#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 110413#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 110414#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 110069#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 109881#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 109882#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 109865#L556-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 109866#L561-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 110412#L566-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 110203#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 110204#L769 assume !(0 == ~M_E~0); 110226#L769-2 assume !(0 == ~T1_E~0); 110227#L774-1 assume !(0 == ~T2_E~0); 110259#L779-1 assume !(0 == ~T3_E~0); 110396#L784-1 assume !(0 == ~T4_E~0); 110200#L789-1 assume !(0 == ~T5_E~0); 110201#L794-1 assume !(0 == ~T6_E~0); 110320#L799-1 assume !(0 == ~T7_E~0); 110207#L804-1 assume !(0 == ~E_M~0); 110208#L809-1 assume !(0 == ~E_1~0); 110251#L814-1 assume !(0 == ~E_2~0); 109608#L819-1 assume !(0 == ~E_3~0); 109609#L824-1 assume !(0 == ~E_4~0); 109956#L829-1 assume !(0 == ~E_5~0); 110488#L834-1 assume !(0 == ~E_6~0); 109741#L839-1 assume !(0 == ~E_7~0); 109742#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 110148#L376 assume !(1 == ~m_pc~0); 110145#L376-2 is_master_triggered_~__retres1~0#1 := 0; 110146#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 110381#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 109680#L955 assume !(0 != activate_threads_~tmp~1#1); 109681#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 110060#L395 assume !(1 == ~t1_pc~0); 110228#L395-2 is_transmit1_triggered_~__retres1~1#1 := 0; 110382#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 109638#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 109639#L963 assume !(0 != activate_threads_~tmp___0~0#1); 110153#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 110154#L414 assume !(1 == ~t2_pc~0); 109744#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 109745#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 109963#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 109964#L971 assume !(0 != activate_threads_~tmp___1~0#1); 110419#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 110065#L433 assume !(1 == ~t3_pc~0); 109853#L433-2 is_transmit3_triggered_~__retres1~3#1 := 0; 109854#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 109606#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 109607#L979 assume !(0 != activate_threads_~tmp___2~0#1); 109705#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 109706#L452 assume !(1 == ~t4_pc~0); 109861#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 109862#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 109699#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 109700#L987 assume !(0 != activate_threads_~tmp___3~0#1); 109893#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 109894#L471 assume !(1 == ~t5_pc~0); 110305#L471-2 is_transmit5_triggered_~__retres1~5#1 := 0; 109876#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 109877#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 110385#L995 assume !(0 != activate_threads_~tmp___4~0#1); 110476#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 110477#L490 assume 1 == ~t6_pc~0; 110446#L491 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 110152#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 109950#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 109951#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 110075#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 110042#L509 assume !(1 == ~t7_pc~0); 110043#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 109834#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 109835#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 109900#L1011 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 109901#L1011-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 110425#L857 assume 1 == ~M_E~0;~M_E~0 := 2; 110426#L857-2 assume !(1 == ~T1_E~0); 109967#L862-1 assume !(1 == ~T2_E~0); 109968#L867-1 assume !(1 == ~T3_E~0); 110066#L872-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 110067#L877-1 assume !(1 == ~T5_E~0); 110444#L882-1 assume !(1 == ~T6_E~0); 110445#L887-1 assume !(1 == ~T7_E~0); 110524#L892-1 assume !(1 == ~E_M~0); 110502#L897-1 assume !(1 == ~E_1~0); 109992#L902-1 assume !(1 == ~E_2~0); 109993#L907-1 assume !(1 == ~E_3~0); 110296#L912-1 assume 1 == ~E_4~0;~E_4~0 := 2; 110289#L917-1 assume !(1 == ~E_5~0); 110290#L922-1 assume !(1 == ~E_6~0); 110491#L927-1 assume !(1 == ~E_7~0); 110555#L932-1 assume { :end_inline_reset_delta_events } true; 116477#L1178-2 [2022-12-13 12:19:19,753 INFO L750 eck$LassoCheckResult]: Loop: 116477#L1178-2 assume !false; 122132#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 122131#L744 assume !false; 122130#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 122129#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 122121#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 122120#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 122118#L641 assume !(0 != eval_~tmp~0#1); 122119#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 123530#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 123529#L769-3 assume 0 == ~M_E~0;~M_E~0 := 1; 123528#L769-5 assume !(0 == ~T1_E~0); 123527#L774-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 123526#L779-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 123525#L784-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 123524#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 123523#L794-3 assume !(0 == ~T6_E~0); 123522#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 123521#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 123520#L809-3 assume !(0 == ~E_1~0); 123519#L814-3 assume 0 == ~E_2~0;~E_2~0 := 1; 123518#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 123517#L824-3 assume 0 == ~E_4~0;~E_4~0 := 1; 123516#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 123515#L834-3 assume !(0 == ~E_6~0); 123514#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 123513#L844-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 123512#L376-27 assume !(1 == ~m_pc~0); 123511#L376-29 is_master_triggered_~__retres1~0#1 := 0; 123510#L387-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 123509#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 123508#L955-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 123507#L955-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 123506#L395-27 assume !(1 == ~t1_pc~0); 123505#L395-29 is_transmit1_triggered_~__retres1~1#1 := 0; 123504#L406-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 123503#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 123502#L963-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 123501#L963-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 123500#L414-27 assume 1 == ~t2_pc~0; 123499#L415-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 123497#L425-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 123496#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 123495#L971-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 123494#L971-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 123493#L433-27 assume !(1 == ~t3_pc~0); 123492#L433-29 is_transmit3_triggered_~__retres1~3#1 := 0; 123491#L444-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 123490#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 123489#L979-27 assume !(0 != activate_threads_~tmp___2~0#1); 123488#L979-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 123487#L452-27 assume 1 == ~t4_pc~0; 123485#L453-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 123484#L463-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 123483#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 123482#L987-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 123481#L987-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 123480#L471-27 assume !(1 == ~t5_pc~0); 123479#L471-29 is_transmit5_triggered_~__retres1~5#1 := 0; 123478#L482-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 123477#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 123476#L995-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 123475#L995-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 123474#L490-27 assume !(1 == ~t6_pc~0); 123473#L490-29 is_transmit6_triggered_~__retres1~6#1 := 0; 123471#L501-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 123470#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 123469#L1003-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 123468#L1003-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 123467#L509-27 assume !(1 == ~t7_pc~0); 123465#L509-29 is_transmit7_triggered_~__retres1~7#1 := 0; 123464#L520-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 123463#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 123462#L1011-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 123461#L1011-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 122758#L857-3 assume 1 == ~M_E~0;~M_E~0 := 2; 122406#L857-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 122757#L862-3 assume !(1 == ~T2_E~0); 122756#L867-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 122755#L872-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 122754#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 122397#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 122396#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 122395#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 122394#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 122393#L902-3 assume !(1 == ~E_2~0); 122392#L907-3 assume 1 == ~E_3~0;~E_3~0 := 2; 122391#L912-3 assume 1 == ~E_4~0;~E_4~0 := 2; 122390#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 122389#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 122387#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 122386#L932-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 122382#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 122377#L626-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 122376#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 122265#L1197 assume !(0 == start_simulation_~tmp~3#1); 122264#L1197-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 122260#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 122255#L626-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 122254#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 122253#L1152 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 122252#L1159 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 122251#stop_simulation_returnLabel#1 start_simulation_#t~ret24#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 122250#L1210 assume !(0 != start_simulation_~tmp___0~1#1); 116477#L1178-2 [2022-12-13 12:19:19,753 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:19:19,754 INFO L85 PathProgramCache]: Analyzing trace with hash -2127260292, now seen corresponding path program 1 times [2022-12-13 12:19:19,754 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:19:19,754 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1604364772] [2022-12-13 12:19:19,754 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:19:19,754 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:19:19,763 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:19:19,808 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:19:19,809 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:19:19,809 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1604364772] [2022-12-13 12:19:19,809 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1604364772] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:19:19,809 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:19:19,809 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:19:19,809 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1999796409] [2022-12-13 12:19:19,809 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:19:19,810 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 12:19:19,810 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:19:19,810 INFO L85 PathProgramCache]: Analyzing trace with hash -2003441624, now seen corresponding path program 1 times [2022-12-13 12:19:19,810 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:19:19,810 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1492966412] [2022-12-13 12:19:19,811 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:19:19,811 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:19:19,820 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:19:19,848 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:19:19,848 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:19:19,848 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1492966412] [2022-12-13 12:19:19,848 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1492966412] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:19:19,848 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:19:19,848 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:19:19,848 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1954772757] [2022-12-13 12:19:19,848 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:19:19,849 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:19:19,849 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:19:19,849 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 12:19:19,849 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 12:19:19,850 INFO L87 Difference]: Start difference. First operand 35826 states and 51613 transitions. cyclomatic complexity: 15819 Second operand has 4 states, 4 states have (on average 23.75) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:19:20,356 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:19:20,356 INFO L93 Difference]: Finished difference Result 98927 states and 141456 transitions. [2022-12-13 12:19:20,356 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 98927 states and 141456 transitions. [2022-12-13 12:19:20,734 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 96097 [2022-12-13 12:19:20,939 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 98927 states to 98927 states and 141456 transitions. [2022-12-13 12:19:20,939 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 98927 [2022-12-13 12:19:21,017 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 98927 [2022-12-13 12:19:21,017 INFO L73 IsDeterministic]: Start isDeterministic. Operand 98927 states and 141456 transitions. [2022-12-13 12:19:21,055 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:19:21,055 INFO L218 hiAutomatonCegarLoop]: Abstraction has 98927 states and 141456 transitions. [2022-12-13 12:19:21,091 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 98927 states and 141456 transitions. [2022-12-13 12:19:21,828 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 98927 to 95639. [2022-12-13 12:19:21,888 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 95639 states, 95639 states have (on average 1.4347285103357417) internal successors, (137216), 95638 states have internal predecessors, (137216), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:19:22,011 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 95639 states to 95639 states and 137216 transitions. [2022-12-13 12:19:22,011 INFO L240 hiAutomatonCegarLoop]: Abstraction has 95639 states and 137216 transitions. [2022-12-13 12:19:22,012 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 12:19:22,012 INFO L428 stractBuchiCegarLoop]: Abstraction has 95639 states and 137216 transitions. [2022-12-13 12:19:22,012 INFO L335 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2022-12-13 12:19:22,012 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 95639 states and 137216 transitions. [2022-12-13 12:19:22,213 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 95017 [2022-12-13 12:19:22,213 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:19:22,213 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:19:22,214 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:19:22,214 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:19:22,215 INFO L748 eck$LassoCheckResult]: Stem: 244573#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 244574#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 245230#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 245231#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 245208#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 245209#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 244835#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 244643#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 244644#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 244627#L556-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 244628#L561-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 245207#L566-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 244968#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 244969#L769 assume !(0 == ~M_E~0); 244992#L769-2 assume !(0 == ~T1_E~0); 244993#L774-1 assume !(0 == ~T2_E~0); 245027#L779-1 assume !(0 == ~T3_E~0); 245191#L784-1 assume !(0 == ~T4_E~0); 244966#L789-1 assume !(0 == ~T5_E~0); 244967#L794-1 assume !(0 == ~T6_E~0); 245099#L799-1 assume !(0 == ~T7_E~0); 244971#L804-1 assume !(0 == ~E_M~0); 244972#L809-1 assume !(0 == ~E_1~0); 245017#L814-1 assume !(0 == ~E_2~0); 244371#L819-1 assume !(0 == ~E_3~0); 244372#L824-1 assume !(0 == ~E_4~0); 244718#L829-1 assume !(0 == ~E_5~0); 245289#L834-1 assume !(0 == ~E_6~0); 244500#L839-1 assume !(0 == ~E_7~0); 244501#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 244916#L376 assume !(1 == ~m_pc~0); 244912#L376-2 is_master_triggered_~__retres1~0#1 := 0; 244913#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 245171#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 244442#L955 assume !(0 != activate_threads_~tmp~1#1); 244443#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 244827#L395 assume !(1 == ~t1_pc~0); 244994#L395-2 is_transmit1_triggered_~__retres1~1#1 := 0; 245172#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 244400#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 244401#L963 assume !(0 != activate_threads_~tmp___0~0#1); 244920#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 244921#L414 assume !(1 == ~t2_pc~0); 244503#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 244504#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 244727#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 244728#L971 assume !(0 != activate_threads_~tmp___1~0#1); 245212#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 244832#L433 assume !(1 == ~t3_pc~0); 244614#L433-2 is_transmit3_triggered_~__retres1~3#1 := 0; 244615#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 244369#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 244370#L979 assume !(0 != activate_threads_~tmp___2~0#1); 244466#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 244467#L452 assume !(1 == ~t4_pc~0); 244623#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 244624#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 244460#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 244461#L987 assume !(0 != activate_threads_~tmp___3~0#1); 244653#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 244654#L471 assume !(1 == ~t5_pc~0); 245078#L471-2 is_transmit5_triggered_~__retres1~5#1 := 0; 244638#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 244639#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 245175#L995 assume !(0 != activate_threads_~tmp___4~0#1); 245274#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 245275#L490 assume !(1 == ~t6_pc~0); 244918#L490-2 is_transmit6_triggered_~__retres1~6#1 := 0; 244919#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 244712#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 244713#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 244841#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 244806#L509 assume !(1 == ~t7_pc~0); 244807#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 244594#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 244595#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 244660#L1011 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 244661#L1011-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 245218#L857 assume 1 == ~M_E~0;~M_E~0 := 2; 244449#L857-2 assume !(1 == ~T1_E~0); 244450#L862-1 assume !(1 == ~T2_E~0); 244731#L867-1 assume !(1 == ~T3_E~0); 244736#L872-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 244833#L877-1 assume !(1 == ~T5_E~0); 245047#L882-1 assume !(1 == ~T6_E~0); 245239#L887-1 assume !(1 == ~T7_E~0); 321012#L892-1 assume !(1 == ~E_M~0); 321001#L897-1 assume !(1 == ~E_1~0); 244753#L902-1 assume !(1 == ~E_2~0); 244754#L907-1 assume !(1 == ~E_3~0); 245064#L912-1 assume 1 == ~E_4~0;~E_4~0 := 2; 245065#L917-1 assume !(1 == ~E_5~0); 245293#L922-1 assume !(1 == ~E_6~0); 245294#L927-1 assume !(1 == ~E_7~0); 245042#L932-1 assume { :end_inline_reset_delta_events } true; 245043#L1178-2 [2022-12-13 12:19:22,215 INFO L750 eck$LassoCheckResult]: Loop: 245043#L1178-2 assume !false; 333156#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 333157#L744 assume !false; 333151#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 333152#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 335928#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 335927#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 333133#L641 assume !(0 != eval_~tmp~0#1); 333135#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 337268#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 337269#L769-3 assume 0 == ~M_E~0;~M_E~0 := 1; 337264#L769-5 assume !(0 == ~T1_E~0); 337265#L774-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 337259#L779-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 337260#L784-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 337255#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 337256#L794-3 assume !(0 == ~T6_E~0); 337249#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 337250#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 337243#L809-3 assume !(0 == ~E_1~0); 337244#L814-3 assume 0 == ~E_2~0;~E_2~0 := 1; 337236#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 337237#L824-3 assume 0 == ~E_4~0;~E_4~0 := 1; 337230#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 337231#L834-3 assume !(0 == ~E_6~0); 337224#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 337225#L844-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 337219#L376-27 assume !(1 == ~m_pc~0); 337220#L376-29 is_master_triggered_~__retres1~0#1 := 0; 337213#L387-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 337214#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 337207#L955-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 337208#L955-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 337200#L395-27 assume !(1 == ~t1_pc~0); 337201#L395-29 is_transmit1_triggered_~__retres1~1#1 := 0; 337195#L406-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 337196#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 244990#L963-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 244991#L963-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 245268#L414-27 assume !(1 == ~t2_pc~0); 245270#L414-29 is_transmit2_triggered_~__retres1~2#1 := 0; 245053#L425-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 245054#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 244899#L971-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 244900#L971-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 339311#L433-27 assume !(1 == ~t3_pc~0); 338799#L433-29 is_transmit3_triggered_~__retres1~3#1 := 0; 338800#L444-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 338792#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 338793#L979-27 assume !(0 != activate_threads_~tmp___2~0#1); 338786#L979-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 338787#L452-27 assume !(1 == ~t4_pc~0); 338780#L452-29 is_transmit4_triggered_~__retres1~4#1 := 0; 338779#L463-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 338771#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 338772#L987-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 338765#L987-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 338766#L471-27 assume !(1 == ~t5_pc~0); 244746#L471-29 is_transmit5_triggered_~__retres1~5#1 := 0; 244747#L482-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 245185#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 245186#L995-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 244995#L995-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 244914#L490-27 assume !(1 == ~t6_pc~0); 244915#L490-29 is_transmit6_triggered_~__retres1~6#1 := 0; 244611#L501-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 244612#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 339294#L1003-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 339293#L1003-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 339292#L509-27 assume !(1 == ~t7_pc~0); 244802#L509-29 is_transmit7_triggered_~__retres1~7#1 := 0; 244803#L520-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 339291#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 244936#L1011-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 244937#L1011-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 244951#L857-3 assume 1 == ~M_E~0;~M_E~0 := 2; 244952#L857-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 244988#L862-3 assume !(1 == ~T2_E~0); 245324#L867-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 245325#L872-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 244943#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 244944#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 244982#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 244983#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 337047#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 337046#L902-3 assume !(1 == ~E_2~0); 337045#L907-3 assume 1 == ~E_3~0;~E_3~0 := 2; 337044#L912-3 assume 1 == ~E_4~0;~E_4~0 := 2; 337043#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 337042#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 244625#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 244626#L932-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 244475#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 244381#L626-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 244683#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 244684#L1197 assume !(0 == start_simulation_~tmp~3#1); 244818#L1197-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 244530#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 244498#L626-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 244398#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 244399#L1152 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 245334#L1159 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 336080#stop_simulation_returnLabel#1 start_simulation_#t~ret24#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 334151#L1210 assume !(0 != start_simulation_~tmp___0~1#1); 245043#L1178-2 [2022-12-13 12:19:22,215 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:19:22,215 INFO L85 PathProgramCache]: Analyzing trace with hash 1196032317, now seen corresponding path program 1 times [2022-12-13 12:19:22,215 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:19:22,215 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2010728310] [2022-12-13 12:19:22,216 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:19:22,216 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:19:22,224 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:19:22,259 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:19:22,259 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:19:22,259 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2010728310] [2022-12-13 12:19:22,259 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2010728310] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:19:22,260 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:19:22,260 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-12-13 12:19:22,260 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1538758729] [2022-12-13 12:19:22,260 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:19:22,260 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 12:19:22,260 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:19:22,261 INFO L85 PathProgramCache]: Analyzing trace with hash -1899577302, now seen corresponding path program 1 times [2022-12-13 12:19:22,261 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:19:22,261 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [484308202] [2022-12-13 12:19:22,261 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:19:22,261 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:19:22,268 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:19:22,284 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:19:22,284 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:19:22,284 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [484308202] [2022-12-13 12:19:22,285 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [484308202] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:19:22,285 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:19:22,285 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:19:22,285 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1096635151] [2022-12-13 12:19:22,285 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:19:22,285 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:19:22,285 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:19:22,286 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-12-13 12:19:22,286 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-12-13 12:19:22,286 INFO L87 Difference]: Start difference. First operand 95639 states and 137216 transitions. cyclomatic complexity: 41641 Second operand has 5 states, 5 states have (on average 19.0) internal successors, (95), 5 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:19:23,051 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:19:23,051 INFO L93 Difference]: Finished difference Result 217819 states and 316152 transitions. [2022-12-13 12:19:23,052 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 217819 states and 316152 transitions. [2022-12-13 12:19:23,866 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 216166 [2022-12-13 12:19:24,340 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 217819 states to 217819 states and 316152 transitions. [2022-12-13 12:19:24,341 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 217819 [2022-12-13 12:19:24,416 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 217819 [2022-12-13 12:19:24,416 INFO L73 IsDeterministic]: Start isDeterministic. Operand 217819 states and 316152 transitions. [2022-12-13 12:19:24,515 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:19:24,515 INFO L218 hiAutomatonCegarLoop]: Abstraction has 217819 states and 316152 transitions. [2022-12-13 12:19:24,606 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 217819 states and 316152 transitions. [2022-12-13 12:19:25,588 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 217819 to 99398. [2022-12-13 12:19:25,653 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 99398 states, 99398 states have (on average 1.4182880943278537) internal successors, (140975), 99397 states have internal predecessors, (140975), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:19:25,796 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 99398 states to 99398 states and 140975 transitions. [2022-12-13 12:19:25,796 INFO L240 hiAutomatonCegarLoop]: Abstraction has 99398 states and 140975 transitions. [2022-12-13 12:19:25,797 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-12-13 12:19:25,797 INFO L428 stractBuchiCegarLoop]: Abstraction has 99398 states and 140975 transitions. [2022-12-13 12:19:25,797 INFO L335 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2022-12-13 12:19:25,797 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 99398 states and 140975 transitions. [2022-12-13 12:19:26,050 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 98773 [2022-12-13 12:19:26,051 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:19:26,051 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:19:26,052 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:19:26,052 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:19:26,052 INFO L748 eck$LassoCheckResult]: Stem: 558044#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 558045#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 558689#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 558690#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 558658#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 558659#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 558297#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 558114#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 558115#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 558098#L556-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 558099#L561-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 558657#L566-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 558430#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 558431#L769 assume !(0 == ~M_E~0); 558452#L769-2 assume !(0 == ~T1_E~0); 558453#L774-1 assume !(0 == ~T2_E~0); 558488#L779-1 assume !(0 == ~T3_E~0); 558642#L784-1 assume !(0 == ~T4_E~0); 558428#L789-1 assume !(0 == ~T5_E~0); 558429#L794-1 assume !(0 == ~T6_E~0); 558555#L799-1 assume !(0 == ~T7_E~0); 558433#L804-1 assume !(0 == ~E_M~0); 558434#L809-1 assume !(0 == ~E_1~0); 558478#L814-1 assume !(0 == ~E_2~0); 557842#L819-1 assume !(0 == ~E_3~0); 557843#L824-1 assume !(0 == ~E_4~0); 558188#L829-1 assume !(0 == ~E_5~0); 558747#L834-1 assume !(0 == ~E_6~0); 557973#L839-1 assume !(0 == ~E_7~0); 557974#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 558377#L376 assume !(1 == ~m_pc~0); 558373#L376-2 is_master_triggered_~__retres1~0#1 := 0; 558374#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 558621#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 557914#L955 assume !(0 != activate_threads_~tmp~1#1); 557915#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 558290#L395 assume !(1 == ~t1_pc~0); 558454#L395-2 is_transmit1_triggered_~__retres1~1#1 := 0; 558622#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 557871#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 557872#L963 assume !(0 != activate_threads_~tmp___0~0#1); 558382#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 558383#L414 assume !(1 == ~t2_pc~0); 557976#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 557977#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 558197#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 558198#L971 assume !(0 != activate_threads_~tmp___1~0#1); 558664#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 558294#L433 assume !(1 == ~t3_pc~0); 558088#L433-2 is_transmit3_triggered_~__retres1~3#1 := 0; 558089#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 557840#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 557841#L979 assume !(0 != activate_threads_~tmp___2~0#1); 557938#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 557939#L452 assume !(1 == ~t4_pc~0); 558094#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 558095#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 557932#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 557933#L987 assume !(0 != activate_threads_~tmp___3~0#1); 558125#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 558126#L471 assume !(1 == ~t5_pc~0); 558532#L471-2 is_transmit5_triggered_~__retres1~5#1 := 0; 558109#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 558110#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 558626#L995 assume !(0 != activate_threads_~tmp___4~0#1); 558733#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 558734#L490 assume !(1 == ~t6_pc~0); 558380#L490-2 is_transmit6_triggered_~__retres1~6#1 := 0; 558381#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 558182#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 558183#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 558305#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 558272#L509 assume !(1 == ~t7_pc~0); 558273#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 558069#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 558070#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 558132#L1011 assume !(0 != activate_threads_~tmp___6~0#1); 558133#L1011-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 558676#L857 assume 1 == ~M_E~0;~M_E~0 := 2; 558677#L857-2 assume !(1 == ~T1_E~0); 603322#L862-1 assume !(1 == ~T2_E~0); 603321#L867-1 assume !(1 == ~T3_E~0); 603320#L872-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 603319#L877-1 assume !(1 == ~T5_E~0); 558697#L882-1 assume !(1 == ~T6_E~0); 558698#L887-1 assume !(1 == ~T7_E~0); 558582#L892-1 assume !(1 == ~E_M~0); 558583#L897-1 assume !(1 == ~E_1~0); 558223#L902-1 assume !(1 == ~E_2~0); 558224#L907-1 assume !(1 == ~E_3~0); 558522#L912-1 assume 1 == ~E_4~0;~E_4~0 := 2; 558512#L917-1 assume !(1 == ~E_5~0); 558513#L922-1 assume !(1 == ~E_6~0); 558750#L927-1 assume !(1 == ~E_7~0); 558501#L932-1 assume { :end_inline_reset_delta_events } true; 558502#L1178-2 [2022-12-13 12:19:26,052 INFO L750 eck$LassoCheckResult]: Loop: 558502#L1178-2 assume !false; 643415#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 643352#L744 assume !false; 643348#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 643301#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 643289#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 643283#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 643274#L641 assume !(0 != eval_~tmp~0#1); 643275#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 645254#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 645237#L769-3 assume 0 == ~M_E~0;~M_E~0 := 1; 645199#L769-5 assume !(0 == ~T1_E~0); 645197#L774-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 644026#L779-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 644025#L784-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 644024#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 644023#L794-3 assume !(0 == ~T6_E~0); 644022#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 643973#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 643971#L809-3 assume !(0 == ~E_1~0); 643968#L814-3 assume 0 == ~E_2~0;~E_2~0 := 1; 643967#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 643965#L824-3 assume 0 == ~E_4~0;~E_4~0 := 1; 643964#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 643963#L834-3 assume !(0 == ~E_6~0); 643961#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 643902#L844-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 643901#L376-27 assume !(1 == ~m_pc~0); 643900#L376-29 is_master_triggered_~__retres1~0#1 := 0; 643899#L387-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 643898#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 643897#L955-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 643896#L955-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 643895#L395-27 assume !(1 == ~t1_pc~0); 643894#L395-29 is_transmit1_triggered_~__retres1~1#1 := 0; 643893#L406-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 643892#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 643891#L963-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 643890#L963-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 643889#L414-27 assume !(1 == ~t2_pc~0); 643887#L414-29 is_transmit2_triggered_~__retres1~2#1 := 0; 643886#L425-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 643885#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 643884#L971-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 643883#L971-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 643882#L433-27 assume !(1 == ~t3_pc~0); 643881#L433-29 is_transmit3_triggered_~__retres1~3#1 := 0; 643880#L444-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 643879#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 643878#L979-27 assume !(0 != activate_threads_~tmp___2~0#1); 643877#L979-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 643876#L452-27 assume !(1 == ~t4_pc~0); 643875#L452-29 is_transmit4_triggered_~__retres1~4#1 := 0; 643873#L463-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 643872#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 643871#L987-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 643870#L987-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 643869#L471-27 assume !(1 == ~t5_pc~0); 643868#L471-29 is_transmit5_triggered_~__retres1~5#1 := 0; 643867#L482-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 643866#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 643865#L995-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 643864#L995-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 643863#L490-27 assume !(1 == ~t6_pc~0); 643862#L490-29 is_transmit6_triggered_~__retres1~6#1 := 0; 643861#L501-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 643860#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 643859#L1003-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 643858#L1003-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 643857#L509-27 assume 1 == ~t7_pc~0; 643855#L510-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 643853#L520-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 643851#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 643849#L1011-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 643847#L1011-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 643846#L857-3 assume 1 == ~M_E~0;~M_E~0 := 2; 603770#L857-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 643845#L862-3 assume !(1 == ~T2_E~0); 643844#L867-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 643843#L872-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 643842#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 643838#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 616686#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 643837#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 643792#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 643790#L902-3 assume !(1 == ~E_2~0); 643788#L907-3 assume 1 == ~E_3~0;~E_3~0 := 2; 643786#L912-3 assume 1 == ~E_4~0;~E_4~0 := 2; 643784#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 643782#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 615695#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 643779#L932-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 643696#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 643682#L626-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 643679#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 643676#L1197 assume !(0 == start_simulation_~tmp~3#1); 643674#L1197-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 643616#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 643609#L626-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 643604#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 643548#L1152 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 643545#L1159 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 643536#stop_simulation_returnLabel#1 start_simulation_#t~ret24#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 643476#L1210 assume !(0 != start_simulation_~tmp___0~1#1); 558502#L1178-2 [2022-12-13 12:19:26,052 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:19:26,052 INFO L85 PathProgramCache]: Analyzing trace with hash -492911425, now seen corresponding path program 1 times [2022-12-13 12:19:26,053 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:19:26,053 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [137346081] [2022-12-13 12:19:26,053 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:19:26,053 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:19:26,060 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:19:26,088 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:19:26,088 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:19:26,088 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [137346081] [2022-12-13 12:19:26,088 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [137346081] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:19:26,088 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:19:26,089 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-12-13 12:19:26,089 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [207607173] [2022-12-13 12:19:26,089 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:19:26,089 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 12:19:26,089 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:19:26,089 INFO L85 PathProgramCache]: Analyzing trace with hash 1343940905, now seen corresponding path program 1 times [2022-12-13 12:19:26,090 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:19:26,090 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1587309862] [2022-12-13 12:19:26,090 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:19:26,090 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:19:26,096 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:19:26,111 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:19:26,112 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:19:26,112 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1587309862] [2022-12-13 12:19:26,112 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1587309862] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:19:26,112 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:19:26,112 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:19:26,112 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1252912564] [2022-12-13 12:19:26,112 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:19:26,113 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:19:26,113 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:19:26,113 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 12:19:26,113 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 12:19:26,113 INFO L87 Difference]: Start difference. First operand 99398 states and 140975 transitions. cyclomatic complexity: 41641 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 2 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:19:26,562 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:19:26,562 INFO L93 Difference]: Finished difference Result 124856 states and 177173 transitions. [2022-12-13 12:19:26,562 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 124856 states and 177173 transitions. [2022-12-13 12:19:26,921 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 124121 [2022-12-13 12:19:27,267 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 124856 states to 124856 states and 177173 transitions. [2022-12-13 12:19:27,267 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 124856 [2022-12-13 12:19:27,297 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 124856 [2022-12-13 12:19:27,298 INFO L73 IsDeterministic]: Start isDeterministic. Operand 124856 states and 177173 transitions. [2022-12-13 12:19:27,329 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:19:27,329 INFO L218 hiAutomatonCegarLoop]: Abstraction has 124856 states and 177173 transitions. [2022-12-13 12:19:27,368 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 124856 states and 177173 transitions. [2022-12-13 12:19:27,796 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 124856 to 54166. [2022-12-13 12:19:27,829 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 54166 states, 54166 states have (on average 1.4244175312926928) internal successors, (77155), 54165 states have internal predecessors, (77155), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:19:27,900 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 54166 states to 54166 states and 77155 transitions. [2022-12-13 12:19:27,900 INFO L240 hiAutomatonCegarLoop]: Abstraction has 54166 states and 77155 transitions. [2022-12-13 12:19:27,901 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 12:19:27,901 INFO L428 stractBuchiCegarLoop]: Abstraction has 54166 states and 77155 transitions. [2022-12-13 12:19:27,901 INFO L335 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2022-12-13 12:19:27,901 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 54166 states and 77155 transitions. [2022-12-13 12:19:28,151 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 53817 [2022-12-13 12:19:28,151 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:19:28,152 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:19:28,156 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:19:28,156 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:19:28,157 INFO L748 eck$LassoCheckResult]: Stem: 782307#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 782308#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 782952#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 782953#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 782922#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 782923#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 782559#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 782377#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 782378#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 782361#L556-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 782362#L561-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 782919#L566-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 782692#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 782693#L769 assume !(0 == ~M_E~0); 782715#L769-2 assume !(0 == ~T1_E~0); 782716#L774-1 assume !(0 == ~T2_E~0); 782752#L779-1 assume !(0 == ~T3_E~0); 782901#L784-1 assume !(0 == ~T4_E~0); 782690#L789-1 assume !(0 == ~T5_E~0); 782691#L794-1 assume !(0 == ~T6_E~0); 782822#L799-1 assume !(0 == ~T7_E~0); 782695#L804-1 assume !(0 == ~E_M~0); 782696#L809-1 assume !(0 == ~E_1~0); 782744#L814-1 assume !(0 == ~E_2~0); 782103#L819-1 assume !(0 == ~E_3~0); 782104#L824-1 assume !(0 == ~E_4~0); 782449#L829-1 assume !(0 == ~E_5~0); 783014#L834-1 assume !(0 == ~E_6~0); 782236#L839-1 assume !(0 == ~E_7~0); 782237#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 782640#L376 assume !(1 == ~m_pc~0); 782636#L376-2 is_master_triggered_~__retres1~0#1 := 0; 782637#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 782882#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 782176#L955 assume !(0 != activate_threads_~tmp~1#1); 782177#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 782552#L395 assume !(1 == ~t1_pc~0); 782717#L395-2 is_transmit1_triggered_~__retres1~1#1 := 0; 782883#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 782132#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 782133#L963 assume !(0 != activate_threads_~tmp___0~0#1); 782645#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 782646#L414 assume !(1 == ~t2_pc~0); 782239#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 782240#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 782456#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 782457#L971 assume !(0 != activate_threads_~tmp___1~0#1); 782930#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 782556#L433 assume !(1 == ~t3_pc~0); 782348#L433-2 is_transmit3_triggered_~__retres1~3#1 := 0; 782349#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 782101#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 782102#L979 assume !(0 != activate_threads_~tmp___2~0#1); 782200#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 782201#L452 assume !(1 == ~t4_pc~0); 782357#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 782358#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 782194#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 782195#L987 assume !(0 != activate_threads_~tmp___3~0#1); 782387#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 782388#L471 assume !(1 == ~t5_pc~0); 782800#L471-2 is_transmit5_triggered_~__retres1~5#1 := 0; 782372#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 782373#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 782886#L995 assume !(0 != activate_threads_~tmp___4~0#1); 782996#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 782997#L490 assume !(1 == ~t6_pc~0); 782643#L490-2 is_transmit6_triggered_~__retres1~6#1 := 0; 782644#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 782443#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 782444#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 782566#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 782533#L509 assume !(1 == ~t7_pc~0); 782534#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 782329#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 782330#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 782394#L1011 assume !(0 != activate_threads_~tmp___6~0#1); 782395#L1011-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 782939#L857 assume !(1 == ~M_E~0); 782183#L857-2 assume !(1 == ~T1_E~0); 782184#L862-1 assume !(1 == ~T2_E~0); 782460#L867-1 assume !(1 == ~T3_E~0); 782465#L872-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 782557#L877-1 assume !(1 == ~T5_E~0); 782771#L882-1 assume !(1 == ~T6_E~0); 782962#L887-1 assume !(1 == ~T7_E~0); 782845#L892-1 assume !(1 == ~E_M~0); 782846#L897-1 assume !(1 == ~E_1~0); 782481#L902-1 assume !(1 == ~E_2~0); 782482#L907-1 assume !(1 == ~E_3~0); 782790#L912-1 assume 1 == ~E_4~0;~E_4~0 := 2; 782779#L917-1 assume !(1 == ~E_5~0); 782780#L922-1 assume !(1 == ~E_6~0); 783020#L927-1 assume !(1 == ~E_7~0); 782766#L932-1 assume { :end_inline_reset_delta_events } true; 782767#L1178-2 [2022-12-13 12:19:28,157 INFO L750 eck$LassoCheckResult]: Loop: 782767#L1178-2 assume !false; 825543#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 825541#L744 assume !false; 825538#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 825536#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 825527#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 825525#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 825522#L641 assume !(0 != eval_~tmp~0#1); 825520#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 825517#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 825515#L769-3 assume !(0 == ~M_E~0); 825513#L769-5 assume !(0 == ~T1_E~0); 825511#L774-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 825509#L779-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 825507#L784-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 825504#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 825502#L794-3 assume !(0 == ~T6_E~0); 825500#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 825498#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 825496#L809-3 assume !(0 == ~E_1~0); 825494#L814-3 assume 0 == ~E_2~0;~E_2~0 := 1; 825492#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 825490#L824-3 assume 0 == ~E_4~0;~E_4~0 := 1; 825488#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 825486#L834-3 assume !(0 == ~E_6~0); 811864#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 811855#L844-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 811853#L376-27 assume !(1 == ~m_pc~0); 811851#L376-29 is_master_triggered_~__retres1~0#1 := 0; 811850#L387-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 811841#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 811839#L955-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 811837#L955-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 811835#L395-27 assume !(1 == ~t1_pc~0); 811833#L395-29 is_transmit1_triggered_~__retres1~1#1 := 0; 811831#L406-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 811829#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 811827#L963-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 811825#L963-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 811823#L414-27 assume 1 == ~t2_pc~0; 811820#L415-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 811817#L425-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 811815#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 811813#L971-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 811811#L971-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 811809#L433-27 assume !(1 == ~t3_pc~0); 811806#L433-29 is_transmit3_triggered_~__retres1~3#1 := 0; 811804#L444-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 811802#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 811800#L979-27 assume !(0 != activate_threads_~tmp___2~0#1); 811798#L979-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 811796#L452-27 assume 1 == ~t4_pc~0; 811793#L453-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 811791#L463-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 811789#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 811787#L987-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 811785#L987-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 811781#L471-27 assume !(1 == ~t5_pc~0); 811779#L471-29 is_transmit5_triggered_~__retres1~5#1 := 0; 811777#L482-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 811775#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 811772#L995-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 811770#L995-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 811768#L490-27 assume !(1 == ~t6_pc~0); 811767#L490-29 is_transmit6_triggered_~__retres1~6#1 := 0; 811765#L501-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 811763#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 811761#L1003-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 811759#L1003-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 811757#L509-27 assume !(1 == ~t7_pc~0); 811753#L509-29 is_transmit7_triggered_~__retres1~7#1 := 0; 811751#L520-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 811749#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 811747#L1011-27 assume !(0 != activate_threads_~tmp___6~0#1); 811744#L1011-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 811742#L857-3 assume !(1 == ~M_E~0); 808988#L857-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 811739#L862-3 assume !(1 == ~T2_E~0); 811737#L867-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 811735#L872-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 811734#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 811733#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 811732#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 811731#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 811730#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 811721#L902-3 assume !(1 == ~E_2~0); 811719#L907-3 assume 1 == ~E_3~0;~E_3~0 := 2; 811717#L912-3 assume 1 == ~E_4~0;~E_4~0 := 2; 811716#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 811715#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 811714#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 811713#L932-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 811709#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 811696#L626-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 811694#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 809099#L1197 assume !(0 == start_simulation_~tmp~3#1); 809100#L1197-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 825644#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 825638#L626-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 825636#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 825634#L1152 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 825632#L1159 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 825629#stop_simulation_returnLabel#1 start_simulation_#t~ret24#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 825627#L1210 assume !(0 != start_simulation_~tmp___0~1#1); 782767#L1178-2 [2022-12-13 12:19:28,157 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:19:28,158 INFO L85 PathProgramCache]: Analyzing trace with hash -2081259327, now seen corresponding path program 1 times [2022-12-13 12:19:28,158 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:19:28,158 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1477942127] [2022-12-13 12:19:28,158 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:19:28,158 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:19:28,173 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:19:28,227 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:19:28,227 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:19:28,227 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1477942127] [2022-12-13 12:19:28,227 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1477942127] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:19:28,228 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:19:28,228 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:19:28,228 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1463784518] [2022-12-13 12:19:28,228 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:19:28,228 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 12:19:28,229 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:19:28,229 INFO L85 PathProgramCache]: Analyzing trace with hash -1534613270, now seen corresponding path program 1 times [2022-12-13 12:19:28,229 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:19:28,229 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1945443433] [2022-12-13 12:19:28,229 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:19:28,229 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:19:28,240 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:19:28,263 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:19:28,263 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:19:28,263 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1945443433] [2022-12-13 12:19:28,263 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1945443433] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:19:28,263 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:19:28,263 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:19:28,263 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2071216012] [2022-12-13 12:19:28,263 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:19:28,264 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:19:28,264 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:19:28,264 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 12:19:28,264 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 12:19:28,264 INFO L87 Difference]: Start difference. First operand 54166 states and 77155 transitions. cyclomatic complexity: 23005 Second operand has 4 states, 4 states have (on average 23.75) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:19:28,529 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:19:28,529 INFO L93 Difference]: Finished difference Result 86719 states and 122940 transitions. [2022-12-13 12:19:28,529 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 86719 states and 122940 transitions. [2022-12-13 12:19:28,858 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 86163 [2022-12-13 12:19:29,066 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 86719 states to 86719 states and 122940 transitions. [2022-12-13 12:19:29,066 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 86719 [2022-12-13 12:19:29,111 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 86719 [2022-12-13 12:19:29,111 INFO L73 IsDeterministic]: Start isDeterministic. Operand 86719 states and 122940 transitions. [2022-12-13 12:19:29,157 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:19:29,158 INFO L218 hiAutomatonCegarLoop]: Abstraction has 86719 states and 122940 transitions. [2022-12-13 12:19:29,202 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 86719 states and 122940 transitions. [2022-12-13 12:19:29,741 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 86719 to 62099. [2022-12-13 12:19:29,779 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 62099 states, 62099 states have (on average 1.4212145123109874) internal successors, (88256), 62098 states have internal predecessors, (88256), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:19:29,859 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 62099 states to 62099 states and 88256 transitions. [2022-12-13 12:19:29,859 INFO L240 hiAutomatonCegarLoop]: Abstraction has 62099 states and 88256 transitions. [2022-12-13 12:19:29,860 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 12:19:29,860 INFO L428 stractBuchiCegarLoop]: Abstraction has 62099 states and 88256 transitions. [2022-12-13 12:19:29,860 INFO L335 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2022-12-13 12:19:29,860 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 62099 states and 88256 transitions. [2022-12-13 12:19:30,009 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 61679 [2022-12-13 12:19:30,009 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:19:30,009 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:19:30,010 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:19:30,010 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:19:30,010 INFO L748 eck$LassoCheckResult]: Stem: 923202#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 923203#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 923865#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 923866#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 923828#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 923829#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 923460#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 923272#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 923273#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 923255#L556-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 923256#L561-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 923827#L566-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 923602#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 923603#L769 assume !(0 == ~M_E~0); 923624#L769-2 assume !(0 == ~T1_E~0); 923625#L774-1 assume !(0 == ~T2_E~0); 923660#L779-1 assume !(0 == ~T3_E~0); 923812#L784-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 923813#L789-1 assume !(0 == ~T5_E~0); 924026#L794-1 assume !(0 == ~T6_E~0); 924001#L799-1 assume !(0 == ~T7_E~0); 924002#L804-1 assume !(0 == ~E_M~0); 923651#L809-1 assume !(0 == ~E_1~0); 923652#L814-1 assume !(0 == ~E_2~0); 923000#L819-1 assume !(0 == ~E_3~0); 923001#L824-1 assume !(0 == ~E_4~0); 923993#L829-1 assume !(0 == ~E_5~0); 923994#L834-1 assume !(0 == ~E_6~0); 923130#L839-1 assume !(0 == ~E_7~0); 923131#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 923729#L376 assume !(1 == ~m_pc~0); 923536#L376-2 is_master_triggered_~__retres1~0#1 := 0; 923537#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 923793#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 923794#L955 assume !(0 != activate_threads_~tmp~1#1); 924024#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 923626#L395 assume !(1 == ~t1_pc~0); 923627#L395-2 is_transmit1_triggered_~__retres1~1#1 := 0; 923814#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 923815#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 923855#L963 assume !(0 != activate_threads_~tmp___0~0#1); 923856#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 924007#L414 assume !(1 == ~t2_pc~0); 924008#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 923999#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 924000#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 923837#L971 assume !(0 != activate_threads_~tmp___1~0#1); 923838#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 924023#L433 assume !(1 == ~t3_pc~0); 924022#L433-2 is_transmit3_triggered_~__retres1~3#1 := 0; 923927#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 922996#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 922997#L979 assume !(0 != activate_threads_~tmp___2~0#1); 923096#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 923097#L452 assume !(1 == ~t4_pc~0); 923251#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 923252#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 923090#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 923091#L987 assume !(0 != activate_threads_~tmp___3~0#1); 923282#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 923283#L471 assume !(1 == ~t5_pc~0); 923702#L471-2 is_transmit5_triggered_~__retres1~5#1 := 0; 923267#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 923268#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 923997#L995 assume !(0 != activate_threads_~tmp___4~0#1); 923998#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 923951#L490 assume !(1 == ~t6_pc~0); 923952#L490-2 is_transmit6_triggered_~__retres1~6#1 := 0; 923587#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 923588#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 923594#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 923595#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 924019#L509 assume !(1 == ~t7_pc~0); 923843#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 923224#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 923225#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 923289#L1011 assume !(0 != activate_threads_~tmp___6~0#1); 923290#L1011-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 923851#L857 assume !(1 == ~M_E~0); 923852#L857-2 assume !(1 == ~T1_E~0); 923356#L862-1 assume !(1 == ~T2_E~0); 923357#L867-1 assume !(1 == ~T3_E~0); 924016#L872-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 923458#L877-1 assume !(1 == ~T5_E~0); 923679#L882-1 assume !(1 == ~T6_E~0); 923872#L887-1 assume !(1 == ~T7_E~0); 923748#L892-1 assume !(1 == ~E_M~0); 923749#L897-1 assume !(1 == ~E_1~0); 923382#L902-1 assume !(1 == ~E_2~0); 923383#L907-1 assume !(1 == ~E_3~0); 923695#L912-1 assume 1 == ~E_4~0;~E_4~0 := 2; 923686#L917-1 assume !(1 == ~E_5~0); 923687#L922-1 assume !(1 == ~E_6~0); 923916#L927-1 assume !(1 == ~E_7~0); 923674#L932-1 assume { :end_inline_reset_delta_events } true; 923675#L1178-2 [2022-12-13 12:19:30,010 INFO L750 eck$LassoCheckResult]: Loop: 923675#L1178-2 assume !false; 946238#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 946231#L744 assume !false; 946226#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 946203#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 946189#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 946182#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 946175#L641 assume !(0 != eval_~tmp~0#1); 946176#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 946970#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 946969#L769-3 assume !(0 == ~M_E~0); 946968#L769-5 assume !(0 == ~T1_E~0); 946967#L774-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 946966#L779-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 946964#L784-3 assume !(0 == ~T4_E~0); 946965#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 947699#L794-3 assume !(0 == ~T6_E~0); 947694#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 947689#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 947682#L809-3 assume !(0 == ~E_1~0); 947676#L814-3 assume 0 == ~E_2~0;~E_2~0 := 1; 947668#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 947436#L824-3 assume 0 == ~E_4~0;~E_4~0 := 1; 947430#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 947428#L834-3 assume !(0 == ~E_6~0); 947426#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 947423#L844-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 947420#L376-27 assume !(1 == ~m_pc~0); 947418#L376-29 is_master_triggered_~__retres1~0#1 := 0; 947416#L387-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 947414#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 947412#L955-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 947410#L955-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 947404#L395-27 assume !(1 == ~t1_pc~0); 947402#L395-29 is_transmit1_triggered_~__retres1~1#1 := 0; 947400#L406-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 947297#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 947295#L963-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 947293#L963-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 947291#L414-27 assume !(1 == ~t2_pc~0); 947288#L414-29 is_transmit2_triggered_~__retres1~2#1 := 0; 947286#L425-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 947284#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 947282#L971-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 947280#L971-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 947278#L433-27 assume !(1 == ~t3_pc~0); 947238#L433-29 is_transmit3_triggered_~__retres1~3#1 := 0; 947186#L444-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 947178#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 947155#L979-27 assume !(0 != activate_threads_~tmp___2~0#1); 947154#L979-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 947145#L452-27 assume 1 == ~t4_pc~0; 947138#L453-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 947136#L463-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 947134#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 947132#L987-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 947130#L987-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 947125#L471-27 assume !(1 == ~t5_pc~0); 947121#L471-29 is_transmit5_triggered_~__retres1~5#1 := 0; 947092#L482-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 947086#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 947080#L995-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 947073#L995-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 947067#L490-27 assume !(1 == ~t6_pc~0); 947060#L490-29 is_transmit6_triggered_~__retres1~6#1 := 0; 947055#L501-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 947049#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 947043#L1003-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 947035#L1003-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 947028#L509-27 assume 1 == ~t7_pc~0; 947020#L510-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 947012#L520-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 947004#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 946995#L1011-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 946989#L1011-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 946985#L857-3 assume !(1 == ~M_E~0); 946702#L857-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 946977#L862-3 assume !(1 == ~T2_E~0); 946971#L867-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 946894#L872-3 assume !(1 == ~T4_E~0); 946891#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 946889#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 946887#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 946884#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 946882#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 946880#L902-3 assume !(1 == ~E_2~0); 946878#L907-3 assume 1 == ~E_3~0;~E_3~0 := 2; 946876#L912-3 assume 1 == ~E_4~0;~E_4~0 := 2; 946873#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 946872#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 946869#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 946867#L932-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 946849#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 946844#L626-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 946842#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 946593#L1197 assume !(0 == start_simulation_~tmp~3#1); 946590#L1197-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 946298#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 946292#L626-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 946290#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 946288#L1152 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 946286#L1159 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 946283#stop_simulation_returnLabel#1 start_simulation_#t~ret24#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 946281#L1210 assume !(0 != start_simulation_~tmp___0~1#1); 923675#L1178-2 [2022-12-13 12:19:30,011 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:19:30,011 INFO L85 PathProgramCache]: Analyzing trace with hash 1374674307, now seen corresponding path program 1 times [2022-12-13 12:19:30,011 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:19:30,011 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1795714101] [2022-12-13 12:19:30,011 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:19:30,011 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:19:30,018 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:19:30,047 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:19:30,047 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:19:30,047 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1795714101] [2022-12-13 12:19:30,047 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1795714101] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:19:30,047 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:19:30,047 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:19:30,047 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [810964912] [2022-12-13 12:19:30,048 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:19:30,048 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 12:19:30,048 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:19:30,048 INFO L85 PathProgramCache]: Analyzing trace with hash -892407576, now seen corresponding path program 1 times [2022-12-13 12:19:30,048 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:19:30,048 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1543233395] [2022-12-13 12:19:30,048 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:19:30,048 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:19:30,055 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:19:30,070 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:19:30,071 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:19:30,071 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1543233395] [2022-12-13 12:19:30,071 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1543233395] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:19:30,071 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:19:30,071 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:19:30,071 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1252691940] [2022-12-13 12:19:30,071 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:19:30,071 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:19:30,071 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:19:30,071 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 12:19:30,071 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 12:19:30,072 INFO L87 Difference]: Start difference. First operand 62099 states and 88256 transitions. cyclomatic complexity: 26173 Second operand has 4 states, 4 states have (on average 23.75) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:19:30,371 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:19:30,372 INFO L93 Difference]: Finished difference Result 78774 states and 111436 transitions. [2022-12-13 12:19:30,372 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 78774 states and 111436 transitions. [2022-12-13 12:19:30,590 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 78301 [2022-12-13 12:19:30,721 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 78774 states to 78774 states and 111436 transitions. [2022-12-13 12:19:30,722 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 78774 [2022-12-13 12:19:30,752 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 78774 [2022-12-13 12:19:30,752 INFO L73 IsDeterministic]: Start isDeterministic. Operand 78774 states and 111436 transitions. [2022-12-13 12:19:30,779 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:19:30,779 INFO L218 hiAutomatonCegarLoop]: Abstraction has 78774 states and 111436 transitions. [2022-12-13 12:19:30,810 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 78774 states and 111436 transitions. [2022-12-13 12:19:31,303 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 78774 to 54166. [2022-12-13 12:19:31,324 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 54166 states, 54166 states have (on average 1.4183989956799468) internal successors, (76829), 54165 states have internal predecessors, (76829), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:19:31,390 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 54166 states to 54166 states and 76829 transitions. [2022-12-13 12:19:31,390 INFO L240 hiAutomatonCegarLoop]: Abstraction has 54166 states and 76829 transitions. [2022-12-13 12:19:31,391 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 12:19:31,391 INFO L428 stractBuchiCegarLoop]: Abstraction has 54166 states and 76829 transitions. [2022-12-13 12:19:31,391 INFO L335 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2022-12-13 12:19:31,391 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 54166 states and 76829 transitions. [2022-12-13 12:19:31,509 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 53817 [2022-12-13 12:19:31,509 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:19:31,509 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:19:31,510 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:19:31,510 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:19:31,510 INFO L748 eck$LassoCheckResult]: Stem: 1064084#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 1064085#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 1064703#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1064704#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1064679#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 1064680#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1064337#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1064155#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1064156#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1064139#L556-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1064140#L561-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1064678#L566-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1064469#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1064470#L769 assume !(0 == ~M_E~0); 1064490#L769-2 assume !(0 == ~T1_E~0); 1064491#L774-1 assume !(0 == ~T2_E~0); 1064525#L779-1 assume !(0 == ~T3_E~0); 1064664#L784-1 assume !(0 == ~T4_E~0); 1064467#L789-1 assume !(0 == ~T5_E~0); 1064468#L794-1 assume !(0 == ~T6_E~0); 1064588#L799-1 assume !(0 == ~T7_E~0); 1064472#L804-1 assume !(0 == ~E_M~0); 1064473#L809-1 assume !(0 == ~E_1~0); 1064517#L814-1 assume !(0 == ~E_2~0); 1063883#L819-1 assume !(0 == ~E_3~0); 1063884#L824-1 assume !(0 == ~E_4~0); 1064229#L829-1 assume !(0 == ~E_5~0); 1064759#L834-1 assume !(0 == ~E_6~0); 1064012#L839-1 assume !(0 == ~E_7~0); 1064013#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1064418#L376 assume !(1 == ~m_pc~0); 1064414#L376-2 is_master_triggered_~__retres1~0#1 := 0; 1064415#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1064647#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1063955#L955 assume !(0 != activate_threads_~tmp~1#1); 1063956#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1064330#L395 assume !(1 == ~t1_pc~0); 1064492#L395-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1064649#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1063910#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1063911#L963 assume !(0 != activate_threads_~tmp___0~0#1); 1064425#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1064426#L414 assume !(1 == ~t2_pc~0); 1064015#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1064016#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1064236#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1064237#L971 assume !(0 != activate_threads_~tmp___1~0#1); 1064684#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1064334#L433 assume !(1 == ~t3_pc~0); 1064126#L433-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1064127#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1063879#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1063880#L979 assume !(0 != activate_threads_~tmp___2~0#1); 1063978#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1063979#L452 assume !(1 == ~t4_pc~0); 1064135#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1064136#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1063972#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1063973#L987 assume !(0 != activate_threads_~tmp___3~0#1); 1064165#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1064166#L471 assume !(1 == ~t5_pc~0); 1064569#L471-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1064150#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1064151#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1064651#L995 assume !(0 != activate_threads_~tmp___4~0#1); 1064745#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1064746#L490 assume !(1 == ~t6_pc~0); 1064422#L490-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1064423#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1064223#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1064224#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 1064345#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1064309#L509 assume !(1 == ~t7_pc~0); 1064310#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1064108#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1064109#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1064172#L1011 assume !(0 != activate_threads_~tmp___6~0#1); 1064173#L1011-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1064692#L857 assume !(1 == ~M_E~0); 1063960#L857-2 assume !(1 == ~T1_E~0); 1063961#L862-1 assume !(1 == ~T2_E~0); 1064240#L867-1 assume !(1 == ~T3_E~0); 1064245#L872-1 assume !(1 == ~T4_E~0); 1064335#L877-1 assume !(1 == ~T5_E~0); 1064545#L882-1 assume !(1 == ~T6_E~0); 1064712#L887-1 assume !(1 == ~T7_E~0); 1064609#L892-1 assume !(1 == ~E_M~0); 1064610#L897-1 assume !(1 == ~E_1~0); 1064263#L902-1 assume !(1 == ~E_2~0); 1064264#L907-1 assume !(1 == ~E_3~0); 1064559#L912-1 assume 1 == ~E_4~0;~E_4~0 := 2; 1064551#L917-1 assume !(1 == ~E_5~0); 1064552#L922-1 assume !(1 == ~E_6~0); 1064763#L927-1 assume !(1 == ~E_7~0); 1064540#L932-1 assume { :end_inline_reset_delta_events } true; 1064541#L1178-2 [2022-12-13 12:19:31,510 INFO L750 eck$LassoCheckResult]: Loop: 1064541#L1178-2 assume !false; 1106180#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1106178#L744 assume !false; 1106176#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1106174#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1106165#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1106163#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1106160#L641 assume !(0 != eval_~tmp~0#1); 1106161#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1118018#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1118015#L769-3 assume !(0 == ~M_E~0); 1118013#L769-5 assume !(0 == ~T1_E~0); 1118010#L774-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1118003#L779-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1118001#L784-3 assume !(0 == ~T4_E~0); 1117997#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1117994#L794-3 assume !(0 == ~T6_E~0); 1117993#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1117992#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1117991#L809-3 assume !(0 == ~E_1~0); 1117894#L814-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1117702#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1117570#L824-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1116339#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1116338#L834-3 assume !(0 == ~E_6~0); 1116337#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1116336#L844-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1116335#L376-27 assume !(1 == ~m_pc~0); 1116333#L376-29 is_master_triggered_~__retres1~0#1 := 0; 1116331#L387-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1116329#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1116327#L955-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1116324#L955-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1116322#L395-27 assume !(1 == ~t1_pc~0); 1116320#L395-29 is_transmit1_triggered_~__retres1~1#1 := 0; 1116318#L406-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1116316#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1116314#L963-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1116313#L963-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1116312#L414-27 assume 1 == ~t2_pc~0; 1116311#L415-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1116308#L425-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1116306#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1116216#L971-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1116170#L971-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1116165#L433-27 assume !(1 == ~t3_pc~0); 1116156#L433-29 is_transmit3_triggered_~__retres1~3#1 := 0; 1116144#L444-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1116024#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1116022#L979-27 assume !(0 != activate_threads_~tmp___2~0#1); 1116020#L979-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1116018#L452-27 assume !(1 == ~t4_pc~0); 1116016#L452-29 is_transmit4_triggered_~__retres1~4#1 := 0; 1116013#L463-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1116011#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1116009#L987-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1116007#L987-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1116005#L471-27 assume !(1 == ~t5_pc~0); 1116003#L471-29 is_transmit5_triggered_~__retres1~5#1 := 0; 1116001#L482-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1115999#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1115997#L995-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1115995#L995-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1115993#L490-27 assume !(1 == ~t6_pc~0); 1115991#L490-29 is_transmit6_triggered_~__retres1~6#1 := 0; 1115990#L501-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1115989#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1115988#L1003-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1115987#L1003-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1115986#L509-27 assume 1 == ~t7_pc~0; 1115984#L510-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 1115985#L520-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1116159#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1115969#L1011-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1115968#L1011-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1109179#L857-3 assume !(1 == ~M_E~0); 1077029#L857-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1109175#L862-3 assume !(1 == ~T2_E~0); 1109173#L867-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1109171#L872-3 assume !(1 == ~T4_E~0); 1109169#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1109167#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1109164#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1103208#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1103207#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1103206#L902-3 assume !(1 == ~E_2~0); 1081328#L907-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1081327#L912-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1081326#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1081325#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1081324#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1081323#L932-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1081305#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1081299#L626-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1081297#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 1077179#L1197 assume !(0 == start_simulation_~tmp~3#1); 1077180#L1197-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1106237#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1106231#L626-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1106229#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 1106227#L1152 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1106225#L1159 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1106223#stop_simulation_returnLabel#1 start_simulation_#t~ret24#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 1106221#L1210 assume !(0 != start_simulation_~tmp___0~1#1); 1064541#L1178-2 [2022-12-13 12:19:31,510 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:19:31,511 INFO L85 PathProgramCache]: Analyzing trace with hash 1626901955, now seen corresponding path program 1 times [2022-12-13 12:19:31,511 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:19:31,511 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1961197089] [2022-12-13 12:19:31,511 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:19:31,511 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:19:31,518 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:19:31,550 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:19:31,550 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:19:31,550 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1961197089] [2022-12-13 12:19:31,550 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1961197089] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:19:31,550 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:19:31,550 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:19:31,550 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [852257966] [2022-12-13 12:19:31,550 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:19:31,551 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 12:19:31,551 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:19:31,551 INFO L85 PathProgramCache]: Analyzing trace with hash -1543828888, now seen corresponding path program 1 times [2022-12-13 12:19:31,551 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:19:31,551 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1557002826] [2022-12-13 12:19:31,551 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:19:31,551 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:19:31,560 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:19:31,575 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:19:31,575 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:19:31,575 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1557002826] [2022-12-13 12:19:31,575 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1557002826] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:19:31,575 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:19:31,575 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:19:31,575 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [513150841] [2022-12-13 12:19:31,576 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:19:31,576 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:19:31,576 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:19:31,576 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 12:19:31,576 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 12:19:31,576 INFO L87 Difference]: Start difference. First operand 54166 states and 76829 transitions. cyclomatic complexity: 22679 Second operand has 4 states, 4 states have (on average 23.75) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:19:31,833 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:19:31,833 INFO L93 Difference]: Finished difference Result 86752 states and 121537 transitions. [2022-12-13 12:19:31,833 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 86752 states and 121537 transitions. [2022-12-13 12:19:32,235 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 86146 [2022-12-13 12:19:32,402 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 86752 states to 86752 states and 121537 transitions. [2022-12-13 12:19:32,402 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 86752 [2022-12-13 12:19:32,434 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 86752 [2022-12-13 12:19:32,434 INFO L73 IsDeterministic]: Start isDeterministic. Operand 86752 states and 121537 transitions. [2022-12-13 12:19:32,472 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:19:32,472 INFO L218 hiAutomatonCegarLoop]: Abstraction has 86752 states and 121537 transitions. [2022-12-13 12:19:32,505 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 86752 states and 121537 transitions. [2022-12-13 12:19:33,071 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 86752 to 62099. [2022-12-13 12:19:33,111 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 62099 states, 62099 states have (on average 1.40557818966489) internal successors, (87285), 62098 states have internal predecessors, (87285), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:19:33,315 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 62099 states to 62099 states and 87285 transitions. [2022-12-13 12:19:33,316 INFO L240 hiAutomatonCegarLoop]: Abstraction has 62099 states and 87285 transitions. [2022-12-13 12:19:33,316 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 12:19:33,316 INFO L428 stractBuchiCegarLoop]: Abstraction has 62099 states and 87285 transitions. [2022-12-13 12:19:33,316 INFO L335 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2022-12-13 12:19:33,317 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 62099 states and 87285 transitions. [2022-12-13 12:19:33,442 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 61679 [2022-12-13 12:19:33,442 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:19:33,442 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:19:33,443 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:19:33,443 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:19:33,443 INFO L748 eck$LassoCheckResult]: Stem: 1205014#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 1205015#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 1205673#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1205674#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1205640#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 1205641#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1205266#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1205082#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1205083#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1205066#L556-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1205067#L561-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1205639#L566-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1205404#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1205405#L769 assume !(0 == ~M_E~0); 1205425#L769-2 assume !(0 == ~T1_E~0); 1205426#L774-1 assume !(0 == ~T2_E~0); 1205463#L779-1 assume !(0 == ~T3_E~0); 1205621#L784-1 assume !(0 == ~T4_E~0); 1205401#L789-1 assume !(0 == ~T5_E~0); 1205402#L794-1 assume !(0 == ~T6_E~0); 1205529#L799-1 assume !(0 == ~T7_E~0); 1205407#L804-1 assume !(0 == ~E_M~0); 1205408#L809-1 assume !(0 == ~E_1~0); 1205455#L814-1 assume !(0 == ~E_2~0); 1204813#L819-1 assume !(0 == ~E_3~0); 1204814#L824-1 assume 0 == ~E_4~0;~E_4~0 := 1; 1205153#L829-1 assume !(0 == ~E_5~0); 1205814#L834-1 assume !(0 == ~E_6~0); 1204941#L839-1 assume !(0 == ~E_7~0); 1204942#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1205348#L376 assume !(1 == ~m_pc~0); 1205349#L376-2 is_master_triggered_~__retres1~0#1 := 0; 1205785#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1205786#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1204884#L955 assume !(0 != activate_threads_~tmp~1#1); 1204885#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1205427#L395 assume !(1 == ~t1_pc~0); 1205428#L395-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1205622#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1205623#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1205658#L963 assume !(0 != activate_threads_~tmp___0~0#1); 1205659#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1205822#L414 assume !(1 == ~t2_pc~0); 1205823#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1205817#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1205818#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1205646#L971 assume !(0 != activate_threads_~tmp___1~0#1); 1205647#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1205262#L433 assume !(1 == ~t3_pc~0); 1205263#L433-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1205744#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1205745#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1205581#L979 assume !(0 != activate_threads_~tmp___2~0#1); 1205582#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1205800#L452 assume !(1 == ~t4_pc~0); 1205801#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1205843#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1205864#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1205863#L987 assume !(0 != activate_threads_~tmp___3~0#1); 1205862#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1205861#L471 assume !(1 == ~t5_pc~0); 1205860#L471-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1205859#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1205858#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1205857#L995 assume !(0 != activate_threads_~tmp___4~0#1); 1205856#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1205855#L490 assume !(1 == ~t6_pc~0); 1205854#L490-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1205853#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1205852#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1205851#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 1205850#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1205849#L509 assume !(1 == ~t7_pc~0); 1205648#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1205649#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1205846#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1205841#L1011 assume !(0 != activate_threads_~tmp___6~0#1); 1205840#L1011-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1205839#L857 assume !(1 == ~M_E~0); 1205838#L857-2 assume !(1 == ~T1_E~0); 1205837#L862-1 assume !(1 == ~T2_E~0); 1205836#L867-1 assume !(1 == ~T3_E~0); 1205835#L872-1 assume !(1 == ~T4_E~0); 1205834#L877-1 assume !(1 == ~T5_E~0); 1205833#L882-1 assume !(1 == ~T6_E~0); 1205832#L887-1 assume !(1 == ~T7_E~0); 1205831#L892-1 assume !(1 == ~E_M~0); 1205830#L897-1 assume !(1 == ~E_1~0); 1205829#L902-1 assume !(1 == ~E_2~0); 1205828#L907-1 assume !(1 == ~E_3~0); 1205827#L912-1 assume 1 == ~E_4~0;~E_4~0 := 2; 1205489#L917-1 assume !(1 == ~E_5~0); 1205490#L922-1 assume !(1 == ~E_6~0); 1205731#L927-1 assume !(1 == ~E_7~0); 1205477#L932-1 assume { :end_inline_reset_delta_events } true; 1205478#L1178-2 [2022-12-13 12:19:33,444 INFO L750 eck$LassoCheckResult]: Loop: 1205478#L1178-2 assume !false; 1251282#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1251280#L744 assume !false; 1251278#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1251276#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1251267#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1251265#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1251262#L641 assume !(0 != eval_~tmp~0#1); 1251263#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1254244#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1254242#L769-3 assume !(0 == ~M_E~0); 1254240#L769-5 assume !(0 == ~T1_E~0); 1254238#L774-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1254236#L779-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1254234#L784-3 assume !(0 == ~T4_E~0); 1254229#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1254226#L794-3 assume !(0 == ~T6_E~0); 1254225#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1254224#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1254223#L809-3 assume !(0 == ~E_1~0); 1254222#L814-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1254221#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1215231#L824-3 assume !(0 == ~E_4~0); 1215232#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1259905#L834-3 assume !(0 == ~E_6~0); 1215388#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1215386#L844-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1215384#L376-27 assume !(1 == ~m_pc~0); 1215381#L376-29 is_master_triggered_~__retres1~0#1 := 0; 1215379#L387-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1215377#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1215375#L955-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1215373#L955-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1215371#L395-27 assume !(1 == ~t1_pc~0); 1215369#L395-29 is_transmit1_triggered_~__retres1~1#1 := 0; 1215368#L406-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1215367#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1215365#L963-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1215363#L963-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1215361#L414-27 assume !(1 == ~t2_pc~0); 1215358#L414-29 is_transmit2_triggered_~__retres1~2#1 := 0; 1215356#L425-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1215354#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1215352#L971-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1215350#L971-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1215348#L433-27 assume !(1 == ~t3_pc~0); 1215346#L433-29 is_transmit3_triggered_~__retres1~3#1 := 0; 1215344#L444-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1215342#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1215340#L979-27 assume !(0 != activate_threads_~tmp___2~0#1); 1215337#L979-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1215335#L452-27 assume !(1 == ~t4_pc~0); 1215199#L452-29 is_transmit4_triggered_~__retres1~4#1 := 0; 1215331#L463-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1215329#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1215327#L987-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1215325#L987-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1215322#L471-27 assume !(1 == ~t5_pc~0); 1215323#L471-29 is_transmit5_triggered_~__retres1~5#1 := 0; 1254227#L482-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1254212#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1254211#L995-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1254210#L995-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1254208#L490-27 assume !(1 == ~t6_pc~0); 1254206#L490-29 is_transmit6_triggered_~__retres1~6#1 := 0; 1254159#L501-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1254146#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1254143#L1003-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1215297#L1003-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1215298#L509-27 assume 1 == ~t7_pc~0; 1253636#L510-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 1253633#L520-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1253631#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1253624#L1011-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1251669#L1011-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1251660#L857-3 assume !(1 == ~M_E~0); 1249462#L857-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1251658#L862-3 assume !(1 == ~T2_E~0); 1251657#L867-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1251656#L872-3 assume !(1 == ~T4_E~0); 1251651#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1251650#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1251649#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1251648#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1251647#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1251645#L902-3 assume !(1 == ~E_2~0); 1251643#L907-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1251641#L912-3 assume !(1 == ~E_4~0); 1251638#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1251636#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1251634#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1251632#L932-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1251518#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1251511#L626-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1251508#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 1251500#L1197 assume !(0 == start_simulation_~tmp~3#1); 1251497#L1197-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1251426#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1251421#L626-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1251420#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 1251419#L1152 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1251417#L1159 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1251415#stop_simulation_returnLabel#1 start_simulation_#t~ret24#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 1251413#L1210 assume !(0 != start_simulation_~tmp___0~1#1); 1205478#L1178-2 [2022-12-13 12:19:33,444 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:19:33,444 INFO L85 PathProgramCache]: Analyzing trace with hash -281555835, now seen corresponding path program 1 times [2022-12-13 12:19:33,444 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:19:33,444 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [667072397] [2022-12-13 12:19:33,444 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:19:33,444 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:19:33,450 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:19:33,478 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:19:33,478 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:19:33,478 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [667072397] [2022-12-13 12:19:33,478 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [667072397] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:19:33,478 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:19:33,478 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:19:33,478 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1374774003] [2022-12-13 12:19:33,478 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:19:33,479 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 12:19:33,479 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:19:33,479 INFO L85 PathProgramCache]: Analyzing trace with hash -1187776023, now seen corresponding path program 1 times [2022-12-13 12:19:33,479 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:19:33,479 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [860748947] [2022-12-13 12:19:33,480 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:19:33,480 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:19:33,488 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:19:33,502 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:19:33,502 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:19:33,502 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [860748947] [2022-12-13 12:19:33,502 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [860748947] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:19:33,502 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:19:33,502 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:19:33,503 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [728916504] [2022-12-13 12:19:33,503 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:19:33,503 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:19:33,503 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:19:33,503 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 12:19:33,503 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 12:19:33,503 INFO L87 Difference]: Start difference. First operand 62099 states and 87285 transitions. cyclomatic complexity: 25202 Second operand has 4 states, 4 states have (on average 23.75) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:19:33,740 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:19:33,741 INFO L93 Difference]: Finished difference Result 77737 states and 108679 transitions. [2022-12-13 12:19:33,741 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 77737 states and 108679 transitions. [2022-12-13 12:19:33,974 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 77246 [2022-12-13 12:19:34,116 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 77737 states to 77737 states and 108679 transitions. [2022-12-13 12:19:34,116 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 77737 [2022-12-13 12:19:34,151 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 77737 [2022-12-13 12:19:34,151 INFO L73 IsDeterministic]: Start isDeterministic. Operand 77737 states and 108679 transitions. [2022-12-13 12:19:34,182 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:19:34,182 INFO L218 hiAutomatonCegarLoop]: Abstraction has 77737 states and 108679 transitions. [2022-12-13 12:19:34,216 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 77737 states and 108679 transitions. [2022-12-13 12:19:34,682 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 77737 to 54166. [2022-12-13 12:19:34,715 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 54166 states, 54166 states have (on average 1.4004726212014917) internal successors, (75858), 54165 states have internal predecessors, (75858), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:19:34,786 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 54166 states to 54166 states and 75858 transitions. [2022-12-13 12:19:34,786 INFO L240 hiAutomatonCegarLoop]: Abstraction has 54166 states and 75858 transitions. [2022-12-13 12:19:34,786 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 12:19:34,787 INFO L428 stractBuchiCegarLoop]: Abstraction has 54166 states and 75858 transitions. [2022-12-13 12:19:34,787 INFO L335 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2022-12-13 12:19:34,787 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 54166 states and 75858 transitions. [2022-12-13 12:19:34,915 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 53817 [2022-12-13 12:19:34,916 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:19:34,916 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:19:34,917 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:19:34,917 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:19:34,917 INFO L748 eck$LassoCheckResult]: Stem: 1344860#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 1344861#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 1345493#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1345494#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1345463#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 1345464#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1345112#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1344929#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1344930#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1344913#L556-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1344914#L561-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1345461#L566-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1345243#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1345244#L769 assume !(0 == ~M_E~0); 1345264#L769-2 assume !(0 == ~T1_E~0); 1345265#L774-1 assume !(0 == ~T2_E~0); 1345300#L779-1 assume !(0 == ~T3_E~0); 1345448#L784-1 assume !(0 == ~T4_E~0); 1345241#L789-1 assume !(0 == ~T5_E~0); 1345242#L794-1 assume !(0 == ~T6_E~0); 1345360#L799-1 assume !(0 == ~T7_E~0); 1345246#L804-1 assume !(0 == ~E_M~0); 1345247#L809-1 assume !(0 == ~E_1~0); 1345290#L814-1 assume !(0 == ~E_2~0); 1344659#L819-1 assume !(0 == ~E_3~0); 1344660#L824-1 assume !(0 == ~E_4~0); 1345003#L829-1 assume !(0 == ~E_5~0); 1345549#L834-1 assume !(0 == ~E_6~0); 1344789#L839-1 assume !(0 == ~E_7~0); 1344790#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1345192#L376 assume !(1 == ~m_pc~0); 1345188#L376-2 is_master_triggered_~__retres1~0#1 := 0; 1345189#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1345433#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1344731#L955 assume !(0 != activate_threads_~tmp~1#1); 1344732#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1345104#L395 assume !(1 == ~t1_pc~0); 1345266#L395-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1345436#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1344685#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1344686#L963 assume !(0 != activate_threads_~tmp___0~0#1); 1345200#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1345201#L414 assume !(1 == ~t2_pc~0); 1344792#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1344793#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1345010#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1345011#L971 assume !(0 != activate_threads_~tmp___1~0#1); 1345472#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1345109#L433 assume !(1 == ~t3_pc~0); 1344900#L433-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1344901#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1344653#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1344654#L979 assume !(0 != activate_threads_~tmp___2~0#1); 1344754#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1344755#L452 assume !(1 == ~t4_pc~0); 1344909#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1344910#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1344748#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1344749#L987 assume !(0 != activate_threads_~tmp___3~0#1); 1344939#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1344940#L471 assume !(1 == ~t5_pc~0); 1345339#L471-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1344924#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1344925#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1345437#L995 assume !(0 != activate_threads_~tmp___4~0#1); 1345535#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1345536#L490 assume !(1 == ~t6_pc~0); 1345196#L490-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1345197#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1344997#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1344998#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 1345122#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1345084#L509 assume !(1 == ~t7_pc~0); 1345085#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1344886#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1344887#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1344946#L1011 assume !(0 != activate_threads_~tmp___6~0#1); 1344947#L1011-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1345481#L857 assume !(1 == ~M_E~0); 1344736#L857-2 assume !(1 == ~T1_E~0); 1344737#L862-1 assume !(1 == ~T2_E~0); 1345014#L867-1 assume !(1 == ~T3_E~0); 1345019#L872-1 assume !(1 == ~T4_E~0); 1345110#L877-1 assume !(1 == ~T5_E~0); 1345317#L882-1 assume !(1 == ~T6_E~0); 1345499#L887-1 assume !(1 == ~T7_E~0); 1345389#L892-1 assume !(1 == ~E_M~0); 1345390#L897-1 assume !(1 == ~E_1~0); 1345038#L902-1 assume !(1 == ~E_2~0); 1345039#L907-1 assume !(1 == ~E_3~0); 1345331#L912-1 assume !(1 == ~E_4~0); 1345323#L917-1 assume !(1 == ~E_5~0); 1345324#L922-1 assume !(1 == ~E_6~0); 1345553#L927-1 assume !(1 == ~E_7~0); 1345312#L932-1 assume { :end_inline_reset_delta_events } true; 1345313#L1178-2 [2022-12-13 12:19:34,917 INFO L750 eck$LassoCheckResult]: Loop: 1345313#L1178-2 assume !false; 1362523#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1362505#L744 assume !false; 1362500#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1362213#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1362204#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1362201#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1362198#L641 assume !(0 != eval_~tmp~0#1); 1362196#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1362194#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1362182#L769-3 assume !(0 == ~M_E~0); 1362173#L769-5 assume !(0 == ~T1_E~0); 1362163#L774-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1362153#L779-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1362148#L784-3 assume !(0 == ~T4_E~0); 1362142#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1362137#L794-3 assume !(0 == ~T6_E~0); 1362132#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1362127#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1362121#L809-3 assume !(0 == ~E_1~0); 1362116#L814-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1362112#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1362107#L824-3 assume !(0 == ~E_4~0); 1362101#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1362096#L834-3 assume !(0 == ~E_6~0); 1362092#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1362086#L844-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1362081#L376-27 assume !(1 == ~m_pc~0); 1362075#L376-29 is_master_triggered_~__retres1~0#1 := 0; 1362070#L387-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1362064#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1362059#L955-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1362054#L955-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1362049#L395-27 assume !(1 == ~t1_pc~0); 1362043#L395-29 is_transmit1_triggered_~__retres1~1#1 := 0; 1362038#L406-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1362033#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1362028#L963-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1362023#L963-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1361933#L414-27 assume !(1 == ~t2_pc~0); 1361900#L414-29 is_transmit2_triggered_~__retres1~2#1 := 0; 1361894#L425-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1361888#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1361882#L971-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1361798#L971-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1361795#L433-27 assume !(1 == ~t3_pc~0); 1361793#L433-29 is_transmit3_triggered_~__retres1~3#1 := 0; 1361791#L444-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1361790#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1361788#L979-27 assume !(0 != activate_threads_~tmp___2~0#1); 1361786#L979-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1361784#L452-27 assume !(1 == ~t4_pc~0); 1361781#L452-29 is_transmit4_triggered_~__retres1~4#1 := 0; 1361779#L463-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1361777#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1361775#L987-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1361773#L987-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1361771#L471-27 assume !(1 == ~t5_pc~0); 1361769#L471-29 is_transmit5_triggered_~__retres1~5#1 := 0; 1361767#L482-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1361765#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1361763#L995-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1361732#L995-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1361713#L490-27 assume !(1 == ~t6_pc~0); 1361712#L490-29 is_transmit6_triggered_~__retres1~6#1 := 0; 1361711#L501-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1361710#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1361709#L1003-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1361708#L1003-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1361707#L509-27 assume !(1 == ~t7_pc~0); 1361704#L509-29 is_transmit7_triggered_~__retres1~7#1 := 0; 1361695#L520-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1361693#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1361691#L1011-27 assume !(0 != activate_threads_~tmp___6~0#1); 1361688#L1011-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1361686#L857-3 assume !(1 == ~M_E~0); 1354599#L857-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1361681#L862-3 assume !(1 == ~T2_E~0); 1361679#L867-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1361677#L872-3 assume !(1 == ~T4_E~0); 1361675#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1361672#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1361670#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1361668#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1361667#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1361665#L902-3 assume !(1 == ~E_2~0); 1361663#L907-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1361661#L912-3 assume !(1 == ~E_4~0); 1361659#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1361657#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1361643#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1361637#L932-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1358154#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1358148#L626-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1358146#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 1354637#L1197 assume !(0 == start_simulation_~tmp~3#1); 1354638#L1197-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1362616#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1362602#L626-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1362584#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 1362572#L1152 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1362563#L1159 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1362543#stop_simulation_returnLabel#1 start_simulation_#t~ret24#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 1362536#L1210 assume !(0 != start_simulation_~tmp___0~1#1); 1345313#L1178-2 [2022-12-13 12:19:34,917 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:19:34,917 INFO L85 PathProgramCache]: Analyzing trace with hash 1628748997, now seen corresponding path program 1 times [2022-12-13 12:19:34,918 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:19:34,918 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [66325670] [2022-12-13 12:19:34,918 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:19:34,918 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:19:34,925 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 12:19:34,925 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 12:19:34,930 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 12:19:34,971 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 12:19:34,971 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:19:34,971 INFO L85 PathProgramCache]: Analyzing trace with hash 565272940, now seen corresponding path program 1 times [2022-12-13 12:19:34,971 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:19:34,971 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [320427352] [2022-12-13 12:19:34,971 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:19:34,971 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:19:34,977 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:19:34,992 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:19:34,992 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:19:34,992 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [320427352] [2022-12-13 12:19:34,992 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [320427352] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:19:34,992 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:19:34,992 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:19:34,992 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [896850282] [2022-12-13 12:19:34,992 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:19:34,993 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:19:34,993 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:19:34,993 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 12:19:34,993 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 12:19:34,993 INFO L87 Difference]: Start difference. First operand 54166 states and 75858 transitions. cyclomatic complexity: 21708 Second operand has 3 states, 3 states have (on average 34.666666666666664) internal successors, (104), 3 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:19:35,263 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:19:35,264 INFO L93 Difference]: Finished difference Result 62099 states and 86740 transitions. [2022-12-13 12:19:35,264 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 62099 states and 86740 transitions. [2022-12-13 12:19:35,432 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 61679 [2022-12-13 12:19:35,530 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 62099 states to 62099 states and 86740 transitions. [2022-12-13 12:19:35,530 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 62099 [2022-12-13 12:19:35,551 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 62099 [2022-12-13 12:19:35,551 INFO L73 IsDeterministic]: Start isDeterministic. Operand 62099 states and 86740 transitions. [2022-12-13 12:19:35,572 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:19:35,572 INFO L218 hiAutomatonCegarLoop]: Abstraction has 62099 states and 86740 transitions. [2022-12-13 12:19:35,594 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 62099 states and 86740 transitions. [2022-12-13 12:19:35,921 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 62099 to 62099. [2022-12-13 12:19:35,959 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 62099 states, 62099 states have (on average 1.3968018808676468) internal successors, (86740), 62098 states have internal predecessors, (86740), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:19:36,059 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 62099 states to 62099 states and 86740 transitions. [2022-12-13 12:19:36,059 INFO L240 hiAutomatonCegarLoop]: Abstraction has 62099 states and 86740 transitions. [2022-12-13 12:19:36,060 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 12:19:36,060 INFO L428 stractBuchiCegarLoop]: Abstraction has 62099 states and 86740 transitions. [2022-12-13 12:19:36,060 INFO L335 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2022-12-13 12:19:36,060 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 62099 states and 86740 transitions. [2022-12-13 12:19:36,303 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 61679 [2022-12-13 12:19:36,303 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:19:36,303 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:19:36,304 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:19:36,304 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:19:36,304 INFO L748 eck$LassoCheckResult]: Stem: 1461131#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 1461132#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 1461795#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1461796#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1461759#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 1461760#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1461381#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1461197#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1461198#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1461182#L556-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1461183#L561-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1461758#L566-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1461523#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1461524#L769 assume !(0 == ~M_E~0); 1461546#L769-2 assume !(0 == ~T1_E~0); 1461547#L774-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1461587#L779-1 assume !(0 == ~T3_E~0); 1461740#L784-1 assume !(0 == ~T4_E~0); 1461741#L789-1 assume !(0 == ~T5_E~0); 1461980#L794-1 assume !(0 == ~T6_E~0); 1461979#L799-1 assume !(0 == ~T7_E~0); 1461526#L804-1 assume !(0 == ~E_M~0); 1461527#L809-1 assume !(0 == ~E_1~0); 1461579#L814-1 assume !(0 == ~E_2~0); 1460928#L819-1 assume !(0 == ~E_3~0); 1460929#L824-1 assume !(0 == ~E_4~0); 1461939#L829-1 assume !(0 == ~E_5~0); 1461940#L834-1 assume !(0 == ~E_6~0); 1461058#L839-1 assume !(0 == ~E_7~0); 1461059#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1461655#L376 assume !(1 == ~m_pc~0); 1461460#L376-2 is_master_triggered_~__retres1~0#1 := 0; 1461461#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1461720#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1461721#L955 assume !(0 != activate_threads_~tmp~1#1); 1461976#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1461548#L395 assume !(1 == ~t1_pc~0); 1461549#L395-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1461742#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1461743#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1461781#L963 assume !(0 != activate_threads_~tmp___0~0#1); 1461782#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1461975#L414 assume !(1 == ~t2_pc~0); 1461061#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1461062#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1461944#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1461765#L971 assume !(0 != activate_threads_~tmp___1~0#1); 1461766#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1461972#L433 assume !(1 == ~t3_pc~0); 1461971#L433-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1461866#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1460924#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1460925#L979 assume !(0 != activate_threads_~tmp___2~0#1); 1461969#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1461967#L452 assume !(1 == ~t4_pc~0); 1461178#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1461179#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1461966#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1461864#L987 assume !(0 != activate_threads_~tmp___3~0#1); 1461865#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1461965#L471 assume !(1 == ~t5_pc~0); 1461883#L471-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1461884#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1461726#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1461727#L995 assume !(0 != activate_threads_~tmp___4~0#1); 1461943#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1461892#L490 assume !(1 == ~t6_pc~0); 1461893#L490-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1461509#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1461510#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1461516#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 1461517#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1461963#L509 assume !(1 == ~t7_pc~0); 1461770#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1461771#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1461974#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1461215#L1011 assume !(0 != activate_threads_~tmp___6~0#1); 1461216#L1011-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1461778#L857 assume !(1 == ~M_E~0); 1461006#L857-2 assume !(1 == ~T1_E~0); 1461007#L862-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1461284#L867-1 assume !(1 == ~T3_E~0); 1461289#L872-1 assume !(1 == ~T4_E~0); 1461379#L877-1 assume !(1 == ~T5_E~0); 1461607#L882-1 assume !(1 == ~T6_E~0); 1461804#L887-1 assume !(1 == ~T7_E~0); 1461678#L892-1 assume !(1 == ~E_M~0); 1461679#L897-1 assume !(1 == ~E_1~0); 1461307#L902-1 assume !(1 == ~E_2~0); 1461308#L907-1 assume !(1 == ~E_3~0); 1461621#L912-1 assume !(1 == ~E_4~0); 1461613#L917-1 assume !(1 == ~E_5~0); 1461614#L922-1 assume !(1 == ~E_6~0); 1461854#L927-1 assume !(1 == ~E_7~0); 1461602#L932-1 assume { :end_inline_reset_delta_events } true; 1461603#L1178-2 [2022-12-13 12:19:36,305 INFO L750 eck$LassoCheckResult]: Loop: 1461603#L1178-2 assume !false; 1487307#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1487296#L744 assume !false; 1487297#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1487229#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1487222#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1487215#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1487216#L641 assume !(0 != eval_~tmp~0#1); 1495162#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1495161#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1495160#L769-3 assume !(0 == ~M_E~0); 1495159#L769-5 assume !(0 == ~T1_E~0); 1495158#L774-3 assume !(0 == ~T2_E~0); 1495156#L779-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1495154#L784-3 assume !(0 == ~T4_E~0); 1495152#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1495150#L794-3 assume !(0 == ~T6_E~0); 1495148#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1495146#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1495144#L809-3 assume !(0 == ~E_1~0); 1495142#L814-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1495140#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1495138#L824-3 assume !(0 == ~E_4~0); 1495136#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1495134#L834-3 assume !(0 == ~E_6~0); 1495132#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1495130#L844-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1495128#L376-27 assume !(1 == ~m_pc~0); 1495126#L376-29 is_master_triggered_~__retres1~0#1 := 0; 1495124#L387-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1495122#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1495120#L955-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1495118#L955-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1495116#L395-27 assume !(1 == ~t1_pc~0); 1495114#L395-29 is_transmit1_triggered_~__retres1~1#1 := 0; 1495112#L406-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1495110#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1495108#L963-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1495106#L963-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1495104#L414-27 assume !(1 == ~t2_pc~0); 1495100#L414-29 is_transmit2_triggered_~__retres1~2#1 := 0; 1495098#L425-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1495096#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1495094#L971-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1495092#L971-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1495090#L433-27 assume !(1 == ~t3_pc~0); 1495088#L433-29 is_transmit3_triggered_~__retres1~3#1 := 0; 1495086#L444-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1495084#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1495082#L979-27 assume !(0 != activate_threads_~tmp___2~0#1); 1495080#L979-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1495077#L452-27 assume !(1 == ~t4_pc~0); 1495074#L452-29 is_transmit4_triggered_~__retres1~4#1 := 0; 1495072#L463-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1495070#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1495068#L987-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1495066#L987-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1495064#L471-27 assume !(1 == ~t5_pc~0); 1495061#L471-29 is_transmit5_triggered_~__retres1~5#1 := 0; 1495058#L482-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1495055#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1495052#L995-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1495048#L995-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1495044#L490-27 assume !(1 == ~t6_pc~0); 1495040#L490-29 is_transmit6_triggered_~__retres1~6#1 := 0; 1495036#L501-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1495032#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1495028#L1003-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1495024#L1003-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1495020#L509-27 assume 1 == ~t7_pc~0; 1495014#L510-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 1495008#L520-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1495002#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1494996#L1011-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1494992#L1011-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1494988#L857-3 assume !(1 == ~M_E~0); 1494767#L857-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1494982#L862-3 assume !(1 == ~T2_E~0); 1494979#L867-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1494976#L872-3 assume !(1 == ~T4_E~0); 1494973#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1494970#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1494967#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1494964#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1494961#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1494958#L902-3 assume !(1 == ~E_2~0); 1494955#L907-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1494952#L912-3 assume !(1 == ~E_4~0); 1494949#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1494944#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1494941#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1494938#L932-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1494932#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1494925#L626-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1494922#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 1494918#L1197 assume !(0 == start_simulation_~tmp~3#1); 1494919#L1197-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1522560#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1522555#L626-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1520532#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 1517999#L1152 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1512477#L1159 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1487317#stop_simulation_returnLabel#1 start_simulation_#t~ret24#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 1487318#L1210 assume !(0 != start_simulation_~tmp___0~1#1); 1461603#L1178-2 [2022-12-13 12:19:36,305 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:19:36,305 INFO L85 PathProgramCache]: Analyzing trace with hash -243852155, now seen corresponding path program 1 times [2022-12-13 12:19:36,305 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:19:36,305 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1833006090] [2022-12-13 12:19:36,305 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:19:36,306 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:19:36,316 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:19:36,356 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:19:36,357 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:19:36,357 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1833006090] [2022-12-13 12:19:36,357 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1833006090] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:19:36,357 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:19:36,357 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:19:36,357 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [479871304] [2022-12-13 12:19:36,357 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:19:36,358 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 12:19:36,358 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:19:36,358 INFO L85 PathProgramCache]: Analyzing trace with hash -1216276313, now seen corresponding path program 1 times [2022-12-13 12:19:36,358 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:19:36,358 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1831979265] [2022-12-13 12:19:36,358 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:19:36,358 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:19:36,367 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:19:36,388 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:19:36,388 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:19:36,388 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1831979265] [2022-12-13 12:19:36,388 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1831979265] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:19:36,389 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:19:36,389 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:19:36,389 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1254812564] [2022-12-13 12:19:36,389 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:19:36,389 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:19:36,389 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:19:36,390 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 12:19:36,390 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 12:19:36,390 INFO L87 Difference]: Start difference. First operand 62099 states and 86740 transitions. cyclomatic complexity: 24657 Second operand has 4 states, 4 states have (on average 23.75) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:19:36,636 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:19:36,636 INFO L93 Difference]: Finished difference Result 78788 states and 109924 transitions. [2022-12-13 12:19:36,636 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 78788 states and 109924 transitions. [2022-12-13 12:19:36,933 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 78301 [2022-12-13 12:19:37,116 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 78788 states to 78788 states and 109924 transitions. [2022-12-13 12:19:37,116 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 78788 [2022-12-13 12:19:37,153 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 78788 [2022-12-13 12:19:37,153 INFO L73 IsDeterministic]: Start isDeterministic. Operand 78788 states and 109924 transitions. [2022-12-13 12:19:37,186 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:19:37,186 INFO L218 hiAutomatonCegarLoop]: Abstraction has 78788 states and 109924 transitions. [2022-12-13 12:19:37,220 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 78788 states and 109924 transitions. [2022-12-13 12:19:37,684 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 78788 to 54166. [2022-12-13 12:19:37,717 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 54166 states, 54166 states have (on average 1.3984602887420152) internal successors, (75749), 54165 states have internal predecessors, (75749), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:19:37,955 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 54166 states to 54166 states and 75749 transitions. [2022-12-13 12:19:37,955 INFO L240 hiAutomatonCegarLoop]: Abstraction has 54166 states and 75749 transitions. [2022-12-13 12:19:37,956 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 12:19:37,956 INFO L428 stractBuchiCegarLoop]: Abstraction has 54166 states and 75749 transitions. [2022-12-13 12:19:37,956 INFO L335 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2022-12-13 12:19:37,956 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 54166 states and 75749 transitions. [2022-12-13 12:19:38,072 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 53817 [2022-12-13 12:19:38,072 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:19:38,072 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:19:38,074 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:19:38,074 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:19:38,074 INFO L748 eck$LassoCheckResult]: Stem: 1602027#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 1602028#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 1602669#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1602670#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1602642#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 1602643#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1602277#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1602094#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1602095#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1602079#L556-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1602080#L561-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1602640#L566-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1602415#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1602416#L769 assume !(0 == ~M_E~0); 1602438#L769-2 assume !(0 == ~T1_E~0); 1602439#L774-1 assume !(0 == ~T2_E~0); 1602472#L779-1 assume !(0 == ~T3_E~0); 1602628#L784-1 assume !(0 == ~T4_E~0); 1602413#L789-1 assume !(0 == ~T5_E~0); 1602414#L794-1 assume !(0 == ~T6_E~0); 1602543#L799-1 assume !(0 == ~T7_E~0); 1602418#L804-1 assume !(0 == ~E_M~0); 1602419#L809-1 assume !(0 == ~E_1~0); 1602465#L814-1 assume !(0 == ~E_2~0); 1601827#L819-1 assume !(0 == ~E_3~0); 1601828#L824-1 assume !(0 == ~E_4~0); 1602168#L829-1 assume !(0 == ~E_5~0); 1602722#L834-1 assume !(0 == ~E_6~0); 1601956#L839-1 assume !(0 == ~E_7~0); 1601957#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1602359#L376 assume !(1 == ~m_pc~0); 1602355#L376-2 is_master_triggered_~__retres1~0#1 := 0; 1602356#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1602610#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1601900#L955 assume !(0 != activate_threads_~tmp~1#1); 1601901#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1602269#L395 assume !(1 == ~t1_pc~0); 1602440#L395-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1602614#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1601853#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1601854#L963 assume !(0 != activate_threads_~tmp___0~0#1); 1602366#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1602367#L414 assume !(1 == ~t2_pc~0); 1601959#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1601960#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1602176#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1602177#L971 assume !(0 != activate_threads_~tmp___1~0#1); 1602649#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1602274#L433 assume !(1 == ~t3_pc~0); 1602069#L433-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1602070#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1601821#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1601822#L979 assume !(0 != activate_threads_~tmp___2~0#1); 1601922#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1601923#L452 assume !(1 == ~t4_pc~0); 1602075#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1602076#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1601916#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1601917#L987 assume !(0 != activate_threads_~tmp___3~0#1); 1602104#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1602105#L471 assume !(1 == ~t5_pc~0); 1602520#L471-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1602089#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1602090#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1602615#L995 assume !(0 != activate_threads_~tmp___4~0#1); 1602708#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1602709#L490 assume !(1 == ~t6_pc~0); 1602363#L490-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1602364#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1602162#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1602163#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 1602286#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1602250#L509 assume !(1 == ~t7_pc~0); 1602251#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1602054#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1602055#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1602111#L1011 assume !(0 != activate_threads_~tmp___6~0#1); 1602112#L1011-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1602658#L857 assume !(1 == ~M_E~0); 1601905#L857-2 assume !(1 == ~T1_E~0); 1601906#L862-1 assume !(1 == ~T2_E~0); 1602180#L867-1 assume !(1 == ~T3_E~0); 1602185#L872-1 assume !(1 == ~T4_E~0); 1602275#L877-1 assume !(1 == ~T5_E~0); 1602490#L882-1 assume !(1 == ~T6_E~0); 1602675#L887-1 assume !(1 == ~T7_E~0); 1602566#L892-1 assume !(1 == ~E_M~0); 1602567#L897-1 assume !(1 == ~E_1~0); 1602204#L902-1 assume !(1 == ~E_2~0); 1602205#L907-1 assume !(1 == ~E_3~0); 1602510#L912-1 assume !(1 == ~E_4~0); 1602498#L917-1 assume !(1 == ~E_5~0); 1602499#L922-1 assume !(1 == ~E_6~0); 1602725#L927-1 assume !(1 == ~E_7~0); 1602485#L932-1 assume { :end_inline_reset_delta_events } true; 1602486#L1178-2 [2022-12-13 12:19:38,074 INFO L750 eck$LassoCheckResult]: Loop: 1602486#L1178-2 assume !false; 1634559#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1634557#L744 assume !false; 1634555#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1634553#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1634542#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1634539#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1634527#L641 assume !(0 != eval_~tmp~0#1); 1634528#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1643345#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1643343#L769-3 assume !(0 == ~M_E~0); 1643341#L769-5 assume !(0 == ~T1_E~0); 1643339#L774-3 assume !(0 == ~T2_E~0); 1643337#L779-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1643335#L784-3 assume !(0 == ~T4_E~0); 1643333#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1643331#L794-3 assume !(0 == ~T6_E~0); 1643329#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1643327#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1643325#L809-3 assume !(0 == ~E_1~0); 1643323#L814-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1643321#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1643318#L824-3 assume !(0 == ~E_4~0); 1643316#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1643314#L834-3 assume !(0 == ~E_6~0); 1643312#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1643310#L844-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1643308#L376-27 assume !(1 == ~m_pc~0); 1643307#L376-29 is_master_triggered_~__retres1~0#1 := 0; 1643305#L387-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1643303#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1643301#L955-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1643299#L955-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1643297#L395-27 assume !(1 == ~t1_pc~0); 1643294#L395-29 is_transmit1_triggered_~__retres1~1#1 := 0; 1643292#L406-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1643290#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1643288#L963-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1643286#L963-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1643284#L414-27 assume 1 == ~t2_pc~0; 1643283#L415-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1643280#L425-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1643278#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1643276#L971-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1643274#L971-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1643271#L433-27 assume !(1 == ~t3_pc~0); 1643269#L433-29 is_transmit3_triggered_~__retres1~3#1 := 0; 1643267#L444-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1643265#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1643263#L979-27 assume !(0 != activate_threads_~tmp___2~0#1); 1643261#L979-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1643259#L452-27 assume !(1 == ~t4_pc~0); 1643256#L452-29 is_transmit4_triggered_~__retres1~4#1 := 0; 1643254#L463-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1643252#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1643250#L987-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1643248#L987-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1643246#L471-27 assume !(1 == ~t5_pc~0); 1643245#L471-29 is_transmit5_triggered_~__retres1~5#1 := 0; 1643242#L482-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1643240#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1643238#L995-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1643236#L995-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1643234#L490-27 assume !(1 == ~t6_pc~0); 1643230#L490-29 is_transmit6_triggered_~__retres1~6#1 := 0; 1643228#L501-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1643226#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1643224#L1003-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1643221#L1003-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1643219#L509-27 assume !(1 == ~t7_pc~0); 1643215#L509-29 is_transmit7_triggered_~__retres1~7#1 := 0; 1643214#L520-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1643212#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1643210#L1011-27 assume !(0 != activate_threads_~tmp___6~0#1); 1643207#L1011-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1643205#L857-3 assume !(1 == ~M_E~0); 1616288#L857-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1643202#L862-3 assume !(1 == ~T2_E~0); 1643200#L867-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1643198#L872-3 assume !(1 == ~T4_E~0); 1643196#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1643194#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1643192#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1643190#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1643188#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1643186#L902-3 assume !(1 == ~E_2~0); 1643184#L907-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1643183#L912-3 assume !(1 == ~E_4~0); 1643182#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1643181#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1643180#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1643179#L932-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1643175#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1643170#L626-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1643161#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 1616438#L1197 assume !(0 == start_simulation_~tmp~3#1); 1616439#L1197-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1634646#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1634637#L626-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1634631#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 1634625#L1152 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1634619#L1159 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1634612#stop_simulation_returnLabel#1 start_simulation_#t~ret24#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 1634606#L1210 assume !(0 != start_simulation_~tmp___0~1#1); 1602486#L1178-2 [2022-12-13 12:19:38,075 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:19:38,075 INFO L85 PathProgramCache]: Analyzing trace with hash 1628748997, now seen corresponding path program 2 times [2022-12-13 12:19:38,075 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:19:38,075 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2140341827] [2022-12-13 12:19:38,075 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:19:38,075 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:19:38,085 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 12:19:38,085 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 12:19:38,090 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 12:19:38,111 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 12:19:38,112 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:19:38,112 INFO L85 PathProgramCache]: Analyzing trace with hash 159129833, now seen corresponding path program 1 times [2022-12-13 12:19:38,112 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:19:38,112 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1944189461] [2022-12-13 12:19:38,112 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:19:38,112 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:19:38,118 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:19:38,131 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:19:38,131 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:19:38,132 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1944189461] [2022-12-13 12:19:38,132 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1944189461] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:19:38,132 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:19:38,132 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:19:38,132 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1900725878] [2022-12-13 12:19:38,132 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:19:38,132 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:19:38,132 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:19:38,133 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 12:19:38,133 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 12:19:38,133 INFO L87 Difference]: Start difference. First operand 54166 states and 75749 transitions. cyclomatic complexity: 21599 Second operand has 3 states, 3 states have (on average 34.666666666666664) internal successors, (104), 3 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:19:38,387 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:19:38,387 INFO L93 Difference]: Finished difference Result 101010 states and 139464 transitions. [2022-12-13 12:19:38,387 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 101010 states and 139464 transitions. [2022-12-13 12:19:38,824 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 100342 [2022-12-13 12:19:38,978 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 101010 states to 101010 states and 139464 transitions. [2022-12-13 12:19:38,979 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 101010 [2022-12-13 12:19:39,012 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 101010 [2022-12-13 12:19:39,013 INFO L73 IsDeterministic]: Start isDeterministic. Operand 101010 states and 139464 transitions. [2022-12-13 12:19:39,043 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:19:39,043 INFO L218 hiAutomatonCegarLoop]: Abstraction has 101010 states and 139464 transitions. [2022-12-13 12:19:39,075 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 101010 states and 139464 transitions. [2022-12-13 12:19:39,637 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 101010 to 100974. [2022-12-13 12:19:39,695 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 100974 states, 100974 states have (on average 1.3808307088953593) internal successors, (139428), 100973 states have internal predecessors, (139428), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:19:39,973 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 100974 states to 100974 states and 139428 transitions. [2022-12-13 12:19:39,973 INFO L240 hiAutomatonCegarLoop]: Abstraction has 100974 states and 139428 transitions. [2022-12-13 12:19:39,974 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 12:19:39,974 INFO L428 stractBuchiCegarLoop]: Abstraction has 100974 states and 139428 transitions. [2022-12-13 12:19:39,974 INFO L335 stractBuchiCegarLoop]: ======== Iteration 23 ============ [2022-12-13 12:19:39,974 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 100974 states and 139428 transitions. [2022-12-13 12:19:40,183 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 100306 [2022-12-13 12:19:40,183 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:19:40,183 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:19:40,184 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:19:40,184 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:19:40,185 INFO L748 eck$LassoCheckResult]: Stem: 1757205#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 1757206#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 1757873#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1757874#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1757839#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 1757840#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1757463#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1757274#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1757275#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1757259#L556-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1757260#L561-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1757838#L566-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1757605#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1757606#L769 assume !(0 == ~M_E~0); 1757628#L769-2 assume !(0 == ~T1_E~0); 1757629#L774-1 assume !(0 == ~T2_E~0); 1757661#L779-1 assume !(0 == ~T3_E~0); 1757818#L784-1 assume !(0 == ~T4_E~0); 1757602#L789-1 assume !(0 == ~T5_E~0); 1757603#L794-1 assume !(0 == ~T6_E~0); 1757725#L799-1 assume !(0 == ~T7_E~0); 1757608#L804-1 assume !(0 == ~E_M~0); 1757609#L809-1 assume !(0 == ~E_1~0); 1757653#L814-1 assume 0 == ~E_2~0;~E_2~0 := 1; 1757851#L819-1 assume !(0 == ~E_3~0); 1757348#L824-1 assume !(0 == ~E_4~0); 1757349#L829-1 assume !(0 == ~E_5~0); 1758021#L834-1 assume !(0 == ~E_6~0); 1757136#L839-1 assume !(0 == ~E_7~0); 1757137#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1757732#L376 assume !(1 == ~m_pc~0); 1757542#L376-2 is_master_triggered_~__retres1~0#1 := 0; 1757543#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1758061#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1757078#L955 assume !(0 != activate_threads_~tmp~1#1); 1757079#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1757456#L395 assume !(1 == ~t1_pc~0); 1758059#L395-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1757819#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1757820#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1757863#L963 assume !(0 != activate_threads_~tmp___0~0#1); 1757864#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1758058#L414 assume !(1 == ~t2_pc~0); 1757849#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1757139#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1757357#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1757358#L971 assume !(0 != activate_threads_~tmp___1~0#1); 1757938#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1757460#L433 assume !(1 == ~t3_pc~0); 1757246#L433-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1757247#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1758068#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1757785#L979 assume !(0 != activate_threads_~tmp___2~0#1); 1757103#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1757104#L452 assume !(1 == ~t4_pc~0); 1757255#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1757256#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1757097#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1757098#L987 assume !(0 != activate_threads_~tmp___3~0#1); 1757284#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1757285#L471 assume !(1 == ~t5_pc~0); 1757705#L471-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1757269#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1757270#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1758064#L995 assume !(0 != activate_threads_~tmp___4~0#1); 1757917#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1757918#L490 assume !(1 == ~t6_pc~0); 1757550#L490-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1757551#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1757342#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1757343#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 1757469#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1757438#L509 assume !(1 == ~t7_pc~0); 1757439#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1757226#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1757227#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1757291#L1011 assume !(0 != activate_threads_~tmp___6~0#1); 1757292#L1011-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1757860#L857 assume !(1 == ~M_E~0); 1757085#L857-2 assume !(1 == ~T1_E~0); 1757086#L862-1 assume !(1 == ~T2_E~0); 1757361#L867-1 assume !(1 == ~T3_E~0); 1757366#L872-1 assume !(1 == ~T4_E~0); 1757461#L877-1 assume !(1 == ~T5_E~0); 1757684#L882-1 assume !(1 == ~T6_E~0); 1757881#L887-1 assume !(1 == ~T7_E~0); 1757754#L892-1 assume !(1 == ~E_M~0); 1757755#L897-1 assume !(1 == ~E_1~0); 1757383#L902-1 assume 1 == ~E_2~0;~E_2~0 := 2; 1757384#L907-1 assume !(1 == ~E_3~0); 1757698#L912-1 assume !(1 == ~E_4~0); 1757690#L917-1 assume !(1 == ~E_5~0); 1757691#L922-1 assume !(1 == ~E_6~0); 1757936#L927-1 assume !(1 == ~E_7~0); 1757679#L932-1 assume { :end_inline_reset_delta_events } true; 1757680#L1178-2 [2022-12-13 12:19:40,185 INFO L750 eck$LassoCheckResult]: Loop: 1757680#L1178-2 assume !false; 1806867#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1806866#L744 assume !false; 1806865#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1806856#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1806847#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1806845#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1806841#L641 assume !(0 != eval_~tmp~0#1); 1806839#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1806837#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1806835#L769-3 assume !(0 == ~M_E~0); 1806833#L769-5 assume !(0 == ~T1_E~0); 1806831#L774-3 assume !(0 == ~T2_E~0); 1806829#L779-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1806827#L784-3 assume !(0 == ~T4_E~0); 1806825#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1806823#L794-3 assume !(0 == ~T6_E~0); 1806821#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1806819#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1806817#L809-3 assume !(0 == ~E_1~0); 1806815#L814-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1806814#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1806812#L824-3 assume !(0 == ~E_4~0); 1806810#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1806808#L834-3 assume !(0 == ~E_6~0); 1806806#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1806804#L844-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1806802#L376-27 assume !(1 == ~m_pc~0); 1806800#L376-29 is_master_triggered_~__retres1~0#1 := 0; 1806798#L387-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1806796#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1806794#L955-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1806792#L955-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1806790#L395-27 assume !(1 == ~t1_pc~0); 1806788#L395-29 is_transmit1_triggered_~__retres1~1#1 := 0; 1806786#L406-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1806784#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1806782#L963-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1806780#L963-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1806778#L414-27 assume 1 == ~t2_pc~0; 1806774#L415-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1806771#L425-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1806769#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1806767#L971-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1806765#L971-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1806763#L433-27 assume !(1 == ~t3_pc~0); 1806761#L433-29 is_transmit3_triggered_~__retres1~3#1 := 0; 1806759#L444-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1806757#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1806755#L979-27 assume !(0 != activate_threads_~tmp___2~0#1); 1806753#L979-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1806750#L452-27 assume !(1 == ~t4_pc~0); 1806747#L452-29 is_transmit4_triggered_~__retres1~4#1 := 0; 1806745#L463-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1806743#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1806741#L987-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1806739#L987-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1806737#L471-27 assume !(1 == ~t5_pc~0); 1806735#L471-29 is_transmit5_triggered_~__retres1~5#1 := 0; 1806733#L482-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1806731#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1806729#L995-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1806727#L995-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1806725#L490-27 assume !(1 == ~t6_pc~0); 1806723#L490-29 is_transmit6_triggered_~__retres1~6#1 := 0; 1806721#L501-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1806719#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1806717#L1003-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1806715#L1003-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1806711#L509-27 assume !(1 == ~t7_pc~0); 1806707#L509-29 is_transmit7_triggered_~__retres1~7#1 := 0; 1806705#L520-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1806703#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1806700#L1011-27 assume !(0 != activate_threads_~tmp___6~0#1); 1806697#L1011-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1806695#L857-3 assume !(1 == ~M_E~0); 1806524#L857-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1806693#L862-3 assume !(1 == ~T2_E~0); 1806691#L867-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1806689#L872-3 assume !(1 == ~T4_E~0); 1806687#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1806685#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1806683#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1806681#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1806679#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1806678#L902-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1806676#L907-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1806675#L912-3 assume !(1 == ~E_4~0); 1806674#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1806673#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1806672#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1806671#L932-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1806497#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1806491#L626-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1806489#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 1806486#L1197 assume !(0 == start_simulation_~tmp~3#1); 1806487#L1197-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1809935#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1809929#L626-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1809927#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 1809926#L1152 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1809925#L1159 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1806877#stop_simulation_returnLabel#1 start_simulation_#t~ret24#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 1806873#L1210 assume !(0 != start_simulation_~tmp___0~1#1); 1757680#L1178-2 [2022-12-13 12:19:40,185 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:19:40,185 INFO L85 PathProgramCache]: Analyzing trace with hash -223159163, now seen corresponding path program 1 times [2022-12-13 12:19:40,185 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:19:40,185 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [265526276] [2022-12-13 12:19:40,186 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:19:40,186 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:19:40,191 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:19:40,211 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:19:40,211 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:19:40,211 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [265526276] [2022-12-13 12:19:40,211 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [265526276] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:19:40,211 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:19:40,211 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-12-13 12:19:40,211 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1833769564] [2022-12-13 12:19:40,212 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:19:40,212 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 12:19:40,212 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:19:40,212 INFO L85 PathProgramCache]: Analyzing trace with hash 1848073575, now seen corresponding path program 1 times [2022-12-13 12:19:40,212 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:19:40,212 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [312956216] [2022-12-13 12:19:40,213 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:19:40,213 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:19:40,219 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:19:40,245 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:19:40,245 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:19:40,245 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [312956216] [2022-12-13 12:19:40,245 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [312956216] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:19:40,245 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:19:40,245 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-12-13 12:19:40,245 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2033144749] [2022-12-13 12:19:40,245 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:19:40,246 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:19:40,246 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:19:40,246 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 12:19:40,246 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 12:19:40,246 INFO L87 Difference]: Start difference. First operand 100974 states and 139428 transitions. cyclomatic complexity: 38470 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 2 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:19:40,389 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:19:40,389 INFO L93 Difference]: Finished difference Result 54166 states and 74742 transitions. [2022-12-13 12:19:40,389 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 54166 states and 74742 transitions. [2022-12-13 12:19:40,559 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 53817 [2022-12-13 12:19:40,663 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 54166 states to 54166 states and 74742 transitions. [2022-12-13 12:19:40,663 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 54166 [2022-12-13 12:19:40,688 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 54166 [2022-12-13 12:19:40,688 INFO L73 IsDeterministic]: Start isDeterministic. Operand 54166 states and 74742 transitions. [2022-12-13 12:19:40,710 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:19:40,710 INFO L218 hiAutomatonCegarLoop]: Abstraction has 54166 states and 74742 transitions. [2022-12-13 12:19:40,734 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 54166 states and 74742 transitions. [2022-12-13 12:19:41,265 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 54166 to 54166. [2022-12-13 12:19:41,298 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 54166 states, 54166 states have (on average 1.3798692906989625) internal successors, (74742), 54165 states have internal predecessors, (74742), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:19:41,398 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 54166 states to 54166 states and 74742 transitions. [2022-12-13 12:19:41,398 INFO L240 hiAutomatonCegarLoop]: Abstraction has 54166 states and 74742 transitions. [2022-12-13 12:19:41,399 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 12:19:41,399 INFO L428 stractBuchiCegarLoop]: Abstraction has 54166 states and 74742 transitions. [2022-12-13 12:19:41,399 INFO L335 stractBuchiCegarLoop]: ======== Iteration 24 ============ [2022-12-13 12:19:41,399 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 54166 states and 74742 transitions. [2022-12-13 12:19:41,563 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 53817 [2022-12-13 12:19:41,563 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:19:41,563 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:19:41,564 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:19:41,564 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:19:41,565 INFO L748 eck$LassoCheckResult]: Stem: 1912353#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 1912354#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 1913012#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1913013#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1912982#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 1912983#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1912607#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1912422#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1912423#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1912407#L556-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1912408#L561-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1912981#L566-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1912743#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1912744#L769 assume !(0 == ~M_E~0); 1912766#L769-2 assume !(0 == ~T1_E~0); 1912767#L774-1 assume !(0 == ~T2_E~0); 1912802#L779-1 assume !(0 == ~T3_E~0); 1912963#L784-1 assume !(0 == ~T4_E~0); 1912741#L789-1 assume !(0 == ~T5_E~0); 1912742#L794-1 assume !(0 == ~T6_E~0); 1912867#L799-1 assume !(0 == ~T7_E~0); 1912746#L804-1 assume !(0 == ~E_M~0); 1912747#L809-1 assume !(0 == ~E_1~0); 1912792#L814-1 assume !(0 == ~E_2~0); 1912154#L819-1 assume !(0 == ~E_3~0); 1912155#L824-1 assume !(0 == ~E_4~0); 1912494#L829-1 assume !(0 == ~E_5~0); 1913072#L834-1 assume !(0 == ~E_6~0); 1912284#L839-1 assume !(0 == ~E_7~0); 1912285#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1912693#L376 assume !(1 == ~m_pc~0); 1912689#L376-2 is_master_triggered_~__retres1~0#1 := 0; 1912690#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1912943#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1912227#L955 assume !(0 != activate_threads_~tmp~1#1); 1912228#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1912600#L395 assume !(1 == ~t1_pc~0); 1912768#L395-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1912944#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1912183#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1912184#L963 assume !(0 != activate_threads_~tmp___0~0#1); 1912698#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1912699#L414 assume !(1 == ~t2_pc~0); 1912287#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1912991#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1912501#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1912502#L971 assume !(0 != activate_threads_~tmp___1~0#1); 1912990#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1912604#L433 assume !(1 == ~t3_pc~0); 1912394#L433-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1912395#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1912152#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1912153#L979 assume !(0 != activate_threads_~tmp___2~0#1); 1912251#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1912252#L452 assume !(1 == ~t4_pc~0); 1912403#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1912404#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1912245#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1912246#L987 assume !(0 != activate_threads_~tmp___3~0#1); 1912432#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1912433#L471 assume !(1 == ~t5_pc~0); 1912846#L471-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1912417#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1912418#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1912947#L995 assume !(0 != activate_threads_~tmp___4~0#1); 1913059#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1913060#L490 assume !(1 == ~t6_pc~0); 1912696#L490-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1912697#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1912488#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1912489#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 1912613#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1912579#L509 assume !(1 == ~t7_pc~0); 1912580#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1912374#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1912375#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1912439#L1011 assume !(0 != activate_threads_~tmp___6~0#1); 1912440#L1011-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1913000#L857 assume !(1 == ~M_E~0); 1912234#L857-2 assume !(1 == ~T1_E~0); 1912235#L862-1 assume !(1 == ~T2_E~0); 1912505#L867-1 assume !(1 == ~T3_E~0); 1912510#L872-1 assume !(1 == ~T4_E~0); 1912605#L877-1 assume !(1 == ~T5_E~0); 1912820#L882-1 assume !(1 == ~T6_E~0); 1913021#L887-1 assume !(1 == ~T7_E~0); 1912894#L892-1 assume !(1 == ~E_M~0); 1912895#L897-1 assume !(1 == ~E_1~0); 1912526#L902-1 assume !(1 == ~E_2~0); 1912527#L907-1 assume !(1 == ~E_3~0); 1912834#L912-1 assume !(1 == ~E_4~0); 1912826#L917-1 assume !(1 == ~E_5~0); 1912827#L922-1 assume !(1 == ~E_6~0); 1913076#L927-1 assume !(1 == ~E_7~0); 1912815#L932-1 assume { :end_inline_reset_delta_events } true; 1912816#L1178-2 [2022-12-13 12:19:41,565 INFO L750 eck$LassoCheckResult]: Loop: 1912816#L1178-2 assume !false; 1941556#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1941557#L744 assume !false; 1943154#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1943153#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1941527#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1941528#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1941517#L641 assume !(0 != eval_~tmp~0#1); 1941519#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1949092#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1949090#L769-3 assume !(0 == ~M_E~0); 1949088#L769-5 assume !(0 == ~T1_E~0); 1949086#L774-3 assume !(0 == ~T2_E~0); 1949084#L779-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1949082#L784-3 assume !(0 == ~T4_E~0); 1949080#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1949078#L794-3 assume !(0 == ~T6_E~0); 1949076#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1949074#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1949072#L809-3 assume !(0 == ~E_1~0); 1949070#L814-3 assume !(0 == ~E_2~0); 1949068#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1949066#L824-3 assume !(0 == ~E_4~0); 1949064#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1949062#L834-3 assume !(0 == ~E_6~0); 1949060#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1949058#L844-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1949056#L376-27 assume !(1 == ~m_pc~0); 1949054#L376-29 is_master_triggered_~__retres1~0#1 := 0; 1949052#L387-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1949050#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1949048#L955-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1949046#L955-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1949044#L395-27 assume !(1 == ~t1_pc~0); 1949042#L395-29 is_transmit1_triggered_~__retres1~1#1 := 0; 1949040#L406-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1949038#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1949036#L963-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1949034#L963-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1949031#L414-27 assume !(1 == ~t2_pc~0); 1949028#L414-29 is_transmit2_triggered_~__retres1~2#1 := 0; 1949026#L425-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1949024#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1949022#L971-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1949020#L971-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1949018#L433-27 assume !(1 == ~t3_pc~0); 1949016#L433-29 is_transmit3_triggered_~__retres1~3#1 := 0; 1949014#L444-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1949012#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1949010#L979-27 assume !(0 != activate_threads_~tmp___2~0#1); 1949008#L979-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1949005#L452-27 assume !(1 == ~t4_pc~0); 1949002#L452-29 is_transmit4_triggered_~__retres1~4#1 := 0; 1949000#L463-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1948998#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1948996#L987-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1948994#L987-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1948992#L471-27 assume !(1 == ~t5_pc~0); 1948990#L471-29 is_transmit5_triggered_~__retres1~5#1 := 0; 1948988#L482-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1948986#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1948984#L995-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1948982#L995-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1948980#L490-27 assume !(1 == ~t6_pc~0); 1948978#L490-29 is_transmit6_triggered_~__retres1~6#1 := 0; 1948976#L501-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1948974#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1948972#L1003-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1948970#L1003-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1948966#L509-27 assume 1 == ~t7_pc~0; 1948964#L510-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 1948965#L520-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1949095#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1948954#L1011-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1948952#L1011-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1948951#L857-3 assume !(1 == ~M_E~0); 1948948#L857-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1948947#L862-3 assume !(1 == ~T2_E~0); 1948946#L867-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1948937#L872-3 assume !(1 == ~T4_E~0); 1948935#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1948933#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1948930#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1948929#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1948927#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1948925#L902-3 assume !(1 == ~E_2~0); 1948923#L907-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1948921#L912-3 assume !(1 == ~E_4~0); 1948919#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1948917#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1948915#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1948913#L932-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1948901#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1948895#L626-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1948893#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 1948797#L1197 assume !(0 == start_simulation_~tmp~3#1); 1948795#L1197-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1948782#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1948775#L626-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1948773#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 1948772#L1152 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1948771#L1159 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1948767#stop_simulation_returnLabel#1 start_simulation_#t~ret24#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 1948765#L1210 assume !(0 != start_simulation_~tmp___0~1#1); 1912816#L1178-2 [2022-12-13 12:19:41,565 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:19:41,566 INFO L85 PathProgramCache]: Analyzing trace with hash 1628748997, now seen corresponding path program 3 times [2022-12-13 12:19:41,566 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:19:41,566 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [733432795] [2022-12-13 12:19:41,566 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:19:41,566 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:19:41,575 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 12:19:41,575 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 12:19:41,580 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 12:19:41,595 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 12:19:41,595 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:19:41,595 INFO L85 PathProgramCache]: Analyzing trace with hash 1199560037, now seen corresponding path program 1 times [2022-12-13 12:19:41,595 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:19:41,595 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1453230633] [2022-12-13 12:19:41,596 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:19:41,596 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:19:41,603 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:19:41,634 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:19:41,634 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:19:41,634 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1453230633] [2022-12-13 12:19:41,634 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1453230633] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:19:41,635 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:19:41,635 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-12-13 12:19:41,635 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [898020907] [2022-12-13 12:19:41,635 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:19:41,635 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:19:41,635 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:19:41,636 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-12-13 12:19:41,636 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-12-13 12:19:41,636 INFO L87 Difference]: Start difference. First operand 54166 states and 74742 transitions. cyclomatic complexity: 20592 Second operand has 5 states, 5 states have (on average 20.8) internal successors, (104), 5 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:19:41,972 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:19:41,972 INFO L93 Difference]: Finished difference Result 97237 states and 132459 transitions. [2022-12-13 12:19:41,972 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 97237 states and 132459 transitions. [2022-12-13 12:19:42,438 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 96640 [2022-12-13 12:19:42,572 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 97237 states to 97237 states and 132459 transitions. [2022-12-13 12:19:42,572 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 97237 [2022-12-13 12:19:42,605 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 97237 [2022-12-13 12:19:42,605 INFO L73 IsDeterministic]: Start isDeterministic. Operand 97237 states and 132459 transitions. [2022-12-13 12:19:42,635 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:19:42,635 INFO L218 hiAutomatonCegarLoop]: Abstraction has 97237 states and 132459 transitions. [2022-12-13 12:19:42,672 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 97237 states and 132459 transitions. [2022-12-13 12:19:43,076 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 97237 to 54490. [2022-12-13 12:19:43,107 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 54490 states, 54490 states have (on average 1.377610570746926) internal successors, (75066), 54489 states have internal predecessors, (75066), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:19:43,296 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 54490 states to 54490 states and 75066 transitions. [2022-12-13 12:19:43,296 INFO L240 hiAutomatonCegarLoop]: Abstraction has 54490 states and 75066 transitions. [2022-12-13 12:19:43,297 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2022-12-13 12:19:43,297 INFO L428 stractBuchiCegarLoop]: Abstraction has 54490 states and 75066 transitions. [2022-12-13 12:19:43,297 INFO L335 stractBuchiCegarLoop]: ======== Iteration 25 ============ [2022-12-13 12:19:43,297 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 54490 states and 75066 transitions. [2022-12-13 12:19:43,406 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 54141 [2022-12-13 12:19:43,406 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:19:43,406 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:19:43,407 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:19:43,407 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:19:43,407 INFO L748 eck$LassoCheckResult]: Stem: 2063775#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 2063776#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 2064472#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2064473#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2064440#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 2064441#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2064039#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2063846#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2063847#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 2063828#L556-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 2063829#L561-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 2064439#L566-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 2064183#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2064184#L769 assume !(0 == ~M_E~0); 2064208#L769-2 assume !(0 == ~T1_E~0); 2064209#L774-1 assume !(0 == ~T2_E~0); 2064244#L779-1 assume !(0 == ~T3_E~0); 2064420#L784-1 assume !(0 == ~T4_E~0); 2064181#L789-1 assume !(0 == ~T5_E~0); 2064182#L794-1 assume !(0 == ~T6_E~0); 2064320#L799-1 assume !(0 == ~T7_E~0); 2064187#L804-1 assume !(0 == ~E_M~0); 2064188#L809-1 assume !(0 == ~E_1~0); 2064236#L814-1 assume !(0 == ~E_2~0); 2063573#L819-1 assume !(0 == ~E_3~0); 2063574#L824-1 assume !(0 == ~E_4~0); 2063918#L829-1 assume !(0 == ~E_5~0); 2064538#L834-1 assume !(0 == ~E_6~0); 2063703#L839-1 assume !(0 == ~E_7~0); 2063704#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2064132#L376 assume !(1 == ~m_pc~0); 2064128#L376-2 is_master_triggered_~__retres1~0#1 := 0; 2064129#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2064402#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2063644#L955 assume !(0 != activate_threads_~tmp~1#1); 2063645#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2064031#L395 assume !(1 == ~t1_pc~0); 2064210#L395-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2064403#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2063602#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2063603#L963 assume !(0 != activate_threads_~tmp___0~0#1); 2064138#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2064139#L414 assume !(1 == ~t2_pc~0); 2063706#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2064446#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2063926#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2063927#L971 assume !(0 != activate_threads_~tmp___1~0#1); 2064445#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2064035#L433 assume !(1 == ~t3_pc~0); 2063815#L433-2 is_transmit3_triggered_~__retres1~3#1 := 0; 2063816#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2063571#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2063572#L979 assume !(0 != activate_threads_~tmp___2~0#1); 2063669#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2063670#L452 assume !(1 == ~t4_pc~0); 2063824#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 2063825#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2063663#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2063664#L987 assume !(0 != activate_threads_~tmp___3~0#1); 2063856#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2063857#L471 assume !(1 == ~t5_pc~0); 2064294#L471-2 is_transmit5_triggered_~__retres1~5#1 := 0; 2063840#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2063841#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2064406#L995 assume !(0 != activate_threads_~tmp___4~0#1); 2064523#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2064524#L490 assume !(1 == ~t6_pc~0); 2064136#L490-2 is_transmit6_triggered_~__retres1~6#1 := 0; 2064137#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2063912#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2063913#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 2064047#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2064010#L509 assume !(1 == ~t7_pc~0); 2064011#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 2063796#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2063797#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2063863#L1011 assume !(0 != activate_threads_~tmp___6~0#1); 2063864#L1011-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2064454#L857 assume !(1 == ~M_E~0); 2063651#L857-2 assume !(1 == ~T1_E~0); 2063652#L862-1 assume !(1 == ~T2_E~0); 2063930#L867-1 assume !(1 == ~T3_E~0); 2063936#L872-1 assume !(1 == ~T4_E~0); 2064036#L877-1 assume !(1 == ~T5_E~0); 2064266#L882-1 assume !(1 == ~T6_E~0); 2064479#L887-1 assume !(1 == ~T7_E~0); 2064352#L892-1 assume !(1 == ~E_M~0); 2064353#L897-1 assume !(1 == ~E_1~0); 2063955#L902-1 assume !(1 == ~E_2~0); 2063956#L907-1 assume !(1 == ~E_3~0); 2064283#L912-1 assume !(1 == ~E_4~0); 2064274#L917-1 assume !(1 == ~E_5~0); 2064275#L922-1 assume !(1 == ~E_6~0); 2064543#L927-1 assume !(1 == ~E_7~0); 2064260#L932-1 assume { :end_inline_reset_delta_events } true; 2064261#L1178-2 [2022-12-13 12:19:43,407 INFO L750 eck$LassoCheckResult]: Loop: 2064261#L1178-2 assume !false; 2117924#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2117270#L744 assume !false; 2117267#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 2117245#L584 assume !(0 == ~m_st~0); 2117241#L588 assume !(0 == ~t1_st~0); 2117242#L592 assume !(0 == ~t2_st~0); 2117244#L596 assume !(0 == ~t3_st~0); 2117239#L600 assume !(0 == ~t4_st~0); 2117240#L604 assume !(0 == ~t5_st~0); 2117243#L608 assume !(0 == ~t6_st~0); 2117237#L612 assume !(0 == ~t7_st~0);exists_runnable_thread_~__retres1~8#1 := 0; 2117238#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 2089523#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 2089524#L641 assume !(0 != eval_~tmp~0#1); 2117225#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2117236#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2064520#L769-3 assume !(0 == ~M_E~0); 2064033#L769-5 assume !(0 == ~T1_E~0); 2064034#L774-3 assume !(0 == ~T2_E~0); 2063752#L779-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2063753#L784-3 assume !(0 == ~T4_E~0); 2064643#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2063575#L794-3 assume !(0 == ~T6_E~0); 2063576#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 2063872#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2063873#L809-3 assume !(0 == ~E_1~0); 2117811#L814-3 assume !(0 == ~E_2~0); 2064430#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2064431#L824-3 assume !(0 == ~E_4~0); 2064384#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2064385#L834-3 assume !(0 == ~E_6~0); 2064318#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 2064319#L844-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2064584#L376-27 assume !(1 == ~m_pc~0); 2064585#L376-29 is_master_triggered_~__retres1~0#1 := 0; 2064218#L387-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2064219#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2064547#L955-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2064548#L955-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2117810#L395-27 assume !(1 == ~t1_pc~0); 2064055#L395-29 is_transmit1_triggered_~__retres1~1#1 := 0; 2063933#L406-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2063934#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2117808#L963-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2064040#L963-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2064041#L414-27 assume !(1 == ~t2_pc~0); 2064602#L414-29 is_transmit2_triggered_~__retres1~2#1 := 0; 2064603#L425-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2064270#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2064271#L971-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2063628#L971-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2063629#L433-27 assume !(1 == ~t3_pc~0); 2117806#L433-29 is_transmit3_triggered_~__retres1~3#1 := 0; 2064049#L444-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2064050#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2063801#L979-27 assume !(0 != activate_threads_~tmp___2~0#1); 2063802#L979-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2064605#L452-27 assume !(1 == ~t4_pc~0); 2117803#L452-29 is_transmit4_triggered_~__retres1~4#1 := 0; 2064422#L463-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2064008#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2064009#L987-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 2064521#L987-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2064522#L471-27 assume !(1 == ~t5_pc~0); 2063947#L471-29 is_transmit5_triggered_~__retres1~5#1 := 0; 2063948#L482-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2064417#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2064298#L995-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 2064299#L995-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2064130#L490-27 assume !(1 == ~t6_pc~0); 2064131#L490-29 is_transmit6_triggered_~__retres1~6#1 := 0; 2063812#L501-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2063813#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2117798#L1003-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 2064566#L1003-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2064567#L509-27 assume !(1 == ~t7_pc~0); 2064006#L509-29 is_transmit7_triggered_~__retres1~7#1 := 0; 2064007#L520-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2063877#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2063878#L1011-27 assume !(0 != activate_threads_~tmp___6~0#1); 2064155#L1011-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2064167#L857-3 assume !(1 == ~M_E~0); 2064168#L857-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2118043#L862-3 assume !(1 == ~T2_E~0); 2118042#L867-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2118041#L872-3 assume !(1 == ~T4_E~0); 2118040#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2118039#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 2118038#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 2118037#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2118036#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2118035#L902-3 assume !(1 == ~E_2~0); 2118034#L907-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2118033#L912-3 assume !(1 == ~E_4~0); 2118032#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2118031#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 2118030#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 2118029#L932-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 2063679#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 2063583#L626-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 2064324#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 2064021#L1197 assume !(0 == start_simulation_~tmp~3#1); 2064022#L1197-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 2063732#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 2063701#L626-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 2063600#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 2063601#L1152 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2064598#L1159 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2117980#stop_simulation_returnLabel#1 start_simulation_#t~ret24#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 2117979#L1210 assume !(0 != start_simulation_~tmp___0~1#1); 2064261#L1178-2 [2022-12-13 12:19:43,408 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:19:43,408 INFO L85 PathProgramCache]: Analyzing trace with hash 1628748997, now seen corresponding path program 4 times [2022-12-13 12:19:43,408 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:19:43,408 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1268230774] [2022-12-13 12:19:43,408 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:19:43,408 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:19:43,414 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 12:19:43,414 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 12:19:43,418 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 12:19:43,430 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 12:19:43,430 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:19:43,431 INFO L85 PathProgramCache]: Analyzing trace with hash 1565522552, now seen corresponding path program 1 times [2022-12-13 12:19:43,431 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:19:43,431 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [489400211] [2022-12-13 12:19:43,431 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:19:43,431 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:19:43,438 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:19:43,488 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:19:43,488 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:19:43,488 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [489400211] [2022-12-13 12:19:43,488 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [489400211] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:19:43,488 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:19:43,488 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-12-13 12:19:43,488 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1671017560] [2022-12-13 12:19:43,488 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:19:43,489 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:19:43,489 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:19:43,489 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-12-13 12:19:43,489 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-12-13 12:19:43,489 INFO L87 Difference]: Start difference. First operand 54490 states and 75066 transitions. cyclomatic complexity: 20592 Second operand has 5 states, 5 states have (on average 22.2) internal successors, (111), 5 states have internal predecessors, (111), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:19:43,830 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:19:43,830 INFO L93 Difference]: Finished difference Result 89930 states and 123281 transitions. [2022-12-13 12:19:43,830 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 89930 states and 123281 transitions. [2022-12-13 12:19:44,093 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 89517 [2022-12-13 12:19:44,244 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 89930 states to 89930 states and 123281 transitions. [2022-12-13 12:19:44,244 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 89930 [2022-12-13 12:19:44,286 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 89930 [2022-12-13 12:19:44,286 INFO L73 IsDeterministic]: Start isDeterministic. Operand 89930 states and 123281 transitions. [2022-12-13 12:19:44,322 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:19:44,322 INFO L218 hiAutomatonCegarLoop]: Abstraction has 89930 states and 123281 transitions. [2022-12-13 12:19:44,359 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 89930 states and 123281 transitions. [2022-12-13 12:19:44,883 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 89930 to 55210. [2022-12-13 12:19:44,917 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 55210 states, 55210 states have (on average 1.3646984241985147) internal successors, (75345), 55209 states have internal predecessors, (75345), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:19:44,989 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 55210 states to 55210 states and 75345 transitions. [2022-12-13 12:19:44,989 INFO L240 hiAutomatonCegarLoop]: Abstraction has 55210 states and 75345 transitions. [2022-12-13 12:19:44,990 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-12-13 12:19:44,991 INFO L428 stractBuchiCegarLoop]: Abstraction has 55210 states and 75345 transitions. [2022-12-13 12:19:44,991 INFO L335 stractBuchiCegarLoop]: ======== Iteration 26 ============ [2022-12-13 12:19:44,991 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 55210 states and 75345 transitions. [2022-12-13 12:19:45,123 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 54861 [2022-12-13 12:19:45,123 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:19:45,123 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:19:45,124 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:19:45,124 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:19:45,124 INFO L748 eck$LassoCheckResult]: Stem: 2208205#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 2208206#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 2208880#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2208881#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2208847#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 2208848#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2208468#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2208276#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2208277#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 2208260#L556-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 2208261#L561-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 2208846#L566-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 2208610#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2208611#L769 assume !(0 == ~M_E~0); 2208631#L769-2 assume !(0 == ~T1_E~0); 2208632#L774-1 assume !(0 == ~T2_E~0); 2208664#L779-1 assume !(0 == ~T3_E~0); 2208827#L784-1 assume !(0 == ~T4_E~0); 2208608#L789-1 assume !(0 == ~T5_E~0); 2208609#L794-1 assume !(0 == ~T6_E~0); 2208731#L799-1 assume !(0 == ~T7_E~0); 2208613#L804-1 assume !(0 == ~E_M~0); 2208614#L809-1 assume !(0 == ~E_1~0); 2208655#L814-1 assume !(0 == ~E_2~0); 2208006#L819-1 assume !(0 == ~E_3~0); 2208007#L824-1 assume !(0 == ~E_4~0); 2208346#L829-1 assume !(0 == ~E_5~0); 2208936#L834-1 assume !(0 == ~E_6~0); 2208135#L839-1 assume !(0 == ~E_7~0); 2208136#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2208556#L376 assume !(1 == ~m_pc~0); 2208552#L376-2 is_master_triggered_~__retres1~0#1 := 0; 2208553#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2208808#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2208078#L955 assume !(0 != activate_threads_~tmp~1#1); 2208079#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2208459#L395 assume !(1 == ~t1_pc~0); 2208633#L395-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2208809#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2208036#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2208037#L963 assume !(0 != activate_threads_~tmp___0~0#1); 2208563#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2208564#L414 assume !(1 == ~t2_pc~0); 2208138#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2208856#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2208354#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2208355#L971 assume !(0 != activate_threads_~tmp___1~0#1); 2208854#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2208465#L433 assume !(1 == ~t3_pc~0); 2208248#L433-2 is_transmit3_triggered_~__retres1~3#1 := 0; 2208249#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2208004#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2208005#L979 assume !(0 != activate_threads_~tmp___2~0#1); 2208102#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2208103#L452 assume !(1 == ~t4_pc~0); 2208256#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 2208257#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2208096#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2208097#L987 assume !(0 != activate_threads_~tmp___3~0#1); 2208286#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2208287#L471 assume !(1 == ~t5_pc~0); 2208708#L471-2 is_transmit5_triggered_~__retres1~5#1 := 0; 2208270#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2208271#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2208812#L995 assume !(0 != activate_threads_~tmp___4~0#1); 2208923#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2208924#L490 assume !(1 == ~t6_pc~0); 2208561#L490-2 is_transmit6_triggered_~__retres1~6#1 := 0; 2208562#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2208340#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2208341#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 2208475#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2208437#L509 assume !(1 == ~t7_pc~0); 2208438#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 2208228#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2208229#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2208293#L1011 assume !(0 != activate_threads_~tmp___6~0#1); 2208294#L1011-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2208867#L857 assume !(1 == ~M_E~0); 2208085#L857-2 assume !(1 == ~T1_E~0); 2208086#L862-1 assume !(1 == ~T2_E~0); 2208358#L867-1 assume !(1 == ~T3_E~0); 2208364#L872-1 assume !(1 == ~T4_E~0); 2208466#L877-1 assume !(1 == ~T5_E~0); 2208683#L882-1 assume !(1 == ~T6_E~0); 2208889#L887-1 assume !(1 == ~T7_E~0); 2208760#L892-1 assume !(1 == ~E_M~0); 2208761#L897-1 assume !(1 == ~E_1~0); 2208382#L902-1 assume !(1 == ~E_2~0); 2208383#L907-1 assume !(1 == ~E_3~0); 2208699#L912-1 assume !(1 == ~E_4~0); 2208690#L917-1 assume !(1 == ~E_5~0); 2208691#L922-1 assume !(1 == ~E_6~0); 2208939#L927-1 assume !(1 == ~E_7~0); 2208678#L932-1 assume { :end_inline_reset_delta_events } true; 2208679#L1178-2 [2022-12-13 12:19:45,125 INFO L750 eck$LassoCheckResult]: Loop: 2208679#L1178-2 assume !false; 2225843#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2225844#L744 assume !false; 2225839#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 2225840#L584 assume !(0 == ~m_st~0); 2231620#L588 assume !(0 == ~t1_st~0); 2231621#L592 assume !(0 == ~t2_st~0); 2231623#L596 assume !(0 == ~t3_st~0); 2231618#L600 assume !(0 == ~t4_st~0); 2231619#L604 assume !(0 == ~t5_st~0); 2231622#L608 assume !(0 == ~t6_st~0); 2231616#L612 assume !(0 == ~t7_st~0);exists_runnable_thread_~__retres1~8#1 := 0; 2231617#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 2231649#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 2231611#L641 assume !(0 != eval_~tmp~0#1); 2231612#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2224833#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2224834#L769-3 assume !(0 == ~M_E~0); 2224829#L769-5 assume !(0 == ~T1_E~0); 2224830#L774-3 assume !(0 == ~T2_E~0); 2224825#L779-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2224826#L784-3 assume !(0 == ~T4_E~0); 2224821#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2224822#L794-3 assume !(0 == ~T6_E~0); 2224817#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 2224818#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2224813#L809-3 assume !(0 == ~E_1~0); 2224814#L814-3 assume !(0 == ~E_2~0); 2224809#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2224810#L824-3 assume !(0 == ~E_4~0); 2224805#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2224806#L834-3 assume !(0 == ~E_6~0); 2224801#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 2224802#L844-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2224797#L376-27 assume !(1 == ~m_pc~0); 2224798#L376-29 is_master_triggered_~__retres1~0#1 := 0; 2224793#L387-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2224794#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2224789#L955-27 assume !(0 != activate_threads_~tmp~1#1); 2224790#L955-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2224785#L395-27 assume !(1 == ~t1_pc~0); 2224786#L395-29 is_transmit1_triggered_~__retres1~1#1 := 0; 2224782#L406-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2224783#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2224778#L963-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2224779#L963-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2224775#L414-27 assume !(1 == ~t2_pc~0); 2224774#L414-29 is_transmit2_triggered_~__retres1~2#1 := 0; 2224769#L425-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2224770#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2224765#L971-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2224766#L971-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2224761#L433-27 assume !(1 == ~t3_pc~0); 2224762#L433-29 is_transmit3_triggered_~__retres1~3#1 := 0; 2224757#L444-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2224758#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2224753#L979-27 assume !(0 != activate_threads_~tmp___2~0#1); 2224754#L979-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2224750#L452-27 assume !(1 == ~t4_pc~0); 2224749#L452-29 is_transmit4_triggered_~__retres1~4#1 := 0; 2224744#L463-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2224745#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2224740#L987-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 2224741#L987-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2224736#L471-27 assume !(1 == ~t5_pc~0); 2224737#L471-29 is_transmit5_triggered_~__retres1~5#1 := 0; 2224732#L482-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2224733#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2224728#L995-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 2224729#L995-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2224724#L490-27 assume !(1 == ~t6_pc~0); 2224725#L490-29 is_transmit6_triggered_~__retres1~6#1 := 0; 2224720#L501-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2224721#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2224716#L1003-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 2224717#L1003-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2224711#L509-27 assume 1 == ~t7_pc~0; 2224713#L510-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 2224838#L520-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2224839#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2224700#L1011-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 2224701#L1011-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2224697#L857-3 assume !(1 == ~M_E~0); 2224695#L857-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2224690#L862-3 assume !(1 == ~T2_E~0); 2224691#L867-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2224686#L872-3 assume !(1 == ~T4_E~0); 2224687#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2224682#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 2224683#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 2224678#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2224679#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2224674#L902-3 assume !(1 == ~E_2~0); 2224675#L907-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2224670#L912-3 assume !(1 == ~E_4~0); 2224671#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2224666#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 2224667#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 2224662#L932-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 2224663#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 2232199#L626-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 2232198#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 2232197#L1197 assume !(0 == start_simulation_~tmp~3#1); 2225949#L1197-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 2225950#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 2234474#L626-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 2234473#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 2234472#L1152 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2234471#L1159 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2234470#stop_simulation_returnLabel#1 start_simulation_#t~ret24#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 2234469#L1210 assume !(0 != start_simulation_~tmp___0~1#1); 2208679#L1178-2 [2022-12-13 12:19:45,125 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:19:45,125 INFO L85 PathProgramCache]: Analyzing trace with hash 1628748997, now seen corresponding path program 5 times [2022-12-13 12:19:45,125 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:19:45,125 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [247524863] [2022-12-13 12:19:45,125 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:19:45,125 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:19:45,133 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 12:19:45,133 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 12:19:45,138 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 12:19:45,150 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 12:19:45,150 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:19:45,150 INFO L85 PathProgramCache]: Analyzing trace with hash -2098568969, now seen corresponding path program 1 times [2022-12-13 12:19:45,150 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:19:45,150 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1108196143] [2022-12-13 12:19:45,150 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:19:45,150 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:19:45,157 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:19:45,174 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:19:45,175 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:19:45,175 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1108196143] [2022-12-13 12:19:45,175 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1108196143] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:19:45,175 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:19:45,175 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:19:45,175 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [367855544] [2022-12-13 12:19:45,175 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:19:45,175 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:19:45,176 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:19:45,176 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 12:19:45,176 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 12:19:45,176 INFO L87 Difference]: Start difference. First operand 55210 states and 75345 transitions. cyclomatic complexity: 20151 Second operand has 3 states, 3 states have (on average 37.0) internal successors, (111), 3 states have internal predecessors, (111), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:19:45,365 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:19:45,366 INFO L93 Difference]: Finished difference Result 83525 states and 112470 transitions. [2022-12-13 12:19:45,366 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 83525 states and 112470 transitions. [2022-12-13 12:19:45,765 INFO L131 ngComponentsAnalysis]: Automaton has 30 accepting balls. 83174 [2022-12-13 12:19:45,926 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 83525 states to 83525 states and 112470 transitions. [2022-12-13 12:19:45,927 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 83525 [2022-12-13 12:19:45,961 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 83525 [2022-12-13 12:19:45,961 INFO L73 IsDeterministic]: Start isDeterministic. Operand 83525 states and 112470 transitions. [2022-12-13 12:19:46,003 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:19:46,004 INFO L218 hiAutomatonCegarLoop]: Abstraction has 83525 states and 112470 transitions. [2022-12-13 12:19:46,035 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 83525 states and 112470 transitions. [2022-12-13 12:19:46,614 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 83525 to 81861. [2022-12-13 12:19:46,664 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 81861 states, 81861 states have (on average 1.347723580215243) internal successors, (110326), 81860 states have internal predecessors, (110326), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:19:46,918 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 81861 states to 81861 states and 110326 transitions. [2022-12-13 12:19:46,918 INFO L240 hiAutomatonCegarLoop]: Abstraction has 81861 states and 110326 transitions. [2022-12-13 12:19:46,919 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 12:19:46,919 INFO L428 stractBuchiCegarLoop]: Abstraction has 81861 states and 110326 transitions. [2022-12-13 12:19:46,919 INFO L335 stractBuchiCegarLoop]: ======== Iteration 27 ============ [2022-12-13 12:19:46,919 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 81861 states and 110326 transitions. [2022-12-13 12:19:47,080 INFO L131 ngComponentsAnalysis]: Automaton has 30 accepting balls. 81510 [2022-12-13 12:19:47,081 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:19:47,081 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:19:47,081 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:19:47,081 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:19:47,081 INFO L748 eck$LassoCheckResult]: Stem: 2346948#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 2346949#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 2347622#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2347623#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2347593#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 2347594#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2347205#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2347018#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2347019#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 2347002#L556-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 2347003#L561-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 2347592#L566-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 2347354#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2347355#L769 assume !(0 == ~M_E~0); 2347376#L769-2 assume !(0 == ~T1_E~0); 2347377#L774-1 assume !(0 == ~T2_E~0); 2347413#L779-1 assume !(0 == ~T3_E~0); 2347574#L784-1 assume !(0 == ~T4_E~0); 2347350#L789-1 assume !(0 == ~T5_E~0); 2347351#L794-1 assume !(0 == ~T6_E~0); 2347481#L799-1 assume !(0 == ~T7_E~0); 2347357#L804-1 assume !(0 == ~E_M~0); 2347358#L809-1 assume !(0 == ~E_1~0); 2347403#L814-1 assume !(0 == ~E_2~0); 2346747#L819-1 assume !(0 == ~E_3~0); 2346748#L824-1 assume !(0 == ~E_4~0); 2347092#L829-1 assume !(0 == ~E_5~0); 2347689#L834-1 assume !(0 == ~E_6~0); 2346877#L839-1 assume !(0 == ~E_7~0); 2346878#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2347297#L376 assume !(1 == ~m_pc~0); 2347293#L376-2 is_master_triggered_~__retres1~0#1 := 0; 2347294#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2347555#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2346819#L955 assume !(0 != activate_threads_~tmp~1#1); 2346820#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2347198#L395 assume !(1 == ~t1_pc~0); 2347378#L395-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2347556#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2346776#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2346777#L963 assume !(0 != activate_threads_~tmp___0~0#1); 2347302#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2347303#L414 assume !(1 == ~t2_pc~0); 2346880#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2347601#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2347100#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2347101#L971 assume !(0 != activate_threads_~tmp___1~0#1); 2347599#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2347203#L433 assume !(1 == ~t3_pc~0); 2346989#L433-2 is_transmit3_triggered_~__retres1~3#1 := 0; 2346990#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2346745#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2346746#L979 assume !(0 != activate_threads_~tmp___2~0#1); 2346844#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2346845#L452 assume !(1 == ~t4_pc~0); 2346998#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 2346999#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2346838#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2346839#L987 assume !(0 != activate_threads_~tmp___3~0#1); 2347028#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2347029#L471 assume !(1 == ~t5_pc~0); 2347461#L471-2 is_transmit5_triggered_~__retres1~5#1 := 0; 2347013#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2347014#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2347560#L995 assume !(0 != activate_threads_~tmp___4~0#1); 2347677#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2347678#L490 assume !(1 == ~t6_pc~0); 2347300#L490-2 is_transmit6_triggered_~__retres1~6#1 := 0; 2347301#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2347086#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2347087#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 2347211#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2347179#L509 assume !(1 == ~t7_pc~0); 2347180#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 2346970#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2346971#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2347035#L1011 assume !(0 != activate_threads_~tmp___6~0#1); 2347036#L1011-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2347609#L857 assume !(1 == ~M_E~0); 2346826#L857-2 assume !(1 == ~T1_E~0); 2346827#L862-1 assume !(1 == ~T2_E~0); 2347104#L867-1 assume !(1 == ~T3_E~0); 2347111#L872-1 assume !(1 == ~T4_E~0); 2347202#L877-1 assume !(1 == ~T5_E~0); 2347434#L882-1 assume !(1 == ~T6_E~0); 2347631#L887-1 assume !(1 == ~T7_E~0); 2347509#L892-1 assume !(1 == ~E_M~0); 2347510#L897-1 assume !(1 == ~E_1~0); 2347129#L902-1 assume !(1 == ~E_2~0); 2347130#L907-1 assume !(1 == ~E_3~0); 2347448#L912-1 assume !(1 == ~E_4~0); 2347440#L917-1 assume !(1 == ~E_5~0); 2347441#L922-1 assume !(1 == ~E_6~0); 2347694#L927-1 assume !(1 == ~E_7~0); 2347429#L932-1 assume { :end_inline_reset_delta_events } true; 2347430#L1178-2 assume !false; 2398286#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2398283#L744 [2022-12-13 12:19:47,082 INFO L750 eck$LassoCheckResult]: Loop: 2398283#L744 assume !false; 2398281#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 2398279#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 2398278#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 2398274#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 2398272#L641 assume 0 != eval_~tmp~0#1; 2398269#L641-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 2398268#L649 assume !(0 != eval_~tmp_ndt_1~0#1); 2398267#L646 assume !(0 == ~t1_st~0); 2398265#L660 assume !(0 == ~t2_st~0); 2398256#L674 assume !(0 == ~t3_st~0); 2398253#L688 assume !(0 == ~t4_st~0); 2398236#L702 assume !(0 == ~t5_st~0); 2398228#L716 assume !(0 == ~t6_st~0); 2398290#L730 assume !(0 == ~t7_st~0); 2398283#L744 [2022-12-13 12:19:47,082 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:19:47,082 INFO L85 PathProgramCache]: Analyzing trace with hash 1859704647, now seen corresponding path program 1 times [2022-12-13 12:19:47,082 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:19:47,082 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [695978617] [2022-12-13 12:19:47,082 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:19:47,082 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:19:47,089 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 12:19:47,089 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 12:19:47,093 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 12:19:47,105 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 12:19:47,106 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:19:47,106 INFO L85 PathProgramCache]: Analyzing trace with hash 1396700962, now seen corresponding path program 1 times [2022-12-13 12:19:47,106 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:19:47,106 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1286332288] [2022-12-13 12:19:47,106 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:19:47,106 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:19:47,108 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 12:19:47,108 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 12:19:47,109 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 12:19:47,111 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 12:19:47,111 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:19:47,111 INFO L85 PathProgramCache]: Analyzing trace with hash -2002719972, now seen corresponding path program 1 times [2022-12-13 12:19:47,111 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:19:47,111 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [257979996] [2022-12-13 12:19:47,111 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:19:47,111 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:19:47,117 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:19:47,135 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:19:47,135 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:19:47,135 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [257979996] [2022-12-13 12:19:47,135 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [257979996] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:19:47,135 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:19:47,136 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:19:47,136 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [690958672] [2022-12-13 12:19:47,136 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:19:47,221 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:19:47,221 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 12:19:47,221 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 12:19:47,221 INFO L87 Difference]: Start difference. First operand 81861 states and 110326 transitions. cyclomatic complexity: 28495 Second operand has 3 states, 3 states have (on average 37.333333333333336) internal successors, (112), 3 states have internal predecessors, (112), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:19:47,579 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:19:47,579 INFO L93 Difference]: Finished difference Result 156414 states and 208777 transitions. [2022-12-13 12:19:47,579 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 156414 states and 208777 transitions. [2022-12-13 12:19:48,210 INFO L131 ngComponentsAnalysis]: Automaton has 54 accepting balls. 151335 [2022-12-13 12:19:48,439 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 156414 states to 156414 states and 208777 transitions. [2022-12-13 12:19:48,439 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 156414 [2022-12-13 12:19:48,490 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 156414 [2022-12-13 12:19:48,490 INFO L73 IsDeterministic]: Start isDeterministic. Operand 156414 states and 208777 transitions. [2022-12-13 12:19:48,537 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:19:48,537 INFO L218 hiAutomatonCegarLoop]: Abstraction has 156414 states and 208777 transitions. [2022-12-13 12:19:48,588 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 156414 states and 208777 transitions. [2022-12-13 12:19:49,466 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 156414 to 153487. [2022-12-13 12:19:49,552 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 153487 states, 153487 states have (on average 1.3361392170020914) internal successors, (205080), 153486 states have internal predecessors, (205080), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:19:49,749 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 153487 states to 153487 states and 205080 transitions. [2022-12-13 12:19:49,749 INFO L240 hiAutomatonCegarLoop]: Abstraction has 153487 states and 205080 transitions. [2022-12-13 12:19:49,750 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 12:19:49,751 INFO L428 stractBuchiCegarLoop]: Abstraction has 153487 states and 205080 transitions. [2022-12-13 12:19:49,751 INFO L335 stractBuchiCegarLoop]: ======== Iteration 28 ============ [2022-12-13 12:19:49,751 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 153487 states and 205080 transitions. [2022-12-13 12:19:50,291 INFO L131 ngComponentsAnalysis]: Automaton has 54 accepting balls. 148408 [2022-12-13 12:19:50,291 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:19:50,291 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:19:50,292 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:19:50,292 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:19:50,293 INFO L748 eck$LassoCheckResult]: Stem: 2585231#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 2585232#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 2585925#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2585926#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2585879#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 2585880#L536-2 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 2586074#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2585300#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2585301#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 2585283#L556-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 2585284#L561-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 2585877#L566-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 2585878#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2585972#L769 assume !(0 == ~M_E~0); 2585973#L769-2 assume !(0 == ~T1_E~0); 2585696#L774-1 assume !(0 == ~T2_E~0); 2585697#L779-1 assume !(0 == ~T3_E~0); 2585855#L784-1 assume !(0 == ~T4_E~0); 2585856#L789-1 assume !(0 == ~T5_E~0); 2585762#L794-1 assume !(0 == ~T6_E~0); 2585763#L799-1 assume !(0 == ~T7_E~0); 2585639#L804-1 assume !(0 == ~E_M~0); 2585640#L809-1 assume !(0 == ~E_1~0); 2585892#L814-1 assume !(0 == ~E_2~0); 2585893#L819-1 assume !(0 == ~E_3~0); 2585372#L824-1 assume !(0 == ~E_4~0); 2585373#L829-1 assume !(0 == ~E_5~0); 2585987#L834-1 assume !(0 == ~E_6~0); 2585988#L839-1 assume !(0 == ~E_7~0); 2585768#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2585769#L376 assume !(1 == ~m_pc~0); 2585570#L376-2 is_master_triggered_~__retres1~0#1 := 0; 2585571#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2585832#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2585833#L955 assume !(0 != activate_threads_~tmp~1#1); 2585478#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2585479#L395 assume !(1 == ~t1_pc~0); 2585834#L395-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2585835#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2585059#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2585060#L963 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2585912#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2586103#L414 assume !(1 == ~t2_pc~0); 2585163#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2586096#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2586097#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2585887#L971 assume !(0 != activate_threads_~tmp___1~0#1); 2585888#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2585484#L433 assume !(1 == ~t3_pc~0); 2585485#L433-2 is_transmit3_triggered_~__retres1~3#1 := 0; 2586012#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2586013#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2585818#L979 assume !(0 != activate_threads_~tmp___2~0#1); 2585819#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2586075#L452 assume !(1 == ~t4_pc~0); 2586055#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 2585616#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2585617#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2586006#L987 assume !(0 != activate_threads_~tmp___3~0#1); 2586007#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2585743#L471 assume !(1 == ~t5_pc~0); 2585744#L471-2 is_transmit5_triggered_~__retres1~5#1 := 0; 2585294#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2585295#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2586094#L995 assume !(0 != activate_threads_~tmp___4~0#1); 2586095#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2586035#L490 assume !(1 == ~t6_pc~0); 2586036#L490-2 is_transmit6_triggered_~__retres1~6#1 := 0; 2585621#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2585622#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2585628#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 2585629#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2585456#L509 assume !(1 == ~t7_pc~0); 2585457#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 2585252#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2585253#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2585317#L1011 assume !(0 != activate_threads_~tmp___6~0#1); 2585318#L1011-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2585906#L857 assume !(1 == ~M_E~0); 2585907#L857-2 assume !(1 == ~T1_E~0); 2585385#L862-1 assume !(1 == ~T2_E~0); 2585386#L867-1 assume !(1 == ~T3_E~0); 2585486#L872-1 assume !(1 == ~T4_E~0); 2585487#L877-1 assume !(1 == ~T5_E~0); 2585935#L882-1 assume !(1 == ~T6_E~0); 2585936#L887-1 assume !(1 == ~T7_E~0); 2585789#L892-1 assume !(1 == ~E_M~0); 2585790#L897-1 assume !(1 == ~E_1~0); 2585409#L902-1 assume !(1 == ~E_2~0); 2585410#L907-1 assume !(1 == ~E_3~0); 2585731#L912-1 assume !(1 == ~E_4~0); 2585732#L917-1 assume !(1 == ~E_5~0); 2585996#L922-1 assume !(1 == ~E_6~0); 2585997#L927-1 assume !(1 == ~E_7~0); 2585711#L932-1 assume { :end_inline_reset_delta_events } true; 2585712#L1178-2 assume !false; 2590872#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2590873#L744 [2022-12-13 12:19:50,293 INFO L750 eck$LassoCheckResult]: Loop: 2590873#L744 assume !false; 2612042#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 2612040#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 2612039#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 2612038#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 2612037#L641 assume 0 != eval_~tmp~0#1; 2612035#L641-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 2612034#L649 assume !(0 != eval_~tmp_ndt_1~0#1); 2612033#L646 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 2612031#L663 assume !(0 != eval_~tmp_ndt_2~0#1); 2590361#L660 assume !(0 == ~t2_st~0); 2590356#L674 assume !(0 == ~t3_st~0); 2590297#L688 assume !(0 == ~t4_st~0); 2612052#L702 assume !(0 == ~t5_st~0); 2612049#L716 assume !(0 == ~t6_st~0); 2612046#L730 assume !(0 == ~t7_st~0); 2590873#L744 [2022-12-13 12:19:50,293 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:19:50,294 INFO L85 PathProgramCache]: Analyzing trace with hash 570287107, now seen corresponding path program 1 times [2022-12-13 12:19:50,294 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:19:50,294 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [619541101] [2022-12-13 12:19:50,294 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:19:50,294 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:19:50,302 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:19:50,320 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:19:50,320 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:19:50,321 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [619541101] [2022-12-13 12:19:50,321 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [619541101] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:19:50,321 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:19:50,321 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:19:50,321 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1810050757] [2022-12-13 12:19:50,321 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:19:50,321 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 12:19:50,321 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:19:50,321 INFO L85 PathProgramCache]: Analyzing trace with hash -2139482281, now seen corresponding path program 1 times [2022-12-13 12:19:50,322 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:19:50,322 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2031399252] [2022-12-13 12:19:50,322 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:19:50,322 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:19:50,324 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 12:19:50,324 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 12:19:50,326 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 12:19:50,327 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 12:19:50,427 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:19:50,427 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 12:19:50,427 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 12:19:50,427 INFO L87 Difference]: Start difference. First operand 153487 states and 205080 transitions. cyclomatic complexity: 51647 Second operand has 3 states, 3 states have (on average 32.333333333333336) internal successors, (97), 3 states have internal predecessors, (97), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:19:50,798 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:19:50,798 INFO L93 Difference]: Finished difference Result 122380 states and 163658 transitions. [2022-12-13 12:19:50,798 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 122380 states and 163658 transitions. [2022-12-13 12:19:51,297 INFO L131 ngComponentsAnalysis]: Automaton has 30 accepting balls. 121863 [2022-12-13 12:19:51,599 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 122380 states to 122380 states and 163658 transitions. [2022-12-13 12:19:51,599 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 122380 [2022-12-13 12:19:51,665 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 122380 [2022-12-13 12:19:51,665 INFO L73 IsDeterministic]: Start isDeterministic. Operand 122380 states and 163658 transitions. [2022-12-13 12:19:51,925 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:19:51,925 INFO L218 hiAutomatonCegarLoop]: Abstraction has 122380 states and 163658 transitions. [2022-12-13 12:19:51,965 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 122380 states and 163658 transitions. [2022-12-13 12:19:52,617 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 122380 to 122380. [2022-12-13 12:19:52,687 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 122380 states, 122380 states have (on average 1.337293675437163) internal successors, (163658), 122379 states have internal predecessors, (163658), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:19:52,997 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 122380 states to 122380 states and 163658 transitions. [2022-12-13 12:19:52,997 INFO L240 hiAutomatonCegarLoop]: Abstraction has 122380 states and 163658 transitions. [2022-12-13 12:19:52,998 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 12:19:52,998 INFO L428 stractBuchiCegarLoop]: Abstraction has 122380 states and 163658 transitions. [2022-12-13 12:19:52,998 INFO L335 stractBuchiCegarLoop]: ======== Iteration 29 ============ [2022-12-13 12:19:52,998 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 122380 states and 163658 transitions. [2022-12-13 12:19:53,259 INFO L131 ngComponentsAnalysis]: Automaton has 30 accepting balls. 121863 [2022-12-13 12:19:53,259 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:19:53,259 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:19:53,260 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:19:53,260 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:19:53,260 INFO L748 eck$LassoCheckResult]: Stem: 2861102#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 2861103#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 2861761#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2861762#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2861733#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 2861734#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2861361#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2861171#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2861172#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 2861154#L556-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 2861155#L561-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 2861731#L566-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 2861497#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2861498#L769 assume !(0 == ~M_E~0); 2861521#L769-2 assume !(0 == ~T1_E~0); 2861522#L774-1 assume !(0 == ~T2_E~0); 2861557#L779-1 assume !(0 == ~T3_E~0); 2861716#L784-1 assume !(0 == ~T4_E~0); 2861494#L789-1 assume !(0 == ~T5_E~0); 2861495#L794-1 assume !(0 == ~T6_E~0); 2861629#L799-1 assume !(0 == ~T7_E~0); 2861501#L804-1 assume !(0 == ~E_M~0); 2861502#L809-1 assume !(0 == ~E_1~0); 2861549#L814-1 assume !(0 == ~E_2~0); 2860903#L819-1 assume !(0 == ~E_3~0); 2860904#L824-1 assume !(0 == ~E_4~0); 2861247#L829-1 assume !(0 == ~E_5~0); 2861818#L834-1 assume !(0 == ~E_6~0); 2861032#L839-1 assume !(0 == ~E_7~0); 2861033#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2861445#L376 assume !(1 == ~m_pc~0); 2861441#L376-2 is_master_triggered_~__retres1~0#1 := 0; 2861442#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2861697#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2860976#L955 assume !(0 != activate_threads_~tmp~1#1); 2860977#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2861351#L395 assume !(1 == ~t1_pc~0); 2861523#L395-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2861698#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2860933#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2860934#L963 assume !(0 != activate_threads_~tmp___0~0#1); 2861449#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2861450#L414 assume !(1 == ~t2_pc~0); 2861035#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2861741#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2861254#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2861255#L971 assume !(0 != activate_threads_~tmp___1~0#1); 2861740#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2861357#L433 assume !(1 == ~t3_pc~0); 2861142#L433-2 is_transmit3_triggered_~__retres1~3#1 := 0; 2861143#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2860901#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2860902#L979 assume !(0 != activate_threads_~tmp___2~0#1); 2861000#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2861001#L452 assume !(1 == ~t4_pc~0); 2861150#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 2861151#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2860994#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2860995#L987 assume !(0 != activate_threads_~tmp___3~0#1); 2861181#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2861182#L471 assume !(1 == ~t5_pc~0); 2861605#L471-2 is_transmit5_triggered_~__retres1~5#1 := 0; 2861165#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2861166#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2861701#L995 assume !(0 != activate_threads_~tmp___4~0#1); 2861803#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2861804#L490 assume !(1 == ~t6_pc~0); 2861447#L490-2 is_transmit6_triggered_~__retres1~6#1 := 0; 2861448#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2861241#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2861242#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 2861368#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2861331#L509 assume !(1 == ~t7_pc~0); 2861332#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 2861123#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2861124#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2861188#L1011 assume !(0 != activate_threads_~tmp___6~0#1); 2861189#L1011-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2861749#L857 assume !(1 == ~M_E~0); 2860983#L857-2 assume !(1 == ~T1_E~0); 2860984#L862-1 assume !(1 == ~T2_E~0); 2861258#L867-1 assume !(1 == ~T3_E~0); 2861264#L872-1 assume !(1 == ~T4_E~0); 2861358#L877-1 assume !(1 == ~T5_E~0); 2861577#L882-1 assume !(1 == ~T6_E~0); 2861768#L887-1 assume !(1 == ~T7_E~0); 2861654#L892-1 assume !(1 == ~E_M~0); 2861655#L897-1 assume !(1 == ~E_1~0); 2861281#L902-1 assume !(1 == ~E_2~0); 2861282#L907-1 assume !(1 == ~E_3~0); 2861593#L912-1 assume !(1 == ~E_4~0); 2861584#L917-1 assume !(1 == ~E_5~0); 2861585#L922-1 assume !(1 == ~E_6~0); 2861822#L927-1 assume !(1 == ~E_7~0); 2861572#L932-1 assume { :end_inline_reset_delta_events } true; 2861573#L1178-2 assume !false; 2939261#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2939262#L744 [2022-12-13 12:19:53,260 INFO L750 eck$LassoCheckResult]: Loop: 2939262#L744 assume !false; 2952199#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 2952196#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 2952193#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 2952191#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 2952189#L641 assume 0 != eval_~tmp~0#1; 2952187#L641-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 2952185#L649 assume !(0 != eval_~tmp_ndt_1~0#1); 2952183#L646 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 2952181#L663 assume !(0 != eval_~tmp_ndt_2~0#1); 2952179#L660 assume !(0 == ~t2_st~0); 2952171#L674 assume !(0 == ~t3_st~0); 2952167#L688 assume !(0 == ~t4_st~0); 2952211#L702 assume !(0 == ~t5_st~0); 2952208#L716 assume !(0 == ~t6_st~0); 2944007#L730 assume !(0 == ~t7_st~0); 2939262#L744 [2022-12-13 12:19:53,260 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:19:53,261 INFO L85 PathProgramCache]: Analyzing trace with hash 1859704647, now seen corresponding path program 2 times [2022-12-13 12:19:53,261 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:19:53,261 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1039212957] [2022-12-13 12:19:53,261 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:19:53,261 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:19:53,267 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 12:19:53,268 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 12:19:53,271 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 12:19:53,283 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 12:19:53,283 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:19:53,283 INFO L85 PathProgramCache]: Analyzing trace with hash -2139482281, now seen corresponding path program 2 times [2022-12-13 12:19:53,283 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:19:53,283 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [742624700] [2022-12-13 12:19:53,283 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:19:53,283 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:19:53,285 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 12:19:53,285 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 12:19:53,286 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 12:19:53,288 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 12:19:53,288 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:19:53,288 INFO L85 PathProgramCache]: Analyzing trace with hash -147348835, now seen corresponding path program 1 times [2022-12-13 12:19:53,288 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:19:53,288 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [339074250] [2022-12-13 12:19:53,289 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:19:53,289 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:19:53,294 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:19:53,311 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:19:53,311 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:19:53,311 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [339074250] [2022-12-13 12:19:53,311 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [339074250] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:19:53,311 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:19:53,311 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:19:53,311 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2039723409] [2022-12-13 12:19:53,311 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:19:53,389 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:19:53,390 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 12:19:53,390 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 12:19:53,390 INFO L87 Difference]: Start difference. First operand 122380 states and 163658 transitions. cyclomatic complexity: 41308 Second operand has 3 states, 3 states have (on average 37.666666666666664) internal successors, (113), 3 states have internal predecessors, (113), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:19:54,053 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:19:54,053 INFO L93 Difference]: Finished difference Result 232205 states and 309337 transitions. [2022-12-13 12:19:54,053 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 232205 states and 309337 transitions. [2022-12-13 12:19:54,762 INFO L131 ngComponentsAnalysis]: Automaton has 30 accepting balls. 231274 [2022-12-13 12:19:55,355 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 232205 states to 232205 states and 309337 transitions. [2022-12-13 12:19:55,355 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 232205 [2022-12-13 12:19:55,428 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 232205 [2022-12-13 12:19:55,428 INFO L73 IsDeterministic]: Start isDeterministic. Operand 232205 states and 309337 transitions. [2022-12-13 12:19:55,506 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:19:55,506 INFO L218 hiAutomatonCegarLoop]: Abstraction has 232205 states and 309337 transitions. [2022-12-13 12:19:55,592 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 232205 states and 309337 transitions. [2022-12-13 12:19:57,172 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 232205 to 220787. [2022-12-13 12:19:57,301 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 220787 states, 220787 states have (on average 1.335961809345659) internal successors, (294963), 220786 states have internal predecessors, (294963), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:19:57,765 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 220787 states to 220787 states and 294963 transitions. [2022-12-13 12:19:57,765 INFO L240 hiAutomatonCegarLoop]: Abstraction has 220787 states and 294963 transitions. [2022-12-13 12:19:57,766 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 12:19:57,767 INFO L428 stractBuchiCegarLoop]: Abstraction has 220787 states and 294963 transitions. [2022-12-13 12:19:57,767 INFO L335 stractBuchiCegarLoop]: ======== Iteration 30 ============ [2022-12-13 12:19:57,767 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 220787 states and 294963 transitions. [2022-12-13 12:19:58,227 INFO L131 ngComponentsAnalysis]: Automaton has 30 accepting balls. 219856 [2022-12-13 12:19:58,227 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:19:58,227 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:19:58,228 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:19:58,228 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:19:58,228 INFO L748 eck$LassoCheckResult]: Stem: 3215696#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 3215697#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 3216365#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3216366#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3216335#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 3216336#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3215951#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3215765#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3215766#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 3215749#L556-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 3215750#L561-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 3216333#L566-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 3216091#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3216092#L769 assume !(0 == ~M_E~0); 3216116#L769-2 assume !(0 == ~T1_E~0); 3216117#L774-1 assume !(0 == ~T2_E~0); 3216148#L779-1 assume !(0 == ~T3_E~0); 3216314#L784-1 assume !(0 == ~T4_E~0); 3216089#L789-1 assume !(0 == ~T5_E~0); 3216090#L794-1 assume !(0 == ~T6_E~0); 3216216#L799-1 assume !(0 == ~T7_E~0); 3216094#L804-1 assume !(0 == ~E_M~0); 3216095#L809-1 assume !(0 == ~E_1~0); 3216139#L814-1 assume !(0 == ~E_2~0); 3215500#L819-1 assume !(0 == ~E_3~0); 3215501#L824-1 assume !(0 == ~E_4~0); 3215836#L829-1 assume !(0 == ~E_5~0); 3216427#L834-1 assume !(0 == ~E_6~0); 3215624#L839-1 assume !(0 == ~E_7~0); 3215625#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3216041#L376 assume !(1 == ~m_pc~0); 3216037#L376-2 is_master_triggered_~__retres1~0#1 := 0; 3216038#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3216293#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 3215568#L955 assume !(0 != activate_threads_~tmp~1#1); 3215569#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3215944#L395 assume !(1 == ~t1_pc~0); 3216118#L395-2 is_transmit1_triggered_~__retres1~1#1 := 0; 3216296#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3215525#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3215526#L963 assume !(0 != activate_threads_~tmp___0~0#1); 3216046#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3216047#L414 assume !(1 == ~t2_pc~0); 3215627#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 3216343#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3215843#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3215844#L971 assume !(0 != activate_threads_~tmp___1~0#1); 3216342#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3215948#L433 assume !(1 == ~t3_pc~0); 3215737#L433-2 is_transmit3_triggered_~__retres1~3#1 := 0; 3215738#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3215494#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3215495#L979 assume !(0 != activate_threads_~tmp___2~0#1); 3215590#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3215591#L452 assume !(1 == ~t4_pc~0); 3215745#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 3215746#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3215584#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3215585#L987 assume !(0 != activate_threads_~tmp___3~0#1); 3215775#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3215776#L471 assume !(1 == ~t5_pc~0); 3216197#L471-2 is_transmit5_triggered_~__retres1~5#1 := 0; 3215759#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3215760#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3216297#L995 assume !(0 != activate_threads_~tmp___4~0#1); 3216413#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3216414#L490 assume !(1 == ~t6_pc~0); 3216043#L490-2 is_transmit6_triggered_~__retres1~6#1 := 0; 3216044#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3215830#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3215831#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 3215960#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3215924#L509 assume !(1 == ~t7_pc~0); 3215925#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 3215721#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3215722#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3215782#L1011 assume !(0 != activate_threads_~tmp___6~0#1); 3215783#L1011-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3216350#L857 assume !(1 == ~M_E~0); 3215573#L857-2 assume !(1 == ~T1_E~0); 3215574#L862-1 assume !(1 == ~T2_E~0); 3215847#L867-1 assume !(1 == ~T3_E~0); 3215853#L872-1 assume !(1 == ~T4_E~0); 3215949#L877-1 assume !(1 == ~T5_E~0); 3216171#L882-1 assume !(1 == ~T6_E~0); 3216374#L887-1 assume !(1 == ~T7_E~0); 3216245#L892-1 assume !(1 == ~E_M~0); 3216246#L897-1 assume !(1 == ~E_1~0); 3215873#L902-1 assume !(1 == ~E_2~0); 3215874#L907-1 assume !(1 == ~E_3~0); 3216187#L912-1 assume !(1 == ~E_4~0); 3216179#L917-1 assume !(1 == ~E_5~0); 3216180#L922-1 assume !(1 == ~E_6~0); 3216431#L927-1 assume !(1 == ~E_7~0); 3216166#L932-1 assume { :end_inline_reset_delta_events } true; 3216167#L1178-2 assume !false; 3363014#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3363012#L744 [2022-12-13 12:19:58,228 INFO L750 eck$LassoCheckResult]: Loop: 3363012#L744 assume !false; 3363013#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 3363005#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 3363007#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 3362999#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 3363000#L641 assume 0 != eval_~tmp~0#1; 3362878#L641-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 3362879#L649 assume !(0 != eval_~tmp_ndt_1~0#1); 3362851#L646 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 3362852#L663 assume !(0 != eval_~tmp_ndt_2~0#1); 3354122#L660 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 3354123#L677 assume !(0 != eval_~tmp_ndt_3~0#1); 3354115#L674 assume !(0 == ~t3_st~0); 3354116#L688 assume !(0 == ~t4_st~0); 3374132#L702 assume !(0 == ~t5_st~0); 3374129#L716 assume !(0 == ~t6_st~0); 3363022#L730 assume !(0 == ~t7_st~0); 3363012#L744 [2022-12-13 12:19:58,229 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:19:58,229 INFO L85 PathProgramCache]: Analyzing trace with hash 1859704647, now seen corresponding path program 3 times [2022-12-13 12:19:58,229 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:19:58,229 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [936547386] [2022-12-13 12:19:58,229 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:19:58,229 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:19:58,235 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 12:19:58,235 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 12:19:58,239 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 12:19:58,250 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 12:19:58,251 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:19:58,251 INFO L85 PathProgramCache]: Analyzing trace with hash -455661331, now seen corresponding path program 1 times [2022-12-13 12:19:58,251 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:19:58,251 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [505184487] [2022-12-13 12:19:58,251 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:19:58,251 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:19:58,253 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 12:19:58,253 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 12:19:58,254 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 12:19:58,255 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 12:19:58,256 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:19:58,256 INFO L85 PathProgramCache]: Analyzing trace with hash 1170933351, now seen corresponding path program 1 times [2022-12-13 12:19:58,256 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:19:58,256 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [942876377] [2022-12-13 12:19:58,256 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:19:58,256 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:19:58,261 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:19:58,277 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:19:58,277 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:19:58,277 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [942876377] [2022-12-13 12:19:58,278 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [942876377] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:19:58,278 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:19:58,278 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:19:58,278 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [30346606] [2022-12-13 12:19:58,278 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:19:58,363 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:19:58,363 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 12:19:58,363 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 12:19:58,363 INFO L87 Difference]: Start difference. First operand 220787 states and 294963 transitions. cyclomatic complexity: 74206 Second operand has 3 states, 3 states have (on average 38.0) internal successors, (114), 3 states have internal predecessors, (114), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:19:59,148 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:19:59,148 INFO L93 Difference]: Finished difference Result 350293 states and 467417 transitions. [2022-12-13 12:19:59,148 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 350293 states and 467417 transitions. [2022-12-13 12:20:00,484 INFO L131 ngComponentsAnalysis]: Automaton has 30 accepting balls. 348810 [2022-12-13 12:20:01,171 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 350293 states to 350293 states and 467417 transitions. [2022-12-13 12:20:01,171 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 350293 [2022-12-13 12:20:01,321 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 350293 [2022-12-13 12:20:01,321 INFO L73 IsDeterministic]: Start isDeterministic. Operand 350293 states and 467417 transitions. [2022-12-13 12:20:01,657 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:20:01,657 INFO L218 hiAutomatonCegarLoop]: Abstraction has 350293 states and 467417 transitions. [2022-12-13 12:20:01,746 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 350293 states and 467417 transitions. [2022-12-13 12:20:03,668 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 350293 to 343521. [2022-12-13 12:20:03,826 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 343521 states, 343521 states have (on average 1.335292456647483) internal successors, (458701), 343520 states have internal predecessors, (458701), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:20:04,301 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 343521 states to 343521 states and 458701 transitions. [2022-12-13 12:20:04,301 INFO L240 hiAutomatonCegarLoop]: Abstraction has 343521 states and 458701 transitions. [2022-12-13 12:20:04,302 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 12:20:04,302 INFO L428 stractBuchiCegarLoop]: Abstraction has 343521 states and 458701 transitions. [2022-12-13 12:20:04,302 INFO L335 stractBuchiCegarLoop]: ======== Iteration 31 ============ [2022-12-13 12:20:04,302 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 343521 states and 458701 transitions. [2022-12-13 12:20:05,351 INFO L131 ngComponentsAnalysis]: Automaton has 30 accepting balls. 342038 [2022-12-13 12:20:05,351 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:20:05,351 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:20:05,352 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:20:05,352 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:20:05,353 INFO L748 eck$LassoCheckResult]: Stem: 3786789#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 3786790#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 3787504#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3787505#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3787473#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 3787474#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3787060#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3786859#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3786860#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 3786843#L556-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 3786844#L561-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 3787472#L566-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 3787213#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3787214#L769 assume !(0 == ~M_E~0); 3787239#L769-2 assume !(0 == ~T1_E~0); 3787240#L774-1 assume !(0 == ~T2_E~0); 3787280#L779-1 assume !(0 == ~T3_E~0); 3787452#L784-1 assume !(0 == ~T4_E~0); 3787210#L789-1 assume !(0 == ~T5_E~0); 3787211#L794-1 assume !(0 == ~T6_E~0); 3787353#L799-1 assume !(0 == ~T7_E~0); 3787216#L804-1 assume !(0 == ~E_M~0); 3787217#L809-1 assume !(0 == ~E_1~0); 3787271#L814-1 assume !(0 == ~E_2~0); 3786588#L819-1 assume !(0 == ~E_3~0); 3786589#L824-1 assume !(0 == ~E_4~0); 3786934#L829-1 assume !(0 == ~E_5~0); 3787564#L834-1 assume !(0 == ~E_6~0); 3786715#L839-1 assume !(0 == ~E_7~0); 3786716#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3787156#L376 assume !(1 == ~m_pc~0); 3787152#L376-2 is_master_triggered_~__retres1~0#1 := 0; 3787153#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3787430#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 3786658#L955 assume !(0 != activate_threads_~tmp~1#1); 3786659#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3787051#L395 assume !(1 == ~t1_pc~0); 3787241#L395-2 is_transmit1_triggered_~__retres1~1#1 := 0; 3787435#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3786613#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3786614#L963 assume !(0 != activate_threads_~tmp___0~0#1); 3787162#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3787163#L414 assume !(1 == ~t2_pc~0); 3786718#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 3787480#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3786942#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3786943#L971 assume !(0 != activate_threads_~tmp___1~0#1); 3787479#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3787057#L433 assume !(1 == ~t3_pc~0); 3786830#L433-2 is_transmit3_triggered_~__retres1~3#1 := 0; 3786831#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3786582#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3786583#L979 assume !(0 != activate_threads_~tmp___2~0#1); 3786681#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3786682#L452 assume !(1 == ~t4_pc~0); 3786839#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 3786840#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3786675#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3786676#L987 assume !(0 != activate_threads_~tmp___3~0#1); 3786869#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3786870#L471 assume !(1 == ~t5_pc~0); 3787332#L471-2 is_transmit5_triggered_~__retres1~5#1 := 0; 3786853#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3786854#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3787436#L995 assume !(0 != activate_threads_~tmp___4~0#1); 3787550#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3787551#L490 assume !(1 == ~t6_pc~0); 3787159#L490-2 is_transmit6_triggered_~__retres1~6#1 := 0; 3787160#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3786928#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3786929#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 3787072#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3787029#L509 assume !(1 == ~t7_pc~0); 3787030#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 3786815#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3786816#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3786876#L1011 assume !(0 != activate_threads_~tmp___6~0#1); 3786877#L1011-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3787492#L857 assume !(1 == ~M_E~0); 3786663#L857-2 assume !(1 == ~T1_E~0); 3786664#L862-1 assume !(1 == ~T2_E~0); 3786946#L867-1 assume !(1 == ~T3_E~0); 3786952#L872-1 assume !(1 == ~T4_E~0); 3787058#L877-1 assume !(1 == ~T5_E~0); 3787302#L882-1 assume !(1 == ~T6_E~0); 3787514#L887-1 assume !(1 == ~T7_E~0); 3787380#L892-1 assume !(1 == ~E_M~0); 3787381#L897-1 assume !(1 == ~E_1~0); 3786974#L902-1 assume !(1 == ~E_2~0); 3786975#L907-1 assume !(1 == ~E_3~0); 3787321#L912-1 assume !(1 == ~E_4~0); 3787309#L917-1 assume !(1 == ~E_5~0); 3787310#L922-1 assume !(1 == ~E_6~0); 3787569#L927-1 assume !(1 == ~E_7~0); 3787297#L932-1 assume { :end_inline_reset_delta_events } true; 3787298#L1178-2 assume !false; 3851114#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3851110#L744 [2022-12-13 12:20:05,353 INFO L750 eck$LassoCheckResult]: Loop: 3851110#L744 assume !false; 3851106#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 3851100#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 3851101#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 3983076#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 3983075#L641 assume 0 != eval_~tmp~0#1; 3851081#L641-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 3851082#L649 assume !(0 != eval_~tmp_ndt_1~0#1); 4020174#L646 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 4020173#L663 assume !(0 != eval_~tmp_ndt_2~0#1); 4020172#L660 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 4020163#L677 assume !(0 != eval_~tmp_ndt_3~0#1); 3849390#L674 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 3849386#L691 assume !(0 != eval_~tmp_ndt_4~0#1); 3849388#L688 assume !(0 == ~t4_st~0); 3849541#L702 assume !(0 == ~t5_st~0); 3849538#L716 assume !(0 == ~t6_st~0); 3851118#L730 assume !(0 == ~t7_st~0); 3851110#L744 [2022-12-13 12:20:05,353 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:20:05,353 INFO L85 PathProgramCache]: Analyzing trace with hash 1859704647, now seen corresponding path program 4 times [2022-12-13 12:20:05,353 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:20:05,353 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1894628178] [2022-12-13 12:20:05,353 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:20:05,354 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:20:05,362 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 12:20:05,362 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 12:20:05,367 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 12:20:05,379 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 12:20:05,379 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:20:05,379 INFO L85 PathProgramCache]: Analyzing trace with hash 745639308, now seen corresponding path program 1 times [2022-12-13 12:20:05,380 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:20:05,380 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [931756538] [2022-12-13 12:20:05,380 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:20:05,380 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:20:05,382 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 12:20:05,383 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 12:20:05,384 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 12:20:05,385 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 12:20:05,386 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:20:05,386 INFO L85 PathProgramCache]: Analyzing trace with hash -369533102, now seen corresponding path program 1 times [2022-12-13 12:20:05,386 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:20:05,386 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [436561378] [2022-12-13 12:20:05,386 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:20:05,386 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:20:05,394 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:20:05,414 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:20:05,414 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:20:05,414 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [436561378] [2022-12-13 12:20:05,414 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [436561378] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:20:05,414 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:20:05,414 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:20:05,414 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [346149470] [2022-12-13 12:20:05,415 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:20:05,527 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:20:05,527 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 12:20:05,527 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 12:20:05,527 INFO L87 Difference]: Start difference. First operand 343521 states and 458701 transitions. cyclomatic complexity: 115210 Second operand has 3 states, 3 states have (on average 38.333333333333336) internal successors, (115), 3 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:20:07,181 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:20:07,182 INFO L93 Difference]: Finished difference Result 640915 states and 855331 transitions. [2022-12-13 12:20:07,182 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 640915 states and 855331 transitions. [2022-12-13 12:20:09,353 INFO L131 ngComponentsAnalysis]: Automaton has 30 accepting balls. 638052 [2022-12-13 12:20:10,487 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 640915 states to 640915 states and 855331 transitions. [2022-12-13 12:20:10,487 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 640915 [2022-12-13 12:20:10,706 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 640915 [2022-12-13 12:20:10,706 INFO L73 IsDeterministic]: Start isDeterministic. Operand 640915 states and 855331 transitions. [2022-12-13 12:20:10,943 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:20:10,943 INFO L218 hiAutomatonCegarLoop]: Abstraction has 640915 states and 855331 transitions. [2022-12-13 12:20:11,178 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 640915 states and 855331 transitions. [2022-12-13 12:20:14,962 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 640915 to 616207. [2022-12-13 12:20:15,241 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 616207 states, 616207 states have (on average 1.3379383875872881) internal successors, (824447), 616206 states have internal predecessors, (824447), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:20:16,598 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 616207 states to 616207 states and 824447 transitions. [2022-12-13 12:20:16,598 INFO L240 hiAutomatonCegarLoop]: Abstraction has 616207 states and 824447 transitions. [2022-12-13 12:20:16,598 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 12:20:16,599 INFO L428 stractBuchiCegarLoop]: Abstraction has 616207 states and 824447 transitions. [2022-12-13 12:20:16,599 INFO L335 stractBuchiCegarLoop]: ======== Iteration 32 ============ [2022-12-13 12:20:16,599 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 616207 states and 824447 transitions. [2022-12-13 12:20:18,187 INFO L131 ngComponentsAnalysis]: Automaton has 30 accepting balls. 613344 [2022-12-13 12:20:18,187 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:20:18,187 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:20:18,188 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:20:18,188 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:20:18,188 INFO L748 eck$LassoCheckResult]: Stem: 4771228#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 4771229#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 4771946#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4771947#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4771912#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 4771913#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4771504#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4771299#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 4771300#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 4771282#L556-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 4771283#L561-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 4771910#L566-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 4771659#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4771660#L769 assume !(0 == ~M_E~0); 4771685#L769-2 assume !(0 == ~T1_E~0); 4771686#L774-1 assume !(0 == ~T2_E~0); 4771718#L779-1 assume !(0 == ~T3_E~0); 4771888#L784-1 assume !(0 == ~T4_E~0); 4771656#L789-1 assume !(0 == ~T5_E~0); 4771657#L794-1 assume !(0 == ~T6_E~0); 4771787#L799-1 assume !(0 == ~T7_E~0); 4771662#L804-1 assume !(0 == ~E_M~0); 4771663#L809-1 assume !(0 == ~E_1~0); 4771710#L814-1 assume !(0 == ~E_2~0); 4771032#L819-1 assume !(0 == ~E_3~0); 4771033#L824-1 assume !(0 == ~E_4~0); 4771377#L829-1 assume !(0 == ~E_5~0); 4772002#L834-1 assume !(0 == ~E_6~0); 4771156#L839-1 assume !(0 == ~E_7~0); 4771157#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4771603#L376 assume !(1 == ~m_pc~0); 4771599#L376-2 is_master_triggered_~__retres1~0#1 := 0; 4771600#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4771866#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4771102#L955 assume !(0 != activate_threads_~tmp~1#1); 4771103#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4771494#L395 assume !(1 == ~t1_pc~0); 4771687#L395-2 is_transmit1_triggered_~__retres1~1#1 := 0; 4771870#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4771058#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4771059#L963 assume !(0 != activate_threads_~tmp___0~0#1); 4771611#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4771612#L414 assume !(1 == ~t2_pc~0); 4771159#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 4771921#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4771383#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4771384#L971 assume !(0 != activate_threads_~tmp___1~0#1); 4771920#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4771501#L433 assume !(1 == ~t3_pc~0); 4771272#L433-2 is_transmit3_triggered_~__retres1~3#1 := 0; 4771273#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4771026#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4771027#L979 assume !(0 != activate_threads_~tmp___2~0#1); 4771125#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4771126#L452 assume !(1 == ~t4_pc~0); 4771278#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 4771279#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4771119#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4771120#L987 assume !(0 != activate_threads_~tmp___3~0#1); 4771309#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4771310#L471 assume !(1 == ~t5_pc~0); 4771767#L471-2 is_transmit5_triggered_~__retres1~5#1 := 0; 4771292#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4771293#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4771871#L995 assume !(0 != activate_threads_~tmp___4~0#1); 4771988#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4771989#L490 assume !(1 == ~t6_pc~0); 4771607#L490-2 is_transmit6_triggered_~__retres1~6#1 := 0; 4771608#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4771371#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4771372#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 4771516#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4771472#L509 assume !(1 == ~t7_pc~0); 4771473#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 4771256#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4771257#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4771316#L1011 assume !(0 != activate_threads_~tmp___6~0#1); 4771317#L1011-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4771931#L857 assume !(1 == ~M_E~0); 4771107#L857-2 assume !(1 == ~T1_E~0); 4771108#L862-1 assume !(1 == ~T2_E~0); 4771387#L867-1 assume !(1 == ~T3_E~0); 4771396#L872-1 assume !(1 == ~T4_E~0); 4771502#L877-1 assume !(1 == ~T5_E~0); 4771739#L882-1 assume !(1 == ~T6_E~0); 4771953#L887-1 assume !(1 == ~T7_E~0); 4771815#L892-1 assume !(1 == ~E_M~0); 4771816#L897-1 assume !(1 == ~E_1~0); 4771418#L902-1 assume !(1 == ~E_2~0); 4771419#L907-1 assume !(1 == ~E_3~0); 4771759#L912-1 assume !(1 == ~E_4~0); 4771746#L917-1 assume !(1 == ~E_5~0); 4771747#L922-1 assume !(1 == ~E_6~0); 4772006#L927-1 assume !(1 == ~E_7~0); 4771734#L932-1 assume { :end_inline_reset_delta_events } true; 4771735#L1178-2 assume !false; 4879408#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4879409#L744 [2022-12-13 12:20:18,188 INFO L750 eck$LassoCheckResult]: Loop: 4879409#L744 assume !false; 5237759#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 5237757#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 5237756#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 5237755#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 5237754#L641 assume 0 != eval_~tmp~0#1; 5237752#L641-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 5237751#L649 assume !(0 != eval_~tmp_ndt_1~0#1); 5237750#L646 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 5237749#L663 assume !(0 != eval_~tmp_ndt_2~0#1); 5237748#L660 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 5237733#L677 assume !(0 != eval_~tmp_ndt_3~0#1); 5237747#L674 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 5237772#L691 assume !(0 != eval_~tmp_ndt_4~0#1); 5237771#L688 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0#1;eval_~tmp_ndt_5~0#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; 5237583#L705 assume !(0 != eval_~tmp_ndt_5~0#1); 5237769#L702 assume !(0 == ~t5_st~0); 5237766#L716 assume !(0 == ~t6_st~0); 5237763#L730 assume !(0 == ~t7_st~0); 4879409#L744 [2022-12-13 12:20:18,188 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:20:18,189 INFO L85 PathProgramCache]: Analyzing trace with hash 1859704647, now seen corresponding path program 5 times [2022-12-13 12:20:18,189 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:20:18,189 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1287511617] [2022-12-13 12:20:18,189 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:20:18,189 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:20:18,195 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 12:20:18,195 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 12:20:18,200 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 12:20:18,212 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 12:20:18,212 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:20:18,212 INFO L85 PathProgramCache]: Analyzing trace with hash 1426962104, now seen corresponding path program 1 times [2022-12-13 12:20:18,212 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:20:18,212 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1201620407] [2022-12-13 12:20:18,212 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:20:18,212 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:20:18,215 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 12:20:18,215 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 12:20:18,217 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 12:20:18,218 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 12:20:18,218 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:20:18,218 INFO L85 PathProgramCache]: Analyzing trace with hash 1216355762, now seen corresponding path program 1 times [2022-12-13 12:20:18,219 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:20:18,219 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [625354168] [2022-12-13 12:20:18,219 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:20:18,219 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:20:18,225 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:20:18,240 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:20:18,240 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:20:18,241 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [625354168] [2022-12-13 12:20:18,241 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [625354168] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:20:18,241 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:20:18,241 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:20:18,241 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1850182995] [2022-12-13 12:20:18,241 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:20:18,379 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:20:18,380 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 12:20:18,380 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 12:20:18,380 INFO L87 Difference]: Start difference. First operand 616207 states and 824447 transitions. cyclomatic complexity: 208270 Second operand has 3 states, 3 states have (on average 38.666666666666664) internal successors, (116), 3 states have internal predecessors, (116), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:20:20,231 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:20:20,231 INFO L93 Difference]: Finished difference Result 755159 states and 1007003 transitions. [2022-12-13 12:20:20,231 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 755159 states and 1007003 transitions. [2022-12-13 12:20:22,903 INFO L131 ngComponentsAnalysis]: Automaton has 30 accepting balls. 752476 [2022-12-13 12:20:24,219 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 755159 states to 755159 states and 1007003 transitions. [2022-12-13 12:20:24,219 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 755159 [2022-12-13 12:20:24,479 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 755159 [2022-12-13 12:20:24,479 INFO L73 IsDeterministic]: Start isDeterministic. Operand 755159 states and 1007003 transitions. [2022-12-13 12:20:24,840 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:20:24,840 INFO L218 hiAutomatonCegarLoop]: Abstraction has 755159 states and 1007003 transitions. [2022-12-13 12:20:25,103 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 755159 states and 1007003 transitions. [2022-12-13 12:20:30,095 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 755159 to 736431. [2022-12-13 12:20:30,433 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 736431 states, 736431 states have (on average 1.3360912291850833) internal successors, (983939), 736430 states have internal predecessors, (983939), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)