./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/token_ring.07.cil-2.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 2329fc70 Calling Ultimate with: /usr/lib/jvm/java-1.11.0-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a5ed5b2d-5486-4af7-9f0d-c9bfd4507727/bin/uautomizer-uyxdKDjOR8/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a5ed5b2d-5486-4af7-9f0d-c9bfd4507727/bin/uautomizer-uyxdKDjOR8/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a5ed5b2d-5486-4af7-9f0d-c9bfd4507727/bin/uautomizer-uyxdKDjOR8/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a5ed5b2d-5486-4af7-9f0d-c9bfd4507727/bin/uautomizer-uyxdKDjOR8/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/token_ring.07.cil-2.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a5ed5b2d-5486-4af7-9f0d-c9bfd4507727/bin/uautomizer-uyxdKDjOR8/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a5ed5b2d-5486-4af7-9f0d-c9bfd4507727/bin/uautomizer-uyxdKDjOR8 --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 32b030e5f1b46150870f8dd8e24821389f0ffe4175e43053767dc9109bffcf9b --- Real Ultimate output --- [0.001s][warning][os,container] Duplicate cpuset controllers detected. Picking /sys/fs/cgroup/cpuset, skipping /sys/fs/cgroup/cpuset. This is Ultimate 0.2.2-dev-2329fc7 [2022-12-13 11:54:17,643 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-12-13 11:54:17,645 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-12-13 11:54:17,685 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-12-13 11:54:17,686 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-12-13 11:54:17,687 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-12-13 11:54:17,688 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-12-13 11:54:17,689 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-12-13 11:54:17,691 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-12-13 11:54:17,691 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-12-13 11:54:17,692 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-12-13 11:54:17,693 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-12-13 11:54:17,694 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-12-13 11:54:17,695 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-12-13 11:54:17,696 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-12-13 11:54:17,697 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-12-13 11:54:17,697 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-12-13 11:54:17,698 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-12-13 11:54:17,700 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-12-13 11:54:17,701 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-12-13 11:54:17,702 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-12-13 11:54:17,704 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-12-13 11:54:17,705 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-12-13 11:54:17,705 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-12-13 11:54:17,708 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-12-13 11:54:17,709 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-12-13 11:54:17,709 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-12-13 11:54:17,710 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-12-13 11:54:17,710 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-12-13 11:54:17,711 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-12-13 11:54:17,711 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-12-13 11:54:17,712 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-12-13 11:54:17,713 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-12-13 11:54:17,713 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-12-13 11:54:17,714 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-12-13 11:54:17,714 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-12-13 11:54:17,715 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-12-13 11:54:17,715 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-12-13 11:54:17,715 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-12-13 11:54:17,716 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-12-13 11:54:17,716 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-12-13 11:54:17,717 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a5ed5b2d-5486-4af7-9f0d-c9bfd4507727/bin/uautomizer-uyxdKDjOR8/config/svcomp-Termination-32bit-Automizer_Default.epf [2022-12-13 11:54:17,737 INFO L113 SettingsManager]: Loading preferences was successful [2022-12-13 11:54:17,737 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-12-13 11:54:17,737 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-12-13 11:54:17,737 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-12-13 11:54:17,738 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-12-13 11:54:17,738 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-12-13 11:54:17,739 INFO L138 SettingsManager]: * Use SBE=true [2022-12-13 11:54:17,739 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2022-12-13 11:54:17,739 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2022-12-13 11:54:17,739 INFO L138 SettingsManager]: * Use old map elimination=false [2022-12-13 11:54:17,739 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2022-12-13 11:54:17,739 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2022-12-13 11:54:17,739 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2022-12-13 11:54:17,740 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-12-13 11:54:17,740 INFO L138 SettingsManager]: * sizeof long=4 [2022-12-13 11:54:17,740 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2022-12-13 11:54:17,740 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-12-13 11:54:17,740 INFO L138 SettingsManager]: * sizeof POINTER=4 [2022-12-13 11:54:17,740 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-12-13 11:54:17,741 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2022-12-13 11:54:17,741 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2022-12-13 11:54:17,741 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2022-12-13 11:54:17,741 INFO L138 SettingsManager]: * sizeof long double=12 [2022-12-13 11:54:17,741 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-12-13 11:54:17,741 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2022-12-13 11:54:17,741 INFO L138 SettingsManager]: * Use constant arrays=true [2022-12-13 11:54:17,742 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2022-12-13 11:54:17,742 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-12-13 11:54:17,742 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-12-13 11:54:17,742 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-12-13 11:54:17,742 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-12-13 11:54:17,743 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-12-13 11:54:17,743 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a5ed5b2d-5486-4af7-9f0d-c9bfd4507727/bin/uautomizer-uyxdKDjOR8/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a5ed5b2d-5486-4af7-9f0d-c9bfd4507727/bin/uautomizer-uyxdKDjOR8 Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 32b030e5f1b46150870f8dd8e24821389f0ffe4175e43053767dc9109bffcf9b [2022-12-13 11:54:17,898 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-12-13 11:54:17,933 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-12-13 11:54:17,936 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-12-13 11:54:17,937 INFO L271 PluginConnector]: Initializing CDTParser... [2022-12-13 11:54:17,938 INFO L275 PluginConnector]: CDTParser initialized [2022-12-13 11:54:17,939 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a5ed5b2d-5486-4af7-9f0d-c9bfd4507727/bin/uautomizer-uyxdKDjOR8/../../sv-benchmarks/c/systemc/token_ring.07.cil-2.c [2022-12-13 11:54:20,617 INFO L500 CDTParser]: Created temporary CDT project at NULL [2022-12-13 11:54:20,754 INFO L351 CDTParser]: Found 1 translation units. [2022-12-13 11:54:20,754 INFO L172 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a5ed5b2d-5486-4af7-9f0d-c9bfd4507727/sv-benchmarks/c/systemc/token_ring.07.cil-2.c [2022-12-13 11:54:20,762 INFO L394 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a5ed5b2d-5486-4af7-9f0d-c9bfd4507727/bin/uautomizer-uyxdKDjOR8/data/a4f4c737e/1b963d7872da447cba5adaf62efbea69/FLAGa6ae0abe5 [2022-12-13 11:54:20,772 INFO L402 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a5ed5b2d-5486-4af7-9f0d-c9bfd4507727/bin/uautomizer-uyxdKDjOR8/data/a4f4c737e/1b963d7872da447cba5adaf62efbea69 [2022-12-13 11:54:20,774 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-12-13 11:54:20,775 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-12-13 11:54:20,776 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-12-13 11:54:20,776 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-12-13 11:54:20,779 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-12-13 11:54:20,780 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.12 11:54:20" (1/1) ... [2022-12-13 11:54:20,780 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@3ed1b711 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 11:54:20, skipping insertion in model container [2022-12-13 11:54:20,780 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.12 11:54:20" (1/1) ... [2022-12-13 11:54:20,787 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-12-13 11:54:20,815 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-12-13 11:54:20,922 WARN L237 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a5ed5b2d-5486-4af7-9f0d-c9bfd4507727/sv-benchmarks/c/systemc/token_ring.07.cil-2.c[671,684] [2022-12-13 11:54:20,990 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-12-13 11:54:21,012 INFO L203 MainTranslator]: Completed pre-run [2022-12-13 11:54:21,021 WARN L237 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a5ed5b2d-5486-4af7-9f0d-c9bfd4507727/sv-benchmarks/c/systemc/token_ring.07.cil-2.c[671,684] [2022-12-13 11:54:21,053 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-12-13 11:54:21,066 INFO L208 MainTranslator]: Completed translation [2022-12-13 11:54:21,066 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 11:54:21 WrapperNode [2022-12-13 11:54:21,066 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-12-13 11:54:21,067 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-12-13 11:54:21,067 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-12-13 11:54:21,067 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-12-13 11:54:21,072 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 11:54:21" (1/1) ... [2022-12-13 11:54:21,080 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 11:54:21" (1/1) ... [2022-12-13 11:54:21,120 INFO L138 Inliner]: procedures = 42, calls = 53, calls flagged for inlining = 48, calls inlined = 135, statements flattened = 2001 [2022-12-13 11:54:21,121 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-12-13 11:54:21,121 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-12-13 11:54:21,121 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-12-13 11:54:21,121 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-12-13 11:54:21,128 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 11:54:21" (1/1) ... [2022-12-13 11:54:21,129 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 11:54:21" (1/1) ... [2022-12-13 11:54:21,133 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 11:54:21" (1/1) ... [2022-12-13 11:54:21,133 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 11:54:21" (1/1) ... [2022-12-13 11:54:21,148 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 11:54:21" (1/1) ... [2022-12-13 11:54:21,159 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 11:54:21" (1/1) ... [2022-12-13 11:54:21,162 INFO L185 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 11:54:21" (1/1) ... [2022-12-13 11:54:21,166 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 11:54:21" (1/1) ... [2022-12-13 11:54:21,172 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-12-13 11:54:21,173 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-12-13 11:54:21,173 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-12-13 11:54:21,173 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-12-13 11:54:21,174 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 11:54:21" (1/1) ... [2022-12-13 11:54:21,179 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-12-13 11:54:21,190 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a5ed5b2d-5486-4af7-9f0d-c9bfd4507727/bin/uautomizer-uyxdKDjOR8/z3 [2022-12-13 11:54:21,202 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a5ed5b2d-5486-4af7-9f0d-c9bfd4507727/bin/uautomizer-uyxdKDjOR8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-12-13 11:54:21,205 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a5ed5b2d-5486-4af7-9f0d-c9bfd4507727/bin/uautomizer-uyxdKDjOR8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2022-12-13 11:54:21,239 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-12-13 11:54:21,239 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-12-13 11:54:21,239 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-12-13 11:54:21,239 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-12-13 11:54:21,325 INFO L235 CfgBuilder]: Building ICFG [2022-12-13 11:54:21,327 INFO L261 CfgBuilder]: Building CFG for each procedure with an implementation [2022-12-13 11:54:22,231 INFO L276 CfgBuilder]: Performing block encoding [2022-12-13 11:54:22,241 INFO L295 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-12-13 11:54:22,241 INFO L300 CfgBuilder]: Removed 10 assume(true) statements. [2022-12-13 11:54:22,243 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.12 11:54:22 BoogieIcfgContainer [2022-12-13 11:54:22,243 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-12-13 11:54:22,244 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2022-12-13 11:54:22,244 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2022-12-13 11:54:22,247 INFO L275 PluginConnector]: BuchiAutomizer initialized [2022-12-13 11:54:22,247 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-12-13 11:54:22,248 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 13.12 11:54:20" (1/3) ... [2022-12-13 11:54:22,248 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@489ecfb1 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 13.12 11:54:22, skipping insertion in model container [2022-12-13 11:54:22,249 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-12-13 11:54:22,249 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 11:54:21" (2/3) ... [2022-12-13 11:54:22,249 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@489ecfb1 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 13.12 11:54:22, skipping insertion in model container [2022-12-13 11:54:22,249 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-12-13 11:54:22,249 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.12 11:54:22" (3/3) ... [2022-12-13 11:54:22,250 INFO L332 chiAutomizerObserver]: Analyzing ICFG token_ring.07.cil-2.c [2022-12-13 11:54:22,301 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2022-12-13 11:54:22,302 INFO L304 stractBuchiCegarLoop]: Hoare is false [2022-12-13 11:54:22,302 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2022-12-13 11:54:22,302 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2022-12-13 11:54:22,302 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2022-12-13 11:54:22,302 INFO L308 stractBuchiCegarLoop]: Difference is false [2022-12-13 11:54:22,302 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2022-12-13 11:54:22,302 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2022-12-13 11:54:22,308 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 843 states, 842 states have (on average 1.520190023752969) internal successors, (1280), 842 states have internal predecessors, (1280), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 11:54:22,342 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 736 [2022-12-13 11:54:22,342 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 11:54:22,342 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 11:54:22,351 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 11:54:22,351 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 11:54:22,351 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2022-12-13 11:54:22,353 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 843 states, 842 states have (on average 1.520190023752969) internal successors, (1280), 842 states have internal predecessors, (1280), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 11:54:22,362 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 736 [2022-12-13 11:54:22,363 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 11:54:22,363 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 11:54:22,365 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 11:54:22,365 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 11:54:22,372 INFO L748 eck$LassoCheckResult]: Stem: 124#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 776#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 615#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 774#update_channels_returnLabel#1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 796#L548true assume !(1 == ~m_i~0);~m_st~0 := 2; 206#L548-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 392#L553-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 286#L558-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 752#L563-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 148#L568-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 41#L573-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 783#L578-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 127#L583-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 497#L781true assume !(0 == ~M_E~0); 812#L781-2true assume !(0 == ~T1_E~0); 836#L786-1true assume !(0 == ~T2_E~0); 21#L791-1true assume !(0 == ~T3_E~0); 376#L796-1true assume !(0 == ~T4_E~0); 347#L801-1true assume !(0 == ~T5_E~0); 378#L806-1true assume 0 == ~T6_E~0;~T6_E~0 := 1; 758#L811-1true assume !(0 == ~T7_E~0); 130#L816-1true assume !(0 == ~E_M~0); 619#L821-1true assume !(0 == ~E_1~0); 37#L826-1true assume !(0 == ~E_2~0); 345#L831-1true assume !(0 == ~E_3~0); 203#L836-1true assume !(0 == ~E_4~0); 499#L841-1true assume !(0 == ~E_5~0); 106#L846-1true assume 0 == ~E_6~0;~E_6~0 := 1; 789#L851-1true assume !(0 == ~E_7~0); 118#L856-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 643#L388true assume !(1 == ~m_pc~0); 115#L388-2true is_master_triggered_~__retres1~0#1 := 0; 470#L399true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 537#is_master_triggered_returnLabel#1true activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 44#L967true assume !(0 != activate_threads_~tmp~1#1); 759#L967-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11#L407true assume 1 == ~t1_pc~0; 405#L408true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 13#L418true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 29#is_transmit1_triggered_returnLabel#1true activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 611#L975true assume !(0 != activate_threads_~tmp___0~0#1); 636#L975-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 178#L426true assume !(1 == ~t2_pc~0); 654#L426-2true is_transmit2_triggered_~__retres1~2#1 := 0; 746#L437true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 191#is_transmit2_triggered_returnLabel#1true activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 738#L983true assume !(0 != activate_threads_~tmp___1~0#1); 837#L983-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 234#L445true assume 1 == ~t3_pc~0; 828#L446true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 509#L456true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10#is_transmit3_triggered_returnLabel#1true activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 432#L991true assume !(0 != activate_threads_~tmp___2~0#1); 504#L991-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 406#L464true assume !(1 == ~t4_pc~0); 120#L464-2true is_transmit4_triggered_~__retres1~4#1 := 0; 52#L475true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 58#is_transmit4_triggered_returnLabel#1true activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 835#L999true assume !(0 != activate_threads_~tmp___3~0#1); 220#L999-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 401#L483true assume 1 == ~t5_pc~0; 730#L484true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 586#L494true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 540#is_transmit5_triggered_returnLabel#1true activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 693#L1007true assume !(0 != activate_threads_~tmp___4~0#1); 169#L1007-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 452#L502true assume 1 == ~t6_pc~0; 374#L503true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 73#L513true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 183#is_transmit6_triggered_returnLabel#1true activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 313#L1015true assume !(0 != activate_threads_~tmp___5~0#1); 552#L1015-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 703#L521true assume !(1 == ~t7_pc~0); 658#L521-2true is_transmit7_triggered_~__retres1~7#1 := 0; 42#L532true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 790#is_transmit7_triggered_returnLabel#1true activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 600#L1023true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 562#L1023-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 460#L869true assume !(1 == ~M_E~0); 216#L869-2true assume !(1 == ~T1_E~0); 731#L874-1true assume !(1 == ~T2_E~0); 678#L879-1true assume !(1 == ~T3_E~0); 263#L884-1true assume 1 == ~T4_E~0;~T4_E~0 := 2; 5#L889-1true assume !(1 == ~T5_E~0); 134#L894-1true assume !(1 == ~T6_E~0); 826#L899-1true assume !(1 == ~T7_E~0); 422#L904-1true assume !(1 == ~E_M~0); 231#L909-1true assume !(1 == ~E_1~0); 362#L914-1true assume !(1 == ~E_2~0); 385#L919-1true assume !(1 == ~E_3~0); 177#L924-1true assume 1 == ~E_4~0;~E_4~0 := 2; 89#L929-1true assume !(1 == ~E_5~0); 697#L934-1true assume !(1 == ~E_6~0); 218#L939-1true assume !(1 == ~E_7~0); 551#L944-1true assume { :end_inline_reset_delta_events } true; 547#L1190-2true [2022-12-13 11:54:22,373 INFO L750 eck$LassoCheckResult]: Loop: 547#L1190-2true assume !false; 131#L1191true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 270#L756true assume !true; 483#eval_returnLabel#1true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 293#update_channels_returnLabel#2true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 389#L781-3true assume 0 == ~M_E~0;~M_E~0 := 1; 59#L781-5true assume !(0 == ~T1_E~0); 246#L786-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 299#L791-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 34#L796-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 624#L801-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 170#L806-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 294#L811-3true assume 0 == ~T7_E~0;~T7_E~0 := 1; 489#L816-3true assume 0 == ~E_M~0;~E_M~0 := 1; 655#L821-3true assume !(0 == ~E_1~0); 769#L826-3true assume 0 == ~E_2~0;~E_2~0 := 1; 428#L831-3true assume 0 == ~E_3~0;~E_3~0 := 1; 670#L836-3true assume 0 == ~E_4~0;~E_4~0 := 1; 111#L841-3true assume 0 == ~E_5~0;~E_5~0 := 1; 599#L846-3true assume 0 == ~E_6~0;~E_6~0 := 1; 312#L851-3true assume 0 == ~E_7~0;~E_7~0 := 1; 55#L856-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 751#L388-27true assume 1 == ~m_pc~0; 601#L389-9true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 765#L399-9true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 449#is_master_triggered_returnLabel#10true activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 701#L967-27true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 150#L967-29true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 450#L407-27true assume 1 == ~t1_pc~0; 433#L408-9true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 532#L418-9true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 356#is_transmit1_triggered_returnLabel#10true activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 474#L975-27true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 329#L975-29true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 107#L426-27true assume 1 == ~t2_pc~0; 681#L427-9true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 112#L437-9true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 429#is_transmit2_triggered_returnLabel#10true activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 699#L983-27true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 595#L983-29true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 289#L445-27true assume !(1 == ~t3_pc~0); 766#L445-29true is_transmit3_triggered_~__retres1~3#1 := 0; 32#L456-9true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 290#is_transmit3_triggered_returnLabel#10true activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 844#L991-27true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 367#L991-29true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 165#L464-27true assume 1 == ~t4_pc~0; 475#L465-9true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 65#L475-9true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 244#is_transmit4_triggered_returnLabel#10true activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 295#L999-27true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 103#L999-29true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 786#L483-27true assume 1 == ~t5_pc~0; 519#L484-9true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 56#L494-9true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 556#is_transmit5_triggered_returnLabel#10true activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 544#L1007-27true assume !(0 != activate_threads_~tmp___4~0#1); 814#L1007-29true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 709#L502-27true assume !(1 == ~t6_pc~0); 308#L502-29true is_transmit6_triggered_~__retres1~6#1 := 0; 698#L513-9true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 682#is_transmit6_triggered_returnLabel#10true activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 455#L1015-27true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 743#L1015-29true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6#L521-27true assume 1 == ~t7_pc~0; 186#L522-9true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 777#L532-9true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 157#is_transmit7_triggered_returnLabel#10true activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 30#L1023-27true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 320#L1023-29true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 669#L869-3true assume 1 == ~M_E~0;~M_E~0 := 2; 453#L869-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 245#L874-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 282#L879-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 311#L884-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 276#L889-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 84#L894-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 416#L899-3true assume !(1 == ~T7_E~0); 96#L904-3true assume 1 == ~E_M~0;~E_M~0 := 2; 260#L909-3true assume 1 == ~E_1~0;~E_1~0 := 2; 74#L914-3true assume 1 == ~E_2~0;~E_2~0 := 2; 93#L919-3true assume 1 == ~E_3~0;~E_3~0 := 2; 612#L924-3true assume 1 == ~E_4~0;~E_4~0 := 2; 439#L929-3true assume 1 == ~E_5~0;~E_5~0 := 2; 365#L934-3true assume 1 == ~E_6~0;~E_6~0 := 2; 558#L939-3true assume !(1 == ~E_7~0); 99#L944-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 594#L596-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 665#L638-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 163#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 782#L1209true assume !(0 == start_simulation_~tmp~3#1); 305#L1209-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 292#L596-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 536#L638-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 27#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 602#L1164true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 25#L1171true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 306#stop_simulation_returnLabel#1true start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 125#L1222true assume !(0 != start_simulation_~tmp___0~1#1); 547#L1190-2true [2022-12-13 11:54:22,377 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 11:54:22,378 INFO L85 PathProgramCache]: Analyzing trace with hash 1617538625, now seen corresponding path program 1 times [2022-12-13 11:54:22,395 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 11:54:22,395 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1402558847] [2022-12-13 11:54:22,395 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 11:54:22,396 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 11:54:22,467 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 11:54:22,561 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 11:54:22,562 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 11:54:22,562 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1402558847] [2022-12-13 11:54:22,562 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1402558847] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 11:54:22,563 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 11:54:22,563 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 11:54:22,564 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [738341969] [2022-12-13 11:54:22,565 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 11:54:22,568 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 11:54:22,569 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 11:54:22,569 INFO L85 PathProgramCache]: Analyzing trace with hash 205817869, now seen corresponding path program 1 times [2022-12-13 11:54:22,569 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 11:54:22,569 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [818993262] [2022-12-13 11:54:22,569 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 11:54:22,569 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 11:54:22,578 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 11:54:22,602 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 11:54:22,602 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 11:54:22,602 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [818993262] [2022-12-13 11:54:22,603 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [818993262] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 11:54:22,603 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 11:54:22,603 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-12-13 11:54:22,603 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [204328159] [2022-12-13 11:54:22,603 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 11:54:22,604 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 11:54:22,605 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 11:54:22,628 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 11:54:22,628 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 11:54:22,630 INFO L87 Difference]: Start difference. First operand has 843 states, 842 states have (on average 1.520190023752969) internal successors, (1280), 842 states have internal predecessors, (1280), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 11:54:22,679 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 11:54:22,679 INFO L93 Difference]: Finished difference Result 841 states and 1255 transitions. [2022-12-13 11:54:22,680 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 841 states and 1255 transitions. [2022-12-13 11:54:22,685 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 732 [2022-12-13 11:54:22,692 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 841 states to 835 states and 1249 transitions. [2022-12-13 11:54:22,693 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 835 [2022-12-13 11:54:22,694 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 835 [2022-12-13 11:54:22,694 INFO L73 IsDeterministic]: Start isDeterministic. Operand 835 states and 1249 transitions. [2022-12-13 11:54:22,697 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 11:54:22,697 INFO L218 hiAutomatonCegarLoop]: Abstraction has 835 states and 1249 transitions. [2022-12-13 11:54:22,712 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 835 states and 1249 transitions. [2022-12-13 11:54:22,733 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 835 to 835. [2022-12-13 11:54:22,735 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 835 states, 835 states have (on average 1.495808383233533) internal successors, (1249), 834 states have internal predecessors, (1249), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 11:54:22,737 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 835 states to 835 states and 1249 transitions. [2022-12-13 11:54:22,737 INFO L240 hiAutomatonCegarLoop]: Abstraction has 835 states and 1249 transitions. [2022-12-13 11:54:22,738 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 11:54:22,742 INFO L428 stractBuchiCegarLoop]: Abstraction has 835 states and 1249 transitions. [2022-12-13 11:54:22,742 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2022-12-13 11:54:22,742 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 835 states and 1249 transitions. [2022-12-13 11:54:22,745 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 732 [2022-12-13 11:54:22,745 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 11:54:22,745 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 11:54:22,747 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 11:54:22,747 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 11:54:22,747 INFO L748 eck$LassoCheckResult]: Stem: 1938#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 1939#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 2483#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2484#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2523#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 2076#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2077#L553-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 2197#L558-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 2198#L563-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1981#L568-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 1778#L573-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 1779#L578-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 1943#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1944#L781 assume !(0 == ~M_E~0); 2417#L781-2 assume !(0 == ~T1_E~0); 2526#L786-1 assume !(0 == ~T2_E~0); 1738#L791-1 assume !(0 == ~T3_E~0); 1739#L796-1 assume !(0 == ~T4_E~0); 2268#L801-1 assume !(0 == ~T5_E~0); 2269#L806-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 2299#L811-1 assume !(0 == ~T7_E~0); 1950#L816-1 assume !(0 == ~E_M~0); 1951#L821-1 assume !(0 == ~E_1~0); 1769#L826-1 assume !(0 == ~E_2~0); 1770#L831-1 assume !(0 == ~E_3~0); 2071#L836-1 assume !(0 == ~E_4~0); 2072#L841-1 assume !(0 == ~E_5~0); 1904#L846-1 assume 0 == ~E_6~0;~E_6~0 := 1; 1905#L851-1 assume !(0 == ~E_7~0); 1928#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1929#L388 assume !(1 == ~m_pc~0); 1922#L388-2 is_master_triggered_~__retres1~0#1 := 0; 1923#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2395#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1784#L967 assume !(0 != activate_threads_~tmp~1#1); 1785#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1714#L407 assume 1 == ~t1_pc~0; 1715#L408 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1719#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1720#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1755#L975 assume !(0 != activate_threads_~tmp___0~0#1); 2481#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2032#L426 assume !(1 == ~t2_pc~0); 2033#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2498#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2053#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2054#L983 assume !(0 != activate_threads_~tmp___1~0#1); 2519#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2116#L445 assume 1 == ~t3_pc~0; 2117#L446 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 2423#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1712#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1713#L991 assume !(0 != activate_threads_~tmp___2~0#1); 2358#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2326#L464 assume !(1 == ~t4_pc~0); 1932#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1804#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1805#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1816#L999 assume !(0 != activate_threads_~tmp___3~0#1); 2096#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2097#L483 assume 1 == ~t5_pc~0; 2322#L484 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 2463#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2436#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2437#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 2015#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2016#L502 assume 1 == ~t6_pc~0; 2296#L503 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1844#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1845#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2039#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 2234#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2446#L521 assume !(1 == ~t7_pc~0); 2478#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1780#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1781#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2472#L1023 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 2450#L1023-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2386#L869 assume !(1 == ~M_E~0); 2090#L869-2 assume !(1 == ~T1_E~0); 2091#L874-1 assume !(1 == ~T2_E~0); 2506#L879-1 assume !(1 == ~T3_E~0); 2162#L884-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1700#L889-1 assume !(1 == ~T5_E~0); 1701#L894-1 assume !(1 == ~T6_E~0); 1957#L899-1 assume !(1 == ~T7_E~0); 2347#L904-1 assume !(1 == ~E_M~0); 2112#L909-1 assume !(1 == ~E_1~0); 2113#L914-1 assume !(1 == ~E_2~0); 2284#L919-1 assume !(1 == ~E_3~0); 2031#L924-1 assume 1 == ~E_4~0;~E_4~0 := 2; 1875#L929-1 assume !(1 == ~E_5~0); 1876#L934-1 assume !(1 == ~E_6~0); 2092#L939-1 assume !(1 == ~E_7~0); 2093#L944-1 assume { :end_inline_reset_delta_events } true; 1941#L1190-2 [2022-12-13 11:54:22,747 INFO L750 eck$LassoCheckResult]: Loop: 1941#L1190-2 assume !false; 1952#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1953#L756 assume !false; 2176#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 2524#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1797#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 2078#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 2079#L653 assume !(0 != eval_~tmp~0#1); 2129#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2207#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2208#L781-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1817#L781-5 assume !(0 == ~T1_E~0); 1818#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2135#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1763#L796-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1764#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2017#L806-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 2018#L811-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 2209#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2409#L821-3 assume !(0 == ~E_1~0); 2499#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2351#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2352#L836-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1915#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1916#L846-3 assume 0 == ~E_6~0;~E_6~0 := 1; 2233#L851-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1811#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1812#L388-27 assume 1 == ~m_pc~0; 2473#L389-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 2475#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2376#is_master_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2377#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1984#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1985#L407-27 assume 1 == ~t1_pc~0; 2359#L408-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2360#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2278#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2279#L975-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2253#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1906#L426-27 assume !(1 == ~t2_pc~0); 1907#L426-29 is_transmit2_triggered_~__retres1~2#1 := 0; 1920#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1921#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2353#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2470#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2201#L445-27 assume 1 == ~t3_pc~0; 2174#L446-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1760#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1761#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2202#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2289#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2007#L464-27 assume 1 == ~t4_pc~0; 2008#L465-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1759#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1830#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2132#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1899#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1900#L483-27 assume 1 == ~t5_pc~0; 2428#L484-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1813#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1814#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2441#L1007-27 assume !(0 != activate_threads_~tmp___4~0#1); 2442#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2510#L502-27 assume !(1 == ~t6_pc~0); 2227#L502-29 is_transmit6_triggered_~__retres1~6#1 := 0; 2228#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2507#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2382#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 2383#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1702#L521-27 assume !(1 == ~t7_pc~0); 1703#L521-29 is_transmit7_triggered_~__retres1~7#1 := 0; 2044#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1996#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1756#L1023-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1757#L1023-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2243#L869-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2379#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2133#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2134#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2193#L884-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2186#L889-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1865#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1866#L899-3 assume !(1 == ~T7_E~0); 1886#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1887#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1846#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1847#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1881#L924-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2366#L929-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2286#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 2287#L939-3 assume !(1 == ~E_7~0); 1891#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1892#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1722#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 2004#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 2005#L1209 assume !(0 == start_simulation_~tmp~3#1); 2223#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 2206#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1859#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1751#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 1752#L1164 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1747#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1748#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 1940#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 1941#L1190-2 [2022-12-13 11:54:22,748 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 11:54:22,748 INFO L85 PathProgramCache]: Analyzing trace with hash -736846657, now seen corresponding path program 1 times [2022-12-13 11:54:22,748 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 11:54:22,748 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2016938836] [2022-12-13 11:54:22,748 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 11:54:22,749 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 11:54:22,761 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 11:54:22,805 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 11:54:22,805 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 11:54:22,805 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2016938836] [2022-12-13 11:54:22,805 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2016938836] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 11:54:22,806 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 11:54:22,806 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 11:54:22,806 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [790526239] [2022-12-13 11:54:22,806 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 11:54:22,806 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 11:54:22,807 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 11:54:22,807 INFO L85 PathProgramCache]: Analyzing trace with hash -350291807, now seen corresponding path program 1 times [2022-12-13 11:54:22,808 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 11:54:22,808 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1739236134] [2022-12-13 11:54:22,808 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 11:54:22,808 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 11:54:22,828 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 11:54:22,878 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 11:54:22,878 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 11:54:22,879 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1739236134] [2022-12-13 11:54:22,879 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1739236134] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 11:54:22,879 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 11:54:22,879 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 11:54:22,879 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1547195381] [2022-12-13 11:54:22,879 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 11:54:22,880 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 11:54:22,880 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 11:54:22,880 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 11:54:22,881 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 11:54:22,881 INFO L87 Difference]: Start difference. First operand 835 states and 1249 transitions. cyclomatic complexity: 415 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 11:54:22,899 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 11:54:22,899 INFO L93 Difference]: Finished difference Result 835 states and 1248 transitions. [2022-12-13 11:54:22,899 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 835 states and 1248 transitions. [2022-12-13 11:54:22,903 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 732 [2022-12-13 11:54:22,905 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 835 states to 835 states and 1248 transitions. [2022-12-13 11:54:22,905 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 835 [2022-12-13 11:54:22,906 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 835 [2022-12-13 11:54:22,906 INFO L73 IsDeterministic]: Start isDeterministic. Operand 835 states and 1248 transitions. [2022-12-13 11:54:22,908 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 11:54:22,908 INFO L218 hiAutomatonCegarLoop]: Abstraction has 835 states and 1248 transitions. [2022-12-13 11:54:22,909 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 835 states and 1248 transitions. [2022-12-13 11:54:22,917 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 835 to 835. [2022-12-13 11:54:22,918 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 835 states, 835 states have (on average 1.4946107784431137) internal successors, (1248), 834 states have internal predecessors, (1248), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 11:54:22,920 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 835 states to 835 states and 1248 transitions. [2022-12-13 11:54:22,920 INFO L240 hiAutomatonCegarLoop]: Abstraction has 835 states and 1248 transitions. [2022-12-13 11:54:22,920 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 11:54:22,921 INFO L428 stractBuchiCegarLoop]: Abstraction has 835 states and 1248 transitions. [2022-12-13 11:54:22,921 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2022-12-13 11:54:22,921 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 835 states and 1248 transitions. [2022-12-13 11:54:22,924 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 732 [2022-12-13 11:54:22,924 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 11:54:22,924 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 11:54:22,925 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 11:54:22,925 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 11:54:22,925 INFO L748 eck$LassoCheckResult]: Stem: 3615#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 3616#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 4160#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4161#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4200#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 3753#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3754#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3874#L558-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 3875#L563-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 3658#L568-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 3455#L573-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 3456#L578-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 3620#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3621#L781 assume !(0 == ~M_E~0); 4094#L781-2 assume !(0 == ~T1_E~0); 4203#L786-1 assume !(0 == ~T2_E~0); 3415#L791-1 assume !(0 == ~T3_E~0); 3416#L796-1 assume !(0 == ~T4_E~0); 3945#L801-1 assume !(0 == ~T5_E~0); 3946#L806-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 3976#L811-1 assume !(0 == ~T7_E~0); 3627#L816-1 assume !(0 == ~E_M~0); 3628#L821-1 assume !(0 == ~E_1~0); 3446#L826-1 assume !(0 == ~E_2~0); 3447#L831-1 assume !(0 == ~E_3~0); 3748#L836-1 assume !(0 == ~E_4~0); 3749#L841-1 assume !(0 == ~E_5~0); 3581#L846-1 assume 0 == ~E_6~0;~E_6~0 := 1; 3582#L851-1 assume !(0 == ~E_7~0); 3605#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3606#L388 assume !(1 == ~m_pc~0); 3599#L388-2 is_master_triggered_~__retres1~0#1 := 0; 3600#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4072#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3461#L967 assume !(0 != activate_threads_~tmp~1#1); 3462#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3391#L407 assume 1 == ~t1_pc~0; 3392#L408 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3396#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3397#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3432#L975 assume !(0 != activate_threads_~tmp___0~0#1); 4158#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3709#L426 assume !(1 == ~t2_pc~0); 3710#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 4175#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3730#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3731#L983 assume !(0 != activate_threads_~tmp___1~0#1); 4196#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3793#L445 assume 1 == ~t3_pc~0; 3794#L446 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 4100#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3389#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3390#L991 assume !(0 != activate_threads_~tmp___2~0#1); 4035#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4003#L464 assume !(1 == ~t4_pc~0); 3609#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 3481#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3482#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3493#L999 assume !(0 != activate_threads_~tmp___3~0#1); 3773#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3774#L483 assume 1 == ~t5_pc~0; 3999#L484 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 4140#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4113#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4114#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 3692#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3693#L502 assume 1 == ~t6_pc~0; 3973#L503 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 3521#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3522#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3716#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 3911#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4123#L521 assume !(1 == ~t7_pc~0); 4155#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 3457#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3458#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4149#L1023 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 4127#L1023-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4063#L869 assume !(1 == ~M_E~0); 3767#L869-2 assume !(1 == ~T1_E~0); 3768#L874-1 assume !(1 == ~T2_E~0); 4183#L879-1 assume !(1 == ~T3_E~0); 3839#L884-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3377#L889-1 assume !(1 == ~T5_E~0); 3378#L894-1 assume !(1 == ~T6_E~0); 3634#L899-1 assume !(1 == ~T7_E~0); 4024#L904-1 assume !(1 == ~E_M~0); 3789#L909-1 assume !(1 == ~E_1~0); 3790#L914-1 assume !(1 == ~E_2~0); 3961#L919-1 assume !(1 == ~E_3~0); 3708#L924-1 assume 1 == ~E_4~0;~E_4~0 := 2; 3552#L929-1 assume !(1 == ~E_5~0); 3553#L934-1 assume !(1 == ~E_6~0); 3769#L939-1 assume !(1 == ~E_7~0); 3770#L944-1 assume { :end_inline_reset_delta_events } true; 3618#L1190-2 [2022-12-13 11:54:22,926 INFO L750 eck$LassoCheckResult]: Loop: 3618#L1190-2 assume !false; 3629#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3630#L756 assume !false; 3853#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 4201#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 3474#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 3755#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 3756#L653 assume !(0 != eval_~tmp~0#1); 3806#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3884#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3885#L781-3 assume 0 == ~M_E~0;~M_E~0 := 1; 3494#L781-5 assume !(0 == ~T1_E~0); 3495#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3812#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3440#L796-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3441#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 3694#L806-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 3695#L811-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 3886#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 4086#L821-3 assume !(0 == ~E_1~0); 4176#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4028#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4029#L836-3 assume 0 == ~E_4~0;~E_4~0 := 1; 3592#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 3593#L846-3 assume 0 == ~E_6~0;~E_6~0 := 1; 3910#L851-3 assume 0 == ~E_7~0;~E_7~0 := 1; 3488#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3489#L388-27 assume 1 == ~m_pc~0; 4150#L389-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 4152#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4053#is_master_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4054#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3661#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3662#L407-27 assume 1 == ~t1_pc~0; 4036#L408-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4037#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3955#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3956#L975-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3930#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3583#L426-27 assume !(1 == ~t2_pc~0); 3584#L426-29 is_transmit2_triggered_~__retres1~2#1 := 0; 3597#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3598#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4030#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4147#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3878#L445-27 assume 1 == ~t3_pc~0; 3851#L446-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3437#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3438#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3879#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3966#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3684#L464-27 assume 1 == ~t4_pc~0; 3685#L465-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3436#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3507#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3809#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 3576#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3577#L483-27 assume 1 == ~t5_pc~0; 4105#L484-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 3490#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3491#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4118#L1007-27 assume !(0 != activate_threads_~tmp___4~0#1); 4119#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4187#L502-27 assume !(1 == ~t6_pc~0); 3904#L502-29 is_transmit6_triggered_~__retres1~6#1 := 0; 3905#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4184#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4059#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 4060#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3379#L521-27 assume !(1 == ~t7_pc~0); 3380#L521-29 is_transmit7_triggered_~__retres1~7#1 := 0; 3721#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3673#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3433#L1023-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 3434#L1023-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3920#L869-3 assume 1 == ~M_E~0;~M_E~0 := 2; 4056#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3810#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3811#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3870#L884-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3863#L889-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3542#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 3543#L899-3 assume !(1 == ~T7_E~0); 3563#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 3564#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3523#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3524#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3558#L924-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4043#L929-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3963#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 3964#L939-3 assume !(1 == ~E_7~0); 3568#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 3569#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 3399#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 3681#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 3682#L1209 assume !(0 == start_simulation_~tmp~3#1); 3900#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 3883#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 3536#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 3428#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 3429#L1164 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3424#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3425#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 3617#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 3618#L1190-2 [2022-12-13 11:54:22,926 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 11:54:22,926 INFO L85 PathProgramCache]: Analyzing trace with hash 33886909, now seen corresponding path program 1 times [2022-12-13 11:54:22,926 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 11:54:22,926 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [434816775] [2022-12-13 11:54:22,927 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 11:54:22,927 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 11:54:22,936 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 11:54:22,960 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 11:54:22,960 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 11:54:22,960 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [434816775] [2022-12-13 11:54:22,960 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [434816775] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 11:54:22,960 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 11:54:22,961 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 11:54:22,961 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1229718292] [2022-12-13 11:54:22,961 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 11:54:22,961 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 11:54:22,962 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 11:54:22,962 INFO L85 PathProgramCache]: Analyzing trace with hash -350291807, now seen corresponding path program 2 times [2022-12-13 11:54:22,962 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 11:54:22,962 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [767627612] [2022-12-13 11:54:22,962 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 11:54:22,963 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 11:54:22,976 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 11:54:23,033 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 11:54:23,033 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 11:54:23,033 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [767627612] [2022-12-13 11:54:23,033 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [767627612] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 11:54:23,034 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 11:54:23,034 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 11:54:23,034 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [847150913] [2022-12-13 11:54:23,034 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 11:54:23,035 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 11:54:23,035 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 11:54:23,035 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 11:54:23,035 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 11:54:23,036 INFO L87 Difference]: Start difference. First operand 835 states and 1248 transitions. cyclomatic complexity: 414 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 11:54:23,054 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 11:54:23,055 INFO L93 Difference]: Finished difference Result 835 states and 1247 transitions. [2022-12-13 11:54:23,055 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 835 states and 1247 transitions. [2022-12-13 11:54:23,059 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 732 [2022-12-13 11:54:23,061 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 835 states to 835 states and 1247 transitions. [2022-12-13 11:54:23,062 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 835 [2022-12-13 11:54:23,062 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 835 [2022-12-13 11:54:23,062 INFO L73 IsDeterministic]: Start isDeterministic. Operand 835 states and 1247 transitions. [2022-12-13 11:54:23,063 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 11:54:23,064 INFO L218 hiAutomatonCegarLoop]: Abstraction has 835 states and 1247 transitions. [2022-12-13 11:54:23,065 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 835 states and 1247 transitions. [2022-12-13 11:54:23,073 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 835 to 835. [2022-12-13 11:54:23,074 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 835 states, 835 states have (on average 1.4934131736526945) internal successors, (1247), 834 states have internal predecessors, (1247), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 11:54:23,076 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 835 states to 835 states and 1247 transitions. [2022-12-13 11:54:23,077 INFO L240 hiAutomatonCegarLoop]: Abstraction has 835 states and 1247 transitions. [2022-12-13 11:54:23,077 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 11:54:23,078 INFO L428 stractBuchiCegarLoop]: Abstraction has 835 states and 1247 transitions. [2022-12-13 11:54:23,078 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2022-12-13 11:54:23,078 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 835 states and 1247 transitions. [2022-12-13 11:54:23,081 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 732 [2022-12-13 11:54:23,081 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 11:54:23,081 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 11:54:23,082 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 11:54:23,082 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 11:54:23,083 INFO L748 eck$LassoCheckResult]: Stem: 5292#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 5293#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 5837#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5838#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5877#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 5430#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5431#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5551#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 5552#L563-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 5335#L568-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 5132#L573-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 5133#L578-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 5297#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5298#L781 assume !(0 == ~M_E~0); 5771#L781-2 assume !(0 == ~T1_E~0); 5880#L786-1 assume !(0 == ~T2_E~0); 5092#L791-1 assume !(0 == ~T3_E~0); 5093#L796-1 assume !(0 == ~T4_E~0); 5622#L801-1 assume !(0 == ~T5_E~0); 5623#L806-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 5653#L811-1 assume !(0 == ~T7_E~0); 5304#L816-1 assume !(0 == ~E_M~0); 5305#L821-1 assume !(0 == ~E_1~0); 5123#L826-1 assume !(0 == ~E_2~0); 5124#L831-1 assume !(0 == ~E_3~0); 5425#L836-1 assume !(0 == ~E_4~0); 5426#L841-1 assume !(0 == ~E_5~0); 5258#L846-1 assume 0 == ~E_6~0;~E_6~0 := 1; 5259#L851-1 assume !(0 == ~E_7~0); 5282#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5283#L388 assume !(1 == ~m_pc~0); 5276#L388-2 is_master_triggered_~__retres1~0#1 := 0; 5277#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5749#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 5138#L967 assume !(0 != activate_threads_~tmp~1#1); 5139#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5068#L407 assume 1 == ~t1_pc~0; 5069#L408 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 5073#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5074#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5109#L975 assume !(0 != activate_threads_~tmp___0~0#1); 5835#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5386#L426 assume !(1 == ~t2_pc~0); 5387#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 5852#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5407#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 5408#L983 assume !(0 != activate_threads_~tmp___1~0#1); 5873#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5470#L445 assume 1 == ~t3_pc~0; 5471#L446 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 5777#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5066#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 5067#L991 assume !(0 != activate_threads_~tmp___2~0#1); 5712#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5680#L464 assume !(1 == ~t4_pc~0); 5286#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 5158#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5159#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 5170#L999 assume !(0 != activate_threads_~tmp___3~0#1); 5450#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5451#L483 assume 1 == ~t5_pc~0; 5676#L484 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 5817#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5790#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 5791#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 5369#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 5370#L502 assume 1 == ~t6_pc~0; 5650#L503 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 5198#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5199#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 5393#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 5588#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5800#L521 assume !(1 == ~t7_pc~0); 5832#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 5134#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5135#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 5826#L1023 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 5804#L1023-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5740#L869 assume !(1 == ~M_E~0); 5444#L869-2 assume !(1 == ~T1_E~0); 5445#L874-1 assume !(1 == ~T2_E~0); 5860#L879-1 assume !(1 == ~T3_E~0); 5516#L884-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5054#L889-1 assume !(1 == ~T5_E~0); 5055#L894-1 assume !(1 == ~T6_E~0); 5311#L899-1 assume !(1 == ~T7_E~0); 5701#L904-1 assume !(1 == ~E_M~0); 5466#L909-1 assume !(1 == ~E_1~0); 5467#L914-1 assume !(1 == ~E_2~0); 5638#L919-1 assume !(1 == ~E_3~0); 5385#L924-1 assume 1 == ~E_4~0;~E_4~0 := 2; 5229#L929-1 assume !(1 == ~E_5~0); 5230#L934-1 assume !(1 == ~E_6~0); 5446#L939-1 assume !(1 == ~E_7~0); 5447#L944-1 assume { :end_inline_reset_delta_events } true; 5295#L1190-2 [2022-12-13 11:54:23,083 INFO L750 eck$LassoCheckResult]: Loop: 5295#L1190-2 assume !false; 5306#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5307#L756 assume !false; 5530#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 5878#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 5151#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 5432#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 5433#L653 assume !(0 != eval_~tmp~0#1); 5483#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5561#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5562#L781-3 assume 0 == ~M_E~0;~M_E~0 := 1; 5171#L781-5 assume !(0 == ~T1_E~0); 5172#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 5489#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5117#L796-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5118#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 5371#L806-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 5372#L811-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 5563#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 5763#L821-3 assume !(0 == ~E_1~0); 5853#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5705#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 5706#L836-3 assume 0 == ~E_4~0;~E_4~0 := 1; 5269#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 5270#L846-3 assume 0 == ~E_6~0;~E_6~0 := 1; 5587#L851-3 assume 0 == ~E_7~0;~E_7~0 := 1; 5165#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5166#L388-27 assume 1 == ~m_pc~0; 5827#L389-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 5829#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5730#is_master_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 5731#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 5338#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5339#L407-27 assume 1 == ~t1_pc~0; 5713#L408-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 5714#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5632#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5633#L975-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 5607#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5260#L426-27 assume !(1 == ~t2_pc~0); 5261#L426-29 is_transmit2_triggered_~__retres1~2#1 := 0; 5274#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5275#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 5707#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 5824#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5555#L445-27 assume 1 == ~t3_pc~0; 5528#L446-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 5114#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5115#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 5556#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 5643#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5361#L464-27 assume 1 == ~t4_pc~0; 5362#L465-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5113#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5184#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 5486#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 5253#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5254#L483-27 assume 1 == ~t5_pc~0; 5782#L484-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 5167#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5168#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 5795#L1007-27 assume !(0 != activate_threads_~tmp___4~0#1); 5796#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 5864#L502-27 assume 1 == ~t6_pc~0; 5865#L503-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 5582#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5861#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 5736#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 5737#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5056#L521-27 assume !(1 == ~t7_pc~0); 5057#L521-29 is_transmit7_triggered_~__retres1~7#1 := 0; 5398#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5350#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 5110#L1023-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 5111#L1023-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5597#L869-3 assume 1 == ~M_E~0;~M_E~0 := 2; 5733#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5487#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5488#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 5547#L884-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5540#L889-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 5219#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 5220#L899-3 assume !(1 == ~T7_E~0); 5240#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 5241#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5200#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5201#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5235#L924-3 assume 1 == ~E_4~0;~E_4~0 := 2; 5720#L929-3 assume 1 == ~E_5~0;~E_5~0 := 2; 5640#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 5641#L939-3 assume !(1 == ~E_7~0); 5245#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 5246#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 5076#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 5358#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 5359#L1209 assume !(0 == start_simulation_~tmp~3#1); 5577#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 5560#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 5213#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 5105#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 5106#L1164 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5101#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5102#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 5294#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 5295#L1190-2 [2022-12-13 11:54:23,084 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 11:54:23,084 INFO L85 PathProgramCache]: Analyzing trace with hash 1028580607, now seen corresponding path program 1 times [2022-12-13 11:54:23,084 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 11:54:23,084 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1017782953] [2022-12-13 11:54:23,084 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 11:54:23,084 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 11:54:23,094 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 11:54:23,119 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 11:54:23,120 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 11:54:23,120 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1017782953] [2022-12-13 11:54:23,120 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1017782953] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 11:54:23,120 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 11:54:23,120 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 11:54:23,121 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [346409131] [2022-12-13 11:54:23,121 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 11:54:23,121 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 11:54:23,122 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 11:54:23,122 INFO L85 PathProgramCache]: Analyzing trace with hash 134882912, now seen corresponding path program 1 times [2022-12-13 11:54:23,122 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 11:54:23,122 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1364136135] [2022-12-13 11:54:23,122 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 11:54:23,123 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 11:54:23,136 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 11:54:23,170 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 11:54:23,171 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 11:54:23,171 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1364136135] [2022-12-13 11:54:23,171 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1364136135] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 11:54:23,171 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 11:54:23,171 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 11:54:23,172 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [517704686] [2022-12-13 11:54:23,172 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 11:54:23,172 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 11:54:23,172 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 11:54:23,173 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 11:54:23,173 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 11:54:23,173 INFO L87 Difference]: Start difference. First operand 835 states and 1247 transitions. cyclomatic complexity: 413 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 11:54:23,190 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 11:54:23,191 INFO L93 Difference]: Finished difference Result 835 states and 1246 transitions. [2022-12-13 11:54:23,191 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 835 states and 1246 transitions. [2022-12-13 11:54:23,194 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 732 [2022-12-13 11:54:23,197 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 835 states to 835 states and 1246 transitions. [2022-12-13 11:54:23,198 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 835 [2022-12-13 11:54:23,198 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 835 [2022-12-13 11:54:23,198 INFO L73 IsDeterministic]: Start isDeterministic. Operand 835 states and 1246 transitions. [2022-12-13 11:54:23,199 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 11:54:23,199 INFO L218 hiAutomatonCegarLoop]: Abstraction has 835 states and 1246 transitions. [2022-12-13 11:54:23,200 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 835 states and 1246 transitions. [2022-12-13 11:54:23,209 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 835 to 835. [2022-12-13 11:54:23,210 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 835 states, 835 states have (on average 1.4922155688622754) internal successors, (1246), 834 states have internal predecessors, (1246), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 11:54:23,212 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 835 states to 835 states and 1246 transitions. [2022-12-13 11:54:23,212 INFO L240 hiAutomatonCegarLoop]: Abstraction has 835 states and 1246 transitions. [2022-12-13 11:54:23,213 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 11:54:23,213 INFO L428 stractBuchiCegarLoop]: Abstraction has 835 states and 1246 transitions. [2022-12-13 11:54:23,213 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2022-12-13 11:54:23,213 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 835 states and 1246 transitions. [2022-12-13 11:54:23,216 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 732 [2022-12-13 11:54:23,216 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 11:54:23,216 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 11:54:23,217 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 11:54:23,217 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 11:54:23,217 INFO L748 eck$LassoCheckResult]: Stem: 6969#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 6970#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 7514#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 7515#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7554#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 7107#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7108#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 7228#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 7229#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 7012#L568-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 6809#L573-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 6810#L578-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 6977#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 6978#L781 assume !(0 == ~M_E~0); 7448#L781-2 assume !(0 == ~T1_E~0); 7557#L786-1 assume !(0 == ~T2_E~0); 6769#L791-1 assume !(0 == ~T3_E~0); 6770#L796-1 assume !(0 == ~T4_E~0); 7299#L801-1 assume !(0 == ~T5_E~0); 7300#L806-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 7330#L811-1 assume !(0 == ~T7_E~0); 6981#L816-1 assume !(0 == ~E_M~0); 6982#L821-1 assume !(0 == ~E_1~0); 6800#L826-1 assume !(0 == ~E_2~0); 6801#L831-1 assume !(0 == ~E_3~0); 7102#L836-1 assume !(0 == ~E_4~0); 7103#L841-1 assume !(0 == ~E_5~0); 6935#L846-1 assume 0 == ~E_6~0;~E_6~0 := 1; 6936#L851-1 assume !(0 == ~E_7~0); 6959#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6960#L388 assume !(1 == ~m_pc~0); 6953#L388-2 is_master_triggered_~__retres1~0#1 := 0; 6954#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7426#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 6815#L967 assume !(0 != activate_threads_~tmp~1#1); 6816#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6745#L407 assume 1 == ~t1_pc~0; 6746#L408 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 6753#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6754#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 6788#L975 assume !(0 != activate_threads_~tmp___0~0#1); 7512#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7063#L426 assume !(1 == ~t2_pc~0); 7064#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 7529#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7084#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 7085#L983 assume !(0 != activate_threads_~tmp___1~0#1); 7550#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7147#L445 assume 1 == ~t3_pc~0; 7148#L446 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 7454#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6743#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6744#L991 assume !(0 != activate_threads_~tmp___2~0#1); 7389#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7357#L464 assume !(1 == ~t4_pc~0); 6963#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 6835#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6836#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 6847#L999 assume !(0 != activate_threads_~tmp___3~0#1); 7127#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7128#L483 assume 1 == ~t5_pc~0; 7353#L484 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 7494#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7467#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 7468#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 7046#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7047#L502 assume 1 == ~t6_pc~0; 7328#L503 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 6875#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6876#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 7072#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 7265#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 7477#L521 assume !(1 == ~t7_pc~0); 7509#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 6811#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 6812#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 7503#L1023 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 7481#L1023-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7419#L869 assume !(1 == ~M_E~0); 7121#L869-2 assume !(1 == ~T1_E~0); 7122#L874-1 assume !(1 == ~T2_E~0); 7537#L879-1 assume !(1 == ~T3_E~0); 7193#L884-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 6731#L889-1 assume !(1 == ~T5_E~0); 6732#L894-1 assume !(1 == ~T6_E~0); 6991#L899-1 assume !(1 == ~T7_E~0); 7379#L904-1 assume !(1 == ~E_M~0); 7143#L909-1 assume !(1 == ~E_1~0); 7144#L914-1 assume !(1 == ~E_2~0); 7316#L919-1 assume !(1 == ~E_3~0); 7062#L924-1 assume 1 == ~E_4~0;~E_4~0 := 2; 6906#L929-1 assume !(1 == ~E_5~0); 6907#L934-1 assume !(1 == ~E_6~0); 7125#L939-1 assume !(1 == ~E_7~0); 7126#L944-1 assume { :end_inline_reset_delta_events } true; 6972#L1190-2 [2022-12-13 11:54:23,218 INFO L750 eck$LassoCheckResult]: Loop: 6972#L1190-2 assume !false; 6983#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 6984#L756 assume !false; 7207#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 7555#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 6830#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 7110#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 7111#L653 assume !(0 != eval_~tmp~0#1); 7163#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 7238#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 7239#L781-3 assume 0 == ~M_E~0;~M_E~0 := 1; 6848#L781-5 assume !(0 == ~T1_E~0); 6849#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7166#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 6794#L796-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 6795#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 7048#L806-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 7049#L811-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 7240#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 7440#L821-3 assume !(0 == ~E_1~0); 7530#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 7383#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 7384#L836-3 assume 0 == ~E_4~0;~E_4~0 := 1; 6946#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 6947#L846-3 assume 0 == ~E_6~0;~E_6~0 := 1; 7264#L851-3 assume 0 == ~E_7~0;~E_7~0 := 1; 6842#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6843#L388-27 assume 1 == ~m_pc~0; 7504#L389-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 7506#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7407#is_master_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 7408#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 7015#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7016#L407-27 assume !(1 == ~t1_pc~0); 7392#L407-29 is_transmit1_triggered_~__retres1~1#1 := 0; 7391#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7309#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 7310#L975-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 7284#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6937#L426-27 assume !(1 == ~t2_pc~0); 6938#L426-29 is_transmit2_triggered_~__retres1~2#1 := 0; 6951#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6952#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 7382#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 7501#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7232#L445-27 assume 1 == ~t3_pc~0; 7203#L446-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 6791#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6792#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 7233#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 7319#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7038#L464-27 assume !(1 == ~t4_pc~0); 6789#L464-29 is_transmit4_triggered_~__retres1~4#1 := 0; 6790#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6859#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 7161#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 6930#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6931#L483-27 assume 1 == ~t5_pc~0; 7459#L484-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 6844#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6845#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 7472#L1007-27 assume !(0 != activate_threads_~tmp___4~0#1); 7473#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7541#L502-27 assume 1 == ~t6_pc~0; 7542#L503-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 7259#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 7538#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 7413#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 7414#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6733#L521-27 assume !(1 == ~t7_pc~0); 6734#L521-29 is_transmit7_triggered_~__retres1~7#1 := 0; 7075#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 7027#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 6786#L1023-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 6787#L1023-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7274#L869-3 assume 1 == ~M_E~0;~M_E~0 := 2; 7410#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 7164#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7165#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 7224#L884-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 7217#L889-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 6896#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 6897#L899-3 assume !(1 == ~T7_E~0); 6917#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 6918#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 6877#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 6878#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 6912#L924-3 assume 1 == ~E_4~0;~E_4~0 := 2; 7397#L929-3 assume 1 == ~E_5~0;~E_5~0 := 2; 7317#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 7318#L939-3 assume !(1 == ~E_7~0); 6922#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 6923#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 6751#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 7035#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 7036#L1209 assume !(0 == start_simulation_~tmp~3#1); 7254#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 7237#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 6890#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 6782#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 6783#L1164 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 6778#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 6779#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 6971#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 6972#L1190-2 [2022-12-13 11:54:23,218 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 11:54:23,218 INFO L85 PathProgramCache]: Analyzing trace with hash 1614856829, now seen corresponding path program 1 times [2022-12-13 11:54:23,218 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 11:54:23,218 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [385641646] [2022-12-13 11:54:23,218 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 11:54:23,219 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 11:54:23,227 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 11:54:23,247 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 11:54:23,247 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 11:54:23,248 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [385641646] [2022-12-13 11:54:23,248 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [385641646] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 11:54:23,248 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 11:54:23,248 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 11:54:23,248 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1358793032] [2022-12-13 11:54:23,248 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 11:54:23,249 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 11:54:23,249 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 11:54:23,249 INFO L85 PathProgramCache]: Analyzing trace with hash -2094216798, now seen corresponding path program 1 times [2022-12-13 11:54:23,249 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 11:54:23,250 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2097157013] [2022-12-13 11:54:23,250 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 11:54:23,250 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 11:54:23,262 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 11:54:23,287 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 11:54:23,287 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 11:54:23,287 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2097157013] [2022-12-13 11:54:23,288 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2097157013] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 11:54:23,288 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 11:54:23,288 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 11:54:23,288 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1240665000] [2022-12-13 11:54:23,288 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 11:54:23,288 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 11:54:23,289 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 11:54:23,289 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 11:54:23,289 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 11:54:23,289 INFO L87 Difference]: Start difference. First operand 835 states and 1246 transitions. cyclomatic complexity: 412 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 11:54:23,305 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 11:54:23,306 INFO L93 Difference]: Finished difference Result 835 states and 1245 transitions. [2022-12-13 11:54:23,306 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 835 states and 1245 transitions. [2022-12-13 11:54:23,309 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 732 [2022-12-13 11:54:23,311 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 835 states to 835 states and 1245 transitions. [2022-12-13 11:54:23,311 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 835 [2022-12-13 11:54:23,311 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 835 [2022-12-13 11:54:23,312 INFO L73 IsDeterministic]: Start isDeterministic. Operand 835 states and 1245 transitions. [2022-12-13 11:54:23,312 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 11:54:23,312 INFO L218 hiAutomatonCegarLoop]: Abstraction has 835 states and 1245 transitions. [2022-12-13 11:54:23,313 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 835 states and 1245 transitions. [2022-12-13 11:54:23,319 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 835 to 835. [2022-12-13 11:54:23,320 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 835 states, 835 states have (on average 1.4910179640718564) internal successors, (1245), 834 states have internal predecessors, (1245), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 11:54:23,321 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 835 states to 835 states and 1245 transitions. [2022-12-13 11:54:23,321 INFO L240 hiAutomatonCegarLoop]: Abstraction has 835 states and 1245 transitions. [2022-12-13 11:54:23,322 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 11:54:23,322 INFO L428 stractBuchiCegarLoop]: Abstraction has 835 states and 1245 transitions. [2022-12-13 11:54:23,322 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2022-12-13 11:54:23,322 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 835 states and 1245 transitions. [2022-12-13 11:54:23,324 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 732 [2022-12-13 11:54:23,325 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 11:54:23,325 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 11:54:23,325 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 11:54:23,325 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 11:54:23,326 INFO L748 eck$LassoCheckResult]: Stem: 8646#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 8647#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 9191#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 9192#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 9231#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 8784#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 8785#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 8905#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 8906#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 8689#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 8486#L573-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 8487#L578-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 8654#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8655#L781 assume !(0 == ~M_E~0); 9125#L781-2 assume !(0 == ~T1_E~0); 9234#L786-1 assume !(0 == ~T2_E~0); 8446#L791-1 assume !(0 == ~T3_E~0); 8447#L796-1 assume !(0 == ~T4_E~0); 8976#L801-1 assume !(0 == ~T5_E~0); 8977#L806-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 9007#L811-1 assume !(0 == ~T7_E~0); 8658#L816-1 assume !(0 == ~E_M~0); 8659#L821-1 assume !(0 == ~E_1~0); 8477#L826-1 assume !(0 == ~E_2~0); 8478#L831-1 assume !(0 == ~E_3~0); 8779#L836-1 assume !(0 == ~E_4~0); 8780#L841-1 assume !(0 == ~E_5~0); 8612#L846-1 assume 0 == ~E_6~0;~E_6~0 := 1; 8613#L851-1 assume !(0 == ~E_7~0); 8636#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8637#L388 assume !(1 == ~m_pc~0); 8630#L388-2 is_master_triggered_~__retres1~0#1 := 0; 8631#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9103#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 8492#L967 assume !(0 != activate_threads_~tmp~1#1); 8493#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8422#L407 assume 1 == ~t1_pc~0; 8423#L408 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 8430#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8431#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 8465#L975 assume !(0 != activate_threads_~tmp___0~0#1); 9189#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8740#L426 assume !(1 == ~t2_pc~0); 8741#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 9206#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8761#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 8762#L983 assume !(0 != activate_threads_~tmp___1~0#1); 9227#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8824#L445 assume 1 == ~t3_pc~0; 8825#L446 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 9131#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8420#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 8421#L991 assume !(0 != activate_threads_~tmp___2~0#1); 9066#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9034#L464 assume !(1 == ~t4_pc~0); 8640#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 8512#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8513#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 8524#L999 assume !(0 != activate_threads_~tmp___3~0#1); 8804#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8805#L483 assume 1 == ~t5_pc~0; 9030#L484 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 9171#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9144#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 9145#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 8723#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8724#L502 assume 1 == ~t6_pc~0; 9005#L503 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 8552#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8553#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8747#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 8942#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9154#L521 assume !(1 == ~t7_pc~0); 9186#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 8488#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8489#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 9180#L1023 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 9158#L1023-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9094#L869 assume !(1 == ~M_E~0); 8798#L869-2 assume !(1 == ~T1_E~0); 8799#L874-1 assume !(1 == ~T2_E~0); 9214#L879-1 assume !(1 == ~T3_E~0); 8870#L884-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8408#L889-1 assume !(1 == ~T5_E~0); 8409#L894-1 assume !(1 == ~T6_E~0); 8665#L899-1 assume !(1 == ~T7_E~0); 9056#L904-1 assume !(1 == ~E_M~0); 8820#L909-1 assume !(1 == ~E_1~0); 8821#L914-1 assume !(1 == ~E_2~0); 8992#L919-1 assume !(1 == ~E_3~0); 8739#L924-1 assume 1 == ~E_4~0;~E_4~0 := 2; 8583#L929-1 assume !(1 == ~E_5~0); 8584#L934-1 assume !(1 == ~E_6~0); 8800#L939-1 assume !(1 == ~E_7~0); 8801#L944-1 assume { :end_inline_reset_delta_events } true; 8649#L1190-2 [2022-12-13 11:54:23,326 INFO L750 eck$LassoCheckResult]: Loop: 8649#L1190-2 assume !false; 8660#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 8661#L756 assume !false; 8884#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 9232#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 8507#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 8786#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 8787#L653 assume !(0 != eval_~tmp~0#1); 8837#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 8915#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 8916#L781-3 assume 0 == ~M_E~0;~M_E~0 := 1; 8525#L781-5 assume !(0 == ~T1_E~0); 8526#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 8843#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 8471#L796-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 8472#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 8725#L806-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 8726#L811-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 8917#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 9117#L821-3 assume !(0 == ~E_1~0); 9207#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 9059#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 9060#L836-3 assume 0 == ~E_4~0;~E_4~0 := 1; 8623#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 8624#L846-3 assume 0 == ~E_6~0;~E_6~0 := 1; 8941#L851-3 assume 0 == ~E_7~0;~E_7~0 := 1; 8519#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8520#L388-27 assume 1 == ~m_pc~0; 9181#L389-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 9183#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9084#is_master_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 9085#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 8692#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8693#L407-27 assume 1 == ~t1_pc~0; 9067#L408-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 9068#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8986#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 8987#L975-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 8961#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8614#L426-27 assume !(1 == ~t2_pc~0); 8615#L426-29 is_transmit2_triggered_~__retres1~2#1 := 0; 8628#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8629#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 9061#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 9178#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8909#L445-27 assume 1 == ~t3_pc~0; 8882#L446-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 8468#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8469#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 8910#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 8997#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8715#L464-27 assume !(1 == ~t4_pc~0); 8466#L464-29 is_transmit4_triggered_~__retres1~4#1 := 0; 8467#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8538#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 8840#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 8609#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8610#L483-27 assume 1 == ~t5_pc~0; 9136#L484-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 8521#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8522#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 9149#L1007-27 assume !(0 != activate_threads_~tmp___4~0#1); 9150#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 9218#L502-27 assume 1 == ~t6_pc~0; 9219#L503-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 8936#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 9215#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 9090#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 9091#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8410#L521-27 assume !(1 == ~t7_pc~0); 8411#L521-29 is_transmit7_triggered_~__retres1~7#1 := 0; 8752#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8704#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 8463#L1023-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 8464#L1023-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8949#L869-3 assume 1 == ~M_E~0;~M_E~0 := 2; 9087#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 8841#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 8842#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 8901#L884-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8894#L889-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 8573#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 8574#L899-3 assume !(1 == ~T7_E~0); 8594#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 8595#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 8554#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 8555#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 8589#L924-3 assume 1 == ~E_4~0;~E_4~0 := 2; 9074#L929-3 assume 1 == ~E_5~0;~E_5~0 := 2; 8994#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 8995#L939-3 assume !(1 == ~E_7~0); 8599#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 8600#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 8428#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 8712#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 8713#L1209 assume !(0 == start_simulation_~tmp~3#1); 8931#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 8914#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 8567#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 8459#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 8460#L1164 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 8455#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 8456#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 8648#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 8649#L1190-2 [2022-12-13 11:54:23,326 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 11:54:23,326 INFO L85 PathProgramCache]: Analyzing trace with hash -721535681, now seen corresponding path program 1 times [2022-12-13 11:54:23,326 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 11:54:23,326 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1591350911] [2022-12-13 11:54:23,327 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 11:54:23,327 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 11:54:23,333 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 11:54:23,351 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 11:54:23,351 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 11:54:23,351 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1591350911] [2022-12-13 11:54:23,351 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1591350911] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 11:54:23,351 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 11:54:23,352 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 11:54:23,352 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1987328438] [2022-12-13 11:54:23,352 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 11:54:23,352 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 11:54:23,353 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 11:54:23,353 INFO L85 PathProgramCache]: Analyzing trace with hash -138895583, now seen corresponding path program 1 times [2022-12-13 11:54:23,353 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 11:54:23,353 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [391270418] [2022-12-13 11:54:23,353 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 11:54:23,353 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 11:54:23,363 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 11:54:23,387 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 11:54:23,387 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 11:54:23,387 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [391270418] [2022-12-13 11:54:23,387 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [391270418] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 11:54:23,387 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 11:54:23,388 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 11:54:23,388 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1734592827] [2022-12-13 11:54:23,388 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 11:54:23,388 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 11:54:23,388 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 11:54:23,389 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 11:54:23,389 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 11:54:23,389 INFO L87 Difference]: Start difference. First operand 835 states and 1245 transitions. cyclomatic complexity: 411 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 11:54:23,405 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 11:54:23,405 INFO L93 Difference]: Finished difference Result 835 states and 1244 transitions. [2022-12-13 11:54:23,405 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 835 states and 1244 transitions. [2022-12-13 11:54:23,408 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 732 [2022-12-13 11:54:23,410 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 835 states to 835 states and 1244 transitions. [2022-12-13 11:54:23,410 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 835 [2022-12-13 11:54:23,411 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 835 [2022-12-13 11:54:23,411 INFO L73 IsDeterministic]: Start isDeterministic. Operand 835 states and 1244 transitions. [2022-12-13 11:54:23,411 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 11:54:23,412 INFO L218 hiAutomatonCegarLoop]: Abstraction has 835 states and 1244 transitions. [2022-12-13 11:54:23,412 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 835 states and 1244 transitions. [2022-12-13 11:54:23,418 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 835 to 835. [2022-12-13 11:54:23,420 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 835 states, 835 states have (on average 1.4898203592814372) internal successors, (1244), 834 states have internal predecessors, (1244), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 11:54:23,421 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 835 states to 835 states and 1244 transitions. [2022-12-13 11:54:23,421 INFO L240 hiAutomatonCegarLoop]: Abstraction has 835 states and 1244 transitions. [2022-12-13 11:54:23,422 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 11:54:23,422 INFO L428 stractBuchiCegarLoop]: Abstraction has 835 states and 1244 transitions. [2022-12-13 11:54:23,422 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2022-12-13 11:54:23,422 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 835 states and 1244 transitions. [2022-12-13 11:54:23,425 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 732 [2022-12-13 11:54:23,425 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 11:54:23,425 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 11:54:23,426 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 11:54:23,426 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 11:54:23,426 INFO L748 eck$LassoCheckResult]: Stem: 10323#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 10324#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 10868#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 10869#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 10908#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 10461#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 10462#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 10582#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 10583#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 10366#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 10163#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 10164#L578-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 10328#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 10329#L781 assume !(0 == ~M_E~0); 10802#L781-2 assume !(0 == ~T1_E~0); 10911#L786-1 assume !(0 == ~T2_E~0); 10123#L791-1 assume !(0 == ~T3_E~0); 10124#L796-1 assume !(0 == ~T4_E~0); 10653#L801-1 assume !(0 == ~T5_E~0); 10654#L806-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 10684#L811-1 assume !(0 == ~T7_E~0); 10335#L816-1 assume !(0 == ~E_M~0); 10336#L821-1 assume !(0 == ~E_1~0); 10154#L826-1 assume !(0 == ~E_2~0); 10155#L831-1 assume !(0 == ~E_3~0); 10456#L836-1 assume !(0 == ~E_4~0); 10457#L841-1 assume !(0 == ~E_5~0); 10289#L846-1 assume 0 == ~E_6~0;~E_6~0 := 1; 10290#L851-1 assume !(0 == ~E_7~0); 10313#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10314#L388 assume !(1 == ~m_pc~0); 10307#L388-2 is_master_triggered_~__retres1~0#1 := 0; 10308#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10780#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 10169#L967 assume !(0 != activate_threads_~tmp~1#1); 10170#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10099#L407 assume 1 == ~t1_pc~0; 10100#L408 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 10104#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10105#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 10140#L975 assume !(0 != activate_threads_~tmp___0~0#1); 10866#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10417#L426 assume !(1 == ~t2_pc~0); 10418#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 10883#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10438#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 10439#L983 assume !(0 != activate_threads_~tmp___1~0#1); 10904#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10501#L445 assume 1 == ~t3_pc~0; 10502#L446 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 10808#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10097#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 10098#L991 assume !(0 != activate_threads_~tmp___2~0#1); 10743#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10711#L464 assume !(1 == ~t4_pc~0); 10317#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 10189#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10190#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 10201#L999 assume !(0 != activate_threads_~tmp___3~0#1); 10481#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10482#L483 assume 1 == ~t5_pc~0; 10707#L484 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 10848#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10821#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 10822#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 10400#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 10401#L502 assume 1 == ~t6_pc~0; 10681#L503 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 10229#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 10230#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 10424#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 10619#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 10831#L521 assume !(1 == ~t7_pc~0); 10863#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 10165#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 10166#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 10857#L1023 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 10835#L1023-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10771#L869 assume !(1 == ~M_E~0); 10475#L869-2 assume !(1 == ~T1_E~0); 10476#L874-1 assume !(1 == ~T2_E~0); 10891#L879-1 assume !(1 == ~T3_E~0); 10547#L884-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 10085#L889-1 assume !(1 == ~T5_E~0); 10086#L894-1 assume !(1 == ~T6_E~0); 10342#L899-1 assume !(1 == ~T7_E~0); 10732#L904-1 assume !(1 == ~E_M~0); 10497#L909-1 assume !(1 == ~E_1~0); 10498#L914-1 assume !(1 == ~E_2~0); 10669#L919-1 assume !(1 == ~E_3~0); 10416#L924-1 assume 1 == ~E_4~0;~E_4~0 := 2; 10260#L929-1 assume !(1 == ~E_5~0); 10261#L934-1 assume !(1 == ~E_6~0); 10477#L939-1 assume !(1 == ~E_7~0); 10478#L944-1 assume { :end_inline_reset_delta_events } true; 10326#L1190-2 [2022-12-13 11:54:23,426 INFO L750 eck$LassoCheckResult]: Loop: 10326#L1190-2 assume !false; 10337#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 10338#L756 assume !false; 10561#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 10909#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 10182#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 10463#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 10464#L653 assume !(0 != eval_~tmp~0#1); 10514#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 10592#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 10593#L781-3 assume 0 == ~M_E~0;~M_E~0 := 1; 10202#L781-5 assume !(0 == ~T1_E~0); 10203#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 10520#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 10148#L796-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 10149#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 10402#L806-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 10403#L811-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 10594#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 10794#L821-3 assume !(0 == ~E_1~0); 10884#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 10736#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 10737#L836-3 assume 0 == ~E_4~0;~E_4~0 := 1; 10300#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 10301#L846-3 assume 0 == ~E_6~0;~E_6~0 := 1; 10618#L851-3 assume 0 == ~E_7~0;~E_7~0 := 1; 10196#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10197#L388-27 assume 1 == ~m_pc~0; 10858#L389-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 10860#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10761#is_master_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 10762#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 10369#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10370#L407-27 assume 1 == ~t1_pc~0; 10744#L408-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 10745#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10663#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 10664#L975-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 10638#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10291#L426-27 assume !(1 == ~t2_pc~0); 10292#L426-29 is_transmit2_triggered_~__retres1~2#1 := 0; 10305#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10306#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 10738#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 10855#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10586#L445-27 assume !(1 == ~t3_pc~0); 10560#L445-29 is_transmit3_triggered_~__retres1~3#1 := 0; 10145#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10146#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 10587#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 10674#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10392#L464-27 assume 1 == ~t4_pc~0; 10393#L465-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 10144#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10215#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 10517#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 10284#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10285#L483-27 assume 1 == ~t5_pc~0; 10813#L484-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 10198#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10199#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 10826#L1007-27 assume !(0 != activate_threads_~tmp___4~0#1); 10827#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 10895#L502-27 assume 1 == ~t6_pc~0; 10896#L503-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 10613#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 10892#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 10767#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 10768#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 10087#L521-27 assume !(1 == ~t7_pc~0); 10088#L521-29 is_transmit7_triggered_~__retres1~7#1 := 0; 10429#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 10381#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 10141#L1023-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 10142#L1023-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10628#L869-3 assume 1 == ~M_E~0;~M_E~0 := 2; 10764#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 10518#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 10519#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 10578#L884-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 10571#L889-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 10250#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 10251#L899-3 assume !(1 == ~T7_E~0); 10271#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 10272#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 10231#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 10232#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 10266#L924-3 assume 1 == ~E_4~0;~E_4~0 := 2; 10751#L929-3 assume 1 == ~E_5~0;~E_5~0 := 2; 10671#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 10672#L939-3 assume !(1 == ~E_7~0); 10276#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 10277#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 10107#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 10389#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 10390#L1209 assume !(0 == start_simulation_~tmp~3#1); 10608#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 10591#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 10244#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 10136#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 10137#L1164 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 10132#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 10133#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 10325#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 10326#L1190-2 [2022-12-13 11:54:23,426 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 11:54:23,426 INFO L85 PathProgramCache]: Analyzing trace with hash 1696948797, now seen corresponding path program 1 times [2022-12-13 11:54:23,427 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 11:54:23,427 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [206077689] [2022-12-13 11:54:23,427 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 11:54:23,427 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 11:54:23,443 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 11:54:23,460 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 11:54:23,460 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 11:54:23,460 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [206077689] [2022-12-13 11:54:23,460 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [206077689] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 11:54:23,460 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 11:54:23,461 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 11:54:23,461 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2125562284] [2022-12-13 11:54:23,461 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 11:54:23,461 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 11:54:23,461 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 11:54:23,462 INFO L85 PathProgramCache]: Analyzing trace with hash -896447903, now seen corresponding path program 1 times [2022-12-13 11:54:23,462 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 11:54:23,462 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1550457690] [2022-12-13 11:54:23,462 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 11:54:23,462 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 11:54:23,471 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 11:54:23,493 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 11:54:23,493 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 11:54:23,493 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1550457690] [2022-12-13 11:54:23,493 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1550457690] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 11:54:23,493 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 11:54:23,493 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 11:54:23,493 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1645470217] [2022-12-13 11:54:23,494 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 11:54:23,494 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 11:54:23,494 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 11:54:23,494 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 11:54:23,495 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 11:54:23,495 INFO L87 Difference]: Start difference. First operand 835 states and 1244 transitions. cyclomatic complexity: 410 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 11:54:23,508 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 11:54:23,508 INFO L93 Difference]: Finished difference Result 835 states and 1243 transitions. [2022-12-13 11:54:23,508 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 835 states and 1243 transitions. [2022-12-13 11:54:23,512 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 732 [2022-12-13 11:54:23,514 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 835 states to 835 states and 1243 transitions. [2022-12-13 11:54:23,514 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 835 [2022-12-13 11:54:23,515 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 835 [2022-12-13 11:54:23,515 INFO L73 IsDeterministic]: Start isDeterministic. Operand 835 states and 1243 transitions. [2022-12-13 11:54:23,515 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 11:54:23,516 INFO L218 hiAutomatonCegarLoop]: Abstraction has 835 states and 1243 transitions. [2022-12-13 11:54:23,516 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 835 states and 1243 transitions. [2022-12-13 11:54:23,523 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 835 to 835. [2022-12-13 11:54:23,524 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 835 states, 835 states have (on average 1.488622754491018) internal successors, (1243), 834 states have internal predecessors, (1243), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 11:54:23,525 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 835 states to 835 states and 1243 transitions. [2022-12-13 11:54:23,525 INFO L240 hiAutomatonCegarLoop]: Abstraction has 835 states and 1243 transitions. [2022-12-13 11:54:23,526 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 11:54:23,526 INFO L428 stractBuchiCegarLoop]: Abstraction has 835 states and 1243 transitions. [2022-12-13 11:54:23,526 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2022-12-13 11:54:23,526 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 835 states and 1243 transitions. [2022-12-13 11:54:23,529 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 732 [2022-12-13 11:54:23,529 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 11:54:23,529 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 11:54:23,530 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 11:54:23,530 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 11:54:23,530 INFO L748 eck$LassoCheckResult]: Stem: 12000#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 12001#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 12545#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 12546#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 12585#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 12138#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 12139#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 12259#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 12260#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 12043#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 11840#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 11841#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 12005#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 12006#L781 assume !(0 == ~M_E~0); 12479#L781-2 assume !(0 == ~T1_E~0); 12588#L786-1 assume !(0 == ~T2_E~0); 11800#L791-1 assume !(0 == ~T3_E~0); 11801#L796-1 assume !(0 == ~T4_E~0); 12330#L801-1 assume !(0 == ~T5_E~0); 12331#L806-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 12361#L811-1 assume !(0 == ~T7_E~0); 12012#L816-1 assume !(0 == ~E_M~0); 12013#L821-1 assume !(0 == ~E_1~0); 11831#L826-1 assume !(0 == ~E_2~0); 11832#L831-1 assume !(0 == ~E_3~0); 12133#L836-1 assume !(0 == ~E_4~0); 12134#L841-1 assume !(0 == ~E_5~0); 11966#L846-1 assume 0 == ~E_6~0;~E_6~0 := 1; 11967#L851-1 assume !(0 == ~E_7~0); 11990#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11991#L388 assume !(1 == ~m_pc~0); 11984#L388-2 is_master_triggered_~__retres1~0#1 := 0; 11985#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12457#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 11846#L967 assume !(0 != activate_threads_~tmp~1#1); 11847#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11776#L407 assume 1 == ~t1_pc~0; 11777#L408 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 11781#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11782#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 11817#L975 assume !(0 != activate_threads_~tmp___0~0#1); 12543#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12094#L426 assume !(1 == ~t2_pc~0); 12095#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 12560#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12115#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 12116#L983 assume !(0 != activate_threads_~tmp___1~0#1); 12581#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12178#L445 assume 1 == ~t3_pc~0; 12179#L446 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 12485#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11774#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 11775#L991 assume !(0 != activate_threads_~tmp___2~0#1); 12420#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12388#L464 assume !(1 == ~t4_pc~0); 11994#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 11866#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 11867#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 11878#L999 assume !(0 != activate_threads_~tmp___3~0#1); 12158#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 12159#L483 assume 1 == ~t5_pc~0; 12384#L484 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 12525#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12498#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 12499#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 12077#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 12078#L502 assume 1 == ~t6_pc~0; 12358#L503 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 11906#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11907#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 12101#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 12296#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12508#L521 assume !(1 == ~t7_pc~0); 12540#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 11842#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 11843#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 12534#L1023 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 12512#L1023-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12448#L869 assume !(1 == ~M_E~0); 12152#L869-2 assume !(1 == ~T1_E~0); 12153#L874-1 assume !(1 == ~T2_E~0); 12568#L879-1 assume !(1 == ~T3_E~0); 12224#L884-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 11762#L889-1 assume !(1 == ~T5_E~0); 11763#L894-1 assume !(1 == ~T6_E~0); 12019#L899-1 assume !(1 == ~T7_E~0); 12409#L904-1 assume !(1 == ~E_M~0); 12174#L909-1 assume !(1 == ~E_1~0); 12175#L914-1 assume !(1 == ~E_2~0); 12346#L919-1 assume !(1 == ~E_3~0); 12093#L924-1 assume 1 == ~E_4~0;~E_4~0 := 2; 11937#L929-1 assume !(1 == ~E_5~0); 11938#L934-1 assume !(1 == ~E_6~0); 12154#L939-1 assume !(1 == ~E_7~0); 12155#L944-1 assume { :end_inline_reset_delta_events } true; 12003#L1190-2 [2022-12-13 11:54:23,530 INFO L750 eck$LassoCheckResult]: Loop: 12003#L1190-2 assume !false; 12014#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 12015#L756 assume !false; 12238#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 12586#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 11859#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 12140#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 12141#L653 assume !(0 != eval_~tmp~0#1); 12191#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 12269#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 12270#L781-3 assume 0 == ~M_E~0;~M_E~0 := 1; 11879#L781-5 assume !(0 == ~T1_E~0); 11880#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 12197#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 11825#L796-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 11826#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 12079#L806-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 12080#L811-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 12271#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 12471#L821-3 assume !(0 == ~E_1~0); 12561#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 12413#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 12414#L836-3 assume 0 == ~E_4~0;~E_4~0 := 1; 11977#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 11978#L846-3 assume 0 == ~E_6~0;~E_6~0 := 1; 12295#L851-3 assume 0 == ~E_7~0;~E_7~0 := 1; 11873#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11874#L388-27 assume 1 == ~m_pc~0; 12535#L389-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 12537#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12438#is_master_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 12439#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 12046#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12047#L407-27 assume 1 == ~t1_pc~0; 12421#L408-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 12422#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12340#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 12341#L975-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 12315#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11968#L426-27 assume !(1 == ~t2_pc~0); 11969#L426-29 is_transmit2_triggered_~__retres1~2#1 := 0; 11982#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11983#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 12415#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 12532#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12263#L445-27 assume 1 == ~t3_pc~0; 12236#L446-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 11822#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11823#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 12264#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 12351#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12069#L464-27 assume 1 == ~t4_pc~0; 12070#L465-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 11821#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 11892#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 12194#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 11961#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 11962#L483-27 assume 1 == ~t5_pc~0; 12490#L484-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 11875#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 11876#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 12503#L1007-27 assume !(0 != activate_threads_~tmp___4~0#1); 12504#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 12572#L502-27 assume !(1 == ~t6_pc~0); 12289#L502-29 is_transmit6_triggered_~__retres1~6#1 := 0; 12290#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12569#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 12444#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 12445#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 11764#L521-27 assume !(1 == ~t7_pc~0); 11765#L521-29 is_transmit7_triggered_~__retres1~7#1 := 0; 12106#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 12058#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 11818#L1023-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 11819#L1023-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12305#L869-3 assume 1 == ~M_E~0;~M_E~0 := 2; 12441#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 12195#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 12196#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 12255#L884-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 12248#L889-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 11927#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 11928#L899-3 assume !(1 == ~T7_E~0); 11948#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 11949#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 11908#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 11909#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 11943#L924-3 assume 1 == ~E_4~0;~E_4~0 := 2; 12428#L929-3 assume 1 == ~E_5~0;~E_5~0 := 2; 12348#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 12349#L939-3 assume !(1 == ~E_7~0); 11953#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 11954#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 11784#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 12066#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 12067#L1209 assume !(0 == start_simulation_~tmp~3#1); 12285#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 12268#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 11921#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 11813#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 11814#L1164 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 11809#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 11810#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 12002#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 12003#L1190-2 [2022-12-13 11:54:23,530 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 11:54:23,530 INFO L85 PathProgramCache]: Analyzing trace with hash -718887553, now seen corresponding path program 1 times [2022-12-13 11:54:23,531 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 11:54:23,531 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1421196078] [2022-12-13 11:54:23,531 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 11:54:23,531 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 11:54:23,539 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 11:54:23,582 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 11:54:23,582 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 11:54:23,582 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1421196078] [2022-12-13 11:54:23,582 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1421196078] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 11:54:23,582 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 11:54:23,582 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 11:54:23,583 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1021539251] [2022-12-13 11:54:23,583 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 11:54:23,583 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 11:54:23,583 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 11:54:23,584 INFO L85 PathProgramCache]: Analyzing trace with hash -350291807, now seen corresponding path program 3 times [2022-12-13 11:54:23,584 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 11:54:23,584 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1241267979] [2022-12-13 11:54:23,584 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 11:54:23,584 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 11:54:23,596 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 11:54:23,629 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 11:54:23,629 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 11:54:23,629 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1241267979] [2022-12-13 11:54:23,629 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1241267979] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 11:54:23,630 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 11:54:23,630 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 11:54:23,630 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1873184867] [2022-12-13 11:54:23,630 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 11:54:23,630 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 11:54:23,630 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 11:54:23,631 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 11:54:23,631 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 11:54:23,631 INFO L87 Difference]: Start difference. First operand 835 states and 1243 transitions. cyclomatic complexity: 409 Second operand has 4 states, 4 states have (on average 23.75) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 11:54:23,721 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 11:54:23,721 INFO L93 Difference]: Finished difference Result 1509 states and 2238 transitions. [2022-12-13 11:54:23,721 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1509 states and 2238 transitions. [2022-12-13 11:54:23,727 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1390 [2022-12-13 11:54:23,731 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1509 states to 1509 states and 2238 transitions. [2022-12-13 11:54:23,731 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1509 [2022-12-13 11:54:23,732 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1509 [2022-12-13 11:54:23,732 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1509 states and 2238 transitions. [2022-12-13 11:54:23,734 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 11:54:23,734 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1509 states and 2238 transitions. [2022-12-13 11:54:23,735 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1509 states and 2238 transitions. [2022-12-13 11:54:23,751 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1509 to 1509. [2022-12-13 11:54:23,753 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1509 states, 1509 states have (on average 1.4831013916500995) internal successors, (2238), 1508 states have internal predecessors, (2238), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 11:54:23,756 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1509 states to 1509 states and 2238 transitions. [2022-12-13 11:54:23,756 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1509 states and 2238 transitions. [2022-12-13 11:54:23,757 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 11:54:23,757 INFO L428 stractBuchiCegarLoop]: Abstraction has 1509 states and 2238 transitions. [2022-12-13 11:54:23,757 INFO L335 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2022-12-13 11:54:23,757 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1509 states and 2238 transitions. [2022-12-13 11:54:23,761 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1390 [2022-12-13 11:54:23,762 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 11:54:23,762 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 11:54:23,763 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 11:54:23,763 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 11:54:23,763 INFO L748 eck$LassoCheckResult]: Stem: 14354#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 14355#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 14923#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 14924#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 14968#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 14493#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 14494#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 14617#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 14618#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 14398#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 14194#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 14195#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 14359#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 14360#L781 assume !(0 == ~M_E~0); 14855#L781-2 assume !(0 == ~T1_E~0); 14973#L786-1 assume !(0 == ~T2_E~0); 14154#L791-1 assume !(0 == ~T3_E~0); 14155#L796-1 assume !(0 == ~T4_E~0); 14692#L801-1 assume !(0 == ~T5_E~0); 14693#L806-1 assume !(0 == ~T6_E~0); 14724#L811-1 assume !(0 == ~T7_E~0); 14366#L816-1 assume !(0 == ~E_M~0); 14367#L821-1 assume !(0 == ~E_1~0); 14185#L826-1 assume !(0 == ~E_2~0); 14186#L831-1 assume !(0 == ~E_3~0); 14488#L836-1 assume !(0 == ~E_4~0); 14489#L841-1 assume !(0 == ~E_5~0); 14320#L846-1 assume 0 == ~E_6~0;~E_6~0 := 1; 14321#L851-1 assume !(0 == ~E_7~0); 14344#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 14345#L388 assume !(1 == ~m_pc~0); 14338#L388-2 is_master_triggered_~__retres1~0#1 := 0; 14339#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 14831#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 14200#L967 assume !(0 != activate_threads_~tmp~1#1); 14201#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14130#L407 assume 1 == ~t1_pc~0; 14131#L408 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 14135#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14136#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 14171#L975 assume !(0 != activate_threads_~tmp___0~0#1); 14921#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14449#L426 assume !(1 == ~t2_pc~0); 14450#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 14942#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14470#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 14471#L983 assume !(0 != activate_threads_~tmp___1~0#1); 14964#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14535#L445 assume 1 == ~t3_pc~0; 14536#L446 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 14861#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14128#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 14129#L991 assume !(0 != activate_threads_~tmp___2~0#1); 14792#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 14757#L464 assume !(1 == ~t4_pc~0); 14348#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 14220#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 14221#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 14232#L999 assume !(0 != activate_threads_~tmp___3~0#1); 14513#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14514#L483 assume 1 == ~t5_pc~0; 14752#L484 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 14903#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 14874#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 14875#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 14432#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14433#L502 assume 1 == ~t6_pc~0; 14721#L503 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 14260#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 14261#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 14456#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 14657#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 14885#L521 assume !(1 == ~t7_pc~0); 14918#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 14196#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 14197#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 14912#L1023 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 14889#L1023-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14821#L869 assume 1 == ~M_E~0;~M_E~0 := 2; 14507#L869-2 assume !(1 == ~T1_E~0); 14508#L874-1 assume !(1 == ~T2_E~0); 14950#L879-1 assume !(1 == ~T3_E~0); 14582#L884-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 14116#L889-1 assume !(1 == ~T5_E~0); 14117#L894-1 assume !(1 == ~T6_E~0); 14373#L899-1 assume !(1 == ~T7_E~0); 14781#L904-1 assume !(1 == ~E_M~0); 14530#L909-1 assume !(1 == ~E_1~0); 14531#L914-1 assume !(1 == ~E_2~0); 14708#L919-1 assume !(1 == ~E_3~0); 14448#L924-1 assume 1 == ~E_4~0;~E_4~0 := 2; 14291#L929-1 assume !(1 == ~E_5~0); 14292#L934-1 assume !(1 == ~E_6~0); 14509#L939-1 assume !(1 == ~E_7~0); 14510#L944-1 assume { :end_inline_reset_delta_events } true; 14357#L1190-2 [2022-12-13 11:54:23,763 INFO L750 eck$LassoCheckResult]: Loop: 14357#L1190-2 assume !false; 14985#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 14984#L756 assume !false; 14983#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 14982#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 14747#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 14748#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 14547#L653 assume !(0 != eval_~tmp~0#1); 14549#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 14628#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 14629#L781-3 assume 0 == ~M_E~0;~M_E~0 := 1; 14233#L781-5 assume !(0 == ~T1_E~0); 14234#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 14555#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 14179#L796-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 14180#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 14434#L806-3 assume !(0 == ~T6_E~0); 14435#L811-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 14630#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 14847#L821-3 assume !(0 == ~E_1~0); 14943#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 14785#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 14786#L836-3 assume 0 == ~E_4~0;~E_4~0 := 1; 14331#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 14332#L846-3 assume 0 == ~E_6~0;~E_6~0 := 1; 14656#L851-3 assume 0 == ~E_7~0;~E_7~0 := 1; 14227#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 14228#L388-27 assume 1 == ~m_pc~0; 14913#L389-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 14915#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 14811#is_master_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 14812#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 14401#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14402#L407-27 assume 1 == ~t1_pc~0; 14793#L408-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 14794#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14702#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 14703#L975-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 14676#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14322#L426-27 assume !(1 == ~t2_pc~0); 14323#L426-29 is_transmit2_triggered_~__retres1~2#1 := 0; 14336#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14337#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 14787#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 14910#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14622#L445-27 assume 1 == ~t3_pc~0; 14594#L446-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 14176#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14177#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 14623#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 14714#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 14424#L464-27 assume 1 == ~t4_pc~0; 14425#L465-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 14175#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 14246#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 14552#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 14315#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14316#L483-27 assume 1 == ~t5_pc~0; 14866#L484-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 14229#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 14230#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 14879#L1007-27 assume !(0 != activate_threads_~tmp___4~0#1); 14880#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14955#L502-27 assume !(1 == ~t6_pc~0); 14650#L502-29 is_transmit6_triggered_~__retres1~6#1 := 0; 14651#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 14951#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 14817#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 14818#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 14118#L521-27 assume !(1 == ~t7_pc~0); 14119#L521-29 is_transmit7_triggered_~__retres1~7#1 := 0; 14461#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 14413#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 14172#L1023-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 14173#L1023-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14666#L869-3 assume 1 == ~M_E~0;~M_E~0 := 2; 14814#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 14553#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 14554#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 14613#L884-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 14606#L889-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 14281#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 14282#L899-3 assume !(1 == ~T7_E~0); 14302#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 14303#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 14262#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 14263#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 14297#L924-3 assume 1 == ~E_4~0;~E_4~0 := 2; 14801#L929-3 assume 1 == ~E_5~0;~E_5~0 := 2; 14711#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 14712#L939-3 assume !(1 == ~E_7~0); 14307#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 14308#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 14138#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 14421#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 14422#L1209 assume !(0 == start_simulation_~tmp~3#1); 14644#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 14627#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 14275#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 14167#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 14168#L1164 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 14163#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 14164#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 14356#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 14357#L1190-2 [2022-12-13 11:54:23,763 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 11:54:23,764 INFO L85 PathProgramCache]: Analyzing trace with hash -1207876549, now seen corresponding path program 1 times [2022-12-13 11:54:23,764 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 11:54:23,764 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [326675376] [2022-12-13 11:54:23,764 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 11:54:23,764 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 11:54:23,771 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 11:54:23,804 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 11:54:23,804 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 11:54:23,804 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [326675376] [2022-12-13 11:54:23,804 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [326675376] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 11:54:23,804 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 11:54:23,805 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 11:54:23,805 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2083505459] [2022-12-13 11:54:23,805 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 11:54:23,805 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 11:54:23,805 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 11:54:23,806 INFO L85 PathProgramCache]: Analyzing trace with hash -1344985505, now seen corresponding path program 1 times [2022-12-13 11:54:23,806 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 11:54:23,806 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [426757357] [2022-12-13 11:54:23,806 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 11:54:23,806 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 11:54:23,818 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 11:54:23,849 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 11:54:23,850 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 11:54:23,850 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [426757357] [2022-12-13 11:54:23,850 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [426757357] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 11:54:23,850 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 11:54:23,850 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 11:54:23,850 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1432121693] [2022-12-13 11:54:23,850 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 11:54:23,851 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 11:54:23,851 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 11:54:23,851 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 11:54:23,851 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 11:54:23,851 INFO L87 Difference]: Start difference. First operand 1509 states and 2238 transitions. cyclomatic complexity: 731 Second operand has 4 states, 4 states have (on average 23.75) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 11:54:23,981 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 11:54:23,982 INFO L93 Difference]: Finished difference Result 2723 states and 4027 transitions. [2022-12-13 11:54:23,982 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2723 states and 4027 transitions. [2022-12-13 11:54:23,998 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2590 [2022-12-13 11:54:24,021 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2723 states to 2723 states and 4027 transitions. [2022-12-13 11:54:24,021 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2723 [2022-12-13 11:54:24,022 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2723 [2022-12-13 11:54:24,023 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2723 states and 4027 transitions. [2022-12-13 11:54:24,025 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 11:54:24,025 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2723 states and 4027 transitions. [2022-12-13 11:54:24,027 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2723 states and 4027 transitions. [2022-12-13 11:54:24,051 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2723 to 2721. [2022-12-13 11:54:24,054 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2721 states, 2721 states have (on average 1.4792355751561925) internal successors, (4025), 2720 states have internal predecessors, (4025), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 11:54:24,059 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2721 states to 2721 states and 4025 transitions. [2022-12-13 11:54:24,059 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2721 states and 4025 transitions. [2022-12-13 11:54:24,060 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 11:54:24,060 INFO L428 stractBuchiCegarLoop]: Abstraction has 2721 states and 4025 transitions. [2022-12-13 11:54:24,060 INFO L335 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2022-12-13 11:54:24,060 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2721 states and 4025 transitions. [2022-12-13 11:54:24,067 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2590 [2022-12-13 11:54:24,067 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 11:54:24,068 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 11:54:24,068 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 11:54:24,069 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 11:54:24,069 INFO L748 eck$LassoCheckResult]: Stem: 18598#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 18599#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 19199#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 19200#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 19270#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 18742#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 18743#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 18869#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 18870#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 18644#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 18436#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 18437#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 18607#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 18608#L781 assume !(0 == ~M_E~0); 19117#L781-2 assume !(0 == ~T1_E~0); 19276#L786-1 assume !(0 == ~T2_E~0); 18396#L791-1 assume !(0 == ~T3_E~0); 18397#L796-1 assume !(0 == ~T4_E~0); 18943#L801-1 assume !(0 == ~T5_E~0); 18944#L806-1 assume !(0 == ~T6_E~0); 18980#L811-1 assume !(0 == ~T7_E~0); 18612#L816-1 assume !(0 == ~E_M~0); 18613#L821-1 assume !(0 == ~E_1~0); 18427#L826-1 assume !(0 == ~E_2~0); 18428#L831-1 assume !(0 == ~E_3~0); 18737#L836-1 assume !(0 == ~E_4~0); 18738#L841-1 assume !(0 == ~E_5~0); 18563#L846-1 assume !(0 == ~E_6~0); 18564#L851-1 assume !(0 == ~E_7~0); 18587#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 18588#L388 assume !(1 == ~m_pc~0); 18581#L388-2 is_master_triggered_~__retres1~0#1 := 0; 18582#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 19088#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 18442#L967 assume !(0 != activate_threads_~tmp~1#1); 18443#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 18372#L407 assume 1 == ~t1_pc~0; 18373#L408 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 18380#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 18381#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 18415#L975 assume !(0 != activate_threads_~tmp___0~0#1); 19197#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 18696#L426 assume !(1 == ~t2_pc~0); 18697#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 19224#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 18718#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 18719#L983 assume !(0 != activate_threads_~tmp___1~0#1); 19262#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 18785#L445 assume 1 == ~t3_pc~0; 18786#L446 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 19127#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 18370#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 18371#L991 assume !(0 != activate_threads_~tmp___2~0#1); 19048#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19012#L464 assume !(1 == ~t4_pc~0); 18591#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 18462#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 18463#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 18474#L999 assume !(0 != activate_threads_~tmp___3~0#1); 18764#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 18765#L483 assume 1 == ~t5_pc~0; 19008#L484 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 19177#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 19143#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 19144#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 18678#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 18679#L502 assume 1 == ~t6_pc~0; 18978#L503 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 18502#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 18503#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 18705#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 18907#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 19153#L521 assume !(1 == ~t7_pc~0); 19194#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 18438#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 18439#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 19188#L1023 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 19161#L1023-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19079#L869 assume 1 == ~M_E~0;~M_E~0 := 2; 19080#L869-2 assume !(1 == ~T1_E~0); 19258#L874-1 assume !(1 == ~T2_E~0); 19259#L879-1 assume !(1 == ~T3_E~0); 18833#L884-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 18834#L889-1 assume !(1 == ~T5_E~0); 18622#L894-1 assume !(1 == ~T6_E~0); 18623#L899-1 assume !(1 == ~T7_E~0); 19409#L904-1 assume !(1 == ~E_M~0); 19408#L909-1 assume !(1 == ~E_1~0); 19356#L914-1 assume !(1 == ~E_2~0); 19354#L919-1 assume !(1 == ~E_3~0); 18695#L924-1 assume 1 == ~E_4~0;~E_4~0 := 2; 18534#L929-1 assume !(1 == ~E_5~0); 18535#L934-1 assume !(1 == ~E_6~0); 19318#L939-1 assume !(1 == ~E_7~0); 19310#L944-1 assume { :end_inline_reset_delta_events } true; 19304#L1190-2 [2022-12-13 11:54:24,069 INFO L750 eck$LassoCheckResult]: Loop: 19304#L1190-2 assume !false; 19299#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 19298#L756 assume !false; 19297#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 19296#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 19288#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 19287#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 19285#L653 assume !(0 != eval_~tmp~0#1); 19284#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 19283#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 19281#L781-3 assume 0 == ~M_E~0;~M_E~0 := 1; 19282#L781-5 assume !(0 == ~T1_E~0); 20072#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 20046#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 20044#L796-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 20041#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 20038#L806-3 assume !(0 == ~T6_E~0); 20035#L811-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 20033#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 20028#L821-3 assume !(0 == ~E_1~0); 20020#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 20016#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 20012#L836-3 assume 0 == ~E_4~0;~E_4~0 := 1; 20008#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 20001#L846-3 assume !(0 == ~E_6~0); 19996#L851-3 assume 0 == ~E_7~0;~E_7~0 := 1; 19990#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 19985#L388-27 assume !(1 == ~m_pc~0); 19979#L388-29 is_master_triggered_~__retres1~0#1 := 0; 19974#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 19966#is_master_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 19961#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 19953#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 19948#L407-27 assume 1 == ~t1_pc~0; 19941#L408-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 19935#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 19933#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 19931#L975-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 19921#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 19901#L426-27 assume !(1 == ~t2_pc~0); 19895#L426-29 is_transmit2_triggered_~__retres1~2#1 := 0; 19885#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 19875#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 19869#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 19864#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 19856#L445-27 assume 1 == ~t3_pc~0; 19847#L446-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 19840#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 19828#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 19826#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 19820#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19813#L464-27 assume !(1 == ~t4_pc~0); 19777#L464-29 is_transmit4_triggered_~__retres1~4#1 := 0; 19775#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 19773#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 19771#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 19769#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 19766#L483-27 assume 1 == ~t5_pc~0; 19761#L484-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 19759#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 19757#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 19754#L1007-27 assume !(0 != activate_threads_~tmp___4~0#1); 19752#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 19750#L502-27 assume 1 == ~t6_pc~0; 19680#L503-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 19678#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 19676#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 19674#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 19672#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 19670#L521-27 assume !(1 == ~t7_pc~0); 19666#L521-29 is_transmit7_triggered_~__retres1~7#1 := 0; 19664#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 19662#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 19660#L1023-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 19623#L1023-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19614#L869-3 assume 1 == ~M_E~0;~M_E~0 := 2; 19231#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 19592#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 19590#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 19588#L884-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 19586#L889-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 19584#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 18524#L899-3 assume !(1 == ~T7_E~0); 19580#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 19578#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 19576#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 19566#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 19560#L924-3 assume 1 == ~E_4~0;~E_4~0 := 2; 19554#L929-3 assume 1 == ~E_5~0;~E_5~0 := 2; 19544#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 19540#L939-3 assume !(1 == ~E_7~0); 19539#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 19535#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 19527#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 19525#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 19523#L1209 assume !(0 == start_simulation_~tmp~3#1); 18908#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 19364#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 19357#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 19355#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 19353#L1164 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 19332#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 19319#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 19311#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 19304#L1190-2 [2022-12-13 11:54:24,069 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 11:54:24,070 INFO L85 PathProgramCache]: Analyzing trace with hash -253936391, now seen corresponding path program 1 times [2022-12-13 11:54:24,070 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 11:54:24,070 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1458876562] [2022-12-13 11:54:24,070 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 11:54:24,070 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 11:54:24,077 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 11:54:24,109 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 11:54:24,109 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 11:54:24,109 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1458876562] [2022-12-13 11:54:24,109 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1458876562] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 11:54:24,109 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 11:54:24,110 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 11:54:24,110 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [482664575] [2022-12-13 11:54:24,110 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 11:54:24,110 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 11:54:24,110 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 11:54:24,111 INFO L85 PathProgramCache]: Analyzing trace with hash 176561758, now seen corresponding path program 1 times [2022-12-13 11:54:24,111 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 11:54:24,111 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [317742737] [2022-12-13 11:54:24,111 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 11:54:24,111 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 11:54:24,118 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 11:54:24,138 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 11:54:24,138 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 11:54:24,138 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [317742737] [2022-12-13 11:54:24,138 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [317742737] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 11:54:24,138 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 11:54:24,138 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 11:54:24,139 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [460852667] [2022-12-13 11:54:24,139 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 11:54:24,139 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 11:54:24,139 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 11:54:24,139 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 11:54:24,140 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 11:54:24,140 INFO L87 Difference]: Start difference. First operand 2721 states and 4025 transitions. cyclomatic complexity: 1308 Second operand has 4 states, 4 states have (on average 23.75) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 11:54:24,366 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 11:54:24,366 INFO L93 Difference]: Finished difference Result 7498 states and 10918 transitions. [2022-12-13 11:54:24,366 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7498 states and 10918 transitions. [2022-12-13 11:54:24,398 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 7117 [2022-12-13 11:54:24,423 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7498 states to 7498 states and 10918 transitions. [2022-12-13 11:54:24,424 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7498 [2022-12-13 11:54:24,430 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7498 [2022-12-13 11:54:24,430 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7498 states and 10918 transitions. [2022-12-13 11:54:24,438 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 11:54:24,438 INFO L218 hiAutomatonCegarLoop]: Abstraction has 7498 states and 10918 transitions. [2022-12-13 11:54:24,444 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7498 states and 10918 transitions. [2022-12-13 11:54:24,552 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7498 to 7066. [2022-12-13 11:54:24,561 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7066 states, 7066 states have (on average 1.4613642796490236) internal successors, (10326), 7065 states have internal predecessors, (10326), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 11:54:24,574 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7066 states to 7066 states and 10326 transitions. [2022-12-13 11:54:24,574 INFO L240 hiAutomatonCegarLoop]: Abstraction has 7066 states and 10326 transitions. [2022-12-13 11:54:24,574 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 11:54:24,575 INFO L428 stractBuchiCegarLoop]: Abstraction has 7066 states and 10326 transitions. [2022-12-13 11:54:24,575 INFO L335 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2022-12-13 11:54:24,575 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7066 states and 10326 transitions. [2022-12-13 11:54:24,596 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 6917 [2022-12-13 11:54:24,596 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 11:54:24,596 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 11:54:24,597 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 11:54:24,597 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 11:54:24,598 INFO L748 eck$LassoCheckResult]: Stem: 28833#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 28834#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 29504#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 29505#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 29604#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 28982#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 28983#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 29116#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 29117#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 28878#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 28663#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 28664#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 28838#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 28839#L781 assume !(0 == ~M_E~0); 29403#L781-2 assume !(0 == ~T1_E~0); 29623#L786-1 assume !(0 == ~T2_E~0); 28623#L791-1 assume !(0 == ~T3_E~0); 28624#L796-1 assume !(0 == ~T4_E~0); 29198#L801-1 assume !(0 == ~T5_E~0); 29199#L806-1 assume !(0 == ~T6_E~0); 29242#L811-1 assume !(0 == ~T7_E~0); 28845#L816-1 assume !(0 == ~E_M~0); 28846#L821-1 assume !(0 == ~E_1~0); 28654#L826-1 assume !(0 == ~E_2~0); 28655#L831-1 assume !(0 == ~E_3~0); 28977#L836-1 assume !(0 == ~E_4~0); 28978#L841-1 assume !(0 == ~E_5~0); 28797#L846-1 assume !(0 == ~E_6~0); 28798#L851-1 assume !(0 == ~E_7~0); 28822#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 28823#L388 assume !(1 == ~m_pc~0); 28816#L388-2 is_master_triggered_~__retres1~0#1 := 0; 28817#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 29364#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 28669#L967 assume !(0 != activate_threads_~tmp~1#1); 28670#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 28601#L407 assume !(1 == ~t1_pc~0); 28602#L407-2 is_transmit1_triggered_~__retres1~1#1 := 0; 28605#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 28606#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 28640#L975 assume !(0 != activate_threads_~tmp___0~0#1); 29502#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 28934#L426 assume !(1 == ~t2_pc~0); 28935#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 29528#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 28956#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 28957#L983 assume !(0 != activate_threads_~tmp___1~0#1); 29587#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 29023#L445 assume 1 == ~t3_pc~0; 29024#L446 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 29415#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 28599#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 28600#L991 assume !(0 != activate_threads_~tmp___2~0#1); 29313#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 29272#L464 assume !(1 == ~t4_pc~0); 28826#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 28689#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 28690#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 28703#L999 assume !(0 != activate_threads_~tmp___3~0#1); 29003#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 29004#L483 assume 1 == ~t5_pc~0; 29268#L484 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 29481#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 29437#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 29438#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 28916#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 28917#L502 assume 1 == ~t6_pc~0; 29239#L503 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 28732#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 28733#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 28941#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 29157#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 29451#L521 assume !(1 == ~t7_pc~0); 29499#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 28665#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 28666#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 29493#L1023 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 29460#L1023-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 29349#L869 assume 1 == ~M_E~0;~M_E~0 := 2; 29350#L869-2 assume !(1 == ~T1_E~0); 30918#L874-1 assume !(1 == ~T2_E~0); 30917#L879-1 assume !(1 == ~T3_E~0); 30916#L884-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 30915#L889-1 assume !(1 == ~T5_E~0); 28852#L894-1 assume !(1 == ~T6_E~0); 28853#L899-1 assume !(1 == ~T7_E~0); 29297#L904-1 assume !(1 == ~E_M~0); 29019#L909-1 assume !(1 == ~E_1~0); 29020#L914-1 assume !(1 == ~E_2~0); 29224#L919-1 assume !(1 == ~E_3~0); 29251#L924-1 assume 1 == ~E_4~0;~E_4~0 := 2; 30843#L929-1 assume !(1 == ~E_5~0); 30841#L934-1 assume !(1 == ~E_6~0); 30830#L939-1 assume !(1 == ~E_7~0); 30822#L944-1 assume { :end_inline_reset_delta_events } true; 30816#L1190-2 [2022-12-13 11:54:24,598 INFO L750 eck$LassoCheckResult]: Loop: 30816#L1190-2 assume !false; 30811#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 30810#L756 assume !false; 30809#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 30808#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 30800#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 30799#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 30797#L653 assume !(0 != eval_~tmp~0#1); 30796#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 30795#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 30792#L781-3 assume 0 == ~M_E~0;~M_E~0 := 1; 30793#L781-5 assume !(0 == ~T1_E~0); 31353#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 31351#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 31349#L796-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 31347#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 31345#L806-3 assume !(0 == ~T6_E~0); 31343#L811-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 31341#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 31339#L821-3 assume !(0 == ~E_1~0); 31337#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 31335#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 31333#L836-3 assume 0 == ~E_4~0;~E_4~0 := 1; 31331#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 31329#L846-3 assume !(0 == ~E_6~0); 31327#L851-3 assume 0 == ~E_7~0;~E_7~0 := 1; 31325#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 31323#L388-27 assume !(1 == ~m_pc~0); 31321#L388-29 is_master_triggered_~__retres1~0#1 := 0; 31319#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 31317#is_master_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 31314#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 31312#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 31310#L407-27 assume !(1 == ~t1_pc~0); 31308#L407-29 is_transmit1_triggered_~__retres1~1#1 := 0; 31306#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 31304#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 31301#L975-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 31299#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 31297#L426-27 assume !(1 == ~t2_pc~0); 31294#L426-29 is_transmit2_triggered_~__retres1~2#1 := 0; 31292#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 31290#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 31287#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 31285#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 31283#L445-27 assume 1 == ~t3_pc~0; 31280#L446-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 31278#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 31276#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 31273#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 31272#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 31271#L464-27 assume !(1 == ~t4_pc~0); 31268#L464-29 is_transmit4_triggered_~__retres1~4#1 := 0; 31266#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 31264#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 31262#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 31260#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 31258#L483-27 assume 1 == ~t5_pc~0; 31255#L484-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 31253#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 31251#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 31249#L1007-27 assume !(0 != activate_threads_~tmp___4~0#1); 31247#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 31245#L502-27 assume 1 == ~t6_pc~0; 31242#L503-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 31239#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 31237#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 31235#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 31223#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 31222#L521-27 assume !(1 == ~t7_pc~0); 31197#L521-29 is_transmit7_triggered_~__retres1~7#1 := 0; 31195#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 31192#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 31190#L1023-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 31164#L1023-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 31146#L869-3 assume 1 == ~M_E~0;~M_E~0 := 2; 31123#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 31121#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 31119#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 31117#L884-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 31098#L889-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 31096#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 28755#L899-3 assume !(1 == ~T7_E~0); 31057#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 31055#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 31053#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 31052#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 31051#L924-3 assume 1 == ~E_4~0;~E_4~0 := 2; 31039#L929-3 assume 1 == ~E_5~0;~E_5~0 := 2; 31020#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 31004#L939-3 assume !(1 == ~E_7~0); 30989#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 30972#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 30964#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 30942#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 30941#L1209 assume !(0 == start_simulation_~tmp~3#1); 29160#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 30909#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 30903#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 30868#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 30854#L1164 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 30842#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 30831#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 30823#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 30816#L1190-2 [2022-12-13 11:54:24,598 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 11:54:24,598 INFO L85 PathProgramCache]: Analyzing trace with hash -1285267206, now seen corresponding path program 1 times [2022-12-13 11:54:24,598 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 11:54:24,598 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [128466544] [2022-12-13 11:54:24,598 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 11:54:24,598 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 11:54:24,606 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 11:54:24,641 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 11:54:24,641 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 11:54:24,641 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [128466544] [2022-12-13 11:54:24,641 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [128466544] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 11:54:24,642 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 11:54:24,642 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 11:54:24,642 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [218187779] [2022-12-13 11:54:24,642 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 11:54:24,642 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 11:54:24,642 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 11:54:24,643 INFO L85 PathProgramCache]: Analyzing trace with hash -1778759457, now seen corresponding path program 1 times [2022-12-13 11:54:24,643 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 11:54:24,643 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [215382924] [2022-12-13 11:54:24,643 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 11:54:24,643 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 11:54:24,652 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 11:54:24,674 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 11:54:24,674 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 11:54:24,674 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [215382924] [2022-12-13 11:54:24,674 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [215382924] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 11:54:24,674 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 11:54:24,675 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 11:54:24,675 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1551948232] [2022-12-13 11:54:24,675 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 11:54:24,675 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 11:54:24,675 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 11:54:24,676 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 11:54:24,676 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 11:54:24,676 INFO L87 Difference]: Start difference. First operand 7066 states and 10326 transitions. cyclomatic complexity: 3268 Second operand has 4 states, 4 states have (on average 23.75) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 11:54:24,909 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 11:54:24,909 INFO L93 Difference]: Finished difference Result 19679 states and 28431 transitions. [2022-12-13 11:54:24,910 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 19679 states and 28431 transitions. [2022-12-13 11:54:25,007 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 18975 [2022-12-13 11:54:25,068 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 19679 states to 19679 states and 28431 transitions. [2022-12-13 11:54:25,069 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 19679 [2022-12-13 11:54:25,080 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 19679 [2022-12-13 11:54:25,080 INFO L73 IsDeterministic]: Start isDeterministic. Operand 19679 states and 28431 transitions. [2022-12-13 11:54:25,096 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 11:54:25,096 INFO L218 hiAutomatonCegarLoop]: Abstraction has 19679 states and 28431 transitions. [2022-12-13 11:54:25,109 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 19679 states and 28431 transitions. [2022-12-13 11:54:25,330 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 19679 to 18731. [2022-12-13 11:54:25,354 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 18731 states, 18731 states have (on average 1.4497357322086382) internal successors, (27155), 18730 states have internal predecessors, (27155), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 11:54:25,391 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 18731 states to 18731 states and 27155 transitions. [2022-12-13 11:54:25,391 INFO L240 hiAutomatonCegarLoop]: Abstraction has 18731 states and 27155 transitions. [2022-12-13 11:54:25,391 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 11:54:25,392 INFO L428 stractBuchiCegarLoop]: Abstraction has 18731 states and 27155 transitions. [2022-12-13 11:54:25,392 INFO L335 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2022-12-13 11:54:25,392 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 18731 states and 27155 transitions. [2022-12-13 11:54:25,440 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 18543 [2022-12-13 11:54:25,440 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 11:54:25,440 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 11:54:25,441 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 11:54:25,442 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 11:54:25,442 INFO L748 eck$LassoCheckResult]: Stem: 55582#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 55583#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 56278#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 56279#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 56388#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 55731#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 55732#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 55863#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 55864#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 55629#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 55416#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 55417#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 55588#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 55589#L781 assume !(0 == ~M_E~0); 56161#L781-2 assume !(0 == ~T1_E~0); 56412#L786-1 assume !(0 == ~T2_E~0); 55377#L791-1 assume !(0 == ~T3_E~0); 55378#L796-1 assume !(0 == ~T4_E~0); 55953#L801-1 assume !(0 == ~T5_E~0); 55954#L806-1 assume !(0 == ~T6_E~0); 55995#L811-1 assume !(0 == ~T7_E~0); 55595#L816-1 assume !(0 == ~E_M~0); 55596#L821-1 assume !(0 == ~E_1~0); 55408#L826-1 assume !(0 == ~E_2~0); 55409#L831-1 assume !(0 == ~E_3~0); 55726#L836-1 assume !(0 == ~E_4~0); 55727#L841-1 assume !(0 == ~E_5~0); 55547#L846-1 assume !(0 == ~E_6~0); 55548#L851-1 assume !(0 == ~E_7~0); 55571#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 55572#L388 assume !(1 == ~m_pc~0); 55565#L388-2 is_master_triggered_~__retres1~0#1 := 0; 55566#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 56123#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 55422#L967 assume !(0 != activate_threads_~tmp~1#1); 55423#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 55356#L407 assume !(1 == ~t1_pc~0); 55357#L407-2 is_transmit1_triggered_~__retres1~1#1 := 0; 55360#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 55361#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 55394#L975 assume !(0 != activate_threads_~tmp___0~0#1); 56272#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 55682#L426 assume !(1 == ~t2_pc~0); 55683#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 56304#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 55706#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 55707#L983 assume !(0 != activate_threads_~tmp___1~0#1); 56369#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 55775#L445 assume !(1 == ~t3_pc~0); 55776#L445-2 is_transmit3_triggered_~__retres1~3#1 := 0; 56173#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 55354#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 55355#L991 assume !(0 != activate_threads_~tmp___2~0#1); 56074#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 56034#L464 assume !(1 == ~t4_pc~0); 55575#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 55442#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 55443#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 55456#L999 assume !(0 != activate_threads_~tmp___3~0#1); 55752#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 55753#L483 assume 1 == ~t5_pc~0; 56029#L484 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 56250#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 56197#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 56198#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 55665#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 55666#L502 assume 1 == ~t6_pc~0; 55992#L503 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 55484#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 55485#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 55689#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 55908#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 56216#L521 assume !(1 == ~t7_pc~0); 56268#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 55418#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 55419#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 56262#L1023 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 56227#L1023-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 56111#L869 assume 1 == ~M_E~0;~M_E~0 := 2; 56112#L869-2 assume !(1 == ~T1_E~0); 56365#L874-1 assume !(1 == ~T2_E~0); 56366#L879-1 assume !(1 == ~T3_E~0); 55823#L884-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 55824#L889-1 assume !(1 == ~T5_E~0); 55602#L894-1 assume !(1 == ~T6_E~0); 55603#L899-1 assume !(1 == ~T7_E~0); 56059#L904-1 assume !(1 == ~E_M~0); 55770#L909-1 assume !(1 == ~E_1~0); 55771#L914-1 assume !(1 == ~E_2~0); 55977#L919-1 assume !(1 == ~E_3~0); 56007#L924-1 assume 1 == ~E_4~0;~E_4~0 := 2; 61617#L929-1 assume !(1 == ~E_5~0); 61615#L934-1 assume !(1 == ~E_6~0); 56338#L939-1 assume !(1 == ~E_7~0); 61559#L944-1 assume { :end_inline_reset_delta_events } true; 61547#L1190-2 [2022-12-13 11:54:25,442 INFO L750 eck$LassoCheckResult]: Loop: 61547#L1190-2 assume !false; 61541#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 61531#L756 assume !false; 61530#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 61511#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 61500#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 61494#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 61485#L653 assume !(0 != eval_~tmp~0#1); 61486#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 62576#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 62574#L781-3 assume 0 == ~M_E~0;~M_E~0 := 1; 62572#L781-5 assume !(0 == ~T1_E~0); 62570#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 62568#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 62566#L796-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 62564#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 62562#L806-3 assume !(0 == ~T6_E~0); 62560#L811-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 62558#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 62556#L821-3 assume !(0 == ~E_1~0); 62554#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 62552#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 62550#L836-3 assume 0 == ~E_4~0;~E_4~0 := 1; 62548#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 62546#L846-3 assume !(0 == ~E_6~0); 62544#L851-3 assume 0 == ~E_7~0;~E_7~0 := 1; 62542#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 62540#L388-27 assume !(1 == ~m_pc~0); 62538#L388-29 is_master_triggered_~__retres1~0#1 := 0; 62536#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 62534#is_master_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 62532#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 62530#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 62528#L407-27 assume !(1 == ~t1_pc~0); 62526#L407-29 is_transmit1_triggered_~__retres1~1#1 := 0; 62524#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 62522#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 62520#L975-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 62518#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 62515#L426-27 assume !(1 == ~t2_pc~0); 62512#L426-29 is_transmit2_triggered_~__retres1~2#1 := 0; 62510#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 62508#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 62506#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 62504#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 62502#L445-27 assume !(1 == ~t3_pc~0); 62500#L445-29 is_transmit3_triggered_~__retres1~3#1 := 0; 62498#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 62496#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 62494#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 62492#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 62489#L464-27 assume !(1 == ~t4_pc~0); 62486#L464-29 is_transmit4_triggered_~__retres1~4#1 := 0; 62484#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 62482#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 62480#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 62478#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 62475#L483-27 assume 1 == ~t5_pc~0; 62472#L484-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 62470#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 62468#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 62466#L1007-27 assume !(0 != activate_threads_~tmp___4~0#1); 62464#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 62461#L502-27 assume 1 == ~t6_pc~0; 62458#L503-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 62456#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 62454#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 62452#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 62450#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 62447#L521-27 assume !(1 == ~t7_pc~0); 62444#L521-29 is_transmit7_triggered_~__retres1~7#1 := 0; 62442#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 62440#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 62438#L1023-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 62437#L1023-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 62436#L869-3 assume 1 == ~M_E~0;~M_E~0 := 2; 61138#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 62431#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 62429#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 62427#L884-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 62425#L889-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 62423#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 62419#L899-3 assume !(1 == ~T7_E~0); 62417#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 62415#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 62413#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 62411#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 62409#L924-3 assume 1 == ~E_4~0;~E_4~0 := 2; 62398#L929-3 assume 1 == ~E_5~0;~E_5~0 := 2; 62392#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 62003#L939-3 assume !(1 == ~E_7~0); 62380#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 62193#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 62182#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 62174#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 62168#L1209 assume !(0 == start_simulation_~tmp~3#1); 62166#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 61685#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 61678#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 61675#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 61673#L1164 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 61566#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 61562#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 61560#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 61547#L1190-2 [2022-12-13 11:54:25,442 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 11:54:25,443 INFO L85 PathProgramCache]: Analyzing trace with hash 1116257915, now seen corresponding path program 1 times [2022-12-13 11:54:25,443 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 11:54:25,443 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1638123514] [2022-12-13 11:54:25,443 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 11:54:25,443 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 11:54:25,451 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 11:54:25,478 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 11:54:25,479 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 11:54:25,479 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1638123514] [2022-12-13 11:54:25,479 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1638123514] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 11:54:25,479 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 11:54:25,479 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-12-13 11:54:25,479 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [185442206] [2022-12-13 11:54:25,479 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 11:54:25,480 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 11:54:25,480 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 11:54:25,480 INFO L85 PathProgramCache]: Analyzing trace with hash 1484877024, now seen corresponding path program 1 times [2022-12-13 11:54:25,480 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 11:54:25,480 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [653396251] [2022-12-13 11:54:25,480 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 11:54:25,480 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 11:54:25,488 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 11:54:25,507 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 11:54:25,507 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 11:54:25,507 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [653396251] [2022-12-13 11:54:25,507 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [653396251] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 11:54:25,507 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 11:54:25,507 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 11:54:25,507 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [801138882] [2022-12-13 11:54:25,507 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 11:54:25,508 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 11:54:25,508 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 11:54:25,508 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 11:54:25,508 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 11:54:25,508 INFO L87 Difference]: Start difference. First operand 18731 states and 27155 transitions. cyclomatic complexity: 8440 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 2 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 11:54:25,681 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 11:54:25,681 INFO L93 Difference]: Finished difference Result 36058 states and 51973 transitions. [2022-12-13 11:54:25,681 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 36058 states and 51973 transitions. [2022-12-13 11:54:25,847 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 35739 [2022-12-13 11:54:26,002 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 36058 states to 36058 states and 51973 transitions. [2022-12-13 11:54:26,002 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 36058 [2022-12-13 11:54:26,038 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 36058 [2022-12-13 11:54:26,038 INFO L73 IsDeterministic]: Start isDeterministic. Operand 36058 states and 51973 transitions. [2022-12-13 11:54:26,068 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 11:54:26,069 INFO L218 hiAutomatonCegarLoop]: Abstraction has 36058 states and 51973 transitions. [2022-12-13 11:54:26,110 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 36058 states and 51973 transitions. [2022-12-13 11:54:26,483 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 36058 to 35986. [2022-12-13 11:54:26,521 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 35986 states, 35986 states have (on average 1.442255321513922) internal successors, (51901), 35985 states have internal predecessors, (51901), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 11:54:26,629 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 35986 states to 35986 states and 51901 transitions. [2022-12-13 11:54:26,630 INFO L240 hiAutomatonCegarLoop]: Abstraction has 35986 states and 51901 transitions. [2022-12-13 11:54:26,630 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 11:54:26,631 INFO L428 stractBuchiCegarLoop]: Abstraction has 35986 states and 51901 transitions. [2022-12-13 11:54:26,631 INFO L335 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2022-12-13 11:54:26,631 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 35986 states and 51901 transitions. [2022-12-13 11:54:26,704 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 35667 [2022-12-13 11:54:26,704 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 11:54:26,704 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 11:54:26,705 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 11:54:26,705 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 11:54:26,705 INFO L748 eck$LassoCheckResult]: Stem: 110372#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 110373#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 111013#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 111014#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 111100#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 110515#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 110516#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 110642#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 110643#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 110417#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 110212#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 110213#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 110378#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 110379#L781 assume !(0 == ~M_E~0); 110914#L781-2 assume !(0 == ~T1_E~0); 111117#L786-1 assume !(0 == ~T2_E~0); 110173#L791-1 assume !(0 == ~T3_E~0); 110174#L796-1 assume !(0 == ~T4_E~0); 110722#L801-1 assume !(0 == ~T5_E~0); 110723#L806-1 assume !(0 == ~T6_E~0); 110762#L811-1 assume !(0 == ~T7_E~0); 110386#L816-1 assume !(0 == ~E_M~0); 110387#L821-1 assume !(0 == ~E_1~0); 110204#L826-1 assume !(0 == ~E_2~0); 110205#L831-1 assume !(0 == ~E_3~0); 110510#L836-1 assume !(0 == ~E_4~0); 110511#L841-1 assume !(0 == ~E_5~0); 110338#L846-1 assume !(0 == ~E_6~0); 110339#L851-1 assume !(0 == ~E_7~0); 110362#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 110363#L388 assume !(1 == ~m_pc~0); 110356#L388-2 is_master_triggered_~__retres1~0#1 := 0; 110357#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 110884#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 110218#L967 assume !(0 != activate_threads_~tmp~1#1); 110219#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 110152#L407 assume !(1 == ~t1_pc~0); 110153#L407-2 is_transmit1_triggered_~__retres1~1#1 := 0; 110156#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 110157#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 110190#L975 assume !(0 != activate_threads_~tmp___0~0#1); 111010#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 110467#L426 assume !(1 == ~t2_pc~0); 110468#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 111038#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 110490#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 110491#L983 assume !(0 != activate_threads_~tmp___1~0#1); 111085#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 110556#L445 assume !(1 == ~t3_pc~0); 110557#L445-2 is_transmit3_triggered_~__retres1~3#1 := 0; 110925#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 110150#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 110151#L991 assume !(0 != activate_threads_~tmp___2~0#1); 110835#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 110796#L464 assume !(1 == ~t4_pc~0); 110366#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 110238#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 110239#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 110250#L999 assume !(0 != activate_threads_~tmp___3~0#1); 110534#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 110535#L483 assume !(1 == ~t5_pc~0); 110792#L483-2 is_transmit5_triggered_~__retres1~5#1 := 0; 110990#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 110947#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 110948#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 110450#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 110451#L502 assume 1 == ~t6_pc~0; 110759#L503 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 110278#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 110279#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 110475#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 110685#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 110961#L521 assume !(1 == ~t7_pc~0); 111006#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 110214#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 110215#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 111000#L1023 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 110971#L1023-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 110872#L869 assume 1 == ~M_E~0;~M_E~0 := 2; 110528#L869-2 assume !(1 == ~T1_E~0); 110529#L874-1 assume !(1 == ~T2_E~0); 111052#L879-1 assume !(1 == ~T3_E~0); 110603#L884-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 110138#L889-1 assume !(1 == ~T5_E~0); 110139#L894-1 assume !(1 == ~T6_E~0); 110393#L899-1 assume !(1 == ~T7_E~0); 110820#L904-1 assume !(1 == ~E_M~0); 110551#L909-1 assume !(1 == ~E_1~0); 110552#L914-1 assume !(1 == ~E_2~0); 110745#L919-1 assume !(1 == ~E_3~0); 110466#L924-1 assume 1 == ~E_4~0;~E_4~0 := 2; 110310#L929-1 assume !(1 == ~E_5~0); 110311#L934-1 assume !(1 == ~E_6~0); 110530#L939-1 assume !(1 == ~E_7~0); 110531#L944-1 assume { :end_inline_reset_delta_events } true; 110375#L1190-2 [2022-12-13 11:54:26,706 INFO L750 eck$LassoCheckResult]: Loop: 110375#L1190-2 assume !false; 110388#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 110389#L756 assume !false; 143162#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 142586#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 142574#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 125519#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 125511#L653 assume !(0 != eval_~tmp~0#1); 125513#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 144725#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 144724#L781-3 assume 0 == ~M_E~0;~M_E~0 := 1; 144723#L781-5 assume !(0 == ~T1_E~0); 144722#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 144721#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 144720#L796-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 144719#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 144718#L806-3 assume !(0 == ~T6_E~0); 144717#L811-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 144716#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 144715#L821-3 assume !(0 == ~E_1~0); 144714#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 144713#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 144712#L836-3 assume 0 == ~E_4~0;~E_4~0 := 1; 144711#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 144710#L846-3 assume !(0 == ~E_6~0); 144709#L851-3 assume 0 == ~E_7~0;~E_7~0 := 1; 144708#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 144707#L388-27 assume !(1 == ~m_pc~0); 144706#L388-29 is_master_triggered_~__retres1~0#1 := 0; 144705#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 144704#is_master_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 144703#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 144702#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 144701#L407-27 assume !(1 == ~t1_pc~0); 144700#L407-29 is_transmit1_triggered_~__retres1~1#1 := 0; 144699#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 144698#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 144697#L975-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 144696#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 144695#L426-27 assume 1 == ~t2_pc~0; 144694#L427-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 144692#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 144691#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 144690#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 144689#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 144688#L445-27 assume !(1 == ~t3_pc~0); 144687#L445-29 is_transmit3_triggered_~__retres1~3#1 := 0; 144686#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 144685#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 144684#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 144683#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 144682#L464-27 assume !(1 == ~t4_pc~0); 144680#L464-29 is_transmit4_triggered_~__retres1~4#1 := 0; 144679#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 144678#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 144677#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 144676#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 144675#L483-27 assume !(1 == ~t5_pc~0); 144674#L483-29 is_transmit5_triggered_~__retres1~5#1 := 0; 144673#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 144672#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 144671#L1007-27 assume !(0 != activate_threads_~tmp___4~0#1); 144670#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 144669#L502-27 assume 1 == ~t6_pc~0; 144667#L503-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 144666#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 144665#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 144664#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 144663#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 144662#L521-27 assume !(1 == ~t7_pc~0); 144660#L521-29 is_transmit7_triggered_~__retres1~7#1 := 0; 144659#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 144658#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 144657#L1023-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 144656#L1023-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 144655#L869-3 assume 1 == ~M_E~0;~M_E~0 := 2; 131031#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 144654#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 144653#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 144652#L884-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 144651#L889-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 144650#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 131017#L899-3 assume !(1 == ~T7_E~0); 144649#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 144648#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 144647#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 144646#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 144645#L924-3 assume 1 == ~E_4~0;~E_4~0 := 2; 144644#L929-3 assume 1 == ~E_5~0;~E_5~0 := 2; 144643#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 134018#L939-3 assume !(1 == ~E_7~0); 144642#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 144624#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 144617#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 144615#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 144542#L1209 assume !(0 == start_simulation_~tmp~3#1); 144541#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 110652#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 110293#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 110186#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 110187#L1164 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 110182#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 110183#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 110374#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 110375#L1190-2 [2022-12-13 11:54:26,706 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 11:54:26,706 INFO L85 PathProgramCache]: Analyzing trace with hash -2127260292, now seen corresponding path program 1 times [2022-12-13 11:54:26,706 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 11:54:26,706 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [381099823] [2022-12-13 11:54:26,706 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 11:54:26,706 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 11:54:26,715 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 11:54:26,750 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 11:54:26,750 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 11:54:26,750 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [381099823] [2022-12-13 11:54:26,750 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [381099823] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 11:54:26,750 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 11:54:26,751 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 11:54:26,751 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [919286669] [2022-12-13 11:54:26,751 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 11:54:26,751 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 11:54:26,751 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 11:54:26,752 INFO L85 PathProgramCache]: Analyzing trace with hash -786207968, now seen corresponding path program 1 times [2022-12-13 11:54:26,752 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 11:54:26,752 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [675952862] [2022-12-13 11:54:26,752 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 11:54:26,752 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 11:54:26,763 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 11:54:26,845 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 11:54:26,845 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 11:54:26,845 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [675952862] [2022-12-13 11:54:26,845 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [675952862] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 11:54:26,845 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 11:54:26,846 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 11:54:26,846 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1496958815] [2022-12-13 11:54:26,846 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 11:54:26,846 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 11:54:26,846 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 11:54:26,847 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 11:54:26,847 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 11:54:26,848 INFO L87 Difference]: Start difference. First operand 35986 states and 51901 transitions. cyclomatic complexity: 15947 Second operand has 4 states, 4 states have (on average 23.75) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 11:54:27,516 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 11:54:27,516 INFO L93 Difference]: Finished difference Result 99247 states and 142032 transitions. [2022-12-13 11:54:27,516 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 99247 states and 142032 transitions. [2022-12-13 11:54:27,891 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 96417 [2022-12-13 11:54:28,116 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 99247 states to 99247 states and 142032 transitions. [2022-12-13 11:54:28,116 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 99247 [2022-12-13 11:54:28,151 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 99247 [2022-12-13 11:54:28,152 INFO L73 IsDeterministic]: Start isDeterministic. Operand 99247 states and 142032 transitions. [2022-12-13 11:54:28,187 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 11:54:28,188 INFO L218 hiAutomatonCegarLoop]: Abstraction has 99247 states and 142032 transitions. [2022-12-13 11:54:28,224 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 99247 states and 142032 transitions. [2022-12-13 11:54:28,955 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 99247 to 95959. [2022-12-13 11:54:29,034 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 95959 states, 95959 states have (on average 1.4359466021946874) internal successors, (137792), 95958 states have internal predecessors, (137792), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 11:54:29,214 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 95959 states to 95959 states and 137792 transitions. [2022-12-13 11:54:29,214 INFO L240 hiAutomatonCegarLoop]: Abstraction has 95959 states and 137792 transitions. [2022-12-13 11:54:29,215 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 11:54:29,215 INFO L428 stractBuchiCegarLoop]: Abstraction has 95959 states and 137792 transitions. [2022-12-13 11:54:29,215 INFO L335 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2022-12-13 11:54:29,216 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 95959 states and 137792 transitions. [2022-12-13 11:54:29,491 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 95337 [2022-12-13 11:54:29,491 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 11:54:29,491 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 11:54:29,492 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 11:54:29,492 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 11:54:29,493 INFO L748 eck$LassoCheckResult]: Stem: 245616#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 245617#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 246272#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 246273#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 246368#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 245762#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 245763#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 245897#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 245898#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 245661#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 245455#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 245456#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 245621#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 245622#L781 assume !(0 == ~M_E~0); 246165#L781-2 assume !(0 == ~T1_E~0); 246384#L786-1 assume !(0 == ~T2_E~0); 245416#L791-1 assume !(0 == ~T3_E~0); 245417#L796-1 assume !(0 == ~T4_E~0); 245982#L801-1 assume !(0 == ~T5_E~0); 245983#L806-1 assume !(0 == ~T6_E~0); 246025#L811-1 assume !(0 == ~T7_E~0); 245628#L816-1 assume !(0 == ~E_M~0); 245629#L821-1 assume !(0 == ~E_1~0); 245447#L826-1 assume !(0 == ~E_2~0); 245448#L831-1 assume !(0 == ~E_3~0); 245757#L836-1 assume !(0 == ~E_4~0); 245758#L841-1 assume !(0 == ~E_5~0); 245582#L846-1 assume !(0 == ~E_6~0); 245583#L851-1 assume !(0 == ~E_7~0); 245606#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 245607#L388 assume !(1 == ~m_pc~0); 245600#L388-2 is_master_triggered_~__retres1~0#1 := 0; 245601#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 246138#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 245461#L967 assume !(0 != activate_threads_~tmp~1#1); 245462#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 245395#L407 assume !(1 == ~t1_pc~0); 245396#L407-2 is_transmit1_triggered_~__retres1~1#1 := 0; 245399#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 245400#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 245433#L975 assume !(0 != activate_threads_~tmp___0~0#1); 246265#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 245712#L426 assume !(1 == ~t2_pc~0); 245713#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 246297#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 245737#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 245738#L983 assume !(0 != activate_threads_~tmp___1~0#1); 246352#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 245805#L445 assume !(1 == ~t3_pc~0); 245806#L445-2 is_transmit3_triggered_~__retres1~3#1 := 0; 246172#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 245393#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 245394#L991 assume !(0 != activate_threads_~tmp___2~0#1); 246092#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 246054#L464 assume !(1 == ~t4_pc~0); 245610#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 245481#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 245482#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 245493#L999 assume !(0 != activate_threads_~tmp___3~0#1); 245783#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 245784#L483 assume !(1 == ~t5_pc~0); 246050#L483-2 is_transmit5_triggered_~__retres1~5#1 := 0; 246240#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 246197#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 246198#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 245697#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 245698#L502 assume !(1 == ~t6_pc~0); 245561#L502-2 is_transmit6_triggered_~__retres1~6#1 := 0; 245521#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 245522#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 245721#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 245941#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 246215#L521 assume !(1 == ~t7_pc~0); 246258#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 245457#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 245458#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 246252#L1023 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 246221#L1023-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 246128#L869 assume 1 == ~M_E~0;~M_E~0 := 2; 246129#L869-2 assume !(1 == ~T1_E~0); 246347#L874-1 assume !(1 == ~T2_E~0); 246348#L879-1 assume !(1 == ~T3_E~0); 245857#L884-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 245858#L889-1 assume !(1 == ~T5_E~0); 245635#L894-1 assume !(1 == ~T6_E~0); 245636#L899-1 assume !(1 == ~T7_E~0); 246080#L904-1 assume !(1 == ~E_M~0); 245799#L909-1 assume !(1 == ~E_1~0); 245800#L914-1 assume !(1 == ~E_2~0); 246003#L919-1 assume !(1 == ~E_3~0); 245711#L924-1 assume 1 == ~E_4~0;~E_4~0 := 2; 245553#L929-1 assume !(1 == ~E_5~0); 245554#L934-1 assume !(1 == ~E_6~0); 246326#L939-1 assume !(1 == ~E_7~0); 329038#L944-1 assume { :end_inline_reset_delta_events } true; 329036#L1190-2 [2022-12-13 11:54:29,493 INFO L750 eck$LassoCheckResult]: Loop: 329036#L1190-2 assume !false; 328915#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 328913#L756 assume !false; 328911#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 328909#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 328900#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 328899#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 328897#L653 assume !(0 != eval_~tmp~0#1); 328898#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 338422#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 338420#L781-3 assume 0 == ~M_E~0;~M_E~0 := 1; 331614#L781-5 assume !(0 == ~T1_E~0); 331613#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 331612#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 331611#L796-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 331610#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 331609#L806-3 assume !(0 == ~T6_E~0); 331608#L811-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 331607#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 331606#L821-3 assume !(0 == ~E_1~0); 331605#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 331604#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 331603#L836-3 assume 0 == ~E_4~0;~E_4~0 := 1; 331602#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 331601#L846-3 assume !(0 == ~E_6~0); 331600#L851-3 assume 0 == ~E_7~0;~E_7~0 := 1; 331599#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 331597#L388-27 assume !(1 == ~m_pc~0); 331595#L388-29 is_master_triggered_~__retres1~0#1 := 0; 331593#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 331591#is_master_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 331588#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 331586#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 331584#L407-27 assume !(1 == ~t1_pc~0); 331582#L407-29 is_transmit1_triggered_~__retres1~1#1 := 0; 331580#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 331578#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 331575#L975-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 331573#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 331571#L426-27 assume 1 == ~t2_pc~0; 331569#L427-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 331566#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 331564#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 331563#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 331561#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 331559#L445-27 assume !(1 == ~t3_pc~0); 331557#L445-29 is_transmit3_triggered_~__retres1~3#1 := 0; 331555#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 331553#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 331550#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 331548#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 331546#L464-27 assume !(1 == ~t4_pc~0); 331543#L464-29 is_transmit4_triggered_~__retres1~4#1 := 0; 331541#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 331539#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 331538#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 331537#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 331535#L483-27 assume !(1 == ~t5_pc~0); 331533#L483-29 is_transmit5_triggered_~__retres1~5#1 := 0; 331531#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 331529#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 331528#L1007-27 assume !(0 != activate_threads_~tmp___4~0#1); 331526#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 331524#L502-27 assume !(1 == ~t6_pc~0); 331522#L502-29 is_transmit6_triggered_~__retres1~6#1 := 0; 331520#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 331518#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 331118#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 329220#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 329211#L521-27 assume 1 == ~t7_pc~0; 329209#L522-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 329206#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 329203#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 329202#L1023-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 329200#L1023-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 329198#L869-3 assume 1 == ~M_E~0;~M_E~0 := 2; 280949#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 329193#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 329191#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 329189#L884-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 329187#L889-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 329185#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 329181#L899-3 assume !(1 == ~T7_E~0); 329179#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 329177#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 329175#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 329173#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 329170#L924-3 assume 1 == ~E_4~0;~E_4~0 := 2; 329168#L929-3 assume 1 == ~E_5~0;~E_5~0 := 2; 329166#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 296610#L939-3 assume !(1 == ~E_7~0); 329163#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 329155#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 329148#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 329146#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 329067#L1209 assume !(0 == start_simulation_~tmp~3#1); 329065#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 329057#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 329050#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 329048#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 329046#L1164 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 329043#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 329041#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 329039#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 329036#L1190-2 [2022-12-13 11:54:29,493 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 11:54:29,493 INFO L85 PathProgramCache]: Analyzing trace with hash 1196032317, now seen corresponding path program 1 times [2022-12-13 11:54:29,493 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 11:54:29,494 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1161631392] [2022-12-13 11:54:29,494 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 11:54:29,494 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 11:54:29,504 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 11:54:29,540 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 11:54:29,540 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 11:54:29,540 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1161631392] [2022-12-13 11:54:29,541 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1161631392] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 11:54:29,541 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 11:54:29,541 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-12-13 11:54:29,541 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2143261839] [2022-12-13 11:54:29,541 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 11:54:29,541 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 11:54:29,542 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 11:54:29,542 INFO L85 PathProgramCache]: Analyzing trace with hash 1972135520, now seen corresponding path program 1 times [2022-12-13 11:54:29,542 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 11:54:29,542 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1455992581] [2022-12-13 11:54:29,542 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 11:54:29,542 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 11:54:29,554 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 11:54:29,580 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 11:54:29,580 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 11:54:29,580 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1455992581] [2022-12-13 11:54:29,580 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1455992581] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 11:54:29,580 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 11:54:29,580 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 11:54:29,580 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1779508138] [2022-12-13 11:54:29,580 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 11:54:29,581 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 11:54:29,581 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 11:54:29,581 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-12-13 11:54:29,581 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-12-13 11:54:29,581 INFO L87 Difference]: Start difference. First operand 95959 states and 137792 transitions. cyclomatic complexity: 41897 Second operand has 5 states, 5 states have (on average 19.0) internal successors, (95), 5 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 11:54:30,382 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 11:54:30,383 INFO L93 Difference]: Finished difference Result 218779 states and 317880 transitions. [2022-12-13 11:54:30,383 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 218779 states and 317880 transitions. [2022-12-13 11:54:31,149 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 217126 [2022-12-13 11:54:31,546 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 218779 states to 218779 states and 317880 transitions. [2022-12-13 11:54:31,546 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 218779 [2022-12-13 11:54:31,632 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 218779 [2022-12-13 11:54:31,632 INFO L73 IsDeterministic]: Start isDeterministic. Operand 218779 states and 317880 transitions. [2022-12-13 11:54:31,817 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 11:54:31,818 INFO L218 hiAutomatonCegarLoop]: Abstraction has 218779 states and 317880 transitions. [2022-12-13 11:54:31,906 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 218779 states and 317880 transitions. [2022-12-13 11:54:32,996 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 218779 to 99718. [2022-12-13 11:54:33,063 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 99718 states, 99718 states have (on average 1.4195130267353937) internal successors, (141551), 99717 states have internal predecessors, (141551), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 11:54:33,310 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 99718 states to 99718 states and 141551 transitions. [2022-12-13 11:54:33,310 INFO L240 hiAutomatonCegarLoop]: Abstraction has 99718 states and 141551 transitions. [2022-12-13 11:54:33,310 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-12-13 11:54:33,311 INFO L428 stractBuchiCegarLoop]: Abstraction has 99718 states and 141551 transitions. [2022-12-13 11:54:33,311 INFO L335 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2022-12-13 11:54:33,311 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 99718 states and 141551 transitions. [2022-12-13 11:54:33,523 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 99093 [2022-12-13 11:54:33,523 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 11:54:33,523 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 11:54:33,525 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 11:54:33,525 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 11:54:33,525 INFO L748 eck$LassoCheckResult]: Stem: 560368#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 560369#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 561037#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 561038#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 561140#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 560513#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 560514#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 560647#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 560648#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 560414#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 560206#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 560207#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 560376#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 560377#L781 assume !(0 == ~M_E~0); 560922#L781-2 assume !(0 == ~T1_E~0); 561162#L786-1 assume !(0 == ~T2_E~0); 560167#L791-1 assume !(0 == ~T3_E~0); 560168#L796-1 assume !(0 == ~T4_E~0); 560733#L801-1 assume !(0 == ~T5_E~0); 560734#L806-1 assume !(0 == ~T6_E~0); 560774#L811-1 assume !(0 == ~T7_E~0); 560380#L816-1 assume !(0 == ~E_M~0); 560381#L821-1 assume !(0 == ~E_1~0); 560198#L826-1 assume !(0 == ~E_2~0); 560199#L831-1 assume !(0 == ~E_3~0); 560508#L836-1 assume !(0 == ~E_4~0); 560509#L841-1 assume !(0 == ~E_5~0); 560335#L846-1 assume !(0 == ~E_6~0); 560336#L851-1 assume !(0 == ~E_7~0); 560358#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 560359#L388 assume !(1 == ~m_pc~0); 560352#L388-2 is_master_triggered_~__retres1~0#1 := 0; 560353#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 560897#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 560212#L967 assume !(0 != activate_threads_~tmp~1#1); 560213#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 560146#L407 assume !(1 == ~t1_pc~0); 560147#L407-2 is_transmit1_triggered_~__retres1~1#1 := 0; 560153#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 560154#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 560184#L975 assume !(0 != activate_threads_~tmp___0~0#1); 561031#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 560463#L426 assume !(1 == ~t2_pc~0); 560464#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 561066#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 560488#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 560489#L983 assume !(0 != activate_threads_~tmp___1~0#1); 561118#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 560555#L445 assume !(1 == ~t3_pc~0); 560556#L445-2 is_transmit3_triggered_~__retres1~3#1 := 0; 560931#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 560144#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 560145#L991 assume !(0 != activate_threads_~tmp___2~0#1); 560848#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 560805#L464 assume !(1 == ~t4_pc~0); 560362#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 560232#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 560233#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 560244#L999 assume !(0 != activate_threads_~tmp___3~0#1); 560533#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 560534#L483 assume !(1 == ~t5_pc~0); 560802#L483-2 is_transmit5_triggered_~__retres1~5#1 := 0; 561010#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 560958#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 560959#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 560448#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 560449#L502 assume !(1 == ~t6_pc~0); 560311#L502-2 is_transmit6_triggered_~__retres1~6#1 := 0; 560272#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 560273#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 560472#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 560691#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 560977#L521 assume !(1 == ~t7_pc~0); 561028#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 560208#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 560209#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 561021#L1023 assume !(0 != activate_threads_~tmp___6~0#1); 560990#L1023-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 560882#L869 assume 1 == ~M_E~0;~M_E~0 := 2; 560883#L869-2 assume !(1 == ~T1_E~0); 561114#L874-1 assume !(1 == ~T2_E~0); 561115#L879-1 assume !(1 == ~T3_E~0); 560603#L884-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 560604#L889-1 assume !(1 == ~T5_E~0); 560391#L894-1 assume !(1 == ~T6_E~0); 560392#L899-1 assume !(1 == ~T7_E~0); 561169#L904-1 assume !(1 == ~E_M~0); 560550#L909-1 assume !(1 == ~E_1~0); 560551#L914-1 assume !(1 == ~E_2~0); 560784#L919-1 assume !(1 == ~E_3~0); 560462#L924-1 assume 1 == ~E_4~0;~E_4~0 := 2; 560304#L929-1 assume !(1 == ~E_5~0); 560305#L934-1 assume !(1 == ~E_6~0); 560529#L939-1 assume !(1 == ~E_7~0); 560530#L944-1 assume { :end_inline_reset_delta_events } true; 560976#L1190-2 [2022-12-13 11:54:33,525 INFO L750 eck$LassoCheckResult]: Loop: 560976#L1190-2 assume !false; 625345#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 625256#L756 assume !false; 625249#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 625230#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 625221#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 625209#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 625150#L653 assume !(0 != eval_~tmp~0#1); 625151#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 626008#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 626007#L781-3 assume 0 == ~M_E~0;~M_E~0 := 1; 626006#L781-5 assume !(0 == ~T1_E~0); 626005#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 626004#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 626003#L796-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 626002#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 626001#L806-3 assume !(0 == ~T6_E~0); 626000#L811-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 625999#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 625998#L821-3 assume !(0 == ~E_1~0); 625997#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 625996#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 625995#L836-3 assume 0 == ~E_4~0;~E_4~0 := 1; 625994#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 625993#L846-3 assume !(0 == ~E_6~0); 625992#L851-3 assume 0 == ~E_7~0;~E_7~0 := 1; 625991#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 625990#L388-27 assume !(1 == ~m_pc~0); 625989#L388-29 is_master_triggered_~__retres1~0#1 := 0; 625988#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 625987#is_master_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 625986#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 625985#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 625984#L407-27 assume !(1 == ~t1_pc~0); 625983#L407-29 is_transmit1_triggered_~__retres1~1#1 := 0; 625982#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 625981#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 625980#L975-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 625979#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 625978#L426-27 assume 1 == ~t2_pc~0; 625977#L427-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 625975#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 625974#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 625973#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 625972#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 625971#L445-27 assume !(1 == ~t3_pc~0); 625970#L445-29 is_transmit3_triggered_~__retres1~3#1 := 0; 625969#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 625968#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 625967#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 625966#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 625965#L464-27 assume !(1 == ~t4_pc~0); 625963#L464-29 is_transmit4_triggered_~__retres1~4#1 := 0; 625962#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 625961#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 625960#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 625959#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 625958#L483-27 assume !(1 == ~t5_pc~0); 625957#L483-29 is_transmit5_triggered_~__retres1~5#1 := 0; 625956#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 625955#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 625954#L1007-27 assume !(0 != activate_threads_~tmp___4~0#1); 625953#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 625952#L502-27 assume !(1 == ~t6_pc~0); 625951#L502-29 is_transmit6_triggered_~__retres1~6#1 := 0; 625950#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 625949#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 625948#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 625947#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 625946#L521-27 assume !(1 == ~t7_pc~0); 625945#L521-29 is_transmit7_triggered_~__retres1~7#1 := 0; 625943#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 625941#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 625939#L1023-27 assume !(0 != activate_threads_~tmp___6~0#1); 625937#L1023-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 625936#L869-3 assume 1 == ~M_E~0;~M_E~0 := 2; 613283#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 625882#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 625880#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 625878#L884-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 625876#L889-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 625874#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 621925#L899-3 assume !(1 == ~T7_E~0); 625824#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 625821#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 625818#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 625815#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 625812#L924-3 assume 1 == ~E_4~0;~E_4~0 := 2; 625809#L929-3 assume 1 == ~E_5~0;~E_5~0 := 2; 625806#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 624833#L939-3 assume !(1 == ~E_7~0); 625748#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 625691#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 625679#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 625666#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 625577#L1209 assume !(0 == start_simulation_~tmp~3#1); 625572#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 625515#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 625416#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 625361#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 625359#L1164 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 625358#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 625357#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 625353#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 560976#L1190-2 [2022-12-13 11:54:33,525 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 11:54:33,526 INFO L85 PathProgramCache]: Analyzing trace with hash -492911425, now seen corresponding path program 1 times [2022-12-13 11:54:33,526 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 11:54:33,526 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [227191447] [2022-12-13 11:54:33,526 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 11:54:33,526 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 11:54:33,535 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 11:54:33,570 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 11:54:33,571 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 11:54:33,571 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [227191447] [2022-12-13 11:54:33,571 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [227191447] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 11:54:33,571 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 11:54:33,571 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-12-13 11:54:33,571 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1787078044] [2022-12-13 11:54:33,571 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 11:54:33,572 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 11:54:33,572 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 11:54:33,572 INFO L85 PathProgramCache]: Analyzing trace with hash -569782813, now seen corresponding path program 1 times [2022-12-13 11:54:33,572 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 11:54:33,572 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1805620535] [2022-12-13 11:54:33,572 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 11:54:33,572 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 11:54:33,583 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 11:54:33,603 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 11:54:33,604 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 11:54:33,604 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1805620535] [2022-12-13 11:54:33,604 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1805620535] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 11:54:33,604 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 11:54:33,604 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 11:54:33,604 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2007616422] [2022-12-13 11:54:33,604 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 11:54:33,604 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 11:54:33,605 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 11:54:33,605 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 11:54:33,605 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 11:54:33,605 INFO L87 Difference]: Start difference. First operand 99718 states and 141551 transitions. cyclomatic complexity: 41897 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 2 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 11:54:33,996 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 11:54:33,996 INFO L93 Difference]: Finished difference Result 125256 states and 177893 transitions. [2022-12-13 11:54:33,996 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 125256 states and 177893 transitions. [2022-12-13 11:54:34,376 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 124521 [2022-12-13 11:54:34,611 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 125256 states to 125256 states and 177893 transitions. [2022-12-13 11:54:34,612 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 125256 [2022-12-13 11:54:34,666 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 125256 [2022-12-13 11:54:34,666 INFO L73 IsDeterministic]: Start isDeterministic. Operand 125256 states and 177893 transitions. [2022-12-13 11:54:34,711 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 11:54:34,711 INFO L218 hiAutomatonCegarLoop]: Abstraction has 125256 states and 177893 transitions. [2022-12-13 11:54:34,761 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 125256 states and 177893 transitions. [2022-12-13 11:54:35,328 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 125256 to 54326. [2022-12-13 11:54:35,362 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 54326 states, 54326 states have (on average 1.42552369031403) internal successors, (77443), 54325 states have internal predecessors, (77443), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 11:54:35,437 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 54326 states to 54326 states and 77443 transitions. [2022-12-13 11:54:35,437 INFO L240 hiAutomatonCegarLoop]: Abstraction has 54326 states and 77443 transitions. [2022-12-13 11:54:35,438 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 11:54:35,438 INFO L428 stractBuchiCegarLoop]: Abstraction has 54326 states and 77443 transitions. [2022-12-13 11:54:35,438 INFO L335 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2022-12-13 11:54:35,438 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 54326 states and 77443 transitions. [2022-12-13 11:54:35,573 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 53977 [2022-12-13 11:54:35,573 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 11:54:35,573 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 11:54:35,574 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 11:54:35,574 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 11:54:35,574 INFO L748 eck$LassoCheckResult]: Stem: 785348#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 785349#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 785985#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 785986#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 786081#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 785488#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 785489#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 785619#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 785620#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 785392#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 785187#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 785188#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 785353#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 785354#L781 assume !(0 == ~M_E~0); 785884#L781-2 assume !(0 == ~T1_E~0); 786103#L786-1 assume !(0 == ~T2_E~0); 785148#L791-1 assume !(0 == ~T3_E~0); 785149#L796-1 assume !(0 == ~T4_E~0); 785702#L801-1 assume !(0 == ~T5_E~0); 785703#L806-1 assume !(0 == ~T6_E~0); 785738#L811-1 assume !(0 == ~T7_E~0); 785360#L816-1 assume !(0 == ~E_M~0); 785361#L821-1 assume !(0 == ~E_1~0); 785179#L826-1 assume !(0 == ~E_2~0); 785180#L831-1 assume !(0 == ~E_3~0); 785483#L836-1 assume !(0 == ~E_4~0); 785484#L841-1 assume !(0 == ~E_5~0); 785314#L846-1 assume !(0 == ~E_6~0); 785315#L851-1 assume !(0 == ~E_7~0); 785338#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 785339#L388 assume !(1 == ~m_pc~0); 785332#L388-2 is_master_triggered_~__retres1~0#1 := 0; 785333#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 785853#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 785193#L967 assume !(0 != activate_threads_~tmp~1#1); 785194#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 785127#L407 assume !(1 == ~t1_pc~0); 785128#L407-2 is_transmit1_triggered_~__retres1~1#1 := 0; 785131#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 785132#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 785165#L975 assume !(0 != activate_threads_~tmp___0~0#1); 785979#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 785441#L426 assume !(1 == ~t2_pc~0); 785442#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 786010#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 785465#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 785466#L983 assume !(0 != activate_threads_~tmp___1~0#1); 786063#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 785530#L445 assume !(1 == ~t3_pc~0); 785531#L445-2 is_transmit3_triggered_~__retres1~3#1 := 0; 785891#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 785125#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 785126#L991 assume !(0 != activate_threads_~tmp___2~0#1); 785806#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 785768#L464 assume !(1 == ~t4_pc~0); 785342#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 785213#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 785214#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 785225#L999 assume !(0 != activate_threads_~tmp___3~0#1); 785510#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 785511#L483 assume !(1 == ~t5_pc~0); 785765#L483-2 is_transmit5_triggered_~__retres1~5#1 := 0; 785959#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 785917#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 785918#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 785425#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 785426#L502 assume !(1 == ~t6_pc~0); 785292#L502-2 is_transmit6_triggered_~__retres1~6#1 := 0; 785253#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 785254#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 785450#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 785660#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 785932#L521 assume !(1 == ~t7_pc~0); 785976#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 785189#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 785190#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 785969#L1023 assume !(0 != activate_threads_~tmp___6~0#1); 785938#L1023-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 785841#L869 assume !(1 == ~M_E~0); 785503#L869-2 assume !(1 == ~T1_E~0); 785504#L874-1 assume !(1 == ~T2_E~0); 786026#L879-1 assume !(1 == ~T3_E~0); 785577#L884-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 785113#L889-1 assume !(1 == ~T5_E~0); 785114#L894-1 assume !(1 == ~T6_E~0); 785367#L899-1 assume !(1 == ~T7_E~0); 785793#L904-1 assume !(1 == ~E_M~0); 785525#L909-1 assume !(1 == ~E_1~0); 785526#L914-1 assume !(1 == ~E_2~0); 785720#L919-1 assume !(1 == ~E_3~0); 785440#L924-1 assume 1 == ~E_4~0;~E_4~0 := 2; 785285#L929-1 assume !(1 == ~E_5~0); 785286#L934-1 assume !(1 == ~E_6~0); 785506#L939-1 assume !(1 == ~E_7~0); 785507#L944-1 assume { :end_inline_reset_delta_events } true; 785931#L1190-2 [2022-12-13 11:54:35,575 INFO L750 eck$LassoCheckResult]: Loop: 785931#L1190-2 assume !false; 824040#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 824038#L756 assume !false; 823952#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 823649#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 823640#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 823638#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 823636#L653 assume !(0 != eval_~tmp~0#1); 823637#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 839389#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 839387#L781-3 assume !(0 == ~M_E~0); 839385#L781-5 assume !(0 == ~T1_E~0); 839383#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 839381#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 839380#L796-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 839378#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 839376#L806-3 assume !(0 == ~T6_E~0); 839374#L811-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 839372#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 839370#L821-3 assume !(0 == ~E_1~0); 839367#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 839366#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 839365#L836-3 assume 0 == ~E_4~0;~E_4~0 := 1; 839363#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 839347#L846-3 assume !(0 == ~E_6~0); 839344#L851-3 assume 0 == ~E_7~0;~E_7~0 := 1; 839340#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 839337#L388-27 assume !(1 == ~m_pc~0); 839334#L388-29 is_master_triggered_~__retres1~0#1 := 0; 839331#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 839330#is_master_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 839319#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 785395#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 785396#L407-27 assume !(1 == ~t1_pc~0); 785832#L407-29 is_transmit1_triggered_~__retres1~1#1 := 0; 785912#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 785712#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 785713#L975-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 838502#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 838501#L426-27 assume 1 == ~t2_pc~0; 838500#L427-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 838498#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 838496#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 838105#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 838104#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 837512#L445-27 assume !(1 == ~t3_pc~0); 837478#L445-29 is_transmit3_triggered_~__retres1~3#1 := 0; 837316#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 837311#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 837309#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 837307#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 837298#L464-27 assume !(1 == ~t4_pc~0); 837295#L464-29 is_transmit4_triggered_~__retres1~4#1 := 0; 837293#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 837290#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 837285#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 837283#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 837281#L483-27 assume !(1 == ~t5_pc~0); 837279#L483-29 is_transmit5_triggered_~__retres1~5#1 := 0; 837277#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 837275#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 837273#L1007-27 assume !(0 != activate_threads_~tmp___4~0#1); 837270#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 837268#L502-27 assume !(1 == ~t6_pc~0); 837266#L502-29 is_transmit6_triggered_~__retres1~6#1 := 0; 837264#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 837262#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 837260#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 837173#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 837170#L521-27 assume 1 == ~t7_pc~0; 837166#L522-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 837162#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 837158#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 837153#L1023-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 837148#L1023-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 837143#L869-3 assume !(1 == ~M_E~0); 802472#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 837132#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 837125#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 837119#L884-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 837113#L889-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 837105#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 837098#L899-3 assume !(1 == ~T7_E~0); 837089#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 837083#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 837075#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 837065#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 837058#L924-3 assume 1 == ~E_4~0;~E_4~0 := 2; 836999#L929-3 assume 1 == ~E_5~0;~E_5~0 := 2; 836991#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 836984#L939-3 assume !(1 == ~E_7~0); 836980#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 836907#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 836899#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 815149#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 802534#L1209 assume !(0 == start_simulation_~tmp~3#1); 802535#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 824229#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 824222#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 824221#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 824220#L1164 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 824218#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 824216#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 824214#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 785931#L1190-2 [2022-12-13 11:54:35,575 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 11:54:35,575 INFO L85 PathProgramCache]: Analyzing trace with hash -2081259327, now seen corresponding path program 1 times [2022-12-13 11:54:35,575 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 11:54:35,575 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [217372185] [2022-12-13 11:54:35,575 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 11:54:35,575 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 11:54:35,584 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 11:54:35,617 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 11:54:35,617 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 11:54:35,617 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [217372185] [2022-12-13 11:54:35,617 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [217372185] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 11:54:35,618 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 11:54:35,618 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 11:54:35,618 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [87433877] [2022-12-13 11:54:35,618 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 11:54:35,618 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 11:54:35,618 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 11:54:35,618 INFO L85 PathProgramCache]: Analyzing trace with hash 1739364000, now seen corresponding path program 1 times [2022-12-13 11:54:35,618 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 11:54:35,618 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1936424869] [2022-12-13 11:54:35,618 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 11:54:35,619 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 11:54:35,625 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 11:54:35,642 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 11:54:35,642 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 11:54:35,642 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1936424869] [2022-12-13 11:54:35,642 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1936424869] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 11:54:35,642 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 11:54:35,642 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 11:54:35,642 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2079270577] [2022-12-13 11:54:35,642 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 11:54:35,643 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 11:54:35,643 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 11:54:35,643 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 11:54:35,643 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 11:54:35,643 INFO L87 Difference]: Start difference. First operand 54326 states and 77443 transitions. cyclomatic complexity: 23133 Second operand has 4 states, 4 states have (on average 23.75) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 11:54:35,873 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 11:54:35,873 INFO L93 Difference]: Finished difference Result 86959 states and 123372 transitions. [2022-12-13 11:54:35,873 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 86959 states and 123372 transitions. [2022-12-13 11:54:36,339 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 86403 [2022-12-13 11:54:36,516 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 86959 states to 86959 states and 123372 transitions. [2022-12-13 11:54:36,517 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 86959 [2022-12-13 11:54:36,552 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 86959 [2022-12-13 11:54:36,552 INFO L73 IsDeterministic]: Start isDeterministic. Operand 86959 states and 123372 transitions. [2022-12-13 11:54:36,590 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 11:54:36,590 INFO L218 hiAutomatonCegarLoop]: Abstraction has 86959 states and 123372 transitions. [2022-12-13 11:54:36,626 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 86959 states and 123372 transitions. [2022-12-13 11:54:37,203 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 86959 to 62259. [2022-12-13 11:54:37,241 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 62259 states, 62259 states have (on average 1.4221879567612714) internal successors, (88544), 62258 states have internal predecessors, (88544), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 11:54:37,324 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 62259 states to 62259 states and 88544 transitions. [2022-12-13 11:54:37,324 INFO L240 hiAutomatonCegarLoop]: Abstraction has 62259 states and 88544 transitions. [2022-12-13 11:54:37,325 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 11:54:37,325 INFO L428 stractBuchiCegarLoop]: Abstraction has 62259 states and 88544 transitions. [2022-12-13 11:54:37,325 INFO L335 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2022-12-13 11:54:37,325 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 62259 states and 88544 transitions. [2022-12-13 11:54:37,476 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 61839 [2022-12-13 11:54:37,476 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 11:54:37,476 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 11:54:37,477 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 11:54:37,477 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 11:54:37,478 INFO L748 eck$LassoCheckResult]: Stem: 926645#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 926646#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 927286#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 927287#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 927403#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 926790#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 926791#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 926920#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 926921#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 926691#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 926483#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 926484#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 926650#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 926651#L781 assume !(0 == ~M_E~0); 927181#L781-2 assume !(0 == ~T1_E~0); 927421#L786-1 assume !(0 == ~T2_E~0); 926443#L791-1 assume !(0 == ~T3_E~0); 926444#L796-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 927040#L801-1 assume !(0 == ~T5_E~0); 927042#L806-1 assume !(0 == ~T6_E~0); 927043#L811-1 assume !(0 == ~T7_E~0); 927460#L816-1 assume !(0 == ~E_M~0); 927289#L821-1 assume !(0 == ~E_1~0); 927290#L826-1 assume !(0 == ~E_2~0); 927003#L831-1 assume !(0 == ~E_3~0); 926785#L836-1 assume !(0 == ~E_4~0); 926786#L841-1 assume !(0 == ~E_5~0); 926610#L846-1 assume !(0 == ~E_6~0); 926611#L851-1 assume !(0 == ~E_7~0); 927456#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 927310#L388 assume !(1 == ~m_pc~0); 926628#L388-2 is_master_triggered_~__retres1~0#1 := 0; 926629#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 927154#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 926489#L967 assume !(0 != activate_threads_~tmp~1#1); 926490#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 926422#L407 assume !(1 == ~t1_pc~0); 926423#L407-2 is_transmit1_triggered_~__retres1~1#1 := 0; 927453#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 927452#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 927279#L975 assume !(0 != activate_threads_~tmp___0~0#1); 927280#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 926739#L426 assume !(1 == ~t2_pc~0); 926740#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 927385#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 927386#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 927381#L983 assume !(0 != activate_threads_~tmp___1~0#1); 927382#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 926834#L445 assume !(1 == ~t3_pc~0); 926835#L445-2 is_transmit3_triggered_~__retres1~3#1 := 0; 927449#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 926420#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 926421#L991 assume !(0 != activate_threads_~tmp___2~0#1); 927111#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 927186#L464 assume !(1 == ~t4_pc~0); 927445#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 926509#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 926510#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 926521#L999 assume !(0 != activate_threads_~tmp___3~0#1); 926814#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 926815#L483 assume !(1 == ~t5_pc~0); 927070#L483-2 is_transmit5_triggered_~__retres1~5#1 := 0; 927256#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 927257#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 927349#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 927350#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 927440#L502 assume !(1 == ~t6_pc~0); 926588#L502-2 is_transmit6_triggered_~__retres1~6#1 := 0; 926589#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 926748#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 926749#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 927233#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 927234#L521 assume !(1 == ~t7_pc~0); 927276#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 926485#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 926486#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 927433#L1023 assume !(0 != activate_threads_~tmp___6~0#1); 927241#L1023-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 927144#L869 assume !(1 == ~M_E~0); 926808#L869-2 assume !(1 == ~T1_E~0); 926809#L874-1 assume !(1 == ~T2_E~0); 927335#L879-1 assume !(1 == ~T3_E~0); 927336#L884-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 926408#L889-1 assume !(1 == ~T5_E~0); 926409#L894-1 assume !(1 == ~T6_E~0); 926668#L899-1 assume !(1 == ~T7_E~0); 927099#L904-1 assume !(1 == ~E_M~0); 926829#L909-1 assume !(1 == ~E_1~0); 926830#L914-1 assume !(1 == ~E_2~0); 927026#L919-1 assume !(1 == ~E_3~0); 926738#L924-1 assume 1 == ~E_4~0;~E_4~0 := 2; 926581#L929-1 assume !(1 == ~E_5~0); 926582#L934-1 assume !(1 == ~E_6~0); 926812#L939-1 assume !(1 == ~E_7~0); 926813#L944-1 assume { :end_inline_reset_delta_events } true; 927232#L1190-2 [2022-12-13 11:54:37,478 INFO L750 eck$LassoCheckResult]: Loop: 927232#L1190-2 assume !false; 944253#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 944251#L756 assume !false; 944249#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 944247#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 944238#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 944236#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 944233#L653 assume !(0 != eval_~tmp~0#1); 944231#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 944229#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 944227#L781-3 assume !(0 == ~M_E~0); 944225#L781-5 assume !(0 == ~T1_E~0); 944223#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 944221#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 944217#L796-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 944218#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 945074#L806-3 assume !(0 == ~T6_E~0); 945072#L811-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 945070#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 945068#L821-3 assume !(0 == ~E_1~0); 945066#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 945064#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 945062#L836-3 assume 0 == ~E_4~0;~E_4~0 := 1; 945060#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 944271#L846-3 assume !(0 == ~E_6~0); 944266#L851-3 assume 0 == ~E_7~0;~E_7~0 := 1; 944262#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 944258#L388-27 assume !(1 == ~m_pc~0); 944252#L388-29 is_master_triggered_~__retres1~0#1 := 0; 944250#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 944248#is_master_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 944239#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 944237#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 944235#L407-27 assume !(1 == ~t1_pc~0); 944232#L407-29 is_transmit1_triggered_~__retres1~1#1 := 0; 944230#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 944228#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 944226#L975-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 944224#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 944222#L426-27 assume 1 == ~t2_pc~0; 944220#L427-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 944216#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 944214#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 944212#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 944210#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 944208#L445-27 assume !(1 == ~t3_pc~0); 944206#L445-29 is_transmit3_triggered_~__retres1~3#1 := 0; 944204#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 944202#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 944200#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 944198#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 944196#L464-27 assume 1 == ~t4_pc~0; 944194#L465-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 944191#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 944189#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 944187#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 944185#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 944183#L483-27 assume !(1 == ~t5_pc~0); 944181#L483-29 is_transmit5_triggered_~__retres1~5#1 := 0; 944179#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 944177#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 944175#L1007-27 assume !(0 != activate_threads_~tmp___4~0#1); 944173#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 944171#L502-27 assume !(1 == ~t6_pc~0); 944169#L502-29 is_transmit6_triggered_~__retres1~6#1 := 0; 944167#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 944165#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 944162#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 944160#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 944158#L521-27 assume 1 == ~t7_pc~0; 944156#L522-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 944157#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 944626#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 944147#L1023-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 944145#L1023-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 944143#L869-3 assume !(1 == ~M_E~0); 943893#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 944140#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 944138#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 944083#L884-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 944081#L889-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 944079#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 944077#L899-3 assume !(1 == ~T7_E~0); 944074#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 944072#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 944070#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 944068#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 944066#L924-3 assume 1 == ~E_4~0;~E_4~0 := 2; 944064#L929-3 assume 1 == ~E_5~0;~E_5~0 := 2; 944061#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 944059#L939-3 assume !(1 == ~E_7~0); 944057#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 944049#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 944042#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 944040#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 943872#L1209 assume !(0 == start_simulation_~tmp~3#1); 943873#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 951186#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 951179#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 951177#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 951175#L1164 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 951173#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 951171#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 951169#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 927232#L1190-2 [2022-12-13 11:54:37,478 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 11:54:37,478 INFO L85 PathProgramCache]: Analyzing trace with hash 1374674307, now seen corresponding path program 1 times [2022-12-13 11:54:37,478 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 11:54:37,478 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1012121668] [2022-12-13 11:54:37,478 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 11:54:37,479 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 11:54:37,485 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 11:54:37,514 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 11:54:37,515 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 11:54:37,515 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1012121668] [2022-12-13 11:54:37,515 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1012121668] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 11:54:37,515 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 11:54:37,515 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 11:54:37,515 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1299837616] [2022-12-13 11:54:37,515 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 11:54:37,516 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 11:54:37,516 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 11:54:37,516 INFO L85 PathProgramCache]: Analyzing trace with hash 2013142495, now seen corresponding path program 1 times [2022-12-13 11:54:37,516 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 11:54:37,516 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [786700010] [2022-12-13 11:54:37,517 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 11:54:37,517 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 11:54:37,528 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 11:54:37,552 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 11:54:37,552 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 11:54:37,552 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [786700010] [2022-12-13 11:54:37,552 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [786700010] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 11:54:37,552 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 11:54:37,552 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 11:54:37,552 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [226731762] [2022-12-13 11:54:37,552 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 11:54:37,553 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 11:54:37,553 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 11:54:37,553 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 11:54:37,553 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 11:54:37,553 INFO L87 Difference]: Start difference. First operand 62259 states and 88544 transitions. cyclomatic complexity: 26301 Second operand has 4 states, 4 states have (on average 23.75) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 11:54:37,785 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 11:54:37,785 INFO L93 Difference]: Finished difference Result 79014 states and 111868 transitions. [2022-12-13 11:54:37,785 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 79014 states and 111868 transitions. [2022-12-13 11:54:38,062 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 78541 [2022-12-13 11:54:38,355 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 79014 states to 79014 states and 111868 transitions. [2022-12-13 11:54:38,355 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 79014 [2022-12-13 11:54:38,378 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 79014 [2022-12-13 11:54:38,378 INFO L73 IsDeterministic]: Start isDeterministic. Operand 79014 states and 111868 transitions. [2022-12-13 11:54:38,400 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 11:54:38,401 INFO L218 hiAutomatonCegarLoop]: Abstraction has 79014 states and 111868 transitions. [2022-12-13 11:54:38,424 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 79014 states and 111868 transitions. [2022-12-13 11:54:38,785 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 79014 to 54326. [2022-12-13 11:54:38,818 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 54326 states, 54326 states have (on average 1.419522880388764) internal successors, (77117), 54325 states have internal predecessors, (77117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 11:54:39,010 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 54326 states to 54326 states and 77117 transitions. [2022-12-13 11:54:39,010 INFO L240 hiAutomatonCegarLoop]: Abstraction has 54326 states and 77117 transitions. [2022-12-13 11:54:39,011 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 11:54:39,011 INFO L428 stractBuchiCegarLoop]: Abstraction has 54326 states and 77117 transitions. [2022-12-13 11:54:39,011 INFO L335 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2022-12-13 11:54:39,011 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 54326 states and 77117 transitions. [2022-12-13 11:54:39,111 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 53977 [2022-12-13 11:54:39,111 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 11:54:39,111 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 11:54:39,112 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 11:54:39,112 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 11:54:39,112 INFO L748 eck$LassoCheckResult]: Stem: 1067926#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 1067927#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 1068574#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1068575#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1068681#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 1068066#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1068067#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1068195#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1068196#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1067972#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1067765#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1067766#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1067931#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1067932#L781 assume !(0 == ~M_E~0); 1068467#L781-2 assume !(0 == ~T1_E~0); 1068710#L786-1 assume !(0 == ~T2_E~0); 1067726#L791-1 assume !(0 == ~T3_E~0); 1067727#L796-1 assume !(0 == ~T4_E~0); 1068280#L801-1 assume !(0 == ~T5_E~0); 1068281#L806-1 assume !(0 == ~T6_E~0); 1068319#L811-1 assume !(0 == ~T7_E~0); 1067938#L816-1 assume !(0 == ~E_M~0); 1067939#L821-1 assume !(0 == ~E_1~0); 1067757#L826-1 assume !(0 == ~E_2~0); 1067758#L831-1 assume !(0 == ~E_3~0); 1068061#L836-1 assume !(0 == ~E_4~0); 1068062#L841-1 assume !(0 == ~E_5~0); 1067892#L846-1 assume !(0 == ~E_6~0); 1067893#L851-1 assume !(0 == ~E_7~0); 1067916#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1067917#L388 assume !(1 == ~m_pc~0); 1067910#L388-2 is_master_triggered_~__retres1~0#1 := 0; 1067911#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1068436#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1067771#L967 assume !(0 != activate_threads_~tmp~1#1); 1067772#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1067705#L407 assume !(1 == ~t1_pc~0); 1067706#L407-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1067712#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1067713#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1067745#L975 assume !(0 != activate_threads_~tmp___0~0#1); 1068567#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1068021#L426 assume !(1 == ~t2_pc~0); 1068022#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1068605#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1068042#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1068043#L983 assume !(0 != activate_threads_~tmp___1~0#1); 1068661#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1068105#L445 assume !(1 == ~t3_pc~0); 1068106#L445-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1068476#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1067703#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1067704#L991 assume !(0 != activate_threads_~tmp___2~0#1); 1068387#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1068348#L464 assume !(1 == ~t4_pc~0); 1067920#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1067791#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1067792#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1067803#L999 assume !(0 != activate_threads_~tmp___3~0#1); 1068085#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1068086#L483 assume !(1 == ~t5_pc~0); 1068345#L483-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1068543#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1068499#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1068500#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 1068005#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1068006#L502 assume !(1 == ~t6_pc~0); 1067871#L502-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1067831#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1067832#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1068028#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 1068237#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1068516#L521 assume !(1 == ~t7_pc~0); 1068564#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1067767#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1067768#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1068557#L1023 assume !(0 != activate_threads_~tmp___6~0#1); 1068524#L1023-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1068426#L869 assume !(1 == ~M_E~0); 1068079#L869-2 assume !(1 == ~T1_E~0); 1068080#L874-1 assume !(1 == ~T2_E~0); 1068624#L879-1 assume !(1 == ~T3_E~0); 1068153#L884-1 assume !(1 == ~T4_E~0); 1067691#L889-1 assume !(1 == ~T5_E~0); 1067692#L894-1 assume !(1 == ~T6_E~0); 1067948#L899-1 assume !(1 == ~T7_E~0); 1068374#L904-1 assume !(1 == ~E_M~0); 1068100#L909-1 assume !(1 == ~E_1~0); 1068101#L914-1 assume !(1 == ~E_2~0); 1068303#L919-1 assume !(1 == ~E_3~0); 1068020#L924-1 assume 1 == ~E_4~0;~E_4~0 := 2; 1067863#L929-1 assume !(1 == ~E_5~0); 1067864#L934-1 assume !(1 == ~E_6~0); 1068083#L939-1 assume !(1 == ~E_7~0); 1068084#L944-1 assume { :end_inline_reset_delta_events } true; 1068515#L1190-2 [2022-12-13 11:54:39,112 INFO L750 eck$LassoCheckResult]: Loop: 1068515#L1190-2 assume !false; 1104633#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1104632#L756 assume !false; 1104631#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1104630#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1104621#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1104619#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1104616#L653 assume !(0 != eval_~tmp~0#1); 1104614#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1104612#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1104610#L781-3 assume !(0 == ~M_E~0); 1104608#L781-5 assume !(0 == ~T1_E~0); 1104605#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1104603#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1104601#L796-3 assume !(0 == ~T4_E~0); 1104599#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1104597#L806-3 assume !(0 == ~T6_E~0); 1104594#L811-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1104593#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1104590#L821-3 assume !(0 == ~E_1~0); 1104588#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1104586#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1104584#L836-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1104582#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1104580#L846-3 assume !(0 == ~E_6~0); 1104577#L851-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1104575#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1104573#L388-27 assume !(1 == ~m_pc~0); 1104571#L388-29 is_master_triggered_~__retres1~0#1 := 0; 1104569#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1104567#is_master_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1104565#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1104563#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1104561#L407-27 assume !(1 == ~t1_pc~0); 1104559#L407-29 is_transmit1_triggered_~__retres1~1#1 := 0; 1104557#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1104554#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1104553#L975-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1104550#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1104548#L426-27 assume !(1 == ~t2_pc~0); 1104545#L426-29 is_transmit2_triggered_~__retres1~2#1 := 0; 1104543#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1104541#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1104537#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1104535#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1104533#L445-27 assume !(1 == ~t3_pc~0); 1104531#L445-29 is_transmit3_triggered_~__retres1~3#1 := 0; 1104528#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1104526#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1104525#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1104524#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1102875#L464-27 assume !(1 == ~t4_pc~0); 1102872#L464-29 is_transmit4_triggered_~__retres1~4#1 := 0; 1102870#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1102868#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1102866#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1102864#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1102862#L483-27 assume !(1 == ~t5_pc~0); 1102858#L483-29 is_transmit5_triggered_~__retres1~5#1 := 0; 1102856#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1102854#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1102852#L1007-27 assume !(0 != activate_threads_~tmp___4~0#1); 1102849#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1102847#L502-27 assume !(1 == ~t6_pc~0); 1102845#L502-29 is_transmit6_triggered_~__retres1~6#1 := 0; 1102844#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1102843#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1102842#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1102841#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1102840#L521-27 assume !(1 == ~t7_pc~0); 1102838#L521-29 is_transmit7_triggered_~__retres1~7#1 := 0; 1102836#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1102834#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1102833#L1023-27 assume !(0 != activate_threads_~tmp___6~0#1); 1102831#L1023-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1102830#L869-3 assume !(1 == ~M_E~0); 1081268#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1102829#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1102828#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1102827#L884-3 assume !(1 == ~T4_E~0); 1102826#L889-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1102825#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1102823#L899-3 assume !(1 == ~T7_E~0); 1102822#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1102821#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1102820#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1102819#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1102818#L924-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1102809#L929-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1102807#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1102805#L939-3 assume !(1 == ~E_7~0); 1102803#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1102790#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1102212#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1102196#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 1100062#L1209 assume !(0 == start_simulation_~tmp~3#1); 1100063#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1104832#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1104826#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1104825#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 1104824#L1164 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1104823#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1104822#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 1104821#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 1068515#L1190-2 [2022-12-13 11:54:39,112 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 11:54:39,113 INFO L85 PathProgramCache]: Analyzing trace with hash 1626901955, now seen corresponding path program 1 times [2022-12-13 11:54:39,113 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 11:54:39,113 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1473853191] [2022-12-13 11:54:39,113 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 11:54:39,113 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 11:54:39,121 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 11:54:39,154 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 11:54:39,154 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 11:54:39,154 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1473853191] [2022-12-13 11:54:39,154 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1473853191] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 11:54:39,155 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 11:54:39,155 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 11:54:39,155 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1917856265] [2022-12-13 11:54:39,155 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 11:54:39,155 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 11:54:39,155 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 11:54:39,156 INFO L85 PathProgramCache]: Analyzing trace with hash 1592700324, now seen corresponding path program 1 times [2022-12-13 11:54:39,156 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 11:54:39,156 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [705354987] [2022-12-13 11:54:39,156 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 11:54:39,156 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 11:54:39,165 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 11:54:39,185 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 11:54:39,185 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 11:54:39,185 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [705354987] [2022-12-13 11:54:39,186 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [705354987] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 11:54:39,186 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 11:54:39,186 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 11:54:39,186 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [23214136] [2022-12-13 11:54:39,186 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 11:54:39,186 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 11:54:39,186 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 11:54:39,187 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 11:54:39,187 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 11:54:39,187 INFO L87 Difference]: Start difference. First operand 54326 states and 77117 transitions. cyclomatic complexity: 22807 Second operand has 4 states, 4 states have (on average 23.75) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 11:54:39,467 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 11:54:39,467 INFO L93 Difference]: Finished difference Result 86992 states and 121969 transitions. [2022-12-13 11:54:39,468 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 86992 states and 121969 transitions. [2022-12-13 11:54:39,729 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 86386 [2022-12-13 11:54:39,899 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 86992 states to 86992 states and 121969 transitions. [2022-12-13 11:54:39,899 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 86992 [2022-12-13 11:54:39,938 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 86992 [2022-12-13 11:54:39,938 INFO L73 IsDeterministic]: Start isDeterministic. Operand 86992 states and 121969 transitions. [2022-12-13 11:54:39,974 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 11:54:39,974 INFO L218 hiAutomatonCegarLoop]: Abstraction has 86992 states and 121969 transitions. [2022-12-13 11:54:40,013 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 86992 states and 121969 transitions. [2022-12-13 11:54:40,711 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 86992 to 62259. [2022-12-13 11:54:40,751 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 62259 states, 62259 states have (on average 1.4065918180504025) internal successors, (87573), 62258 states have internal predecessors, (87573), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 11:54:40,868 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 62259 states to 62259 states and 87573 transitions. [2022-12-13 11:54:40,869 INFO L240 hiAutomatonCegarLoop]: Abstraction has 62259 states and 87573 transitions. [2022-12-13 11:54:40,869 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 11:54:40,870 INFO L428 stractBuchiCegarLoop]: Abstraction has 62259 states and 87573 transitions. [2022-12-13 11:54:40,870 INFO L335 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2022-12-13 11:54:40,870 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 62259 states and 87573 transitions. [2022-12-13 11:54:41,109 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 61839 [2022-12-13 11:54:41,109 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 11:54:41,109 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 11:54:41,110 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 11:54:41,110 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 11:54:41,110 INFO L748 eck$LassoCheckResult]: Stem: 1209254#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 1209255#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 1209884#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1209885#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1210000#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 1209389#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1209390#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1209513#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1209514#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1209298#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1209093#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1209094#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1209259#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1209260#L781 assume !(0 == ~M_E~0); 1209777#L781-2 assume !(0 == ~T1_E~0); 1210022#L786-1 assume !(0 == ~T2_E~0); 1209057#L791-1 assume !(0 == ~T3_E~0); 1209058#L796-1 assume !(0 == ~T4_E~0); 1209597#L801-1 assume !(0 == ~T5_E~0); 1209598#L806-1 assume !(0 == ~T6_E~0); 1209631#L811-1 assume !(0 == ~T7_E~0); 1209265#L816-1 assume !(0 == ~E_M~0); 1209266#L821-1 assume !(0 == ~E_1~0); 1209085#L826-1 assume !(0 == ~E_2~0); 1209086#L831-1 assume !(0 == ~E_3~0); 1209383#L836-1 assume 0 == ~E_4~0;~E_4~0 := 1; 1209384#L841-1 assume !(0 == ~E_5~0); 1209220#L846-1 assume !(0 == ~E_6~0); 1209221#L851-1 assume !(0 == ~E_7~0); 1210083#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1209909#L388 assume !(1 == ~m_pc~0); 1209237#L388-2 is_master_triggered_~__retres1~0#1 := 0; 1209238#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1209748#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1209099#L967 assume !(0 != activate_threads_~tmp~1#1); 1209100#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1209033#L407 assume !(1 == ~t1_pc~0); 1209034#L407-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1210080#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1210079#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1209880#L975 assume !(0 != activate_threads_~tmp___0~0#1); 1209881#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1209346#L426 assume !(1 == ~t2_pc~0); 1209347#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1210078#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1209366#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1209367#L983 assume !(0 != activate_threads_~tmp___1~0#1); 1209977#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1209429#L445 assume !(1 == ~t3_pc~0); 1209430#L445-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1210073#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1209031#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1209032#L991 assume !(0 != activate_threads_~tmp___2~0#1); 1209699#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1209784#L464 assume !(1 == ~t4_pc~0); 1210067#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1210066#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1210065#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1210064#L999 assume !(0 != activate_threads_~tmp___3~0#1); 1210063#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1210062#L483 assume !(1 == ~t5_pc~0); 1210061#L483-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1210060#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1210059#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1210058#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 1210057#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1210056#L502 assume !(1 == ~t6_pc~0); 1210055#L502-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1210054#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1210053#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1210052#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 1210051#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1210050#L521 assume !(1 == ~t7_pc~0); 1210049#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1210074#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1210010#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1210011#L1023 assume !(0 != activate_threads_~tmp___6~0#1); 1210044#L1023-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1210043#L869 assume !(1 == ~M_E~0); 1210042#L869-2 assume !(1 == ~T1_E~0); 1210041#L874-1 assume !(1 == ~T2_E~0); 1210040#L879-1 assume !(1 == ~T3_E~0); 1210039#L884-1 assume !(1 == ~T4_E~0); 1210038#L889-1 assume !(1 == ~T5_E~0); 1210037#L894-1 assume !(1 == ~T6_E~0); 1210036#L899-1 assume !(1 == ~T7_E~0); 1210035#L904-1 assume !(1 == ~E_M~0); 1210034#L909-1 assume !(1 == ~E_1~0); 1210033#L914-1 assume !(1 == ~E_2~0); 1210032#L919-1 assume !(1 == ~E_3~0); 1210031#L924-1 assume 1 == ~E_4~0;~E_4~0 := 2; 1209190#L929-1 assume !(1 == ~E_5~0); 1209191#L934-1 assume !(1 == ~E_6~0); 1209407#L939-1 assume !(1 == ~E_7~0); 1209408#L944-1 assume { :end_inline_reset_delta_events } true; 1209831#L1190-2 [2022-12-13 11:54:41,111 INFO L750 eck$LassoCheckResult]: Loop: 1209831#L1190-2 assume !false; 1236157#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1236155#L756 assume !false; 1236153#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1228051#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1228043#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1228042#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1228040#L653 assume !(0 != eval_~tmp~0#1); 1228039#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1228038#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1228037#L781-3 assume !(0 == ~M_E~0); 1228036#L781-5 assume !(0 == ~T1_E~0); 1228035#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1228034#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1228033#L796-3 assume !(0 == ~T4_E~0); 1228032#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1228031#L806-3 assume !(0 == ~T6_E~0); 1228030#L811-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1228029#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1228028#L821-3 assume !(0 == ~E_1~0); 1228027#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1228026#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1228024#L836-3 assume !(0 == ~E_4~0); 1228023#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1228022#L846-3 assume !(0 == ~E_6~0); 1228021#L851-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1228020#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1228019#L388-27 assume !(1 == ~m_pc~0); 1228018#L388-29 is_master_triggered_~__retres1~0#1 := 0; 1228017#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1228016#is_master_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1228015#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1228014#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1228013#L407-27 assume !(1 == ~t1_pc~0); 1228012#L407-29 is_transmit1_triggered_~__retres1~1#1 := 0; 1228011#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1228010#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1228009#L975-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1228008#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1228007#L426-27 assume 1 == ~t2_pc~0; 1228006#L427-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1228004#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1228003#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1228002#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1228001#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1228000#L445-27 assume !(1 == ~t3_pc~0); 1227999#L445-29 is_transmit3_triggered_~__retres1~3#1 := 0; 1227998#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1227997#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1227996#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1227995#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1227994#L464-27 assume !(1 == ~t4_pc~0); 1227990#L464-29 is_transmit4_triggered_~__retres1~4#1 := 0; 1227989#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1227988#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1227987#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1227986#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1227985#L483-27 assume !(1 == ~t5_pc~0); 1227984#L483-29 is_transmit5_triggered_~__retres1~5#1 := 0; 1227983#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1227982#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1227981#L1007-27 assume !(0 != activate_threads_~tmp___4~0#1); 1227980#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1227979#L502-27 assume !(1 == ~t6_pc~0); 1227978#L502-29 is_transmit6_triggered_~__retres1~6#1 := 0; 1227977#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1227976#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1227975#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1227974#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1227973#L521-27 assume !(1 == ~t7_pc~0); 1227970#L521-29 is_transmit7_triggered_~__retres1~7#1 := 0; 1227969#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1227968#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1227967#L1023-27 assume !(0 != activate_threads_~tmp___6~0#1); 1227965#L1023-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1227964#L869-3 assume !(1 == ~M_E~0); 1227961#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1227960#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1227959#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1227958#L884-3 assume !(1 == ~T4_E~0); 1227957#L889-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1227956#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1227955#L899-3 assume !(1 == ~T7_E~0); 1227954#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1227953#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1227952#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1227951#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1227950#L924-3 assume !(1 == ~E_4~0); 1227940#L929-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1227938#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1227936#L939-3 assume !(1 == ~E_7~0); 1227935#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1227932#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1227926#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1227925#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 1227923#L1209 assume !(0 == start_simulation_~tmp~3#1); 1227924#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1243465#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1243459#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1243455#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 1243453#L1164 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1242431#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1241434#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 1241362#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 1209831#L1190-2 [2022-12-13 11:54:41,111 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 11:54:41,111 INFO L85 PathProgramCache]: Analyzing trace with hash -281555835, now seen corresponding path program 1 times [2022-12-13 11:54:41,111 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 11:54:41,111 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [20035018] [2022-12-13 11:54:41,111 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 11:54:41,111 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 11:54:41,118 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 11:54:41,143 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 11:54:41,143 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 11:54:41,143 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [20035018] [2022-12-13 11:54:41,143 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [20035018] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 11:54:41,143 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 11:54:41,143 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 11:54:41,143 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [548861045] [2022-12-13 11:54:41,143 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 11:54:41,144 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 11:54:41,144 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 11:54:41,144 INFO L85 PathProgramCache]: Analyzing trace with hash 1193467555, now seen corresponding path program 1 times [2022-12-13 11:54:41,144 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 11:54:41,144 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [577851989] [2022-12-13 11:54:41,144 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 11:54:41,144 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 11:54:41,150 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 11:54:41,165 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 11:54:41,165 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 11:54:41,165 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [577851989] [2022-12-13 11:54:41,165 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [577851989] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 11:54:41,165 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 11:54:41,165 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 11:54:41,165 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [798567436] [2022-12-13 11:54:41,165 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 11:54:41,166 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 11:54:41,166 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 11:54:41,166 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 11:54:41,166 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 11:54:41,166 INFO L87 Difference]: Start difference. First operand 62259 states and 87573 transitions. cyclomatic complexity: 25330 Second operand has 4 states, 4 states have (on average 23.75) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 11:54:41,385 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 11:54:41,385 INFO L93 Difference]: Finished difference Result 77977 states and 109111 transitions. [2022-12-13 11:54:41,385 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 77977 states and 109111 transitions. [2022-12-13 11:54:41,620 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 77486 [2022-12-13 11:54:41,792 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 77977 states to 77977 states and 109111 transitions. [2022-12-13 11:54:41,792 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 77977 [2022-12-13 11:54:41,833 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 77977 [2022-12-13 11:54:41,833 INFO L73 IsDeterministic]: Start isDeterministic. Operand 77977 states and 109111 transitions. [2022-12-13 11:54:41,873 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 11:54:41,874 INFO L218 hiAutomatonCegarLoop]: Abstraction has 77977 states and 109111 transitions. [2022-12-13 11:54:41,913 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 77977 states and 109111 transitions. [2022-12-13 11:54:42,410 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 77977 to 54326. [2022-12-13 11:54:42,444 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 54326 states, 54326 states have (on average 1.4016493023598278) internal successors, (76146), 54325 states have internal predecessors, (76146), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 11:54:42,519 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 54326 states to 54326 states and 76146 transitions. [2022-12-13 11:54:42,519 INFO L240 hiAutomatonCegarLoop]: Abstraction has 54326 states and 76146 transitions. [2022-12-13 11:54:42,520 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 11:54:42,521 INFO L428 stractBuchiCegarLoop]: Abstraction has 54326 states and 76146 transitions. [2022-12-13 11:54:42,521 INFO L335 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2022-12-13 11:54:42,521 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 54326 states and 76146 transitions. [2022-12-13 11:54:42,653 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 53977 [2022-12-13 11:54:42,654 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 11:54:42,654 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 11:54:42,654 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 11:54:42,655 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 11:54:42,655 INFO L748 eck$LassoCheckResult]: Stem: 1349502#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 1349503#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 1350145#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1350146#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1350239#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 1349643#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1349644#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1349773#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1349774#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1349548#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1349339#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1349340#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1349507#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1349508#L781 assume !(0 == ~M_E~0); 1350036#L781-2 assume !(0 == ~T1_E~0); 1350260#L786-1 assume !(0 == ~T2_E~0); 1349303#L791-1 assume !(0 == ~T3_E~0); 1349304#L796-1 assume !(0 == ~T4_E~0); 1349858#L801-1 assume !(0 == ~T5_E~0); 1349859#L806-1 assume !(0 == ~T6_E~0); 1349894#L811-1 assume !(0 == ~T7_E~0); 1349513#L816-1 assume !(0 == ~E_M~0); 1349514#L821-1 assume !(0 == ~E_1~0); 1349331#L826-1 assume !(0 == ~E_2~0); 1349332#L831-1 assume !(0 == ~E_3~0); 1349638#L836-1 assume !(0 == ~E_4~0); 1349639#L841-1 assume !(0 == ~E_5~0); 1349468#L846-1 assume !(0 == ~E_6~0); 1349469#L851-1 assume !(0 == ~E_7~0); 1349492#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1349493#L388 assume !(1 == ~m_pc~0); 1349486#L388-2 is_master_triggered_~__retres1~0#1 := 0; 1349487#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1350009#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1349345#L967 assume !(0 != activate_threads_~tmp~1#1); 1349346#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1349279#L407 assume !(1 == ~t1_pc~0); 1349280#L407-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1349286#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1349287#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1349319#L975 assume !(0 != activate_threads_~tmp___0~0#1); 1350139#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1349596#L426 assume !(1 == ~t2_pc~0); 1349597#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1350171#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1349618#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1349619#L983 assume !(0 != activate_threads_~tmp___1~0#1); 1350220#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1349686#L445 assume !(1 == ~t3_pc~0); 1349687#L445-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1350045#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1349277#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1349278#L991 assume !(0 != activate_threads_~tmp___2~0#1); 1349965#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1349925#L464 assume !(1 == ~t4_pc~0); 1349496#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1349365#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1349366#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1349379#L999 assume !(0 != activate_threads_~tmp___3~0#1); 1349665#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1349666#L483 assume !(1 == ~t5_pc~0); 1349922#L483-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1350118#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1350072#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1350073#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 1349583#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1349584#L502 assume !(1 == ~t6_pc~0); 1349445#L502-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1349404#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1349405#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1349607#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 1349815#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1350090#L521 assume !(1 == ~t7_pc~0); 1350136#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1349341#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1349342#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1350129#L1023 assume !(0 != activate_threads_~tmp___6~0#1); 1350101#L1023-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1350001#L869 assume !(1 == ~M_E~0); 1349658#L869-2 assume !(1 == ~T1_E~0); 1349659#L874-1 assume !(1 == ~T2_E~0); 1350190#L879-1 assume !(1 == ~T3_E~0); 1349735#L884-1 assume !(1 == ~T4_E~0); 1349265#L889-1 assume !(1 == ~T5_E~0); 1349266#L894-1 assume !(1 == ~T6_E~0); 1349524#L899-1 assume !(1 == ~T7_E~0); 1349952#L904-1 assume !(1 == ~E_M~0); 1349680#L909-1 assume !(1 == ~E_1~0); 1349681#L914-1 assume !(1 == ~E_2~0); 1349880#L919-1 assume !(1 == ~E_3~0); 1349595#L924-1 assume !(1 == ~E_4~0); 1349436#L929-1 assume !(1 == ~E_5~0); 1349437#L934-1 assume !(1 == ~E_6~0); 1349663#L939-1 assume !(1 == ~E_7~0); 1349664#L944-1 assume { :end_inline_reset_delta_events } true; 1350089#L1190-2 [2022-12-13 11:54:42,655 INFO L750 eck$LassoCheckResult]: Loop: 1350089#L1190-2 assume !false; 1379493#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1379491#L756 assume !false; 1379490#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1379489#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1379481#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1379480#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1379478#L653 assume !(0 != eval_~tmp~0#1); 1379479#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1403572#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1403571#L781-3 assume !(0 == ~M_E~0); 1403570#L781-5 assume !(0 == ~T1_E~0); 1403569#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1403568#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1403567#L796-3 assume !(0 == ~T4_E~0); 1403566#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1403565#L806-3 assume !(0 == ~T6_E~0); 1403563#L811-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1403561#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1403559#L821-3 assume !(0 == ~E_1~0); 1403557#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1403555#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1403554#L836-3 assume !(0 == ~E_4~0); 1403552#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1403550#L846-3 assume !(0 == ~E_6~0); 1403548#L851-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1403546#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1403544#L388-27 assume !(1 == ~m_pc~0); 1403541#L388-29 is_master_triggered_~__retres1~0#1 := 0; 1403539#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1403537#is_master_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1403535#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1403534#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1403533#L407-27 assume !(1 == ~t1_pc~0); 1403532#L407-29 is_transmit1_triggered_~__retres1~1#1 := 0; 1403531#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1403530#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1403528#L975-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1403526#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1403525#L426-27 assume 1 == ~t2_pc~0; 1403524#L427-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1403522#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1403521#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1403520#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1403519#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1403481#L445-27 assume !(1 == ~t3_pc~0); 1403479#L445-29 is_transmit3_triggered_~__retres1~3#1 := 0; 1403476#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1349781#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1349782#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1402943#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1402942#L464-27 assume !(1 == ~t4_pc~0); 1402940#L464-29 is_transmit4_triggered_~__retres1~4#1 := 0; 1402939#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1402937#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1402935#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1402933#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1402931#L483-27 assume !(1 == ~t5_pc~0); 1402929#L483-29 is_transmit5_triggered_~__retres1~5#1 := 0; 1402927#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1402925#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1402923#L1007-27 assume !(0 != activate_threads_~tmp___4~0#1); 1402921#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1402919#L502-27 assume !(1 == ~t6_pc~0); 1402917#L502-29 is_transmit6_triggered_~__retres1~6#1 := 0; 1402915#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1402913#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1402911#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1402909#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1402908#L521-27 assume 1 == ~t7_pc~0; 1402907#L522-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 1402905#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1402903#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1402900#L1023-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1402897#L1023-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1402895#L869-3 assume !(1 == ~M_E~0); 1358122#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1402892#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1402890#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1402888#L884-3 assume !(1 == ~T4_E~0); 1402886#L889-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1402884#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1402882#L899-3 assume !(1 == ~T7_E~0); 1402880#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1402878#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1402875#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1402873#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1380351#L924-3 assume !(1 == ~E_4~0); 1380345#L929-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1380340#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1380337#L939-3 assume !(1 == ~E_7~0); 1380335#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1380262#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1380252#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1380245#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 1358003#L1209 assume !(0 == start_simulation_~tmp~3#1); 1358004#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1379640#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1379633#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1379631#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 1379629#L1164 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1379626#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1379624#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 1379623#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 1350089#L1190-2 [2022-12-13 11:54:42,655 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 11:54:42,655 INFO L85 PathProgramCache]: Analyzing trace with hash 1628748997, now seen corresponding path program 1 times [2022-12-13 11:54:42,656 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 11:54:42,656 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1974798098] [2022-12-13 11:54:42,656 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 11:54:42,656 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 11:54:42,663 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 11:54:42,663 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 11:54:42,668 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 11:54:42,710 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 11:54:42,711 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 11:54:42,711 INFO L85 PathProgramCache]: Analyzing trace with hash -559581408, now seen corresponding path program 1 times [2022-12-13 11:54:42,711 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 11:54:42,711 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [709198963] [2022-12-13 11:54:42,711 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 11:54:42,711 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 11:54:42,717 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 11:54:42,733 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 11:54:42,733 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 11:54:42,733 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [709198963] [2022-12-13 11:54:42,733 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [709198963] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 11:54:42,733 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 11:54:42,733 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 11:54:42,734 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [222390704] [2022-12-13 11:54:42,734 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 11:54:42,734 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 11:54:42,734 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 11:54:42,734 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 11:54:42,734 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 11:54:42,734 INFO L87 Difference]: Start difference. First operand 54326 states and 76146 transitions. cyclomatic complexity: 21836 Second operand has 3 states, 3 states have (on average 34.666666666666664) internal successors, (104), 3 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 11:54:42,896 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 11:54:42,896 INFO L93 Difference]: Finished difference Result 62259 states and 87137 transitions. [2022-12-13 11:54:42,896 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 62259 states and 87137 transitions. [2022-12-13 11:54:43,217 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 61839 [2022-12-13 11:54:43,316 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 62259 states to 62259 states and 87137 transitions. [2022-12-13 11:54:43,316 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 62259 [2022-12-13 11:54:43,338 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 62259 [2022-12-13 11:54:43,338 INFO L73 IsDeterministic]: Start isDeterministic. Operand 62259 states and 87137 transitions. [2022-12-13 11:54:43,359 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 11:54:43,359 INFO L218 hiAutomatonCegarLoop]: Abstraction has 62259 states and 87137 transitions. [2022-12-13 11:54:43,380 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 62259 states and 87137 transitions. [2022-12-13 11:54:43,712 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 62259 to 62259. [2022-12-13 11:54:43,750 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 62259 states, 62259 states have (on average 1.3995888144685908) internal successors, (87137), 62258 states have internal predecessors, (87137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 11:54:43,834 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 62259 states to 62259 states and 87137 transitions. [2022-12-13 11:54:43,834 INFO L240 hiAutomatonCegarLoop]: Abstraction has 62259 states and 87137 transitions. [2022-12-13 11:54:43,835 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 11:54:43,835 INFO L428 stractBuchiCegarLoop]: Abstraction has 62259 states and 87137 transitions. [2022-12-13 11:54:43,835 INFO L335 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2022-12-13 11:54:43,836 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 62259 states and 87137 transitions. [2022-12-13 11:54:44,074 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 61839 [2022-12-13 11:54:44,074 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 11:54:44,074 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 11:54:44,075 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 11:54:44,075 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 11:54:44,075 INFO L748 eck$LassoCheckResult]: Stem: 1466092#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 1466093#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 1466747#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1466748#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1466848#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 1466232#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1466233#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1466361#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1466362#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1466137#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1465931#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1465932#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1466097#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1466098#L781 assume !(0 == ~M_E~0); 1466634#L781-2 assume !(0 == ~T1_E~0); 1466866#L786-1 assume !(0 == ~T2_E~0); 1465894#L791-1 assume !(0 == ~T3_E~0); 1465895#L796-1 assume !(0 == ~T4_E~0); 1466443#L801-1 assume !(0 == ~T5_E~0); 1466444#L806-1 assume !(0 == ~T6_E~0); 1466482#L811-1 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1466103#L816-1 assume !(0 == ~E_M~0); 1466104#L821-1 assume !(0 == ~E_1~0); 1465923#L826-1 assume !(0 == ~E_2~0); 1465924#L831-1 assume !(0 == ~E_3~0); 1466227#L836-1 assume !(0 == ~E_4~0); 1466228#L841-1 assume !(0 == ~E_5~0); 1466057#L846-1 assume !(0 == ~E_6~0); 1466058#L851-1 assume !(0 == ~E_7~0); 1466908#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1466771#L388 assume !(1 == ~m_pc~0); 1466075#L388-2 is_master_triggered_~__retres1~0#1 := 0; 1466076#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1466604#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1465937#L967 assume !(0 != activate_threads_~tmp~1#1); 1465938#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1465870#L407 assume !(1 == ~t1_pc~0); 1465871#L407-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1466905#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1466904#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1466741#L975 assume !(0 != activate_threads_~tmp___0~0#1); 1466742#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1466185#L426 assume !(1 == ~t2_pc~0); 1466186#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1466833#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1466834#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1466829#L983 assume !(0 != activate_threads_~tmp___1~0#1); 1466830#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1466275#L445 assume !(1 == ~t3_pc~0); 1466276#L445-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1466641#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1466642#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1466899#L991 assume !(0 != activate_threads_~tmp___2~0#1); 1466898#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1466896#L464 assume !(1 == ~t4_pc~0); 1466895#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1465957#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1465958#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1465971#L999 assume !(0 != activate_threads_~tmp___3~0#1); 1466253#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1466254#L483 assume !(1 == ~t5_pc~0); 1466755#L483-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1466756#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1466675#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1466676#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 1466891#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1466890#L502 assume !(1 == ~t6_pc~0); 1466035#L502-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1466036#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1466196#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1466197#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 1466691#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1466692#L521 assume !(1 == ~t7_pc~0); 1466887#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1466885#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1466884#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1466883#L1023 assume !(0 != activate_threads_~tmp___6~0#1); 1466699#L1023-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1466594#L869 assume !(1 == ~M_E~0); 1466247#L869-2 assume !(1 == ~T1_E~0); 1466248#L874-1 assume !(1 == ~T2_E~0); 1466792#L879-1 assume !(1 == ~T3_E~0); 1466793#L884-1 assume !(1 == ~T4_E~0); 1465856#L889-1 assume !(1 == ~T5_E~0); 1465857#L894-1 assume !(1 == ~T6_E~0); 1466113#L899-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1466541#L904-1 assume !(1 == ~E_M~0); 1466269#L909-1 assume !(1 == ~E_1~0); 1466270#L914-1 assume !(1 == ~E_2~0); 1466467#L919-1 assume !(1 == ~E_3~0); 1466184#L924-1 assume !(1 == ~E_4~0); 1466028#L929-1 assume !(1 == ~E_5~0); 1466029#L934-1 assume !(1 == ~E_6~0); 1466251#L939-1 assume !(1 == ~E_7~0); 1466252#L944-1 assume { :end_inline_reset_delta_events } true; 1466690#L1190-2 [2022-12-13 11:54:44,076 INFO L750 eck$LassoCheckResult]: Loop: 1466690#L1190-2 assume !false; 1495231#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1495230#L756 assume !false; 1495229#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1495228#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1495220#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1495219#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1495217#L653 assume !(0 != eval_~tmp~0#1); 1495218#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1495857#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1495855#L781-3 assume !(0 == ~M_E~0); 1495853#L781-5 assume !(0 == ~T1_E~0); 1495849#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1495845#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1495841#L796-3 assume !(0 == ~T4_E~0); 1495836#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1495831#L806-3 assume !(0 == ~T6_E~0); 1495825#L811-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1495826#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1495838#L821-3 assume !(0 == ~E_1~0); 1495833#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1495828#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1495823#L836-3 assume !(0 == ~E_4~0); 1495819#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1495813#L846-3 assume !(0 == ~E_6~0); 1495808#L851-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1495803#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1495798#L388-27 assume !(1 == ~m_pc~0); 1495793#L388-29 is_master_triggered_~__retres1~0#1 := 0; 1495788#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1495781#is_master_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1495769#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1495764#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1495759#L407-27 assume !(1 == ~t1_pc~0); 1495753#L407-29 is_transmit1_triggered_~__retres1~1#1 := 0; 1495749#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1495744#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1495739#L975-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1495734#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1495729#L426-27 assume 1 == ~t2_pc~0; 1495724#L427-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1495718#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1495713#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1495708#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1495703#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1495695#L445-27 assume !(1 == ~t3_pc~0); 1495690#L445-29 is_transmit3_triggered_~__retres1~3#1 := 0; 1495685#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1495680#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1495674#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1495669#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1495664#L464-27 assume !(1 == ~t4_pc~0); 1495658#L464-29 is_transmit4_triggered_~__retres1~4#1 := 0; 1495653#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1495648#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1495643#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1495635#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1495630#L483-27 assume !(1 == ~t5_pc~0); 1495625#L483-29 is_transmit5_triggered_~__retres1~5#1 := 0; 1495620#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1495614#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1495609#L1007-27 assume !(0 != activate_threads_~tmp___4~0#1); 1495604#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1495599#L502-27 assume !(1 == ~t6_pc~0); 1495594#L502-29 is_transmit6_triggered_~__retres1~6#1 := 0; 1495589#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1495584#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1495579#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1495574#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1495568#L521-27 assume !(1 == ~t7_pc~0); 1495562#L521-29 is_transmit7_triggered_~__retres1~7#1 := 0; 1495570#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1495564#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1495491#L1023-27 assume !(0 != activate_threads_~tmp___6~0#1); 1495477#L1023-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1495468#L869-3 assume !(1 == ~M_E~0); 1495457#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1495449#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1495443#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1495436#L884-3 assume !(1 == ~T4_E~0); 1495430#L889-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1495424#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1495417#L899-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1495411#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1495405#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1495400#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1495395#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1495390#L924-3 assume !(1 == ~E_4~0); 1495385#L929-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1495380#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1495375#L939-3 assume !(1 == ~E_7~0); 1495372#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1495363#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1495353#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1495348#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 1495342#L1209 assume !(0 == start_simulation_~tmp~3#1); 1495338#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1495280#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1495270#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1495263#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 1495256#L1164 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1495250#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1495242#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 1495237#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 1466690#L1190-2 [2022-12-13 11:54:44,076 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 11:54:44,076 INFO L85 PathProgramCache]: Analyzing trace with hash 287671557, now seen corresponding path program 1 times [2022-12-13 11:54:44,076 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 11:54:44,076 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1654021222] [2022-12-13 11:54:44,076 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 11:54:44,077 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 11:54:44,084 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 11:54:44,114 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 11:54:44,114 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 11:54:44,114 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1654021222] [2022-12-13 11:54:44,114 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1654021222] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 11:54:44,114 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 11:54:44,115 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 11:54:44,115 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1318071298] [2022-12-13 11:54:44,115 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 11:54:44,115 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 11:54:44,115 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 11:54:44,115 INFO L85 PathProgramCache]: Analyzing trace with hash 974612837, now seen corresponding path program 1 times [2022-12-13 11:54:44,116 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 11:54:44,116 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1036808827] [2022-12-13 11:54:44,116 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 11:54:44,116 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 11:54:44,123 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 11:54:44,142 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 11:54:44,142 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 11:54:44,143 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1036808827] [2022-12-13 11:54:44,143 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1036808827] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 11:54:44,143 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 11:54:44,143 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 11:54:44,143 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1337437807] [2022-12-13 11:54:44,143 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 11:54:44,143 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 11:54:44,144 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 11:54:44,144 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 11:54:44,144 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 11:54:44,144 INFO L87 Difference]: Start difference. First operand 62259 states and 87137 transitions. cyclomatic complexity: 24894 Second operand has 4 states, 4 states have (on average 23.75) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 11:54:44,396 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 11:54:44,396 INFO L93 Difference]: Finished difference Result 79023 states and 110347 transitions. [2022-12-13 11:54:44,397 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 79023 states and 110347 transitions. [2022-12-13 11:54:44,704 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 78541 [2022-12-13 11:54:44,896 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 79023 states to 79023 states and 110347 transitions. [2022-12-13 11:54:44,896 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 79023 [2022-12-13 11:54:44,936 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 79023 [2022-12-13 11:54:44,937 INFO L73 IsDeterministic]: Start isDeterministic. Operand 79023 states and 110347 transitions. [2022-12-13 11:54:44,977 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 11:54:44,977 INFO L218 hiAutomatonCegarLoop]: Abstraction has 79023 states and 110347 transitions. [2022-12-13 11:54:45,016 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 79023 states and 110347 transitions. [2022-12-13 11:54:45,569 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 79023 to 54326. [2022-12-13 11:54:45,601 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 54326 states, 54326 states have (on average 1.3996428965872694) internal successors, (76037), 54325 states have internal predecessors, (76037), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 11:54:45,675 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 54326 states to 54326 states and 76037 transitions. [2022-12-13 11:54:45,675 INFO L240 hiAutomatonCegarLoop]: Abstraction has 54326 states and 76037 transitions. [2022-12-13 11:54:45,676 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 11:54:45,676 INFO L428 stractBuchiCegarLoop]: Abstraction has 54326 states and 76037 transitions. [2022-12-13 11:54:45,676 INFO L335 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2022-12-13 11:54:45,676 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 54326 states and 76037 transitions. [2022-12-13 11:54:45,804 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 53977 [2022-12-13 11:54:45,804 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 11:54:45,804 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 11:54:45,805 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 11:54:45,805 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 11:54:45,805 INFO L748 eck$LassoCheckResult]: Stem: 1607379#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 1607380#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 1608011#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1608012#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1608101#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 1607520#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1607521#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1607647#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1607648#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1607425#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1607222#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1607223#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1607386#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1607387#L781 assume !(0 == ~M_E~0); 1607909#L781-2 assume !(0 == ~T1_E~0); 1608121#L786-1 assume !(0 == ~T2_E~0); 1607186#L791-1 assume !(0 == ~T3_E~0); 1607187#L796-1 assume !(0 == ~T4_E~0); 1607730#L801-1 assume !(0 == ~T5_E~0); 1607731#L806-1 assume !(0 == ~T6_E~0); 1607766#L811-1 assume !(0 == ~T7_E~0); 1607391#L816-1 assume !(0 == ~E_M~0); 1607392#L821-1 assume !(0 == ~E_1~0); 1607214#L826-1 assume !(0 == ~E_2~0); 1607215#L831-1 assume !(0 == ~E_3~0); 1607515#L836-1 assume !(0 == ~E_4~0); 1607516#L841-1 assume !(0 == ~E_5~0); 1607346#L846-1 assume !(0 == ~E_6~0); 1607347#L851-1 assume !(0 == ~E_7~0); 1607369#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1607370#L388 assume !(1 == ~m_pc~0); 1607363#L388-2 is_master_triggered_~__retres1~0#1 := 0; 1607364#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1607883#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1607228#L967 assume !(0 != activate_threads_~tmp~1#1); 1607229#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1607162#L407 assume !(1 == ~t1_pc~0); 1607163#L407-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1607169#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1607170#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1607202#L975 assume !(0 != activate_threads_~tmp___0~0#1); 1608005#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1607474#L426 assume !(1 == ~t2_pc~0); 1607475#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1608042#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1607496#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1607497#L983 assume !(0 != activate_threads_~tmp___1~0#1); 1608084#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1607560#L445 assume !(1 == ~t3_pc~0); 1607561#L445-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1607916#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1607160#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1607161#L991 assume !(0 != activate_threads_~tmp___2~0#1); 1607835#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1607796#L464 assume !(1 == ~t4_pc~0); 1607373#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1607248#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1607249#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1607262#L999 assume !(0 != activate_threads_~tmp___3~0#1); 1607540#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1607541#L483 assume !(1 == ~t5_pc~0); 1607793#L483-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1607984#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1607941#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1607942#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 1607461#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1607462#L502 assume !(1 == ~t6_pc~0); 1607325#L502-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1607287#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1607288#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1607485#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 1607690#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1607962#L521 assume !(1 == ~t7_pc~0); 1608002#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1607224#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1607225#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1607995#L1023 assume !(0 != activate_threads_~tmp___6~0#1); 1607969#L1023-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1607874#L869 assume !(1 == ~M_E~0); 1607534#L869-2 assume !(1 == ~T1_E~0); 1607535#L874-1 assume !(1 == ~T2_E~0); 1608056#L879-1 assume !(1 == ~T3_E~0); 1607609#L884-1 assume !(1 == ~T4_E~0); 1607148#L889-1 assume !(1 == ~T5_E~0); 1607149#L894-1 assume !(1 == ~T6_E~0); 1607401#L899-1 assume !(1 == ~T7_E~0); 1607825#L904-1 assume !(1 == ~E_M~0); 1607555#L909-1 assume !(1 == ~E_1~0); 1607556#L914-1 assume !(1 == ~E_2~0); 1607751#L919-1 assume !(1 == ~E_3~0); 1607473#L924-1 assume !(1 == ~E_4~0); 1607318#L929-1 assume !(1 == ~E_5~0); 1607319#L934-1 assume !(1 == ~E_6~0); 1607538#L939-1 assume !(1 == ~E_7~0); 1607539#L944-1 assume { :end_inline_reset_delta_events } true; 1607961#L1190-2 [2022-12-13 11:54:45,805 INFO L750 eck$LassoCheckResult]: Loop: 1607961#L1190-2 assume !false; 1629452#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1629450#L756 assume !false; 1629448#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1629446#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1629436#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1629434#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1629432#L653 assume !(0 != eval_~tmp~0#1); 1629433#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1660423#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1660421#L781-3 assume !(0 == ~M_E~0); 1660419#L781-5 assume !(0 == ~T1_E~0); 1660418#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1660416#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1660414#L796-3 assume !(0 == ~T4_E~0); 1660412#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1660410#L806-3 assume !(0 == ~T6_E~0); 1660408#L811-3 assume !(0 == ~T7_E~0); 1660405#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1660403#L821-3 assume !(0 == ~E_1~0); 1660401#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1660399#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1660397#L836-3 assume !(0 == ~E_4~0); 1660395#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1660393#L846-3 assume !(0 == ~E_6~0); 1660391#L851-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1660389#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1660387#L388-27 assume !(1 == ~m_pc~0); 1660385#L388-29 is_master_triggered_~__retres1~0#1 := 0; 1660382#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1660380#is_master_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1660378#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1660376#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1660374#L407-27 assume !(1 == ~t1_pc~0); 1660372#L407-29 is_transmit1_triggered_~__retres1~1#1 := 0; 1660370#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1660367#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1660365#L975-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1660363#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1660361#L426-27 assume 1 == ~t2_pc~0; 1660359#L427-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1660356#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1660355#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1660353#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1660352#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1660351#L445-27 assume !(1 == ~t3_pc~0); 1660350#L445-29 is_transmit3_triggered_~__retres1~3#1 := 0; 1660348#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1660346#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1660344#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1660342#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1658812#L464-27 assume !(1 == ~t4_pc~0); 1658809#L464-29 is_transmit4_triggered_~__retres1~4#1 := 0; 1658807#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1658803#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1658801#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1658799#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1658797#L483-27 assume !(1 == ~t5_pc~0); 1658794#L483-29 is_transmit5_triggered_~__retres1~5#1 := 0; 1658792#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1658790#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1658789#L1007-27 assume !(0 != activate_threads_~tmp___4~0#1); 1658787#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1658785#L502-27 assume !(1 == ~t6_pc~0); 1658783#L502-29 is_transmit6_triggered_~__retres1~6#1 := 0; 1658781#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1658779#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1658777#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1658775#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1658773#L521-27 assume !(1 == ~t7_pc~0); 1658769#L521-29 is_transmit7_triggered_~__retres1~7#1 := 0; 1658767#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1658765#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1658763#L1023-27 assume !(0 != activate_threads_~tmp___6~0#1); 1658760#L1023-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1658758#L869-3 assume !(1 == ~M_E~0); 1618749#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1658754#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1658752#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1658750#L884-3 assume !(1 == ~T4_E~0); 1657751#L889-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1635201#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1635200#L899-3 assume !(1 == ~T7_E~0); 1635199#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1635198#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1635196#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1635193#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1635191#L924-3 assume !(1 == ~E_4~0); 1635189#L929-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1635187#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1635185#L939-3 assume !(1 == ~E_7~0); 1633466#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1619330#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1619323#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1619321#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 1618886#L1209 assume !(0 == start_simulation_~tmp~3#1); 1618887#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1629573#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1629567#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1629566#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 1629565#L1164 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1629564#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1629562#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 1629560#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 1607961#L1190-2 [2022-12-13 11:54:45,806 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 11:54:45,806 INFO L85 PathProgramCache]: Analyzing trace with hash 1628748997, now seen corresponding path program 2 times [2022-12-13 11:54:45,806 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 11:54:45,806 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1282918840] [2022-12-13 11:54:45,806 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 11:54:45,806 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 11:54:45,815 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 11:54:45,815 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 11:54:45,820 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 11:54:45,835 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 11:54:45,835 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 11:54:45,835 INFO L85 PathProgramCache]: Analyzing trace with hash 607191333, now seen corresponding path program 1 times [2022-12-13 11:54:45,836 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 11:54:45,836 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1477403276] [2022-12-13 11:54:45,836 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 11:54:45,836 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 11:54:45,846 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 11:54:45,862 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 11:54:45,862 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 11:54:45,862 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1477403276] [2022-12-13 11:54:45,862 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1477403276] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 11:54:45,862 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 11:54:45,862 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 11:54:45,863 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1495413270] [2022-12-13 11:54:45,863 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 11:54:45,863 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 11:54:45,863 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 11:54:45,863 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 11:54:45,863 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 11:54:45,864 INFO L87 Difference]: Start difference. First operand 54326 states and 76037 transitions. cyclomatic complexity: 21727 Second operand has 3 states, 3 states have (on average 34.666666666666664) internal successors, (104), 3 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 11:54:46,148 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 11:54:46,148 INFO L93 Difference]: Finished difference Result 98522 states and 136894 transitions. [2022-12-13 11:54:46,149 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 98522 states and 136894 transitions. [2022-12-13 11:54:46,622 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 97857 [2022-12-13 11:54:46,784 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 98522 states to 98522 states and 136894 transitions. [2022-12-13 11:54:46,784 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 98522 [2022-12-13 11:54:46,819 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 98522 [2022-12-13 11:54:46,819 INFO L73 IsDeterministic]: Start isDeterministic. Operand 98522 states and 136894 transitions. [2022-12-13 11:54:46,850 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 11:54:46,850 INFO L218 hiAutomatonCegarLoop]: Abstraction has 98522 states and 136894 transitions. [2022-12-13 11:54:46,882 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 98522 states and 136894 transitions. [2022-12-13 11:54:47,568 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 98522 to 98486. [2022-12-13 11:54:47,634 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 98486 states, 98486 states have (on average 1.3896188290721523) internal successors, (136858), 98485 states have internal predecessors, (136858), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 11:54:47,778 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 98486 states to 98486 states and 136858 transitions. [2022-12-13 11:54:47,779 INFO L240 hiAutomatonCegarLoop]: Abstraction has 98486 states and 136858 transitions. [2022-12-13 11:54:47,779 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 11:54:47,780 INFO L428 stractBuchiCegarLoop]: Abstraction has 98486 states and 136858 transitions. [2022-12-13 11:54:47,780 INFO L335 stractBuchiCegarLoop]: ======== Iteration 23 ============ [2022-12-13 11:54:47,780 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 98486 states and 136858 transitions. [2022-12-13 11:54:48,035 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 97821 [2022-12-13 11:54:48,035 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 11:54:48,036 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 11:54:48,037 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 11:54:48,037 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 11:54:48,037 INFO L748 eck$LassoCheckResult]: Stem: 1760237#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 1760238#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 1760897#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1760898#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1761024#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 1760380#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1760381#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1760511#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1760512#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1760284#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1760076#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1760077#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1760242#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1760243#L781 assume !(0 == ~M_E~0); 1760783#L781-2 assume !(0 == ~T1_E~0); 1761043#L786-1 assume !(0 == ~T2_E~0); 1760037#L791-1 assume !(0 == ~T3_E~0); 1760038#L796-1 assume !(0 == ~T4_E~0); 1760600#L801-1 assume !(0 == ~T5_E~0); 1760601#L806-1 assume !(0 == ~T6_E~0); 1760634#L811-1 assume !(0 == ~T7_E~0); 1760248#L816-1 assume !(0 == ~E_M~0); 1760249#L821-1 assume !(0 == ~E_1~0); 1760068#L826-1 assume !(0 == ~E_2~0); 1760069#L831-1 assume !(0 == ~E_3~0); 1760375#L836-1 assume !(0 == ~E_4~0); 1760376#L841-1 assume !(0 == ~E_5~0); 1760203#L846-1 assume !(0 == ~E_6~0); 1760204#L851-1 assume 0 == ~E_7~0;~E_7~0 := 1; 1761032#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1760920#L388 assume !(1 == ~m_pc~0); 1760221#L388-2 is_master_triggered_~__retres1~0#1 := 0; 1760222#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1760755#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1760813#L967 assume !(0 != activate_threads_~tmp~1#1); 1761010#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1761011#L407 assume !(1 == ~t1_pc~0); 1761022#L407-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1760020#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1760021#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1760054#L975 assume !(0 != activate_threads_~tmp___0~0#1); 1760915#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1760916#L426 assume !(1 == ~t2_pc~0); 1760932#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1760933#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1760356#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1760357#L983 assume !(0 != activate_threads_~tmp___1~0#1); 1761096#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1761095#L445 assume !(1 == ~t3_pc~0); 1761044#L445-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1760792#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1760793#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1761093#L991 assume !(0 != activate_threads_~tmp___2~0#1); 1761092#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1761090#L464 assume !(1 == ~t4_pc~0); 1761089#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1761088#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1761087#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1761086#L999 assume !(0 != activate_threads_~tmp___3~0#1); 1761085#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1761084#L483 assume !(1 == ~t5_pc~0); 1760903#L483-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1760904#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1761083#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1760963#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 1760964#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1761081#L502 assume !(1 == ~t6_pc~0); 1760179#L502-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1760180#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1760342#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1760343#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 1760832#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1760833#L521 assume !(1 == ~t7_pc~0); 1761076#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1760078#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1760079#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1761033#L1023 assume !(0 != activate_threads_~tmp___6~0#1); 1760840#L1023-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1760740#L869 assume !(1 == ~M_E~0); 1760397#L869-2 assume !(1 == ~T1_E~0); 1760398#L874-1 assume !(1 == ~T2_E~0); 1760954#L879-1 assume !(1 == ~T3_E~0); 1760473#L884-1 assume !(1 == ~T4_E~0); 1760002#L889-1 assume !(1 == ~T5_E~0); 1760003#L894-1 assume !(1 == ~T6_E~0); 1761058#L899-1 assume !(1 == ~T7_E~0); 1760691#L904-1 assume !(1 == ~E_M~0); 1760420#L909-1 assume !(1 == ~E_1~0); 1760421#L914-1 assume !(1 == ~E_2~0); 1760618#L919-1 assume !(1 == ~E_3~0); 1760334#L924-1 assume !(1 == ~E_4~0); 1760172#L929-1 assume !(1 == ~E_5~0); 1760173#L934-1 assume !(1 == ~E_6~0); 1760399#L939-1 assume 1 == ~E_7~0;~E_7~0 := 2; 1760400#L944-1 assume { :end_inline_reset_delta_events } true; 1760831#L1190-2 [2022-12-13 11:54:48,037 INFO L750 eck$LassoCheckResult]: Loop: 1760831#L1190-2 assume !false; 1772853#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1772717#L756 assume !false; 1772706#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1772556#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1772546#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1772542#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1772529#L653 assume !(0 != eval_~tmp~0#1); 1772530#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1775488#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1775487#L781-3 assume !(0 == ~M_E~0); 1775486#L781-5 assume !(0 == ~T1_E~0); 1773433#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1773423#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1773421#L796-3 assume !(0 == ~T4_E~0); 1773419#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1773415#L806-3 assume !(0 == ~T6_E~0); 1773413#L811-3 assume !(0 == ~T7_E~0); 1773411#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1773409#L821-3 assume !(0 == ~E_1~0); 1773407#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1773405#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1773403#L836-3 assume !(0 == ~E_4~0); 1773401#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1773399#L846-3 assume !(0 == ~E_6~0); 1773380#L851-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1773378#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1773376#L388-27 assume !(1 == ~m_pc~0); 1773374#L388-29 is_master_triggered_~__retres1~0#1 := 0; 1773372#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1773370#is_master_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1773368#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1773364#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1773365#L407-27 assume !(1 == ~t1_pc~0); 1843549#L407-29 is_transmit1_triggered_~__retres1~1#1 := 0; 1843548#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1843547#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1843544#L975-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1843542#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1843540#L426-27 assume !(1 == ~t2_pc~0); 1843535#L426-29 is_transmit2_triggered_~__retres1~2#1 := 0; 1843534#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1843532#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1843530#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1843528#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1843526#L445-27 assume !(1 == ~t3_pc~0); 1843524#L445-29 is_transmit3_triggered_~__retres1~3#1 := 0; 1843521#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1843519#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1843517#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1843515#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1843513#L464-27 assume !(1 == ~t4_pc~0); 1843510#L464-29 is_transmit4_triggered_~__retres1~4#1 := 0; 1843509#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1843507#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1843505#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1843503#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1843502#L483-27 assume !(1 == ~t5_pc~0); 1843501#L483-29 is_transmit5_triggered_~__retres1~5#1 := 0; 1843499#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1843497#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1843495#L1007-27 assume !(0 != activate_threads_~tmp___4~0#1); 1843493#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1843491#L502-27 assume !(1 == ~t6_pc~0); 1843489#L502-29 is_transmit6_triggered_~__retres1~6#1 := 0; 1843487#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1843485#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1843483#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1843481#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1843478#L521-27 assume !(1 == ~t7_pc~0); 1843476#L521-29 is_transmit7_triggered_~__retres1~7#1 := 0; 1843474#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1843472#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1843470#L1023-27 assume !(0 != activate_threads_~tmp___6~0#1); 1843467#L1023-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1843465#L869-3 assume !(1 == ~M_E~0); 1773259#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1843463#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1843461#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1843459#L884-3 assume !(1 == ~T4_E~0); 1843457#L889-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1843455#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1843453#L899-3 assume !(1 == ~T7_E~0); 1843451#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1843449#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1843447#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1843445#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1843443#L924-3 assume !(1 == ~E_4~0); 1843441#L929-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1843439#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1843436#L939-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1843433#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1843425#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1843418#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1843416#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 1843415#L1209 assume !(0 == start_simulation_~tmp~3#1); 1773054#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1773046#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1773040#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1773039#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 1773035#L1164 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1773033#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1773032#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 1773028#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 1760831#L1190-2 [2022-12-13 11:54:48,038 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 11:54:48,038 INFO L85 PathProgramCache]: Analyzing trace with hash -1450064635, now seen corresponding path program 1 times [2022-12-13 11:54:48,038 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 11:54:48,038 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1610044269] [2022-12-13 11:54:48,038 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 11:54:48,039 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 11:54:48,045 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 11:54:48,072 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 11:54:48,073 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 11:54:48,073 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1610044269] [2022-12-13 11:54:48,073 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1610044269] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 11:54:48,073 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 11:54:48,073 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 11:54:48,073 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [47628089] [2022-12-13 11:54:48,073 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 11:54:48,074 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 11:54:48,074 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 11:54:48,074 INFO L85 PathProgramCache]: Analyzing trace with hash 1995951400, now seen corresponding path program 1 times [2022-12-13 11:54:48,074 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 11:54:48,074 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [228264584] [2022-12-13 11:54:48,074 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 11:54:48,075 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 11:54:48,081 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 11:54:48,114 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 11:54:48,114 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 11:54:48,114 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [228264584] [2022-12-13 11:54:48,114 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [228264584] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 11:54:48,114 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 11:54:48,115 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-12-13 11:54:48,115 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [467502042] [2022-12-13 11:54:48,115 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 11:54:48,115 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 11:54:48,115 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 11:54:48,115 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 11:54:48,115 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 11:54:48,116 INFO L87 Difference]: Start difference. First operand 98486 states and 136858 transitions. cyclomatic complexity: 38388 Second operand has 4 states, 4 states have (on average 23.75) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 11:54:48,696 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 11:54:48,696 INFO L93 Difference]: Finished difference Result 143269 states and 198353 transitions. [2022-12-13 11:54:48,696 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 143269 states and 198353 transitions. [2022-12-13 11:54:49,250 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 137485 [2022-12-13 11:54:49,576 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 143269 states to 143269 states and 198353 transitions. [2022-12-13 11:54:49,576 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 143269 [2022-12-13 11:54:49,643 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 143269 [2022-12-13 11:54:49,643 INFO L73 IsDeterministic]: Start isDeterministic. Operand 143269 states and 198353 transitions. [2022-12-13 11:54:49,709 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 11:54:49,709 INFO L218 hiAutomatonCegarLoop]: Abstraction has 143269 states and 198353 transitions. [2022-12-13 11:54:49,776 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 143269 states and 198353 transitions. [2022-12-13 11:54:50,643 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 143269 to 98435. [2022-12-13 11:54:50,704 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 98435 states, 98435 states have (on average 1.3886016152791183) internal successors, (136687), 98434 states have internal predecessors, (136687), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 11:54:50,859 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 98435 states to 98435 states and 136687 transitions. [2022-12-13 11:54:50,860 INFO L240 hiAutomatonCegarLoop]: Abstraction has 98435 states and 136687 transitions. [2022-12-13 11:54:50,860 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 11:54:50,861 INFO L428 stractBuchiCegarLoop]: Abstraction has 98435 states and 136687 transitions. [2022-12-13 11:54:50,861 INFO L335 stractBuchiCegarLoop]: ======== Iteration 24 ============ [2022-12-13 11:54:50,861 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 98435 states and 136687 transitions. [2022-12-13 11:54:51,192 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 97821 [2022-12-13 11:54:51,192 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 11:54:51,192 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 11:54:51,193 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 11:54:51,193 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 11:54:51,194 INFO L748 eck$LassoCheckResult]: Stem: 2002001#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 2002002#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 2002661#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2002662#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2002761#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 2002146#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2002147#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2002278#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2002279#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 2002049#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 2001843#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 2001844#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 2002007#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2002008#L781 assume !(0 == ~M_E~0); 2002552#L781-2 assume !(0 == ~T1_E~0); 2002784#L786-1 assume !(0 == ~T2_E~0); 2001804#L791-1 assume !(0 == ~T3_E~0); 2001805#L796-1 assume !(0 == ~T4_E~0); 2002362#L801-1 assume !(0 == ~T5_E~0); 2002363#L806-1 assume !(0 == ~T6_E~0); 2002401#L811-1 assume !(0 == ~T7_E~0); 2002013#L816-1 assume !(0 == ~E_M~0); 2002014#L821-1 assume !(0 == ~E_1~0); 2001835#L826-1 assume !(0 == ~E_2~0); 2001836#L831-1 assume !(0 == ~E_3~0); 2002141#L836-1 assume !(0 == ~E_4~0); 2002142#L841-1 assume !(0 == ~E_5~0); 2001967#L846-1 assume !(0 == ~E_6~0); 2001968#L851-1 assume !(0 == ~E_7~0); 2001991#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2001992#L388 assume !(1 == ~m_pc~0); 2001985#L388-2 is_master_triggered_~__retres1~0#1 := 0; 2001986#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2002522#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2001849#L967 assume !(0 != activate_threads_~tmp~1#1); 2001850#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2001783#L407 assume !(1 == ~t1_pc~0); 2001784#L407-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2001787#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2001788#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2001821#L975 assume !(0 != activate_threads_~tmp___0~0#1); 2002659#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2002100#L426 assume !(1 == ~t2_pc~0); 2002101#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2002691#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2002123#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2002124#L983 assume !(0 != activate_threads_~tmp___1~0#1); 2002744#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2002189#L445 assume !(1 == ~t3_pc~0); 2002190#L445-2 is_transmit3_triggered_~__retres1~3#1 := 0; 2002565#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2001781#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2001782#L991 assume !(0 != activate_threads_~tmp___2~0#1); 2002472#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2002432#L464 assume !(1 == ~t4_pc~0); 2001995#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 2001869#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2001870#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2001880#L999 assume !(0 != activate_threads_~tmp___3~0#1); 2002167#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2002168#L483 assume !(1 == ~t5_pc~0); 2002429#L483-2 is_transmit5_triggered_~__retres1~5#1 := 0; 2002637#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2002591#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2002592#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 2002085#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2002086#L502 assume !(1 == ~t6_pc~0); 2001945#L502-2 is_transmit6_triggered_~__retres1~6#1 := 0; 2001907#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2001908#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2002109#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 2002318#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2002606#L521 assume !(1 == ~t7_pc~0); 2002654#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 2002693#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2002801#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2002647#L1023 assume !(0 != activate_threads_~tmp___6~0#1); 2002648#L1023-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2002806#L869 assume !(1 == ~M_E~0); 2002805#L869-2 assume !(1 == ~T1_E~0); 2002739#L874-1 assume !(1 == ~T2_E~0); 2002740#L879-1 assume !(1 == ~T3_E~0); 2002239#L884-1 assume !(1 == ~T4_E~0); 2002240#L889-1 assume !(1 == ~T5_E~0); 2002020#L894-1 assume !(1 == ~T6_E~0); 2002021#L899-1 assume !(1 == ~T7_E~0); 2002459#L904-1 assume !(1 == ~E_M~0); 2002184#L909-1 assume !(1 == ~E_1~0); 2002185#L914-1 assume !(1 == ~E_2~0); 2002411#L919-1 assume !(1 == ~E_3~0); 2002412#L924-1 assume !(1 == ~E_4~0); 2002800#L929-1 assume !(1 == ~E_5~0); 2002799#L934-1 assume !(1 == ~E_6~0); 2002798#L939-1 assume !(1 == ~E_7~0); 2002164#L944-1 assume { :end_inline_reset_delta_events } true; 2002605#L1190-2 [2022-12-13 11:54:51,194 INFO L750 eck$LassoCheckResult]: Loop: 2002605#L1190-2 assume !false; 2077686#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2075006#L756 assume !false; 2077685#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 2077684#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 2077676#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 2077675#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 2077673#L653 assume !(0 != eval_~tmp~0#1); 2077674#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2084557#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2084555#L781-3 assume !(0 == ~M_E~0); 2084553#L781-5 assume !(0 == ~T1_E~0); 2084551#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2084549#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2084547#L796-3 assume !(0 == ~T4_E~0); 2084545#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2084543#L806-3 assume !(0 == ~T6_E~0); 2084541#L811-3 assume !(0 == ~T7_E~0); 2084539#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2084537#L821-3 assume !(0 == ~E_1~0); 2084534#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2084532#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2084530#L836-3 assume !(0 == ~E_4~0); 2084528#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2084526#L846-3 assume !(0 == ~E_6~0); 2084523#L851-3 assume !(0 == ~E_7~0); 2084522#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2084519#L388-27 assume !(1 == ~m_pc~0); 2084517#L388-29 is_master_triggered_~__retres1~0#1 := 0; 2084515#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2083147#is_master_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2072333#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2072331#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2072329#L407-27 assume !(1 == ~t1_pc~0); 2072328#L407-29 is_transmit1_triggered_~__retres1~1#1 := 0; 2072326#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2072324#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2072322#L975-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2072320#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2072318#L426-27 assume 1 == ~t2_pc~0; 2072315#L427-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2072312#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2072310#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2072308#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2072306#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2070745#L445-27 assume !(1 == ~t3_pc~0); 2070743#L445-29 is_transmit3_triggered_~__retres1~3#1 := 0; 2070741#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2070739#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2070737#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2070735#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2070733#L464-27 assume !(1 == ~t4_pc~0); 2070729#L464-29 is_transmit4_triggered_~__retres1~4#1 := 0; 2070727#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2070725#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2070723#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 2070721#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2070719#L483-27 assume !(1 == ~t5_pc~0); 2070717#L483-29 is_transmit5_triggered_~__retres1~5#1 := 0; 2070715#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2070713#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2070711#L1007-27 assume !(0 != activate_threads_~tmp___4~0#1); 2070709#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2070707#L502-27 assume !(1 == ~t6_pc~0); 2070705#L502-29 is_transmit6_triggered_~__retres1~6#1 := 0; 2070703#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2070701#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2070699#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 2070697#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2070695#L521-27 assume 1 == ~t7_pc~0; 2070693#L522-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 2070694#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2070831#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2070682#L1023-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 2070680#L1023-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2070678#L869-3 assume !(1 == ~M_E~0); 2027078#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2070676#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2070674#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2070672#L884-3 assume !(1 == ~T4_E~0); 2070670#L889-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2070668#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 2070666#L899-3 assume !(1 == ~T7_E~0); 2070664#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2070662#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2070660#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2070658#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2070656#L924-3 assume !(1 == ~E_4~0); 2070654#L929-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2070652#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 2070651#L939-3 assume 1 == ~E_7~0;~E_7~0 := 2; 2070649#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 2015229#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 2015223#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 2015221#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 2015222#L1209 assume !(0 == start_simulation_~tmp~3#1); 2027030#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 2077737#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 2077730#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 2077728#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 2077726#L1164 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2077724#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2077720#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 2077718#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 2002605#L1190-2 [2022-12-13 11:54:51,194 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 11:54:51,194 INFO L85 PathProgramCache]: Analyzing trace with hash 1628748997, now seen corresponding path program 3 times [2022-12-13 11:54:51,194 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 11:54:51,195 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1232792098] [2022-12-13 11:54:51,195 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 11:54:51,195 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 11:54:51,204 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 11:54:51,204 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 11:54:51,209 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 11:54:51,233 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 11:54:51,234 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 11:54:51,234 INFO L85 PathProgramCache]: Analyzing trace with hash 105499366, now seen corresponding path program 1 times [2022-12-13 11:54:51,234 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 11:54:51,234 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [422997622] [2022-12-13 11:54:51,234 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 11:54:51,234 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 11:54:51,240 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 11:54:51,265 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 11:54:51,265 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 11:54:51,265 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [422997622] [2022-12-13 11:54:51,265 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [422997622] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 11:54:51,265 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 11:54:51,265 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-12-13 11:54:51,265 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [922599675] [2022-12-13 11:54:51,265 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 11:54:51,266 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 11:54:51,266 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 11:54:51,266 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-12-13 11:54:51,266 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-12-13 11:54:51,266 INFO L87 Difference]: Start difference. First operand 98435 states and 136687 transitions. cyclomatic complexity: 38268 Second operand has 5 states, 5 states have (on average 20.8) internal successors, (104), 5 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 11:54:51,693 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 11:54:51,693 INFO L93 Difference]: Finished difference Result 176708 states and 242992 transitions. [2022-12-13 11:54:51,693 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 176708 states and 242992 transitions. [2022-12-13 11:54:52,335 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 175598 [2022-12-13 11:54:52,595 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 176708 states to 176708 states and 242992 transitions. [2022-12-13 11:54:52,595 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 176708 [2022-12-13 11:54:52,648 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 176708 [2022-12-13 11:54:52,648 INFO L73 IsDeterministic]: Start isDeterministic. Operand 176708 states and 242992 transitions. [2022-12-13 11:54:52,698 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 11:54:52,699 INFO L218 hiAutomatonCegarLoop]: Abstraction has 176708 states and 242992 transitions. [2022-12-13 11:54:52,762 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 176708 states and 242992 transitions. [2022-12-13 11:54:53,958 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 176708 to 99083. [2022-12-13 11:54:54,027 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 99083 states, 99083 states have (on average 1.3860601717751784) internal successors, (137335), 99082 states have internal predecessors, (137335), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 11:54:54,339 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 99083 states to 99083 states and 137335 transitions. [2022-12-13 11:54:54,339 INFO L240 hiAutomatonCegarLoop]: Abstraction has 99083 states and 137335 transitions. [2022-12-13 11:54:54,340 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2022-12-13 11:54:54,340 INFO L428 stractBuchiCegarLoop]: Abstraction has 99083 states and 137335 transitions. [2022-12-13 11:54:54,340 INFO L335 stractBuchiCegarLoop]: ======== Iteration 25 ============ [2022-12-13 11:54:54,340 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 99083 states and 137335 transitions. [2022-12-13 11:54:54,524 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 98469 [2022-12-13 11:54:54,524 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 11:54:54,524 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 11:54:54,525 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 11:54:54,525 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 11:54:54,526 INFO L748 eck$LassoCheckResult]: Stem: 2277162#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 2277163#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 2277829#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2277830#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2277934#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 2277302#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2277303#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2277434#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2277435#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 2277208#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 2277002#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 2277003#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 2277167#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2277168#L781 assume !(0 == ~M_E~0); 2277726#L781-2 assume !(0 == ~T1_E~0); 2277953#L786-1 assume !(0 == ~T2_E~0); 2276963#L791-1 assume !(0 == ~T3_E~0); 2276964#L796-1 assume !(0 == ~T4_E~0); 2277528#L801-1 assume !(0 == ~T5_E~0); 2277529#L806-1 assume !(0 == ~T6_E~0); 2277568#L811-1 assume !(0 == ~T7_E~0); 2277173#L816-1 assume !(0 == ~E_M~0); 2277174#L821-1 assume !(0 == ~E_1~0); 2276994#L826-1 assume !(0 == ~E_2~0); 2276995#L831-1 assume !(0 == ~E_3~0); 2277297#L836-1 assume !(0 == ~E_4~0); 2277298#L841-1 assume !(0 == ~E_5~0); 2277128#L846-1 assume !(0 == ~E_6~0); 2277129#L851-1 assume !(0 == ~E_7~0); 2277152#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2277153#L388 assume !(1 == ~m_pc~0); 2277146#L388-2 is_master_triggered_~__retres1~0#1 := 0; 2277147#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2277695#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2277008#L967 assume !(0 != activate_threads_~tmp~1#1); 2277009#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2276942#L407 assume !(1 == ~t1_pc~0); 2276943#L407-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2276946#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2276947#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2276980#L975 assume !(0 != activate_threads_~tmp___0~0#1); 2277822#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2277256#L426 assume !(1 == ~t2_pc~0); 2277257#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2277859#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2277279#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2277280#L983 assume !(0 != activate_threads_~tmp___1~0#1); 2277915#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2277345#L445 assume !(1 == ~t3_pc~0); 2277346#L445-2 is_transmit3_triggered_~__retres1~3#1 := 0; 2277735#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2276940#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2276941#L991 assume !(0 != activate_threads_~tmp___2~0#1); 2277640#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2277599#L464 assume !(1 == ~t4_pc~0); 2277156#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 2277028#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2277029#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2277039#L999 assume !(0 != activate_threads_~tmp___3~0#1); 2277324#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2277325#L483 assume !(1 == ~t5_pc~0); 2277596#L483-2 is_transmit5_triggered_~__retres1~5#1 := 0; 2277799#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2277756#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2277757#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 2277241#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2277242#L502 assume !(1 == ~t6_pc~0); 2277107#L502-2 is_transmit6_triggered_~__retres1~6#1 := 0; 2277067#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2277068#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2277265#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 2277480#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2277775#L521 assume !(1 == ~t7_pc~0); 2277818#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 2277004#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2277005#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2277810#L1023 assume !(0 != activate_threads_~tmp___6~0#1); 2277811#L1023-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2277972#L869 assume !(1 == ~M_E~0); 2277971#L869-2 assume !(1 == ~T1_E~0); 2277909#L874-1 assume !(1 == ~T2_E~0); 2277910#L879-1 assume !(1 == ~T3_E~0); 2277390#L884-1 assume !(1 == ~T4_E~0); 2277391#L889-1 assume !(1 == ~T5_E~0); 2277180#L894-1 assume !(1 == ~T6_E~0); 2277181#L899-1 assume !(1 == ~T7_E~0); 2277970#L904-1 assume !(1 == ~E_M~0); 2277969#L909-1 assume !(1 == ~E_1~0); 2277551#L914-1 assume !(1 == ~E_2~0); 2277552#L919-1 assume !(1 == ~E_3~0); 2277968#L924-1 assume !(1 == ~E_4~0); 2277967#L929-1 assume !(1 == ~E_5~0); 2277966#L934-1 assume !(1 == ~E_6~0); 2277965#L939-1 assume !(1 == ~E_7~0); 2277321#L944-1 assume { :end_inline_reset_delta_events } true; 2277774#L1190-2 [2022-12-13 11:54:54,526 INFO L750 eck$LassoCheckResult]: Loop: 2277774#L1190-2 assume !false; 2336812#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2293567#L756 assume !false; 2293527#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 2293466#L596 assume !(0 == ~m_st~0); 2293462#L600 assume !(0 == ~t1_st~0); 2293463#L604 assume !(0 == ~t2_st~0); 2293465#L608 assume !(0 == ~t3_st~0); 2293460#L612 assume !(0 == ~t4_st~0); 2293461#L616 assume !(0 == ~t5_st~0); 2293464#L620 assume !(0 == ~t6_st~0); 2293457#L624 assume !(0 == ~t7_st~0);exists_runnable_thread_~__retres1~8#1 := 0; 2293459#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 2326059#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 2326045#L653 assume !(0 != eval_~tmp~0#1); 2293440#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2293441#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2293432#L781-3 assume !(0 == ~M_E~0); 2293433#L781-5 assume !(0 == ~T1_E~0); 2293424#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2293425#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2293416#L796-3 assume !(0 == ~T4_E~0); 2293417#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2293408#L806-3 assume !(0 == ~T6_E~0); 2293409#L811-3 assume !(0 == ~T7_E~0); 2293400#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2293401#L821-3 assume !(0 == ~E_1~0); 2293392#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2293393#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2293384#L836-3 assume !(0 == ~E_4~0); 2293385#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2293376#L846-3 assume !(0 == ~E_6~0); 2293377#L851-3 assume !(0 == ~E_7~0); 2293368#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2293369#L388-27 assume !(1 == ~m_pc~0); 2293360#L388-29 is_master_triggered_~__retres1~0#1 := 0; 2293361#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2293352#is_master_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2293353#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2293344#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2293345#L407-27 assume !(1 == ~t1_pc~0); 2293336#L407-29 is_transmit1_triggered_~__retres1~1#1 := 0; 2293337#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2293328#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2293329#L975-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2293320#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2293321#L426-27 assume 1 == ~t2_pc~0; 2293310#L427-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2293309#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2293300#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2293301#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2293292#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2293293#L445-27 assume !(1 == ~t3_pc~0); 2293284#L445-29 is_transmit3_triggered_~__retres1~3#1 := 0; 2293285#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2293276#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2293277#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2293268#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2293269#L464-27 assume !(1 == ~t4_pc~0); 2293258#L464-29 is_transmit4_triggered_~__retres1~4#1 := 0; 2293259#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2293250#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2293251#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 2293242#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2293243#L483-27 assume !(1 == ~t5_pc~0); 2293234#L483-29 is_transmit5_triggered_~__retres1~5#1 := 0; 2293235#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2293226#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2293227#L1007-27 assume !(0 != activate_threads_~tmp___4~0#1); 2293218#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2293219#L502-27 assume !(1 == ~t6_pc~0); 2293210#L502-29 is_transmit6_triggered_~__retres1~6#1 := 0; 2293211#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2293203#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2293201#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 2293198#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2293199#L521-27 assume !(1 == ~t7_pc~0); 2293184#L521-29 is_transmit7_triggered_~__retres1~7#1 := 0; 2293185#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2293172#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2293173#L1023-27 assume !(0 != activate_threads_~tmp___6~0#1); 2293163#L1023-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2293164#L869-3 assume !(1 == ~M_E~0); 2293157#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2293158#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2293149#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2293150#L884-3 assume !(1 == ~T4_E~0); 2293141#L889-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2293142#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 2293133#L899-3 assume !(1 == ~T7_E~0); 2293134#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2293125#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2293126#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2293117#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2293118#L924-3 assume !(1 == ~E_4~0); 2293109#L929-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2293110#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 2293102#L939-3 assume !(1 == ~E_7~0); 2293103#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 2293097#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 2293090#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 2293088#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 2293084#L1209 assume !(0 == start_simulation_~tmp~3#1); 2293085#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 2293593#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 2336828#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 2336826#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 2336824#L1164 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2336822#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2336820#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 2336817#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 2277774#L1190-2 [2022-12-13 11:54:54,526 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 11:54:54,526 INFO L85 PathProgramCache]: Analyzing trace with hash 1628748997, now seen corresponding path program 4 times [2022-12-13 11:54:54,526 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 11:54:54,527 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [508152254] [2022-12-13 11:54:54,527 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 11:54:54,527 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 11:54:54,536 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 11:54:54,537 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 11:54:54,543 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 11:54:54,565 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 11:54:54,565 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 11:54:54,565 INFO L85 PathProgramCache]: Analyzing trace with hash -539655369, now seen corresponding path program 1 times [2022-12-13 11:54:54,565 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 11:54:54,565 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1633236595] [2022-12-13 11:54:54,566 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 11:54:54,566 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 11:54:54,576 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 11:54:54,642 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 11:54:54,642 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 11:54:54,642 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1633236595] [2022-12-13 11:54:54,642 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1633236595] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 11:54:54,642 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 11:54:54,642 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-12-13 11:54:54,642 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1556912828] [2022-12-13 11:54:54,643 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 11:54:54,643 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 11:54:54,643 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 11:54:54,643 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-12-13 11:54:54,643 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-12-13 11:54:54,644 INFO L87 Difference]: Start difference. First operand 99083 states and 137335 transitions. cyclomatic complexity: 38268 Second operand has 5 states, 5 states have (on average 22.2) internal successors, (111), 5 states have internal predecessors, (111), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 11:54:55,132 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 11:54:55,133 INFO L93 Difference]: Finished difference Result 163995 states and 226384 transitions. [2022-12-13 11:54:55,133 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 163995 states and 226384 transitions. [2022-12-13 11:54:55,798 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 163253 [2022-12-13 11:54:56,032 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 163995 states to 163995 states and 226384 transitions. [2022-12-13 11:54:56,032 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 163995 [2022-12-13 11:54:56,084 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 163995 [2022-12-13 11:54:56,084 INFO L73 IsDeterministic]: Start isDeterministic. Operand 163995 states and 226384 transitions. [2022-12-13 11:54:56,132 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 11:54:56,132 INFO L218 hiAutomatonCegarLoop]: Abstraction has 163995 states and 226384 transitions. [2022-12-13 11:54:56,184 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 163995 states and 226384 transitions. [2022-12-13 11:54:57,052 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 163995 to 100427. [2022-12-13 11:54:57,116 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 100427 states, 100427 states have (on average 1.372698577075886) internal successors, (137856), 100426 states have internal predecessors, (137856), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 11:54:57,262 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 100427 states to 100427 states and 137856 transitions. [2022-12-13 11:54:57,262 INFO L240 hiAutomatonCegarLoop]: Abstraction has 100427 states and 137856 transitions. [2022-12-13 11:54:57,263 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-12-13 11:54:57,263 INFO L428 stractBuchiCegarLoop]: Abstraction has 100427 states and 137856 transitions. [2022-12-13 11:54:57,263 INFO L335 stractBuchiCegarLoop]: ======== Iteration 26 ============ [2022-12-13 11:54:57,263 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 100427 states and 137856 transitions. [2022-12-13 11:54:57,523 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 99813 [2022-12-13 11:54:57,523 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 11:54:57,523 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 11:54:57,524 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 11:54:57,524 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 11:54:57,524 INFO L748 eck$LassoCheckResult]: Stem: 2540254#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 2540255#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 2540911#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2540912#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2541012#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 2540396#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2540397#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2540524#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2540525#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 2540301#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 2540093#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 2540094#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 2540259#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2540260#L781 assume !(0 == ~M_E~0); 2540800#L781-2 assume !(0 == ~T1_E~0); 2541031#L786-1 assume !(0 == ~T2_E~0); 2540054#L791-1 assume !(0 == ~T3_E~0); 2540055#L796-1 assume !(0 == ~T4_E~0); 2540605#L801-1 assume !(0 == ~T5_E~0); 2540606#L806-1 assume !(0 == ~T6_E~0); 2540646#L811-1 assume !(0 == ~T7_E~0); 2540265#L816-1 assume !(0 == ~E_M~0); 2540266#L821-1 assume !(0 == ~E_1~0); 2540085#L826-1 assume !(0 == ~E_2~0); 2540086#L831-1 assume !(0 == ~E_3~0); 2540391#L836-1 assume !(0 == ~E_4~0); 2540392#L841-1 assume !(0 == ~E_5~0); 2540219#L846-1 assume !(0 == ~E_6~0); 2540220#L851-1 assume !(0 == ~E_7~0); 2540243#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2540244#L388 assume !(1 == ~m_pc~0); 2540237#L388-2 is_master_triggered_~__retres1~0#1 := 0; 2540238#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2540769#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2540099#L967 assume !(0 != activate_threads_~tmp~1#1); 2540100#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2540033#L407 assume !(1 == ~t1_pc~0); 2540034#L407-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2540037#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2540038#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2540071#L975 assume !(0 != activate_threads_~tmp___0~0#1); 2540906#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2540349#L426 assume !(1 == ~t2_pc~0); 2540350#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2540939#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2540372#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2540373#L983 assume !(0 != activate_threads_~tmp___1~0#1); 2540990#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2540439#L445 assume !(1 == ~t3_pc~0); 2540440#L445-2 is_transmit3_triggered_~__retres1~3#1 := 0; 2540812#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2540031#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2540032#L991 assume !(0 != activate_threads_~tmp___2~0#1); 2540718#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2540678#L464 assume !(1 == ~t4_pc~0); 2540247#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 2540119#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2540120#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2540130#L999 assume !(0 != activate_threads_~tmp___3~0#1); 2540417#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2540418#L483 assume !(1 == ~t5_pc~0); 2540674#L483-2 is_transmit5_triggered_~__retres1~5#1 := 0; 2540878#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2540834#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2540835#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 2540334#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2540335#L502 assume !(1 == ~t6_pc~0); 2540195#L502-2 is_transmit6_triggered_~__retres1~6#1 := 0; 2540157#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2540158#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2540359#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 2540562#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2540850#L521 assume !(1 == ~t7_pc~0); 2540902#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 2540095#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2540096#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2540892#L1023 assume !(0 != activate_threads_~tmp___6~0#1); 2540893#L1023-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2541054#L869 assume !(1 == ~M_E~0); 2541053#L869-2 assume !(1 == ~T1_E~0); 2540985#L874-1 assume !(1 == ~T2_E~0); 2540986#L879-1 assume !(1 == ~T3_E~0); 2540484#L884-1 assume !(1 == ~T4_E~0); 2540485#L889-1 assume !(1 == ~T5_E~0); 2540272#L894-1 assume !(1 == ~T6_E~0); 2540273#L899-1 assume !(1 == ~T7_E~0); 2541052#L904-1 assume !(1 == ~E_M~0); 2541051#L909-1 assume !(1 == ~E_1~0); 2540625#L914-1 assume !(1 == ~E_2~0); 2540626#L919-1 assume !(1 == ~E_3~0); 2541050#L924-1 assume !(1 == ~E_4~0); 2541049#L929-1 assume !(1 == ~E_5~0); 2541048#L934-1 assume !(1 == ~E_6~0); 2541047#L939-1 assume !(1 == ~E_7~0); 2540414#L944-1 assume { :end_inline_reset_delta_events } true; 2540849#L1190-2 [2022-12-13 11:54:57,524 INFO L750 eck$LassoCheckResult]: Loop: 2540849#L1190-2 assume !false; 2593932#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2554391#L756 assume !false; 2593928#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 2593926#L596 assume !(0 == ~m_st~0); 2593922#L600 assume !(0 == ~t1_st~0); 2593923#L604 assume !(0 == ~t2_st~0); 2593925#L608 assume !(0 == ~t3_st~0); 2593920#L612 assume !(0 == ~t4_st~0); 2593921#L616 assume !(0 == ~t5_st~0); 2593924#L620 assume !(0 == ~t6_st~0); 2593919#L624 assume !(0 == ~t7_st~0);exists_runnable_thread_~__retres1~8#1 := 0; 2555867#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 2555868#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 2568402#L653 assume !(0 != eval_~tmp~0#1); 2593911#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2595926#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2595925#L781-3 assume !(0 == ~M_E~0); 2595924#L781-5 assume !(0 == ~T1_E~0); 2595923#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2595922#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2595921#L796-3 assume !(0 == ~T4_E~0); 2595920#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2595919#L806-3 assume !(0 == ~T6_E~0); 2595918#L811-3 assume !(0 == ~T7_E~0); 2595917#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2595916#L821-3 assume !(0 == ~E_1~0); 2595915#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2595914#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2595913#L836-3 assume !(0 == ~E_4~0); 2595912#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2595911#L846-3 assume !(0 == ~E_6~0); 2595910#L851-3 assume !(0 == ~E_7~0); 2595909#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2595908#L388-27 assume !(1 == ~m_pc~0); 2595907#L388-29 is_master_triggered_~__retres1~0#1 := 0; 2595906#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2595905#is_master_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2595904#L967-27 assume !(0 != activate_threads_~tmp~1#1); 2595903#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2595902#L407-27 assume !(1 == ~t1_pc~0); 2595901#L407-29 is_transmit1_triggered_~__retres1~1#1 := 0; 2595900#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2595899#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2595898#L975-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2595897#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2595896#L426-27 assume 1 == ~t2_pc~0; 2595895#L427-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2595893#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2595892#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2595891#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2595890#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2595889#L445-27 assume !(1 == ~t3_pc~0); 2595888#L445-29 is_transmit3_triggered_~__retres1~3#1 := 0; 2595887#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2595886#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2595885#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2595884#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2595883#L464-27 assume !(1 == ~t4_pc~0); 2595881#L464-29 is_transmit4_triggered_~__retres1~4#1 := 0; 2595880#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2595879#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2595878#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 2595877#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2595876#L483-27 assume !(1 == ~t5_pc~0); 2595875#L483-29 is_transmit5_triggered_~__retres1~5#1 := 0; 2595874#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2595873#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2595872#L1007-27 assume !(0 != activate_threads_~tmp___4~0#1); 2595871#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2595870#L502-27 assume !(1 == ~t6_pc~0); 2595869#L502-29 is_transmit6_triggered_~__retres1~6#1 := 0; 2595868#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2595867#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2595866#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 2554985#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2554986#L521-27 assume 1 == ~t7_pc~0; 2591471#L522-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 2555244#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2591511#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2555098#L1023-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 2555099#L1023-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2568603#L869-3 assume !(1 == ~M_E~0); 2555044#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2555038#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2555035#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2555036#L884-3 assume !(1 == ~T4_E~0); 2555028#L889-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2555029#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 2554919#L899-3 assume !(1 == ~T7_E~0); 2554920#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2554899#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2554900#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2554879#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2554880#L924-3 assume !(1 == ~E_4~0); 2554860#L929-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2554861#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 2554847#L939-3 assume 1 == ~E_7~0;~E_7~0 := 2; 2554846#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 2568571#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 2578801#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 2578800#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 2578798#L1209 assume !(0 == start_simulation_~tmp~3#1); 2578799#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 2593969#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 2593962#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 2593960#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 2593958#L1164 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2593956#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2593954#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 2593952#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 2540849#L1190-2 [2022-12-13 11:54:57,525 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 11:54:57,525 INFO L85 PathProgramCache]: Analyzing trace with hash 1628748997, now seen corresponding path program 5 times [2022-12-13 11:54:57,525 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 11:54:57,525 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [497818105] [2022-12-13 11:54:57,525 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 11:54:57,525 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 11:54:57,534 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 11:54:57,534 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 11:54:57,539 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 11:54:57,551 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 11:54:57,552 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 11:54:57,552 INFO L85 PathProgramCache]: Analyzing trace with hash 1102337656, now seen corresponding path program 1 times [2022-12-13 11:54:57,552 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 11:54:57,552 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1239203038] [2022-12-13 11:54:57,552 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 11:54:57,552 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 11:54:57,559 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 11:54:57,580 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 11:54:57,580 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 11:54:57,580 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1239203038] [2022-12-13 11:54:57,580 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1239203038] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 11:54:57,580 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 11:54:57,580 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 11:54:57,580 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [127792053] [2022-12-13 11:54:57,580 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 11:54:57,581 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 11:54:57,581 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 11:54:57,581 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 11:54:57,581 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 11:54:57,581 INFO L87 Difference]: Start difference. First operand 100427 states and 137856 transitions. cyclomatic complexity: 37445 Second operand has 3 states, 3 states have (on average 37.0) internal successors, (111), 3 states have internal predecessors, (111), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 11:54:58,122 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 11:54:58,122 INFO L93 Difference]: Finished difference Result 152921 states and 207398 transitions. [2022-12-13 11:54:58,122 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 152921 states and 207398 transitions. [2022-12-13 11:54:58,736 INFO L131 ngComponentsAnalysis]: Automaton has 38 accepting balls. 152305 [2022-12-13 11:54:59,101 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 152921 states to 152921 states and 207398 transitions. [2022-12-13 11:54:59,101 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 152921 [2022-12-13 11:54:59,178 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 152921 [2022-12-13 11:54:59,178 INFO L73 IsDeterministic]: Start isDeterministic. Operand 152921 states and 207398 transitions. [2022-12-13 11:54:59,406 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 11:54:59,406 INFO L218 hiAutomatonCegarLoop]: Abstraction has 152921 states and 207398 transitions. [2022-12-13 11:54:59,446 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 152921 states and 207398 transitions. [2022-12-13 11:55:00,399 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 152921 to 149689. [2022-12-13 11:55:00,482 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 149689 states, 149689 states have (on average 1.3575212607472826) internal successors, (203206), 149688 states have internal predecessors, (203206), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 11:55:00,688 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 149689 states to 149689 states and 203206 transitions. [2022-12-13 11:55:00,689 INFO L240 hiAutomatonCegarLoop]: Abstraction has 149689 states and 203206 transitions. [2022-12-13 11:55:00,689 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 11:55:00,690 INFO L428 stractBuchiCegarLoop]: Abstraction has 149689 states and 203206 transitions. [2022-12-13 11:55:00,690 INFO L335 stractBuchiCegarLoop]: ======== Iteration 27 ============ [2022-12-13 11:55:00,690 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 149689 states and 203206 transitions. [2022-12-13 11:55:01,065 INFO L131 ngComponentsAnalysis]: Automaton has 38 accepting balls. 149073 [2022-12-13 11:55:01,066 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 11:55:01,066 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 11:55:01,066 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 11:55:01,066 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 11:55:01,067 INFO L748 eck$LassoCheckResult]: Stem: 2793605#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 2793606#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 2794291#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2794292#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2794406#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 2793756#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2793757#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2793895#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2793896#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 2793652#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 2793448#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 2793449#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 2793611#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2793612#L781 assume !(0 == ~M_E~0); 2794176#L781-2 assume !(0 == ~T1_E~0); 2794424#L786-1 assume !(0 == ~T2_E~0); 2793408#L791-1 assume !(0 == ~T3_E~0); 2793409#L796-1 assume !(0 == ~T4_E~0); 2793982#L801-1 assume !(0 == ~T5_E~0); 2793983#L806-1 assume !(0 == ~T6_E~0); 2794022#L811-1 assume !(0 == ~T7_E~0); 2793617#L816-1 assume !(0 == ~E_M~0); 2793618#L821-1 assume !(0 == ~E_1~0); 2793440#L826-1 assume !(0 == ~E_2~0); 2793441#L831-1 assume !(0 == ~E_3~0); 2793751#L836-1 assume !(0 == ~E_4~0); 2793752#L841-1 assume !(0 == ~E_5~0); 2793572#L846-1 assume !(0 == ~E_6~0); 2793573#L851-1 assume !(0 == ~E_7~0); 2793595#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2793596#L388 assume !(1 == ~m_pc~0); 2793589#L388-2 is_master_triggered_~__retres1~0#1 := 0; 2793590#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2794148#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2793454#L967 assume !(0 != activate_threads_~tmp~1#1); 2793455#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2793387#L407 assume !(1 == ~t1_pc~0); 2793388#L407-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2793391#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2793392#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2793425#L975 assume !(0 != activate_threads_~tmp___0~0#1); 2794286#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2793702#L426 assume !(1 == ~t2_pc~0); 2793703#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2794325#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2793726#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2793727#L983 assume !(0 != activate_threads_~tmp___1~0#1); 2794387#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2793807#L445 assume !(1 == ~t3_pc~0); 2793808#L445-2 is_transmit3_triggered_~__retres1~3#1 := 0; 2794187#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2793385#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2793386#L991 assume !(0 != activate_threads_~tmp___2~0#1); 2794094#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2794054#L464 assume !(1 == ~t4_pc~0); 2793599#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 2793474#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2793475#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2793485#L999 assume !(0 != activate_threads_~tmp___3~0#1); 2793781#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2793782#L483 assume !(1 == ~t5_pc~0); 2794050#L483-2 is_transmit5_triggered_~__retres1~5#1 := 0; 2794257#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2794211#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2794212#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 2793686#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2793687#L502 assume !(1 == ~t6_pc~0); 2793551#L502-2 is_transmit6_triggered_~__retres1~6#1 := 0; 2793512#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2793513#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2793712#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 2793937#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2794230#L521 assume !(1 == ~t7_pc~0); 2794282#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 2793450#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2793451#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2794270#L1023 assume !(0 != activate_threads_~tmp___6~0#1); 2794271#L1023-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2794446#L869 assume !(1 == ~M_E~0); 2794445#L869-2 assume !(1 == ~T1_E~0); 2794379#L874-1 assume !(1 == ~T2_E~0); 2794380#L879-1 assume !(1 == ~T3_E~0); 2793854#L884-1 assume !(1 == ~T4_E~0); 2793855#L889-1 assume !(1 == ~T5_E~0); 2793624#L894-1 assume !(1 == ~T6_E~0); 2793625#L899-1 assume !(1 == ~T7_E~0); 2794444#L904-1 assume !(1 == ~E_M~0); 2794443#L909-1 assume !(1 == ~E_1~0); 2794003#L914-1 assume !(1 == ~E_2~0); 2794004#L919-1 assume !(1 == ~E_3~0); 2794442#L924-1 assume !(1 == ~E_4~0); 2794441#L929-1 assume !(1 == ~E_5~0); 2794440#L934-1 assume !(1 == ~E_6~0); 2794439#L939-1 assume !(1 == ~E_7~0); 2793778#L944-1 assume { :end_inline_reset_delta_events } true; 2794229#L1190-2 assume !false; 2807138#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2807139#L756 [2022-12-13 11:55:01,067 INFO L750 eck$LassoCheckResult]: Loop: 2807139#L756 assume !false; 2862980#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 2862978#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 2862977#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 2862976#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 2862975#L653 assume 0 != eval_~tmp~0#1; 2862973#L653-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 2862972#L661 assume !(0 != eval_~tmp_ndt_1~0#1); 2862971#L658 assume !(0 == ~t1_st~0); 2862968#L672 assume !(0 == ~t2_st~0); 2862962#L686 assume !(0 == ~t3_st~0); 2862961#L700 assume !(0 == ~t4_st~0); 2862957#L714 assume !(0 == ~t5_st~0); 2807087#L728 assume !(0 == ~t6_st~0); 2798488#L742 assume !(0 == ~t7_st~0); 2807139#L756 [2022-12-13 11:55:01,067 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 11:55:01,067 INFO L85 PathProgramCache]: Analyzing trace with hash 1859704647, now seen corresponding path program 1 times [2022-12-13 11:55:01,068 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 11:55:01,068 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [772071612] [2022-12-13 11:55:01,068 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 11:55:01,068 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 11:55:01,075 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 11:55:01,075 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 11:55:01,080 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 11:55:01,093 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 11:55:01,093 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 11:55:01,093 INFO L85 PathProgramCache]: Analyzing trace with hash -1020995678, now seen corresponding path program 1 times [2022-12-13 11:55:01,093 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 11:55:01,093 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [125017737] [2022-12-13 11:55:01,093 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 11:55:01,094 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 11:55:01,096 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 11:55:01,096 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 11:55:01,098 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 11:55:01,100 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 11:55:01,100 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 11:55:01,101 INFO L85 PathProgramCache]: Analyzing trace with hash -125449316, now seen corresponding path program 1 times [2022-12-13 11:55:01,101 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 11:55:01,101 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1017201044] [2022-12-13 11:55:01,101 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 11:55:01,101 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 11:55:01,108 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 11:55:01,128 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 11:55:01,128 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 11:55:01,128 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1017201044] [2022-12-13 11:55:01,128 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1017201044] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 11:55:01,128 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 11:55:01,128 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 11:55:01,129 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [360985980] [2022-12-13 11:55:01,129 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 11:55:01,205 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 11:55:01,205 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 11:55:01,205 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 11:55:01,205 INFO L87 Difference]: Start difference. First operand 149689 states and 203206 transitions. cyclomatic complexity: 53555 Second operand has 3 states, 3 states have (on average 37.333333333333336) internal successors, (112), 3 states have internal predecessors, (112), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 11:55:01,965 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 11:55:01,965 INFO L93 Difference]: Finished difference Result 286064 states and 385477 transitions. [2022-12-13 11:55:01,965 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 286064 states and 385477 transitions. [2022-12-13 11:55:03,201 INFO L131 ngComponentsAnalysis]: Automaton has 74 accepting balls. 277821 [2022-12-13 11:55:03,854 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 286064 states to 286064 states and 385477 transitions. [2022-12-13 11:55:03,854 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 286064 [2022-12-13 11:55:03,984 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 286064 [2022-12-13 11:55:03,984 INFO L73 IsDeterministic]: Start isDeterministic. Operand 286064 states and 385477 transitions. [2022-12-13 11:55:04,257 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 11:55:04,257 INFO L218 hiAutomatonCegarLoop]: Abstraction has 286064 states and 385477 transitions. [2022-12-13 11:55:04,330 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 286064 states and 385477 transitions. [2022-12-13 11:55:06,163 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 286064 to 280396. [2022-12-13 11:55:06,282 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 280396 states, 280396 states have (on average 1.3490527682277922) internal successors, (378269), 280395 states have internal predecessors, (378269), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 11:55:06,699 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 280396 states to 280396 states and 378269 transitions. [2022-12-13 11:55:06,699 INFO L240 hiAutomatonCegarLoop]: Abstraction has 280396 states and 378269 transitions. [2022-12-13 11:55:06,700 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 11:55:06,700 INFO L428 stractBuchiCegarLoop]: Abstraction has 280396 states and 378269 transitions. [2022-12-13 11:55:06,700 INFO L335 stractBuchiCegarLoop]: ======== Iteration 28 ============ [2022-12-13 11:55:06,700 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 280396 states and 378269 transitions. [2022-12-13 11:55:07,645 INFO L131 ngComponentsAnalysis]: Automaton has 74 accepting balls. 272153 [2022-12-13 11:55:07,645 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 11:55:07,645 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 11:55:07,646 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 11:55:07,646 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 11:55:07,646 INFO L748 eck$LassoCheckResult]: Stem: 3229368#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 3229369#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 3230081#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3230082#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3230228#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 3229511#L548-2 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 3229512#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3229645#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3229646#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 3229414#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 3229415#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 3230233#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 3230234#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3229958#L781 assume !(0 == ~M_E~0); 3229959#L781-2 assume !(0 == ~T1_E~0); 3230283#L786-1 assume !(0 == ~T2_E~0); 3230284#L791-1 assume !(0 == ~T3_E~0); 3229787#L796-1 assume !(0 == ~T4_E~0); 3229788#L801-1 assume !(0 == ~T5_E~0); 3229790#L806-1 assume !(0 == ~T6_E~0); 3229791#L811-1 assume !(0 == ~T7_E~0); 3229379#L816-1 assume !(0 == ~E_M~0); 3229380#L821-1 assume !(0 == ~E_1~0); 3229201#L826-1 assume !(0 == ~E_2~0); 3229202#L831-1 assume !(0 == ~E_3~0); 3229506#L836-1 assume !(0 == ~E_4~0); 3229507#L841-1 assume !(0 == ~E_5~0); 3229334#L846-1 assume !(0 == ~E_6~0); 3229335#L851-1 assume !(0 == ~E_7~0); 3229357#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3229358#L388 assume !(1 == ~m_pc~0); 3229351#L388-2 is_master_triggered_~__retres1~0#1 := 0; 3229352#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3229996#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3229997#L967 assume !(0 != activate_threads_~tmp~1#1); 3230215#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3230216#L407 assume !(1 == ~t1_pc~0); 3230225#L407-2 is_transmit1_triggered_~__retres1~1#1 := 0; 3230226#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3229188#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3229189#L975 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3230075#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3229465#L426 assume !(1 == ~t2_pc~0); 3229466#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 3230203#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3230204#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3230195#L983 assume !(0 != activate_threads_~tmp___1~0#1); 3230196#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3229560#L445 assume !(1 == ~t3_pc~0); 3229561#L445-2 is_transmit3_triggered_~__retres1~3#1 := 0; 3229972#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3229973#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3229871#L991 assume !(0 != activate_threads_~tmp___2~0#1); 3229872#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3229829#L464 assume !(1 == ~t4_pc~0); 3229830#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 3229235#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3229236#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3230281#L999 assume !(0 != activate_threads_~tmp___3~0#1); 3230282#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3229825#L483 assume !(1 == ~t5_pc~0); 3229826#L483-2 is_transmit5_triggered_~__retres1~5#1 := 0; 3230049#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3230050#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3230152#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 3230153#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3229901#L502 assume !(1 == ~t6_pc~0); 3229902#L502-2 is_transmit6_triggered_~__retres1~6#1 := 0; 3229274#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3229275#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3229691#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 3229692#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3230160#L521 assume !(1 == ~t7_pc~0); 3230161#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 3229211#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3229212#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3230062#L1023 assume !(0 != activate_threads_~tmp___6~0#1); 3230063#L1023-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3230327#L869 assume !(1 == ~M_E~0); 3230328#L869-2 assume !(1 == ~T1_E~0); 3230188#L874-1 assume !(1 == ~T2_E~0); 3230189#L879-1 assume !(1 == ~T3_E~0); 3229607#L884-1 assume !(1 == ~T4_E~0); 3229608#L889-1 assume !(1 == ~T5_E~0); 3229389#L894-1 assume !(1 == ~T6_E~0); 3229390#L899-1 assume !(1 == ~T7_E~0); 3230311#L904-1 assume !(1 == ~E_M~0); 3230312#L909-1 assume !(1 == ~E_1~0); 3229771#L914-1 assume !(1 == ~E_2~0); 3229772#L919-1 assume !(1 == ~E_3~0); 3230297#L924-1 assume !(1 == ~E_4~0); 3230298#L929-1 assume !(1 == ~E_5~0); 3230293#L934-1 assume !(1 == ~E_6~0); 3230294#L939-1 assume !(1 == ~E_7~0); 3230021#L944-1 assume { :end_inline_reset_delta_events } true; 3230022#L1190-2 assume !false; 3247129#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3247130#L756 [2022-12-13 11:55:07,646 INFO L750 eck$LassoCheckResult]: Loop: 3247130#L756 assume !false; 3418616#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 3418614#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 3418610#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 3418608#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 3418606#L653 assume 0 != eval_~tmp~0#1; 3418604#L653-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 3418602#L661 assume !(0 != eval_~tmp_ndt_1~0#1); 3418600#L658 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 3246314#L675 assume !(0 != eval_~tmp_ndt_2~0#1); 3418598#L672 assume !(0 == ~t2_st~0); 3418593#L686 assume !(0 == ~t3_st~0); 3418591#L700 assume !(0 == ~t4_st~0); 3418626#L714 assume !(0 == ~t5_st~0); 3418623#L728 assume !(0 == ~t6_st~0); 3247145#L742 assume !(0 == ~t7_st~0); 3247130#L756 [2022-12-13 11:55:07,646 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 11:55:07,647 INFO L85 PathProgramCache]: Analyzing trace with hash 570287107, now seen corresponding path program 1 times [2022-12-13 11:55:07,647 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 11:55:07,647 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2047356979] [2022-12-13 11:55:07,647 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 11:55:07,647 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 11:55:07,656 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 11:55:07,675 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 11:55:07,675 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 11:55:07,675 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2047356979] [2022-12-13 11:55:07,675 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2047356979] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 11:55:07,675 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 11:55:07,676 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 11:55:07,676 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [62509026] [2022-12-13 11:55:07,676 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 11:55:07,676 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 11:55:07,677 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 11:55:07,677 INFO L85 PathProgramCache]: Analyzing trace with hash 221333240, now seen corresponding path program 1 times [2022-12-13 11:55:07,677 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 11:55:07,677 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [8189516] [2022-12-13 11:55:07,677 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 11:55:07,677 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 11:55:07,681 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 11:55:07,681 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 11:55:07,683 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 11:55:07,685 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 11:55:07,772 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 11:55:07,772 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 11:55:07,773 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 11:55:07,773 INFO L87 Difference]: Start difference. First operand 280396 states and 378269 transitions. cyclomatic complexity: 97947 Second operand has 3 states, 3 states have (on average 32.333333333333336) internal successors, (97), 3 states have internal predecessors, (97), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 11:55:08,455 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 11:55:08,455 INFO L93 Difference]: Finished difference Result 224408 states and 302970 transitions. [2022-12-13 11:55:08,455 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 224408 states and 302970 transitions. [2022-12-13 11:55:09,411 INFO L131 ngComponentsAnalysis]: Automaton has 42 accepting balls. 223460 [2022-12-13 11:55:09,871 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 224408 states to 224408 states and 302970 transitions. [2022-12-13 11:55:09,871 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 224408 [2022-12-13 11:55:09,992 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 224408 [2022-12-13 11:55:09,992 INFO L73 IsDeterministic]: Start isDeterministic. Operand 224408 states and 302970 transitions. [2022-12-13 11:55:10,074 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 11:55:10,075 INFO L218 hiAutomatonCegarLoop]: Abstraction has 224408 states and 302970 transitions. [2022-12-13 11:55:10,178 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 224408 states and 302970 transitions. [2022-12-13 11:55:11,815 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 224408 to 224408. [2022-12-13 11:55:11,950 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 224408 states, 224408 states have (on average 1.350085558447114) internal successors, (302970), 224407 states have internal predecessors, (302970), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 11:55:12,285 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 224408 states to 224408 states and 302970 transitions. [2022-12-13 11:55:12,285 INFO L240 hiAutomatonCegarLoop]: Abstraction has 224408 states and 302970 transitions. [2022-12-13 11:55:12,286 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 11:55:12,286 INFO L428 stractBuchiCegarLoop]: Abstraction has 224408 states and 302970 transitions. [2022-12-13 11:55:12,286 INFO L335 stractBuchiCegarLoop]: ======== Iteration 29 ============ [2022-12-13 11:55:12,286 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 224408 states and 302970 transitions. [2022-12-13 11:55:12,898 INFO L131 ngComponentsAnalysis]: Automaton has 42 accepting balls. 223460 [2022-12-13 11:55:12,898 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 11:55:12,898 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 11:55:12,899 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 11:55:12,899 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 11:55:12,899 INFO L748 eck$LassoCheckResult]: Stem: 3734175#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 3734176#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 3734846#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3734847#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3734966#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 3734318#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3734319#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3734457#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3734458#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 3734221#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 3734018#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 3734019#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 3734180#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3734181#L781 assume !(0 == ~M_E~0); 3734732#L781-2 assume !(0 == ~T1_E~0); 3734997#L786-1 assume !(0 == ~T2_E~0); 3733982#L791-1 assume !(0 == ~T3_E~0); 3733983#L796-1 assume !(0 == ~T4_E~0); 3734542#L801-1 assume !(0 == ~T5_E~0); 3734543#L806-1 assume !(0 == ~T6_E~0); 3734581#L811-1 assume !(0 == ~T7_E~0); 3734186#L816-1 assume !(0 == ~E_M~0); 3734187#L821-1 assume !(0 == ~E_1~0); 3734010#L826-1 assume !(0 == ~E_2~0); 3734011#L831-1 assume !(0 == ~E_3~0); 3734313#L836-1 assume !(0 == ~E_4~0); 3734314#L841-1 assume !(0 == ~E_5~0); 3734142#L846-1 assume !(0 == ~E_6~0); 3734143#L851-1 assume !(0 == ~E_7~0); 3734165#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3734166#L388 assume !(1 == ~m_pc~0); 3734159#L388-2 is_master_triggered_~__retres1~0#1 := 0; 3734160#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3734702#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3734024#L967 assume !(0 != activate_threads_~tmp~1#1); 3734025#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3733958#L407 assume !(1 == ~t1_pc~0); 3733959#L407-2 is_transmit1_triggered_~__retres1~1#1 := 0; 3733965#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3733966#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3733998#L975 assume !(0 != activate_threads_~tmp___0~0#1); 3734842#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3734270#L426 assume !(1 == ~t2_pc~0); 3734271#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 3734881#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3734291#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3734292#L983 assume !(0 != activate_threads_~tmp___1~0#1); 3734945#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3734365#L445 assume !(1 == ~t3_pc~0); 3734366#L445-2 is_transmit3_triggered_~__retres1~3#1 := 0; 3734742#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3733956#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3733957#L991 assume !(0 != activate_threads_~tmp___2~0#1); 3734654#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3734616#L464 assume !(1 == ~t4_pc~0); 3734169#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 3734044#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3734045#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3734057#L999 assume !(0 != activate_threads_~tmp___3~0#1); 3734341#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3734342#L483 assume !(1 == ~t5_pc~0); 3734613#L483-2 is_transmit5_triggered_~__retres1~5#1 := 0; 3734818#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3734768#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3734769#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 3734256#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3734257#L502 assume !(1 == ~t6_pc~0); 3734120#L502-2 is_transmit6_triggered_~__retres1~6#1 := 0; 3734082#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3734083#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3734279#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 3734498#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3734785#L521 assume !(1 == ~t7_pc~0); 3734837#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 3734020#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3734021#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3734829#L1023 assume !(0 != activate_threads_~tmp___6~0#1); 3734830#L1023-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3735018#L869 assume !(1 == ~M_E~0); 3735017#L869-2 assume !(1 == ~T1_E~0); 3734936#L874-1 assume !(1 == ~T2_E~0); 3734937#L879-1 assume !(1 == ~T3_E~0); 3734416#L884-1 assume !(1 == ~T4_E~0); 3734417#L889-1 assume !(1 == ~T5_E~0); 3734196#L894-1 assume !(1 == ~T6_E~0); 3734197#L899-1 assume !(1 == ~T7_E~0); 3735016#L904-1 assume !(1 == ~E_M~0); 3735015#L909-1 assume !(1 == ~E_1~0); 3734563#L914-1 assume !(1 == ~E_2~0); 3734564#L919-1 assume !(1 == ~E_3~0); 3735014#L924-1 assume !(1 == ~E_4~0); 3735013#L929-1 assume !(1 == ~E_5~0); 3735012#L934-1 assume !(1 == ~E_6~0); 3735011#L939-1 assume !(1 == ~E_7~0); 3734340#L944-1 assume { :end_inline_reset_delta_events } true; 3734784#L1190-2 assume !false; 3754239#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3754240#L756 [2022-12-13 11:55:12,899 INFO L750 eck$LassoCheckResult]: Loop: 3754240#L756 assume !false; 3905105#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 3905103#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 3905101#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 3905099#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 3905097#L653 assume 0 != eval_~tmp~0#1; 3905096#L653-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 3754212#L661 assume !(0 != eval_~tmp_ndt_1~0#1); 3754214#L658 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 3794530#L675 assume !(0 != eval_~tmp_ndt_2~0#1); 3794531#L672 assume !(0 == ~t2_st~0); 3884922#L686 assume !(0 == ~t3_st~0); 3753954#L700 assume !(0 == ~t4_st~0); 3753952#L714 assume !(0 == ~t5_st~0); 3904262#L728 assume !(0 == ~t6_st~0); 3875054#L742 assume !(0 == ~t7_st~0); 3754240#L756 [2022-12-13 11:55:12,900 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 11:55:12,900 INFO L85 PathProgramCache]: Analyzing trace with hash 1859704647, now seen corresponding path program 2 times [2022-12-13 11:55:12,900 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 11:55:12,900 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [781699727] [2022-12-13 11:55:12,900 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 11:55:12,900 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 11:55:12,906 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 11:55:12,906 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 11:55:12,910 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 11:55:12,922 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 11:55:12,922 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 11:55:12,923 INFO L85 PathProgramCache]: Analyzing trace with hash 221333240, now seen corresponding path program 2 times [2022-12-13 11:55:12,923 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 11:55:12,923 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [776084172] [2022-12-13 11:55:12,923 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 11:55:12,923 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 11:55:12,925 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 11:55:12,925 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 11:55:12,926 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 11:55:12,927 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 11:55:12,928 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 11:55:12,928 INFO L85 PathProgramCache]: Analyzing trace with hash -2081500610, now seen corresponding path program 1 times [2022-12-13 11:55:12,928 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 11:55:12,928 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [964704146] [2022-12-13 11:55:12,928 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 11:55:12,928 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 11:55:12,934 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 11:55:12,951 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 11:55:12,951 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 11:55:12,951 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [964704146] [2022-12-13 11:55:12,951 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [964704146] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 11:55:12,951 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 11:55:12,951 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 11:55:12,951 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [585396410] [2022-12-13 11:55:12,951 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 11:55:13,036 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 11:55:13,037 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 11:55:13,037 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 11:55:13,037 INFO L87 Difference]: Start difference. First operand 224408 states and 302970 transitions. cyclomatic complexity: 78604 Second operand has 3 states, 3 states have (on average 37.666666666666664) internal successors, (113), 3 states have internal predecessors, (113), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 11:55:14,275 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 11:55:14,275 INFO L93 Difference]: Finished difference Result 424512 states and 570686 transitions. [2022-12-13 11:55:14,275 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 424512 states and 570686 transitions. [2022-12-13 11:55:16,084 INFO L131 ngComponentsAnalysis]: Automaton has 42 accepting balls. 422736 [2022-12-13 11:55:16,989 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 424512 states to 424512 states and 570686 transitions. [2022-12-13 11:55:16,989 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 424512 [2022-12-13 11:55:17,099 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 424512 [2022-12-13 11:55:17,099 INFO L73 IsDeterministic]: Start isDeterministic. Operand 424512 states and 570686 transitions. [2022-12-13 11:55:17,197 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 11:55:17,197 INFO L218 hiAutomatonCegarLoop]: Abstraction has 424512 states and 570686 transitions. [2022-12-13 11:55:17,321 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 424512 states and 570686 transitions. [2022-12-13 11:55:20,170 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 424512 to 402528. [2022-12-13 11:55:20,419 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 402528 states, 402528 states have (on average 1.3498638604022577) internal successors, (543358), 402527 states have internal predecessors, (543358), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 11:55:21,318 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 402528 states to 402528 states and 543358 transitions. [2022-12-13 11:55:21,319 INFO L240 hiAutomatonCegarLoop]: Abstraction has 402528 states and 543358 transitions. [2022-12-13 11:55:21,319 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 11:55:21,320 INFO L428 stractBuchiCegarLoop]: Abstraction has 402528 states and 543358 transitions. [2022-12-13 11:55:21,320 INFO L335 stractBuchiCegarLoop]: ======== Iteration 30 ============ [2022-12-13 11:55:21,321 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 402528 states and 543358 transitions. [2022-12-13 11:55:22,497 INFO L131 ngComponentsAnalysis]: Automaton has 42 accepting balls. 400752 [2022-12-13 11:55:22,497 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 11:55:22,497 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 11:55:22,498 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 11:55:22,498 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 11:55:22,498 INFO L748 eck$LassoCheckResult]: Stem: 4383104#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 4383105#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 4383804#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4383805#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4383941#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 4383249#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4383250#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4383389#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 4383390#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 4383150#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 4382945#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 4382946#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 4383111#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4383112#L781 assume !(0 == ~M_E~0); 4383674#L781-2 assume !(0 == ~T1_E~0); 4383969#L786-1 assume !(0 == ~T2_E~0); 4382909#L791-1 assume !(0 == ~T3_E~0); 4382910#L796-1 assume !(0 == ~T4_E~0); 4383478#L801-1 assume !(0 == ~T5_E~0); 4383479#L806-1 assume !(0 == ~T6_E~0); 4383515#L811-1 assume !(0 == ~T7_E~0); 4383115#L816-1 assume !(0 == ~E_M~0); 4383116#L821-1 assume !(0 == ~E_1~0); 4382937#L826-1 assume !(0 == ~E_2~0); 4382938#L831-1 assume !(0 == ~E_3~0); 4383244#L836-1 assume !(0 == ~E_4~0); 4383245#L841-1 assume !(0 == ~E_5~0); 4383069#L846-1 assume !(0 == ~E_6~0); 4383070#L851-1 assume !(0 == ~E_7~0); 4383092#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4383093#L388 assume !(1 == ~m_pc~0); 4383086#L388-2 is_master_triggered_~__retres1~0#1 := 0; 4383087#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4383645#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4382951#L967 assume !(0 != activate_threads_~tmp~1#1); 4382952#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4382886#L407 assume !(1 == ~t1_pc~0); 4382887#L407-2 is_transmit1_triggered_~__retres1~1#1 := 0; 4382892#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4382893#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4382925#L975 assume !(0 != activate_threads_~tmp___0~0#1); 4383800#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4383202#L426 assume !(1 == ~t2_pc~0); 4383203#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 4383843#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4383225#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4383226#L983 assume !(0 != activate_threads_~tmp___1~0#1); 4383923#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4383300#L445 assume !(1 == ~t3_pc~0); 4383301#L445-2 is_transmit3_triggered_~__retres1~3#1 := 0; 4383685#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4382884#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4382885#L991 assume !(0 != activate_threads_~tmp___2~0#1); 4383590#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4383547#L464 assume !(1 == ~t4_pc~0); 4383096#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 4382971#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4382972#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4382984#L999 assume !(0 != activate_threads_~tmp___3~0#1); 4383276#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4383277#L483 assume !(1 == ~t5_pc~0); 4383544#L483-2 is_transmit5_triggered_~__retres1~5#1 := 0; 4383771#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4383715#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4383716#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 4383188#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4383189#L502 assume !(1 == ~t6_pc~0); 4383047#L502-2 is_transmit6_triggered_~__retres1~6#1 := 0; 4383009#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4383010#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4383214#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 4383431#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4383733#L521 assume !(1 == ~t7_pc~0); 4383795#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 4382947#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4382948#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4383786#L1023 assume !(0 != activate_threads_~tmp___6~0#1); 4383787#L1023-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4383994#L869 assume !(1 == ~M_E~0); 4383993#L869-2 assume !(1 == ~T1_E~0); 4383916#L874-1 assume !(1 == ~T2_E~0); 4383917#L879-1 assume !(1 == ~T3_E~0); 4383346#L884-1 assume !(1 == ~T4_E~0); 4383347#L889-1 assume !(1 == ~T5_E~0); 4383125#L894-1 assume !(1 == ~T6_E~0); 4383126#L899-1 assume !(1 == ~T7_E~0); 4383992#L904-1 assume !(1 == ~E_M~0); 4383991#L909-1 assume !(1 == ~E_1~0); 4383498#L914-1 assume !(1 == ~E_2~0); 4383499#L919-1 assume !(1 == ~E_3~0); 4383990#L924-1 assume !(1 == ~E_4~0); 4383989#L929-1 assume !(1 == ~E_5~0); 4383988#L934-1 assume !(1 == ~E_6~0); 4383987#L939-1 assume !(1 == ~E_7~0); 4383275#L944-1 assume { :end_inline_reset_delta_events } true; 4383732#L1190-2 assume !false; 4611316#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4611314#L756 [2022-12-13 11:55:22,498 INFO L750 eck$LassoCheckResult]: Loop: 4611314#L756 assume !false; 4611311#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 4611308#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 4611306#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 4611304#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 4611302#L653 assume 0 != eval_~tmp~0#1; 4611299#L653-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 4611298#L661 assume !(0 != eval_~tmp_ndt_1~0#1); 4611297#L658 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 4611111#L675 assume !(0 != eval_~tmp_ndt_2~0#1); 4611108#L672 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 4611102#L689 assume !(0 != eval_~tmp_ndt_3~0#1); 4611094#L686 assume !(0 == ~t3_st~0); 4611092#L700 assume !(0 == ~t4_st~0); 4611086#L714 assume !(0 == ~t5_st~0); 4611082#L728 assume !(0 == ~t6_st~0); 4611080#L742 assume !(0 == ~t7_st~0); 4611314#L756 [2022-12-13 11:55:22,499 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 11:55:22,499 INFO L85 PathProgramCache]: Analyzing trace with hash 1859704647, now seen corresponding path program 3 times [2022-12-13 11:55:22,499 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 11:55:22,499 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1855405091] [2022-12-13 11:55:22,499 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 11:55:22,499 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 11:55:22,506 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 11:55:22,506 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 11:55:22,511 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 11:55:22,524 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 11:55:22,524 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 11:55:22,524 INFO L85 PathProgramCache]: Analyzing trace with hash -284824179, now seen corresponding path program 1 times [2022-12-13 11:55:22,525 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 11:55:22,525 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1477064079] [2022-12-13 11:55:22,525 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 11:55:22,525 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 11:55:22,527 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 11:55:22,527 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 11:55:22,528 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 11:55:22,529 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 11:55:22,530 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 11:55:22,530 INFO L85 PathProgramCache]: Analyzing trace with hash 1341770503, now seen corresponding path program 1 times [2022-12-13 11:55:22,530 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 11:55:22,530 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1239645239] [2022-12-13 11:55:22,530 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 11:55:22,530 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 11:55:22,538 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 11:55:22,555 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 11:55:22,555 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 11:55:22,555 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1239645239] [2022-12-13 11:55:22,555 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1239645239] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 11:55:22,555 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 11:55:22,555 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 11:55:22,555 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1928670915] [2022-12-13 11:55:22,555 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 11:55:22,654 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 11:55:22,655 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 11:55:22,655 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 11:55:22,655 INFO L87 Difference]: Start difference. First operand 402528 states and 543358 transitions. cyclomatic complexity: 140872 Second operand has 3 states, 3 states have (on average 38.0) internal successors, (114), 3 states have internal predecessors, (114), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 11:55:24,107 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 11:55:24,107 INFO L93 Difference]: Finished difference Result 639240 states and 861470 transitions. [2022-12-13 11:55:24,107 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 639240 states and 861470 transitions. [2022-12-13 11:55:26,437 INFO L131 ngComponentsAnalysis]: Automaton has 44 accepting balls. 636360 [2022-12-13 11:55:27,631 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 639240 states to 639240 states and 861470 transitions. [2022-12-13 11:55:27,631 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 639240 [2022-12-13 11:55:27,987 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 639240 [2022-12-13 11:55:27,987 INFO L73 IsDeterministic]: Start isDeterministic. Operand 639240 states and 861470 transitions. [2022-12-13 11:55:28,122 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 11:55:28,122 INFO L218 hiAutomatonCegarLoop]: Abstraction has 639240 states and 861470 transitions. [2022-12-13 11:55:28,297 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 639240 states and 861470 transitions. [2022-12-13 11:55:32,476 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 639240 to 626296. [2022-12-13 11:55:32,720 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 626296 states, 626296 states have (on average 1.3492629683089146) internal successors, (845038), 626295 states have internal predecessors, (845038), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 11:55:34,049 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 626296 states to 626296 states and 845038 transitions. [2022-12-13 11:55:34,049 INFO L240 hiAutomatonCegarLoop]: Abstraction has 626296 states and 845038 transitions. [2022-12-13 11:55:34,050 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 11:55:34,050 INFO L428 stractBuchiCegarLoop]: Abstraction has 626296 states and 845038 transitions. [2022-12-13 11:55:34,050 INFO L335 stractBuchiCegarLoop]: ======== Iteration 31 ============ [2022-12-13 11:55:34,050 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 626296 states and 845038 transitions. [2022-12-13 11:55:35,519 INFO L131 ngComponentsAnalysis]: Automaton has 44 accepting balls. 623416 [2022-12-13 11:55:35,519 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 11:55:35,519 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 11:55:35,520 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 11:55:35,520 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 11:55:35,520 INFO L748 eck$LassoCheckResult]: Stem: 5424881#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 5424882#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 5425599#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5425600#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5425744#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 5425034#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5425035#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5425174#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 5425175#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 5424927#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 5424722#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 5424723#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 5424886#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5424887#L781 assume !(0 == ~M_E~0); 5425471#L781-2 assume !(0 == ~T1_E~0); 5425769#L786-1 assume !(0 == ~T2_E~0); 5424686#L791-1 assume !(0 == ~T3_E~0); 5424687#L796-1 assume !(0 == ~T4_E~0); 5425265#L801-1 assume !(0 == ~T5_E~0); 5425266#L806-1 assume !(0 == ~T6_E~0); 5425303#L811-1 assume !(0 == ~T7_E~0); 5424892#L816-1 assume !(0 == ~E_M~0); 5424893#L821-1 assume !(0 == ~E_1~0); 5424714#L826-1 assume !(0 == ~E_2~0); 5424715#L831-1 assume !(0 == ~E_3~0); 5425027#L836-1 assume !(0 == ~E_4~0); 5425028#L841-1 assume !(0 == ~E_5~0); 5424847#L846-1 assume !(0 == ~E_6~0); 5424848#L851-1 assume !(0 == ~E_7~0); 5424870#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5424871#L388 assume !(1 == ~m_pc~0); 5424864#L388-2 is_master_triggered_~__retres1~0#1 := 0; 5424865#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5425433#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 5424728#L967 assume !(0 != activate_threads_~tmp~1#1); 5424729#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5424662#L407 assume !(1 == ~t1_pc~0); 5424663#L407-2 is_transmit1_triggered_~__retres1~1#1 := 0; 5424668#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5424669#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5424702#L975 assume !(0 != activate_threads_~tmp___0~0#1); 5425595#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5424979#L426 assume !(1 == ~t2_pc~0); 5424980#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 5425642#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5425003#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 5425004#L983 assume !(0 != activate_threads_~tmp___1~0#1); 5425725#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5425083#L445 assume !(1 == ~t3_pc~0); 5425084#L445-2 is_transmit3_triggered_~__retres1~3#1 := 0; 5425481#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5424660#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 5424661#L991 assume !(0 != activate_threads_~tmp___2~0#1); 5425377#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5425339#L464 assume !(1 == ~t4_pc~0); 5424874#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 5424747#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5424748#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 5424760#L999 assume !(0 != activate_threads_~tmp___3~0#1); 5425059#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5425060#L483 assume !(1 == ~t5_pc~0); 5425335#L483-2 is_transmit5_triggered_~__retres1~5#1 := 0; 5425564#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5425511#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 5425512#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 5424965#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 5424966#L502 assume !(1 == ~t6_pc~0); 5424824#L502-2 is_transmit6_triggered_~__retres1~6#1 := 0; 5424785#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5424786#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 5424991#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 5425216#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5425529#L521 assume !(1 == ~t7_pc~0); 5425588#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 5424724#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5424725#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 5425580#L1023 assume !(0 != activate_threads_~tmp___6~0#1); 5425581#L1023-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5425797#L869 assume !(1 == ~M_E~0); 5425796#L869-2 assume !(1 == ~T1_E~0); 5425718#L874-1 assume !(1 == ~T2_E~0); 5425719#L879-1 assume !(1 == ~T3_E~0); 5425134#L884-1 assume !(1 == ~T4_E~0); 5425135#L889-1 assume !(1 == ~T5_E~0); 5424902#L894-1 assume !(1 == ~T6_E~0); 5424903#L899-1 assume !(1 == ~T7_E~0); 5425795#L904-1 assume !(1 == ~E_M~0); 5425794#L909-1 assume !(1 == ~E_1~0); 5425284#L914-1 assume !(1 == ~E_2~0); 5425285#L919-1 assume !(1 == ~E_3~0); 5425793#L924-1 assume !(1 == ~E_4~0); 5425792#L929-1 assume !(1 == ~E_5~0); 5425791#L934-1 assume !(1 == ~E_6~0); 5425790#L939-1 assume !(1 == ~E_7~0); 5425058#L944-1 assume { :end_inline_reset_delta_events } true; 5425528#L1190-2 assume !false; 5778249#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5778245#L756 [2022-12-13 11:55:35,520 INFO L750 eck$LassoCheckResult]: Loop: 5778245#L756 assume !false; 5778243#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 5778240#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 5778238#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 5778236#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 5778234#L653 assume 0 != eval_~tmp~0#1; 5778232#L653-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 5778231#L661 assume !(0 != eval_~tmp_ndt_1~0#1); 5778227#L658 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 5778198#L675 assume !(0 != eval_~tmp_ndt_2~0#1); 5778196#L672 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 5778193#L689 assume !(0 != eval_~tmp_ndt_3~0#1); 5778191#L686 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; 5778189#L703 assume !(0 != eval_~tmp_ndt_4~0#1); 5778187#L700 assume !(0 == ~t4_st~0); 5778182#L714 assume !(0 == ~t5_st~0); 5778178#L728 assume !(0 == ~t6_st~0); 5778176#L742 assume !(0 == ~t7_st~0); 5778245#L756 [2022-12-13 11:55:35,520 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 11:55:35,521 INFO L85 PathProgramCache]: Analyzing trace with hash 1859704647, now seen corresponding path program 4 times [2022-12-13 11:55:35,521 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 11:55:35,521 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1759039568] [2022-12-13 11:55:35,521 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 11:55:35,521 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 11:55:35,527 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 11:55:35,527 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 11:55:35,531 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 11:55:35,543 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 11:55:35,543 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 11:55:35,543 INFO L85 PathProgramCache]: Analyzing trace with hash 1746623757, now seen corresponding path program 1 times [2022-12-13 11:55:35,543 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 11:55:35,543 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1512097655] [2022-12-13 11:55:35,543 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 11:55:35,544 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 11:55:35,546 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 11:55:35,546 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 11:55:35,547 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 11:55:35,548 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 11:55:35,548 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 11:55:35,549 INFO L85 PathProgramCache]: Analyzing trace with hash 631451347, now seen corresponding path program 1 times [2022-12-13 11:55:35,549 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 11:55:35,549 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1565924839] [2022-12-13 11:55:35,549 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 11:55:35,549 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 11:55:35,555 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 11:55:35,571 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 11:55:35,571 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 11:55:35,571 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1565924839] [2022-12-13 11:55:35,571 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1565924839] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 11:55:35,571 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 11:55:35,571 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 11:55:35,571 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [974835628] [2022-12-13 11:55:35,571 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 11:55:35,664 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 11:55:35,665 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 11:55:35,665 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 11:55:35,665 INFO L87 Difference]: Start difference. First operand 626296 states and 845038 transitions. cyclomatic complexity: 218786 Second operand has 3 states, 3 states have (on average 38.333333333333336) internal successors, (115), 3 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 11:55:38,720 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 11:55:38,720 INFO L93 Difference]: Finished difference Result 1160712 states and 1564550 transitions. [2022-12-13 11:55:38,720 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1160712 states and 1564550 transitions.