./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/token_ring.10.cil-1.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 2329fc70 Calling Ultimate with: /usr/lib/jvm/java-1.11.0-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_514e9ab3-fff9-421f-8f64-c80932cf1faa/bin/uautomizer-uyxdKDjOR8/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_514e9ab3-fff9-421f-8f64-c80932cf1faa/bin/uautomizer-uyxdKDjOR8/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_514e9ab3-fff9-421f-8f64-c80932cf1faa/bin/uautomizer-uyxdKDjOR8/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_514e9ab3-fff9-421f-8f64-c80932cf1faa/bin/uautomizer-uyxdKDjOR8/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/token_ring.10.cil-1.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_514e9ab3-fff9-421f-8f64-c80932cf1faa/bin/uautomizer-uyxdKDjOR8/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_514e9ab3-fff9-421f-8f64-c80932cf1faa/bin/uautomizer-uyxdKDjOR8 --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 9102a3dc168a1a089cfcbe45042daf88c4c5eebedf113fc0c98e676c1fbaab5b --- Real Ultimate output --- [0.001s][warning][os,container] Duplicate cpuset controllers detected. Picking /sys/fs/cgroup/cpuset, skipping /sys/fs/cgroup/cpuset. This is Ultimate 0.2.2-dev-2329fc7 [2022-12-13 12:11:36,747 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-12-13 12:11:36,750 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-12-13 12:11:36,769 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-12-13 12:11:36,769 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-12-13 12:11:36,770 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-12-13 12:11:36,772 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-12-13 12:11:36,773 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-12-13 12:11:36,775 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-12-13 12:11:36,776 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-12-13 12:11:36,777 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-12-13 12:11:36,778 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-12-13 12:11:36,778 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-12-13 12:11:36,779 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-12-13 12:11:36,780 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-12-13 12:11:36,781 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-12-13 12:11:36,782 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-12-13 12:11:36,783 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-12-13 12:11:36,784 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-12-13 12:11:36,786 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-12-13 12:11:36,787 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-12-13 12:11:36,789 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-12-13 12:11:36,790 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-12-13 12:11:36,790 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-12-13 12:11:36,794 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-12-13 12:11:36,794 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-12-13 12:11:36,794 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-12-13 12:11:36,795 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-12-13 12:11:36,796 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-12-13 12:11:36,797 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-12-13 12:11:36,797 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-12-13 12:11:36,798 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-12-13 12:11:36,798 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-12-13 12:11:36,799 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-12-13 12:11:36,800 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-12-13 12:11:36,800 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-12-13 12:11:36,801 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-12-13 12:11:36,801 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-12-13 12:11:36,801 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-12-13 12:11:36,802 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-12-13 12:11:36,803 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-12-13 12:11:36,803 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_514e9ab3-fff9-421f-8f64-c80932cf1faa/bin/uautomizer-uyxdKDjOR8/config/svcomp-Termination-32bit-Automizer_Default.epf [2022-12-13 12:11:36,818 INFO L113 SettingsManager]: Loading preferences was successful [2022-12-13 12:11:36,819 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-12-13 12:11:36,819 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-12-13 12:11:36,819 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-12-13 12:11:36,820 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-12-13 12:11:36,820 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-12-13 12:11:36,820 INFO L138 SettingsManager]: * Use SBE=true [2022-12-13 12:11:36,820 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2022-12-13 12:11:36,820 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2022-12-13 12:11:36,820 INFO L138 SettingsManager]: * Use old map elimination=false [2022-12-13 12:11:36,821 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2022-12-13 12:11:36,821 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2022-12-13 12:11:36,821 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2022-12-13 12:11:36,821 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-12-13 12:11:36,821 INFO L138 SettingsManager]: * sizeof long=4 [2022-12-13 12:11:36,821 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2022-12-13 12:11:36,822 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-12-13 12:11:36,822 INFO L138 SettingsManager]: * sizeof POINTER=4 [2022-12-13 12:11:36,822 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-12-13 12:11:36,822 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2022-12-13 12:11:36,822 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2022-12-13 12:11:36,822 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2022-12-13 12:11:36,822 INFO L138 SettingsManager]: * sizeof long double=12 [2022-12-13 12:11:36,823 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-12-13 12:11:36,823 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2022-12-13 12:11:36,823 INFO L138 SettingsManager]: * Use constant arrays=true [2022-12-13 12:11:36,823 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2022-12-13 12:11:36,823 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-12-13 12:11:36,823 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-12-13 12:11:36,824 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-12-13 12:11:36,824 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-12-13 12:11:36,824 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-12-13 12:11:36,825 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_514e9ab3-fff9-421f-8f64-c80932cf1faa/bin/uautomizer-uyxdKDjOR8/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_514e9ab3-fff9-421f-8f64-c80932cf1faa/bin/uautomizer-uyxdKDjOR8 Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 9102a3dc168a1a089cfcbe45042daf88c4c5eebedf113fc0c98e676c1fbaab5b [2022-12-13 12:11:36,980 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-12-13 12:11:37,000 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-12-13 12:11:37,002 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-12-13 12:11:37,003 INFO L271 PluginConnector]: Initializing CDTParser... [2022-12-13 12:11:37,003 INFO L275 PluginConnector]: CDTParser initialized [2022-12-13 12:11:37,004 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_514e9ab3-fff9-421f-8f64-c80932cf1faa/bin/uautomizer-uyxdKDjOR8/../../sv-benchmarks/c/systemc/token_ring.10.cil-1.c [2022-12-13 12:11:39,562 INFO L500 CDTParser]: Created temporary CDT project at NULL [2022-12-13 12:11:39,734 INFO L351 CDTParser]: Found 1 translation units. [2022-12-13 12:11:39,735 INFO L172 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_514e9ab3-fff9-421f-8f64-c80932cf1faa/sv-benchmarks/c/systemc/token_ring.10.cil-1.c [2022-12-13 12:11:39,743 INFO L394 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_514e9ab3-fff9-421f-8f64-c80932cf1faa/bin/uautomizer-uyxdKDjOR8/data/fed2c4769/552b024bdd9140a79798db0b873a39b1/FLAGa339d699a [2022-12-13 12:11:39,754 INFO L402 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_514e9ab3-fff9-421f-8f64-c80932cf1faa/bin/uautomizer-uyxdKDjOR8/data/fed2c4769/552b024bdd9140a79798db0b873a39b1 [2022-12-13 12:11:39,756 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-12-13 12:11:39,757 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-12-13 12:11:39,758 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-12-13 12:11:39,758 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-12-13 12:11:39,761 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-12-13 12:11:39,762 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.12 12:11:39" (1/1) ... [2022-12-13 12:11:39,763 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@5b1fc26c and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 12:11:39, skipping insertion in model container [2022-12-13 12:11:39,763 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.12 12:11:39" (1/1) ... [2022-12-13 12:11:39,769 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-12-13 12:11:39,810 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-12-13 12:11:39,910 WARN L237 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_514e9ab3-fff9-421f-8f64-c80932cf1faa/sv-benchmarks/c/systemc/token_ring.10.cil-1.c[671,684] [2022-12-13 12:11:39,988 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-12-13 12:11:39,999 INFO L203 MainTranslator]: Completed pre-run [2022-12-13 12:11:40,007 WARN L237 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_514e9ab3-fff9-421f-8f64-c80932cf1faa/sv-benchmarks/c/systemc/token_ring.10.cil-1.c[671,684] [2022-12-13 12:11:40,048 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-12-13 12:11:40,062 INFO L208 MainTranslator]: Completed translation [2022-12-13 12:11:40,062 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 12:11:40 WrapperNode [2022-12-13 12:11:40,063 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-12-13 12:11:40,063 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-12-13 12:11:40,063 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-12-13 12:11:40,063 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-12-13 12:11:40,069 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 12:11:40" (1/1) ... [2022-12-13 12:11:40,077 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 12:11:40" (1/1) ... [2022-12-13 12:11:40,131 INFO L138 Inliner]: procedures = 48, calls = 62, calls flagged for inlining = 57, calls inlined = 210, statements flattened = 3198 [2022-12-13 12:11:40,131 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-12-13 12:11:40,132 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-12-13 12:11:40,132 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-12-13 12:11:40,132 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-12-13 12:11:40,139 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 12:11:40" (1/1) ... [2022-12-13 12:11:40,139 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 12:11:40" (1/1) ... [2022-12-13 12:11:40,146 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 12:11:40" (1/1) ... [2022-12-13 12:11:40,146 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 12:11:40" (1/1) ... [2022-12-13 12:11:40,168 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 12:11:40" (1/1) ... [2022-12-13 12:11:40,185 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 12:11:40" (1/1) ... [2022-12-13 12:11:40,188 INFO L185 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 12:11:40" (1/1) ... [2022-12-13 12:11:40,194 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 12:11:40" (1/1) ... [2022-12-13 12:11:40,202 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-12-13 12:11:40,203 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-12-13 12:11:40,203 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-12-13 12:11:40,203 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-12-13 12:11:40,204 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 12:11:40" (1/1) ... [2022-12-13 12:11:40,209 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-12-13 12:11:40,218 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_514e9ab3-fff9-421f-8f64-c80932cf1faa/bin/uautomizer-uyxdKDjOR8/z3 [2022-12-13 12:11:40,229 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_514e9ab3-fff9-421f-8f64-c80932cf1faa/bin/uautomizer-uyxdKDjOR8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-12-13 12:11:40,231 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_514e9ab3-fff9-421f-8f64-c80932cf1faa/bin/uautomizer-uyxdKDjOR8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2022-12-13 12:11:40,265 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-12-13 12:11:40,266 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-12-13 12:11:40,266 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-12-13 12:11:40,266 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-12-13 12:11:40,381 INFO L235 CfgBuilder]: Building ICFG [2022-12-13 12:11:40,383 INFO L261 CfgBuilder]: Building CFG for each procedure with an implementation [2022-12-13 12:11:41,568 INFO L276 CfgBuilder]: Performing block encoding [2022-12-13 12:11:41,579 INFO L295 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-12-13 12:11:41,580 INFO L300 CfgBuilder]: Removed 13 assume(true) statements. [2022-12-13 12:11:41,582 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.12 12:11:41 BoogieIcfgContainer [2022-12-13 12:11:41,582 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-12-13 12:11:41,583 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2022-12-13 12:11:41,583 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2022-12-13 12:11:41,586 INFO L275 PluginConnector]: BuchiAutomizer initialized [2022-12-13 12:11:41,586 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-12-13 12:11:41,586 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 13.12 12:11:39" (1/3) ... [2022-12-13 12:11:41,587 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@623d2646 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 13.12 12:11:41, skipping insertion in model container [2022-12-13 12:11:41,587 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-12-13 12:11:41,587 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 12:11:40" (2/3) ... [2022-12-13 12:11:41,588 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@623d2646 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 13.12 12:11:41, skipping insertion in model container [2022-12-13 12:11:41,588 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-12-13 12:11:41,588 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.12 12:11:41" (3/3) ... [2022-12-13 12:11:41,589 INFO L332 chiAutomizerObserver]: Analyzing ICFG token_ring.10.cil-1.c [2022-12-13 12:11:41,642 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2022-12-13 12:11:41,642 INFO L304 stractBuchiCegarLoop]: Hoare is false [2022-12-13 12:11:41,642 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2022-12-13 12:11:41,642 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2022-12-13 12:11:41,642 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2022-12-13 12:11:41,642 INFO L308 stractBuchiCegarLoop]: Difference is false [2022-12-13 12:11:41,642 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2022-12-13 12:11:41,643 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2022-12-13 12:11:41,649 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1374 states, 1373 states have (on average 1.5069191551347414) internal successors, (2069), 1373 states have internal predecessors, (2069), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:11:41,691 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1231 [2022-12-13 12:11:41,691 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:11:41,692 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:11:41,701 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:11:41,701 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:11:41,701 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2022-12-13 12:11:41,703 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1374 states, 1373 states have (on average 1.5069191551347414) internal successors, (2069), 1373 states have internal predecessors, (2069), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:11:41,712 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1231 [2022-12-13 12:11:41,712 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:11:41,712 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:11:41,716 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:11:41,716 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:11:41,723 INFO L748 eck$LassoCheckResult]: Stem: 207#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 1264#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 1014#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1258#update_channels_returnLabel#1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1159#L731true assume !(1 == ~m_i~0);~m_st~0 := 2; 1025#L731-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 933#L736-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 1002#L741-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1318#L746-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 171#L751-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 229#L756-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 844#L761-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 386#L766-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 335#L771-1true assume 1 == ~t9_i~0;~t9_st~0 := 0; 172#L776-1true assume !(1 == ~t10_i~0);~t10_st~0 := 2; 10#L781-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 54#L1036true assume !(0 == ~M_E~0); 1033#L1036-2true assume !(0 == ~T1_E~0); 619#L1041-1true assume !(0 == ~T2_E~0); 974#L1046-1true assume 0 == ~T3_E~0;~T3_E~0 := 1; 195#L1051-1true assume !(0 == ~T4_E~0); 755#L1056-1true assume !(0 == ~T5_E~0); 809#L1061-1true assume !(0 == ~T6_E~0); 139#L1066-1true assume !(0 == ~T7_E~0); 1154#L1071-1true assume !(0 == ~T8_E~0); 735#L1076-1true assume !(0 == ~T9_E~0); 84#L1081-1true assume !(0 == ~T10_E~0); 301#L1086-1true assume 0 == ~E_M~0;~E_M~0 := 1; 1171#L1091-1true assume !(0 == ~E_1~0); 1035#L1096-1true assume !(0 == ~E_2~0); 1269#L1101-1true assume !(0 == ~E_3~0); 344#L1106-1true assume !(0 == ~E_4~0); 558#L1111-1true assume !(0 == ~E_5~0); 463#L1116-1true assume !(0 == ~E_6~0); 1093#L1121-1true assume !(0 == ~E_7~0); 338#L1126-1true assume 0 == ~E_8~0;~E_8~0 := 1; 538#L1131-1true assume !(0 == ~E_9~0); 627#L1136-1true assume !(0 == ~E_10~0); 898#L1141-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 794#L514true assume 1 == ~m_pc~0; 745#L515true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 348#L525true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 870#is_master_triggered_returnLabel#1true activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1105#L1285true assume !(0 != activate_threads_~tmp~1#1); 1192#L1285-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 147#L533true assume !(1 == ~t1_pc~0); 1049#L533-2true is_transmit1_triggered_~__retres1~1#1 := 0; 506#L544true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 34#is_transmit1_triggered_returnLabel#1true activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 912#L1293true assume !(0 != activate_threads_~tmp___0~0#1); 652#L1293-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 902#L552true assume 1 == ~t2_pc~0; 269#L553true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 934#L563true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 340#is_transmit2_triggered_returnLabel#1true activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 978#L1301true assume !(0 != activate_threads_~tmp___1~0#1); 357#L1301-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 517#L571true assume 1 == ~t3_pc~0; 503#L572true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 689#L582true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9#is_transmit3_triggered_returnLabel#1true activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 659#L1309true assume !(0 != activate_threads_~tmp___2~0#1); 466#L1309-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 48#L590true assume !(1 == ~t4_pc~0); 516#L590-2true is_transmit4_triggered_~__retres1~4#1 := 0; 1290#L601true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 93#is_transmit4_triggered_returnLabel#1true activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1117#L1317true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 674#L1317-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 464#L609true assume 1 == ~t5_pc~0; 1280#L610true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1102#L620true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 874#is_transmit5_triggered_returnLabel#1true activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1375#L1325true assume !(0 != activate_threads_~tmp___4~0#1); 458#L1325-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1278#L628true assume !(1 == ~t6_pc~0); 539#L628-2true is_transmit6_triggered_~__retres1~6#1 := 0; 1254#L639true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 324#is_transmit6_triggered_returnLabel#1true activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1182#L1333true assume !(0 != activate_threads_~tmp___5~0#1); 712#L1333-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 853#L647true assume 1 == ~t7_pc~0; 345#L648true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 889#L658true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1284#is_transmit7_triggered_returnLabel#1true activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 346#L1341true assume !(0 != activate_threads_~tmp___6~0#1); 1247#L1341-2true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1220#L666true assume !(1 == ~t8_pc~0); 792#L666-2true is_transmit8_triggered_~__retres1~8#1 := 0; 356#L677true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 795#is_transmit8_triggered_returnLabel#1true activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 483#L1349true assume !(0 != activate_threads_~tmp___7~0#1); 299#L1349-2true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1135#L685true assume 1 == ~t9_pc~0; 1300#L686true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 913#L696true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 381#is_transmit9_triggered_returnLabel#1true activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 316#L1357true assume !(0 != activate_threads_~tmp___8~0#1); 1009#L1357-2true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 598#L704true assume !(1 == ~t10_pc~0); 1090#L704-2true is_transmit10_triggered_~__retres1~10#1 := 0; 1042#L715true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 494#is_transmit10_triggered_returnLabel#1true activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 71#L1365true assume !(0 != activate_threads_~tmp___9~0#1); 199#L1365-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 701#L1154true assume !(1 == ~M_E~0); 1178#L1154-2true assume !(1 == ~T1_E~0); 183#L1159-1true assume !(1 == ~T2_E~0); 1310#L1164-1true assume !(1 == ~T3_E~0); 481#L1169-1true assume !(1 == ~T4_E~0); 382#L1174-1true assume 1 == ~T5_E~0;~T5_E~0 := 2; 253#L1179-1true assume !(1 == ~T6_E~0); 176#L1184-1true assume !(1 == ~T7_E~0); 219#L1189-1true assume !(1 == ~T8_E~0); 290#L1194-1true assume !(1 == ~T9_E~0); 1355#L1199-1true assume !(1 == ~T10_E~0); 263#L1204-1true assume !(1 == ~E_M~0); 1214#L1209-1true assume !(1 == ~E_1~0); 670#L1214-1true assume 1 == ~E_2~0;~E_2~0 := 2; 1308#L1219-1true assume !(1 == ~E_3~0); 1188#L1224-1true assume !(1 == ~E_4~0); 499#L1229-1true assume !(1 == ~E_5~0); 118#L1234-1true assume !(1 == ~E_6~0); 781#L1239-1true assume !(1 == ~E_7~0); 145#L1244-1true assume !(1 == ~E_8~0); 830#L1249-1true assume !(1 == ~E_9~0); 743#L1254-1true assume 1 == ~E_10~0;~E_10~0 := 2; 68#L1259-1true assume { :end_inline_reset_delta_events } true; 1167#L1565-2true [2022-12-13 12:11:41,724 INFO L750 eck$LassoCheckResult]: Loop: 1167#L1565-2true assume !false; 678#L1566true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 273#L1011true assume false; 806#eval_returnLabel#1true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 512#update_channels_returnLabel#2true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 750#L1036-3true assume 0 == ~M_E~0;~M_E~0 := 1; 1069#L1036-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 1306#L1041-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 838#L1046-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 1189#L1051-3true assume !(0 == ~T4_E~0); 751#L1056-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 193#L1061-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 194#L1066-3true assume 0 == ~T7_E~0;~T7_E~0 := 1; 1322#L1071-3true assume 0 == ~T8_E~0;~T8_E~0 := 1; 1072#L1076-3true assume 0 == ~T9_E~0;~T9_E~0 := 1; 65#L1081-3true assume 0 == ~T10_E~0;~T10_E~0 := 1; 1237#L1086-3true assume 0 == ~E_M~0;~E_M~0 := 1; 89#L1091-3true assume !(0 == ~E_1~0); 1145#L1096-3true assume 0 == ~E_2~0;~E_2~0 := 1; 1004#L1101-3true assume 0 == ~E_3~0;~E_3~0 := 1; 1068#L1106-3true assume 0 == ~E_4~0;~E_4~0 := 1; 1122#L1111-3true assume 0 == ~E_5~0;~E_5~0 := 1; 990#L1116-3true assume 0 == ~E_6~0;~E_6~0 := 1; 608#L1121-3true assume 0 == ~E_7~0;~E_7~0 := 1; 937#L1126-3true assume 0 == ~E_8~0;~E_8~0 := 1; 863#L1131-3true assume !(0 == ~E_9~0); 1301#L1136-3true assume 0 == ~E_10~0;~E_10~0 := 1; 1275#L1141-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 612#L514-36true assume 1 == ~m_pc~0; 1349#L515-12true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 284#L525-12true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1017#is_master_triggered_returnLabel#13true activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 650#L1285-36true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 223#L1285-38true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 400#L533-36true assume 1 == ~t1_pc~0; 470#L534-12true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 961#L544-12true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1015#is_transmit1_triggered_returnLabel#13true activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 688#L1293-36true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 515#L1293-38true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1364#L552-36true assume 1 == ~t2_pc~0; 221#L553-12true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 557#L563-12true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 851#is_transmit2_triggered_returnLabel#13true activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1176#L1301-36true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 205#L1301-38true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 841#L571-36true assume 1 == ~t3_pc~0; 455#L572-12true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 254#L582-12true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 378#is_transmit3_triggered_returnLabel#13true activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 836#L1309-36true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 880#L1309-38true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 238#L590-36true assume !(1 == ~t4_pc~0); 883#L590-38true is_transmit4_triggered_~__retres1~4#1 := 0; 1018#L601-12true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 524#is_transmit4_triggered_returnLabel#13true activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1313#L1317-36true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 802#L1317-38true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1060#L609-36true assume !(1 == ~t5_pc~0); 1329#L609-38true is_transmit5_triggered_~__retres1~5#1 := 0; 519#L620-12true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 970#is_transmit5_triggered_returnLabel#13true activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 869#L1325-36true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 579#L1325-38true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 436#L628-36true assume !(1 == ~t6_pc~0); 1132#L628-38true is_transmit6_triggered_~__retres1~6#1 := 0; 1136#L639-12true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 364#is_transmit6_triggered_returnLabel#13true activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 756#L1333-36true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 613#L1333-38true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1099#L647-36true assume 1 == ~t7_pc~0; 553#L648-12true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 77#L658-12true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 941#is_transmit7_triggered_returnLabel#13true activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 86#L1341-36true assume !(0 != activate_threads_~tmp___6~0#1); 703#L1341-38true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 775#L666-36true assume 1 == ~t8_pc~0; 182#L667-12true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 1197#L677-12true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 603#is_transmit8_triggered_returnLabel#13true activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1211#L1349-36true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 268#L1349-38true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 594#L685-36true assume 1 == ~t9_pc~0; 932#L686-12true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 881#L696-12true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 403#is_transmit9_triggered_returnLabel#13true activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1268#L1357-36true assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 354#L1357-38true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 363#L704-36true assume 1 == ~t10_pc~0; 128#L705-12true assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 1151#L715-12true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 306#is_transmit10_triggered_returnLabel#13true activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 729#L1365-36true assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 141#L1365-38true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1348#L1154-3true assume 1 == ~M_E~0;~M_E~0 := 2; 973#L1154-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 765#L1159-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 1324#L1164-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 1095#L1169-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 310#L1174-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 1184#L1179-3true assume !(1 == ~T6_E~0); 916#L1184-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 78#L1189-3true assume 1 == ~T8_E~0;~T8_E~0 := 2; 922#L1194-3true assume 1 == ~T9_E~0;~T9_E~0 := 2; 275#L1199-3true assume 1 == ~T10_E~0;~T10_E~0 := 2; 1358#L1204-3true assume 1 == ~E_M~0;~E_M~0 := 2; 496#L1209-3true assume 1 == ~E_1~0;~E_1~0 := 2; 17#L1214-3true assume 1 == ~E_2~0;~E_2~0 := 2; 1012#L1219-3true assume !(1 == ~E_3~0); 657#L1224-3true assume 1 == ~E_4~0;~E_4~0 := 2; 1369#L1229-3true assume 1 == ~E_5~0;~E_5~0 := 2; 677#L1234-3true assume 1 == ~E_6~0;~E_6~0 := 2; 146#L1239-3true assume 1 == ~E_7~0;~E_7~0 := 2; 534#L1244-3true assume 1 == ~E_8~0;~E_8~0 := 2; 1075#L1249-3true assume 1 == ~E_9~0;~E_9~0 := 2; 991#L1254-3true assume 1 == ~E_10~0;~E_10~0 := 2; 662#L1259-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 759#L794-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 1286#L851-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 298#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 617#L1584true assume !(0 == start_simulation_~tmp~3#1); 642#L1584-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 152#L794-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 936#L851-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 32#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 342#L1539true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 979#L1546true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 527#stop_simulation_returnLabel#1true start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 1162#L1597true assume !(0 != start_simulation_~tmp___0~1#1); 1167#L1565-2true [2022-12-13 12:11:41,729 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:11:41,729 INFO L85 PathProgramCache]: Analyzing trace with hash 121410427, now seen corresponding path program 1 times [2022-12-13 12:11:41,736 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:11:41,736 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [354367607] [2022-12-13 12:11:41,736 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:11:41,737 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:11:41,814 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:11:41,970 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:11:41,971 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:11:41,971 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [354367607] [2022-12-13 12:11:41,972 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [354367607] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:11:41,972 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:11:41,972 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:11:41,973 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1532249153] [2022-12-13 12:11:41,974 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:11:41,979 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 12:11:41,979 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:11:41,980 INFO L85 PathProgramCache]: Analyzing trace with hash 1006475671, now seen corresponding path program 1 times [2022-12-13 12:11:41,980 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:11:41,980 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [602826641] [2022-12-13 12:11:41,980 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:11:41,981 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:11:41,996 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:11:42,035 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:11:42,035 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:11:42,035 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [602826641] [2022-12-13 12:11:42,035 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [602826641] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:11:42,036 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:11:42,036 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-12-13 12:11:42,036 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [721175352] [2022-12-13 12:11:42,036 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:11:42,037 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:11:42,038 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:11:42,069 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 12:11:42,070 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 12:11:42,074 INFO L87 Difference]: Start difference. First operand has 1374 states, 1373 states have (on average 1.5069191551347414) internal successors, (2069), 1373 states have internal predecessors, (2069), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:11:42,143 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:11:42,143 INFO L93 Difference]: Finished difference Result 1372 states and 2038 transitions. [2022-12-13 12:11:42,145 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1372 states and 2038 transitions. [2022-12-13 12:11:42,155 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1227 [2022-12-13 12:11:42,168 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1372 states to 1366 states and 2032 transitions. [2022-12-13 12:11:42,169 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1366 [2022-12-13 12:11:42,172 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1366 [2022-12-13 12:11:42,172 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1366 states and 2032 transitions. [2022-12-13 12:11:42,178 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:11:42,178 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1366 states and 2032 transitions. [2022-12-13 12:11:42,199 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1366 states and 2032 transitions. [2022-12-13 12:11:42,236 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1366 to 1366. [2022-12-13 12:11:42,239 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1366 states, 1366 states have (on average 1.4875549048316252) internal successors, (2032), 1365 states have internal predecessors, (2032), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:11:42,244 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1366 states to 1366 states and 2032 transitions. [2022-12-13 12:11:42,245 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1366 states and 2032 transitions. [2022-12-13 12:11:42,246 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 12:11:42,249 INFO L428 stractBuchiCegarLoop]: Abstraction has 1366 states and 2032 transitions. [2022-12-13 12:11:42,250 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2022-12-13 12:11:42,250 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1366 states and 2032 transitions. [2022-12-13 12:11:42,256 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1227 [2022-12-13 12:11:42,256 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:11:42,256 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:11:42,259 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:11:42,260 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:11:42,260 INFO L748 eck$LassoCheckResult]: Stem: 3178#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 3179#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 4040#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4041#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4102#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 4044#L731-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4004#L736-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 4005#L741-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 4033#L746-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 3116#L751-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 3117#L756-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 3220#L761-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 3461#L766-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 3390#L771-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 3118#L776-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 2773#L781-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2774#L1036 assume !(0 == ~M_E~0); 2871#L1036-2 assume !(0 == ~T1_E~0); 3770#L1041-1 assume !(0 == ~T2_E~0); 3771#L1046-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3153#L1051-1 assume !(0 == ~T4_E~0); 3154#L1056-1 assume !(0 == ~T5_E~0); 3896#L1061-1 assume !(0 == ~T6_E~0); 3047#L1066-1 assume !(0 == ~T7_E~0); 3048#L1071-1 assume !(0 == ~T8_E~0); 3878#L1076-1 assume !(0 == ~T9_E~0); 2935#L1081-1 assume !(0 == ~T10_E~0); 2936#L1086-1 assume 0 == ~E_M~0;~E_M~0 := 1; 3337#L1091-1 assume !(0 == ~E_1~0); 4052#L1096-1 assume !(0 == ~E_2~0); 4053#L1101-1 assume !(0 == ~E_3~0); 3403#L1106-1 assume !(0 == ~E_4~0); 3404#L1111-1 assume !(0 == ~E_5~0); 3565#L1116-1 assume !(0 == ~E_6~0); 3566#L1121-1 assume !(0 == ~E_7~0); 3394#L1126-1 assume 0 == ~E_8~0;~E_8~0 := 1; 3395#L1131-1 assume !(0 == ~E_9~0); 3663#L1136-1 assume !(0 == ~E_10~0); 3776#L1141-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3923#L514 assume 1 == ~m_pc~0; 3889#L515 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 3412#L525 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3413#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3975#L1285 assume !(0 != activate_threads_~tmp~1#1); 4087#L1285-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3066#L533 assume !(1 == ~t1_pc~0); 3067#L533-2 is_transmit1_triggered_~__retres1~1#1 := 0; 3580#L544 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2828#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2829#L1293 assume !(0 != activate_threads_~tmp___0~0#1); 3799#L1293-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3800#L552 assume 1 == ~t2_pc~0; 3285#L553 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3286#L563 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3398#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3399#L1301 assume !(0 != activate_threads_~tmp___1~0#1); 3430#L1301-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3431#L571 assume 1 == ~t3_pc~0; 3618#L572 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3619#L582 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2771#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2772#L1309 assume !(0 != activate_threads_~tmp___2~0#1); 3570#L1309-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2857#L590 assume !(1 == ~t4_pc~0); 2858#L590-2 is_transmit4_triggered_~__retres1~4#1 := 0; 3626#L601 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2953#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2954#L1317 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 3826#L1317-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3567#L609 assume 1 == ~t5_pc~0; 3568#L610 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 4084#L620 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3977#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3978#L1325 assume !(0 != activate_threads_~tmp___4~0#1); 3560#L1325-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3561#L628 assume !(1 == ~t6_pc~0); 3492#L628-2 is_transmit6_triggered_~__retres1~6#1 := 0; 3491#L639 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3371#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3372#L1333 assume !(0 != activate_threads_~tmp___5~0#1); 3859#L1333-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3860#L647 assume 1 == ~t7_pc~0; 3405#L648 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 3406#L658 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3986#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 3410#L1341 assume !(0 != activate_threads_~tmp___6~0#1); 3411#L1341-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4113#L666 assume !(1 == ~t8_pc~0); 3200#L666-2 is_transmit8_triggered_~__retres1~8#1 := 0; 3201#L677 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3424#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 3592#L1349 assume !(0 != activate_threads_~tmp___7~0#1); 3334#L1349-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3335#L685 assume 1 == ~t9_pc~0; 4092#L686 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 3994#L696 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3455#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 3362#L1357 assume !(0 != activate_threads_~tmp___8~0#1); 3363#L1357-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 3741#L704 assume !(1 == ~t10_pc~0); 3354#L704-2 is_transmit10_triggered_~__retres1~10#1 := 0; 3353#L715 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 3606#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 2905#L1365 assume !(0 != activate_threads_~tmp___9~0#1); 2906#L1365-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3162#L1154 assume !(1 == ~M_E~0); 3847#L1154-2 assume !(1 == ~T1_E~0); 3134#L1159-1 assume !(1 == ~T2_E~0); 3135#L1164-1 assume !(1 == ~T3_E~0); 3589#L1169-1 assume !(1 == ~T4_E~0); 3456#L1174-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3264#L1179-1 assume !(1 == ~T6_E~0); 3120#L1184-1 assume !(1 == ~T7_E~0); 3121#L1189-1 assume !(1 == ~T8_E~0); 3198#L1194-1 assume !(1 == ~T9_E~0); 3323#L1199-1 assume !(1 == ~T10_E~0); 3276#L1204-1 assume !(1 == ~E_M~0); 3277#L1209-1 assume !(1 == ~E_1~0); 3821#L1214-1 assume 1 == ~E_2~0;~E_2~0 := 2; 3822#L1219-1 assume !(1 == ~E_3~0); 4106#L1224-1 assume !(1 == ~E_4~0); 3610#L1229-1 assume !(1 == ~E_5~0); 3002#L1234-1 assume !(1 == ~E_6~0); 3003#L1239-1 assume !(1 == ~E_7~0); 3062#L1244-1 assume !(1 == ~E_8~0); 3063#L1249-1 assume !(1 == ~E_9~0); 3887#L1254-1 assume 1 == ~E_10~0;~E_10~0 := 2; 2900#L1259-1 assume { :end_inline_reset_delta_events } true; 2901#L1565-2 [2022-12-13 12:11:42,261 INFO L750 eck$LassoCheckResult]: Loop: 2901#L1565-2 assume !false; 3827#L1566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2852#L1011 assume !false; 3291#L862 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 3339#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 3103#L851 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 3436#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 3131#L866 assume !(0 != eval_~tmp~0#1); 3133#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3629#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3630#L1036-3 assume 0 == ~M_E~0;~M_E~0 := 1; 3891#L1036-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4069#L1041-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3951#L1046-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3952#L1051-3 assume !(0 == ~T4_E~0); 3892#L1056-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 3150#L1061-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 3151#L1066-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 3152#L1071-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 4071#L1076-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 2892#L1081-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 2893#L1086-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2949#L1091-3 assume !(0 == ~E_1~0); 2950#L1096-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4035#L1101-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4036#L1106-3 assume 0 == ~E_4~0;~E_4~0 := 1; 4068#L1111-3 assume 0 == ~E_5~0;~E_5~0 := 1; 4027#L1116-3 assume 0 == ~E_6~0;~E_6~0 := 1; 3756#L1121-3 assume 0 == ~E_7~0;~E_7~0 := 1; 3757#L1126-3 assume 0 == ~E_8~0;~E_8~0 := 1; 3966#L1131-3 assume !(0 == ~E_9~0); 3967#L1136-3 assume 0 == ~E_10~0;~E_10~0 := 1; 4118#L1141-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3759#L514-36 assume !(1 == ~m_pc~0); 3472#L514-38 is_master_triggered_~__retres1~0#1 := 0; 3312#L525-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3313#is_master_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3798#L1285-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3207#L1285-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3208#L533-36 assume 1 == ~t1_pc~0; 3481#L534-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3577#L544-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4017#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3835#L1293-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3633#L1293-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3634#L552-36 assume 1 == ~t2_pc~0; 3202#L553-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3204#L563-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3692#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3959#L1301-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3174#L1301-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3175#L571-36 assume 1 == ~t3_pc~0; 3556#L572-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3262#L582-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3263#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3451#L1309-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3950#L1309-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3231#L590-36 assume !(1 == ~t4_pc~0); 3232#L590-38 is_transmit4_triggered_~__retres1~4#1 := 0; 3848#L601-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3643#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3644#L1317-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 3929#L1317-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3930#L609-36 assume 1 == ~t5_pc~0; 3810#L610-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 3636#L620-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3637#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3974#L1325-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 3720#L1325-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3532#L628-36 assume 1 == ~t6_pc~0; 3382#L629-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 3383#L639-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3432#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3433#L1333-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 3761#L1333-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3762#L647-36 assume 1 == ~t7_pc~0; 3685#L648-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 2919#L658-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2920#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 2939#L1341-36 assume !(0 != activate_threads_~tmp___6~0#1); 2940#L1341-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3849#L666-36 assume 1 == ~t8_pc~0; 3128#L667-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 3129#L677-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3749#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 3750#L1349-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 3282#L1349-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3283#L685-36 assume 1 == ~t9_pc~0; 3736#L686-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 3034#L696-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3485#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 3486#L1357-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 3421#L1357-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 3422#L704-36 assume 1 == ~t10_pc~0; 3021#L705-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 3022#L715-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 3344#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 3345#L1365-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 3051#L1365-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3052#L1154-3 assume 1 == ~M_E~0;~M_E~0 := 2; 4021#L1154-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3905#L1159-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3906#L1164-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4081#L1169-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3350#L1174-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3351#L1179-3 assume !(1 == ~T6_E~0); 3996#L1184-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 2921#L1189-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 2922#L1194-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 3294#L1199-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 3295#L1204-3 assume 1 == ~E_M~0;~E_M~0 := 2; 3605#L1209-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2789#L1214-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2790#L1219-3 assume !(1 == ~E_3~0); 3805#L1224-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3806#L1229-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3825#L1234-3 assume 1 == ~E_6~0;~E_6~0 := 2; 3064#L1239-3 assume 1 == ~E_7~0;~E_7~0 := 2; 3065#L1244-3 assume 1 == ~E_8~0;~E_8~0 := 2; 3656#L1249-3 assume 1 == ~E_9~0;~E_9~0 := 2; 4028#L1254-3 assume 1 == ~E_10~0;~E_10~0 := 2; 3808#L1259-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 3809#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 2869#L851-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 3332#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 3333#L1584 assume !(0 == start_simulation_~tmp~3#1); 3767#L1584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 3078#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 2769#L851-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 2821#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 2822#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3400#L1546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3649#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 3650#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 2901#L1565-2 [2022-12-13 12:11:42,262 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:11:42,262 INFO L85 PathProgramCache]: Analyzing trace with hash -825627459, now seen corresponding path program 1 times [2022-12-13 12:11:42,262 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:11:42,262 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [990582472] [2022-12-13 12:11:42,262 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:11:42,263 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:11:42,280 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:11:42,337 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:11:42,338 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:11:42,338 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [990582472] [2022-12-13 12:11:42,338 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [990582472] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:11:42,338 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:11:42,338 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:11:42,339 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [817459510] [2022-12-13 12:11:42,339 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:11:42,339 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 12:11:42,340 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:11:42,340 INFO L85 PathProgramCache]: Analyzing trace with hash -1709033325, now seen corresponding path program 1 times [2022-12-13 12:11:42,340 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:11:42,340 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [912341186] [2022-12-13 12:11:42,341 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:11:42,341 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:11:42,369 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:11:42,438 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:11:42,438 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:11:42,438 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [912341186] [2022-12-13 12:11:42,438 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [912341186] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:11:42,439 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:11:42,439 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:11:42,439 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [846677710] [2022-12-13 12:11:42,439 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:11:42,439 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:11:42,440 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:11:42,440 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 12:11:42,440 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 12:11:42,441 INFO L87 Difference]: Start difference. First operand 1366 states and 2032 transitions. cyclomatic complexity: 667 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:11:42,479 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:11:42,479 INFO L93 Difference]: Finished difference Result 1366 states and 2031 transitions. [2022-12-13 12:11:42,479 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1366 states and 2031 transitions. [2022-12-13 12:11:42,484 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1227 [2022-12-13 12:11:42,487 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1366 states to 1366 states and 2031 transitions. [2022-12-13 12:11:42,487 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1366 [2022-12-13 12:11:42,488 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1366 [2022-12-13 12:11:42,488 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1366 states and 2031 transitions. [2022-12-13 12:11:42,490 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:11:42,490 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1366 states and 2031 transitions. [2022-12-13 12:11:42,491 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1366 states and 2031 transitions. [2022-12-13 12:11:42,502 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1366 to 1366. [2022-12-13 12:11:42,503 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1366 states, 1366 states have (on average 1.4868228404099562) internal successors, (2031), 1365 states have internal predecessors, (2031), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:11:42,506 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1366 states to 1366 states and 2031 transitions. [2022-12-13 12:11:42,506 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1366 states and 2031 transitions. [2022-12-13 12:11:42,506 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 12:11:42,507 INFO L428 stractBuchiCegarLoop]: Abstraction has 1366 states and 2031 transitions. [2022-12-13 12:11:42,507 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2022-12-13 12:11:42,507 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1366 states and 2031 transitions. [2022-12-13 12:11:42,511 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1227 [2022-12-13 12:11:42,511 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:11:42,511 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:11:42,513 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:11:42,513 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:11:42,514 INFO L748 eck$LassoCheckResult]: Stem: 5917#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 5918#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 6779#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 6780#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6841#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 6783#L731-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 6743#L736-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 6744#L741-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 6772#L746-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 5853#L751-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 5854#L756-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 5959#L761-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 6200#L766-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 6129#L771-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 5855#L776-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 5512#L781-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5513#L1036 assume !(0 == ~M_E~0); 5610#L1036-2 assume !(0 == ~T1_E~0); 6509#L1041-1 assume !(0 == ~T2_E~0); 6510#L1046-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5892#L1051-1 assume !(0 == ~T4_E~0); 5893#L1056-1 assume !(0 == ~T5_E~0); 6635#L1061-1 assume !(0 == ~T6_E~0); 5786#L1066-1 assume !(0 == ~T7_E~0); 5787#L1071-1 assume !(0 == ~T8_E~0); 6617#L1076-1 assume !(0 == ~T9_E~0); 5674#L1081-1 assume !(0 == ~T10_E~0); 5675#L1086-1 assume 0 == ~E_M~0;~E_M~0 := 1; 6076#L1091-1 assume !(0 == ~E_1~0); 6790#L1096-1 assume !(0 == ~E_2~0); 6791#L1101-1 assume !(0 == ~E_3~0); 6142#L1106-1 assume !(0 == ~E_4~0); 6143#L1111-1 assume !(0 == ~E_5~0); 6304#L1116-1 assume !(0 == ~E_6~0); 6305#L1121-1 assume !(0 == ~E_7~0); 6133#L1126-1 assume 0 == ~E_8~0;~E_8~0 := 1; 6134#L1131-1 assume !(0 == ~E_9~0); 6402#L1136-1 assume !(0 == ~E_10~0); 6515#L1141-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6662#L514 assume 1 == ~m_pc~0; 6628#L515 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 6151#L525 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6152#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6714#L1285 assume !(0 != activate_threads_~tmp~1#1); 6825#L1285-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5805#L533 assume !(1 == ~t1_pc~0); 5806#L533-2 is_transmit1_triggered_~__retres1~1#1 := 0; 6319#L544 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5565#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 5566#L1293 assume !(0 != activate_threads_~tmp___0~0#1); 6538#L1293-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6539#L552 assume 1 == ~t2_pc~0; 6023#L553 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 6024#L563 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6137#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 6138#L1301 assume !(0 != activate_threads_~tmp___1~0#1); 6164#L1301-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6165#L571 assume 1 == ~t3_pc~0; 6355#L572 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 6356#L582 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5510#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 5511#L1309 assume !(0 != activate_threads_~tmp___2~0#1); 6309#L1309-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5596#L590 assume !(1 == ~t4_pc~0); 5597#L590-2 is_transmit4_triggered_~__retres1~4#1 := 0; 6365#L601 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5692#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 5693#L1317 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 6564#L1317-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6306#L609 assume 1 == ~t5_pc~0; 6307#L610 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 6823#L620 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6716#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 6717#L1325 assume !(0 != activate_threads_~tmp___4~0#1); 6299#L1325-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6300#L628 assume !(1 == ~t6_pc~0); 6231#L628-2 is_transmit6_triggered_~__retres1~6#1 := 0; 6230#L639 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6110#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 6111#L1333 assume !(0 != activate_threads_~tmp___5~0#1); 6598#L1333-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6599#L647 assume 1 == ~t7_pc~0; 6144#L648 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 6145#L658 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 6725#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 6147#L1341 assume !(0 != activate_threads_~tmp___6~0#1); 6148#L1341-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 6852#L666 assume !(1 == ~t8_pc~0); 5939#L666-2 is_transmit8_triggered_~__retres1~8#1 := 0; 5940#L677 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 6163#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 6330#L1349 assume !(0 != activate_threads_~tmp___7~0#1); 6073#L1349-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 6074#L685 assume 1 == ~t9_pc~0; 6831#L686 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 6733#L696 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 6194#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 6101#L1357 assume !(0 != activate_threads_~tmp___8~0#1); 6102#L1357-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 6480#L704 assume !(1 == ~t10_pc~0); 6093#L704-2 is_transmit10_triggered_~__retres1~10#1 := 0; 6092#L715 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 6344#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 5644#L1365 assume !(0 != activate_threads_~tmp___9~0#1); 5645#L1365-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5901#L1154 assume !(1 == ~M_E~0); 6586#L1154-2 assume !(1 == ~T1_E~0); 5873#L1159-1 assume !(1 == ~T2_E~0); 5874#L1164-1 assume !(1 == ~T3_E~0); 6328#L1169-1 assume !(1 == ~T4_E~0); 6195#L1174-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 6001#L1179-1 assume !(1 == ~T6_E~0); 5859#L1184-1 assume !(1 == ~T7_E~0); 5860#L1189-1 assume !(1 == ~T8_E~0); 5937#L1194-1 assume !(1 == ~T9_E~0); 6060#L1199-1 assume !(1 == ~T10_E~0); 6013#L1204-1 assume !(1 == ~E_M~0); 6014#L1209-1 assume !(1 == ~E_1~0); 6558#L1214-1 assume 1 == ~E_2~0;~E_2~0 := 2; 6559#L1219-1 assume !(1 == ~E_3~0); 6845#L1224-1 assume !(1 == ~E_4~0); 6348#L1229-1 assume !(1 == ~E_5~0); 5741#L1234-1 assume !(1 == ~E_6~0); 5742#L1239-1 assume !(1 == ~E_7~0); 5801#L1244-1 assume !(1 == ~E_8~0); 5802#L1249-1 assume !(1 == ~E_9~0); 6626#L1254-1 assume 1 == ~E_10~0;~E_10~0 := 2; 5639#L1259-1 assume { :end_inline_reset_delta_events } true; 5640#L1565-2 [2022-12-13 12:11:42,514 INFO L750 eck$LassoCheckResult]: Loop: 5640#L1565-2 assume !false; 6566#L1566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5591#L1011 assume !false; 6030#L862 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 6078#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 5842#L851 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 6175#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 5865#L866 assume !(0 != eval_~tmp~0#1); 5867#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 6367#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 6368#L1036-3 assume 0 == ~M_E~0;~M_E~0 := 1; 6630#L1036-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 6808#L1041-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 6690#L1046-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 6691#L1051-3 assume !(0 == ~T4_E~0); 6631#L1056-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 5889#L1061-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 5890#L1066-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 5891#L1071-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 6810#L1076-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 5631#L1081-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 5632#L1086-3 assume 0 == ~E_M~0;~E_M~0 := 1; 5684#L1091-3 assume !(0 == ~E_1~0); 5685#L1096-3 assume 0 == ~E_2~0;~E_2~0 := 1; 6774#L1101-3 assume 0 == ~E_3~0;~E_3~0 := 1; 6775#L1106-3 assume 0 == ~E_4~0;~E_4~0 := 1; 6807#L1111-3 assume 0 == ~E_5~0;~E_5~0 := 1; 6766#L1116-3 assume 0 == ~E_6~0;~E_6~0 := 1; 6495#L1121-3 assume 0 == ~E_7~0;~E_7~0 := 1; 6496#L1126-3 assume 0 == ~E_8~0;~E_8~0 := 1; 6705#L1131-3 assume !(0 == ~E_9~0); 6706#L1136-3 assume 0 == ~E_10~0;~E_10~0 := 1; 6857#L1141-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6498#L514-36 assume !(1 == ~m_pc~0); 6211#L514-38 is_master_triggered_~__retres1~0#1 := 0; 6051#L525-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6052#is_master_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6537#L1285-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 5946#L1285-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5947#L533-36 assume 1 == ~t1_pc~0; 6220#L534-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 6313#L544-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6756#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 6574#L1293-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 6372#L1293-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6373#L552-36 assume 1 == ~t2_pc~0; 5941#L553-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5943#L563-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6431#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 6698#L1301-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 5913#L1301-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5914#L571-36 assume 1 == ~t3_pc~0; 6295#L572-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 6002#L582-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6003#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 6190#L1309-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 6689#L1309-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5973#L590-36 assume !(1 == ~t4_pc~0); 5974#L590-38 is_transmit4_triggered_~__retres1~4#1 := 0; 6587#L601-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6382#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 6383#L1317-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 6668#L1317-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6669#L609-36 assume 1 == ~t5_pc~0; 6549#L610-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 6375#L620-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6376#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 6713#L1325-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 6459#L1325-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6271#L628-36 assume 1 == ~t6_pc~0; 6121#L629-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 6122#L639-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6171#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 6172#L1333-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 6500#L1333-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6501#L647-36 assume 1 == ~t7_pc~0; 6424#L648-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 5658#L658-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5659#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 5678#L1341-36 assume !(0 != activate_threads_~tmp___6~0#1); 5679#L1341-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 6588#L666-36 assume !(1 == ~t8_pc~0); 5872#L666-38 is_transmit8_triggered_~__retres1~8#1 := 0; 5871#L677-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 6488#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 6489#L1349-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 6021#L1349-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 6022#L685-36 assume 1 == ~t9_pc~0; 6475#L686-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 5773#L696-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 6224#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 6225#L1357-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 6160#L1357-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 6161#L704-36 assume 1 == ~t10_pc~0; 5760#L705-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 5761#L715-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 6083#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 6084#L1365-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 5790#L1365-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5791#L1154-3 assume 1 == ~M_E~0;~M_E~0 := 2; 6760#L1154-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 6644#L1159-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 6645#L1164-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 6820#L1169-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 6089#L1174-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 6090#L1179-3 assume !(1 == ~T6_E~0); 6735#L1184-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 5660#L1189-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 5661#L1194-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 6033#L1199-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 6034#L1204-3 assume 1 == ~E_M~0;~E_M~0 := 2; 6345#L1209-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5528#L1214-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5529#L1219-3 assume !(1 == ~E_3~0); 6544#L1224-3 assume 1 == ~E_4~0;~E_4~0 := 2; 6545#L1229-3 assume 1 == ~E_5~0;~E_5~0 := 2; 6565#L1234-3 assume 1 == ~E_6~0;~E_6~0 := 2; 5803#L1239-3 assume 1 == ~E_7~0;~E_7~0 := 2; 5804#L1244-3 assume 1 == ~E_8~0;~E_8~0 := 2; 6399#L1249-3 assume 1 == ~E_9~0;~E_9~0 := 2; 6767#L1254-3 assume 1 == ~E_10~0;~E_10~0 := 2; 6547#L1259-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 6548#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 5608#L851-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 6071#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 6072#L1584 assume !(0 == start_simulation_~tmp~3#1); 6506#L1584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 5817#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 5508#L851-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 5560#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 5561#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 6140#L1546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 6388#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 6389#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 5640#L1565-2 [2022-12-13 12:11:42,515 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:11:42,515 INFO L85 PathProgramCache]: Analyzing trace with hash 1224781439, now seen corresponding path program 1 times [2022-12-13 12:11:42,516 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:11:42,516 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1761406586] [2022-12-13 12:11:42,516 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:11:42,516 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:11:42,531 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:11:42,567 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:11:42,567 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:11:42,567 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1761406586] [2022-12-13 12:11:42,568 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1761406586] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:11:42,568 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:11:42,568 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:11:42,568 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1786780073] [2022-12-13 12:11:42,568 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:11:42,569 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 12:11:42,569 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:11:42,569 INFO L85 PathProgramCache]: Analyzing trace with hash -1982811820, now seen corresponding path program 1 times [2022-12-13 12:11:42,570 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:11:42,570 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [746129814] [2022-12-13 12:11:42,570 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:11:42,570 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:11:42,585 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:11:42,625 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:11:42,625 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:11:42,625 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [746129814] [2022-12-13 12:11:42,626 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [746129814] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:11:42,626 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:11:42,626 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:11:42,626 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [657889503] [2022-12-13 12:11:42,626 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:11:42,627 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:11:42,627 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:11:42,627 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 12:11:42,628 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 12:11:42,628 INFO L87 Difference]: Start difference. First operand 1366 states and 2031 transitions. cyclomatic complexity: 666 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:11:42,647 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:11:42,647 INFO L93 Difference]: Finished difference Result 1366 states and 2030 transitions. [2022-12-13 12:11:42,647 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1366 states and 2030 transitions. [2022-12-13 12:11:42,652 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1227 [2022-12-13 12:11:42,655 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1366 states to 1366 states and 2030 transitions. [2022-12-13 12:11:42,656 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1366 [2022-12-13 12:11:42,656 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1366 [2022-12-13 12:11:42,657 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1366 states and 2030 transitions. [2022-12-13 12:11:42,658 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:11:42,658 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1366 states and 2030 transitions. [2022-12-13 12:11:42,660 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1366 states and 2030 transitions. [2022-12-13 12:11:42,676 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1366 to 1366. [2022-12-13 12:11:42,678 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1366 states, 1366 states have (on average 1.4860907759882869) internal successors, (2030), 1365 states have internal predecessors, (2030), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:11:42,681 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1366 states to 1366 states and 2030 transitions. [2022-12-13 12:11:42,681 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1366 states and 2030 transitions. [2022-12-13 12:11:42,681 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 12:11:42,682 INFO L428 stractBuchiCegarLoop]: Abstraction has 1366 states and 2030 transitions. [2022-12-13 12:11:42,682 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2022-12-13 12:11:42,682 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1366 states and 2030 transitions. [2022-12-13 12:11:42,686 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1227 [2022-12-13 12:11:42,686 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:11:42,686 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:11:42,688 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:11:42,688 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:11:42,688 INFO L748 eck$LassoCheckResult]: Stem: 8656#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 8657#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 9518#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 9519#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 9580#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 9522#L731-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 9482#L736-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 9483#L741-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 9511#L746-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 8592#L751-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 8593#L756-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 8698#L761-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 8939#L766-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 8868#L771-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 8594#L776-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 8251#L781-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8252#L1036 assume !(0 == ~M_E~0); 8349#L1036-2 assume !(0 == ~T1_E~0); 9248#L1041-1 assume !(0 == ~T2_E~0); 9249#L1046-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 8631#L1051-1 assume !(0 == ~T4_E~0); 8632#L1056-1 assume !(0 == ~T5_E~0); 9374#L1061-1 assume !(0 == ~T6_E~0); 8525#L1066-1 assume !(0 == ~T7_E~0); 8526#L1071-1 assume !(0 == ~T8_E~0); 9356#L1076-1 assume !(0 == ~T9_E~0); 8413#L1081-1 assume !(0 == ~T10_E~0); 8414#L1086-1 assume 0 == ~E_M~0;~E_M~0 := 1; 8815#L1091-1 assume !(0 == ~E_1~0); 9529#L1096-1 assume !(0 == ~E_2~0); 9530#L1101-1 assume !(0 == ~E_3~0); 8881#L1106-1 assume !(0 == ~E_4~0); 8882#L1111-1 assume !(0 == ~E_5~0); 9043#L1116-1 assume !(0 == ~E_6~0); 9044#L1121-1 assume !(0 == ~E_7~0); 8872#L1126-1 assume 0 == ~E_8~0;~E_8~0 := 1; 8873#L1131-1 assume !(0 == ~E_9~0); 9141#L1136-1 assume !(0 == ~E_10~0); 9254#L1141-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9401#L514 assume 1 == ~m_pc~0; 9367#L515 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 8890#L525 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8891#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 9453#L1285 assume !(0 != activate_threads_~tmp~1#1); 9564#L1285-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8544#L533 assume !(1 == ~t1_pc~0); 8545#L533-2 is_transmit1_triggered_~__retres1~1#1 := 0; 9058#L544 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8304#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 8305#L1293 assume !(0 != activate_threads_~tmp___0~0#1); 9277#L1293-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9278#L552 assume 1 == ~t2_pc~0; 8762#L553 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 8763#L563 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8876#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8877#L1301 assume !(0 != activate_threads_~tmp___1~0#1); 8903#L1301-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8904#L571 assume 1 == ~t3_pc~0; 9094#L572 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 9095#L582 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8249#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8250#L1309 assume !(0 != activate_threads_~tmp___2~0#1); 9048#L1309-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8335#L590 assume !(1 == ~t4_pc~0); 8336#L590-2 is_transmit4_triggered_~__retres1~4#1 := 0; 9104#L601 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8431#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 8432#L1317 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 9303#L1317-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9045#L609 assume 1 == ~t5_pc~0; 9046#L610 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 9562#L620 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9455#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 9456#L1325 assume !(0 != activate_threads_~tmp___4~0#1); 9038#L1325-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 9039#L628 assume !(1 == ~t6_pc~0); 8970#L628-2 is_transmit6_triggered_~__retres1~6#1 := 0; 8969#L639 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8849#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 8850#L1333 assume !(0 != activate_threads_~tmp___5~0#1); 9337#L1333-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9338#L647 assume 1 == ~t7_pc~0; 8883#L648 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 8884#L658 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 9464#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 8886#L1341 assume !(0 != activate_threads_~tmp___6~0#1); 8887#L1341-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 9591#L666 assume !(1 == ~t8_pc~0); 8678#L666-2 is_transmit8_triggered_~__retres1~8#1 := 0; 8679#L677 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 8902#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 9069#L1349 assume !(0 != activate_threads_~tmp___7~0#1); 8812#L1349-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 8813#L685 assume 1 == ~t9_pc~0; 9570#L686 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 9472#L696 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 8933#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 8840#L1357 assume !(0 != activate_threads_~tmp___8~0#1); 8841#L1357-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 9219#L704 assume !(1 == ~t10_pc~0); 8832#L704-2 is_transmit10_triggered_~__retres1~10#1 := 0; 8831#L715 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 9083#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 8383#L1365 assume !(0 != activate_threads_~tmp___9~0#1); 8384#L1365-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8640#L1154 assume !(1 == ~M_E~0); 9325#L1154-2 assume !(1 == ~T1_E~0); 8612#L1159-1 assume !(1 == ~T2_E~0); 8613#L1164-1 assume !(1 == ~T3_E~0); 9067#L1169-1 assume !(1 == ~T4_E~0); 8934#L1174-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 8740#L1179-1 assume !(1 == ~T6_E~0); 8598#L1184-1 assume !(1 == ~T7_E~0); 8599#L1189-1 assume !(1 == ~T8_E~0); 8676#L1194-1 assume !(1 == ~T9_E~0); 8799#L1199-1 assume !(1 == ~T10_E~0); 8752#L1204-1 assume !(1 == ~E_M~0); 8753#L1209-1 assume !(1 == ~E_1~0); 9297#L1214-1 assume 1 == ~E_2~0;~E_2~0 := 2; 9298#L1219-1 assume !(1 == ~E_3~0); 9584#L1224-1 assume !(1 == ~E_4~0); 9087#L1229-1 assume !(1 == ~E_5~0); 8480#L1234-1 assume !(1 == ~E_6~0); 8481#L1239-1 assume !(1 == ~E_7~0); 8540#L1244-1 assume !(1 == ~E_8~0); 8541#L1249-1 assume !(1 == ~E_9~0); 9365#L1254-1 assume 1 == ~E_10~0;~E_10~0 := 2; 8378#L1259-1 assume { :end_inline_reset_delta_events } true; 8379#L1565-2 [2022-12-13 12:11:42,688 INFO L750 eck$LassoCheckResult]: Loop: 8379#L1565-2 assume !false; 9305#L1566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 8330#L1011 assume !false; 8769#L862 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 8817#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 8581#L851 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 8914#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 8604#L866 assume !(0 != eval_~tmp~0#1); 8606#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 9106#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 9107#L1036-3 assume 0 == ~M_E~0;~M_E~0 := 1; 9369#L1036-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 9547#L1041-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 9429#L1046-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 9430#L1051-3 assume !(0 == ~T4_E~0); 9370#L1056-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 8628#L1061-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 8629#L1066-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 8630#L1071-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 9549#L1076-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 8370#L1081-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 8371#L1086-3 assume 0 == ~E_M~0;~E_M~0 := 1; 8423#L1091-3 assume !(0 == ~E_1~0); 8424#L1096-3 assume 0 == ~E_2~0;~E_2~0 := 1; 9513#L1101-3 assume 0 == ~E_3~0;~E_3~0 := 1; 9514#L1106-3 assume 0 == ~E_4~0;~E_4~0 := 1; 9546#L1111-3 assume 0 == ~E_5~0;~E_5~0 := 1; 9505#L1116-3 assume 0 == ~E_6~0;~E_6~0 := 1; 9234#L1121-3 assume 0 == ~E_7~0;~E_7~0 := 1; 9235#L1126-3 assume 0 == ~E_8~0;~E_8~0 := 1; 9444#L1131-3 assume !(0 == ~E_9~0); 9445#L1136-3 assume 0 == ~E_10~0;~E_10~0 := 1; 9596#L1141-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9237#L514-36 assume !(1 == ~m_pc~0); 8950#L514-38 is_master_triggered_~__retres1~0#1 := 0; 8790#L525-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8791#is_master_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 9276#L1285-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 8685#L1285-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8686#L533-36 assume !(1 == ~t1_pc~0); 8960#L533-38 is_transmit1_triggered_~__retres1~1#1 := 0; 9052#L544-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9495#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 9313#L1293-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 9111#L1293-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9112#L552-36 assume 1 == ~t2_pc~0; 8680#L553-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 8682#L563-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9170#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 9437#L1301-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 8652#L1301-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8653#L571-36 assume 1 == ~t3_pc~0; 9034#L572-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 8741#L582-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8742#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8929#L1309-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 9428#L1309-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8712#L590-36 assume !(1 == ~t4_pc~0); 8713#L590-38 is_transmit4_triggered_~__retres1~4#1 := 0; 9326#L601-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9121#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 9122#L1317-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 9407#L1317-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9408#L609-36 assume 1 == ~t5_pc~0; 9288#L610-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 9114#L620-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9115#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 9452#L1325-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 9198#L1325-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 9010#L628-36 assume 1 == ~t6_pc~0; 8860#L629-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 8861#L639-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8910#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 8911#L1333-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 9239#L1333-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9240#L647-36 assume 1 == ~t7_pc~0; 9163#L648-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 8397#L658-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8398#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 8417#L1341-36 assume !(0 != activate_threads_~tmp___6~0#1); 8418#L1341-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 9327#L666-36 assume 1 == ~t8_pc~0; 8609#L667-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 8610#L677-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 9227#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 9228#L1349-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 8760#L1349-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 8761#L685-36 assume 1 == ~t9_pc~0; 9214#L686-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 8512#L696-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 8963#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 8964#L1357-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 8899#L1357-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 8900#L704-36 assume 1 == ~t10_pc~0; 8499#L705-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 8500#L715-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 8822#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 8823#L1365-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 8529#L1365-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8530#L1154-3 assume 1 == ~M_E~0;~M_E~0 := 2; 9499#L1154-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 9383#L1159-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 9384#L1164-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 9559#L1169-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8828#L1174-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 8829#L1179-3 assume !(1 == ~T6_E~0); 9474#L1184-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 8399#L1189-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 8400#L1194-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 8772#L1199-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 8773#L1204-3 assume 1 == ~E_M~0;~E_M~0 := 2; 9084#L1209-3 assume 1 == ~E_1~0;~E_1~0 := 2; 8267#L1214-3 assume 1 == ~E_2~0;~E_2~0 := 2; 8268#L1219-3 assume !(1 == ~E_3~0); 9283#L1224-3 assume 1 == ~E_4~0;~E_4~0 := 2; 9284#L1229-3 assume 1 == ~E_5~0;~E_5~0 := 2; 9304#L1234-3 assume 1 == ~E_6~0;~E_6~0 := 2; 8542#L1239-3 assume 1 == ~E_7~0;~E_7~0 := 2; 8543#L1244-3 assume 1 == ~E_8~0;~E_8~0 := 2; 9138#L1249-3 assume 1 == ~E_9~0;~E_9~0 := 2; 9506#L1254-3 assume 1 == ~E_10~0;~E_10~0 := 2; 9286#L1259-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 9287#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 8347#L851-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 8810#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 8811#L1584 assume !(0 == start_simulation_~tmp~3#1); 9245#L1584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 8556#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 8247#L851-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 8299#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 8300#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 8879#L1546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 9127#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 9128#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 8379#L1565-2 [2022-12-13 12:11:42,689 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:11:42,689 INFO L85 PathProgramCache]: Analyzing trace with hash 736734333, now seen corresponding path program 1 times [2022-12-13 12:11:42,689 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:11:42,689 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1732192615] [2022-12-13 12:11:42,690 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:11:42,690 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:11:42,701 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:11:42,726 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:11:42,726 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:11:42,726 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1732192615] [2022-12-13 12:11:42,726 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1732192615] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:11:42,726 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:11:42,726 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:11:42,727 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1748043845] [2022-12-13 12:11:42,727 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:11:42,727 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 12:11:42,728 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:11:42,728 INFO L85 PathProgramCache]: Analyzing trace with hash -1836109804, now seen corresponding path program 1 times [2022-12-13 12:11:42,728 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:11:42,728 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1005527674] [2022-12-13 12:11:42,728 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:11:42,728 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:11:42,753 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:11:42,797 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:11:42,798 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:11:42,798 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1005527674] [2022-12-13 12:11:42,798 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1005527674] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:11:42,798 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:11:42,798 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:11:42,799 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1660772390] [2022-12-13 12:11:42,799 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:11:42,799 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:11:42,799 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:11:42,800 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 12:11:42,800 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 12:11:42,800 INFO L87 Difference]: Start difference. First operand 1366 states and 2030 transitions. cyclomatic complexity: 665 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:11:42,831 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:11:42,831 INFO L93 Difference]: Finished difference Result 1366 states and 2029 transitions. [2022-12-13 12:11:42,831 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1366 states and 2029 transitions. [2022-12-13 12:11:42,837 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1227 [2022-12-13 12:11:42,841 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1366 states to 1366 states and 2029 transitions. [2022-12-13 12:11:42,842 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1366 [2022-12-13 12:11:42,843 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1366 [2022-12-13 12:11:42,843 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1366 states and 2029 transitions. [2022-12-13 12:11:42,844 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:11:42,844 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1366 states and 2029 transitions. [2022-12-13 12:11:42,846 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1366 states and 2029 transitions. [2022-12-13 12:11:42,860 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1366 to 1366. [2022-12-13 12:11:42,862 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1366 states, 1366 states have (on average 1.4853587115666178) internal successors, (2029), 1365 states have internal predecessors, (2029), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:11:42,866 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1366 states to 1366 states and 2029 transitions. [2022-12-13 12:11:42,866 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1366 states and 2029 transitions. [2022-12-13 12:11:42,866 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 12:11:42,867 INFO L428 stractBuchiCegarLoop]: Abstraction has 1366 states and 2029 transitions. [2022-12-13 12:11:42,867 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2022-12-13 12:11:42,867 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1366 states and 2029 transitions. [2022-12-13 12:11:42,872 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1227 [2022-12-13 12:11:42,872 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:11:42,873 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:11:42,874 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:11:42,874 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:11:42,875 INFO L748 eck$LassoCheckResult]: Stem: 11395#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 11396#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 12257#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 12258#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 12319#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 12261#L731-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 12221#L736-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 12222#L741-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 12250#L746-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 11333#L751-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 11334#L756-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 11437#L761-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 11678#L766-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 11607#L771-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 11335#L776-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 10990#L781-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 10991#L1036 assume !(0 == ~M_E~0); 11088#L1036-2 assume !(0 == ~T1_E~0); 11987#L1041-1 assume !(0 == ~T2_E~0); 11988#L1046-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 11370#L1051-1 assume !(0 == ~T4_E~0); 11371#L1056-1 assume !(0 == ~T5_E~0); 12113#L1061-1 assume !(0 == ~T6_E~0); 11264#L1066-1 assume !(0 == ~T7_E~0); 11265#L1071-1 assume !(0 == ~T8_E~0); 12095#L1076-1 assume !(0 == ~T9_E~0); 11152#L1081-1 assume !(0 == ~T10_E~0); 11153#L1086-1 assume 0 == ~E_M~0;~E_M~0 := 1; 11554#L1091-1 assume !(0 == ~E_1~0); 12269#L1096-1 assume !(0 == ~E_2~0); 12270#L1101-1 assume !(0 == ~E_3~0); 11620#L1106-1 assume !(0 == ~E_4~0); 11621#L1111-1 assume !(0 == ~E_5~0); 11782#L1116-1 assume !(0 == ~E_6~0); 11783#L1121-1 assume !(0 == ~E_7~0); 11611#L1126-1 assume 0 == ~E_8~0;~E_8~0 := 1; 11612#L1131-1 assume !(0 == ~E_9~0); 11880#L1136-1 assume !(0 == ~E_10~0); 11993#L1141-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12140#L514 assume 1 == ~m_pc~0; 12106#L515 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 11629#L525 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11630#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 12192#L1285 assume !(0 != activate_threads_~tmp~1#1); 12304#L1285-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11283#L533 assume !(1 == ~t1_pc~0); 11284#L533-2 is_transmit1_triggered_~__retres1~1#1 := 0; 11797#L544 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11045#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 11046#L1293 assume !(0 != activate_threads_~tmp___0~0#1); 12016#L1293-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12017#L552 assume 1 == ~t2_pc~0; 11502#L553 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 11503#L563 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11615#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 11616#L1301 assume !(0 != activate_threads_~tmp___1~0#1); 11647#L1301-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11648#L571 assume 1 == ~t3_pc~0; 11835#L572 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 11836#L582 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10988#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 10989#L1309 assume !(0 != activate_threads_~tmp___2~0#1); 11787#L1309-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 11074#L590 assume !(1 == ~t4_pc~0); 11075#L590-2 is_transmit4_triggered_~__retres1~4#1 := 0; 11843#L601 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 11170#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 11171#L1317 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 12043#L1317-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 11784#L609 assume 1 == ~t5_pc~0; 11785#L610 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 12301#L620 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12194#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 12195#L1325 assume !(0 != activate_threads_~tmp___4~0#1); 11777#L1325-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11778#L628 assume !(1 == ~t6_pc~0); 11709#L628-2 is_transmit6_triggered_~__retres1~6#1 := 0; 11708#L639 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11589#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 11590#L1333 assume !(0 != activate_threads_~tmp___5~0#1); 12076#L1333-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12077#L647 assume 1 == ~t7_pc~0; 11622#L648 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 11623#L658 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 12203#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 11627#L1341 assume !(0 != activate_threads_~tmp___6~0#1); 11628#L1341-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 12330#L666 assume !(1 == ~t8_pc~0); 11417#L666-2 is_transmit8_triggered_~__retres1~8#1 := 0; 11418#L677 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 11641#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 11809#L1349 assume !(0 != activate_threads_~tmp___7~0#1); 11552#L1349-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 11553#L685 assume 1 == ~t9_pc~0; 12309#L686 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 12211#L696 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 11672#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 11579#L1357 assume !(0 != activate_threads_~tmp___8~0#1); 11580#L1357-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 11958#L704 assume !(1 == ~t10_pc~0); 11571#L704-2 is_transmit10_triggered_~__retres1~10#1 := 0; 11570#L715 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 11823#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 11122#L1365 assume !(0 != activate_threads_~tmp___9~0#1); 11123#L1365-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11379#L1154 assume !(1 == ~M_E~0); 12064#L1154-2 assume !(1 == ~T1_E~0); 11351#L1159-1 assume !(1 == ~T2_E~0); 11352#L1164-1 assume !(1 == ~T3_E~0); 11806#L1169-1 assume !(1 == ~T4_E~0); 11673#L1174-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 11481#L1179-1 assume !(1 == ~T6_E~0); 11337#L1184-1 assume !(1 == ~T7_E~0); 11338#L1189-1 assume !(1 == ~T8_E~0); 11415#L1194-1 assume !(1 == ~T9_E~0); 11540#L1199-1 assume !(1 == ~T10_E~0); 11493#L1204-1 assume !(1 == ~E_M~0); 11494#L1209-1 assume !(1 == ~E_1~0); 12038#L1214-1 assume 1 == ~E_2~0;~E_2~0 := 2; 12039#L1219-1 assume !(1 == ~E_3~0); 12323#L1224-1 assume !(1 == ~E_4~0); 11827#L1229-1 assume !(1 == ~E_5~0); 11219#L1234-1 assume !(1 == ~E_6~0); 11220#L1239-1 assume !(1 == ~E_7~0); 11279#L1244-1 assume !(1 == ~E_8~0); 11280#L1249-1 assume !(1 == ~E_9~0); 12104#L1254-1 assume 1 == ~E_10~0;~E_10~0 := 2; 11117#L1259-1 assume { :end_inline_reset_delta_events } true; 11118#L1565-2 [2022-12-13 12:11:42,875 INFO L750 eck$LassoCheckResult]: Loop: 11118#L1565-2 assume !false; 12044#L1566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 11069#L1011 assume !false; 11508#L862 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 11556#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 11320#L851 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 11653#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 11348#L866 assume !(0 != eval_~tmp~0#1); 11350#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 11846#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 11847#L1036-3 assume 0 == ~M_E~0;~M_E~0 := 1; 12108#L1036-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 12286#L1041-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 12168#L1046-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 12169#L1051-3 assume !(0 == ~T4_E~0); 12109#L1056-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 11367#L1061-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 11368#L1066-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 11369#L1071-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 12288#L1076-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 11109#L1081-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 11110#L1086-3 assume 0 == ~E_M~0;~E_M~0 := 1; 11166#L1091-3 assume !(0 == ~E_1~0); 11167#L1096-3 assume 0 == ~E_2~0;~E_2~0 := 1; 12252#L1101-3 assume 0 == ~E_3~0;~E_3~0 := 1; 12253#L1106-3 assume 0 == ~E_4~0;~E_4~0 := 1; 12285#L1111-3 assume 0 == ~E_5~0;~E_5~0 := 1; 12244#L1116-3 assume 0 == ~E_6~0;~E_6~0 := 1; 11973#L1121-3 assume 0 == ~E_7~0;~E_7~0 := 1; 11974#L1126-3 assume 0 == ~E_8~0;~E_8~0 := 1; 12183#L1131-3 assume !(0 == ~E_9~0); 12184#L1136-3 assume 0 == ~E_10~0;~E_10~0 := 1; 12335#L1141-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11976#L514-36 assume !(1 == ~m_pc~0); 11689#L514-38 is_master_triggered_~__retres1~0#1 := 0; 11529#L525-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11530#is_master_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 12015#L1285-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 11424#L1285-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11425#L533-36 assume 1 == ~t1_pc~0; 11698#L534-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 11794#L544-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12234#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 12052#L1293-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 11850#L1293-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11851#L552-36 assume 1 == ~t2_pc~0; 11419#L553-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 11421#L563-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11909#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 12176#L1301-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 11391#L1301-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11392#L571-36 assume 1 == ~t3_pc~0; 11773#L572-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 11479#L582-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11480#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 11668#L1309-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 12167#L1309-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 11448#L590-36 assume !(1 == ~t4_pc~0); 11449#L590-38 is_transmit4_triggered_~__retres1~4#1 := 0; 12065#L601-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 11860#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 11861#L1317-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 12146#L1317-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 12147#L609-36 assume 1 == ~t5_pc~0; 12027#L610-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 11853#L620-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 11854#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 12191#L1325-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 11937#L1325-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11749#L628-36 assume !(1 == ~t6_pc~0); 11601#L628-38 is_transmit6_triggered_~__retres1~6#1 := 0; 11600#L639-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11649#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 11650#L1333-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 11978#L1333-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 11979#L647-36 assume 1 == ~t7_pc~0; 11902#L648-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 11136#L658-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 11137#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 11156#L1341-36 assume !(0 != activate_threads_~tmp___6~0#1); 11157#L1341-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 12066#L666-36 assume 1 == ~t8_pc~0; 11345#L667-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 11346#L677-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 11966#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 11967#L1349-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 11499#L1349-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 11500#L685-36 assume 1 == ~t9_pc~0; 11953#L686-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 11251#L696-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 11702#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 11703#L1357-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 11638#L1357-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 11639#L704-36 assume 1 == ~t10_pc~0; 11238#L705-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 11239#L715-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 11561#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 11562#L1365-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 11268#L1365-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11269#L1154-3 assume 1 == ~M_E~0;~M_E~0 := 2; 12238#L1154-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 12122#L1159-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 12123#L1164-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 12298#L1169-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 11567#L1174-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 11568#L1179-3 assume !(1 == ~T6_E~0); 12213#L1184-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 11138#L1189-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 11139#L1194-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 11511#L1199-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 11512#L1204-3 assume 1 == ~E_M~0;~E_M~0 := 2; 11822#L1209-3 assume 1 == ~E_1~0;~E_1~0 := 2; 11006#L1214-3 assume 1 == ~E_2~0;~E_2~0 := 2; 11007#L1219-3 assume !(1 == ~E_3~0); 12022#L1224-3 assume 1 == ~E_4~0;~E_4~0 := 2; 12023#L1229-3 assume 1 == ~E_5~0;~E_5~0 := 2; 12042#L1234-3 assume 1 == ~E_6~0;~E_6~0 := 2; 11281#L1239-3 assume 1 == ~E_7~0;~E_7~0 := 2; 11282#L1244-3 assume 1 == ~E_8~0;~E_8~0 := 2; 11873#L1249-3 assume 1 == ~E_9~0;~E_9~0 := 2; 12245#L1254-3 assume 1 == ~E_10~0;~E_10~0 := 2; 12025#L1259-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 12026#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 11086#L851-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 11549#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 11550#L1584 assume !(0 == start_simulation_~tmp~3#1); 11984#L1584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 11295#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 10986#L851-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 11038#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 11039#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 11617#L1546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 11866#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 11867#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 11118#L1565-2 [2022-12-13 12:11:42,875 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:11:42,875 INFO L85 PathProgramCache]: Analyzing trace with hash 1829369535, now seen corresponding path program 1 times [2022-12-13 12:11:42,876 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:11:42,876 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1733908370] [2022-12-13 12:11:42,876 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:11:42,876 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:11:42,884 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:11:42,905 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:11:42,905 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:11:42,905 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1733908370] [2022-12-13 12:11:42,905 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1733908370] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:11:42,906 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:11:42,906 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:11:42,906 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [224022458] [2022-12-13 12:11:42,906 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:11:42,906 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 12:11:42,907 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:11:42,907 INFO L85 PathProgramCache]: Analyzing trace with hash -1331390508, now seen corresponding path program 1 times [2022-12-13 12:11:42,907 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:11:42,907 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [169788844] [2022-12-13 12:11:42,907 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:11:42,907 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:11:42,916 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:11:42,943 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:11:42,944 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:11:42,944 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [169788844] [2022-12-13 12:11:42,944 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [169788844] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:11:42,944 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:11:42,944 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:11:42,944 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1418425017] [2022-12-13 12:11:42,944 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:11:42,945 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:11:42,945 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:11:42,945 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 12:11:42,945 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 12:11:42,946 INFO L87 Difference]: Start difference. First operand 1366 states and 2029 transitions. cyclomatic complexity: 664 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:11:42,963 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:11:42,963 INFO L93 Difference]: Finished difference Result 1366 states and 2028 transitions. [2022-12-13 12:11:42,963 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1366 states and 2028 transitions. [2022-12-13 12:11:42,968 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1227 [2022-12-13 12:11:42,972 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1366 states to 1366 states and 2028 transitions. [2022-12-13 12:11:42,972 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1366 [2022-12-13 12:11:42,973 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1366 [2022-12-13 12:11:42,973 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1366 states and 2028 transitions. [2022-12-13 12:11:42,974 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:11:42,974 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1366 states and 2028 transitions. [2022-12-13 12:11:42,975 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1366 states and 2028 transitions. [2022-12-13 12:11:42,985 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1366 to 1366. [2022-12-13 12:11:42,987 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1366 states, 1366 states have (on average 1.4846266471449487) internal successors, (2028), 1365 states have internal predecessors, (2028), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:11:42,990 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1366 states to 1366 states and 2028 transitions. [2022-12-13 12:11:42,990 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1366 states and 2028 transitions. [2022-12-13 12:11:42,990 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 12:11:42,990 INFO L428 stractBuchiCegarLoop]: Abstraction has 1366 states and 2028 transitions. [2022-12-13 12:11:42,991 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2022-12-13 12:11:42,991 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1366 states and 2028 transitions. [2022-12-13 12:11:42,994 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1227 [2022-12-13 12:11:42,995 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:11:42,995 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:11:42,996 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:11:42,996 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:11:42,996 INFO L748 eck$LassoCheckResult]: Stem: 14134#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 14135#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 14996#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 14997#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 15058#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 15000#L731-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 14960#L736-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 14961#L741-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 14989#L746-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 14070#L751-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 14071#L756-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 14176#L761-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 14417#L766-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 14346#L771-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 14072#L776-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 13729#L781-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 13730#L1036 assume !(0 == ~M_E~0); 13827#L1036-2 assume !(0 == ~T1_E~0); 14726#L1041-1 assume !(0 == ~T2_E~0); 14727#L1046-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 14109#L1051-1 assume !(0 == ~T4_E~0); 14110#L1056-1 assume !(0 == ~T5_E~0); 14852#L1061-1 assume !(0 == ~T6_E~0); 14003#L1066-1 assume !(0 == ~T7_E~0); 14004#L1071-1 assume !(0 == ~T8_E~0); 14834#L1076-1 assume !(0 == ~T9_E~0); 13891#L1081-1 assume !(0 == ~T10_E~0); 13892#L1086-1 assume 0 == ~E_M~0;~E_M~0 := 1; 14293#L1091-1 assume !(0 == ~E_1~0); 15007#L1096-1 assume !(0 == ~E_2~0); 15008#L1101-1 assume !(0 == ~E_3~0); 14359#L1106-1 assume !(0 == ~E_4~0); 14360#L1111-1 assume !(0 == ~E_5~0); 14521#L1116-1 assume !(0 == ~E_6~0); 14522#L1121-1 assume !(0 == ~E_7~0); 14350#L1126-1 assume 0 == ~E_8~0;~E_8~0 := 1; 14351#L1131-1 assume !(0 == ~E_9~0); 14619#L1136-1 assume !(0 == ~E_10~0); 14732#L1141-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 14879#L514 assume 1 == ~m_pc~0; 14845#L515 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 14368#L525 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 14369#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 14931#L1285 assume !(0 != activate_threads_~tmp~1#1); 15042#L1285-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14022#L533 assume !(1 == ~t1_pc~0); 14023#L533-2 is_transmit1_triggered_~__retres1~1#1 := 0; 14536#L544 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13782#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 13783#L1293 assume !(0 != activate_threads_~tmp___0~0#1); 14755#L1293-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14756#L552 assume 1 == ~t2_pc~0; 14240#L553 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 14241#L563 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14354#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 14355#L1301 assume !(0 != activate_threads_~tmp___1~0#1); 14381#L1301-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14382#L571 assume 1 == ~t3_pc~0; 14572#L572 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 14573#L582 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13727#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 13728#L1309 assume !(0 != activate_threads_~tmp___2~0#1); 14526#L1309-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13813#L590 assume !(1 == ~t4_pc~0); 13814#L590-2 is_transmit4_triggered_~__retres1~4#1 := 0; 14582#L601 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 13909#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 13910#L1317 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 14781#L1317-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14523#L609 assume 1 == ~t5_pc~0; 14524#L610 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 15040#L620 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 14933#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 14934#L1325 assume !(0 != activate_threads_~tmp___4~0#1); 14516#L1325-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14517#L628 assume !(1 == ~t6_pc~0); 14448#L628-2 is_transmit6_triggered_~__retres1~6#1 := 0; 14447#L639 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 14327#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 14328#L1333 assume !(0 != activate_threads_~tmp___5~0#1); 14815#L1333-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 14816#L647 assume 1 == ~t7_pc~0; 14361#L648 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 14362#L658 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 14942#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 14364#L1341 assume !(0 != activate_threads_~tmp___6~0#1); 14365#L1341-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 15069#L666 assume !(1 == ~t8_pc~0); 14156#L666-2 is_transmit8_triggered_~__retres1~8#1 := 0; 14157#L677 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 14380#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 14547#L1349 assume !(0 != activate_threads_~tmp___7~0#1); 14290#L1349-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 14291#L685 assume 1 == ~t9_pc~0; 15048#L686 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 14950#L696 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 14411#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 14318#L1357 assume !(0 != activate_threads_~tmp___8~0#1); 14319#L1357-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 14697#L704 assume !(1 == ~t10_pc~0); 14310#L704-2 is_transmit10_triggered_~__retres1~10#1 := 0; 14309#L715 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 14561#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 13861#L1365 assume !(0 != activate_threads_~tmp___9~0#1); 13862#L1365-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14118#L1154 assume !(1 == ~M_E~0); 14803#L1154-2 assume !(1 == ~T1_E~0); 14090#L1159-1 assume !(1 == ~T2_E~0); 14091#L1164-1 assume !(1 == ~T3_E~0); 14545#L1169-1 assume !(1 == ~T4_E~0); 14412#L1174-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 14218#L1179-1 assume !(1 == ~T6_E~0); 14076#L1184-1 assume !(1 == ~T7_E~0); 14077#L1189-1 assume !(1 == ~T8_E~0); 14154#L1194-1 assume !(1 == ~T9_E~0); 14277#L1199-1 assume !(1 == ~T10_E~0); 14230#L1204-1 assume !(1 == ~E_M~0); 14231#L1209-1 assume !(1 == ~E_1~0); 14775#L1214-1 assume 1 == ~E_2~0;~E_2~0 := 2; 14776#L1219-1 assume !(1 == ~E_3~0); 15062#L1224-1 assume !(1 == ~E_4~0); 14565#L1229-1 assume !(1 == ~E_5~0); 13958#L1234-1 assume !(1 == ~E_6~0); 13959#L1239-1 assume !(1 == ~E_7~0); 14018#L1244-1 assume !(1 == ~E_8~0); 14019#L1249-1 assume !(1 == ~E_9~0); 14843#L1254-1 assume 1 == ~E_10~0;~E_10~0 := 2; 13856#L1259-1 assume { :end_inline_reset_delta_events } true; 13857#L1565-2 [2022-12-13 12:11:42,997 INFO L750 eck$LassoCheckResult]: Loop: 13857#L1565-2 assume !false; 14783#L1566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 13808#L1011 assume !false; 14247#L862 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 14295#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 14059#L851 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 14392#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 14082#L866 assume !(0 != eval_~tmp~0#1); 14084#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 14584#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 14585#L1036-3 assume 0 == ~M_E~0;~M_E~0 := 1; 14847#L1036-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 15025#L1041-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 14907#L1046-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 14908#L1051-3 assume !(0 == ~T4_E~0); 14848#L1056-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 14106#L1061-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 14107#L1066-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 14108#L1071-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 15027#L1076-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 13848#L1081-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 13849#L1086-3 assume 0 == ~E_M~0;~E_M~0 := 1; 13901#L1091-3 assume !(0 == ~E_1~0); 13902#L1096-3 assume 0 == ~E_2~0;~E_2~0 := 1; 14991#L1101-3 assume 0 == ~E_3~0;~E_3~0 := 1; 14992#L1106-3 assume 0 == ~E_4~0;~E_4~0 := 1; 15024#L1111-3 assume 0 == ~E_5~0;~E_5~0 := 1; 14983#L1116-3 assume 0 == ~E_6~0;~E_6~0 := 1; 14712#L1121-3 assume 0 == ~E_7~0;~E_7~0 := 1; 14713#L1126-3 assume 0 == ~E_8~0;~E_8~0 := 1; 14922#L1131-3 assume !(0 == ~E_9~0); 14923#L1136-3 assume 0 == ~E_10~0;~E_10~0 := 1; 15074#L1141-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 14715#L514-36 assume !(1 == ~m_pc~0); 14428#L514-38 is_master_triggered_~__retres1~0#1 := 0; 14268#L525-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 14269#is_master_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 14754#L1285-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 14163#L1285-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14164#L533-36 assume 1 == ~t1_pc~0; 14437#L534-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 14530#L544-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14973#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 14791#L1293-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 14589#L1293-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14590#L552-36 assume 1 == ~t2_pc~0; 14158#L553-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 14160#L563-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14648#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 14915#L1301-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 14130#L1301-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14131#L571-36 assume 1 == ~t3_pc~0; 14512#L572-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 14219#L582-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14220#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 14407#L1309-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 14906#L1309-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 14190#L590-36 assume 1 == ~t4_pc~0; 14192#L591-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 14804#L601-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 14599#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 14600#L1317-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 14885#L1317-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14886#L609-36 assume 1 == ~t5_pc~0; 14766#L610-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 14592#L620-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 14593#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 14930#L1325-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 14676#L1325-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14488#L628-36 assume 1 == ~t6_pc~0; 14338#L629-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 14339#L639-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 14388#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 14389#L1333-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 14717#L1333-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 14718#L647-36 assume 1 == ~t7_pc~0; 14641#L648-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 13875#L658-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 13876#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 13895#L1341-36 assume !(0 != activate_threads_~tmp___6~0#1); 13896#L1341-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 14805#L666-36 assume 1 == ~t8_pc~0; 14087#L667-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 14088#L677-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 14705#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 14706#L1349-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 14238#L1349-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 14239#L685-36 assume 1 == ~t9_pc~0; 14692#L686-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 13990#L696-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 14441#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 14442#L1357-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 14377#L1357-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 14378#L704-36 assume 1 == ~t10_pc~0; 13977#L705-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 13978#L715-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 14300#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 14301#L1365-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 14007#L1365-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14008#L1154-3 assume 1 == ~M_E~0;~M_E~0 := 2; 14977#L1154-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 14861#L1159-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 14862#L1164-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 15037#L1169-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 14306#L1174-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 14307#L1179-3 assume !(1 == ~T6_E~0); 14952#L1184-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 13877#L1189-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 13878#L1194-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 14250#L1199-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 14251#L1204-3 assume 1 == ~E_M~0;~E_M~0 := 2; 14562#L1209-3 assume 1 == ~E_1~0;~E_1~0 := 2; 13745#L1214-3 assume 1 == ~E_2~0;~E_2~0 := 2; 13746#L1219-3 assume !(1 == ~E_3~0); 14761#L1224-3 assume 1 == ~E_4~0;~E_4~0 := 2; 14762#L1229-3 assume 1 == ~E_5~0;~E_5~0 := 2; 14782#L1234-3 assume 1 == ~E_6~0;~E_6~0 := 2; 14020#L1239-3 assume 1 == ~E_7~0;~E_7~0 := 2; 14021#L1244-3 assume 1 == ~E_8~0;~E_8~0 := 2; 14616#L1249-3 assume 1 == ~E_9~0;~E_9~0 := 2; 14984#L1254-3 assume 1 == ~E_10~0;~E_10~0 := 2; 14764#L1259-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 14765#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 13825#L851-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 14288#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 14289#L1584 assume !(0 == start_simulation_~tmp~3#1); 14723#L1584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 14034#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 13725#L851-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 13777#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 13778#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 14357#L1546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 14605#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 14606#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 13857#L1565-2 [2022-12-13 12:11:42,997 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:11:42,997 INFO L85 PathProgramCache]: Analyzing trace with hash -1183425475, now seen corresponding path program 1 times [2022-12-13 12:11:42,997 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:11:42,997 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2107464929] [2022-12-13 12:11:42,997 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:11:42,998 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:11:43,009 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:11:43,041 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:11:43,041 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:11:43,041 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2107464929] [2022-12-13 12:11:43,042 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2107464929] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:11:43,042 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:11:43,042 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:11:43,042 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1873832158] [2022-12-13 12:11:43,042 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:11:43,042 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 12:11:43,042 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:11:43,043 INFO L85 PathProgramCache]: Analyzing trace with hash 133280466, now seen corresponding path program 1 times [2022-12-13 12:11:43,043 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:11:43,043 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1266728825] [2022-12-13 12:11:43,043 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:11:43,043 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:11:43,051 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:11:43,089 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:11:43,089 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:11:43,089 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1266728825] [2022-12-13 12:11:43,089 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1266728825] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:11:43,089 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:11:43,090 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:11:43,090 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1422219539] [2022-12-13 12:11:43,090 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:11:43,090 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:11:43,090 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:11:43,090 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 12:11:43,090 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 12:11:43,090 INFO L87 Difference]: Start difference. First operand 1366 states and 2028 transitions. cyclomatic complexity: 663 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:11:43,108 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:11:43,108 INFO L93 Difference]: Finished difference Result 1366 states and 2027 transitions. [2022-12-13 12:11:43,108 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1366 states and 2027 transitions. [2022-12-13 12:11:43,113 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1227 [2022-12-13 12:11:43,116 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1366 states to 1366 states and 2027 transitions. [2022-12-13 12:11:43,116 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1366 [2022-12-13 12:11:43,117 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1366 [2022-12-13 12:11:43,117 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1366 states and 2027 transitions. [2022-12-13 12:11:43,118 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:11:43,118 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1366 states and 2027 transitions. [2022-12-13 12:11:43,120 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1366 states and 2027 transitions. [2022-12-13 12:11:43,129 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1366 to 1366. [2022-12-13 12:11:43,131 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1366 states, 1366 states have (on average 1.4838945827232797) internal successors, (2027), 1365 states have internal predecessors, (2027), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:11:43,133 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1366 states to 1366 states and 2027 transitions. [2022-12-13 12:11:43,133 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1366 states and 2027 transitions. [2022-12-13 12:11:43,133 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 12:11:43,134 INFO L428 stractBuchiCegarLoop]: Abstraction has 1366 states and 2027 transitions. [2022-12-13 12:11:43,134 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2022-12-13 12:11:43,134 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1366 states and 2027 transitions. [2022-12-13 12:11:43,137 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1227 [2022-12-13 12:11:43,137 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:11:43,137 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:11:43,138 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:11:43,139 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:11:43,139 INFO L748 eck$LassoCheckResult]: Stem: 16873#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 16874#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 17735#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 17736#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 17797#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 17739#L731-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 17699#L736-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 17700#L741-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 17728#L746-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 16809#L751-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 16810#L756-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 16915#L761-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 17156#L766-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 17085#L771-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 16811#L776-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 16468#L781-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 16469#L1036 assume !(0 == ~M_E~0); 16566#L1036-2 assume !(0 == ~T1_E~0); 17465#L1041-1 assume !(0 == ~T2_E~0); 17466#L1046-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 16848#L1051-1 assume !(0 == ~T4_E~0); 16849#L1056-1 assume !(0 == ~T5_E~0); 17591#L1061-1 assume !(0 == ~T6_E~0); 16742#L1066-1 assume !(0 == ~T7_E~0); 16743#L1071-1 assume !(0 == ~T8_E~0); 17573#L1076-1 assume !(0 == ~T9_E~0); 16630#L1081-1 assume !(0 == ~T10_E~0); 16631#L1086-1 assume 0 == ~E_M~0;~E_M~0 := 1; 17032#L1091-1 assume !(0 == ~E_1~0); 17746#L1096-1 assume !(0 == ~E_2~0); 17747#L1101-1 assume !(0 == ~E_3~0); 17098#L1106-1 assume !(0 == ~E_4~0); 17099#L1111-1 assume !(0 == ~E_5~0); 17260#L1116-1 assume !(0 == ~E_6~0); 17261#L1121-1 assume !(0 == ~E_7~0); 17089#L1126-1 assume 0 == ~E_8~0;~E_8~0 := 1; 17090#L1131-1 assume !(0 == ~E_9~0); 17358#L1136-1 assume !(0 == ~E_10~0); 17471#L1141-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 17618#L514 assume 1 == ~m_pc~0; 17584#L515 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 17107#L525 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 17108#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 17670#L1285 assume !(0 != activate_threads_~tmp~1#1); 17781#L1285-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16761#L533 assume !(1 == ~t1_pc~0); 16762#L533-2 is_transmit1_triggered_~__retres1~1#1 := 0; 17275#L544 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16521#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 16522#L1293 assume !(0 != activate_threads_~tmp___0~0#1); 17494#L1293-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 17495#L552 assume 1 == ~t2_pc~0; 16979#L553 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 16980#L563 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17093#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 17094#L1301 assume !(0 != activate_threads_~tmp___1~0#1); 17120#L1301-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 17121#L571 assume 1 == ~t3_pc~0; 17311#L572 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 17312#L582 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 16466#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 16467#L1309 assume !(0 != activate_threads_~tmp___2~0#1); 17265#L1309-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 16552#L590 assume !(1 == ~t4_pc~0); 16553#L590-2 is_transmit4_triggered_~__retres1~4#1 := 0; 17321#L601 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 16648#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 16649#L1317 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 17520#L1317-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 17262#L609 assume 1 == ~t5_pc~0; 17263#L610 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 17779#L620 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 17672#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 17673#L1325 assume !(0 != activate_threads_~tmp___4~0#1); 17255#L1325-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 17256#L628 assume !(1 == ~t6_pc~0); 17187#L628-2 is_transmit6_triggered_~__retres1~6#1 := 0; 17186#L639 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 17066#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 17067#L1333 assume !(0 != activate_threads_~tmp___5~0#1); 17554#L1333-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 17555#L647 assume 1 == ~t7_pc~0; 17100#L648 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 17101#L658 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 17681#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 17103#L1341 assume !(0 != activate_threads_~tmp___6~0#1); 17104#L1341-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 17808#L666 assume !(1 == ~t8_pc~0); 16895#L666-2 is_transmit8_triggered_~__retres1~8#1 := 0; 16896#L677 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 17119#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 17286#L1349 assume !(0 != activate_threads_~tmp___7~0#1); 17029#L1349-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 17030#L685 assume 1 == ~t9_pc~0; 17787#L686 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 17689#L696 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 17150#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 17057#L1357 assume !(0 != activate_threads_~tmp___8~0#1); 17058#L1357-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 17436#L704 assume !(1 == ~t10_pc~0); 17049#L704-2 is_transmit10_triggered_~__retres1~10#1 := 0; 17048#L715 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 17300#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 16600#L1365 assume !(0 != activate_threads_~tmp___9~0#1); 16601#L1365-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16857#L1154 assume !(1 == ~M_E~0); 17542#L1154-2 assume !(1 == ~T1_E~0); 16829#L1159-1 assume !(1 == ~T2_E~0); 16830#L1164-1 assume !(1 == ~T3_E~0); 17284#L1169-1 assume !(1 == ~T4_E~0); 17151#L1174-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 16957#L1179-1 assume !(1 == ~T6_E~0); 16815#L1184-1 assume !(1 == ~T7_E~0); 16816#L1189-1 assume !(1 == ~T8_E~0); 16893#L1194-1 assume !(1 == ~T9_E~0); 17016#L1199-1 assume !(1 == ~T10_E~0); 16969#L1204-1 assume !(1 == ~E_M~0); 16970#L1209-1 assume !(1 == ~E_1~0); 17514#L1214-1 assume 1 == ~E_2~0;~E_2~0 := 2; 17515#L1219-1 assume !(1 == ~E_3~0); 17801#L1224-1 assume !(1 == ~E_4~0); 17304#L1229-1 assume !(1 == ~E_5~0); 16697#L1234-1 assume !(1 == ~E_6~0); 16698#L1239-1 assume !(1 == ~E_7~0); 16757#L1244-1 assume !(1 == ~E_8~0); 16758#L1249-1 assume !(1 == ~E_9~0); 17582#L1254-1 assume 1 == ~E_10~0;~E_10~0 := 2; 16595#L1259-1 assume { :end_inline_reset_delta_events } true; 16596#L1565-2 [2022-12-13 12:11:43,139 INFO L750 eck$LassoCheckResult]: Loop: 16596#L1565-2 assume !false; 17522#L1566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 16547#L1011 assume !false; 16986#L862 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 17034#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 16798#L851 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 17131#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 16821#L866 assume !(0 != eval_~tmp~0#1); 16823#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 17323#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 17324#L1036-3 assume 0 == ~M_E~0;~M_E~0 := 1; 17586#L1036-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 17764#L1041-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 17646#L1046-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 17647#L1051-3 assume !(0 == ~T4_E~0); 17587#L1056-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 16845#L1061-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 16846#L1066-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 16847#L1071-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 17766#L1076-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 16587#L1081-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 16588#L1086-3 assume 0 == ~E_M~0;~E_M~0 := 1; 16640#L1091-3 assume !(0 == ~E_1~0); 16641#L1096-3 assume 0 == ~E_2~0;~E_2~0 := 1; 17730#L1101-3 assume 0 == ~E_3~0;~E_3~0 := 1; 17731#L1106-3 assume 0 == ~E_4~0;~E_4~0 := 1; 17763#L1111-3 assume 0 == ~E_5~0;~E_5~0 := 1; 17722#L1116-3 assume 0 == ~E_6~0;~E_6~0 := 1; 17451#L1121-3 assume 0 == ~E_7~0;~E_7~0 := 1; 17452#L1126-3 assume 0 == ~E_8~0;~E_8~0 := 1; 17661#L1131-3 assume !(0 == ~E_9~0); 17662#L1136-3 assume 0 == ~E_10~0;~E_10~0 := 1; 17813#L1141-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 17454#L514-36 assume !(1 == ~m_pc~0); 17167#L514-38 is_master_triggered_~__retres1~0#1 := 0; 17007#L525-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 17008#is_master_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 17493#L1285-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 16902#L1285-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16903#L533-36 assume 1 == ~t1_pc~0; 17176#L534-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 17269#L544-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 17712#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 17530#L1293-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 17328#L1293-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 17329#L552-36 assume 1 == ~t2_pc~0; 16897#L553-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 16899#L563-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17387#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 17654#L1301-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 16869#L1301-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16870#L571-36 assume 1 == ~t3_pc~0; 17251#L572-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 16958#L582-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 16959#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 17146#L1309-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 17645#L1309-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 16929#L590-36 assume !(1 == ~t4_pc~0); 16930#L590-38 is_transmit4_triggered_~__retres1~4#1 := 0; 17543#L601-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 17339#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 17340#L1317-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 17624#L1317-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 17625#L609-36 assume 1 == ~t5_pc~0; 17505#L610-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 17331#L620-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 17332#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 17669#L1325-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 17415#L1325-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 17227#L628-36 assume 1 == ~t6_pc~0; 17077#L629-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 17078#L639-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 17127#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 17128#L1333-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 17456#L1333-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 17457#L647-36 assume 1 == ~t7_pc~0; 17380#L648-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 16614#L658-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 16615#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 16634#L1341-36 assume !(0 != activate_threads_~tmp___6~0#1); 16635#L1341-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 17544#L666-36 assume 1 == ~t8_pc~0; 16826#L667-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 16827#L677-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 17444#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 17445#L1349-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 16977#L1349-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 16978#L685-36 assume 1 == ~t9_pc~0; 17431#L686-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 16729#L696-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 17180#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 17181#L1357-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 17116#L1357-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 17117#L704-36 assume 1 == ~t10_pc~0; 16716#L705-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 16717#L715-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 17039#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 17040#L1365-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 16746#L1365-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16747#L1154-3 assume 1 == ~M_E~0;~M_E~0 := 2; 17716#L1154-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 17600#L1159-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 17601#L1164-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 17776#L1169-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 17045#L1174-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 17046#L1179-3 assume !(1 == ~T6_E~0); 17691#L1184-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 16616#L1189-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 16617#L1194-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 16989#L1199-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 16990#L1204-3 assume 1 == ~E_M~0;~E_M~0 := 2; 17301#L1209-3 assume 1 == ~E_1~0;~E_1~0 := 2; 16487#L1214-3 assume 1 == ~E_2~0;~E_2~0 := 2; 16488#L1219-3 assume !(1 == ~E_3~0); 17500#L1224-3 assume 1 == ~E_4~0;~E_4~0 := 2; 17501#L1229-3 assume 1 == ~E_5~0;~E_5~0 := 2; 17521#L1234-3 assume 1 == ~E_6~0;~E_6~0 := 2; 16759#L1239-3 assume 1 == ~E_7~0;~E_7~0 := 2; 16760#L1244-3 assume 1 == ~E_8~0;~E_8~0 := 2; 17355#L1249-3 assume 1 == ~E_9~0;~E_9~0 := 2; 17723#L1254-3 assume 1 == ~E_10~0;~E_10~0 := 2; 17503#L1259-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 17504#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 16564#L851-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 17027#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 17028#L1584 assume !(0 == start_simulation_~tmp~3#1); 17462#L1584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 16773#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 16464#L851-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 16516#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 16517#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 17096#L1546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 17344#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 17345#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 16596#L1565-2 [2022-12-13 12:11:43,139 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:11:43,139 INFO L85 PathProgramCache]: Analyzing trace with hash 659050239, now seen corresponding path program 1 times [2022-12-13 12:11:43,139 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:11:43,139 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [910221561] [2022-12-13 12:11:43,140 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:11:43,140 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:11:43,147 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:11:43,168 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:11:43,168 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:11:43,168 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [910221561] [2022-12-13 12:11:43,168 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [910221561] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:11:43,169 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:11:43,169 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:11:43,169 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [659589346] [2022-12-13 12:11:43,169 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:11:43,169 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 12:11:43,170 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:11:43,170 INFO L85 PathProgramCache]: Analyzing trace with hash -1709033325, now seen corresponding path program 2 times [2022-12-13 12:11:43,170 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:11:43,170 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [408820779] [2022-12-13 12:11:43,170 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:11:43,170 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:11:43,182 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:11:43,211 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:11:43,212 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:11:43,212 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [408820779] [2022-12-13 12:11:43,212 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [408820779] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:11:43,212 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:11:43,212 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:11:43,212 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [68757642] [2022-12-13 12:11:43,212 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:11:43,213 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:11:43,213 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:11:43,213 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 12:11:43,213 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 12:11:43,214 INFO L87 Difference]: Start difference. First operand 1366 states and 2027 transitions. cyclomatic complexity: 662 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:11:43,233 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:11:43,233 INFO L93 Difference]: Finished difference Result 1366 states and 2026 transitions. [2022-12-13 12:11:43,233 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1366 states and 2026 transitions. [2022-12-13 12:11:43,237 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1227 [2022-12-13 12:11:43,240 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1366 states to 1366 states and 2026 transitions. [2022-12-13 12:11:43,240 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1366 [2022-12-13 12:11:43,241 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1366 [2022-12-13 12:11:43,241 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1366 states and 2026 transitions. [2022-12-13 12:11:43,242 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:11:43,242 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1366 states and 2026 transitions. [2022-12-13 12:11:43,243 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1366 states and 2026 transitions. [2022-12-13 12:11:43,253 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1366 to 1366. [2022-12-13 12:11:43,254 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1366 states, 1366 states have (on average 1.4831625183016106) internal successors, (2026), 1365 states have internal predecessors, (2026), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:11:43,256 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1366 states to 1366 states and 2026 transitions. [2022-12-13 12:11:43,256 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1366 states and 2026 transitions. [2022-12-13 12:11:43,257 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 12:11:43,257 INFO L428 stractBuchiCegarLoop]: Abstraction has 1366 states and 2026 transitions. [2022-12-13 12:11:43,257 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2022-12-13 12:11:43,257 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1366 states and 2026 transitions. [2022-12-13 12:11:43,262 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1227 [2022-12-13 12:11:43,262 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:11:43,262 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:11:43,264 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:11:43,264 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:11:43,265 INFO L748 eck$LassoCheckResult]: Stem: 19612#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 19613#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 20474#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 20475#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 20536#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 20478#L731-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 20438#L736-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 20439#L741-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 20467#L746-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 19550#L751-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 19551#L756-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 19654#L761-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 19895#L766-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 19824#L771-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 19552#L776-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 19207#L781-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 19208#L1036 assume !(0 == ~M_E~0); 19305#L1036-2 assume !(0 == ~T1_E~0); 20204#L1041-1 assume !(0 == ~T2_E~0); 20205#L1046-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 19587#L1051-1 assume !(0 == ~T4_E~0); 19588#L1056-1 assume !(0 == ~T5_E~0); 20330#L1061-1 assume !(0 == ~T6_E~0); 19481#L1066-1 assume !(0 == ~T7_E~0); 19482#L1071-1 assume !(0 == ~T8_E~0); 20312#L1076-1 assume !(0 == ~T9_E~0); 19369#L1081-1 assume !(0 == ~T10_E~0); 19370#L1086-1 assume 0 == ~E_M~0;~E_M~0 := 1; 19771#L1091-1 assume !(0 == ~E_1~0); 20486#L1096-1 assume !(0 == ~E_2~0); 20487#L1101-1 assume !(0 == ~E_3~0); 19837#L1106-1 assume !(0 == ~E_4~0); 19838#L1111-1 assume !(0 == ~E_5~0); 19999#L1116-1 assume !(0 == ~E_6~0); 20000#L1121-1 assume !(0 == ~E_7~0); 19828#L1126-1 assume 0 == ~E_8~0;~E_8~0 := 1; 19829#L1131-1 assume !(0 == ~E_9~0); 20097#L1136-1 assume !(0 == ~E_10~0); 20210#L1141-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 20357#L514 assume 1 == ~m_pc~0; 20323#L515 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 19846#L525 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 19847#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 20410#L1285 assume !(0 != activate_threads_~tmp~1#1); 20521#L1285-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 19500#L533 assume !(1 == ~t1_pc~0); 19501#L533-2 is_transmit1_triggered_~__retres1~1#1 := 0; 20014#L544 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 19262#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 19263#L1293 assume !(0 != activate_threads_~tmp___0~0#1); 20233#L1293-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 20234#L552 assume 1 == ~t2_pc~0; 19719#L553 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 19720#L563 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 19832#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 19833#L1301 assume !(0 != activate_threads_~tmp___1~0#1); 19864#L1301-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 19865#L571 assume 1 == ~t3_pc~0; 20052#L572 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 20053#L582 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 19205#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 19206#L1309 assume !(0 != activate_threads_~tmp___2~0#1); 20004#L1309-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19291#L590 assume !(1 == ~t4_pc~0); 19292#L590-2 is_transmit4_triggered_~__retres1~4#1 := 0; 20060#L601 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 19387#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 19388#L1317 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 20260#L1317-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 20001#L609 assume 1 == ~t5_pc~0; 20002#L610 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 20518#L620 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 20411#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 20412#L1325 assume !(0 != activate_threads_~tmp___4~0#1); 19994#L1325-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 19995#L628 assume !(1 == ~t6_pc~0); 19926#L628-2 is_transmit6_triggered_~__retres1~6#1 := 0; 19925#L639 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 19806#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 19807#L1333 assume !(0 != activate_threads_~tmp___5~0#1); 20293#L1333-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 20294#L647 assume 1 == ~t7_pc~0; 19839#L648 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 19840#L658 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 20420#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 19844#L1341 assume !(0 != activate_threads_~tmp___6~0#1); 19845#L1341-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 20547#L666 assume !(1 == ~t8_pc~0); 19634#L666-2 is_transmit8_triggered_~__retres1~8#1 := 0; 19635#L677 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 19858#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 20026#L1349 assume !(0 != activate_threads_~tmp___7~0#1); 19769#L1349-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 19770#L685 assume 1 == ~t9_pc~0; 20526#L686 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 20428#L696 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 19889#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 19796#L1357 assume !(0 != activate_threads_~tmp___8~0#1); 19797#L1357-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 20175#L704 assume !(1 == ~t10_pc~0); 19788#L704-2 is_transmit10_triggered_~__retres1~10#1 := 0; 19787#L715 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 20040#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 19339#L1365 assume !(0 != activate_threads_~tmp___9~0#1); 19340#L1365-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19596#L1154 assume !(1 == ~M_E~0); 20281#L1154-2 assume !(1 == ~T1_E~0); 19568#L1159-1 assume !(1 == ~T2_E~0); 19569#L1164-1 assume !(1 == ~T3_E~0); 20023#L1169-1 assume !(1 == ~T4_E~0); 19890#L1174-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 19698#L1179-1 assume !(1 == ~T6_E~0); 19554#L1184-1 assume !(1 == ~T7_E~0); 19555#L1189-1 assume !(1 == ~T8_E~0); 19632#L1194-1 assume !(1 == ~T9_E~0); 19757#L1199-1 assume !(1 == ~T10_E~0); 19710#L1204-1 assume !(1 == ~E_M~0); 19711#L1209-1 assume !(1 == ~E_1~0); 20255#L1214-1 assume 1 == ~E_2~0;~E_2~0 := 2; 20256#L1219-1 assume !(1 == ~E_3~0); 20540#L1224-1 assume !(1 == ~E_4~0); 20044#L1229-1 assume !(1 == ~E_5~0); 19436#L1234-1 assume !(1 == ~E_6~0); 19437#L1239-1 assume !(1 == ~E_7~0); 19496#L1244-1 assume !(1 == ~E_8~0); 19497#L1249-1 assume !(1 == ~E_9~0); 20321#L1254-1 assume 1 == ~E_10~0;~E_10~0 := 2; 19334#L1259-1 assume { :end_inline_reset_delta_events } true; 19335#L1565-2 [2022-12-13 12:11:43,265 INFO L750 eck$LassoCheckResult]: Loop: 19335#L1565-2 assume !false; 20261#L1566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 19286#L1011 assume !false; 19725#L862 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 19773#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 19537#L851 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 19870#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 19565#L866 assume !(0 != eval_~tmp~0#1); 19567#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 20063#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 20064#L1036-3 assume 0 == ~M_E~0;~M_E~0 := 1; 20325#L1036-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 20503#L1041-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 20385#L1046-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 20386#L1051-3 assume !(0 == ~T4_E~0); 20326#L1056-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 19584#L1061-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 19585#L1066-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 19586#L1071-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 20505#L1076-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 19326#L1081-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 19327#L1086-3 assume 0 == ~E_M~0;~E_M~0 := 1; 19383#L1091-3 assume !(0 == ~E_1~0); 19384#L1096-3 assume 0 == ~E_2~0;~E_2~0 := 1; 20469#L1101-3 assume 0 == ~E_3~0;~E_3~0 := 1; 20470#L1106-3 assume 0 == ~E_4~0;~E_4~0 := 1; 20502#L1111-3 assume 0 == ~E_5~0;~E_5~0 := 1; 20461#L1116-3 assume 0 == ~E_6~0;~E_6~0 := 1; 20190#L1121-3 assume 0 == ~E_7~0;~E_7~0 := 1; 20191#L1126-3 assume 0 == ~E_8~0;~E_8~0 := 1; 20400#L1131-3 assume !(0 == ~E_9~0); 20401#L1136-3 assume 0 == ~E_10~0;~E_10~0 := 1; 20552#L1141-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 20193#L514-36 assume !(1 == ~m_pc~0); 19906#L514-38 is_master_triggered_~__retres1~0#1 := 0; 19746#L525-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 19747#is_master_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 20232#L1285-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 19641#L1285-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 19642#L533-36 assume 1 == ~t1_pc~0; 19915#L534-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 20011#L544-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 20451#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 20269#L1293-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 20067#L1293-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 20068#L552-36 assume 1 == ~t2_pc~0; 19636#L553-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 19638#L563-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 20126#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 20393#L1301-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 19608#L1301-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 19609#L571-36 assume 1 == ~t3_pc~0; 19990#L572-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 19696#L582-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 19697#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 19885#L1309-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 20384#L1309-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19665#L590-36 assume !(1 == ~t4_pc~0); 19666#L590-38 is_transmit4_triggered_~__retres1~4#1 := 0; 20282#L601-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 20077#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 20078#L1317-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 20363#L1317-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 20364#L609-36 assume 1 == ~t5_pc~0; 20244#L610-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 20070#L620-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 20071#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 20408#L1325-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 20154#L1325-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 19966#L628-36 assume 1 == ~t6_pc~0; 19816#L629-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 19817#L639-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 19866#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 19867#L1333-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 20195#L1333-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 20196#L647-36 assume 1 == ~t7_pc~0; 20119#L648-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 19353#L658-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 19354#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 19373#L1341-36 assume !(0 != activate_threads_~tmp___6~0#1); 19374#L1341-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 20283#L666-36 assume 1 == ~t8_pc~0; 19562#L667-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 19563#L677-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 20183#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 20184#L1349-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 19716#L1349-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 19717#L685-36 assume 1 == ~t9_pc~0; 20170#L686-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 19468#L696-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 19919#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 19920#L1357-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 19855#L1357-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 19856#L704-36 assume !(1 == ~t10_pc~0); 19457#L704-38 is_transmit10_triggered_~__retres1~10#1 := 0; 19456#L715-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 19778#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 19779#L1365-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 19485#L1365-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19486#L1154-3 assume 1 == ~M_E~0;~M_E~0 := 2; 20455#L1154-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 20339#L1159-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 20340#L1164-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 20515#L1169-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 19784#L1174-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 19785#L1179-3 assume !(1 == ~T6_E~0); 20430#L1184-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 19355#L1189-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 19356#L1194-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 19728#L1199-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 19729#L1204-3 assume 1 == ~E_M~0;~E_M~0 := 2; 20039#L1209-3 assume 1 == ~E_1~0;~E_1~0 := 2; 19223#L1214-3 assume 1 == ~E_2~0;~E_2~0 := 2; 19224#L1219-3 assume !(1 == ~E_3~0); 20239#L1224-3 assume 1 == ~E_4~0;~E_4~0 := 2; 20240#L1229-3 assume 1 == ~E_5~0;~E_5~0 := 2; 20259#L1234-3 assume 1 == ~E_6~0;~E_6~0 := 2; 19498#L1239-3 assume 1 == ~E_7~0;~E_7~0 := 2; 19499#L1244-3 assume 1 == ~E_8~0;~E_8~0 := 2; 20090#L1249-3 assume 1 == ~E_9~0;~E_9~0 := 2; 20462#L1254-3 assume 1 == ~E_10~0;~E_10~0 := 2; 20242#L1259-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 20243#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 19303#L851-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 19766#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 19767#L1584 assume !(0 == start_simulation_~tmp~3#1); 20201#L1584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 19512#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 19203#L851-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 19255#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 19256#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 19835#L1546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 20083#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 20084#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 19335#L1565-2 [2022-12-13 12:11:43,265 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:11:43,265 INFO L85 PathProgramCache]: Analyzing trace with hash -1913914371, now seen corresponding path program 1 times [2022-12-13 12:11:43,266 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:11:43,266 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1588881144] [2022-12-13 12:11:43,266 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:11:43,266 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:11:43,276 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:11:43,298 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:11:43,298 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:11:43,298 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1588881144] [2022-12-13 12:11:43,298 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1588881144] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:11:43,298 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:11:43,298 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:11:43,298 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [368797617] [2022-12-13 12:11:43,299 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:11:43,299 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 12:11:43,299 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:11:43,299 INFO L85 PathProgramCache]: Analyzing trace with hash 2100759252, now seen corresponding path program 1 times [2022-12-13 12:11:43,299 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:11:43,299 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [375037097] [2022-12-13 12:11:43,299 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:11:43,299 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:11:43,308 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:11:43,343 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:11:43,344 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:11:43,344 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [375037097] [2022-12-13 12:11:43,344 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [375037097] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:11:43,344 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:11:43,344 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:11:43,344 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1672482402] [2022-12-13 12:11:43,344 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:11:43,344 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:11:43,344 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:11:43,344 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 12:11:43,345 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 12:11:43,345 INFO L87 Difference]: Start difference. First operand 1366 states and 2026 transitions. cyclomatic complexity: 661 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:11:43,360 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:11:43,360 INFO L93 Difference]: Finished difference Result 1366 states and 2025 transitions. [2022-12-13 12:11:43,360 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1366 states and 2025 transitions. [2022-12-13 12:11:43,364 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1227 [2022-12-13 12:11:43,368 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1366 states to 1366 states and 2025 transitions. [2022-12-13 12:11:43,368 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1366 [2022-12-13 12:11:43,368 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1366 [2022-12-13 12:11:43,368 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1366 states and 2025 transitions. [2022-12-13 12:11:43,370 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:11:43,370 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1366 states and 2025 transitions. [2022-12-13 12:11:43,371 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1366 states and 2025 transitions. [2022-12-13 12:11:43,380 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1366 to 1366. [2022-12-13 12:11:43,382 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1366 states, 1366 states have (on average 1.4824304538799415) internal successors, (2025), 1365 states have internal predecessors, (2025), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:11:43,384 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1366 states to 1366 states and 2025 transitions. [2022-12-13 12:11:43,384 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1366 states and 2025 transitions. [2022-12-13 12:11:43,385 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 12:11:43,385 INFO L428 stractBuchiCegarLoop]: Abstraction has 1366 states and 2025 transitions. [2022-12-13 12:11:43,385 INFO L335 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2022-12-13 12:11:43,385 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1366 states and 2025 transitions. [2022-12-13 12:11:43,388 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1227 [2022-12-13 12:11:43,388 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:11:43,388 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:11:43,389 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:11:43,389 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:11:43,390 INFO L748 eck$LassoCheckResult]: Stem: 22351#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 22352#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 23213#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 23214#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 23275#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 23217#L731-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 23177#L736-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 23178#L741-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 23206#L746-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 22287#L751-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 22288#L756-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 22393#L761-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 22634#L766-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 22563#L771-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 22289#L776-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 21946#L781-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 21947#L1036 assume !(0 == ~M_E~0); 22044#L1036-2 assume !(0 == ~T1_E~0); 22943#L1041-1 assume !(0 == ~T2_E~0); 22944#L1046-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 22326#L1051-1 assume !(0 == ~T4_E~0); 22327#L1056-1 assume !(0 == ~T5_E~0); 23069#L1061-1 assume !(0 == ~T6_E~0); 22220#L1066-1 assume !(0 == ~T7_E~0); 22221#L1071-1 assume !(0 == ~T8_E~0); 23051#L1076-1 assume !(0 == ~T9_E~0); 22108#L1081-1 assume !(0 == ~T10_E~0); 22109#L1086-1 assume 0 == ~E_M~0;~E_M~0 := 1; 22510#L1091-1 assume !(0 == ~E_1~0); 23224#L1096-1 assume !(0 == ~E_2~0); 23225#L1101-1 assume !(0 == ~E_3~0); 22576#L1106-1 assume !(0 == ~E_4~0); 22577#L1111-1 assume !(0 == ~E_5~0); 22738#L1116-1 assume !(0 == ~E_6~0); 22739#L1121-1 assume !(0 == ~E_7~0); 22567#L1126-1 assume 0 == ~E_8~0;~E_8~0 := 1; 22568#L1131-1 assume !(0 == ~E_9~0); 22836#L1136-1 assume !(0 == ~E_10~0); 22949#L1141-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 23096#L514 assume 1 == ~m_pc~0; 23062#L515 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 22585#L525 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 22586#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 23148#L1285 assume !(0 != activate_threads_~tmp~1#1); 23259#L1285-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 22239#L533 assume !(1 == ~t1_pc~0); 22240#L533-2 is_transmit1_triggered_~__retres1~1#1 := 0; 22753#L544 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 21999#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 22000#L1293 assume !(0 != activate_threads_~tmp___0~0#1); 22972#L1293-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 22973#L552 assume 1 == ~t2_pc~0; 22457#L553 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 22458#L563 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 22571#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 22572#L1301 assume !(0 != activate_threads_~tmp___1~0#1); 22598#L1301-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 22599#L571 assume 1 == ~t3_pc~0; 22789#L572 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 22790#L582 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 21944#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 21945#L1309 assume !(0 != activate_threads_~tmp___2~0#1); 22743#L1309-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 22030#L590 assume !(1 == ~t4_pc~0); 22031#L590-2 is_transmit4_triggered_~__retres1~4#1 := 0; 22799#L601 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 22126#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 22127#L1317 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 22998#L1317-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 22740#L609 assume 1 == ~t5_pc~0; 22741#L610 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 23257#L620 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 23150#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 23151#L1325 assume !(0 != activate_threads_~tmp___4~0#1); 22733#L1325-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 22734#L628 assume !(1 == ~t6_pc~0); 22665#L628-2 is_transmit6_triggered_~__retres1~6#1 := 0; 22664#L639 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 22544#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 22545#L1333 assume !(0 != activate_threads_~tmp___5~0#1); 23032#L1333-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 23033#L647 assume 1 == ~t7_pc~0; 22578#L648 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 22579#L658 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 23159#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 22581#L1341 assume !(0 != activate_threads_~tmp___6~0#1); 22582#L1341-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 23286#L666 assume !(1 == ~t8_pc~0); 22373#L666-2 is_transmit8_triggered_~__retres1~8#1 := 0; 22374#L677 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 22597#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 22764#L1349 assume !(0 != activate_threads_~tmp___7~0#1); 22507#L1349-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 22508#L685 assume 1 == ~t9_pc~0; 23265#L686 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 23167#L696 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 22628#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 22535#L1357 assume !(0 != activate_threads_~tmp___8~0#1); 22536#L1357-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 22914#L704 assume !(1 == ~t10_pc~0); 22527#L704-2 is_transmit10_triggered_~__retres1~10#1 := 0; 22526#L715 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 22778#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 22078#L1365 assume !(0 != activate_threads_~tmp___9~0#1); 22079#L1365-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 22335#L1154 assume !(1 == ~M_E~0); 23020#L1154-2 assume !(1 == ~T1_E~0); 22307#L1159-1 assume !(1 == ~T2_E~0); 22308#L1164-1 assume !(1 == ~T3_E~0); 22762#L1169-1 assume !(1 == ~T4_E~0); 22629#L1174-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 22435#L1179-1 assume !(1 == ~T6_E~0); 22293#L1184-1 assume !(1 == ~T7_E~0); 22294#L1189-1 assume !(1 == ~T8_E~0); 22371#L1194-1 assume !(1 == ~T9_E~0); 22494#L1199-1 assume !(1 == ~T10_E~0); 22447#L1204-1 assume !(1 == ~E_M~0); 22448#L1209-1 assume !(1 == ~E_1~0); 22992#L1214-1 assume 1 == ~E_2~0;~E_2~0 := 2; 22993#L1219-1 assume !(1 == ~E_3~0); 23279#L1224-1 assume !(1 == ~E_4~0); 22782#L1229-1 assume !(1 == ~E_5~0); 22175#L1234-1 assume !(1 == ~E_6~0); 22176#L1239-1 assume !(1 == ~E_7~0); 22235#L1244-1 assume !(1 == ~E_8~0); 22236#L1249-1 assume !(1 == ~E_9~0); 23060#L1254-1 assume 1 == ~E_10~0;~E_10~0 := 2; 22073#L1259-1 assume { :end_inline_reset_delta_events } true; 22074#L1565-2 [2022-12-13 12:11:43,390 INFO L750 eck$LassoCheckResult]: Loop: 22074#L1565-2 assume !false; 23000#L1566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 22025#L1011 assume !false; 22464#L862 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 22512#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 22276#L851 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 22609#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 22299#L866 assume !(0 != eval_~tmp~0#1); 22301#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 22801#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 22802#L1036-3 assume 0 == ~M_E~0;~M_E~0 := 1; 23064#L1036-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 23242#L1041-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 23124#L1046-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 23125#L1051-3 assume !(0 == ~T4_E~0); 23065#L1056-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 22323#L1061-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 22324#L1066-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 22325#L1071-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 23244#L1076-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 22065#L1081-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 22066#L1086-3 assume 0 == ~E_M~0;~E_M~0 := 1; 22118#L1091-3 assume !(0 == ~E_1~0); 22119#L1096-3 assume 0 == ~E_2~0;~E_2~0 := 1; 23208#L1101-3 assume 0 == ~E_3~0;~E_3~0 := 1; 23209#L1106-3 assume 0 == ~E_4~0;~E_4~0 := 1; 23241#L1111-3 assume 0 == ~E_5~0;~E_5~0 := 1; 23200#L1116-3 assume 0 == ~E_6~0;~E_6~0 := 1; 22929#L1121-3 assume 0 == ~E_7~0;~E_7~0 := 1; 22930#L1126-3 assume 0 == ~E_8~0;~E_8~0 := 1; 23139#L1131-3 assume !(0 == ~E_9~0); 23140#L1136-3 assume 0 == ~E_10~0;~E_10~0 := 1; 23291#L1141-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 22932#L514-36 assume !(1 == ~m_pc~0); 22645#L514-38 is_master_triggered_~__retres1~0#1 := 0; 22485#L525-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 22486#is_master_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 22971#L1285-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 22380#L1285-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 22381#L533-36 assume 1 == ~t1_pc~0; 22654#L534-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 22747#L544-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 23190#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 23008#L1293-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 22806#L1293-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 22807#L552-36 assume 1 == ~t2_pc~0; 22375#L553-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 22377#L563-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 22865#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 23132#L1301-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 22347#L1301-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 22348#L571-36 assume 1 == ~t3_pc~0; 22729#L572-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 22436#L582-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 22437#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 22624#L1309-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 23123#L1309-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 22407#L590-36 assume !(1 == ~t4_pc~0); 22408#L590-38 is_transmit4_triggered_~__retres1~4#1 := 0; 23021#L601-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 22816#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 22817#L1317-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 23102#L1317-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 23103#L609-36 assume 1 == ~t5_pc~0; 22983#L610-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 22809#L620-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 22810#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 23147#L1325-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 22893#L1325-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 22705#L628-36 assume 1 == ~t6_pc~0; 22555#L629-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 22556#L639-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 22605#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 22606#L1333-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 22934#L1333-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 22935#L647-36 assume 1 == ~t7_pc~0; 22858#L648-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 22092#L658-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 22093#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 22112#L1341-36 assume !(0 != activate_threads_~tmp___6~0#1); 22113#L1341-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 23022#L666-36 assume 1 == ~t8_pc~0; 22304#L667-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 22305#L677-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 22922#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 22923#L1349-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 22455#L1349-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 22456#L685-36 assume 1 == ~t9_pc~0; 22909#L686-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 22207#L696-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 22658#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 22659#L1357-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 22594#L1357-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 22595#L704-36 assume 1 == ~t10_pc~0; 22194#L705-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 22195#L715-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 22517#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 22518#L1365-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 22224#L1365-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 22225#L1154-3 assume 1 == ~M_E~0;~M_E~0 := 2; 23194#L1154-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 23078#L1159-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 23079#L1164-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 23254#L1169-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 22523#L1174-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 22524#L1179-3 assume !(1 == ~T6_E~0); 23169#L1184-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 22094#L1189-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 22095#L1194-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 22467#L1199-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 22468#L1204-3 assume 1 == ~E_M~0;~E_M~0 := 2; 22779#L1209-3 assume 1 == ~E_1~0;~E_1~0 := 2; 21962#L1214-3 assume 1 == ~E_2~0;~E_2~0 := 2; 21963#L1219-3 assume !(1 == ~E_3~0); 22978#L1224-3 assume 1 == ~E_4~0;~E_4~0 := 2; 22979#L1229-3 assume 1 == ~E_5~0;~E_5~0 := 2; 22999#L1234-3 assume 1 == ~E_6~0;~E_6~0 := 2; 22237#L1239-3 assume 1 == ~E_7~0;~E_7~0 := 2; 22238#L1244-3 assume 1 == ~E_8~0;~E_8~0 := 2; 22833#L1249-3 assume 1 == ~E_9~0;~E_9~0 := 2; 23201#L1254-3 assume 1 == ~E_10~0;~E_10~0 := 2; 22981#L1259-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 22982#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 22042#L851-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 22505#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 22506#L1584 assume !(0 == start_simulation_~tmp~3#1); 22940#L1584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 22251#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 21942#L851-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 21994#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 21995#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 22574#L1546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 22822#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 22823#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 22074#L1565-2 [2022-12-13 12:11:43,390 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:11:43,390 INFO L85 PathProgramCache]: Analyzing trace with hash -1581271233, now seen corresponding path program 1 times [2022-12-13 12:11:43,390 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:11:43,390 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [345180827] [2022-12-13 12:11:43,390 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:11:43,390 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:11:43,397 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:11:43,417 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:11:43,417 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:11:43,418 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [345180827] [2022-12-13 12:11:43,418 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [345180827] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:11:43,418 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:11:43,418 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:11:43,418 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [640626474] [2022-12-13 12:11:43,418 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:11:43,418 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 12:11:43,418 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:11:43,419 INFO L85 PathProgramCache]: Analyzing trace with hash -1709033325, now seen corresponding path program 3 times [2022-12-13 12:11:43,419 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:11:43,419 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1398346734] [2022-12-13 12:11:43,419 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:11:43,419 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:11:43,427 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:11:43,454 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:11:43,454 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:11:43,454 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1398346734] [2022-12-13 12:11:43,454 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1398346734] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:11:43,454 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:11:43,454 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:11:43,455 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [8323348] [2022-12-13 12:11:43,455 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:11:43,455 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:11:43,455 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:11:43,455 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 12:11:43,455 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 12:11:43,455 INFO L87 Difference]: Start difference. First operand 1366 states and 2025 transitions. cyclomatic complexity: 660 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:11:43,471 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:11:43,471 INFO L93 Difference]: Finished difference Result 1366 states and 2024 transitions. [2022-12-13 12:11:43,471 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1366 states and 2024 transitions. [2022-12-13 12:11:43,475 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1227 [2022-12-13 12:11:43,478 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1366 states to 1366 states and 2024 transitions. [2022-12-13 12:11:43,478 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1366 [2022-12-13 12:11:43,479 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1366 [2022-12-13 12:11:43,479 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1366 states and 2024 transitions. [2022-12-13 12:11:43,480 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:11:43,480 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1366 states and 2024 transitions. [2022-12-13 12:11:43,481 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1366 states and 2024 transitions. [2022-12-13 12:11:43,491 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1366 to 1366. [2022-12-13 12:11:43,493 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1366 states, 1366 states have (on average 1.4816983894582723) internal successors, (2024), 1365 states have internal predecessors, (2024), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:11:43,495 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1366 states to 1366 states and 2024 transitions. [2022-12-13 12:11:43,495 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1366 states and 2024 transitions. [2022-12-13 12:11:43,495 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 12:11:43,496 INFO L428 stractBuchiCegarLoop]: Abstraction has 1366 states and 2024 transitions. [2022-12-13 12:11:43,496 INFO L335 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2022-12-13 12:11:43,496 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1366 states and 2024 transitions. [2022-12-13 12:11:43,499 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1227 [2022-12-13 12:11:43,499 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:11:43,499 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:11:43,500 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:11:43,500 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:11:43,501 INFO L748 eck$LassoCheckResult]: Stem: 25090#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 25091#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 25952#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 25953#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 26014#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 25956#L731-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 25916#L736-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 25917#L741-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 25945#L746-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 25026#L751-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 25027#L756-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 25132#L761-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 25373#L766-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 25302#L771-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 25028#L776-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 24685#L781-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 24686#L1036 assume !(0 == ~M_E~0); 24783#L1036-2 assume !(0 == ~T1_E~0); 25682#L1041-1 assume !(0 == ~T2_E~0); 25683#L1046-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 25065#L1051-1 assume !(0 == ~T4_E~0); 25066#L1056-1 assume !(0 == ~T5_E~0); 25808#L1061-1 assume !(0 == ~T6_E~0); 24959#L1066-1 assume !(0 == ~T7_E~0); 24960#L1071-1 assume !(0 == ~T8_E~0); 25790#L1076-1 assume !(0 == ~T9_E~0); 24847#L1081-1 assume !(0 == ~T10_E~0); 24848#L1086-1 assume 0 == ~E_M~0;~E_M~0 := 1; 25249#L1091-1 assume !(0 == ~E_1~0); 25963#L1096-1 assume !(0 == ~E_2~0); 25964#L1101-1 assume !(0 == ~E_3~0); 25315#L1106-1 assume !(0 == ~E_4~0); 25316#L1111-1 assume !(0 == ~E_5~0); 25477#L1116-1 assume !(0 == ~E_6~0); 25478#L1121-1 assume !(0 == ~E_7~0); 25306#L1126-1 assume 0 == ~E_8~0;~E_8~0 := 1; 25307#L1131-1 assume !(0 == ~E_9~0); 25575#L1136-1 assume !(0 == ~E_10~0); 25688#L1141-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 25835#L514 assume 1 == ~m_pc~0; 25801#L515 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 25324#L525 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 25325#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 25887#L1285 assume !(0 != activate_threads_~tmp~1#1); 25998#L1285-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 24978#L533 assume !(1 == ~t1_pc~0); 24979#L533-2 is_transmit1_triggered_~__retres1~1#1 := 0; 25492#L544 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 24738#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 24739#L1293 assume !(0 != activate_threads_~tmp___0~0#1); 25711#L1293-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 25712#L552 assume 1 == ~t2_pc~0; 25196#L553 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 25197#L563 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 25310#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 25311#L1301 assume !(0 != activate_threads_~tmp___1~0#1); 25337#L1301-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 25338#L571 assume 1 == ~t3_pc~0; 25528#L572 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 25529#L582 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 24683#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 24684#L1309 assume !(0 != activate_threads_~tmp___2~0#1); 25482#L1309-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 24769#L590 assume !(1 == ~t4_pc~0); 24770#L590-2 is_transmit4_triggered_~__retres1~4#1 := 0; 25538#L601 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 24865#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 24866#L1317 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 25737#L1317-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 25479#L609 assume 1 == ~t5_pc~0; 25480#L610 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 25996#L620 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 25889#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 25890#L1325 assume !(0 != activate_threads_~tmp___4~0#1); 25472#L1325-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 25473#L628 assume !(1 == ~t6_pc~0); 25404#L628-2 is_transmit6_triggered_~__retres1~6#1 := 0; 25403#L639 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 25283#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 25284#L1333 assume !(0 != activate_threads_~tmp___5~0#1); 25771#L1333-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 25772#L647 assume 1 == ~t7_pc~0; 25317#L648 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 25318#L658 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 25898#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 25320#L1341 assume !(0 != activate_threads_~tmp___6~0#1); 25321#L1341-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 26025#L666 assume !(1 == ~t8_pc~0); 25112#L666-2 is_transmit8_triggered_~__retres1~8#1 := 0; 25113#L677 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 25336#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 25503#L1349 assume !(0 != activate_threads_~tmp___7~0#1); 25246#L1349-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 25247#L685 assume 1 == ~t9_pc~0; 26004#L686 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 25906#L696 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 25367#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 25274#L1357 assume !(0 != activate_threads_~tmp___8~0#1); 25275#L1357-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 25653#L704 assume !(1 == ~t10_pc~0); 25266#L704-2 is_transmit10_triggered_~__retres1~10#1 := 0; 25265#L715 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 25517#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 24817#L1365 assume !(0 != activate_threads_~tmp___9~0#1); 24818#L1365-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 25074#L1154 assume !(1 == ~M_E~0); 25759#L1154-2 assume !(1 == ~T1_E~0); 25046#L1159-1 assume !(1 == ~T2_E~0); 25047#L1164-1 assume !(1 == ~T3_E~0); 25501#L1169-1 assume !(1 == ~T4_E~0); 25368#L1174-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 25174#L1179-1 assume !(1 == ~T6_E~0); 25032#L1184-1 assume !(1 == ~T7_E~0); 25033#L1189-1 assume !(1 == ~T8_E~0); 25110#L1194-1 assume !(1 == ~T9_E~0); 25233#L1199-1 assume !(1 == ~T10_E~0); 25186#L1204-1 assume !(1 == ~E_M~0); 25187#L1209-1 assume !(1 == ~E_1~0); 25731#L1214-1 assume 1 == ~E_2~0;~E_2~0 := 2; 25732#L1219-1 assume !(1 == ~E_3~0); 26018#L1224-1 assume !(1 == ~E_4~0); 25521#L1229-1 assume !(1 == ~E_5~0); 24914#L1234-1 assume !(1 == ~E_6~0); 24915#L1239-1 assume !(1 == ~E_7~0); 24974#L1244-1 assume !(1 == ~E_8~0); 24975#L1249-1 assume !(1 == ~E_9~0); 25799#L1254-1 assume 1 == ~E_10~0;~E_10~0 := 2; 24812#L1259-1 assume { :end_inline_reset_delta_events } true; 24813#L1565-2 [2022-12-13 12:11:43,501 INFO L750 eck$LassoCheckResult]: Loop: 24813#L1565-2 assume !false; 25739#L1566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 24764#L1011 assume !false; 25203#L862 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 25251#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 25015#L851 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 25348#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 25038#L866 assume !(0 != eval_~tmp~0#1); 25040#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 25540#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 25541#L1036-3 assume 0 == ~M_E~0;~M_E~0 := 1; 25803#L1036-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 25981#L1041-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 25863#L1046-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 25864#L1051-3 assume !(0 == ~T4_E~0); 25804#L1056-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 25062#L1061-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 25063#L1066-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 25064#L1071-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 25983#L1076-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 24804#L1081-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 24805#L1086-3 assume 0 == ~E_M~0;~E_M~0 := 1; 24857#L1091-3 assume !(0 == ~E_1~0); 24858#L1096-3 assume 0 == ~E_2~0;~E_2~0 := 1; 25947#L1101-3 assume 0 == ~E_3~0;~E_3~0 := 1; 25948#L1106-3 assume 0 == ~E_4~0;~E_4~0 := 1; 25980#L1111-3 assume 0 == ~E_5~0;~E_5~0 := 1; 25939#L1116-3 assume 0 == ~E_6~0;~E_6~0 := 1; 25668#L1121-3 assume 0 == ~E_7~0;~E_7~0 := 1; 25669#L1126-3 assume 0 == ~E_8~0;~E_8~0 := 1; 25878#L1131-3 assume !(0 == ~E_9~0); 25879#L1136-3 assume 0 == ~E_10~0;~E_10~0 := 1; 26030#L1141-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 25671#L514-36 assume !(1 == ~m_pc~0); 25384#L514-38 is_master_triggered_~__retres1~0#1 := 0; 25224#L525-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 25225#is_master_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 25710#L1285-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 25119#L1285-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 25120#L533-36 assume 1 == ~t1_pc~0; 25393#L534-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 25486#L544-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 25929#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 25747#L1293-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 25545#L1293-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 25546#L552-36 assume 1 == ~t2_pc~0; 25114#L553-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 25116#L563-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 25604#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 25871#L1301-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 25086#L1301-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 25087#L571-36 assume 1 == ~t3_pc~0; 25468#L572-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 25175#L582-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 25176#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 25363#L1309-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 25862#L1309-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 25146#L590-36 assume !(1 == ~t4_pc~0); 25147#L590-38 is_transmit4_triggered_~__retres1~4#1 := 0; 25760#L601-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 25556#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 25557#L1317-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 25841#L1317-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 25842#L609-36 assume 1 == ~t5_pc~0; 25722#L610-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 25548#L620-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 25549#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 25886#L1325-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 25632#L1325-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 25444#L628-36 assume !(1 == ~t6_pc~0); 25296#L628-38 is_transmit6_triggered_~__retres1~6#1 := 0; 25295#L639-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 25344#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 25345#L1333-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 25673#L1333-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 25674#L647-36 assume 1 == ~t7_pc~0; 25597#L648-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 24831#L658-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 24832#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 24851#L1341-36 assume !(0 != activate_threads_~tmp___6~0#1); 24852#L1341-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 25761#L666-36 assume 1 == ~t8_pc~0; 25043#L667-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 25044#L677-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 25661#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 25662#L1349-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 25194#L1349-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 25195#L685-36 assume 1 == ~t9_pc~0; 25648#L686-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 24946#L696-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 25397#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 25398#L1357-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 25333#L1357-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 25334#L704-36 assume 1 == ~t10_pc~0; 24933#L705-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 24934#L715-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 25256#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 25257#L1365-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 24963#L1365-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 24964#L1154-3 assume 1 == ~M_E~0;~M_E~0 := 2; 25933#L1154-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 25817#L1159-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 25818#L1164-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 25993#L1169-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 25262#L1174-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 25263#L1179-3 assume !(1 == ~T6_E~0); 25908#L1184-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 24833#L1189-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 24834#L1194-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 25206#L1199-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 25207#L1204-3 assume 1 == ~E_M~0;~E_M~0 := 2; 25518#L1209-3 assume 1 == ~E_1~0;~E_1~0 := 2; 24704#L1214-3 assume 1 == ~E_2~0;~E_2~0 := 2; 24705#L1219-3 assume !(1 == ~E_3~0); 25717#L1224-3 assume 1 == ~E_4~0;~E_4~0 := 2; 25718#L1229-3 assume 1 == ~E_5~0;~E_5~0 := 2; 25738#L1234-3 assume 1 == ~E_6~0;~E_6~0 := 2; 24976#L1239-3 assume 1 == ~E_7~0;~E_7~0 := 2; 24977#L1244-3 assume 1 == ~E_8~0;~E_8~0 := 2; 25572#L1249-3 assume 1 == ~E_9~0;~E_9~0 := 2; 25940#L1254-3 assume 1 == ~E_10~0;~E_10~0 := 2; 25720#L1259-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 25721#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 24781#L851-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 25244#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 25245#L1584 assume !(0 == start_simulation_~tmp~3#1); 25679#L1584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 24990#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 24681#L851-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 24733#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 24734#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 25313#L1546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 25561#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 25562#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 24813#L1565-2 [2022-12-13 12:11:43,501 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:11:43,501 INFO L85 PathProgramCache]: Analyzing trace with hash 711809793, now seen corresponding path program 1 times [2022-12-13 12:11:43,501 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:11:43,501 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [622361627] [2022-12-13 12:11:43,501 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:11:43,501 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:11:43,510 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:11:43,554 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:11:43,554 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:11:43,554 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [622361627] [2022-12-13 12:11:43,554 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [622361627] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:11:43,555 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:11:43,555 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:11:43,555 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2056824250] [2022-12-13 12:11:43,555 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:11:43,555 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 12:11:43,555 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:11:43,555 INFO L85 PathProgramCache]: Analyzing trace with hash -1331390508, now seen corresponding path program 2 times [2022-12-13 12:11:43,555 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:11:43,555 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [877144768] [2022-12-13 12:11:43,555 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:11:43,556 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:11:43,564 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:11:43,589 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:11:43,589 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:11:43,590 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [877144768] [2022-12-13 12:11:43,590 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [877144768] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:11:43,590 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:11:43,590 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:11:43,590 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [708198827] [2022-12-13 12:11:43,590 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:11:43,590 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:11:43,590 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:11:43,591 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 12:11:43,591 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 12:11:43,591 INFO L87 Difference]: Start difference. First operand 1366 states and 2024 transitions. cyclomatic complexity: 659 Second operand has 4 states, 4 states have (on average 32.0) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:11:43,722 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:11:43,722 INFO L93 Difference]: Finished difference Result 2514 states and 3712 transitions. [2022-12-13 12:11:43,722 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2514 states and 3712 transitions. [2022-12-13 12:11:43,734 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2353 [2022-12-13 12:11:43,744 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2514 states to 2514 states and 3712 transitions. [2022-12-13 12:11:43,744 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2514 [2022-12-13 12:11:43,746 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2514 [2022-12-13 12:11:43,746 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2514 states and 3712 transitions. [2022-12-13 12:11:43,749 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:11:43,749 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2514 states and 3712 transitions. [2022-12-13 12:11:43,751 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2514 states and 3712 transitions. [2022-12-13 12:11:43,772 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2514 to 2514. [2022-12-13 12:11:43,775 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2514 states, 2514 states have (on average 1.4765314240254575) internal successors, (3712), 2513 states have internal predecessors, (3712), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:11:43,779 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2514 states to 2514 states and 3712 transitions. [2022-12-13 12:11:43,779 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2514 states and 3712 transitions. [2022-12-13 12:11:43,780 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 12:11:43,780 INFO L428 stractBuchiCegarLoop]: Abstraction has 2514 states and 3712 transitions. [2022-12-13 12:11:43,780 INFO L335 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2022-12-13 12:11:43,780 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2514 states and 3712 transitions. [2022-12-13 12:11:43,787 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2353 [2022-12-13 12:11:43,787 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:11:43,787 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:11:43,788 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:11:43,788 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:11:43,788 INFO L748 eck$LassoCheckResult]: Stem: 28980#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 28981#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 29852#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 29853#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 29923#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 29856#L731-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 29815#L736-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 29816#L741-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 29845#L746-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 28916#L751-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 28917#L756-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 29022#L761-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 29265#L766-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 29193#L771-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 28918#L776-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 28575#L781-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 28576#L1036 assume !(0 == ~M_E~0); 28673#L1036-2 assume !(0 == ~T1_E~0); 29578#L1041-1 assume !(0 == ~T2_E~0); 29579#L1046-1 assume !(0 == ~T3_E~0); 28955#L1051-1 assume !(0 == ~T4_E~0); 28956#L1056-1 assume !(0 == ~T5_E~0); 29706#L1061-1 assume !(0 == ~T6_E~0); 28849#L1066-1 assume !(0 == ~T7_E~0); 28850#L1071-1 assume !(0 == ~T8_E~0); 29688#L1076-1 assume !(0 == ~T9_E~0); 28737#L1081-1 assume !(0 == ~T10_E~0); 28738#L1086-1 assume 0 == ~E_M~0;~E_M~0 := 1; 29140#L1091-1 assume !(0 == ~E_1~0); 29864#L1096-1 assume !(0 == ~E_2~0); 29865#L1101-1 assume !(0 == ~E_3~0); 29206#L1106-1 assume !(0 == ~E_4~0); 29207#L1111-1 assume !(0 == ~E_5~0); 29371#L1116-1 assume !(0 == ~E_6~0); 29372#L1121-1 assume !(0 == ~E_7~0); 29197#L1126-1 assume 0 == ~E_8~0;~E_8~0 := 1; 29198#L1131-1 assume !(0 == ~E_9~0); 29470#L1136-1 assume !(0 == ~E_10~0); 29584#L1141-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 29733#L514 assume 1 == ~m_pc~0; 29699#L515 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 29215#L525 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 29216#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 29785#L1285 assume !(0 != activate_threads_~tmp~1#1); 29904#L1285-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 28868#L533 assume !(1 == ~t1_pc~0); 28869#L533-2 is_transmit1_triggered_~__retres1~1#1 := 0; 29386#L544 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 28628#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 28629#L1293 assume !(0 != activate_threads_~tmp___0~0#1); 29607#L1293-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 29608#L552 assume 1 == ~t2_pc~0; 29086#L553 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 29087#L563 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 29201#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 29202#L1301 assume !(0 != activate_threads_~tmp___1~0#1); 29229#L1301-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 29230#L571 assume 1 == ~t3_pc~0; 29423#L572 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 29424#L582 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 28573#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 28574#L1309 assume !(0 != activate_threads_~tmp___2~0#1); 29376#L1309-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 28659#L590 assume !(1 == ~t4_pc~0); 28660#L590-2 is_transmit4_triggered_~__retres1~4#1 := 0; 29433#L601 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 28755#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 28756#L1317 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 29634#L1317-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 29373#L609 assume 1 == ~t5_pc~0; 29374#L610 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 29902#L620 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 29787#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 29788#L1325 assume !(0 != activate_threads_~tmp___4~0#1); 29366#L1325-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 29367#L628 assume !(1 == ~t6_pc~0); 29297#L628-2 is_transmit6_triggered_~__retres1~6#1 := 0; 29296#L639 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 29174#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 29175#L1333 assume !(0 != activate_threads_~tmp___5~0#1); 29669#L1333-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 29670#L647 assume 1 == ~t7_pc~0; 29208#L648 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 29209#L658 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 29797#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 29211#L1341 assume !(0 != activate_threads_~tmp___6~0#1); 29212#L1341-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 29936#L666 assume !(1 == ~t8_pc~0); 29002#L666-2 is_transmit8_triggered_~__retres1~8#1 := 0; 29003#L677 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 29228#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 29398#L1349 assume !(0 != activate_threads_~tmp___7~0#1); 29137#L1349-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 29138#L685 assume 1 == ~t9_pc~0; 29913#L686 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 29805#L696 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 29259#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 29165#L1357 assume !(0 != activate_threads_~tmp___8~0#1); 29166#L1357-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 29548#L704 assume !(1 == ~t10_pc~0); 29157#L704-2 is_transmit10_triggered_~__retres1~10#1 := 0; 29156#L715 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 29412#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 28707#L1365 assume !(0 != activate_threads_~tmp___9~0#1); 28708#L1365-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 28964#L1154 assume 1 == ~M_E~0;~M_E~0 := 2; 29656#L1154-2 assume !(1 == ~T1_E~0); 30658#L1159-1 assume !(1 == ~T2_E~0); 30656#L1164-1 assume !(1 == ~T3_E~0); 29944#L1169-1 assume !(1 == ~T4_E~0); 30652#L1174-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 30650#L1179-1 assume !(1 == ~T6_E~0); 30648#L1184-1 assume !(1 == ~T7_E~0); 30646#L1189-1 assume !(1 == ~T8_E~0); 30644#L1194-1 assume !(1 == ~T9_E~0); 30641#L1199-1 assume !(1 == ~T10_E~0); 30639#L1204-1 assume !(1 == ~E_M~0); 30638#L1209-1 assume !(1 == ~E_1~0); 30064#L1214-1 assume 1 == ~E_2~0;~E_2~0 := 2; 30052#L1219-1 assume !(1 == ~E_3~0); 30050#L1224-1 assume !(1 == ~E_4~0); 30048#L1229-1 assume !(1 == ~E_5~0); 30046#L1234-1 assume !(1 == ~E_6~0); 30045#L1239-1 assume !(1 == ~E_7~0); 30009#L1244-1 assume !(1 == ~E_8~0); 30008#L1249-1 assume !(1 == ~E_9~0); 29997#L1254-1 assume 1 == ~E_10~0;~E_10~0 := 2; 29986#L1259-1 assume { :end_inline_reset_delta_events } true; 29979#L1565-2 [2022-12-13 12:11:43,788 INFO L750 eck$LassoCheckResult]: Loop: 29979#L1565-2 assume !false; 29973#L1566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 29968#L1011 assume !false; 29967#L862 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 29966#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 29955#L851 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 29954#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 29952#L866 assume !(0 != eval_~tmp~0#1); 29951#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 29950#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 29949#L1036-3 assume 0 == ~M_E~0;~M_E~0 := 1; 29882#L1036-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 29883#L1041-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 29761#L1046-3 assume !(0 == ~T3_E~0); 29762#L1051-3 assume !(0 == ~T4_E~0); 29702#L1056-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 28952#L1061-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 28953#L1066-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 28954#L1071-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 29885#L1076-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 28694#L1081-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 28695#L1086-3 assume 0 == ~E_M~0;~E_M~0 := 1; 28747#L1091-3 assume !(0 == ~E_1~0); 28748#L1096-3 assume 0 == ~E_2~0;~E_2~0 := 1; 29847#L1101-3 assume 0 == ~E_3~0;~E_3~0 := 1; 29848#L1106-3 assume 0 == ~E_4~0;~E_4~0 := 1; 29881#L1111-3 assume 0 == ~E_5~0;~E_5~0 := 1; 29838#L1116-3 assume 0 == ~E_6~0;~E_6~0 := 1; 29563#L1121-3 assume 0 == ~E_7~0;~E_7~0 := 1; 29564#L1126-3 assume 0 == ~E_8~0;~E_8~0 := 1; 29776#L1131-3 assume !(0 == ~E_9~0); 29777#L1136-3 assume 0 == ~E_10~0;~E_10~0 := 1; 29942#L1141-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 29566#L514-36 assume !(1 == ~m_pc~0); 29276#L514-38 is_master_triggered_~__retres1~0#1 := 0; 29115#L525-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 29116#is_master_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 29606#L1285-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 29009#L1285-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 29010#L533-36 assume 1 == ~t1_pc~0; 29286#L534-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 29380#L544-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 29828#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 29644#L1293-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 29440#L1293-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 29441#L552-36 assume 1 == ~t2_pc~0; 29004#L553-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 29006#L563-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 29499#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 29769#L1301-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 28976#L1301-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 28977#L571-36 assume 1 == ~t3_pc~0; 29362#L572-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 29065#L582-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 29066#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 29255#L1309-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 29760#L1309-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 29036#L590-36 assume !(1 == ~t4_pc~0); 29037#L590-38 is_transmit4_triggered_~__retres1~4#1 := 0; 29658#L601-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 29450#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 29451#L1317-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 29739#L1317-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 29740#L609-36 assume 1 == ~t5_pc~0; 29619#L610-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 29443#L620-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 29444#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 29784#L1325-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 29527#L1325-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 29337#L628-36 assume 1 == ~t6_pc~0; 29185#L629-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 29186#L639-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 29236#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 29237#L1333-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 29568#L1333-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 29569#L647-36 assume 1 == ~t7_pc~0; 29492#L648-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 28721#L658-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 28722#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 28741#L1341-36 assume !(0 != activate_threads_~tmp___6~0#1); 28742#L1341-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 29659#L666-36 assume 1 == ~t8_pc~0; 28933#L667-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 28934#L677-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 29556#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 29557#L1349-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 29084#L1349-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 29085#L685-36 assume !(1 == ~t9_pc~0); 28835#L685-38 is_transmit9_triggered_~__retres1~9#1 := 0; 28836#L696-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 29290#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 29291#L1357-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 29224#L1357-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 29225#L704-36 assume 1 == ~t10_pc~0; 28823#L705-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 28824#L715-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 29147#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 29148#L1365-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 28853#L1365-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 28854#L1154-3 assume 1 == ~M_E~0;~M_E~0 := 2; 29832#L1154-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 29715#L1159-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 29716#L1164-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 29898#L1169-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 29153#L1174-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 29154#L1179-3 assume !(1 == ~T6_E~0); 29927#L1184-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 30637#L1189-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 30636#L1194-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 30635#L1199-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 30634#L1204-3 assume 1 == ~E_M~0;~E_M~0 := 2; 30633#L1209-3 assume 1 == ~E_1~0;~E_1~0 := 2; 30632#L1214-3 assume 1 == ~E_2~0;~E_2~0 := 2; 30631#L1219-3 assume !(1 == ~E_3~0); 30629#L1224-3 assume 1 == ~E_4~0;~E_4~0 := 2; 30626#L1229-3 assume 1 == ~E_5~0;~E_5~0 := 2; 30624#L1234-3 assume 1 == ~E_6~0;~E_6~0 := 2; 30622#L1239-3 assume 1 == ~E_7~0;~E_7~0 := 2; 30620#L1244-3 assume 1 == ~E_8~0;~E_8~0 := 2; 30618#L1249-3 assume 1 == ~E_9~0;~E_9~0 := 2; 30616#L1254-3 assume 1 == ~E_10~0;~E_10~0 := 2; 30613#L1259-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 30585#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 30580#L851-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 30578#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 30576#L1584 assume !(0 == start_simulation_~tmp~3#1); 29941#L1584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 30062#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 30051#L851-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 30049#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 30047#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 30010#L1546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 29998#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 29987#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 29979#L1565-2 [2022-12-13 12:11:43,788 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:11:43,789 INFO L85 PathProgramCache]: Analyzing trace with hash 1478663553, now seen corresponding path program 1 times [2022-12-13 12:11:43,789 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:11:43,789 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1490666536] [2022-12-13 12:11:43,789 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:11:43,789 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:11:43,796 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:11:43,834 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:11:43,834 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:11:43,834 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1490666536] [2022-12-13 12:11:43,834 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1490666536] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:11:43,834 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:11:43,834 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:11:43,835 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [938072008] [2022-12-13 12:11:43,835 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:11:43,835 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 12:11:43,835 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:11:43,835 INFO L85 PathProgramCache]: Analyzing trace with hash 1180538902, now seen corresponding path program 1 times [2022-12-13 12:11:43,835 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:11:43,836 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1649664833] [2022-12-13 12:11:43,836 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:11:43,836 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:11:43,846 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:11:43,872 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:11:43,872 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:11:43,873 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1649664833] [2022-12-13 12:11:43,873 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1649664833] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:11:43,873 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:11:43,873 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:11:43,873 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1213552276] [2022-12-13 12:11:43,873 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:11:43,873 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:11:43,873 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:11:43,874 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 12:11:43,874 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 12:11:43,874 INFO L87 Difference]: Start difference. First operand 2514 states and 3712 transitions. cyclomatic complexity: 1200 Second operand has 4 states, 4 states have (on average 32.0) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:11:44,008 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:11:44,008 INFO L93 Difference]: Finished difference Result 4640 states and 6839 transitions. [2022-12-13 12:11:44,008 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4640 states and 6839 transitions. [2022-12-13 12:11:44,028 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4447 [2022-12-13 12:11:44,053 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4640 states to 4640 states and 6839 transitions. [2022-12-13 12:11:44,054 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4640 [2022-12-13 12:11:44,056 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4640 [2022-12-13 12:11:44,056 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4640 states and 6839 transitions. [2022-12-13 12:11:44,060 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:11:44,060 INFO L218 hiAutomatonCegarLoop]: Abstraction has 4640 states and 6839 transitions. [2022-12-13 12:11:44,063 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4640 states and 6839 transitions. [2022-12-13 12:11:44,110 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4640 to 4638. [2022-12-13 12:11:44,116 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4638 states, 4638 states have (on average 1.4741267787839587) internal successors, (6837), 4637 states have internal predecessors, (6837), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:11:44,122 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4638 states to 4638 states and 6837 transitions. [2022-12-13 12:11:44,122 INFO L240 hiAutomatonCegarLoop]: Abstraction has 4638 states and 6837 transitions. [2022-12-13 12:11:44,123 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 12:11:44,123 INFO L428 stractBuchiCegarLoop]: Abstraction has 4638 states and 6837 transitions. [2022-12-13 12:11:44,123 INFO L335 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2022-12-13 12:11:44,123 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4638 states and 6837 transitions. [2022-12-13 12:11:44,135 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4447 [2022-12-13 12:11:44,135 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:11:44,135 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:11:44,136 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:11:44,137 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:11:44,137 INFO L748 eck$LassoCheckResult]: Stem: 36149#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 36150#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 37082#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 37083#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 37173#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 37087#L731-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 37038#L736-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 37039#L741-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 37074#L746-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 36084#L751-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 36085#L756-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 36193#L761-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 36444#L766-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 36370#L771-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 36086#L776-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 35739#L781-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 35740#L1036 assume !(0 == ~M_E~0); 35837#L1036-2 assume !(0 == ~T1_E~0); 36767#L1041-1 assume !(0 == ~T2_E~0); 36768#L1046-1 assume !(0 == ~T3_E~0); 36124#L1051-1 assume !(0 == ~T4_E~0); 36125#L1056-1 assume !(0 == ~T5_E~0); 36910#L1061-1 assume !(0 == ~T6_E~0); 36014#L1066-1 assume !(0 == ~T7_E~0); 36015#L1071-1 assume !(0 == ~T8_E~0); 36890#L1076-1 assume !(0 == ~T9_E~0); 35901#L1081-1 assume !(0 == ~T10_E~0); 35902#L1086-1 assume !(0 == ~E_M~0); 36315#L1091-1 assume !(0 == ~E_1~0); 37098#L1096-1 assume !(0 == ~E_2~0); 37099#L1101-1 assume !(0 == ~E_3~0); 36383#L1106-1 assume !(0 == ~E_4~0); 36384#L1111-1 assume !(0 == ~E_5~0); 36551#L1116-1 assume !(0 == ~E_6~0); 36552#L1121-1 assume !(0 == ~E_7~0); 36374#L1126-1 assume 0 == ~E_8~0;~E_8~0 := 1; 36375#L1131-1 assume !(0 == ~E_9~0); 36654#L1136-1 assume !(0 == ~E_10~0); 36778#L1141-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 36941#L514 assume 1 == ~m_pc~0; 36902#L515 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 36392#L525 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 36393#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 37002#L1285 assume !(0 != activate_threads_~tmp~1#1); 37147#L1285-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 36033#L533 assume !(1 == ~t1_pc~0); 36034#L533-2 is_transmit1_triggered_~__retres1~1#1 := 0; 36566#L544 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 35794#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 35795#L1293 assume !(0 != activate_threads_~tmp___0~0#1); 36804#L1293-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 36805#L552 assume 1 == ~t2_pc~0; 36261#L553 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 36262#L563 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 36378#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 36379#L1301 assume !(0 != activate_threads_~tmp___1~0#1); 36410#L1301-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 36411#L571 assume 1 == ~t3_pc~0; 36608#L572 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 36609#L582 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 35737#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 35738#L1309 assume !(0 != activate_threads_~tmp___2~0#1); 36556#L1309-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 35823#L590 assume !(1 == ~t4_pc~0); 35824#L590-2 is_transmit4_triggered_~__retres1~4#1 := 0; 36618#L601 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 35919#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 35920#L1317 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 36835#L1317-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 36553#L609 assume 1 == ~t5_pc~0; 36554#L610 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 37143#L620 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 37003#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 37004#L1325 assume !(0 != activate_threads_~tmp___4~0#1); 36546#L1325-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 36547#L628 assume !(1 == ~t6_pc~0); 36475#L628-2 is_transmit6_triggered_~__retres1~6#1 := 0; 36474#L639 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 36354#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 36355#L1333 assume !(0 != activate_threads_~tmp___5~0#1); 36869#L1333-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 36870#L647 assume 1 == ~t7_pc~0; 36385#L648 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 36386#L658 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 37013#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 36390#L1341 assume !(0 != activate_threads_~tmp___6~0#1); 36391#L1341-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 37192#L666 assume !(1 == ~t8_pc~0); 36173#L666-2 is_transmit8_triggered_~__retres1~8#1 := 0; 36174#L677 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 36404#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 36580#L1349 assume !(0 != activate_threads_~tmp___7~0#1); 36313#L1349-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 36314#L685 assume 1 == ~t9_pc~0; 37156#L686 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 37026#L696 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 36437#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 36340#L1357 assume !(0 != activate_threads_~tmp___8~0#1); 36341#L1357-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 36738#L704 assume !(1 == ~t10_pc~0); 36332#L704-2 is_transmit10_triggered_~__retres1~10#1 := 0; 36331#L715 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 36596#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 35871#L1365 assume !(0 != activate_threads_~tmp___9~0#1); 35872#L1365-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 36133#L1154 assume 1 == ~M_E~0;~M_E~0 := 2; 36856#L1154-2 assume !(1 == ~T1_E~0); 37177#L1159-1 assume !(1 == ~T2_E~0); 37223#L1164-1 assume !(1 == ~T3_E~0); 37224#L1169-1 assume !(1 == ~T4_E~0); 36438#L1174-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 36439#L1179-1 assume !(1 == ~T6_E~0); 37637#L1184-1 assume !(1 == ~T7_E~0); 37635#L1189-1 assume !(1 == ~T8_E~0); 36300#L1194-1 assume !(1 == ~T9_E~0); 36301#L1199-1 assume !(1 == ~T10_E~0); 37229#L1204-1 assume !(1 == ~E_M~0); 37407#L1209-1 assume !(1 == ~E_1~0); 37406#L1214-1 assume 1 == ~E_2~0;~E_2~0 := 2; 37405#L1219-1 assume !(1 == ~E_3~0); 37404#L1224-1 assume !(1 == ~E_4~0); 37403#L1229-1 assume !(1 == ~E_5~0); 37325#L1234-1 assume !(1 == ~E_6~0); 37322#L1239-1 assume !(1 == ~E_7~0); 37319#L1244-1 assume !(1 == ~E_8~0); 37316#L1249-1 assume !(1 == ~E_9~0); 37312#L1254-1 assume 1 == ~E_10~0;~E_10~0 := 2; 37270#L1259-1 assume { :end_inline_reset_delta_events } true; 37263#L1565-2 [2022-12-13 12:11:44,137 INFO L750 eck$LassoCheckResult]: Loop: 37263#L1565-2 assume !false; 37257#L1566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 37252#L1011 assume !false; 37251#L862 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 37250#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 37239#L851 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 37238#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 37236#L866 assume !(0 != eval_~tmp~0#1); 37235#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 37234#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 37232#L1036-3 assume 0 == ~M_E~0;~M_E~0 := 1; 37233#L1036-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 38673#L1041-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 38671#L1046-3 assume !(0 == ~T3_E~0); 38669#L1051-3 assume !(0 == ~T4_E~0); 38667#L1056-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 38665#L1061-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 38663#L1066-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 38660#L1071-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 38658#L1076-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 38656#L1081-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 38654#L1086-3 assume !(0 == ~E_M~0); 38652#L1091-3 assume !(0 == ~E_1~0); 38650#L1096-3 assume 0 == ~E_2~0;~E_2~0 := 1; 38647#L1101-3 assume 0 == ~E_3~0;~E_3~0 := 1; 38645#L1106-3 assume 0 == ~E_4~0;~E_4~0 := 1; 38643#L1111-3 assume 0 == ~E_5~0;~E_5~0 := 1; 38641#L1116-3 assume 0 == ~E_6~0;~E_6~0 := 1; 38639#L1121-3 assume 0 == ~E_7~0;~E_7~0 := 1; 38637#L1126-3 assume 0 == ~E_8~0;~E_8~0 := 1; 38634#L1131-3 assume !(0 == ~E_9~0); 38632#L1136-3 assume 0 == ~E_10~0;~E_10~0 := 1; 38630#L1141-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 38628#L514-36 assume 1 == ~m_pc~0; 38625#L515-12 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 38623#L525-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 38620#is_master_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 38618#L1285-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 38616#L1285-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 38614#L533-36 assume 1 == ~t1_pc~0; 38611#L534-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 38610#L544-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 38609#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 38608#L1293-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 38607#L1293-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 38606#L552-36 assume !(1 == ~t2_pc~0); 38604#L552-38 is_transmit2_triggered_~__retres1~2#1 := 0; 38603#L563-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 38602#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 38601#L1301-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 38600#L1301-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 38598#L571-36 assume 1 == ~t3_pc~0; 38595#L572-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 36237#L582-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 36238#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 36433#L1309-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 36971#L1309-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 36207#L590-36 assume !(1 == ~t4_pc~0); 36208#L590-38 is_transmit4_triggered_~__retres1~4#1 := 0; 36858#L601-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 37084#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 38213#L1317-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 38211#L1317-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 38209#L609-36 assume 1 == ~t5_pc~0; 38206#L610-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 38204#L620-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 38203#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 38202#L1325-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 38201#L1325-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 36516#L628-36 assume 1 == ~t6_pc~0; 36362#L629-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 36363#L639-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 36413#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 36414#L1333-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 36758#L1333-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 36759#L647-36 assume 1 == ~t7_pc~0; 37782#L648-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 37762#L658-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 37760#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 37758#L1341-36 assume !(0 != activate_threads_~tmp___6~0#1); 37742#L1341-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 37741#L666-36 assume 1 == ~t8_pc~0; 37724#L667-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 37698#L677-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 37696#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 37694#L1349-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 37692#L1349-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 37691#L685-36 assume !(1 == ~t9_pc~0); 37689#L685-38 is_transmit9_triggered_~__retres1~9#1 := 0; 37688#L696-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 36468#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 36469#L1357-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 36401#L1357-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 36402#L704-36 assume 1 == ~t10_pc~0; 35987#L705-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 35988#L715-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 36322#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 36323#L1365-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 36018#L1365-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 36019#L1154-3 assume 1 == ~M_E~0;~M_E~0 := 2; 37058#L1154-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 37059#L1159-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 37559#L1164-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 37541#L1169-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 37539#L1174-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 37537#L1179-3 assume !(1 == ~T6_E~0); 37523#L1184-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 37512#L1189-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 37510#L1194-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 37508#L1199-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 37498#L1204-3 assume 1 == ~E_M~0;~E_M~0 := 2; 37489#L1209-3 assume 1 == ~E_1~0;~E_1~0 := 2; 37483#L1214-3 assume 1 == ~E_2~0;~E_2~0 := 2; 37478#L1219-3 assume !(1 == ~E_3~0); 37477#L1224-3 assume 1 == ~E_4~0;~E_4~0 := 2; 37476#L1229-3 assume 1 == ~E_5~0;~E_5~0 := 2; 37475#L1234-3 assume 1 == ~E_6~0;~E_6~0 := 2; 37474#L1239-3 assume 1 == ~E_7~0;~E_7~0 := 2; 37473#L1244-3 assume 1 == ~E_8~0;~E_8~0 := 2; 37472#L1249-3 assume 1 == ~E_9~0;~E_9~0 := 2; 37471#L1254-3 assume 1 == ~E_10~0;~E_10~0 := 2; 37470#L1259-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 37456#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 37451#L851-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 37448#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 37445#L1584 assume !(0 == start_simulation_~tmp~3#1); 37217#L1584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 37439#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 37426#L851-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 37423#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 37420#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 37416#L1546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 37330#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 37271#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 37263#L1565-2 [2022-12-13 12:11:44,137 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:11:44,137 INFO L85 PathProgramCache]: Analyzing trace with hash 171521155, now seen corresponding path program 1 times [2022-12-13 12:11:44,137 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:11:44,137 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2109260975] [2022-12-13 12:11:44,138 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:11:44,138 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:11:44,145 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:11:44,180 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:11:44,181 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:11:44,181 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2109260975] [2022-12-13 12:11:44,181 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2109260975] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:11:44,181 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:11:44,181 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:11:44,181 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1368617017] [2022-12-13 12:11:44,181 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:11:44,182 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 12:11:44,182 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:11:44,182 INFO L85 PathProgramCache]: Analyzing trace with hash -1743972968, now seen corresponding path program 1 times [2022-12-13 12:11:44,182 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:11:44,182 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [872652151] [2022-12-13 12:11:44,182 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:11:44,183 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:11:44,194 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:11:44,218 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:11:44,218 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:11:44,218 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [872652151] [2022-12-13 12:11:44,219 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [872652151] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:11:44,219 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:11:44,219 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:11:44,219 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [14552577] [2022-12-13 12:11:44,219 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:11:44,219 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:11:44,219 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:11:44,220 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 12:11:44,220 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 12:11:44,220 INFO L87 Difference]: Start difference. First operand 4638 states and 6837 transitions. cyclomatic complexity: 2203 Second operand has 4 states, 4 states have (on average 32.0) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:11:44,394 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:11:44,395 INFO L93 Difference]: Finished difference Result 8692 states and 12784 transitions. [2022-12-13 12:11:44,395 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 8692 states and 12784 transitions. [2022-12-13 12:11:44,421 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 8477 [2022-12-13 12:11:44,441 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 8692 states to 8692 states and 12784 transitions. [2022-12-13 12:11:44,441 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8692 [2022-12-13 12:11:44,446 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8692 [2022-12-13 12:11:44,446 INFO L73 IsDeterministic]: Start isDeterministic. Operand 8692 states and 12784 transitions. [2022-12-13 12:11:44,454 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:11:44,454 INFO L218 hiAutomatonCegarLoop]: Abstraction has 8692 states and 12784 transitions. [2022-12-13 12:11:44,460 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8692 states and 12784 transitions. [2022-12-13 12:11:44,533 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8692 to 8688. [2022-12-13 12:11:44,543 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 8688 states, 8688 states have (on average 1.4709944751381216) internal successors, (12780), 8687 states have internal predecessors, (12780), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:11:44,557 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8688 states to 8688 states and 12780 transitions. [2022-12-13 12:11:44,557 INFO L240 hiAutomatonCegarLoop]: Abstraction has 8688 states and 12780 transitions. [2022-12-13 12:11:44,557 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 12:11:44,558 INFO L428 stractBuchiCegarLoop]: Abstraction has 8688 states and 12780 transitions. [2022-12-13 12:11:44,558 INFO L335 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2022-12-13 12:11:44,558 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 8688 states and 12780 transitions. [2022-12-13 12:11:44,596 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 8477 [2022-12-13 12:11:44,596 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:11:44,596 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:11:44,597 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:11:44,597 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:11:44,598 INFO L748 eck$LassoCheckResult]: Stem: 49485#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 49486#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 50386#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 50387#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 50454#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 50390#L731-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 50344#L736-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 50345#L741-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 50379#L746-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 49421#L751-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 49422#L756-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 49530#L761-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 49777#L766-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 49705#L771-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 49423#L776-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 49079#L781-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 49080#L1036 assume !(0 == ~M_E~0); 49177#L1036-2 assume !(0 == ~T1_E~0); 50095#L1041-1 assume !(0 == ~T2_E~0); 50096#L1046-1 assume !(0 == ~T3_E~0); 49460#L1051-1 assume !(0 == ~T4_E~0); 49461#L1056-1 assume !(0 == ~T5_E~0); 50229#L1061-1 assume !(0 == ~T6_E~0); 49353#L1066-1 assume !(0 == ~T7_E~0); 49354#L1071-1 assume !(0 == ~T8_E~0); 50211#L1076-1 assume !(0 == ~T9_E~0); 49241#L1081-1 assume !(0 == ~T10_E~0); 49242#L1086-1 assume !(0 == ~E_M~0); 49652#L1091-1 assume !(0 == ~E_1~0); 50397#L1096-1 assume !(0 == ~E_2~0); 50398#L1101-1 assume !(0 == ~E_3~0); 49718#L1106-1 assume !(0 == ~E_4~0); 49719#L1111-1 assume !(0 == ~E_5~0); 49885#L1116-1 assume !(0 == ~E_6~0); 49886#L1121-1 assume !(0 == ~E_7~0); 49709#L1126-1 assume !(0 == ~E_8~0); 49710#L1131-1 assume !(0 == ~E_9~0); 49987#L1136-1 assume !(0 == ~E_10~0); 50101#L1141-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 50256#L514 assume 1 == ~m_pc~0; 50222#L515 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 49727#L525 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 49728#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 50314#L1285 assume !(0 != activate_threads_~tmp~1#1); 50437#L1285-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 49373#L533 assume !(1 == ~t1_pc~0); 49374#L533-2 is_transmit1_triggered_~__retres1~1#1 := 0; 49900#L544 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 49132#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 49133#L1293 assume !(0 != activate_threads_~tmp___0~0#1); 50127#L1293-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 50128#L552 assume 1 == ~t2_pc~0; 49598#L553 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 49599#L563 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 49713#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 49714#L1301 assume !(0 != activate_threads_~tmp___1~0#1); 49741#L1301-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 49742#L571 assume 1 == ~t3_pc~0; 49937#L572 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 49938#L582 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 49077#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 49078#L1309 assume !(0 != activate_threads_~tmp___2~0#1); 49890#L1309-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 49163#L590 assume !(1 == ~t4_pc~0); 49164#L590-2 is_transmit4_triggered_~__retres1~4#1 := 0; 49947#L601 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 49259#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 49260#L1317 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 50154#L1317-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 49887#L609 assume 1 == ~t5_pc~0; 49888#L610 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 50435#L620 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 50316#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 50317#L1325 assume !(0 != activate_threads_~tmp___4~0#1); 49879#L1325-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 49880#L628 assume !(1 == ~t6_pc~0); 49809#L628-2 is_transmit6_triggered_~__retres1~6#1 := 0; 49808#L639 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 49686#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 49687#L1333 assume !(0 != activate_threads_~tmp___5~0#1); 50192#L1333-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 50193#L647 assume 1 == ~t7_pc~0; 49720#L648 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 49721#L658 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 50325#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 49723#L1341 assume !(0 != activate_threads_~tmp___6~0#1); 49724#L1341-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 50472#L666 assume !(1 == ~t8_pc~0); 49510#L666-2 is_transmit8_triggered_~__retres1~8#1 := 0; 49511#L677 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 49740#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 49912#L1349 assume !(0 != activate_threads_~tmp___7~0#1); 49649#L1349-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 49650#L685 assume 1 == ~t9_pc~0; 50443#L686 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 50333#L696 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 49771#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 49677#L1357 assume !(0 != activate_threads_~tmp___8~0#1); 49678#L1357-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 50066#L704 assume !(1 == ~t10_pc~0); 49669#L704-2 is_transmit10_triggered_~__retres1~10#1 := 0; 49668#L715 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 49926#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 49211#L1365 assume !(0 != activate_threads_~tmp___9~0#1); 49212#L1365-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 49469#L1154 assume 1 == ~M_E~0;~M_E~0 := 2; 50179#L1154-2 assume !(1 == ~T1_E~0); 50459#L1159-1 assume !(1 == ~T2_E~0); 50486#L1164-1 assume !(1 == ~T3_E~0); 49910#L1169-1 assume !(1 == ~T4_E~0); 49772#L1174-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 49573#L1179-1 assume !(1 == ~T6_E~0); 49427#L1184-1 assume !(1 == ~T7_E~0); 49428#L1189-1 assume !(1 == ~T8_E~0); 49635#L1194-1 assume !(1 == ~T9_E~0); 49636#L1199-1 assume !(1 == ~T10_E~0); 50636#L1204-1 assume !(1 == ~E_M~0); 50634#L1209-1 assume !(1 == ~E_1~0); 50632#L1214-1 assume 1 == ~E_2~0;~E_2~0 := 2; 50630#L1219-1 assume !(1 == ~E_3~0); 50627#L1224-1 assume !(1 == ~E_4~0); 50625#L1229-1 assume !(1 == ~E_5~0); 50623#L1234-1 assume !(1 == ~E_6~0); 50621#L1239-1 assume !(1 == ~E_7~0); 50562#L1244-1 assume !(1 == ~E_8~0); 50559#L1249-1 assume !(1 == ~E_9~0); 50544#L1254-1 assume 1 == ~E_10~0;~E_10~0 := 2; 50533#L1259-1 assume { :end_inline_reset_delta_events } true; 50526#L1565-2 [2022-12-13 12:11:44,598 INFO L750 eck$LassoCheckResult]: Loop: 50526#L1565-2 assume !false; 50520#L1566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 50515#L1011 assume !false; 50514#L862 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 50513#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 50502#L851 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 50501#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 50499#L866 assume !(0 != eval_~tmp~0#1); 50498#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 50497#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 50495#L1036-3 assume 0 == ~M_E~0;~M_E~0 := 1; 50496#L1036-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 51818#L1041-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 51817#L1046-3 assume !(0 == ~T3_E~0); 51815#L1051-3 assume !(0 == ~T4_E~0); 51813#L1056-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 51707#L1061-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 51628#L1066-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 51626#L1071-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 51623#L1076-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 51621#L1081-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 51619#L1086-3 assume !(0 == ~E_M~0); 51618#L1091-3 assume !(0 == ~E_1~0); 51617#L1096-3 assume 0 == ~E_2~0;~E_2~0 := 1; 51616#L1101-3 assume 0 == ~E_3~0;~E_3~0 := 1; 51615#L1106-3 assume 0 == ~E_4~0;~E_4~0 := 1; 51613#L1111-3 assume 0 == ~E_5~0;~E_5~0 := 1; 51611#L1116-3 assume 0 == ~E_6~0;~E_6~0 := 1; 51609#L1121-3 assume 0 == ~E_7~0;~E_7~0 := 1; 51491#L1126-3 assume !(0 == ~E_8~0); 51302#L1131-3 assume !(0 == ~E_9~0); 51261#L1136-3 assume 0 == ~E_10~0;~E_10~0 := 1; 51259#L1141-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 51257#L514-36 assume 1 == ~m_pc~0; 51252#L515-12 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 51251#L525-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 51249#is_master_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 51247#L1285-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 51246#L1285-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 51215#L533-36 assume 1 == ~t1_pc~0; 51190#L534-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 51188#L544-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 51133#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 51130#L1293-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 51128#L1293-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 51127#L552-36 assume !(1 == ~t2_pc~0); 51125#L552-38 is_transmit2_triggered_~__retres1~2#1 := 0; 51097#L563-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 51080#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 51071#L1301-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 51066#L1301-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 51060#L571-36 assume 1 == ~t3_pc~0; 51054#L572-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 51047#L582-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 51042#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 51036#L1309-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 51030#L1309-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 51025#L590-36 assume !(1 == ~t4_pc~0); 51019#L590-38 is_transmit4_triggered_~__retres1~4#1 := 0; 51013#L601-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 51007#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 51001#L1317-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 50995#L1317-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 50990#L609-36 assume 1 == ~t5_pc~0; 50984#L610-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 50978#L620-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 50972#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 50966#L1325-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 50960#L1325-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 50955#L628-36 assume !(1 == ~t6_pc~0); 50949#L628-38 is_transmit6_triggered_~__retres1~6#1 := 0; 50943#L639-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 50937#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 50931#L1333-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 50925#L1333-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 50920#L647-36 assume 1 == ~t7_pc~0; 50914#L648-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 50908#L658-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 50902#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 50896#L1341-36 assume !(0 != activate_threads_~tmp___6~0#1); 50890#L1341-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 50885#L666-36 assume !(1 == ~t8_pc~0); 50880#L666-38 is_transmit8_triggered_~__retres1~8#1 := 0; 50873#L677-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 50869#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 50866#L1349-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 50863#L1349-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 50861#L685-36 assume !(1 == ~t9_pc~0); 50850#L685-38 is_transmit9_triggered_~__retres1~9#1 := 0; 50842#L696-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 50837#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 50832#L1357-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 50827#L1357-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 50820#L704-36 assume 1 == ~t10_pc~0; 50817#L705-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 50808#L715-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 50803#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 50798#L1365-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 50793#L1365-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 50788#L1154-3 assume 1 == ~M_E~0;~M_E~0 := 2; 50490#L1154-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 50778#L1159-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 50773#L1164-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 50766#L1169-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 50763#L1174-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 50760#L1179-3 assume !(1 == ~T6_E~0); 50757#L1184-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 50753#L1189-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 50750#L1194-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 50747#L1199-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 50744#L1204-3 assume 1 == ~E_M~0;~E_M~0 := 2; 50740#L1209-3 assume 1 == ~E_1~0;~E_1~0 := 2; 50738#L1214-3 assume 1 == ~E_2~0;~E_2~0 := 2; 50735#L1219-3 assume !(1 == ~E_3~0); 50733#L1224-3 assume 1 == ~E_4~0;~E_4~0 := 2; 50732#L1229-3 assume 1 == ~E_5~0;~E_5~0 := 2; 50731#L1234-3 assume 1 == ~E_6~0;~E_6~0 := 2; 50729#L1239-3 assume 1 == ~E_7~0;~E_7~0 := 2; 50719#L1244-3 assume 1 == ~E_8~0;~E_8~0 := 2; 50711#L1249-3 assume 1 == ~E_9~0;~E_9~0 := 2; 50706#L1254-3 assume 1 == ~E_10~0;~E_10~0 := 2; 50694#L1259-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 50681#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 50675#L851-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 50670#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 50666#L1584 assume !(0 == start_simulation_~tmp~3#1); 50480#L1584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 50656#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 50645#L851-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 50643#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 50567#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 50565#L1546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 50548#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 50534#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 50526#L1565-2 [2022-12-13 12:11:44,598 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:11:44,598 INFO L85 PathProgramCache]: Analyzing trace with hash -711987835, now seen corresponding path program 1 times [2022-12-13 12:11:44,599 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:11:44,599 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [95501758] [2022-12-13 12:11:44,599 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:11:44,599 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:11:44,609 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:11:44,648 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:11:44,648 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:11:44,648 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [95501758] [2022-12-13 12:11:44,648 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [95501758] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:11:44,648 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:11:44,649 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-12-13 12:11:44,649 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1996080371] [2022-12-13 12:11:44,649 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:11:44,649 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 12:11:44,650 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:11:44,650 INFO L85 PathProgramCache]: Analyzing trace with hash -1521667172, now seen corresponding path program 1 times [2022-12-13 12:11:44,650 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:11:44,650 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [686416915] [2022-12-13 12:11:44,650 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:11:44,650 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:11:44,663 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:11:44,693 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:11:44,694 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:11:44,694 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [686416915] [2022-12-13 12:11:44,694 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [686416915] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:11:44,694 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:11:44,694 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:11:44,694 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [74832433] [2022-12-13 12:11:44,694 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:11:44,695 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:11:44,695 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:11:44,695 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 12:11:44,695 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 12:11:44,696 INFO L87 Difference]: Start difference. First operand 8688 states and 12780 transitions. cyclomatic complexity: 4100 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 2 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:11:44,816 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:11:44,816 INFO L93 Difference]: Finished difference Result 17011 states and 24827 transitions. [2022-12-13 12:11:44,816 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 17011 states and 24827 transitions. [2022-12-13 12:11:44,868 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 16793 [2022-12-13 12:11:44,907 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 17011 states to 17011 states and 24827 transitions. [2022-12-13 12:11:44,907 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 17011 [2022-12-13 12:11:44,918 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 17011 [2022-12-13 12:11:44,918 INFO L73 IsDeterministic]: Start isDeterministic. Operand 17011 states and 24827 transitions. [2022-12-13 12:11:44,960 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:11:44,961 INFO L218 hiAutomatonCegarLoop]: Abstraction has 17011 states and 24827 transitions. [2022-12-13 12:11:44,973 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17011 states and 24827 transitions. [2022-12-13 12:11:45,128 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17011 to 16403. [2022-12-13 12:11:45,142 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 16403 states, 16403 states have (on average 1.4613790160336524) internal successors, (23971), 16402 states have internal predecessors, (23971), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:11:45,167 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16403 states to 16403 states and 23971 transitions. [2022-12-13 12:11:45,167 INFO L240 hiAutomatonCegarLoop]: Abstraction has 16403 states and 23971 transitions. [2022-12-13 12:11:45,168 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 12:11:45,168 INFO L428 stractBuchiCegarLoop]: Abstraction has 16403 states and 23971 transitions. [2022-12-13 12:11:45,168 INFO L335 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2022-12-13 12:11:45,168 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 16403 states and 23971 transitions. [2022-12-13 12:11:45,203 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 16185 [2022-12-13 12:11:45,203 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:11:45,203 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:11:45,204 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:11:45,204 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:11:45,204 INFO L748 eck$LassoCheckResult]: Stem: 75204#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 75205#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 76207#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 76208#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 76303#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 76213#L731-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 76148#L736-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 76149#L741-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 76199#L746-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 75134#L751-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 75135#L756-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 75248#L761-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 75504#L766-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 75429#L771-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 75136#L776-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 74785#L781-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 74786#L1036 assume !(0 == ~M_E~0); 74883#L1036-2 assume !(0 == ~T1_E~0); 75844#L1041-1 assume !(0 == ~T2_E~0); 75845#L1046-1 assume !(0 == ~T3_E~0); 75178#L1051-1 assume !(0 == ~T4_E~0); 75179#L1056-1 assume !(0 == ~T5_E~0); 75994#L1061-1 assume !(0 == ~T6_E~0); 75062#L1066-1 assume !(0 == ~T7_E~0); 75063#L1071-1 assume !(0 == ~T8_E~0); 75976#L1076-1 assume !(0 == ~T9_E~0); 74947#L1081-1 assume !(0 == ~T10_E~0); 74948#L1086-1 assume !(0 == ~E_M~0); 75375#L1091-1 assume !(0 == ~E_1~0); 76222#L1096-1 assume !(0 == ~E_2~0); 76223#L1101-1 assume !(0 == ~E_3~0); 75442#L1106-1 assume !(0 == ~E_4~0); 75443#L1111-1 assume !(0 == ~E_5~0); 75617#L1116-1 assume !(0 == ~E_6~0); 75618#L1121-1 assume !(0 == ~E_7~0); 75433#L1126-1 assume !(0 == ~E_8~0); 75434#L1131-1 assume !(0 == ~E_9~0); 75724#L1136-1 assume !(0 == ~E_10~0); 75854#L1141-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 76033#L514 assume !(1 == ~m_pc~0); 76034#L514-2 is_master_triggered_~__retres1~0#1 := 0; 75451#L525 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 75452#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 76105#L1285 assume !(0 != activate_threads_~tmp~1#1); 76278#L1285-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 75085#L533 assume !(1 == ~t1_pc~0); 75086#L533-2 is_transmit1_triggered_~__retres1~1#1 := 0; 75633#L544 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 74840#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 74841#L1293 assume !(0 != activate_threads_~tmp___0~0#1); 75885#L1293-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 75886#L552 assume 1 == ~t2_pc~0; 75318#L553 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 75319#L563 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 75437#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 75438#L1301 assume !(0 != activate_threads_~tmp___1~0#1); 75472#L1301-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 75473#L571 assume 1 == ~t3_pc~0; 75675#L572 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 75676#L582 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 74783#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 74784#L1309 assume !(0 != activate_threads_~tmp___2~0#1); 75622#L1309-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 74869#L590 assume !(1 == ~t4_pc~0); 74870#L590-2 is_transmit4_triggered_~__retres1~4#1 := 0; 75684#L601 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 74965#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 74966#L1317 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 75915#L1317-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 75619#L609 assume 1 == ~t5_pc~0; 75620#L610 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 76272#L620 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 76106#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 76107#L1325 assume !(0 != activate_threads_~tmp___4~0#1); 75611#L1325-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 75612#L628 assume !(1 == ~t6_pc~0); 75538#L628-2 is_transmit6_triggered_~__retres1~6#1 := 0; 75537#L639 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 75413#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 75414#L1333 assume !(0 != activate_threads_~tmp___5~0#1); 75956#L1333-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 75957#L647 assume 1 == ~t7_pc~0; 75444#L648 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 75445#L658 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 76119#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 75449#L1341 assume !(0 != activate_threads_~tmp___6~0#1); 75450#L1341-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 76335#L666 assume !(1 == ~t8_pc~0); 75229#L666-2 is_transmit8_triggered_~__retres1~8#1 := 0; 75230#L677 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 75465#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 75646#L1349 assume !(0 != activate_threads_~tmp___7~0#1); 75371#L1349-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 75372#L685 assume 1 == ~t9_pc~0; 76283#L686 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 76131#L696 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 75498#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 75399#L1357 assume !(0 != activate_threads_~tmp___8~0#1); 75400#L1357-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 75813#L704 assume !(1 == ~t10_pc~0); 75391#L704-2 is_transmit10_triggered_~__retres1~10#1 := 0; 75390#L715 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 75663#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 74917#L1365 assume !(0 != activate_threads_~tmp___9~0#1); 74918#L1365-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 75186#L1154 assume 1 == ~M_E~0;~M_E~0 := 2; 75942#L1154-2 assume !(1 == ~T1_E~0); 75154#L1159-1 assume !(1 == ~T2_E~0); 75155#L1164-1 assume !(1 == ~T3_E~0); 84461#L1169-1 assume !(1 == ~T4_E~0); 84459#L1174-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 84457#L1179-1 assume !(1 == ~T6_E~0); 84455#L1184-1 assume !(1 == ~T7_E~0); 84452#L1189-1 assume !(1 == ~T8_E~0); 84450#L1194-1 assume !(1 == ~T9_E~0); 84448#L1199-1 assume !(1 == ~T10_E~0); 84446#L1204-1 assume !(1 == ~E_M~0); 84444#L1209-1 assume !(1 == ~E_1~0); 84443#L1214-1 assume 1 == ~E_2~0;~E_2~0 := 2; 84414#L1219-1 assume !(1 == ~E_3~0); 84396#L1224-1 assume !(1 == ~E_4~0); 84394#L1229-1 assume !(1 == ~E_5~0); 84393#L1234-1 assume !(1 == ~E_6~0); 84392#L1239-1 assume !(1 == ~E_7~0); 84390#L1244-1 assume !(1 == ~E_8~0); 84374#L1249-1 assume !(1 == ~E_9~0); 84362#L1254-1 assume 1 == ~E_10~0;~E_10~0 := 2; 84351#L1259-1 assume { :end_inline_reset_delta_events } true; 84344#L1565-2 [2022-12-13 12:11:45,205 INFO L750 eck$LassoCheckResult]: Loop: 84344#L1565-2 assume !false; 84338#L1566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 84333#L1011 assume !false; 84332#L862 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 84331#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 84320#L851 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 84319#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 84317#L866 assume !(0 != eval_~tmp~0#1); 84318#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 87731#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 87729#L1036-3 assume 0 == ~M_E~0;~M_E~0 := 1; 87727#L1036-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 87512#L1041-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 87482#L1046-3 assume !(0 == ~T3_E~0); 87475#L1051-3 assume !(0 == ~T4_E~0); 87470#L1056-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 87461#L1061-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 87455#L1066-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 87448#L1071-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 87442#L1076-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 87436#L1081-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 87430#L1086-3 assume !(0 == ~E_M~0); 87422#L1091-3 assume !(0 == ~E_1~0); 87415#L1096-3 assume 0 == ~E_2~0;~E_2~0 := 1; 87408#L1101-3 assume 0 == ~E_3~0;~E_3~0 := 1; 87402#L1106-3 assume 0 == ~E_4~0;~E_4~0 := 1; 87396#L1111-3 assume 0 == ~E_5~0;~E_5~0 := 1; 87391#L1116-3 assume 0 == ~E_6~0;~E_6~0 := 1; 87386#L1121-3 assume 0 == ~E_7~0;~E_7~0 := 1; 87383#L1126-3 assume !(0 == ~E_8~0); 87382#L1131-3 assume !(0 == ~E_9~0); 87381#L1136-3 assume 0 == ~E_10~0;~E_10~0 := 1; 87380#L1141-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 87379#L514-36 assume !(1 == ~m_pc~0); 87378#L514-38 is_master_triggered_~__retres1~0#1 := 0; 87377#L525-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 87376#is_master_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 87375#L1285-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 87374#L1285-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 87373#L533-36 assume !(1 == ~t1_pc~0); 87371#L533-38 is_transmit1_triggered_~__retres1~1#1 := 0; 87368#L544-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 87366#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 87364#L1293-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 87362#L1293-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 87360#L552-36 assume !(1 == ~t2_pc~0); 87357#L552-38 is_transmit2_triggered_~__retres1~2#1 := 0; 87355#L563-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 87353#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 87351#L1301-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 87349#L1301-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 87347#L571-36 assume !(1 == ~t3_pc~0); 87343#L571-38 is_transmit3_triggered_~__retres1~3#1 := 0; 87339#L582-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 87337#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 87335#L1309-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 87333#L1309-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 87331#L590-36 assume 1 == ~t4_pc~0; 87329#L591-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 87327#L601-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 87324#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 87322#L1317-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 87320#L1317-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 87318#L609-36 assume 1 == ~t5_pc~0; 87315#L610-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 87313#L620-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 87310#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 87308#L1325-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 87306#L1325-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 87304#L628-36 assume !(1 == ~t6_pc~0); 87299#L628-38 is_transmit6_triggered_~__retres1~6#1 := 0; 87297#L639-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 87295#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 87293#L1333-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 87291#L1333-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 87289#L647-36 assume !(1 == ~t7_pc~0); 87287#L647-38 is_transmit7_triggered_~__retres1~7#1 := 0; 87284#L658-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 87282#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 87280#L1341-36 assume !(0 != activate_threads_~tmp___6~0#1); 87278#L1341-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 87276#L666-36 assume 1 == ~t8_pc~0; 87273#L667-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 87271#L677-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 87269#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 87267#L1349-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 87265#L1349-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 87263#L685-36 assume !(1 == ~t9_pc~0); 87259#L685-38 is_transmit9_triggered_~__retres1~9#1 := 0; 87256#L696-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 87254#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 87252#L1357-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 87250#L1357-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 87248#L704-36 assume 1 == ~t10_pc~0; 87173#L705-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 87162#L715-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 87153#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 87145#L1365-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 87135#L1365-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 87127#L1154-3 assume 1 == ~M_E~0;~M_E~0 := 2; 77201#L1154-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 87108#L1159-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 87100#L1164-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 77160#L1169-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 87083#L1174-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 87076#L1179-3 assume !(1 == ~T6_E~0); 87069#L1184-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 87059#L1189-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 87052#L1194-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 87045#L1199-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 87036#L1204-3 assume 1 == ~E_M~0;~E_M~0 := 2; 85733#L1209-3 assume 1 == ~E_1~0;~E_1~0 := 2; 87024#L1214-3 assume 1 == ~E_2~0;~E_2~0 := 2; 87014#L1219-3 assume !(1 == ~E_3~0); 87007#L1224-3 assume 1 == ~E_4~0;~E_4~0 := 2; 87000#L1229-3 assume 1 == ~E_5~0;~E_5~0 := 2; 86991#L1234-3 assume 1 == ~E_6~0;~E_6~0 := 2; 86984#L1239-3 assume 1 == ~E_7~0;~E_7~0 := 2; 86977#L1244-3 assume 1 == ~E_8~0;~E_8~0 := 2; 86973#L1249-3 assume 1 == ~E_9~0;~E_9~0 := 2; 86972#L1254-3 assume 1 == ~E_10~0;~E_10~0 := 2; 86971#L1259-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 86961#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 86957#L851-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 86954#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 86952#L1584 assume !(0 == start_simulation_~tmp~3#1); 76365#L1584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 84441#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 84413#L851-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 84395#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 84379#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 84375#L1546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 84363#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 84352#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 84344#L1565-2 [2022-12-13 12:11:45,205 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:11:45,205 INFO L85 PathProgramCache]: Analyzing trace with hash -2098669114, now seen corresponding path program 1 times [2022-12-13 12:11:45,205 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:11:45,205 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1537275227] [2022-12-13 12:11:45,205 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:11:45,205 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:11:45,213 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:11:45,270 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:11:45,270 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:11:45,270 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1537275227] [2022-12-13 12:11:45,271 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1537275227] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:11:45,271 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:11:45,271 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:11:45,271 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [410710702] [2022-12-13 12:11:45,271 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:11:45,271 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 12:11:45,272 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:11:45,272 INFO L85 PathProgramCache]: Analyzing trace with hash 1300845662, now seen corresponding path program 1 times [2022-12-13 12:11:45,272 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:11:45,272 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [453967726] [2022-12-13 12:11:45,272 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:11:45,272 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:11:45,280 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:11:45,306 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:11:45,306 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:11:45,307 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [453967726] [2022-12-13 12:11:45,307 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [453967726] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:11:45,307 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:11:45,307 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:11:45,307 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [61335039] [2022-12-13 12:11:45,307 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:11:45,308 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:11:45,308 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:11:45,308 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 12:11:45,308 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 12:11:45,309 INFO L87 Difference]: Start difference. First operand 16403 states and 23971 transitions. cyclomatic complexity: 7584 Second operand has 4 states, 4 states have (on average 32.0) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:11:45,734 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:11:45,734 INFO L93 Difference]: Finished difference Result 39772 states and 57640 transitions. [2022-12-13 12:11:45,734 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 39772 states and 57640 transitions. [2022-12-13 12:11:45,922 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 38883 [2022-12-13 12:11:46,004 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 39772 states to 39772 states and 57640 transitions. [2022-12-13 12:11:46,004 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 39772 [2022-12-13 12:11:46,024 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 39772 [2022-12-13 12:11:46,024 INFO L73 IsDeterministic]: Start isDeterministic. Operand 39772 states and 57640 transitions. [2022-12-13 12:11:46,046 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:11:46,046 INFO L218 hiAutomatonCegarLoop]: Abstraction has 39772 states and 57640 transitions. [2022-12-13 12:11:46,073 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 39772 states and 57640 transitions. [2022-12-13 12:11:46,368 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 39772 to 31137. [2022-12-13 12:11:46,392 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 31137 states, 31137 states have (on average 1.454764428172271) internal successors, (45297), 31136 states have internal predecessors, (45297), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:11:46,445 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 31137 states to 31137 states and 45297 transitions. [2022-12-13 12:11:46,445 INFO L240 hiAutomatonCegarLoop]: Abstraction has 31137 states and 45297 transitions. [2022-12-13 12:11:46,445 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 12:11:46,446 INFO L428 stractBuchiCegarLoop]: Abstraction has 31137 states and 45297 transitions. [2022-12-13 12:11:46,446 INFO L335 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2022-12-13 12:11:46,446 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 31137 states and 45297 transitions. [2022-12-13 12:11:46,543 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 30912 [2022-12-13 12:11:46,543 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:11:46,543 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:11:46,545 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:11:46,545 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:11:46,545 INFO L748 eck$LassoCheckResult]: Stem: 131373#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 131374#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 132326#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 132327#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 132411#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 132330#L731-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 132280#L736-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 132281#L741-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 132319#L746-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 131308#L751-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 131309#L756-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 131415#L761-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 131666#L766-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 131591#L771-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 131310#L776-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 130970#L781-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 130971#L1036 assume !(0 == ~M_E~0); 131067#L1036-2 assume !(0 == ~T1_E~0); 132005#L1041-1 assume !(0 == ~T2_E~0); 132006#L1046-1 assume !(0 == ~T3_E~0); 131348#L1051-1 assume !(0 == ~T4_E~0); 131349#L1056-1 assume !(0 == ~T5_E~0); 132148#L1061-1 assume !(0 == ~T6_E~0); 131242#L1066-1 assume !(0 == ~T7_E~0); 131243#L1071-1 assume !(0 == ~T8_E~0); 132131#L1076-1 assume !(0 == ~T9_E~0); 131130#L1081-1 assume !(0 == ~T10_E~0); 131131#L1086-1 assume !(0 == ~E_M~0); 131538#L1091-1 assume !(0 == ~E_1~0); 132341#L1096-1 assume !(0 == ~E_2~0); 132342#L1101-1 assume !(0 == ~E_3~0); 131604#L1106-1 assume !(0 == ~E_4~0); 131605#L1111-1 assume !(0 == ~E_5~0); 131781#L1116-1 assume !(0 == ~E_6~0); 131782#L1121-1 assume !(0 == ~E_7~0); 131595#L1126-1 assume !(0 == ~E_8~0); 131596#L1131-1 assume !(0 == ~E_9~0); 131887#L1136-1 assume !(0 == ~E_10~0); 132014#L1141-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 132183#L514 assume !(1 == ~m_pc~0); 132184#L514-2 is_master_triggered_~__retres1~0#1 := 0; 131613#L525 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 131614#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 132251#L1285 assume !(0 != activate_threads_~tmp~1#1); 132389#L1285-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 131261#L533 assume !(1 == ~t1_pc~0); 131262#L533-2 is_transmit1_triggered_~__retres1~1#1 := 0; 131798#L544 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 131022#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 131023#L1293 assume !(0 != activate_threads_~tmp___0~0#1); 132041#L1293-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 132042#L552 assume !(1 == ~t2_pc~0); 131742#L552-2 is_transmit2_triggered_~__retres1~2#1 := 0; 131743#L563 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 131599#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 131600#L1301 assume !(0 != activate_threads_~tmp___1~0#1); 131626#L1301-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 131627#L571 assume 1 == ~t3_pc~0; 131837#L572 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 131838#L582 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 130968#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 130969#L1309 assume !(0 != activate_threads_~tmp___2~0#1); 131787#L1309-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 131053#L590 assume !(1 == ~t4_pc~0); 131054#L590-2 is_transmit4_triggered_~__retres1~4#1 := 0; 131849#L601 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 131148#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 131149#L1317 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 132070#L1317-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 131783#L609 assume 1 == ~t5_pc~0; 131784#L610 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 132387#L620 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 132253#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 132254#L1325 assume !(0 != activate_threads_~tmp___4~0#1); 131776#L1325-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 131777#L628 assume !(1 == ~t6_pc~0); 131700#L628-2 is_transmit6_triggered_~__retres1~6#1 := 0; 131699#L639 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 131572#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 131573#L1333 assume !(0 != activate_threads_~tmp___5~0#1); 132108#L1333-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 132109#L647 assume 1 == ~t7_pc~0; 131606#L648 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 131607#L658 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 132261#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 131609#L1341 assume !(0 != activate_threads_~tmp___6~0#1); 131610#L1341-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 132443#L666 assume !(1 == ~t8_pc~0); 131396#L666-2 is_transmit8_triggered_~__retres1~8#1 := 0; 131397#L677 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 131625#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 131810#L1349 assume !(0 != activate_threads_~tmp___7~0#1); 131535#L1349-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 131536#L685 assume 1 == ~t9_pc~0; 132399#L686 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 132269#L696 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 131659#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 131562#L1357 assume !(0 != activate_threads_~tmp___8~0#1); 131563#L1357-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 131973#L704 assume !(1 == ~t10_pc~0); 131555#L704-2 is_transmit10_triggered_~__retres1~10#1 := 0; 131554#L715 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 131824#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 131100#L1365 assume !(0 != activate_threads_~tmp___9~0#1); 131101#L1365-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 131357#L1154 assume 1 == ~M_E~0;~M_E~0 := 2; 132093#L1154-2 assume !(1 == ~T1_E~0); 132424#L1159-1 assume !(1 == ~T2_E~0); 132469#L1164-1 assume !(1 == ~T3_E~0); 132470#L1169-1 assume !(1 == ~T4_E~0); 131660#L1174-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 131661#L1179-1 assume !(1 == ~T6_E~0); 131314#L1184-1 assume !(1 == ~T7_E~0); 131315#L1189-1 assume !(1 == ~T8_E~0); 131521#L1194-1 assume !(1 == ~T9_E~0); 131522#L1199-1 assume !(1 == ~T10_E~0); 131471#L1204-1 assume !(1 == ~E_M~0); 131472#L1209-1 assume !(1 == ~E_1~0); 132064#L1214-1 assume 1 == ~E_2~0;~E_2~0 := 2; 132065#L1219-1 assume !(1 == ~E_3~0); 132426#L1224-1 assume !(1 == ~E_4~0); 132427#L1229-1 assume !(1 == ~E_5~0); 131197#L1234-1 assume !(1 == ~E_6~0); 131198#L1239-1 assume !(1 == ~E_7~0); 131257#L1244-1 assume !(1 == ~E_8~0); 131258#L1249-1 assume !(1 == ~E_9~0); 145519#L1254-1 assume 1 == ~E_10~0;~E_10~0 := 2; 145517#L1259-1 assume { :end_inline_reset_delta_events } true; 145506#L1565-2 [2022-12-13 12:11:46,546 INFO L750 eck$LassoCheckResult]: Loop: 145506#L1565-2 assume !false; 145496#L1566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 145486#L1011 assume !false; 145484#L862 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 145309#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 145290#L851 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 141641#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 141639#L866 assume !(0 != eval_~tmp~0#1); 141640#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 146090#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 146088#L1036-3 assume 0 == ~M_E~0;~M_E~0 := 1; 146086#L1036-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 146084#L1041-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 146082#L1046-3 assume !(0 == ~T3_E~0); 146080#L1051-3 assume !(0 == ~T4_E~0); 146077#L1056-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 146075#L1061-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 146073#L1066-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 146071#L1071-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 146069#L1076-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 146067#L1081-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 146064#L1086-3 assume !(0 == ~E_M~0); 146062#L1091-3 assume !(0 == ~E_1~0); 146060#L1096-3 assume 0 == ~E_2~0;~E_2~0 := 1; 146058#L1101-3 assume 0 == ~E_3~0;~E_3~0 := 1; 146056#L1106-3 assume 0 == ~E_4~0;~E_4~0 := 1; 146054#L1111-3 assume 0 == ~E_5~0;~E_5~0 := 1; 146051#L1116-3 assume 0 == ~E_6~0;~E_6~0 := 1; 146049#L1121-3 assume 0 == ~E_7~0;~E_7~0 := 1; 146047#L1126-3 assume !(0 == ~E_8~0); 146045#L1131-3 assume !(0 == ~E_9~0); 146043#L1136-3 assume 0 == ~E_10~0;~E_10~0 := 1; 146041#L1141-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 146038#L514-36 assume !(1 == ~m_pc~0); 146036#L514-38 is_master_triggered_~__retres1~0#1 := 0; 146034#L525-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 146032#is_master_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 146030#L1285-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 146028#L1285-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 146025#L533-36 assume 1 == ~t1_pc~0; 146022#L534-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 146020#L544-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 146018#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 146016#L1293-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 146014#L1293-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 146011#L552-36 assume !(1 == ~t2_pc~0); 136776#L552-38 is_transmit2_triggered_~__retres1~2#1 := 0; 146008#L563-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 146006#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 146004#L1301-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 146002#L1301-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 146000#L571-36 assume !(1 == ~t3_pc~0); 145998#L571-38 is_transmit3_triggered_~__retres1~3#1 := 0; 145996#L582-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 145995#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 145994#L1309-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 145993#L1309-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 145992#L590-36 assume !(1 == ~t4_pc~0); 145990#L590-38 is_transmit4_triggered_~__retres1~4#1 := 0; 145989#L601-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 145988#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 145987#L1317-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 145986#L1317-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 145985#L609-36 assume 1 == ~t5_pc~0; 145982#L610-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 145980#L620-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 145978#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 145976#L1325-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 145974#L1325-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 145971#L628-36 assume !(1 == ~t6_pc~0); 145968#L628-38 is_transmit6_triggered_~__retres1~6#1 := 0; 145966#L639-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 145964#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 145962#L1333-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 145960#L1333-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 145959#L647-36 assume 1 == ~t7_pc~0; 145955#L648-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 145953#L658-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 145951#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 145949#L1341-36 assume !(0 != activate_threads_~tmp___6~0#1); 145947#L1341-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 145945#L666-36 assume !(1 == ~t8_pc~0); 145942#L666-38 is_transmit8_triggered_~__retres1~8#1 := 0; 145939#L677-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 145937#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 145935#L1349-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 145933#L1349-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 145931#L685-36 assume !(1 == ~t9_pc~0); 145927#L685-38 is_transmit9_triggered_~__retres1~9#1 := 0; 145925#L696-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 145923#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 145921#L1357-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 145919#L1357-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 145917#L704-36 assume !(1 == ~t10_pc~0); 145914#L704-38 is_transmit10_triggered_~__retres1~10#1 := 0; 145911#L715-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 145909#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 145907#L1365-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 145905#L1365-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 145903#L1154-3 assume 1 == ~M_E~0;~M_E~0 := 2; 142456#L1154-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 145898#L1159-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 145894#L1164-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 145890#L1169-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 145888#L1174-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 145886#L1179-3 assume !(1 == ~T6_E~0); 145884#L1184-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 145882#L1189-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 145880#L1194-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 145878#L1199-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 145877#L1204-3 assume 1 == ~E_M~0;~E_M~0 := 2; 145874#L1209-3 assume 1 == ~E_1~0;~E_1~0 := 2; 145873#L1214-3 assume 1 == ~E_2~0;~E_2~0 := 2; 145872#L1219-3 assume !(1 == ~E_3~0); 145870#L1224-3 assume 1 == ~E_4~0;~E_4~0 := 2; 145868#L1229-3 assume 1 == ~E_5~0;~E_5~0 := 2; 145866#L1234-3 assume 1 == ~E_6~0;~E_6~0 := 2; 145864#L1239-3 assume 1 == ~E_7~0;~E_7~0 := 2; 145862#L1244-3 assume 1 == ~E_8~0;~E_8~0 := 2; 143940#L1249-3 assume 1 == ~E_9~0;~E_9~0 := 2; 145859#L1254-3 assume 1 == ~E_10~0;~E_10~0 := 2; 145856#L1259-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 145839#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 145835#L851-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 145833#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 145830#L1584 assume !(0 == start_simulation_~tmp~3#1); 132462#L1584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 145575#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 145564#L851-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 145562#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 145560#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 145555#L1546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 145550#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 145518#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 145506#L1565-2 [2022-12-13 12:11:46,546 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:11:46,546 INFO L85 PathProgramCache]: Analyzing trace with hash 353984391, now seen corresponding path program 1 times [2022-12-13 12:11:46,546 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:11:46,546 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1232878209] [2022-12-13 12:11:46,546 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:11:46,547 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:11:46,560 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:11:46,605 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:11:46,605 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:11:46,605 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1232878209] [2022-12-13 12:11:46,605 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1232878209] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:11:46,605 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:11:46,605 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:11:46,606 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1897028153] [2022-12-13 12:11:46,606 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:11:46,606 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 12:11:46,606 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:11:46,606 INFO L85 PathProgramCache]: Analyzing trace with hash -142014049, now seen corresponding path program 1 times [2022-12-13 12:11:46,607 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:11:46,607 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1952265595] [2022-12-13 12:11:46,607 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:11:46,607 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:11:46,617 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:11:46,647 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:11:46,647 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:11:46,647 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1952265595] [2022-12-13 12:11:46,647 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1952265595] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:11:46,647 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:11:46,647 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:11:46,647 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [160478890] [2022-12-13 12:11:46,648 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:11:46,648 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:11:46,648 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:11:46,648 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 12:11:46,648 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 12:11:46,649 INFO L87 Difference]: Start difference. First operand 31137 states and 45297 transitions. cyclomatic complexity: 14176 Second operand has 4 states, 4 states have (on average 32.0) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:11:47,131 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:11:47,131 INFO L93 Difference]: Finished difference Result 75513 states and 109021 transitions. [2022-12-13 12:11:47,131 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 75513 states and 109021 transitions. [2022-12-13 12:11:47,385 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 73953 [2022-12-13 12:11:47,561 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 75513 states to 75513 states and 109021 transitions. [2022-12-13 12:11:47,561 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 75513 [2022-12-13 12:11:47,588 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 75513 [2022-12-13 12:11:47,588 INFO L73 IsDeterministic]: Start isDeterministic. Operand 75513 states and 109021 transitions. [2022-12-13 12:11:47,691 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:11:47,691 INFO L218 hiAutomatonCegarLoop]: Abstraction has 75513 states and 109021 transitions. [2022-12-13 12:11:47,721 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 75513 states and 109021 transitions. [2022-12-13 12:11:48,090 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 75513 to 59180. [2022-12-13 12:11:48,132 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 59180 states, 59180 states have (on average 1.4490368367691788) internal successors, (85754), 59179 states have internal predecessors, (85754), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:11:48,203 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 59180 states to 59180 states and 85754 transitions. [2022-12-13 12:11:48,203 INFO L240 hiAutomatonCegarLoop]: Abstraction has 59180 states and 85754 transitions. [2022-12-13 12:11:48,204 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 12:11:48,204 INFO L428 stractBuchiCegarLoop]: Abstraction has 59180 states and 85754 transitions. [2022-12-13 12:11:48,204 INFO L335 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2022-12-13 12:11:48,204 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 59180 states and 85754 transitions. [2022-12-13 12:11:48,395 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 58940 [2022-12-13 12:11:48,395 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:11:48,395 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:11:48,397 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:11:48,397 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:11:48,397 INFO L748 eck$LassoCheckResult]: Stem: 238035#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 238036#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 239000#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 239001#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 239075#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 239003#L731-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 238959#L736-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 238960#L741-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 238992#L746-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 237970#L751-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 237971#L756-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 238079#L761-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 238330#L766-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 238255#L771-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 237972#L776-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 237630#L781-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 237631#L1036 assume !(0 == ~M_E~0); 237727#L1036-2 assume !(0 == ~T1_E~0); 238673#L1041-1 assume !(0 == ~T2_E~0); 238674#L1046-1 assume !(0 == ~T3_E~0); 238010#L1051-1 assume !(0 == ~T4_E~0); 238011#L1056-1 assume !(0 == ~T5_E~0); 238823#L1061-1 assume !(0 == ~T6_E~0); 237903#L1066-1 assume !(0 == ~T7_E~0); 237904#L1071-1 assume !(0 == ~T8_E~0); 238806#L1076-1 assume !(0 == ~T9_E~0); 237792#L1081-1 assume !(0 == ~T10_E~0); 237793#L1086-1 assume !(0 == ~E_M~0); 238202#L1091-1 assume !(0 == ~E_1~0); 239014#L1096-1 assume !(0 == ~E_2~0); 239015#L1101-1 assume !(0 == ~E_3~0); 238268#L1106-1 assume !(0 == ~E_4~0); 238269#L1111-1 assume !(0 == ~E_5~0); 238446#L1116-1 assume !(0 == ~E_6~0); 238447#L1121-1 assume !(0 == ~E_7~0); 238259#L1126-1 assume !(0 == ~E_8~0); 238260#L1131-1 assume !(0 == ~E_9~0); 238555#L1136-1 assume !(0 == ~E_10~0); 238680#L1141-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 238850#L514 assume !(1 == ~m_pc~0); 238851#L514-2 is_master_triggered_~__retres1~0#1 := 0; 238277#L525 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 238278#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 238922#L1285 assume !(0 != activate_threads_~tmp~1#1); 239056#L1285-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 237923#L533 assume !(1 == ~t1_pc~0); 237924#L533-2 is_transmit1_triggered_~__retres1~1#1 := 0; 238465#L544 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 237682#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 237683#L1293 assume !(0 != activate_threads_~tmp___0~0#1); 238705#L1293-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 238706#L552 assume !(1 == ~t2_pc~0); 238408#L552-2 is_transmit2_triggered_~__retres1~2#1 := 0; 238409#L563 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 238263#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 238264#L1301 assume !(0 != activate_threads_~tmp___1~0#1); 238291#L1301-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 238292#L571 assume !(1 == ~t3_pc~0); 238521#L571-2 is_transmit3_triggered_~__retres1~3#1 := 0; 238609#L582 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 237628#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 237629#L1309 assume !(0 != activate_threads_~tmp___2~0#1); 238453#L1309-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 237713#L590 assume !(1 == ~t4_pc~0); 237714#L590-2 is_transmit4_triggered_~__retres1~4#1 := 0; 238512#L601 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 237810#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 237811#L1317 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 238734#L1317-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 238448#L609 assume 1 == ~t5_pc~0; 238449#L610 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 239054#L620 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 238924#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 238925#L1325 assume !(0 != activate_threads_~tmp___4~0#1); 238441#L1325-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 238442#L628 assume !(1 == ~t6_pc~0); 238364#L628-2 is_transmit6_triggered_~__retres1~6#1 := 0; 238363#L639 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 238236#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 238237#L1333 assume !(0 != activate_threads_~tmp___5~0#1); 238778#L1333-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 238779#L647 assume 1 == ~t7_pc~0; 238270#L648 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 238271#L658 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 238935#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 238273#L1341 assume !(0 != activate_threads_~tmp___6~0#1); 238274#L1341-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 239106#L666 assume !(1 == ~t8_pc~0); 238058#L666-2 is_transmit8_triggered_~__retres1~8#1 := 0; 238059#L677 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 238290#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 238477#L1349 assume !(0 != activate_threads_~tmp___7~0#1); 238199#L1349-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 238200#L685 assume 1 == ~t9_pc~0; 239064#L686 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 238945#L696 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 238323#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 238226#L1357 assume !(0 != activate_threads_~tmp___8~0#1); 238227#L1357-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 238640#L704 assume !(1 == ~t10_pc~0); 238219#L704-2 is_transmit10_triggered_~__retres1~10#1 := 0; 238218#L715 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 238493#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 237762#L1365 assume !(0 != activate_threads_~tmp___9~0#1); 237763#L1365-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 238019#L1154 assume 1 == ~M_E~0;~M_E~0 := 2; 238763#L1154-2 assume !(1 == ~T1_E~0); 239085#L1159-1 assume !(1 == ~T2_E~0); 239136#L1164-1 assume !(1 == ~T3_E~0); 239137#L1169-1 assume !(1 == ~T4_E~0); 238324#L1174-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 238325#L1179-1 assume !(1 == ~T6_E~0); 237976#L1184-1 assume !(1 == ~T7_E~0); 237977#L1189-1 assume !(1 == ~T8_E~0); 238184#L1194-1 assume !(1 == ~T9_E~0); 238185#L1199-1 assume !(1 == ~T10_E~0); 238138#L1204-1 assume !(1 == ~E_M~0); 238139#L1209-1 assume !(1 == ~E_1~0); 260606#L1214-1 assume 1 == ~E_2~0;~E_2~0 := 2; 260605#L1219-1 assume !(1 == ~E_3~0); 260604#L1224-1 assume !(1 == ~E_4~0); 260603#L1229-1 assume !(1 == ~E_5~0); 260602#L1234-1 assume !(1 == ~E_6~0); 260601#L1239-1 assume !(1 == ~E_7~0); 260600#L1244-1 assume !(1 == ~E_8~0); 260598#L1249-1 assume !(1 == ~E_9~0); 260597#L1254-1 assume 1 == ~E_10~0;~E_10~0 := 2; 260595#L1259-1 assume { :end_inline_reset_delta_events } true; 260592#L1565-2 [2022-12-13 12:11:48,398 INFO L750 eck$LassoCheckResult]: Loop: 260592#L1565-2 assume !false; 260581#L1566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 260572#L1011 assume !false; 260568#L862 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 260451#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 260436#L851 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 260428#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 260422#L866 assume !(0 != eval_~tmp~0#1); 260423#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 261301#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 261300#L1036-3 assume 0 == ~M_E~0;~M_E~0 := 1; 261299#L1036-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 261298#L1041-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 261297#L1046-3 assume !(0 == ~T3_E~0); 261296#L1051-3 assume !(0 == ~T4_E~0); 261295#L1056-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 261294#L1061-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 261293#L1066-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 261292#L1071-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 261291#L1076-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 261289#L1081-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 261287#L1086-3 assume !(0 == ~E_M~0); 261285#L1091-3 assume !(0 == ~E_1~0); 261283#L1096-3 assume 0 == ~E_2~0;~E_2~0 := 1; 261281#L1101-3 assume 0 == ~E_3~0;~E_3~0 := 1; 261279#L1106-3 assume 0 == ~E_4~0;~E_4~0 := 1; 261277#L1111-3 assume 0 == ~E_5~0;~E_5~0 := 1; 261276#L1116-3 assume 0 == ~E_6~0;~E_6~0 := 1; 261274#L1121-3 assume 0 == ~E_7~0;~E_7~0 := 1; 261272#L1126-3 assume !(0 == ~E_8~0); 261270#L1131-3 assume !(0 == ~E_9~0); 261268#L1136-3 assume 0 == ~E_10~0;~E_10~0 := 1; 261266#L1141-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 261263#L514-36 assume !(1 == ~m_pc~0); 261261#L514-38 is_master_triggered_~__retres1~0#1 := 0; 261259#L525-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 261257#is_master_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 261255#L1285-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 261253#L1285-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 261250#L533-36 assume !(1 == ~t1_pc~0); 261248#L533-38 is_transmit1_triggered_~__retres1~1#1 := 0; 261245#L544-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 261243#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 261241#L1293-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 261239#L1293-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 261236#L552-36 assume !(1 == ~t2_pc~0); 260192#L552-38 is_transmit2_triggered_~__retres1~2#1 := 0; 261233#L563-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 261231#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 261229#L1301-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 261227#L1301-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 261224#L571-36 assume !(1 == ~t3_pc~0); 249701#L571-38 is_transmit3_triggered_~__retres1~3#1 := 0; 261221#L582-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 261219#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 261217#L1309-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 261215#L1309-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 261212#L590-36 assume 1 == ~t4_pc~0; 261210#L591-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 261207#L601-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 261205#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 261203#L1317-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 261201#L1317-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 261198#L609-36 assume !(1 == ~t5_pc~0); 261139#L609-38 is_transmit5_triggered_~__retres1~5#1 := 0; 261136#L620-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 261134#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 261132#L1325-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 261130#L1325-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 261127#L628-36 assume 1 == ~t6_pc~0; 261125#L629-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 261122#L639-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 261120#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 261118#L1333-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 261116#L1333-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 261115#L647-36 assume 1 == ~t7_pc~0; 261111#L648-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 261109#L658-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 261107#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 261105#L1341-36 assume !(0 != activate_threads_~tmp___6~0#1); 261103#L1341-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 261101#L666-36 assume !(1 == ~t8_pc~0); 261098#L666-38 is_transmit8_triggered_~__retres1~8#1 := 0; 261095#L677-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 261093#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 261091#L1349-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 261089#L1349-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 261087#L685-36 assume !(1 == ~t9_pc~0); 261083#L685-38 is_transmit9_triggered_~__retres1~9#1 := 0; 261081#L696-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 261079#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 261077#L1357-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 261075#L1357-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 261073#L704-36 assume !(1 == ~t10_pc~0); 261070#L704-38 is_transmit10_triggered_~__retres1~10#1 := 0; 261067#L715-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 261065#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 261063#L1365-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 261061#L1365-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 261059#L1154-3 assume 1 == ~M_E~0;~M_E~0 := 2; 255434#L1154-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 261054#L1159-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 261052#L1164-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 261048#L1169-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 261046#L1174-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 261044#L1179-3 assume !(1 == ~T6_E~0); 261042#L1184-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 261040#L1189-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 261038#L1194-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 261036#L1199-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 261034#L1204-3 assume 1 == ~E_M~0;~E_M~0 := 2; 255406#L1209-3 assume 1 == ~E_1~0;~E_1~0 := 2; 261031#L1214-3 assume 1 == ~E_2~0;~E_2~0 := 2; 261029#L1219-3 assume !(1 == ~E_3~0); 261027#L1224-3 assume 1 == ~E_4~0;~E_4~0 := 2; 261025#L1229-3 assume 1 == ~E_5~0;~E_5~0 := 2; 261023#L1234-3 assume 1 == ~E_6~0;~E_6~0 := 2; 261021#L1239-3 assume 1 == ~E_7~0;~E_7~0 := 2; 261019#L1244-3 assume 1 == ~E_8~0;~E_8~0 := 2; 261015#L1249-3 assume 1 == ~E_9~0;~E_9~0 := 2; 261013#L1254-3 assume 1 == ~E_10~0;~E_10~0 := 2; 261012#L1259-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 261001#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 260997#L851-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 260995#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 260993#L1584 assume !(0 == start_simulation_~tmp~3#1); 260990#L1584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 260695#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 260684#L851-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 260682#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 260648#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 260636#L1546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 260613#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 260596#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 260592#L1565-2 [2022-12-13 12:11:48,398 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:11:48,398 INFO L85 PathProgramCache]: Analyzing trace with hash -1601336824, now seen corresponding path program 1 times [2022-12-13 12:11:48,398 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:11:48,399 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1324596999] [2022-12-13 12:11:48,399 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:11:48,399 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:11:48,410 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:11:48,455 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:11:48,455 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:11:48,455 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1324596999] [2022-12-13 12:11:48,455 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1324596999] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:11:48,455 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:11:48,455 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-12-13 12:11:48,455 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2064827302] [2022-12-13 12:11:48,455 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:11:48,456 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 12:11:48,456 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:11:48,456 INFO L85 PathProgramCache]: Analyzing trace with hash -759740769, now seen corresponding path program 1 times [2022-12-13 12:11:48,456 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:11:48,457 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2113061405] [2022-12-13 12:11:48,457 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:11:48,457 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:11:48,471 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:11:48,501 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:11:48,501 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:11:48,501 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2113061405] [2022-12-13 12:11:48,501 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2113061405] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:11:48,501 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:11:48,501 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:11:48,502 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1004389985] [2022-12-13 12:11:48,502 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:11:48,502 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:11:48,502 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:11:48,502 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-12-13 12:11:48,503 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-12-13 12:11:48,503 INFO L87 Difference]: Start difference. First operand 59180 states and 85754 transitions. cyclomatic complexity: 26590 Second operand has 5 states, 5 states have (on average 25.6) internal successors, (128), 5 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:11:49,144 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:11:49,145 INFO L93 Difference]: Finished difference Result 155455 states and 225783 transitions. [2022-12-13 12:11:49,145 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 155455 states and 225783 transitions. [2022-12-13 12:11:49,743 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 154872 [2022-12-13 12:11:49,969 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 155455 states to 155455 states and 225783 transitions. [2022-12-13 12:11:49,969 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 155455 [2022-12-13 12:11:50,024 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 155455 [2022-12-13 12:11:50,024 INFO L73 IsDeterministic]: Start isDeterministic. Operand 155455 states and 225783 transitions. [2022-12-13 12:11:50,073 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:11:50,073 INFO L218 hiAutomatonCegarLoop]: Abstraction has 155455 states and 225783 transitions. [2022-12-13 12:11:50,132 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 155455 states and 225783 transitions. [2022-12-13 12:11:50,681 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 155455 to 61031. [2022-12-13 12:11:50,719 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 61031 states, 61031 states have (on average 1.435418066228638) internal successors, (87605), 61030 states have internal predecessors, (87605), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:11:50,798 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 61031 states to 61031 states and 87605 transitions. [2022-12-13 12:11:50,799 INFO L240 hiAutomatonCegarLoop]: Abstraction has 61031 states and 87605 transitions. [2022-12-13 12:11:50,799 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-12-13 12:11:50,799 INFO L428 stractBuchiCegarLoop]: Abstraction has 61031 states and 87605 transitions. [2022-12-13 12:11:50,800 INFO L335 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2022-12-13 12:11:50,800 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 61031 states and 87605 transitions. [2022-12-13 12:11:50,947 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 60788 [2022-12-13 12:11:50,947 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:11:50,947 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:11:50,948 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:11:50,948 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:11:50,949 INFO L748 eck$LassoCheckResult]: Stem: 452688#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 452689#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 453688#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 453689#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 453784#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 453694#L731-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 453626#L736-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 453627#L741-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 453680#L746-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 452619#L751-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 452620#L756-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 452733#L761-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 452985#L766-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 452910#L771-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 452618#L776-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 452278#L781-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 452279#L1036 assume !(0 == ~M_E~0); 452375#L1036-2 assume !(0 == ~T1_E~0); 453327#L1041-1 assume !(0 == ~T2_E~0); 453328#L1046-1 assume !(0 == ~T3_E~0); 452660#L1051-1 assume !(0 == ~T4_E~0); 452661#L1056-1 assume !(0 == ~T5_E~0); 453477#L1061-1 assume !(0 == ~T6_E~0); 452552#L1066-1 assume !(0 == ~T7_E~0); 452553#L1071-1 assume !(0 == ~T8_E~0); 453453#L1076-1 assume !(0 == ~T9_E~0); 452440#L1081-1 assume !(0 == ~T10_E~0); 452441#L1086-1 assume !(0 == ~E_M~0); 452855#L1091-1 assume !(0 == ~E_1~0); 453704#L1096-1 assume !(0 == ~E_2~0); 453705#L1101-1 assume !(0 == ~E_3~0); 452924#L1106-1 assume !(0 == ~E_4~0); 452925#L1111-1 assume !(0 == ~E_5~0); 453103#L1116-1 assume !(0 == ~E_6~0); 453104#L1121-1 assume !(0 == ~E_7~0); 452914#L1126-1 assume !(0 == ~E_8~0); 452915#L1131-1 assume !(0 == ~E_9~0); 453212#L1136-1 assume !(0 == ~E_10~0); 453335#L1141-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 453509#L514 assume !(1 == ~m_pc~0); 453510#L514-2 is_master_triggered_~__retres1~0#1 := 0; 452933#L525 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 452934#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 453588#L1285 assume !(0 != activate_threads_~tmp~1#1); 453759#L1285-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 452571#L533 assume !(1 == ~t1_pc~0); 452572#L533-2 is_transmit1_triggered_~__retres1~1#1 := 0; 453120#L544 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 452330#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 452331#L1293 assume !(0 != activate_threads_~tmp___0~0#1); 453364#L1293-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 453365#L552 assume !(1 == ~t2_pc~0); 453061#L552-2 is_transmit2_triggered_~__retres1~2#1 := 0; 453062#L563 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 452918#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 452919#L1301 assume !(0 != activate_threads_~tmp___1~0#1); 452946#L1301-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 452947#L571 assume !(1 == ~t3_pc~0); 453179#L571-2 is_transmit3_triggered_~__retres1~3#1 := 0; 453264#L582 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 452276#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 452277#L1309 assume !(0 != activate_threads_~tmp___2~0#1); 453108#L1309-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 452361#L590 assume !(1 == ~t4_pc~0); 452362#L590-2 is_transmit4_triggered_~__retres1~4#1 := 0; 453178#L601 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 453840#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 453764#L1317 assume !(0 != activate_threads_~tmp___3~0#1); 453392#L1317-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 453105#L609 assume 1 == ~t5_pc~0; 453106#L610 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 453757#L620 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 453591#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 453592#L1325 assume !(0 != activate_threads_~tmp___4~0#1); 453097#L1325-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 453098#L628 assume !(1 == ~t6_pc~0); 453021#L628-2 is_transmit6_triggered_~__retres1~6#1 := 0; 453020#L639 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 452890#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 452891#L1333 assume !(0 != activate_threads_~tmp___5~0#1); 453431#L1333-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 453432#L647 assume 1 == ~t7_pc~0; 452926#L648 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 452927#L658 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 453603#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 452929#L1341 assume !(0 != activate_threads_~tmp___6~0#1); 452930#L1341-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 453813#L666 assume !(1 == ~t8_pc~0); 452713#L666-2 is_transmit8_triggered_~__retres1~8#1 := 0; 452714#L677 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 452945#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 453132#L1349 assume !(0 != activate_threads_~tmp___7~0#1); 452850#L1349-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 452851#L685 assume 1 == ~t9_pc~0; 453769#L686 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 453615#L696 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 452978#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 452880#L1357 assume !(0 != activate_threads_~tmp___8~0#1); 452881#L1357-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 453295#L704 assume !(1 == ~t10_pc~0); 452873#L704-2 is_transmit10_triggered_~__retres1~10#1 := 0; 452872#L715 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 453147#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 452410#L1365 assume !(0 != activate_threads_~tmp___9~0#1); 452411#L1365-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 452670#L1154 assume 1 == ~M_E~0;~M_E~0 := 2; 453416#L1154-2 assume !(1 == ~T1_E~0); 465922#L1159-1 assume !(1 == ~T2_E~0); 453847#L1164-1 assume !(1 == ~T3_E~0); 453130#L1169-1 assume !(1 == ~T4_E~0); 452979#L1174-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 452776#L1179-1 assume !(1 == ~T6_E~0); 452626#L1184-1 assume !(1 == ~T7_E~0); 452627#L1189-1 assume !(1 == ~T8_E~0); 452711#L1194-1 assume !(1 == ~T9_E~0); 452836#L1199-1 assume !(1 == ~T10_E~0); 452789#L1204-1 assume !(1 == ~E_M~0); 452790#L1209-1 assume !(1 == ~E_1~0); 453386#L1214-1 assume 1 == ~E_2~0;~E_2~0 := 2; 453387#L1219-1 assume !(1 == ~E_3~0); 453797#L1224-1 assume !(1 == ~E_4~0); 453152#L1229-1 assume !(1 == ~E_5~0); 452506#L1234-1 assume !(1 == ~E_6~0); 452507#L1239-1 assume !(1 == ~E_7~0); 452567#L1244-1 assume !(1 == ~E_8~0); 452568#L1249-1 assume !(1 == ~E_9~0); 479860#L1254-1 assume 1 == ~E_10~0;~E_10~0 := 2; 479849#L1259-1 assume { :end_inline_reset_delta_events } true; 479842#L1565-2 [2022-12-13 12:11:50,949 INFO L750 eck$LassoCheckResult]: Loop: 479842#L1565-2 assume !false; 479836#L1566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 479831#L1011 assume !false; 479829#L862 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 479827#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 479533#L851 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 479514#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 479507#L866 assume !(0 != eval_~tmp~0#1); 479508#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 482913#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 482910#L1036-3 assume 0 == ~M_E~0;~M_E~0 := 1; 482906#L1036-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 482902#L1041-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 482899#L1046-3 assume !(0 == ~T3_E~0); 482896#L1051-3 assume !(0 == ~T4_E~0); 482893#L1056-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 482888#L1061-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 482886#L1066-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 482883#L1071-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 482881#L1076-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 482847#L1081-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 482844#L1086-3 assume !(0 == ~E_M~0); 482841#L1091-3 assume !(0 == ~E_1~0); 482837#L1096-3 assume 0 == ~E_2~0;~E_2~0 := 1; 482834#L1101-3 assume 0 == ~E_3~0;~E_3~0 := 1; 482831#L1106-3 assume 0 == ~E_4~0;~E_4~0 := 1; 482829#L1111-3 assume 0 == ~E_5~0;~E_5~0 := 1; 482792#L1116-3 assume 0 == ~E_6~0;~E_6~0 := 1; 482789#L1121-3 assume 0 == ~E_7~0;~E_7~0 := 1; 482786#L1126-3 assume !(0 == ~E_8~0); 482782#L1131-3 assume !(0 == ~E_9~0); 482765#L1136-3 assume 0 == ~E_10~0;~E_10~0 := 1; 482759#L1141-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 482757#L514-36 assume !(1 == ~m_pc~0); 482754#L514-38 is_master_triggered_~__retres1~0#1 := 0; 482750#L525-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 482747#is_master_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 482744#L1285-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 482741#L1285-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 482738#L533-36 assume !(1 == ~t1_pc~0); 482735#L533-38 is_transmit1_triggered_~__retres1~1#1 := 0; 482731#L544-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 482728#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 482725#L1293-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 482722#L1293-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 453863#L552-36 assume !(1 == ~t2_pc~0); 453864#L552-38 is_transmit2_triggered_~__retres1~2#1 := 0; 482600#L563-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 453569#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 453570#L1301-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 452684#L1301-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 452685#L571-36 assume !(1 == ~t3_pc~0); 454520#L571-38 is_transmit3_triggered_~__retres1~3#1 := 0; 454519#L582-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 454518#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 454517#L1309-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 454515#L1309-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 454516#L590-36 assume !(1 == ~t4_pc~0); 454513#L590-38 is_transmit4_triggered_~__retres1~4#1 := 0; 454510#L601-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 454507#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 454508#L1317-36 assume !(0 != activate_threads_~tmp___3~0#1); 481495#L1317-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 481493#L609-36 assume !(1 == ~t5_pc~0); 481491#L609-38 is_transmit5_triggered_~__retres1~5#1 := 0; 481488#L620-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 481487#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 481486#L1325-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 481203#L1325-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 481201#L628-36 assume 1 == ~t6_pc~0; 481199#L629-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 481195#L639-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 481193#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 481191#L1333-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 481189#L1333-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 481187#L647-36 assume !(1 == ~t7_pc~0); 481185#L647-38 is_transmit7_triggered_~__retres1~7#1 := 0; 481181#L658-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 481179#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 481177#L1341-36 assume !(0 != activate_threads_~tmp___6~0#1); 481175#L1341-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 481173#L666-36 assume !(1 == ~t8_pc~0); 481171#L666-38 is_transmit8_triggered_~__retres1~8#1 := 0; 481167#L677-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 481165#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 481163#L1349-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 481161#L1349-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 481159#L685-36 assume 1 == ~t9_pc~0; 481157#L686-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 481153#L696-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 481151#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 481149#L1357-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 481147#L1357-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 481111#L704-36 assume !(1 == ~t10_pc~0); 481105#L704-38 is_transmit10_triggered_~__retres1~10#1 := 0; 481016#L715-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 480983#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 480981#L1365-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 480979#L1365-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 480967#L1154-3 assume 1 == ~M_E~0;~M_E~0 := 2; 454338#L1154-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 480964#L1159-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 480963#L1164-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 473194#L1169-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 480915#L1174-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 480913#L1179-3 assume !(1 == ~T6_E~0); 480911#L1184-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 480909#L1189-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 480907#L1194-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 480905#L1199-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 480903#L1204-3 assume 1 == ~E_M~0;~E_M~0 := 2; 454311#L1209-3 assume 1 == ~E_1~0;~E_1~0 := 2; 480900#L1214-3 assume 1 == ~E_2~0;~E_2~0 := 2; 480860#L1219-3 assume !(1 == ~E_3~0); 480858#L1224-3 assume 1 == ~E_4~0;~E_4~0 := 2; 480856#L1229-3 assume 1 == ~E_5~0;~E_5~0 := 2; 480853#L1234-3 assume 1 == ~E_6~0;~E_6~0 := 2; 480851#L1239-3 assume 1 == ~E_7~0;~E_7~0 := 2; 480849#L1244-3 assume 1 == ~E_8~0;~E_8~0 := 2; 478983#L1249-3 assume 1 == ~E_9~0;~E_9~0 := 2; 480846#L1254-3 assume 1 == ~E_10~0;~E_10~0 := 2; 480844#L1259-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 480819#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 480814#L851-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 480811#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 480808#L1584 assume !(0 == start_simulation_~tmp~3#1); 480086#L1584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 479913#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 479894#L851-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 479889#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 479873#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 479872#L1546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 479861#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 479850#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 479842#L1565-2 [2022-12-13 12:11:50,949 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:11:50,949 INFO L85 PathProgramCache]: Analyzing trace with hash 360237834, now seen corresponding path program 1 times [2022-12-13 12:11:50,949 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:11:50,949 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [333611547] [2022-12-13 12:11:50,950 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:11:50,950 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:11:50,960 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:11:50,998 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:11:50,998 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:11:50,998 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [333611547] [2022-12-13 12:11:50,998 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [333611547] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:11:50,998 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:11:50,998 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-12-13 12:11:50,998 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [740139399] [2022-12-13 12:11:50,998 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:11:50,998 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 12:11:50,998 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:11:50,999 INFO L85 PathProgramCache]: Analyzing trace with hash 643981538, now seen corresponding path program 1 times [2022-12-13 12:11:50,999 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:11:50,999 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1688711107] [2022-12-13 12:11:50,999 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:11:50,999 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:11:51,007 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:11:51,027 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:11:51,027 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:11:51,027 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1688711107] [2022-12-13 12:11:51,027 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1688711107] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:11:51,027 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:11:51,027 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:11:51,027 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [718203603] [2022-12-13 12:11:51,027 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:11:51,028 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:11:51,028 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:11:51,028 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 12:11:51,028 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 12:11:51,028 INFO L87 Difference]: Start difference. First operand 61031 states and 87605 transitions. cyclomatic complexity: 26590 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 2 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:11:51,489 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:11:51,490 INFO L93 Difference]: Finished difference Result 116082 states and 166006 transitions. [2022-12-13 12:11:51,490 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 116082 states and 166006 transitions. [2022-12-13 12:11:51,928 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 115680 [2022-12-13 12:11:52,198 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 116082 states to 116082 states and 166006 transitions. [2022-12-13 12:11:52,198 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 116082 [2022-12-13 12:11:52,381 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 116082 [2022-12-13 12:11:52,382 INFO L73 IsDeterministic]: Start isDeterministic. Operand 116082 states and 166006 transitions. [2022-12-13 12:11:52,408 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:11:52,408 INFO L218 hiAutomatonCegarLoop]: Abstraction has 116082 states and 166006 transitions. [2022-12-13 12:11:52,457 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 116082 states and 166006 transitions. [2022-12-13 12:11:53,084 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 116082 to 115954. [2022-12-13 12:11:53,155 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 115954 states, 115954 states have (on average 1.4305500457077807) internal successors, (165878), 115953 states have internal predecessors, (165878), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:11:53,318 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 115954 states to 115954 states and 165878 transitions. [2022-12-13 12:11:53,318 INFO L240 hiAutomatonCegarLoop]: Abstraction has 115954 states and 165878 transitions. [2022-12-13 12:11:53,318 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 12:11:53,319 INFO L428 stractBuchiCegarLoop]: Abstraction has 115954 states and 165878 transitions. [2022-12-13 12:11:53,319 INFO L335 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2022-12-13 12:11:53,319 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 115954 states and 165878 transitions. [2022-12-13 12:11:53,644 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 115552 [2022-12-13 12:11:53,644 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:11:53,644 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:11:53,646 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:11:53,646 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:11:53,647 INFO L748 eck$LassoCheckResult]: Stem: 629806#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 629807#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 630809#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 630810#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 630908#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 630813#L731-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 630748#L736-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 630749#L741-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 630801#L746-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 629739#L751-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 629740#L756-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 629848#L761-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 630102#L766-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 630027#L771-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 629741#L776-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 629398#L781-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 629399#L1036 assume !(0 == ~M_E~0); 629494#L1036-2 assume !(0 == ~T1_E~0); 630446#L1041-1 assume !(0 == ~T2_E~0); 630447#L1046-1 assume !(0 == ~T3_E~0); 629783#L1051-1 assume !(0 == ~T4_E~0); 629784#L1056-1 assume !(0 == ~T5_E~0); 630606#L1061-1 assume !(0 == ~T6_E~0); 629670#L1066-1 assume !(0 == ~T7_E~0); 629671#L1071-1 assume !(0 == ~T8_E~0); 630586#L1076-1 assume !(0 == ~T9_E~0); 629558#L1081-1 assume !(0 == ~T10_E~0); 629559#L1086-1 assume !(0 == ~E_M~0); 629973#L1091-1 assume !(0 == ~E_1~0); 630824#L1096-1 assume !(0 == ~E_2~0); 630825#L1101-1 assume !(0 == ~E_3~0); 630041#L1106-1 assume !(0 == ~E_4~0); 630042#L1111-1 assume !(0 == ~E_5~0); 630222#L1116-1 assume !(0 == ~E_6~0); 630223#L1121-1 assume !(0 == ~E_7~0); 630031#L1126-1 assume !(0 == ~E_8~0); 630032#L1131-1 assume !(0 == ~E_9~0); 630329#L1136-1 assume !(0 == ~E_10~0); 630458#L1141-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 630639#L514 assume !(1 == ~m_pc~0); 630640#L514-2 is_master_triggered_~__retres1~0#1 := 0; 630050#L525 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 630051#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 630712#L1285 assume !(0 != activate_threads_~tmp~1#1); 630876#L1285-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 629692#L533 assume !(1 == ~t1_pc~0); 629693#L533-2 is_transmit1_triggered_~__retres1~1#1 := 0; 630237#L544 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 629452#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 629453#L1293 assume !(0 != activate_threads_~tmp___0~0#1); 630484#L1293-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 630485#L552 assume !(1 == ~t2_pc~0); 630182#L552-2 is_transmit2_triggered_~__retres1~2#1 := 0; 630183#L563 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 630035#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 630036#L1301 assume !(0 != activate_threads_~tmp___1~0#1); 630069#L1301-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 630070#L571 assume !(1 == ~t3_pc~0); 630295#L571-2 is_transmit3_triggered_~__retres1~3#1 := 0; 630382#L582 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 629396#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 629397#L1309 assume !(0 != activate_threads_~tmp___2~0#1); 630226#L1309-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 629480#L590 assume !(1 == ~t4_pc~0); 629481#L590-2 is_transmit4_triggered_~__retres1~4#1 := 0; 630292#L601 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 631011#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 630880#L1317 assume !(0 != activate_threads_~tmp___3~0#1); 630519#L1317-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 630224#L609 assume !(1 == ~t5_pc~0); 630225#L609-2 is_transmit5_triggered_~__retres1~5#1 := 0; 630871#L620 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 630713#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 630714#L1325 assume !(0 != activate_threads_~tmp___4~0#1); 630217#L1325-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 630218#L628 assume !(1 == ~t6_pc~0); 630137#L628-2 is_transmit6_triggered_~__retres1~6#1 := 0; 630136#L639 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 630011#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 630012#L1333 assume !(0 != activate_threads_~tmp___5~0#1); 630560#L1333-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 630561#L647 assume 1 == ~t7_pc~0; 630043#L648 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 630044#L658 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 630723#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 630048#L1341 assume !(0 != activate_threads_~tmp___6~0#1); 630049#L1341-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 630940#L666 assume !(1 == ~t8_pc~0); 629829#L666-2 is_transmit8_triggered_~__retres1~8#1 := 0; 629830#L677 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 630063#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 630249#L1349 assume !(0 != activate_threads_~tmp___7~0#1); 629970#L1349-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 629971#L685 assume 1 == ~t9_pc~0; 630889#L686 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 630736#L696 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 630096#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 629996#L1357 assume !(0 != activate_threads_~tmp___8~0#1); 629997#L1357-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 630417#L704 assume !(1 == ~t10_pc~0); 629989#L704-2 is_transmit10_triggered_~__retres1~10#1 := 0; 629988#L715 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 630267#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 629528#L1365 assume !(0 != activate_threads_~tmp___9~0#1); 629529#L1365-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 629790#L1154 assume 1 == ~M_E~0;~M_E~0 := 2; 630546#L1154-2 assume !(1 == ~T1_E~0); 629759#L1159-1 assume !(1 == ~T2_E~0); 629760#L1164-1 assume !(1 == ~T3_E~0); 630979#L1169-1 assume !(1 == ~T4_E~0); 633453#L1174-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 633451#L1179-1 assume !(1 == ~T6_E~0); 633449#L1184-1 assume !(1 == ~T7_E~0); 633447#L1189-1 assume !(1 == ~T8_E~0); 633446#L1194-1 assume !(1 == ~T9_E~0); 633445#L1199-1 assume !(1 == ~T10_E~0); 633444#L1204-1 assume !(1 == ~E_M~0); 633443#L1209-1 assume !(1 == ~E_1~0); 633442#L1214-1 assume 1 == ~E_2~0;~E_2~0 := 2; 633441#L1219-1 assume !(1 == ~E_3~0); 633439#L1224-1 assume !(1 == ~E_4~0); 633437#L1229-1 assume !(1 == ~E_5~0); 633435#L1234-1 assume !(1 == ~E_6~0); 633433#L1239-1 assume !(1 == ~E_7~0); 633431#L1244-1 assume !(1 == ~E_8~0); 633427#L1249-1 assume !(1 == ~E_9~0); 633425#L1254-1 assume 1 == ~E_10~0;~E_10~0 := 2; 633357#L1259-1 assume { :end_inline_reset_delta_events } true; 633355#L1565-2 [2022-12-13 12:11:53,775 INFO L750 eck$LassoCheckResult]: Loop: 633355#L1565-2 assume !false; 633352#L1566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 633346#L1011 assume !false; 633344#L862 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 632749#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 632737#L851 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 632734#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 632731#L866 assume !(0 != eval_~tmp~0#1); 632732#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 656336#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 656332#L1036-3 assume 0 == ~M_E~0;~M_E~0 := 1; 656329#L1036-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 656326#L1041-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 656324#L1046-3 assume !(0 == ~T3_E~0); 656320#L1051-3 assume !(0 == ~T4_E~0); 656316#L1056-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 656313#L1061-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 656309#L1066-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 656305#L1071-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 656301#L1076-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 656295#L1081-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 656290#L1086-3 assume !(0 == ~E_M~0); 656286#L1091-3 assume !(0 == ~E_1~0); 656282#L1096-3 assume 0 == ~E_2~0;~E_2~0 := 1; 656279#L1101-3 assume 0 == ~E_3~0;~E_3~0 := 1; 656276#L1106-3 assume 0 == ~E_4~0;~E_4~0 := 1; 656272#L1111-3 assume 0 == ~E_5~0;~E_5~0 := 1; 656267#L1116-3 assume 0 == ~E_6~0;~E_6~0 := 1; 656262#L1121-3 assume 0 == ~E_7~0;~E_7~0 := 1; 656256#L1126-3 assume !(0 == ~E_8~0); 656252#L1131-3 assume !(0 == ~E_9~0); 656248#L1136-3 assume 0 == ~E_10~0;~E_10~0 := 1; 656244#L1141-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 656240#L514-36 assume !(1 == ~m_pc~0); 656235#L514-38 is_master_triggered_~__retres1~0#1 := 0; 656230#L525-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 656226#is_master_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 656222#L1285-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 656218#L1285-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 656215#L533-36 assume 1 == ~t1_pc~0; 656211#L534-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 656207#L544-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 656204#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 656200#L1293-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 654610#L1293-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 636366#L552-36 assume !(1 == ~t2_pc~0); 636364#L552-38 is_transmit2_triggered_~__retres1~2#1 := 0; 636360#L563-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 636357#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 636354#L1301-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 636212#L1301-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 634903#L571-36 assume !(1 == ~t3_pc~0); 634901#L571-38 is_transmit3_triggered_~__retres1~3#1 := 0; 634899#L582-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 634897#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 634895#L1309-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 634893#L1309-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 634888#L590-36 assume 1 == ~t4_pc~0; 634889#L591-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 634890#L601-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 635654#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 634878#L1317-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 634876#L1317-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 634874#L609-36 assume !(1 == ~t5_pc~0); 634872#L609-38 is_transmit5_triggered_~__retres1~5#1 := 0; 634869#L620-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 634867#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 634865#L1325-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 634863#L1325-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 634861#L628-36 assume 1 == ~t6_pc~0; 634859#L629-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 634855#L639-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 634853#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 634852#L1333-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 634851#L1333-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 634850#L647-36 assume !(1 == ~t7_pc~0); 634849#L647-38 is_transmit7_triggered_~__retres1~7#1 := 0; 634847#L658-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 634846#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 634845#L1341-36 assume !(0 != activate_threads_~tmp___6~0#1); 634844#L1341-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 634843#L666-36 assume 1 == ~t8_pc~0; 634841#L667-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 634840#L677-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 634839#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 634837#L1349-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 634836#L1349-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 634835#L685-36 assume 1 == ~t9_pc~0; 634833#L686-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 634820#L696-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 634818#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 634816#L1357-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 634813#L1357-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 634811#L704-36 assume !(1 == ~t10_pc~0); 634809#L704-38 is_transmit10_triggered_~__retres1~10#1 := 0; 634806#L715-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 634804#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 634802#L1365-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 634800#L1365-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 634798#L1154-3 assume 1 == ~M_E~0;~M_E~0 := 2; 634794#L1154-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 634792#L1159-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 634790#L1164-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 634786#L1169-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 634784#L1174-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 634782#L1179-3 assume !(1 == ~T6_E~0); 634780#L1184-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 634778#L1189-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 634776#L1194-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 634774#L1199-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 634772#L1204-3 assume 1 == ~E_M~0;~E_M~0 := 2; 634768#L1209-3 assume 1 == ~E_1~0;~E_1~0 := 2; 634766#L1214-3 assume 1 == ~E_2~0;~E_2~0 := 2; 634764#L1219-3 assume !(1 == ~E_3~0); 634762#L1224-3 assume 1 == ~E_4~0;~E_4~0 := 2; 634760#L1229-3 assume 1 == ~E_5~0;~E_5~0 := 2; 634758#L1234-3 assume 1 == ~E_6~0;~E_6~0 := 2; 634756#L1239-3 assume 1 == ~E_7~0;~E_7~0 := 2; 634754#L1244-3 assume 1 == ~E_8~0;~E_8~0 := 2; 634750#L1249-3 assume 1 == ~E_9~0;~E_9~0 := 2; 634748#L1254-3 assume 1 == ~E_10~0;~E_10~0 := 2; 634746#L1259-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 634722#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 633892#L851-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 633889#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 633887#L1584 assume !(0 == start_simulation_~tmp~3#1); 633884#L1584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 633379#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 633368#L851-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 633366#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 633364#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 633362#L1546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 633360#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 633358#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 633355#L1565-2 [2022-12-13 12:11:53,775 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:11:53,775 INFO L85 PathProgramCache]: Analyzing trace with hash -671092981, now seen corresponding path program 1 times [2022-12-13 12:11:53,775 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:11:53,776 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [292410205] [2022-12-13 12:11:53,776 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:11:53,776 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:11:53,787 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:11:53,844 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:11:53,845 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:11:53,845 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [292410205] [2022-12-13 12:11:53,845 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [292410205] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:11:53,845 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:11:53,845 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:11:53,845 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [885639195] [2022-12-13 12:11:53,845 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:11:53,846 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 12:11:53,846 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:11:53,846 INFO L85 PathProgramCache]: Analyzing trace with hash 503225565, now seen corresponding path program 1 times [2022-12-13 12:11:53,846 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:11:53,847 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [861823183] [2022-12-13 12:11:53,847 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:11:53,847 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:11:53,857 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:11:53,876 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:11:53,876 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:11:53,876 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [861823183] [2022-12-13 12:11:53,876 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [861823183] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:11:53,876 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:11:53,877 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:11:53,877 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1370502712] [2022-12-13 12:11:53,877 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:11:53,877 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:11:53,877 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:11:53,877 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 12:11:53,877 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 12:11:53,878 INFO L87 Difference]: Start difference. First operand 115954 states and 165878 transitions. cyclomatic complexity: 49956 Second operand has 4 states, 4 states have (on average 32.0) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:11:54,932 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:11:54,932 INFO L93 Difference]: Finished difference Result 283541 states and 402559 transitions. [2022-12-13 12:11:54,932 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 283541 states and 402559 transitions. [2022-12-13 12:11:55,931 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 277476 [2022-12-13 12:11:56,396 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 283541 states to 283541 states and 402559 transitions. [2022-12-13 12:11:56,396 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 283541 [2022-12-13 12:11:56,509 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 283541 [2022-12-13 12:11:56,509 INFO L73 IsDeterministic]: Start isDeterministic. Operand 283541 states and 402559 transitions. [2022-12-13 12:11:56,722 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:11:56,722 INFO L218 hiAutomatonCegarLoop]: Abstraction has 283541 states and 402559 transitions. [2022-12-13 12:11:56,813 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 283541 states and 402559 transitions. [2022-12-13 12:11:58,185 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 283541 to 225089. [2022-12-13 12:11:58,321 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 225089 states, 225089 states have (on average 1.4243743585870479) internal successors, (320611), 225088 states have internal predecessors, (320611), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:11:58,917 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 225089 states to 225089 states and 320611 transitions. [2022-12-13 12:11:58,917 INFO L240 hiAutomatonCegarLoop]: Abstraction has 225089 states and 320611 transitions. [2022-12-13 12:11:58,918 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 12:11:58,918 INFO L428 stractBuchiCegarLoop]: Abstraction has 225089 states and 320611 transitions. [2022-12-13 12:11:58,918 INFO L335 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2022-12-13 12:11:58,918 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 225089 states and 320611 transitions. [2022-12-13 12:11:59,482 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 224496 [2022-12-13 12:11:59,482 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:11:59,483 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:11:59,485 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:11:59,485 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:11:59,485 INFO L748 eck$LassoCheckResult]: Stem: 1029309#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 1029310#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 1030330#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1030331#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1030435#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 1030334#L731-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1030267#L736-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1030268#L741-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1030319#L746-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1029238#L751-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1029239#L756-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1029354#L761-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1029607#L766-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1029528#L771-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1029240#L776-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 1028903#L781-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1028904#L1036 assume !(0 == ~M_E~0); 1028998#L1036-2 assume !(0 == ~T1_E~0); 1029951#L1041-1 assume !(0 == ~T2_E~0); 1029952#L1046-1 assume !(0 == ~T3_E~0); 1029282#L1051-1 assume !(0 == ~T4_E~0); 1029283#L1056-1 assume !(0 == ~T5_E~0); 1030111#L1061-1 assume !(0 == ~T6_E~0); 1029172#L1066-1 assume !(0 == ~T7_E~0); 1029173#L1071-1 assume !(0 == ~T8_E~0); 1030092#L1076-1 assume !(0 == ~T9_E~0); 1029061#L1081-1 assume !(0 == ~T10_E~0); 1029062#L1086-1 assume !(0 == ~E_M~0); 1029473#L1091-1 assume !(0 == ~E_1~0); 1030344#L1096-1 assume !(0 == ~E_2~0); 1030345#L1101-1 assume !(0 == ~E_3~0); 1029542#L1106-1 assume !(0 == ~E_4~0); 1029543#L1111-1 assume !(0 == ~E_5~0); 1029726#L1116-1 assume !(0 == ~E_6~0); 1029727#L1121-1 assume !(0 == ~E_7~0); 1029532#L1126-1 assume !(0 == ~E_8~0); 1029533#L1131-1 assume !(0 == ~E_9~0); 1029834#L1136-1 assume !(0 == ~E_10~0); 1029957#L1141-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1030145#L514 assume !(1 == ~m_pc~0); 1030146#L514-2 is_master_triggered_~__retres1~0#1 := 0; 1029548#L525 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1029549#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1030224#L1285 assume !(0 != activate_threads_~tmp~1#1); 1030406#L1285-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1029191#L533 assume !(1 == ~t1_pc~0); 1029192#L533-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1029740#L544 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1028955#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1028956#L1293 assume !(0 != activate_threads_~tmp___0~0#1); 1029988#L1293-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1029989#L552 assume !(1 == ~t2_pc~0); 1029685#L552-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1029686#L563 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1029536#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1029537#L1301 assume !(0 != activate_threads_~tmp___1~0#1); 1029563#L1301-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1029564#L571 assume !(1 == ~t3_pc~0); 1029804#L571-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1029888#L582 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1028901#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1028902#L1309 assume !(0 != activate_threads_~tmp___2~0#1); 1029730#L1309-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1028984#L590 assume !(1 == ~t4_pc~0); 1028985#L590-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1029803#L601 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1030559#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1030412#L1317 assume !(0 != activate_threads_~tmp___3~0#1); 1030018#L1317-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1029728#L609 assume !(1 == ~t5_pc~0); 1029729#L609-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1030404#L620 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1030226#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1030227#L1325 assume !(0 != activate_threads_~tmp___4~0#1); 1029719#L1325-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1029720#L628 assume !(1 == ~t6_pc~0); 1029642#L628-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1029641#L639 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1029509#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1029510#L1333 assume !(0 != activate_threads_~tmp___5~0#1); 1030067#L1333-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1030068#L647 assume !(1 == ~t7_pc~0); 1030207#L647-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1030238#L658 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1030239#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1029544#L1341 assume !(0 != activate_threads_~tmp___6~0#1); 1029545#L1341-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1030463#L666 assume !(1 == ~t8_pc~0); 1029334#L666-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1029335#L677 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1029562#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1029752#L1349 assume !(0 != activate_threads_~tmp___7~0#1); 1029470#L1349-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1029471#L685 assume 1 == ~t9_pc~0; 1030418#L686 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 1030251#L696 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1029599#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1029498#L1357 assume !(0 != activate_threads_~tmp___8~0#1); 1029499#L1357-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1029919#L704 assume !(1 == ~t10_pc~0); 1029492#L704-2 is_transmit10_triggered_~__retres1~10#1 := 0; 1029491#L715 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1029770#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1029032#L1365 assume !(0 != activate_threads_~tmp___9~0#1); 1029033#L1365-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1029291#L1154 assume 1 == ~M_E~0;~M_E~0 := 2; 1030052#L1154-2 assume !(1 == ~T1_E~0); 1090395#L1159-1 assume !(1 == ~T2_E~0); 1030520#L1164-1 assume !(1 == ~T3_E~0); 1030521#L1169-1 assume !(1 == ~T4_E~0); 1029600#L1174-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1029601#L1179-1 assume !(1 == ~T6_E~0); 1029246#L1184-1 assume !(1 == ~T7_E~0); 1029247#L1189-1 assume !(1 == ~T8_E~0); 1029454#L1194-1 assume !(1 == ~T9_E~0); 1029455#L1199-1 assume !(1 == ~T10_E~0); 1029407#L1204-1 assume !(1 == ~E_M~0); 1029408#L1209-1 assume !(1 == ~E_1~0); 1095501#L1214-1 assume 1 == ~E_2~0;~E_2~0 := 2; 1095500#L1219-1 assume !(1 == ~E_3~0); 1030445#L1224-1 assume !(1 == ~E_4~0); 1030446#L1229-1 assume !(1 == ~E_5~0); 1029128#L1234-1 assume !(1 == ~E_6~0); 1029129#L1239-1 assume !(1 == ~E_7~0); 1029187#L1244-1 assume !(1 == ~E_8~0); 1029188#L1249-1 assume !(1 == ~E_9~0); 1030102#L1254-1 assume 1 == ~E_10~0;~E_10~0 := 2; 1029027#L1259-1 assume { :end_inline_reset_delta_events } true; 1029028#L1565-2 [2022-12-13 12:11:59,486 INFO L750 eck$LassoCheckResult]: Loop: 1029028#L1565-2 assume !false; 1133709#L1566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1133703#L1011 assume !false; 1131148#L862 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 1130422#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 1130410#L851 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 1130409#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1130404#L866 assume !(0 != eval_~tmp~0#1); 1130405#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1137182#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1137115#L1036-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1137096#L1036-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1137091#L1041-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1137086#L1046-3 assume !(0 == ~T3_E~0); 1137081#L1051-3 assume !(0 == ~T4_E~0); 1137032#L1056-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1136981#L1061-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1136979#L1066-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1136977#L1071-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1136975#L1076-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 1136973#L1081-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 1136971#L1086-3 assume !(0 == ~E_M~0); 1136967#L1091-3 assume !(0 == ~E_1~0); 1136964#L1096-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1136960#L1101-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1136956#L1106-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1136699#L1111-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1136692#L1116-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1136686#L1121-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1136587#L1126-3 assume !(0 == ~E_8~0); 1136427#L1131-3 assume !(0 == ~E_9~0); 1136425#L1136-3 assume 0 == ~E_10~0;~E_10~0 := 1; 1136419#L1141-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1136412#L514-36 assume !(1 == ~m_pc~0); 1136405#L514-38 is_master_triggered_~__retres1~0#1 := 0; 1136398#L525-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1136390#is_master_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1136383#L1285-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1136373#L1285-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1136361#L533-36 assume 1 == ~t1_pc~0; 1136351#L534-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1136343#L544-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1136335#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1136326#L1293-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1135803#L1293-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1135701#L552-36 assume !(1 == ~t2_pc~0); 1135695#L552-38 is_transmit2_triggered_~__retres1~2#1 := 0; 1135690#L563-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1135685#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1135680#L1301-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1135675#L1301-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1135671#L571-36 assume !(1 == ~t3_pc~0); 1087488#L571-38 is_transmit3_triggered_~__retres1~3#1 := 0; 1135662#L582-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1135658#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1135654#L1309-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1135650#L1309-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1135647#L590-36 assume !(1 == ~t4_pc~0); 1135643#L590-38 is_transmit4_triggered_~__retres1~4#1 := 0; 1135638#L601-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1135633#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1135628#L1317-36 assume !(0 != activate_threads_~tmp___3~0#1); 1135624#L1317-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1135620#L609-36 assume !(1 == ~t5_pc~0); 1135615#L609-38 is_transmit5_triggered_~__retres1~5#1 := 0; 1135611#L620-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1135607#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1135603#L1325-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1135599#L1325-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1135595#L628-36 assume !(1 == ~t6_pc~0); 1135587#L628-38 is_transmit6_triggered_~__retres1~6#1 := 0; 1135583#L639-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1135579#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1135575#L1333-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1135571#L1333-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1135566#L647-36 assume !(1 == ~t7_pc~0); 1077399#L647-38 is_transmit7_triggered_~__retres1~7#1 := 0; 1135560#L658-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1135556#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1135552#L1341-36 assume !(0 != activate_threads_~tmp___6~0#1); 1135548#L1341-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1135545#L666-36 assume 1 == ~t8_pc~0; 1135541#L667-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 1135537#L677-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1135533#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1135529#L1349-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1135525#L1349-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1135521#L685-36 assume 1 == ~t9_pc~0; 1135515#L686-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 1135509#L696-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1135503#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1135498#L1357-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1135494#L1357-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1135490#L704-36 assume !(1 == ~t10_pc~0); 1135485#L704-38 is_transmit10_triggered_~__retres1~10#1 := 0; 1135481#L715-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1134169#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1134166#L1365-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1134164#L1365-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1134162#L1154-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1091777#L1154-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1134158#L1159-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1134156#L1164-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1111777#L1169-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1134153#L1174-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1134151#L1179-3 assume !(1 == ~T6_E~0); 1134148#L1184-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1134146#L1189-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1134144#L1194-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1134142#L1199-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 1134140#L1204-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1121778#L1209-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1134138#L1214-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1134136#L1219-3 assume !(1 == ~E_3~0); 1134134#L1224-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1134132#L1229-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1134130#L1234-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1134128#L1239-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1134125#L1244-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1094051#L1249-3 assume 1 == ~E_9~0;~E_9~0 := 2; 1134122#L1254-3 assume 1 == ~E_10~0;~E_10~0 := 2; 1134120#L1259-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 1133750#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 1133746#L851-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 1133744#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 1133743#L1584 assume !(0 == start_simulation_~tmp~3#1); 1133741#L1584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 1133734#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 1133723#L851-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 1133721#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 1133719#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1133716#L1546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1133714#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 1133712#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 1029028#L1565-2 [2022-12-13 12:11:59,486 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:11:59,486 INFO L85 PathProgramCache]: Analyzing trace with hash 1730432140, now seen corresponding path program 1 times [2022-12-13 12:11:59,487 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:11:59,487 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2029526057] [2022-12-13 12:11:59,487 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:11:59,487 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:11:59,502 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:11:59,547 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:11:59,547 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:11:59,547 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2029526057] [2022-12-13 12:11:59,548 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2029526057] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:11:59,548 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:11:59,548 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:11:59,548 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [952786360] [2022-12-13 12:11:59,548 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:11:59,548 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 12:11:59,549 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:11:59,549 INFO L85 PathProgramCache]: Analyzing trace with hash 1422479329, now seen corresponding path program 1 times [2022-12-13 12:11:59,549 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:11:59,549 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [899262774] [2022-12-13 12:11:59,549 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:11:59,549 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:11:59,558 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:11:59,744 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:11:59,744 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:11:59,744 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [899262774] [2022-12-13 12:11:59,744 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [899262774] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:11:59,744 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:11:59,744 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:11:59,744 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [127821873] [2022-12-13 12:11:59,744 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:11:59,745 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:11:59,745 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:11:59,745 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 12:11:59,745 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 12:11:59,745 INFO L87 Difference]: Start difference. First operand 225089 states and 320611 transitions. cyclomatic complexity: 95554 Second operand has 4 states, 4 states have (on average 32.0) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:12:01,350 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:12:01,350 INFO L93 Difference]: Finished difference Result 535616 states and 758208 transitions. [2022-12-13 12:12:01,350 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 535616 states and 758208 transitions. [2022-12-13 12:12:03,366 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 523760 [2022-12-13 12:12:04,406 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 535616 states to 535616 states and 758208 transitions. [2022-12-13 12:12:04,406 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 535616 [2022-12-13 12:12:04,606 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 535616 [2022-12-13 12:12:04,606 INFO L73 IsDeterministic]: Start isDeterministic. Operand 535616 states and 758208 transitions. [2022-12-13 12:12:04,900 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:12:04,900 INFO L218 hiAutomatonCegarLoop]: Abstraction has 535616 states and 758208 transitions. [2022-12-13 12:12:05,122 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 535616 states and 758208 transitions. [2022-12-13 12:12:08,300 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 535616 to 426832. [2022-12-13 12:12:08,483 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 426832 states, 426832 states have (on average 1.4204370806312554) internal successors, (606288), 426831 states have internal predecessors, (606288), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:12:09,552 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 426832 states to 426832 states and 606288 transitions. [2022-12-13 12:12:09,553 INFO L240 hiAutomatonCegarLoop]: Abstraction has 426832 states and 606288 transitions. [2022-12-13 12:12:09,553 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 12:12:09,554 INFO L428 stractBuchiCegarLoop]: Abstraction has 426832 states and 606288 transitions. [2022-12-13 12:12:09,554 INFO L335 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2022-12-13 12:12:09,554 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 426832 states and 606288 transitions. [2022-12-13 12:12:10,559 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 425856 [2022-12-13 12:12:10,559 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:12:10,559 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:12:10,561 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:12:10,561 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:12:10,561 INFO L748 eck$LassoCheckResult]: Stem: 1790021#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 1790022#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 1791035#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1791036#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1791134#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 1791040#L731-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1790984#L736-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1790985#L741-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1791024#L746-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1789952#L751-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1789953#L756-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1790066#L761-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1790320#L766-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1790245#L771-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1789954#L776-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 1789618#L781-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1789619#L1036 assume !(0 == ~M_E~0); 1789713#L1036-2 assume !(0 == ~T1_E~0); 1790657#L1041-1 assume !(0 == ~T2_E~0); 1790658#L1046-1 assume !(0 == ~T3_E~0); 1789994#L1051-1 assume !(0 == ~T4_E~0); 1789995#L1056-1 assume !(0 == ~T5_E~0); 1790814#L1061-1 assume !(0 == ~T6_E~0); 1789887#L1066-1 assume !(0 == ~T7_E~0); 1789888#L1071-1 assume !(0 == ~T8_E~0); 1790790#L1076-1 assume !(0 == ~T9_E~0); 1789775#L1081-1 assume !(0 == ~T10_E~0); 1789776#L1086-1 assume !(0 == ~E_M~0); 1790188#L1091-1 assume !(0 == ~E_1~0); 1791054#L1096-1 assume !(0 == ~E_2~0); 1791055#L1101-1 assume !(0 == ~E_3~0); 1790259#L1106-1 assume !(0 == ~E_4~0); 1790260#L1111-1 assume !(0 == ~E_5~0); 1790439#L1116-1 assume !(0 == ~E_6~0); 1790440#L1121-1 assume !(0 == ~E_7~0); 1790249#L1126-1 assume !(0 == ~E_8~0); 1790250#L1131-1 assume !(0 == ~E_9~0); 1790540#L1136-1 assume !(0 == ~E_10~0); 1790663#L1141-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1790854#L514 assume !(1 == ~m_pc~0); 1790855#L514-2 is_master_triggered_~__retres1~0#1 := 0; 1790265#L525 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1790266#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1790942#L1285 assume !(0 != activate_threads_~tmp~1#1); 1791107#L1285-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1789906#L533 assume !(1 == ~t1_pc~0); 1789907#L533-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1790454#L544 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1789670#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1789671#L1293 assume !(0 != activate_threads_~tmp___0~0#1); 1790696#L1293-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1790697#L552 assume !(1 == ~t2_pc~0); 1790394#L552-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1790395#L563 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1790253#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1790254#L1301 assume !(0 != activate_threads_~tmp___1~0#1); 1790278#L1301-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1790279#L571 assume !(1 == ~t3_pc~0); 1790509#L571-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1790592#L582 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1789616#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1789617#L1309 assume !(0 != activate_threads_~tmp___2~0#1); 1790444#L1309-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1789699#L590 assume !(1 == ~t4_pc~0); 1789700#L590-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1790508#L601 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1791262#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1791111#L1317 assume !(0 != activate_threads_~tmp___3~0#1); 1790725#L1317-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1790441#L609 assume !(1 == ~t5_pc~0); 1790442#L609-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1791105#L620 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1790944#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1790945#L1325 assume !(0 != activate_threads_~tmp___4~0#1); 1790432#L1325-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1790433#L628 assume !(1 == ~t6_pc~0); 1790352#L628-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1790351#L639 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1790225#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1790226#L1333 assume !(0 != activate_threads_~tmp___5~0#1); 1790766#L1333-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1790767#L647 assume !(1 == ~t7_pc~0); 1790925#L647-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1790956#L658 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1790957#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1790261#L1341 assume !(0 != activate_threads_~tmp___6~0#1); 1790262#L1341-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1791168#L666 assume !(1 == ~t8_pc~0); 1790046#L666-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1790047#L677 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1790277#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1790466#L1349 assume !(0 != activate_threads_~tmp___7~0#1); 1790185#L1349-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1790186#L685 assume !(1 == ~t9_pc~0); 1791122#L685-2 is_transmit9_triggered_~__retres1~9#1 := 0; 1790971#L696 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1790313#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1790214#L1357 assume !(0 != activate_threads_~tmp___8~0#1); 1790215#L1357-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1790625#L704 assume !(1 == ~t10_pc~0); 1790207#L704-2 is_transmit10_triggered_~__retres1~10#1 := 0; 1790206#L715 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1790481#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1789746#L1365 assume !(0 != activate_threads_~tmp___9~0#1); 1789747#L1365-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1790003#L1154 assume 1 == ~M_E~0;~M_E~0 := 2; 1790750#L1154-2 assume !(1 == ~T1_E~0); 1791147#L1159-1 assume !(1 == ~T2_E~0); 1791220#L1164-1 assume !(1 == ~T3_E~0); 1791221#L1169-1 assume !(1 == ~T4_E~0); 1790314#L1174-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1790315#L1179-1 assume !(1 == ~T6_E~0); 1789958#L1184-1 assume !(1 == ~T7_E~0); 1789959#L1189-1 assume !(1 == ~T8_E~0); 1790170#L1194-1 assume !(1 == ~T9_E~0); 1790171#L1199-1 assume !(1 == ~T10_E~0); 1790122#L1204-1 assume !(1 == ~E_M~0); 1790123#L1209-1 assume !(1 == ~E_1~0); 1791164#L1214-1 assume 1 == ~E_2~0;~E_2~0 := 2; 1791218#L1219-1 assume !(1 == ~E_3~0); 1791152#L1224-1 assume !(1 == ~E_4~0); 1790485#L1229-1 assume !(1 == ~E_5~0); 1789842#L1234-1 assume !(1 == ~E_6~0); 1789843#L1239-1 assume !(1 == ~E_7~0); 1789902#L1244-1 assume !(1 == ~E_8~0); 1789903#L1249-1 assume !(1 == ~E_9~0); 1790802#L1254-1 assume 1 == ~E_10~0;~E_10~0 := 2; 1789741#L1259-1 assume { :end_inline_reset_delta_events } true; 1789742#L1565-2 [2022-12-13 12:12:10,562 INFO L750 eck$LassoCheckResult]: Loop: 1789742#L1565-2 assume !false; 1970166#L1566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1970161#L1011 assume !false; 1970160#L862 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 1970158#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 1970147#L851 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 1970146#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1970143#L866 assume !(0 != eval_~tmp~0#1); 1970144#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1980434#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1980432#L1036-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1980428#L1036-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1980424#L1041-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1980419#L1046-3 assume !(0 == ~T3_E~0); 1980414#L1051-3 assume !(0 == ~T4_E~0); 1980409#L1056-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1980404#L1061-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1980399#L1066-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1980394#L1071-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1980389#L1076-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 1980382#L1081-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 1980377#L1086-3 assume !(0 == ~E_M~0); 1980372#L1091-3 assume !(0 == ~E_1~0); 1980367#L1096-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1980362#L1101-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1980357#L1106-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1980350#L1111-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1980345#L1116-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1980337#L1121-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1980331#L1126-3 assume !(0 == ~E_8~0); 1980325#L1131-3 assume !(0 == ~E_9~0); 1980320#L1136-3 assume 0 == ~E_10~0;~E_10~0 := 1; 1980311#L1141-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1980302#L514-36 assume !(1 == ~m_pc~0); 1980252#L514-38 is_master_triggered_~__retres1~0#1 := 0; 1980243#L525-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1980232#is_master_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1980222#L1285-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1980164#L1285-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1980155#L533-36 assume !(1 == ~t1_pc~0); 1980120#L533-38 is_transmit1_triggered_~__retres1~1#1 := 0; 1980090#L544-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1980059#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1980049#L1293-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1979848#L1293-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1970369#L552-36 assume !(1 == ~t2_pc~0); 1970368#L552-38 is_transmit2_triggered_~__retres1~2#1 := 0; 1970367#L563-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1970366#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1970364#L1301-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1970363#L1301-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1970362#L571-36 assume !(1 == ~t3_pc~0); 1911361#L571-38 is_transmit3_triggered_~__retres1~3#1 := 0; 1970361#L582-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1970359#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1970358#L1309-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1970357#L1309-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1970352#L590-36 assume !(1 == ~t4_pc~0); 1970350#L590-38 is_transmit4_triggered_~__retres1~4#1 := 0; 1970348#L601-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1970346#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1970344#L1317-36 assume !(0 != activate_threads_~tmp___3~0#1); 1970341#L1317-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1970339#L609-36 assume !(1 == ~t5_pc~0); 1970337#L609-38 is_transmit5_triggered_~__retres1~5#1 := 0; 1970336#L620-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1970334#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1970332#L1325-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1970330#L1325-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1970328#L628-36 assume 1 == ~t6_pc~0; 1970324#L629-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1970321#L639-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1970319#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1970317#L1333-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1970314#L1333-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1970312#L647-36 assume !(1 == ~t7_pc~0); 1945052#L647-38 is_transmit7_triggered_~__retres1~7#1 := 0; 1970309#L658-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1970307#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1970305#L1341-36 assume !(0 != activate_threads_~tmp___6~0#1); 1970303#L1341-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1970301#L666-36 assume 1 == ~t8_pc~0; 1970298#L667-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 1970295#L677-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1970293#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1970291#L1349-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1970289#L1349-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1970287#L685-36 assume !(1 == ~t9_pc~0); 1886746#L685-38 is_transmit9_triggered_~__retres1~9#1 := 0; 1970285#L696-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1970283#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1970281#L1357-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1970279#L1357-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1970277#L704-36 assume 1 == ~t10_pc~0; 1970274#L705-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 1970271#L715-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1970269#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1970267#L1365-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1970265#L1365-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1970263#L1154-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1894498#L1154-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1970261#L1159-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1970259#L1164-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1970066#L1169-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1970256#L1174-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1970254#L1179-3 assume !(1 == ~T6_E~0); 1970252#L1184-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1970249#L1189-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1970247#L1194-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1970245#L1199-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 1970243#L1204-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1894470#L1209-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1970240#L1214-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1970238#L1219-3 assume !(1 == ~E_3~0); 1970236#L1224-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1970234#L1229-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1970232#L1234-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1970230#L1239-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1970228#L1244-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1962411#L1249-3 assume 1 == ~E_9~0;~E_9~0 := 2; 1970225#L1254-3 assume 1 == ~E_10~0;~E_10~0 := 2; 1970223#L1259-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 1970204#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 1970200#L851-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 1970198#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 1970197#L1584 assume !(0 == start_simulation_~tmp~3#1); 1970195#L1584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 1970193#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 1970180#L851-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 1970178#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 1970176#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1970175#L1546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1970174#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 1970170#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 1789742#L1565-2 [2022-12-13 12:12:10,562 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:12:10,562 INFO L85 PathProgramCache]: Analyzing trace with hash -1513086067, now seen corresponding path program 1 times [2022-12-13 12:12:10,562 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:12:10,562 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1990940897] [2022-12-13 12:12:10,562 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:12:10,562 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:12:10,574 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:12:10,608 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:12:10,609 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:12:10,609 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1990940897] [2022-12-13 12:12:10,609 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1990940897] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:12:10,609 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:12:10,609 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-12-13 12:12:10,609 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [72682518] [2022-12-13 12:12:10,609 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:12:10,609 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 12:12:10,610 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:12:10,610 INFO L85 PathProgramCache]: Analyzing trace with hash -490507423, now seen corresponding path program 1 times [2022-12-13 12:12:10,610 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:12:10,610 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1205475860] [2022-12-13 12:12:10,610 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:12:10,610 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:12:10,618 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:12:10,635 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:12:10,635 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:12:10,635 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1205475860] [2022-12-13 12:12:10,635 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1205475860] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:12:10,635 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:12:10,635 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:12:10,635 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [366394552] [2022-12-13 12:12:10,636 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:12:10,636 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:12:10,636 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:12:10,636 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 12:12:10,636 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 12:12:10,636 INFO L87 Difference]: Start difference. First operand 426832 states and 606288 transitions. cyclomatic complexity: 179488 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 2 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:12:12,006 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:12:12,006 INFO L93 Difference]: Finished difference Result 484541 states and 688137 transitions. [2022-12-13 12:12:12,006 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 484541 states and 688137 transitions. [2022-12-13 12:12:14,181 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 483488 [2022-12-13 12:12:15,045 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 484541 states to 484541 states and 688137 transitions. [2022-12-13 12:12:15,045 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 484541 [2022-12-13 12:12:15,243 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 484541 [2022-12-13 12:12:15,243 INFO L73 IsDeterministic]: Start isDeterministic. Operand 484541 states and 688137 transitions. [2022-12-13 12:12:15,543 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:12:15,543 INFO L218 hiAutomatonCegarLoop]: Abstraction has 484541 states and 688137 transitions. [2022-12-13 12:12:15,734 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 484541 states and 688137 transitions. [2022-12-13 12:12:17,385 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 484541 to 120648. [2022-12-13 12:12:17,460 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 120648 states, 120648 states have (on average 1.4243584642928189) internal successors, (171846), 120647 states have internal predecessors, (171846), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:12:17,624 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 120648 states to 120648 states and 171846 transitions. [2022-12-13 12:12:17,624 INFO L240 hiAutomatonCegarLoop]: Abstraction has 120648 states and 171846 transitions. [2022-12-13 12:12:17,625 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 12:12:17,625 INFO L428 stractBuchiCegarLoop]: Abstraction has 120648 states and 171846 transitions. [2022-12-13 12:12:17,625 INFO L335 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2022-12-13 12:12:17,625 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 120648 states and 171846 transitions. [2022-12-13 12:12:17,929 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 120320 [2022-12-13 12:12:17,929 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:12:17,929 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:12:17,933 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:12:17,933 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:12:17,934 INFO L748 eck$LassoCheckResult]: Stem: 2701407#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 2701408#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 2702460#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2702461#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2702568#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 2702467#L731-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2702391#L736-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2702392#L741-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2702448#L746-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 2701336#L751-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 2701337#L756-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 2701450#L761-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 2701708#L766-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 2701632#L771-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 2701338#L776-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 2700998#L781-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2700999#L1036 assume !(0 == ~M_E~0); 2701094#L1036-2 assume !(0 == ~T1_E~0); 2702050#L1041-1 assume !(0 == ~T2_E~0); 2702051#L1046-1 assume !(0 == ~T3_E~0); 2701381#L1051-1 assume !(0 == ~T4_E~0); 2701382#L1056-1 assume !(0 == ~T5_E~0); 2702216#L1061-1 assume !(0 == ~T6_E~0); 2701268#L1066-1 assume !(0 == ~T7_E~0); 2701269#L1071-1 assume !(0 == ~T8_E~0); 2702195#L1076-1 assume !(0 == ~T9_E~0); 2701156#L1081-1 assume !(0 == ~T10_E~0); 2701157#L1086-1 assume !(0 == ~E_M~0); 2701575#L1091-1 assume !(0 == ~E_1~0); 2702475#L1096-1 assume !(0 == ~E_2~0); 2702476#L1101-1 assume !(0 == ~E_3~0); 2701646#L1106-1 assume !(0 == ~E_4~0); 2701647#L1111-1 assume !(0 == ~E_5~0); 2701823#L1116-1 assume !(0 == ~E_6~0); 2701824#L1121-1 assume !(0 == ~E_7~0); 2701636#L1126-1 assume !(0 == ~E_8~0); 2701637#L1131-1 assume !(0 == ~E_9~0); 2701925#L1136-1 assume !(0 == ~E_10~0); 2702063#L1141-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2702257#L514 assume !(1 == ~m_pc~0); 2702258#L514-2 is_master_triggered_~__retres1~0#1 := 0; 2701652#L525 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2701653#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2702344#L1285 assume !(0 != activate_threads_~tmp~1#1); 2702534#L1285-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2701287#L533 assume !(1 == ~t1_pc~0); 2701288#L533-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2701838#L544 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2701050#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2701051#L1293 assume !(0 != activate_threads_~tmp___0~0#1); 2702092#L1293-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2702093#L552 assume !(1 == ~t2_pc~0); 2701783#L552-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2701784#L563 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2701640#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2701641#L1301 assume !(0 != activate_threads_~tmp___1~0#1); 2701665#L1301-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2701666#L571 assume !(1 == ~t3_pc~0); 2701894#L571-2 is_transmit3_triggered_~__retres1~3#1 := 0; 2701983#L582 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2700996#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2700997#L1309 assume !(0 != activate_threads_~tmp___2~0#1); 2701828#L1309-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2701080#L590 assume !(1 == ~t4_pc~0); 2701081#L590-2 is_transmit4_triggered_~__retres1~4#1 := 0; 2701893#L601 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2701174#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2701175#L1317 assume !(0 != activate_threads_~tmp___3~0#1); 2702126#L1317-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2701825#L609 assume !(1 == ~t5_pc~0); 2701826#L609-2 is_transmit5_triggered_~__retres1~5#1 := 0; 2702532#L620 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2702347#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2702348#L1325 assume !(0 != activate_threads_~tmp___4~0#1); 2701818#L1325-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2701819#L628 assume !(1 == ~t6_pc~0); 2701740#L628-2 is_transmit6_triggered_~__retres1~6#1 := 0; 2701739#L639 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2701613#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 2701614#L1333 assume !(0 != activate_threads_~tmp___5~0#1); 2702170#L1333-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2702171#L647 assume !(1 == ~t7_pc~0); 2702325#L647-2 is_transmit7_triggered_~__retres1~7#1 := 0; 2702360#L658 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2702361#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 2701648#L1341 assume !(0 != activate_threads_~tmp___6~0#1); 2701649#L1341-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2702601#L666 assume !(1 == ~t8_pc~0); 2701431#L666-2 is_transmit8_triggered_~__retres1~8#1 := 0; 2701432#L677 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2701664#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 2701849#L1349 assume !(0 != activate_threads_~tmp___7~0#1); 2701572#L1349-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 2701573#L685 assume !(1 == ~t9_pc~0); 2702549#L685-2 is_transmit9_triggered_~__retres1~9#1 := 0; 2702372#L696 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 2701701#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 2701603#L1357 assume !(0 != activate_threads_~tmp___8~0#1); 2701604#L1357-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 2702020#L704 assume !(1 == ~t10_pc~0); 2701597#L704-2 is_transmit10_triggered_~__retres1~10#1 := 0; 2701596#L715 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 2701864#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 2701127#L1365 assume !(0 != activate_threads_~tmp___9~0#1); 2701128#L1365-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2701391#L1154 assume !(1 == ~M_E~0); 2702155#L1154-2 assume !(1 == ~T1_E~0); 2701359#L1159-1 assume !(1 == ~T2_E~0); 2701360#L1164-1 assume !(1 == ~T3_E~0); 2701847#L1169-1 assume !(1 == ~T4_E~0); 2701702#L1174-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2701496#L1179-1 assume !(1 == ~T6_E~0); 2701345#L1184-1 assume !(1 == ~T7_E~0); 2701346#L1189-1 assume !(1 == ~T8_E~0); 2701429#L1194-1 assume !(1 == ~T9_E~0); 2701557#L1199-1 assume !(1 == ~T10_E~0); 2701508#L1204-1 assume !(1 == ~E_M~0); 2701509#L1209-1 assume !(1 == ~E_1~0); 2702120#L1214-1 assume 1 == ~E_2~0;~E_2~0 := 2; 2702121#L1219-1 assume !(1 == ~E_3~0); 2702584#L1224-1 assume !(1 == ~E_4~0); 2701868#L1229-1 assume !(1 == ~E_5~0); 2701223#L1234-1 assume !(1 == ~E_6~0); 2701224#L1239-1 assume !(1 == ~E_7~0); 2701283#L1244-1 assume !(1 == ~E_8~0); 2701284#L1249-1 assume !(1 == ~E_9~0); 2702207#L1254-1 assume 1 == ~E_10~0;~E_10~0 := 2; 2701122#L1259-1 assume { :end_inline_reset_delta_events } true; 2701123#L1565-2 [2022-12-13 12:12:17,934 INFO L750 eck$LassoCheckResult]: Loop: 2701123#L1565-2 assume !false; 2793601#L1566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2793595#L1011 assume !false; 2793593#L862 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 2793591#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 2793578#L851 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 2793576#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 2793574#L866 assume !(0 != eval_~tmp~0#1); 2702274#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2701886#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2701887#L1036-3 assume !(0 == ~M_E~0); 2702210#L1036-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2702507#L1041-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2702309#L1046-3 assume !(0 == ~T3_E~0); 2702310#L1051-3 assume !(0 == ~T4_E~0); 2702211#L1056-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2701378#L1061-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 2701379#L1066-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 2701380#L1071-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 2702510#L1076-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 2701114#L1081-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 2701115#L1086-3 assume !(0 == ~E_M~0); 2701166#L1091-3 assume !(0 == ~E_1~0); 2701167#L1096-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2702451#L1101-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2702452#L1106-3 assume 0 == ~E_4~0;~E_4~0 := 1; 2702506#L1111-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2702437#L1116-3 assume 0 == ~E_6~0;~E_6~0 := 1; 2702036#L1121-3 assume 0 == ~E_7~0;~E_7~0 := 1; 2702037#L1126-3 assume !(0 == ~E_8~0); 2702334#L1131-3 assume !(0 == ~E_9~0); 2702335#L1136-3 assume 0 == ~E_10~0;~E_10~0 := 1; 2702644#L1141-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2702039#L514-36 assume !(1 == ~m_pc~0); 2701717#L514-38 is_master_triggered_~__retres1~0#1 := 0; 2701544#L525-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2701545#is_master_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2702091#L1285-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2701438#L1285-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2701439#L533-36 assume 1 == ~t1_pc~0; 2701729#L534-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2701832#L544-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2702420#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2702141#L1293-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2701891#L1293-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2701892#L552-36 assume !(1 == ~t2_pc~0); 2702671#L552-38 is_transmit2_triggered_~__retres1~2#1 := 0; 2702672#L563-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2702323#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2702324#L1301-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2701403#L1301-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2701404#L571-36 assume !(1 == ~t3_pc~0); 2818330#L571-38 is_transmit3_triggered_~__retres1~3#1 := 0; 2818325#L582-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2818320#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2818316#L1309-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2818312#L1309-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2818307#L590-36 assume !(1 == ~t4_pc~0); 2818301#L590-38 is_transmit4_triggered_~__retres1~4#1 := 0; 2818294#L601-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2818288#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2818280#L1317-36 assume !(0 != activate_threads_~tmp___3~0#1); 2818273#L1317-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2818270#L609-36 assume !(1 == ~t5_pc~0); 2818265#L609-38 is_transmit5_triggered_~__retres1~5#1 := 0; 2818259#L620-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2818253#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2818247#L1325-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 2818241#L1325-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2818234#L628-36 assume 1 == ~t6_pc~0; 2818229#L629-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 2818222#L639-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2818216#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 2818212#L1333-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 2818163#L1333-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2812564#L647-36 assume !(1 == ~t7_pc~0); 2812555#L647-38 is_transmit7_triggered_~__retres1~7#1 := 0; 2812549#L658-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2812541#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 2812534#L1341-36 assume !(0 != activate_threads_~tmp___6~0#1); 2812527#L1341-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2812520#L666-36 assume 1 == ~t8_pc~0; 2812475#L667-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 2812466#L677-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2812459#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 2812452#L1349-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 2812445#L1349-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 2766175#L685-36 assume !(1 == ~t9_pc~0); 2766174#L685-38 is_transmit9_triggered_~__retres1~9#1 := 0; 2766173#L696-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 2766171#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 2766169#L1357-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 2766167#L1357-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 2766165#L704-36 assume !(1 == ~t10_pc~0); 2766162#L704-38 is_transmit10_triggered_~__retres1~10#1 := 0; 2766159#L715-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 2766156#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 2766154#L1365-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 2766152#L1365-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2766150#L1154-3 assume !(1 == ~M_E~0); 2736934#L1154-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2766147#L1159-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2766146#L1164-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2766144#L1169-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2766142#L1174-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2766140#L1179-3 assume !(1 == ~T6_E~0); 2766138#L1184-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 2766136#L1189-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 2766134#L1194-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 2766132#L1199-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 2766130#L1204-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2766128#L1209-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2766126#L1214-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2766124#L1219-3 assume !(1 == ~E_3~0); 2766122#L1224-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2766120#L1229-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2766118#L1234-3 assume 1 == ~E_6~0;~E_6~0 := 2; 2766116#L1239-3 assume 1 == ~E_7~0;~E_7~0 := 2; 2766114#L1244-3 assume 1 == ~E_8~0;~E_8~0 := 2; 2766112#L1249-3 assume 1 == ~E_9~0;~E_9~0 := 2; 2766110#L1254-3 assume 1 == ~E_10~0;~E_10~0 := 2; 2766108#L1259-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 2766096#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 2766073#L851-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 2766067#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 2737088#L1584 assume !(0 == start_simulation_~tmp~3#1); 2737089#L1584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 2793627#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 2793614#L851-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 2793610#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 2793609#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2793608#L1546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2793606#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 2793604#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 2701123#L1565-2 [2022-12-13 12:12:17,934 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:12:17,934 INFO L85 PathProgramCache]: Analyzing trace with hash 976442895, now seen corresponding path program 1 times [2022-12-13 12:12:17,935 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:12:17,935 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [834112345] [2022-12-13 12:12:17,935 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:12:17,935 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:12:17,943 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:12:18,164 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:12:18,164 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:12:18,164 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [834112345] [2022-12-13 12:12:18,164 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [834112345] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:12:18,165 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:12:18,165 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:12:18,165 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [553380530] [2022-12-13 12:12:18,165 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:12:18,166 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 12:12:18,166 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:12:18,166 INFO L85 PathProgramCache]: Analyzing trace with hash -745573279, now seen corresponding path program 1 times [2022-12-13 12:12:18,166 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:12:18,167 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [72132014] [2022-12-13 12:12:18,167 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:12:18,167 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:12:18,186 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:12:18,220 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:12:18,220 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:12:18,220 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [72132014] [2022-12-13 12:12:18,220 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [72132014] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:12:18,220 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:12:18,221 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:12:18,221 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1364897953] [2022-12-13 12:12:18,221 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:12:18,221 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:12:18,221 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:12:18,222 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 12:12:18,222 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 12:12:18,222 INFO L87 Difference]: Start difference. First operand 120648 states and 171846 transitions. cyclomatic complexity: 51202 Second operand has 4 states, 4 states have (on average 32.0) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:12:18,766 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:12:18,766 INFO L93 Difference]: Finished difference Result 189882 states and 270031 transitions. [2022-12-13 12:12:18,766 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 189882 states and 270031 transitions. [2022-12-13 12:12:19,669 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 189344 [2022-12-13 12:12:19,920 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 189882 states to 189882 states and 270031 transitions. [2022-12-13 12:12:19,920 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 189882 [2022-12-13 12:12:19,978 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 189882 [2022-12-13 12:12:19,978 INFO L73 IsDeterministic]: Start isDeterministic. Operand 189882 states and 270031 transitions. [2022-12-13 12:12:20,036 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:12:20,037 INFO L218 hiAutomatonCegarLoop]: Abstraction has 189882 states and 270031 transitions. [2022-12-13 12:12:20,107 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 189882 states and 270031 transitions. [2022-12-13 12:12:20,981 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 189882 to 133545. [2022-12-13 12:12:21,059 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 133545 states, 133545 states have (on average 1.4263207158635667) internal successors, (190478), 133544 states have internal predecessors, (190478), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:12:21,234 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 133545 states to 133545 states and 190478 transitions. [2022-12-13 12:12:21,235 INFO L240 hiAutomatonCegarLoop]: Abstraction has 133545 states and 190478 transitions. [2022-12-13 12:12:21,236 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 12:12:21,236 INFO L428 stractBuchiCegarLoop]: Abstraction has 133545 states and 190478 transitions. [2022-12-13 12:12:21,236 INFO L335 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2022-12-13 12:12:21,236 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 133545 states and 190478 transitions. [2022-12-13 12:12:21,573 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 133120 [2022-12-13 12:12:21,573 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:12:21,573 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:12:21,579 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:12:21,579 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:12:21,579 INFO L748 eck$LassoCheckResult]: Stem: 3011948#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 3011949#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 3012995#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3012996#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3013110#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 3012998#L731-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3012930#L736-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3012931#L741-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3012982#L746-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 3011877#L751-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 3011878#L756-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 3011992#L761-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 3012246#L766-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 3012166#L771-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 3011879#L776-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 3011538#L781-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3011539#L1036 assume !(0 == ~M_E~0); 3011634#L1036-2 assume !(0 == ~T1_E~0); 3012593#L1041-1 assume !(0 == ~T2_E~0); 3012594#L1046-1 assume !(0 == ~T3_E~0); 3011922#L1051-1 assume !(0 == ~T4_E~0); 3011923#L1056-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 3012760#L1061-1 assume !(0 == ~T6_E~0); 3011810#L1066-1 assume !(0 == ~T7_E~0); 3011811#L1071-1 assume !(0 == ~T8_E~0); 3012739#L1076-1 assume !(0 == ~T9_E~0); 3012740#L1081-1 assume !(0 == ~T10_E~0); 3012111#L1086-1 assume !(0 == ~E_M~0); 3012112#L1091-1 assume !(0 == ~E_1~0); 3013009#L1096-1 assume !(0 == ~E_2~0); 3013010#L1101-1 assume !(0 == ~E_3~0); 3012180#L1106-1 assume !(0 == ~E_4~0); 3012181#L1111-1 assume !(0 == ~E_5~0); 3012365#L1116-1 assume !(0 == ~E_6~0); 3012366#L1121-1 assume !(0 == ~E_7~0); 3012170#L1126-1 assume !(0 == ~E_8~0); 3012171#L1131-1 assume !(0 == ~E_9~0); 3012599#L1136-1 assume !(0 == ~E_10~0); 3012600#L1141-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3012799#L514 assume !(1 == ~m_pc~0); 3012800#L514-2 is_master_triggered_~__retres1~0#1 := 0; 3012186#L525 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3012187#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3013075#L1285 assume !(0 != activate_threads_~tmp~1#1); 3013076#L1285-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3011831#L533 assume !(1 == ~t1_pc~0); 3011832#L533-2 is_transmit1_triggered_~__retres1~1#1 := 0; 3013256#L544 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3011592#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3011593#L1293 assume !(0 != activate_threads_~tmp___0~0#1); 3012628#L1293-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3012629#L552 assume !(1 == ~t2_pc~0); 3012327#L552-2 is_transmit2_triggered_~__retres1~2#1 := 0; 3012328#L563 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3012174#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3012175#L1301 assume !(0 != activate_threads_~tmp___1~0#1); 3012211#L1301-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3012212#L571 assume !(1 == ~t3_pc~0); 3012442#L571-2 is_transmit3_triggered_~__retres1~3#1 := 0; 3012679#L582 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3012680#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3012637#L1309 assume !(0 != activate_threads_~tmp___2~0#1); 3012638#L1309-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3011620#L590 assume !(1 == ~t4_pc~0); 3011621#L590-2 is_transmit4_triggered_~__retres1~4#1 := 0; 3012440#L601 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3013248#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3013249#L1317 assume !(0 != activate_threads_~tmp___3~0#1); 3012666#L1317-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3012667#L609 assume !(1 == ~t5_pc~0); 3013243#L609-2 is_transmit5_triggered_~__retres1~5#1 := 0; 3013244#L620 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3012886#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3012887#L1325 assume !(0 != activate_threads_~tmp___4~0#1); 3012359#L1325-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3012360#L628 assume !(1 == ~t6_pc~0); 3012282#L628-2 is_transmit6_triggered_~__retres1~6#1 := 0; 3012281#L639 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3012150#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3012151#L1333 assume !(0 != activate_threads_~tmp___5~0#1); 3012711#L1333-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3012712#L647 assume !(1 == ~t7_pc~0); 3013111#L647-2 is_transmit7_triggered_~__retres1~7#1 := 0; 3013112#L658 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3013202#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 3013203#L1341 assume !(0 != activate_threads_~tmp___6~0#1); 3013171#L1341-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3013172#L666 assume !(1 == ~t8_pc~0); 3011972#L666-2 is_transmit8_triggered_~__retres1~8#1 := 0; 3011973#L677 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3012801#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 3012802#L1349 assume !(0 != activate_threads_~tmp___7~0#1); 3012108#L1349-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3012109#L685 assume !(1 == ~t9_pc~0); 3013240#L685-2 is_transmit9_triggered_~__retres1~9#1 := 0; 3013241#L696 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3012238#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 3012239#L1357 assume !(0 != activate_threads_~tmp___8~0#1); 3013252#L1357-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 3012561#L704 assume !(1 == ~t10_pc~0); 3012562#L704-2 is_transmit10_triggered_~__retres1~10#1 := 0; 3013018#L715 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 3013019#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 3011668#L1365 assume !(0 != activate_threads_~tmp___9~0#1); 3011669#L1365-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3012693#L1154 assume !(1 == ~M_E~0); 3012694#L1154-2 assume !(1 == ~T1_E~0); 3011898#L1159-1 assume !(1 == ~T2_E~0); 3011899#L1164-1 assume !(1 == ~T3_E~0); 3012394#L1169-1 assume !(1 == ~T4_E~0); 3012395#L1174-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3012035#L1179-1 assume !(1 == ~T6_E~0); 3011883#L1184-1 assume !(1 == ~T7_E~0); 3011884#L1189-1 assume !(1 == ~T8_E~0); 3011970#L1194-1 assume !(1 == ~T9_E~0); 3012094#L1199-1 assume !(1 == ~T10_E~0); 3012047#L1204-1 assume !(1 == ~E_M~0); 3012048#L1209-1 assume !(1 == ~E_1~0); 3012656#L1214-1 assume 1 == ~E_2~0;~E_2~0 := 2; 3012657#L1219-1 assume !(1 == ~E_3~0); 3013128#L1224-1 assume !(1 == ~E_4~0); 3012419#L1229-1 assume !(1 == ~E_5~0); 3011765#L1234-1 assume !(1 == ~E_6~0); 3011766#L1239-1 assume !(1 == ~E_7~0); 3011825#L1244-1 assume !(1 == ~E_8~0); 3011826#L1249-1 assume !(1 == ~E_9~0); 3012751#L1254-1 assume 1 == ~E_10~0;~E_10~0 := 2; 3011664#L1259-1 assume { :end_inline_reset_delta_events } true; 3011665#L1565-2 [2022-12-13 12:12:21,579 INFO L750 eck$LassoCheckResult]: Loop: 3011665#L1565-2 assume !false; 3069791#L1566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3069784#L1011 assume !false; 3069780#L862 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 3069756#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 3069740#L851 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 3069733#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 3069725#L866 assume !(0 != eval_~tmp~0#1); 3069726#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3073871#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3073869#L1036-3 assume !(0 == ~M_E~0); 3073867#L1036-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3073865#L1041-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3071013#L1046-3 assume !(0 == ~T3_E~0); 3070643#L1051-3 assume !(0 == ~T4_E~0); 3065479#L1056-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 3065480#L1061-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 3065470#L1066-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 3065471#L1071-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 3065462#L1076-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 3065463#L1081-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 3065454#L1086-3 assume !(0 == ~E_M~0); 3065455#L1091-3 assume !(0 == ~E_1~0); 3065446#L1096-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3065447#L1101-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3065438#L1106-3 assume 0 == ~E_4~0;~E_4~0 := 1; 3065439#L1111-3 assume 0 == ~E_5~0;~E_5~0 := 1; 3065430#L1116-3 assume 0 == ~E_6~0;~E_6~0 := 1; 3065431#L1121-3 assume 0 == ~E_7~0;~E_7~0 := 1; 3065422#L1126-3 assume !(0 == ~E_8~0); 3065423#L1131-3 assume !(0 == ~E_9~0); 3065414#L1136-3 assume 0 == ~E_10~0;~E_10~0 := 1; 3065415#L1141-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3065406#L514-36 assume !(1 == ~m_pc~0); 3065407#L514-38 is_master_triggered_~__retres1~0#1 := 0; 3065398#L525-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3065399#is_master_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3065390#L1285-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3065391#L1285-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3065381#L533-36 assume 1 == ~t1_pc~0; 3065382#L534-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3065364#L544-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3065365#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3065349#L1293-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3065350#L1293-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3058525#L552-36 assume !(1 == ~t2_pc~0); 3058526#L552-38 is_transmit2_triggered_~__retres1~2#1 := 0; 3058517#L563-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3058518#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3058508#L1301-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3058509#L1301-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3053076#L571-36 assume !(1 == ~t3_pc~0); 3053075#L571-38 is_transmit3_triggered_~__retres1~3#1 := 0; 3053072#L582-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3053070#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3053068#L1309-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3053066#L1309-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3053058#L590-36 assume 1 == ~t4_pc~0; 3053060#L591-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3053061#L601-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3053082#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3058200#L1317-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 3058199#L1317-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3058198#L609-36 assume !(1 == ~t5_pc~0); 3058197#L609-38 is_transmit5_triggered_~__retres1~5#1 := 0; 3058196#L620-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3058195#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3058194#L1325-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 3058193#L1325-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3058192#L628-36 assume !(1 == ~t6_pc~0); 3058190#L628-38 is_transmit6_triggered_~__retres1~6#1 := 0; 3053022#L639-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3053023#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3053016#L1333-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 3053017#L1333-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3047788#L647-36 assume !(1 == ~t7_pc~0); 3047786#L647-38 is_transmit7_triggered_~__retres1~7#1 := 0; 3047784#L658-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3047782#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 3047780#L1341-36 assume !(0 != activate_threads_~tmp___6~0#1); 3047778#L1341-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3047775#L666-36 assume 1 == ~t8_pc~0; 3047772#L667-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 3047770#L677-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3047767#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 3047765#L1349-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 3047763#L1349-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3047759#L685-36 assume !(1 == ~t9_pc~0); 3042524#L685-38 is_transmit9_triggered_~__retres1~9#1 := 0; 3047755#L696-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3047753#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 3047751#L1357-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 3047749#L1357-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 3047746#L704-36 assume 1 == ~t10_pc~0; 3047743#L705-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 3047741#L715-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 3047739#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 3047737#L1365-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 3047735#L1365-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3047732#L1154-3 assume !(1 == ~M_E~0); 3033729#L1154-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3047727#L1159-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3047724#L1164-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3046552#L1169-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3037894#L1174-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3037892#L1179-3 assume !(1 == ~T6_E~0); 3037890#L1184-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 3037888#L1189-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 3037886#L1194-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 3037884#L1199-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 3037883#L1204-3 assume 1 == ~E_M~0;~E_M~0 := 2; 3037881#L1209-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3037879#L1214-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3037877#L1219-3 assume !(1 == ~E_3~0); 3037875#L1224-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3037873#L1229-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3037870#L1234-3 assume 1 == ~E_6~0;~E_6~0 := 2; 3037868#L1239-3 assume 1 == ~E_7~0;~E_7~0 := 2; 3037866#L1244-3 assume 1 == ~E_8~0;~E_8~0 := 2; 3037864#L1249-3 assume 1 == ~E_9~0;~E_9~0 := 2; 3037862#L1254-3 assume 1 == ~E_10~0;~E_10~0 := 2; 3037861#L1259-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 3034666#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 3034662#L851-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 3034660#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 3033870#L1584 assume !(0 == start_simulation_~tmp~3#1); 3033871#L1584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 3069848#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 3069832#L851-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 3069828#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 3069823#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3069818#L1546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3069812#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 3069804#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 3011665#L1565-2 [2022-12-13 12:12:21,580 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:12:21,580 INFO L85 PathProgramCache]: Analyzing trace with hash -1176663923, now seen corresponding path program 1 times [2022-12-13 12:12:21,580 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:12:21,580 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1821158723] [2022-12-13 12:12:21,580 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:12:21,580 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:12:21,587 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:12:21,619 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:12:21,619 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:12:21,619 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1821158723] [2022-12-13 12:12:21,619 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1821158723] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:12:21,619 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:12:21,619 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:12:21,619 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1230728547] [2022-12-13 12:12:21,619 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:12:21,620 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 12:12:21,620 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:12:21,620 INFO L85 PathProgramCache]: Analyzing trace with hash -424366690, now seen corresponding path program 1 times [2022-12-13 12:12:21,620 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:12:21,620 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [932603081] [2022-12-13 12:12:21,621 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:12:21,621 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:12:21,630 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:12:21,801 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:12:21,802 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:12:21,802 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [932603081] [2022-12-13 12:12:21,802 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [932603081] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:12:21,802 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:12:21,802 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:12:21,802 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [891997213] [2022-12-13 12:12:21,803 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:12:21,803 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:12:21,803 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:12:21,803 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 12:12:21,804 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 12:12:21,804 INFO L87 Difference]: Start difference. First operand 133545 states and 190478 transitions. cyclomatic complexity: 56937 Second operand has 4 states, 4 states have (on average 32.0) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:12:22,250 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:12:22,250 INFO L93 Difference]: Finished difference Result 176968 states and 250916 transitions. [2022-12-13 12:12:22,250 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 176968 states and 250916 transitions. [2022-12-13 12:12:22,797 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 176544 [2022-12-13 12:12:23,316 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 176968 states to 176968 states and 250916 transitions. [2022-12-13 12:12:23,316 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 176968 [2022-12-13 12:12:23,373 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 176968 [2022-12-13 12:12:23,373 INFO L73 IsDeterministic]: Start isDeterministic. Operand 176968 states and 250916 transitions. [2022-12-13 12:12:23,440 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:12:23,440 INFO L218 hiAutomatonCegarLoop]: Abstraction has 176968 states and 250916 transitions. [2022-12-13 12:12:23,513 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 176968 states and 250916 transitions. [2022-12-13 12:12:24,485 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 176968 to 120648. [2022-12-13 12:12:24,547 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 120648 states, 120648 states have (on average 1.4211590743319409) internal successors, (171460), 120647 states have internal predecessors, (171460), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:12:24,710 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 120648 states to 120648 states and 171460 transitions. [2022-12-13 12:12:24,711 INFO L240 hiAutomatonCegarLoop]: Abstraction has 120648 states and 171460 transitions. [2022-12-13 12:12:24,711 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 12:12:24,712 INFO L428 stractBuchiCegarLoop]: Abstraction has 120648 states and 171460 transitions. [2022-12-13 12:12:24,712 INFO L335 stractBuchiCegarLoop]: ======== Iteration 23 ============ [2022-12-13 12:12:24,712 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 120648 states and 171460 transitions. [2022-12-13 12:12:25,020 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 120320 [2022-12-13 12:12:25,021 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:12:25,021 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:12:25,024 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:12:25,024 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:12:25,025 INFO L748 eck$LassoCheckResult]: Stem: 3322467#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 3322468#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 3323473#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3323474#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3323587#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 3323476#L731-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3323409#L736-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3323410#L741-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3323464#L746-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 3322399#L751-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 3322400#L756-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 3322509#L761-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 3322758#L766-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 3322684#L771-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 3322401#L776-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 3322061#L781-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3322062#L1036 assume !(0 == ~M_E~0); 3322157#L1036-2 assume !(0 == ~T1_E~0); 3323092#L1041-1 assume !(0 == ~T2_E~0); 3323093#L1046-1 assume !(0 == ~T3_E~0); 3322442#L1051-1 assume !(0 == ~T4_E~0); 3322443#L1056-1 assume !(0 == ~T5_E~0); 3323255#L1061-1 assume !(0 == ~T6_E~0); 3322332#L1066-1 assume !(0 == ~T7_E~0); 3322333#L1071-1 assume !(0 == ~T8_E~0); 3323236#L1076-1 assume !(0 == ~T9_E~0); 3322220#L1081-1 assume !(0 == ~T10_E~0); 3322221#L1086-1 assume !(0 == ~E_M~0); 3322631#L1091-1 assume !(0 == ~E_1~0); 3323487#L1096-1 assume !(0 == ~E_2~0); 3323488#L1101-1 assume !(0 == ~E_3~0); 3322698#L1106-1 assume !(0 == ~E_4~0); 3322699#L1111-1 assume !(0 == ~E_5~0); 3322874#L1116-1 assume !(0 == ~E_6~0); 3322875#L1121-1 assume !(0 == ~E_7~0); 3322688#L1126-1 assume !(0 == ~E_8~0); 3322689#L1131-1 assume !(0 == ~E_9~0); 3322974#L1136-1 assume !(0 == ~E_10~0); 3323103#L1141-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3323295#L514 assume !(1 == ~m_pc~0); 3323296#L514-2 is_master_triggered_~__retres1~0#1 := 0; 3322704#L525 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3322705#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3323371#L1285 assume !(0 != activate_threads_~tmp~1#1); 3323553#L1285-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3322353#L533 assume !(1 == ~t1_pc~0); 3322354#L533-2 is_transmit1_triggered_~__retres1~1#1 := 0; 3322888#L544 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3322115#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3322116#L1293 assume !(0 != activate_threads_~tmp___0~0#1); 3323136#L1293-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3323137#L552 assume !(1 == ~t2_pc~0); 3322835#L552-2 is_transmit2_triggered_~__retres1~2#1 := 0; 3322836#L563 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3322692#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3322693#L1301 assume !(0 != activate_threads_~tmp___1~0#1); 3322725#L1301-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3322726#L571 assume !(1 == ~t3_pc~0); 3322942#L571-2 is_transmit3_triggered_~__retres1~3#1 := 0; 3323031#L582 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3322059#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3322060#L1309 assume !(0 != activate_threads_~tmp___2~0#1); 3322878#L1309-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3322143#L590 assume !(1 == ~t4_pc~0); 3322144#L590-2 is_transmit4_triggered_~__retres1~4#1 := 0; 3322940#L601 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3323688#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3323555#L1317 assume !(0 != activate_threads_~tmp___3~0#1); 3323168#L1317-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3322876#L609 assume !(1 == ~t5_pc~0); 3322877#L609-2 is_transmit5_triggered_~__retres1~5#1 := 0; 3323547#L620 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3323372#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3323373#L1325 assume !(0 != activate_threads_~tmp___4~0#1); 3322869#L1325-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3322870#L628 assume !(1 == ~t6_pc~0); 3322792#L628-2 is_transmit6_triggered_~__retres1~6#1 := 0; 3322791#L639 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3322668#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3322669#L1333 assume !(0 != activate_threads_~tmp___5~0#1); 3323209#L1333-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3323210#L647 assume !(1 == ~t7_pc~0); 3323353#L647-2 is_transmit7_triggered_~__retres1~7#1 := 0; 3323383#L658 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3323384#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 3322702#L1341 assume !(0 != activate_threads_~tmp___6~0#1); 3322703#L1341-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3323614#L666 assume !(1 == ~t8_pc~0); 3322489#L666-2 is_transmit8_triggered_~__retres1~8#1 := 0; 3322490#L677 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3322716#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 3322901#L1349 assume !(0 != activate_threads_~tmp___7~0#1); 3322628#L1349-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3322629#L685 assume !(1 == ~t9_pc~0); 3323567#L685-2 is_transmit9_triggered_~__retres1~9#1 := 0; 3323394#L696 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3322752#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 3322655#L1357 assume !(0 != activate_threads_~tmp___8~0#1); 3322656#L1357-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 3323062#L704 assume !(1 == ~t10_pc~0); 3322649#L704-2 is_transmit10_triggered_~__retres1~10#1 := 0; 3322648#L715 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 3322914#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 3322191#L1365 assume !(0 != activate_threads_~tmp___9~0#1); 3322192#L1365-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3322449#L1154 assume !(1 == ~M_E~0); 3323191#L1154-2 assume !(1 == ~T1_E~0); 3322419#L1159-1 assume !(1 == ~T2_E~0); 3322420#L1164-1 assume !(1 == ~T3_E~0); 3322897#L1169-1 assume !(1 == ~T4_E~0); 3322753#L1174-1 assume !(1 == ~T5_E~0); 3322555#L1179-1 assume !(1 == ~T6_E~0); 3322404#L1184-1 assume !(1 == ~T7_E~0); 3322405#L1189-1 assume !(1 == ~T8_E~0); 3322487#L1194-1 assume !(1 == ~T9_E~0); 3322615#L1199-1 assume !(1 == ~T10_E~0); 3322567#L1204-1 assume !(1 == ~E_M~0); 3322568#L1209-1 assume !(1 == ~E_1~0); 3323160#L1214-1 assume 1 == ~E_2~0;~E_2~0 := 2; 3323161#L1219-1 assume !(1 == ~E_3~0); 3323595#L1224-1 assume !(1 == ~E_4~0); 3322919#L1229-1 assume !(1 == ~E_5~0); 3322287#L1234-1 assume !(1 == ~E_6~0); 3322288#L1239-1 assume !(1 == ~E_7~0); 3322347#L1244-1 assume !(1 == ~E_8~0); 3322348#L1249-1 assume !(1 == ~E_9~0); 3323247#L1254-1 assume 1 == ~E_10~0;~E_10~0 := 2; 3322187#L1259-1 assume { :end_inline_reset_delta_events } true; 3322188#L1565-2 [2022-12-13 12:12:25,025 INFO L750 eck$LassoCheckResult]: Loop: 3322188#L1565-2 assume !false; 3411457#L1566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3411451#L1011 assume !false; 3411449#L862 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 3411447#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 3411436#L851 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 3411435#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 3411430#L866 assume !(0 != eval_~tmp~0#1); 3411431#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3442469#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3442468#L1036-3 assume !(0 == ~M_E~0); 3442467#L1036-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3442466#L1041-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3442465#L1046-3 assume !(0 == ~T3_E~0); 3442464#L1051-3 assume !(0 == ~T4_E~0); 3442463#L1056-3 assume !(0 == ~T5_E~0); 3442462#L1061-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 3442461#L1066-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 3442459#L1071-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 3442456#L1076-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 3442454#L1081-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 3442452#L1086-3 assume !(0 == ~E_M~0); 3442450#L1091-3 assume !(0 == ~E_1~0); 3442448#L1096-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3442446#L1101-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3442443#L1106-3 assume 0 == ~E_4~0;~E_4~0 := 1; 3442441#L1111-3 assume 0 == ~E_5~0;~E_5~0 := 1; 3442439#L1116-3 assume 0 == ~E_6~0;~E_6~0 := 1; 3442437#L1121-3 assume 0 == ~E_7~0;~E_7~0 := 1; 3442435#L1126-3 assume !(0 == ~E_8~0); 3442433#L1131-3 assume !(0 == ~E_9~0); 3442432#L1136-3 assume 0 == ~E_10~0;~E_10~0 := 1; 3442431#L1141-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3442430#L514-36 assume !(1 == ~m_pc~0); 3442429#L514-38 is_master_triggered_~__retres1~0#1 := 0; 3442428#L525-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3442427#is_master_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3442426#L1285-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3442425#L1285-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3442424#L533-36 assume 1 == ~t1_pc~0; 3442422#L534-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3442421#L544-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3442420#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3442419#L1293-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3442418#L1293-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3442417#L552-36 assume !(1 == ~t2_pc~0); 3442045#L552-38 is_transmit2_triggered_~__retres1~2#1 := 0; 3442416#L563-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3442415#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3442414#L1301-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3442413#L1301-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3442412#L571-36 assume !(1 == ~t3_pc~0); 3432059#L571-38 is_transmit3_triggered_~__retres1~3#1 := 0; 3442411#L582-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3442410#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3442409#L1309-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3442408#L1309-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3442404#L590-36 assume 1 == ~t4_pc~0; 3442405#L591-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3442406#L601-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3442407#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3442399#L1317-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 3442398#L1317-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3442397#L609-36 assume !(1 == ~t5_pc~0); 3442396#L609-38 is_transmit5_triggered_~__retres1~5#1 := 0; 3442395#L620-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3442394#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3442393#L1325-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 3442391#L1325-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3442389#L628-36 assume !(1 == ~t6_pc~0); 3442386#L628-38 is_transmit6_triggered_~__retres1~6#1 := 0; 3442384#L639-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3442382#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3442380#L1333-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 3442378#L1333-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3417493#L647-36 assume !(1 == ~t7_pc~0); 3417491#L647-38 is_transmit7_triggered_~__retres1~7#1 := 0; 3417488#L658-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3417486#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 3417484#L1341-36 assume !(0 != activate_threads_~tmp___6~0#1); 3417482#L1341-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3417480#L666-36 assume 1 == ~t8_pc~0; 3417477#L667-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 3417275#L677-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3417265#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 3417244#L1349-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 3417231#L1349-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3399266#L685-36 assume !(1 == ~t9_pc~0); 3399264#L685-38 is_transmit9_triggered_~__retres1~9#1 := 0; 3399262#L696-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3399260#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 3399259#L1357-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 3399255#L1357-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 3399253#L704-36 assume !(1 == ~t10_pc~0); 3399251#L704-38 is_transmit10_triggered_~__retres1~10#1 := 0; 3399248#L715-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 3399245#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 3399243#L1365-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 3399241#L1365-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3399239#L1154-3 assume !(1 == ~M_E~0); 3378714#L1154-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3399236#L1159-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3399234#L1164-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3399232#L1169-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3399230#L1174-3 assume !(1 == ~T5_E~0); 3399227#L1179-3 assume !(1 == ~T6_E~0); 3399225#L1184-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 3399223#L1189-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 3399221#L1194-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 3396416#L1199-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 3396413#L1204-3 assume 1 == ~E_M~0;~E_M~0 := 2; 3396411#L1209-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3396409#L1214-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3396407#L1219-3 assume !(1 == ~E_3~0); 3396405#L1224-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3396401#L1229-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3396399#L1234-3 assume 1 == ~E_6~0;~E_6~0 := 2; 3396397#L1239-3 assume 1 == ~E_7~0;~E_7~0 := 2; 3396395#L1244-3 assume 1 == ~E_8~0;~E_8~0 := 2; 3396392#L1249-3 assume 1 == ~E_9~0;~E_9~0 := 2; 3396390#L1254-3 assume 1 == ~E_10~0;~E_10~0 := 2; 3396388#L1259-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 3383538#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 3383534#L851-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 3383532#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 3378881#L1584 assume !(0 == start_simulation_~tmp~3#1); 3378882#L1584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 3411483#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 3411471#L851-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 3411469#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 3411467#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3411465#L1546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3411463#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 3411461#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 3322188#L1565-2 [2022-12-13 12:12:25,025 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:12:25,025 INFO L85 PathProgramCache]: Analyzing trace with hash -1017701811, now seen corresponding path program 1 times [2022-12-13 12:12:25,025 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:12:25,025 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [266406949] [2022-12-13 12:12:25,025 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:12:25,026 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:12:25,037 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:12:25,084 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:12:25,084 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:12:25,084 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [266406949] [2022-12-13 12:12:25,084 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [266406949] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:12:25,085 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:12:25,085 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-12-13 12:12:25,085 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1839948381] [2022-12-13 12:12:25,085 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:12:25,085 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 12:12:25,085 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:12:25,085 INFO L85 PathProgramCache]: Analyzing trace with hash 2125885855, now seen corresponding path program 1 times [2022-12-13 12:12:25,086 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:12:25,086 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1816148022] [2022-12-13 12:12:25,086 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:12:25,086 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:12:25,095 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:12:25,113 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:12:25,114 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:12:25,114 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1816148022] [2022-12-13 12:12:25,114 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1816148022] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:12:25,114 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:12:25,114 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:12:25,114 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [600750546] [2022-12-13 12:12:25,114 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:12:25,115 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:12:25,115 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:12:25,115 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 12:12:25,115 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 12:12:25,115 INFO L87 Difference]: Start difference. First operand 120648 states and 171460 transitions. cyclomatic complexity: 50816 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 2 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:12:25,424 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:12:25,425 INFO L93 Difference]: Finished difference Result 120648 states and 170498 transitions. [2022-12-13 12:12:25,425 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 120648 states and 170498 transitions. [2022-12-13 12:12:25,972 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 120320 [2022-12-13 12:12:26,184 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 120648 states to 120648 states and 170498 transitions. [2022-12-13 12:12:26,184 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 120648 [2022-12-13 12:12:26,232 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 120648 [2022-12-13 12:12:26,232 INFO L73 IsDeterministic]: Start isDeterministic. Operand 120648 states and 170498 transitions. [2022-12-13 12:12:26,278 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:12:26,278 INFO L218 hiAutomatonCegarLoop]: Abstraction has 120648 states and 170498 transitions. [2022-12-13 12:12:26,332 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 120648 states and 170498 transitions. [2022-12-13 12:12:27,068 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 120648 to 120648. [2022-12-13 12:12:27,138 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 120648 states, 120648 states have (on average 1.4131854651548306) internal successors, (170498), 120647 states have internal predecessors, (170498), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:12:27,302 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 120648 states to 120648 states and 170498 transitions. [2022-12-13 12:12:27,302 INFO L240 hiAutomatonCegarLoop]: Abstraction has 120648 states and 170498 transitions. [2022-12-13 12:12:27,303 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 12:12:27,303 INFO L428 stractBuchiCegarLoop]: Abstraction has 120648 states and 170498 transitions. [2022-12-13 12:12:27,303 INFO L335 stractBuchiCegarLoop]: ======== Iteration 24 ============ [2022-12-13 12:12:27,303 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 120648 states and 170498 transitions. [2022-12-13 12:12:27,616 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 120320 [2022-12-13 12:12:27,616 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:12:27,616 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:12:27,620 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:12:27,620 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:12:27,620 INFO L748 eck$LassoCheckResult]: Stem: 3563766#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 3563767#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 3564751#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3564752#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3564850#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 3564754#L731-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3564690#L736-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3564691#L741-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3564740#L746-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 3563699#L751-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 3563700#L756-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 3563807#L761-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 3564058#L766-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 3563984#L771-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 3563701#L776-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 3563364#L781-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3563365#L1036 assume !(0 == ~M_E~0); 3563460#L1036-2 assume !(0 == ~T1_E~0); 3564389#L1041-1 assume !(0 == ~T2_E~0); 3564390#L1046-1 assume !(0 == ~T3_E~0); 3563741#L1051-1 assume !(0 == ~T4_E~0); 3563742#L1056-1 assume !(0 == ~T5_E~0); 3564540#L1061-1 assume !(0 == ~T6_E~0); 3563634#L1066-1 assume !(0 == ~T7_E~0); 3563635#L1071-1 assume !(0 == ~T8_E~0); 3564522#L1076-1 assume !(0 == ~T9_E~0); 3563522#L1081-1 assume !(0 == ~T10_E~0); 3563523#L1086-1 assume !(0 == ~E_M~0); 3563927#L1091-1 assume !(0 == ~E_1~0); 3564764#L1096-1 assume !(0 == ~E_2~0); 3564765#L1101-1 assume !(0 == ~E_3~0); 3563998#L1106-1 assume !(0 == ~E_4~0); 3563999#L1111-1 assume !(0 == ~E_5~0); 3564171#L1116-1 assume !(0 == ~E_6~0); 3564172#L1121-1 assume !(0 == ~E_7~0); 3563988#L1126-1 assume !(0 == ~E_8~0); 3563989#L1131-1 assume !(0 == ~E_9~0); 3564270#L1136-1 assume !(0 == ~E_10~0); 3564399#L1141-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3564576#L514 assume !(1 == ~m_pc~0); 3564577#L514-2 is_master_triggered_~__retres1~0#1 := 0; 3564004#L525 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3564005#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3564651#L1285 assume !(0 != activate_threads_~tmp~1#1); 3564818#L1285-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3563653#L533 assume !(1 == ~t1_pc~0); 3563654#L533-2 is_transmit1_triggered_~__retres1~1#1 := 0; 3564185#L544 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3563416#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3563417#L1293 assume !(0 != activate_threads_~tmp___0~0#1); 3564426#L1293-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3564427#L552 assume !(1 == ~t2_pc~0); 3564130#L552-2 is_transmit2_triggered_~__retres1~2#1 := 0; 3564131#L563 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3563992#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3563993#L1301 assume !(0 != activate_threads_~tmp___1~0#1); 3564017#L1301-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3564018#L571 assume !(1 == ~t3_pc~0); 3564238#L571-2 is_transmit3_triggered_~__retres1~3#1 := 0; 3564328#L582 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3563362#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3563363#L1309 assume !(0 != activate_threads_~tmp___2~0#1); 3564175#L1309-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3563446#L590 assume !(1 == ~t4_pc~0); 3563447#L590-2 is_transmit4_triggered_~__retres1~4#1 := 0; 3564237#L601 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3564957#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3564823#L1317 assume !(0 != activate_threads_~tmp___3~0#1); 3564454#L1317-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3564173#L609 assume !(1 == ~t5_pc~0); 3564174#L609-2 is_transmit5_triggered_~__retres1~5#1 := 0; 3564816#L620 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3564653#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3564654#L1325 assume !(0 != activate_threads_~tmp___4~0#1); 3564166#L1325-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3564167#L628 assume !(1 == ~t6_pc~0); 3564091#L628-2 is_transmit6_triggered_~__retres1~6#1 := 0; 3564090#L639 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3563965#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3563966#L1333 assume !(0 != activate_threads_~tmp___5~0#1); 3564496#L1333-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3564497#L647 assume !(1 == ~t7_pc~0); 3564635#L647-2 is_transmit7_triggered_~__retres1~7#1 := 0; 3564664#L658 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3564665#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 3564000#L1341 assume !(0 != activate_threads_~tmp___6~0#1); 3564001#L1341-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3564884#L666 assume !(1 == ~t8_pc~0); 3563789#L666-2 is_transmit8_triggered_~__retres1~8#1 := 0; 3563790#L677 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3564016#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 3564197#L1349 assume !(0 != activate_threads_~tmp___7~0#1); 3563924#L1349-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3563925#L685 assume !(1 == ~t9_pc~0); 3564833#L685-2 is_transmit9_triggered_~__retres1~9#1 := 0; 3564675#L696 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3564051#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 3563953#L1357 assume !(0 != activate_threads_~tmp___8~0#1); 3563954#L1357-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 3564361#L704 assume !(1 == ~t10_pc~0); 3563947#L704-2 is_transmit10_triggered_~__retres1~10#1 := 0; 3563946#L715 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 3564211#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 3563493#L1365 assume !(0 != activate_threads_~tmp___9~0#1); 3563494#L1365-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3563750#L1154 assume !(1 == ~M_E~0); 3564479#L1154-2 assume !(1 == ~T1_E~0); 3563719#L1159-1 assume !(1 == ~T2_E~0); 3563720#L1164-1 assume !(1 == ~T3_E~0); 3564195#L1169-1 assume !(1 == ~T4_E~0); 3564052#L1174-1 assume !(1 == ~T5_E~0); 3563848#L1179-1 assume !(1 == ~T6_E~0); 3563705#L1184-1 assume !(1 == ~T7_E~0); 3563706#L1189-1 assume !(1 == ~T8_E~0); 3563787#L1194-1 assume !(1 == ~T9_E~0); 3563909#L1199-1 assume !(1 == ~T10_E~0); 3563860#L1204-1 assume !(1 == ~E_M~0); 3563861#L1209-1 assume !(1 == ~E_1~0); 3564448#L1214-1 assume !(1 == ~E_2~0); 3564449#L1219-1 assume !(1 == ~E_3~0); 3564866#L1224-1 assume !(1 == ~E_4~0); 3564215#L1229-1 assume !(1 == ~E_5~0); 3563590#L1234-1 assume !(1 == ~E_6~0); 3563591#L1239-1 assume !(1 == ~E_7~0); 3563649#L1244-1 assume !(1 == ~E_8~0); 3563650#L1249-1 assume !(1 == ~E_9~0); 3564533#L1254-1 assume 1 == ~E_10~0;~E_10~0 := 2; 3563487#L1259-1 assume { :end_inline_reset_delta_events } true; 3563488#L1565-2 [2022-12-13 12:12:27,621 INFO L750 eck$LassoCheckResult]: Loop: 3563488#L1565-2 assume !false; 3662145#L1566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3662139#L1011 assume !false; 3662137#L862 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 3662135#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 3662123#L851 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 3662122#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 3662117#L866 assume !(0 != eval_~tmp~0#1); 3662118#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3680209#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3680205#L1036-3 assume !(0 == ~M_E~0); 3680201#L1036-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3680195#L1041-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3680193#L1046-3 assume !(0 == ~T3_E~0); 3680186#L1051-3 assume !(0 == ~T4_E~0); 3680177#L1056-3 assume !(0 == ~T5_E~0); 3680170#L1061-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 3680163#L1066-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 3680156#L1071-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 3680151#L1076-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 3680140#L1081-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 3680111#L1086-3 assume !(0 == ~E_M~0); 3680106#L1091-3 assume !(0 == ~E_1~0); 3680101#L1096-3 assume !(0 == ~E_2~0); 3680096#L1101-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3680090#L1106-3 assume 0 == ~E_4~0;~E_4~0 := 1; 3680085#L1111-3 assume 0 == ~E_5~0;~E_5~0 := 1; 3680077#L1116-3 assume 0 == ~E_6~0;~E_6~0 := 1; 3680071#L1121-3 assume 0 == ~E_7~0;~E_7~0 := 1; 3680065#L1126-3 assume !(0 == ~E_8~0); 3680059#L1131-3 assume !(0 == ~E_9~0); 3680053#L1136-3 assume 0 == ~E_10~0;~E_10~0 := 1; 3680047#L1141-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3680042#L514-36 assume !(1 == ~m_pc~0); 3680037#L514-38 is_master_triggered_~__retres1~0#1 := 0; 3680030#L525-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3680025#is_master_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3680018#L1285-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3680011#L1285-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3680005#L533-36 assume 1 == ~t1_pc~0; 3679998#L534-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3679992#L544-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3679989#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3679869#L1293-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3679868#L1293-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3664696#L552-36 assume !(1 == ~t2_pc~0); 3664694#L552-38 is_transmit2_triggered_~__retres1~2#1 := 0; 3664692#L563-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3664690#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3664688#L1301-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3664686#L1301-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3664683#L571-36 assume !(1 == ~t3_pc~0); 3661918#L571-38 is_transmit3_triggered_~__retres1~3#1 := 0; 3664680#L582-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3664678#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3664676#L1309-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3664673#L1309-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3664668#L590-36 assume 1 == ~t4_pc~0; 3664669#L591-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3664670#L601-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3667150#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3664659#L1317-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 3664657#L1317-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3664656#L609-36 assume !(1 == ~t5_pc~0); 3664654#L609-38 is_transmit5_triggered_~__retres1~5#1 := 0; 3664652#L620-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3664650#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3664648#L1325-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 3664644#L1325-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3664642#L628-36 assume !(1 == ~t6_pc~0); 3664639#L628-38 is_transmit6_triggered_~__retres1~6#1 := 0; 3664637#L639-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3664634#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3664632#L1333-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 3664630#L1333-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3664628#L647-36 assume !(1 == ~t7_pc~0); 3652935#L647-38 is_transmit7_triggered_~__retres1~7#1 := 0; 3664625#L658-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3664623#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 3664621#L1341-36 assume !(0 != activate_threads_~tmp___6~0#1); 3664619#L1341-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3664616#L666-36 assume !(1 == ~t8_pc~0); 3664614#L666-38 is_transmit8_triggered_~__retres1~8#1 := 0; 3664613#L677-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3676753#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 3676751#L1349-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 3676750#L1349-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3662269#L685-36 assume !(1 == ~t9_pc~0); 3662266#L685-38 is_transmit9_triggered_~__retres1~9#1 := 0; 3662264#L696-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3662262#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 3662260#L1357-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 3662258#L1357-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 3662257#L704-36 assume !(1 == ~t10_pc~0); 3662256#L704-38 is_transmit10_triggered_~__retres1~10#1 := 0; 3662254#L715-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 3662250#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 3662248#L1365-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 3662246#L1365-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3662245#L1154-3 assume !(1 == ~M_E~0); 3620768#L1154-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3662241#L1159-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3662238#L1164-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3662233#L1169-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3662230#L1174-3 assume !(1 == ~T5_E~0); 3662225#L1179-3 assume !(1 == ~T6_E~0); 3662221#L1184-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 3662220#L1189-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 3662219#L1194-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 3662218#L1199-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 3662217#L1204-3 assume 1 == ~E_M~0;~E_M~0 := 2; 3662216#L1209-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3662215#L1214-3 assume !(1 == ~E_2~0); 3662214#L1219-3 assume !(1 == ~E_3~0); 3662212#L1224-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3662210#L1229-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3662208#L1234-3 assume 1 == ~E_6~0;~E_6~0 := 2; 3662206#L1239-3 assume 1 == ~E_7~0;~E_7~0 := 2; 3662204#L1244-3 assume 1 == ~E_8~0;~E_8~0 := 2; 3662202#L1249-3 assume 1 == ~E_9~0;~E_9~0 := 2; 3662200#L1254-3 assume 1 == ~E_10~0;~E_10~0 := 2; 3662198#L1259-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 3662179#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 3662175#L851-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 3662173#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 3662172#L1584 assume !(0 == start_simulation_~tmp~3#1); 3662170#L1584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 3662168#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 3662158#L851-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 3662157#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 3662155#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3662153#L1546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3662151#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 3662149#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 3563488#L1565-2 [2022-12-13 12:12:27,621 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:12:27,621 INFO L85 PathProgramCache]: Analyzing trace with hash -1410728821, now seen corresponding path program 1 times [2022-12-13 12:12:27,621 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:12:27,621 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1340954096] [2022-12-13 12:12:27,621 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:12:27,621 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:12:27,629 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:12:27,665 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:12:27,665 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:12:27,665 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1340954096] [2022-12-13 12:12:27,665 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1340954096] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:12:27,665 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:12:27,666 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:12:27,666 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1593271623] [2022-12-13 12:12:27,666 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:12:27,666 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 12:12:27,666 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:12:27,667 INFO L85 PathProgramCache]: Analyzing trace with hash 423599136, now seen corresponding path program 1 times [2022-12-13 12:12:27,667 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:12:27,667 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1950409926] [2022-12-13 12:12:27,667 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:12:27,667 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:12:27,676 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:12:27,692 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:12:27,693 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:12:27,693 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1950409926] [2022-12-13 12:12:27,693 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1950409926] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:12:27,693 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:12:27,693 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:12:27,693 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1006989682] [2022-12-13 12:12:27,693 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:12:27,693 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:12:27,694 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:12:27,694 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 12:12:27,694 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 12:12:27,694 INFO L87 Difference]: Start difference. First operand 120648 states and 170498 transitions. cyclomatic complexity: 49854 Second operand has 4 states, 4 states have (on average 32.0) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:12:28,394 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:12:28,394 INFO L93 Difference]: Finished difference Result 187765 states and 263464 transitions. [2022-12-13 12:12:28,394 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 187765 states and 263464 transitions. [2022-12-13 12:12:29,030 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 187184 [2022-12-13 12:12:29,545 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 187765 states to 187765 states and 263464 transitions. [2022-12-13 12:12:29,546 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 187765 [2022-12-13 12:12:29,590 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 187765 [2022-12-13 12:12:29,590 INFO L73 IsDeterministic]: Start isDeterministic. Operand 187765 states and 263464 transitions. [2022-12-13 12:12:29,639 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:12:29,639 INFO L218 hiAutomatonCegarLoop]: Abstraction has 187765 states and 263464 transitions. [2022-12-13 12:12:29,705 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 187765 states and 263464 transitions. [2022-12-13 12:12:30,638 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 187765 to 133545. [2022-12-13 12:12:30,699 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 133545 states, 133545 states have (on average 1.4071137069901531) internal successors, (187913), 133544 states have internal predecessors, (187913), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:12:30,877 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 133545 states to 133545 states and 187913 transitions. [2022-12-13 12:12:30,878 INFO L240 hiAutomatonCegarLoop]: Abstraction has 133545 states and 187913 transitions. [2022-12-13 12:12:30,878 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 12:12:30,878 INFO L428 stractBuchiCegarLoop]: Abstraction has 133545 states and 187913 transitions. [2022-12-13 12:12:30,879 INFO L335 stractBuchiCegarLoop]: ======== Iteration 25 ============ [2022-12-13 12:12:30,879 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 133545 states and 187913 transitions. [2022-12-13 12:12:31,199 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 133120 [2022-12-13 12:12:31,199 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:12:31,199 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:12:31,204 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:12:31,204 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:12:31,204 INFO L748 eck$LassoCheckResult]: Stem: 3872183#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 3872184#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 3873198#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3873199#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3873302#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 3873201#L731-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3873131#L736-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3873132#L741-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3873186#L746-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 3872119#L751-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 3872120#L756-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 3872227#L761-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 3872477#L766-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 3872401#L771-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 3872118#L776-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 3871787#L781-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3871788#L1036 assume !(0 == ~M_E~0); 3871882#L1036-2 assume !(0 == ~T1_E~0); 3872816#L1041-1 assume !(0 == ~T2_E~0); 3872817#L1046-1 assume !(0 == ~T3_E~0); 3872159#L1051-1 assume !(0 == ~T4_E~0); 3872160#L1056-1 assume !(0 == ~T5_E~0); 3872968#L1061-1 assume !(0 == ~T6_E~0); 3872054#L1066-1 assume !(0 == ~T7_E~0); 3872055#L1071-1 assume !(0 == ~T8_E~0); 3872951#L1076-1 assume !(0 == ~T9_E~0); 3871943#L1081-1 assume !(0 == ~T10_E~0); 3871944#L1086-1 assume !(0 == ~E_M~0); 3872347#L1091-1 assume !(0 == ~E_1~0); 3873210#L1096-1 assume !(0 == ~E_2~0); 3873211#L1101-1 assume !(0 == ~E_3~0); 3872416#L1106-1 assume !(0 == ~E_4~0); 3872417#L1111-1 assume !(0 == ~E_5~0); 3872593#L1116-1 assume !(0 == ~E_6~0); 3872594#L1121-1 assume !(0 == ~E_7~0); 3872405#L1126-1 assume !(0 == ~E_8~0); 3872406#L1131-1 assume !(0 == ~E_9~0); 3872699#L1136-1 assume 0 == ~E_10~0;~E_10~0 := 1; 3872826#L1141-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3873487#L514 assume !(1 == ~m_pc~0); 3873375#L514-2 is_master_triggered_~__retres1~0#1 := 0; 3872422#L525 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3872423#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3873089#L1285 assume !(0 != activate_threads_~tmp~1#1); 3873317#L1285-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3873318#L533 assume !(1 == ~t1_pc~0); 3872610#L533-2 is_transmit1_triggered_~__retres1~1#1 := 0; 3872609#L544 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3872650#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3873483#L1293 assume !(0 != activate_threads_~tmp___0~0#1); 3873482#L1293-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3873481#L552 assume !(1 == ~t2_pc~0); 3873479#L552-2 is_transmit2_triggered_~__retres1~2#1 := 0; 3873476#L563 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3872409#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3872410#L1301 assume !(0 != activate_threads_~tmp___1~0#1); 3872436#L1301-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3872437#L571 assume !(1 == ~t3_pc~0); 3872665#L571-2 is_transmit3_triggered_~__retres1~3#1 := 0; 3872753#L582 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3871785#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3871786#L1309 assume !(0 != activate_threads_~tmp___2~0#1); 3872598#L1309-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3871868#L590 assume !(1 == ~t4_pc~0); 3871869#L590-2 is_transmit4_triggered_~__retres1~4#1 := 0; 3872664#L601 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3873480#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3873274#L1317 assume !(0 != activate_threads_~tmp___3~0#1); 3872886#L1317-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3872595#L609 assume !(1 == ~t5_pc~0); 3872596#L609-2 is_transmit5_triggered_~__retres1~5#1 := 0; 3873402#L620 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3873458#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3873457#L1325 assume !(0 != activate_threads_~tmp___4~0#1); 3873456#L1325-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3873455#L628 assume !(1 == ~t6_pc~0); 3873454#L628-2 is_transmit6_triggered_~__retres1~6#1 := 0; 3873452#L639 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3873451#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3873450#L1333 assume !(0 != activate_threads_~tmp___5~0#1); 3873449#L1333-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3873448#L647 assume !(1 == ~t7_pc~0); 3873447#L647-2 is_transmit7_triggered_~__retres1~7#1 := 0; 3873446#L658 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3873445#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 3873444#L1341 assume !(0 != activate_threads_~tmp___6~0#1); 3873443#L1341-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3873442#L666 assume !(1 == ~t8_pc~0); 3873440#L666-2 is_transmit8_triggered_~__retres1~8#1 := 0; 3873439#L677 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3873438#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 3873437#L1349 assume !(0 != activate_threads_~tmp___7~0#1); 3873436#L1349-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3873285#L685 assume !(1 == ~t9_pc~0); 3873286#L685-2 is_transmit9_triggered_~__retres1~9#1 := 0; 3873119#L696 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3872470#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 3872370#L1357 assume !(0 != activate_threads_~tmp___8~0#1); 3872371#L1357-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 3873196#L704 assume !(1 == ~t10_pc~0); 3873429#L704-2 is_transmit10_triggered_~__retres1~10#1 := 0; 3873428#L715 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 3873427#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 3873426#L1365 assume !(0 != activate_threads_~tmp___9~0#1); 3873425#L1365-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3873424#L1154 assume !(1 == ~M_E~0); 3873423#L1154-2 assume !(1 == ~T1_E~0); 3873422#L1159-1 assume !(1 == ~T2_E~0); 3873421#L1164-1 assume !(1 == ~T3_E~0); 3873420#L1169-1 assume !(1 == ~T4_E~0); 3873419#L1174-1 assume !(1 == ~T5_E~0); 3873418#L1179-1 assume !(1 == ~T6_E~0); 3873417#L1184-1 assume !(1 == ~T7_E~0); 3873416#L1189-1 assume !(1 == ~T8_E~0); 3873415#L1194-1 assume !(1 == ~T9_E~0); 3873414#L1199-1 assume !(1 == ~T10_E~0); 3873413#L1204-1 assume !(1 == ~E_M~0); 3873412#L1209-1 assume !(1 == ~E_1~0); 3873411#L1214-1 assume !(1 == ~E_2~0); 3873410#L1219-1 assume !(1 == ~E_3~0); 3873409#L1224-1 assume !(1 == ~E_4~0); 3873408#L1229-1 assume !(1 == ~E_5~0); 3873407#L1234-1 assume !(1 == ~E_6~0); 3873406#L1239-1 assume !(1 == ~E_7~0); 3873405#L1244-1 assume !(1 == ~E_8~0); 3873404#L1249-1 assume !(1 == ~E_9~0); 3873403#L1254-1 assume 1 == ~E_10~0;~E_10~0 := 2; 3871909#L1259-1 assume { :end_inline_reset_delta_events } true; 3871910#L1565-2 [2022-12-13 12:12:31,205 INFO L750 eck$LassoCheckResult]: Loop: 3871910#L1565-2 assume !false; 3957482#L1566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3957478#L1011 assume !false; 3957477#L862 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 3957476#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 3957465#L851 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 3957464#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 3957462#L866 assume !(0 != eval_~tmp~0#1); 3957463#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3987583#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3987574#L1036-3 assume !(0 == ~M_E~0); 3987565#L1036-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3987557#L1041-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3987549#L1046-3 assume !(0 == ~T3_E~0); 3987540#L1051-3 assume !(0 == ~T4_E~0); 3987530#L1056-3 assume !(0 == ~T5_E~0); 3987522#L1061-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 3987514#L1066-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 3987508#L1071-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 3987501#L1076-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 3987313#L1081-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 3987310#L1086-3 assume !(0 == ~E_M~0); 3987308#L1091-3 assume !(0 == ~E_1~0); 3987306#L1096-3 assume !(0 == ~E_2~0); 3987304#L1101-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3987302#L1106-3 assume 0 == ~E_4~0;~E_4~0 := 1; 3987300#L1111-3 assume 0 == ~E_5~0;~E_5~0 := 1; 3987289#L1116-3 assume 0 == ~E_6~0;~E_6~0 := 1; 3987280#L1121-3 assume 0 == ~E_7~0;~E_7~0 := 1; 3987272#L1126-3 assume !(0 == ~E_8~0); 3987264#L1131-3 assume !(0 == ~E_9~0); 3958365#L1136-3 assume 0 == ~E_10~0;~E_10~0 := 1; 3958366#L1141-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3958341#L514-36 assume !(1 == ~m_pc~0); 3958342#L514-38 is_master_triggered_~__retres1~0#1 := 0; 3958320#L525-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3958321#is_master_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3958269#L1285-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3958270#L1285-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3975701#L533-36 assume 1 == ~t1_pc~0; 3958240#L534-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3958241#L544-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3958221#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3958222#L1293-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3958208#L1293-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3957947#L552-36 assume !(1 == ~t2_pc~0); 3957948#L552-38 is_transmit2_triggered_~__retres1~2#1 := 0; 3957941#L563-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3957942#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3957935#L1301-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3957936#L1301-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3957929#L571-36 assume !(1 == ~t3_pc~0); 3934215#L571-38 is_transmit3_triggered_~__retres1~3#1 := 0; 3957924#L582-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3957925#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3957916#L1309-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3957917#L1309-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3957906#L590-36 assume 1 == ~t4_pc~0; 3957908#L591-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3957960#L601-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3957961#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3957892#L1317-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 3957893#L1317-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3957886#L609-36 assume !(1 == ~t5_pc~0); 3957887#L609-38 is_transmit5_triggered_~__retres1~5#1 := 0; 3957880#L620-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3957881#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3957873#L1325-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 3957874#L1325-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3957866#L628-36 assume !(1 == ~t6_pc~0); 3957868#L628-38 is_transmit6_triggered_~__retres1~6#1 := 0; 3957859#L639-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3957860#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3957854#L1333-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 3957855#L1333-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3957851#L647-36 assume !(1 == ~t7_pc~0); 3957850#L647-38 is_transmit7_triggered_~__retres1~7#1 := 0; 3957849#L658-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3957848#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 3957847#L1341-36 assume !(0 != activate_threads_~tmp___6~0#1); 3957846#L1341-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3957845#L666-36 assume !(1 == ~t8_pc~0); 3957844#L666-38 is_transmit8_triggered_~__retres1~8#1 := 0; 3957842#L677-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3957841#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 3957840#L1349-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 3957839#L1349-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3957838#L685-36 assume !(1 == ~t9_pc~0); 3933365#L685-38 is_transmit9_triggered_~__retres1~9#1 := 0; 3957837#L696-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3957836#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 3957835#L1357-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 3957834#L1357-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 3957833#L704-36 assume !(1 == ~t10_pc~0); 3957832#L704-38 is_transmit10_triggered_~__retres1~10#1 := 0; 3957829#L715-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 3957828#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 3957827#L1365-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 3957826#L1365-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3957825#L1154-3 assume !(1 == ~M_E~0); 3930868#L1154-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3957824#L1159-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3957823#L1164-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3957822#L1169-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3957821#L1174-3 assume !(1 == ~T5_E~0); 3957820#L1179-3 assume !(1 == ~T6_E~0); 3957819#L1184-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 3957818#L1189-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 3957817#L1194-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 3957816#L1199-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 3957815#L1204-3 assume 1 == ~E_M~0;~E_M~0 := 2; 3957814#L1209-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3957813#L1214-3 assume !(1 == ~E_2~0); 3957812#L1219-3 assume !(1 == ~E_3~0); 3957811#L1224-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3957810#L1229-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3957809#L1234-3 assume 1 == ~E_6~0;~E_6~0 := 2; 3957808#L1239-3 assume 1 == ~E_7~0;~E_7~0 := 2; 3957807#L1244-3 assume 1 == ~E_8~0;~E_8~0 := 2; 3957806#L1249-3 assume 1 == ~E_9~0;~E_9~0 := 2; 3957804#L1254-3 assume 1 == ~E_10~0;~E_10~0 := 2; 3957802#L1259-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 3957712#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 3957709#L851-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 3957708#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 3957514#L1584 assume !(0 == start_simulation_~tmp~3#1); 3957510#L1584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 3957503#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 3957493#L851-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 3957492#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 3957488#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3957486#L1546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3957484#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 3957483#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 3871910#L1565-2 [2022-12-13 12:12:31,205 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:12:31,205 INFO L85 PathProgramCache]: Analyzing trace with hash 529853193, now seen corresponding path program 1 times [2022-12-13 12:12:31,205 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:12:31,205 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1589813833] [2022-12-13 12:12:31,205 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:12:31,206 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:12:31,215 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:12:31,253 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:12:31,253 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:12:31,253 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1589813833] [2022-12-13 12:12:31,253 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1589813833] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:12:31,253 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:12:31,253 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:12:31,254 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1458447976] [2022-12-13 12:12:31,254 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:12:31,254 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 12:12:31,254 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:12:31,254 INFO L85 PathProgramCache]: Analyzing trace with hash 423599136, now seen corresponding path program 2 times [2022-12-13 12:12:31,254 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:12:31,254 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1844225218] [2022-12-13 12:12:31,255 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:12:31,255 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:12:31,262 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:12:31,284 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:12:31,285 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:12:31,285 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1844225218] [2022-12-13 12:12:31,285 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1844225218] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:12:31,285 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:12:31,285 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:12:31,285 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1882958336] [2022-12-13 12:12:31,285 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:12:31,285 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:12:31,285 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:12:31,285 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 12:12:31,285 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 12:12:31,286 INFO L87 Difference]: Start difference. First operand 133545 states and 187913 transitions. cyclomatic complexity: 54372 Second operand has 4 states, 4 states have (on average 32.0) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:12:31,899 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:12:31,899 INFO L93 Difference]: Finished difference Result 174456 states and 243951 transitions. [2022-12-13 12:12:31,899 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 174456 states and 243951 transitions. [2022-12-13 12:12:32,369 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 174000 [2022-12-13 12:12:32,645 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 174456 states to 174456 states and 243951 transitions. [2022-12-13 12:12:32,645 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 174456 [2022-12-13 12:12:32,704 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 174456 [2022-12-13 12:12:32,704 INFO L73 IsDeterministic]: Start isDeterministic. Operand 174456 states and 243951 transitions. [2022-12-13 12:12:32,758 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:12:32,758 INFO L218 hiAutomatonCegarLoop]: Abstraction has 174456 states and 243951 transitions. [2022-12-13 12:12:32,830 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 174456 states and 243951 transitions. [2022-12-13 12:12:33,961 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 174456 to 120648. [2022-12-13 12:12:34,029 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 120648 states, 120648 states have (on average 1.4004293481864598) internal successors, (168959), 120647 states have internal predecessors, (168959), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:12:34,195 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 120648 states to 120648 states and 168959 transitions. [2022-12-13 12:12:34,195 INFO L240 hiAutomatonCegarLoop]: Abstraction has 120648 states and 168959 transitions. [2022-12-13 12:12:34,196 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 12:12:34,196 INFO L428 stractBuchiCegarLoop]: Abstraction has 120648 states and 168959 transitions. [2022-12-13 12:12:34,196 INFO L335 stractBuchiCegarLoop]: ======== Iteration 26 ============ [2022-12-13 12:12:34,196 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 120648 states and 168959 transitions. [2022-12-13 12:12:34,626 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 120320 [2022-12-13 12:12:34,626 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:12:34,626 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:12:34,629 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:12:34,629 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:12:34,630 INFO L748 eck$LassoCheckResult]: Stem: 4180198#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 4180199#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 4181191#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4181192#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4181296#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 4181195#L731-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4181130#L736-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4181131#L741-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 4181181#L746-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 4180133#L751-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 4180134#L756-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 4180242#L761-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 4180489#L766-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 4180415#L771-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 4180132#L776-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 4179798#L781-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4179799#L1036 assume !(0 == ~M_E~0); 4179894#L1036-2 assume !(0 == ~T1_E~0); 4180822#L1041-1 assume !(0 == ~T2_E~0); 4180823#L1046-1 assume !(0 == ~T3_E~0); 4180172#L1051-1 assume !(0 == ~T4_E~0); 4180173#L1056-1 assume !(0 == ~T5_E~0); 4180974#L1061-1 assume !(0 == ~T6_E~0); 4180067#L1066-1 assume !(0 == ~T7_E~0); 4180068#L1071-1 assume !(0 == ~T8_E~0); 4180956#L1076-1 assume !(0 == ~T9_E~0); 4179956#L1081-1 assume !(0 == ~T10_E~0); 4179957#L1086-1 assume !(0 == ~E_M~0); 4180362#L1091-1 assume !(0 == ~E_1~0); 4181204#L1096-1 assume !(0 == ~E_2~0); 4181205#L1101-1 assume !(0 == ~E_3~0); 4180429#L1106-1 assume !(0 == ~E_4~0); 4180430#L1111-1 assume !(0 == ~E_5~0); 4180607#L1116-1 assume !(0 == ~E_6~0); 4180608#L1121-1 assume !(0 == ~E_7~0); 4180419#L1126-1 assume !(0 == ~E_8~0); 4180420#L1131-1 assume !(0 == ~E_9~0); 4180704#L1136-1 assume !(0 == ~E_10~0); 4180833#L1141-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4181011#L514 assume !(1 == ~m_pc~0); 4181012#L514-2 is_master_triggered_~__retres1~0#1 := 0; 4180435#L525 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4180436#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4181093#L1285 assume !(0 != activate_threads_~tmp~1#1); 4181261#L1285-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4180085#L533 assume !(1 == ~t1_pc~0); 4180086#L533-2 is_transmit1_triggered_~__retres1~1#1 := 0; 4180622#L544 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4179849#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4179850#L1293 assume !(0 != activate_threads_~tmp___0~0#1); 4180859#L1293-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4180860#L552 assume !(1 == ~t2_pc~0); 4180565#L552-2 is_transmit2_triggered_~__retres1~2#1 := 0; 4180566#L563 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4180423#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4180424#L1301 assume !(0 != activate_threads_~tmp___1~0#1); 4180448#L1301-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4180449#L571 assume !(1 == ~t3_pc~0); 4180675#L571-2 is_transmit3_triggered_~__retres1~3#1 := 0; 4180756#L582 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4179796#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4179797#L1309 assume !(0 != activate_threads_~tmp___2~0#1); 4180612#L1309-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4179880#L590 assume !(1 == ~t4_pc~0); 4179881#L590-2 is_transmit4_triggered_~__retres1~4#1 := 0; 4180674#L601 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4181405#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4181266#L1317 assume !(0 != activate_threads_~tmp___3~0#1); 4180887#L1317-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4180609#L609 assume !(1 == ~t5_pc~0); 4180610#L609-2 is_transmit5_triggered_~__retres1~5#1 := 0; 4181259#L620 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4181096#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4181097#L1325 assume !(0 != activate_threads_~tmp___4~0#1); 4180602#L1325-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4180603#L628 assume !(1 == ~t6_pc~0); 4180524#L628-2 is_transmit6_triggered_~__retres1~6#1 := 0; 4180523#L639 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4180396#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4180397#L1333 assume !(0 != activate_threads_~tmp___5~0#1); 4180931#L1333-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4180932#L647 assume !(1 == ~t7_pc~0); 4181078#L647-2 is_transmit7_triggered_~__retres1~7#1 := 0; 4181107#L658 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4181108#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 4180431#L1341 assume !(0 != activate_threads_~tmp___6~0#1); 4180432#L1341-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4181326#L666 assume !(1 == ~t8_pc~0); 4180222#L666-2 is_transmit8_triggered_~__retres1~8#1 := 0; 4180223#L677 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4180447#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 4180633#L1349 assume !(0 != activate_threads_~tmp___7~0#1); 4180357#L1349-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4180358#L685 assume !(1 == ~t9_pc~0); 4181276#L685-2 is_transmit9_triggered_~__retres1~9#1 := 0; 4181118#L696 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 4180482#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 4180386#L1357 assume !(0 != activate_threads_~tmp___8~0#1); 4180387#L1357-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 4180791#L704 assume !(1 == ~t10_pc~0); 4180380#L704-2 is_transmit10_triggered_~__retres1~10#1 := 0; 4181212#L715 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 4180649#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 4179927#L1365 assume !(0 != activate_threads_~tmp___9~0#1); 4179928#L1365-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4180181#L1154 assume !(1 == ~M_E~0); 4180913#L1154-2 assume !(1 == ~T1_E~0); 4180152#L1159-1 assume !(1 == ~T2_E~0); 4180153#L1164-1 assume !(1 == ~T3_E~0); 4180631#L1169-1 assume !(1 == ~T4_E~0); 4180483#L1174-1 assume !(1 == ~T5_E~0); 4180285#L1179-1 assume !(1 == ~T6_E~0); 4180138#L1184-1 assume !(1 == ~T7_E~0); 4180139#L1189-1 assume !(1 == ~T8_E~0); 4180220#L1194-1 assume !(1 == ~T9_E~0); 4180344#L1199-1 assume !(1 == ~T10_E~0); 4180297#L1204-1 assume !(1 == ~E_M~0); 4180298#L1209-1 assume !(1 == ~E_1~0); 4180881#L1214-1 assume !(1 == ~E_2~0); 4180882#L1219-1 assume !(1 == ~E_3~0); 4181310#L1224-1 assume !(1 == ~E_4~0); 4180653#L1229-1 assume !(1 == ~E_5~0); 4180023#L1234-1 assume !(1 == ~E_6~0); 4180024#L1239-1 assume !(1 == ~E_7~0); 4180081#L1244-1 assume !(1 == ~E_8~0); 4180082#L1249-1 assume !(1 == ~E_9~0); 4180967#L1254-1 assume !(1 == ~E_10~0); 4179921#L1259-1 assume { :end_inline_reset_delta_events } true; 4179922#L1565-2 [2022-12-13 12:12:34,630 INFO L750 eck$LassoCheckResult]: Loop: 4179922#L1565-2 assume !false; 4292449#L1566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4292443#L1011 assume !false; 4292441#L862 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 4292439#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 4292426#L851 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 4292424#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 4292421#L866 assume !(0 != eval_~tmp~0#1); 4292419#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4292417#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4292415#L1036-3 assume !(0 == ~M_E~0); 4292412#L1036-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4292410#L1041-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4292408#L1046-3 assume !(0 == ~T3_E~0); 4292406#L1051-3 assume !(0 == ~T4_E~0); 4292404#L1056-3 assume !(0 == ~T5_E~0); 4292402#L1061-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 4292400#L1066-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 4292398#L1071-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 4292396#L1076-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 4292394#L1081-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 4292392#L1086-3 assume !(0 == ~E_M~0); 4292390#L1091-3 assume !(0 == ~E_1~0); 4292387#L1096-3 assume !(0 == ~E_2~0); 4292385#L1101-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4292383#L1106-3 assume 0 == ~E_4~0;~E_4~0 := 1; 4292381#L1111-3 assume 0 == ~E_5~0;~E_5~0 := 1; 4292379#L1116-3 assume 0 == ~E_6~0;~E_6~0 := 1; 4292377#L1121-3 assume 0 == ~E_7~0;~E_7~0 := 1; 4292374#L1126-3 assume !(0 == ~E_8~0); 4292372#L1131-3 assume !(0 == ~E_9~0); 4292370#L1136-3 assume !(0 == ~E_10~0); 4292368#L1141-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4292366#L514-36 assume !(1 == ~m_pc~0); 4292363#L514-38 is_master_triggered_~__retres1~0#1 := 0; 4292361#L525-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4292359#is_master_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4292357#L1285-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4291674#L1285-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4291672#L533-36 assume !(1 == ~t1_pc~0); 4291669#L533-38 is_transmit1_triggered_~__retres1~1#1 := 0; 4291664#L544-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4291660#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4291654#L1293-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4291647#L1293-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4291639#L552-36 assume !(1 == ~t2_pc~0); 4289093#L552-38 is_transmit2_triggered_~__retres1~2#1 := 0; 4291622#L563-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4291613#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4291606#L1301-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4291598#L1301-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4291592#L571-36 assume !(1 == ~t3_pc~0); 4284929#L571-38 is_transmit3_triggered_~__retres1~3#1 := 0; 4291581#L582-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4291575#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4291569#L1309-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4291565#L1309-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4291557#L590-36 assume 1 == ~t4_pc~0; 4291549#L591-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 4291542#L601-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4291535#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4291527#L1317-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 4291521#L1317-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4291473#L609-36 assume !(1 == ~t5_pc~0); 4291464#L609-38 is_transmit5_triggered_~__retres1~5#1 := 0; 4291457#L620-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4291450#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4291441#L1325-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 4291435#L1325-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4291422#L628-36 assume 1 == ~t6_pc~0; 4291413#L629-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 4291403#L639-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4291395#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4291387#L1333-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 4291348#L1333-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4268437#L647-36 assume !(1 == ~t7_pc~0); 4268435#L647-38 is_transmit7_triggered_~__retres1~7#1 := 0; 4268433#L658-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4268432#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 4268431#L1341-36 assume !(0 != activate_threads_~tmp___6~0#1); 4268430#L1341-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4268429#L666-36 assume 1 == ~t8_pc~0; 4268427#L667-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 4268426#L677-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4268414#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 4268412#L1349-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 4268410#L1349-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4268408#L685-36 assume !(1 == ~t9_pc~0); 4257688#L685-38 is_transmit9_triggered_~__retres1~9#1 := 0; 4268407#L696-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 4268406#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 4268405#L1357-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 4268404#L1357-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 4268403#L704-36 assume !(1 == ~t10_pc~0); 4268401#L704-38 is_transmit10_triggered_~__retres1~10#1 := 0; 4268400#L715-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 4268399#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 4268398#L1365-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 4268397#L1365-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4268395#L1154-3 assume !(1 == ~M_E~0); 4224658#L1154-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4268392#L1159-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4268390#L1164-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4268388#L1169-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4268386#L1174-3 assume !(1 == ~T5_E~0); 4268384#L1179-3 assume !(1 == ~T6_E~0); 4268382#L1184-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 4268380#L1189-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 4268378#L1194-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 4268376#L1199-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 4268374#L1204-3 assume 1 == ~E_M~0;~E_M~0 := 2; 4268372#L1209-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4268370#L1214-3 assume !(1 == ~E_2~0); 4268368#L1219-3 assume !(1 == ~E_3~0); 4268366#L1224-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4268364#L1229-3 assume 1 == ~E_5~0;~E_5~0 := 2; 4268362#L1234-3 assume 1 == ~E_6~0;~E_6~0 := 2; 4268360#L1239-3 assume 1 == ~E_7~0;~E_7~0 := 2; 4268358#L1244-3 assume 1 == ~E_8~0;~E_8~0 := 2; 4268356#L1249-3 assume 1 == ~E_9~0;~E_9~0 := 2; 4268354#L1254-3 assume !(1 == ~E_10~0); 4268352#L1259-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 4268329#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 4268325#L851-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 4268322#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 4224789#L1584 assume !(0 == start_simulation_~tmp~3#1); 4224790#L1584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 4292473#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 4292462#L851-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 4292460#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 4292458#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4292456#L1546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4292454#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 4292452#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 4179922#L1565-2 [2022-12-13 12:12:34,630 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:12:34,631 INFO L85 PathProgramCache]: Analyzing trace with hash -1410728759, now seen corresponding path program 1 times [2022-12-13 12:12:34,631 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:12:34,631 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1454910240] [2022-12-13 12:12:34,631 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:12:34,631 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:12:34,640 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 12:12:34,640 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 12:12:34,647 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 12:12:34,708 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 12:12:34,709 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:12:34,709 INFO L85 PathProgramCache]: Analyzing trace with hash 1443114335, now seen corresponding path program 1 times [2022-12-13 12:12:34,709 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:12:34,709 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1184898840] [2022-12-13 12:12:34,709 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:12:34,709 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:12:34,717 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:12:34,738 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:12:34,738 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:12:34,738 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1184898840] [2022-12-13 12:12:34,738 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1184898840] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:12:34,739 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:12:34,739 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:12:34,739 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [64261466] [2022-12-13 12:12:34,739 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:12:34,739 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:12:34,739 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:12:34,740 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 12:12:34,740 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 12:12:34,740 INFO L87 Difference]: Start difference. First operand 120648 states and 168959 transitions. cyclomatic complexity: 48315 Second operand has 3 states, 3 states have (on average 44.666666666666664) internal successors, (134), 3 states have internal predecessors, (134), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:12:35,011 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:12:35,012 INFO L93 Difference]: Finished difference Result 133545 states and 187139 transitions. [2022-12-13 12:12:35,012 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 133545 states and 187139 transitions. [2022-12-13 12:12:35,447 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 133120 [2022-12-13 12:12:35,902 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 133545 states to 133545 states and 187139 transitions. [2022-12-13 12:12:35,902 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 133545 [2022-12-13 12:12:35,936 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 133545 [2022-12-13 12:12:35,936 INFO L73 IsDeterministic]: Start isDeterministic. Operand 133545 states and 187139 transitions. [2022-12-13 12:12:35,963 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:12:35,963 INFO L218 hiAutomatonCegarLoop]: Abstraction has 133545 states and 187139 transitions. [2022-12-13 12:12:36,004 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 133545 states and 187139 transitions. [2022-12-13 12:12:36,680 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 133545 to 133545. [2022-12-13 12:12:36,758 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 133545 states, 133545 states have (on average 1.4013179078213336) internal successors, (187139), 133544 states have internal predecessors, (187139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:12:37,095 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 133545 states to 133545 states and 187139 transitions. [2022-12-13 12:12:37,095 INFO L240 hiAutomatonCegarLoop]: Abstraction has 133545 states and 187139 transitions. [2022-12-13 12:12:37,096 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 12:12:37,096 INFO L428 stractBuchiCegarLoop]: Abstraction has 133545 states and 187139 transitions. [2022-12-13 12:12:37,096 INFO L335 stractBuchiCegarLoop]: ======== Iteration 27 ============ [2022-12-13 12:12:37,096 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 133545 states and 187139 transitions. [2022-12-13 12:12:37,395 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 133120 [2022-12-13 12:12:37,395 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:12:37,395 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:12:37,400 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:12:37,400 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:12:37,400 INFO L748 eck$LassoCheckResult]: Stem: 4434400#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 4434401#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 4435410#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4435411#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4435522#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 4435415#L731-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4435348#L736-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4435349#L741-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 4435399#L746-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 4434332#L751-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 4434333#L756-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 4434445#L761-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 4434688#L766-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 4434613#L771-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 4434334#L776-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 4433997#L781-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4433998#L1036 assume !(0 == ~M_E~0); 4434094#L1036-2 assume !(0 == ~T1_E~0); 4435035#L1041-1 assume !(0 == ~T2_E~0); 4435036#L1046-1 assume !(0 == ~T3_E~0); 4434374#L1051-1 assume !(0 == ~T4_E~0); 4434375#L1056-1 assume !(0 == ~T5_E~0); 4435187#L1061-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 4435244#L1066-1 assume !(0 == ~T7_E~0); 4435516#L1071-1 assume !(0 == ~T8_E~0); 4435517#L1076-1 assume !(0 == ~T9_E~0); 4434156#L1081-1 assume !(0 == ~T10_E~0); 4434157#L1086-1 assume !(0 == ~E_M~0); 4435533#L1091-1 assume !(0 == ~E_1~0); 4435534#L1096-1 assume !(0 == ~E_2~0); 4435597#L1101-1 assume !(0 == ~E_3~0); 4435598#L1106-1 assume !(0 == ~E_4~0); 4434947#L1111-1 assume !(0 == ~E_5~0); 4434806#L1116-1 assume !(0 == ~E_6~0); 4434807#L1121-1 assume !(0 == ~E_7~0); 4434617#L1126-1 assume !(0 == ~E_8~0); 4434618#L1131-1 assume !(0 == ~E_9~0); 4435044#L1136-1 assume !(0 == ~E_10~0); 4435045#L1141-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4435223#L514 assume !(1 == ~m_pc~0); 4435224#L514-2 is_master_triggered_~__retres1~0#1 := 0; 4434633#L525 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4434634#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4435304#L1285 assume !(0 != activate_threads_~tmp~1#1); 4435544#L1285-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4435545#L533 assume !(1 == ~t1_pc~0); 4434824#L533-2 is_transmit1_triggered_~__retres1~1#1 := 0; 4434823#L544 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4434867#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4435694#L1293 assume !(0 != activate_threads_~tmp___0~0#1); 4435072#L1293-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4435073#L552 assume !(1 == ~t2_pc~0); 4434766#L552-2 is_transmit2_triggered_~__retres1~2#1 := 0; 4434767#L563 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4435350#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4435690#L1301 assume !(0 != activate_threads_~tmp___1~0#1); 4435689#L1301-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4435688#L571 assume !(1 == ~t3_pc~0); 4434971#L571-2 is_transmit3_triggered_~__retres1~3#1 := 0; 4434972#L582 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4435116#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4435081#L1309 assume !(0 != activate_threads_~tmp___2~0#1); 4434812#L1309-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4434080#L590 assume !(1 == ~t4_pc~0); 4434081#L590-2 is_transmit4_triggered_~__retres1~4#1 := 0; 4434881#L601 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4435680#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4435677#L1317 assume !(0 != activate_threads_~tmp___3~0#1); 4435103#L1317-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4434808#L609 assume !(1 == ~t5_pc~0); 4434809#L609-2 is_transmit5_triggered_~__retres1~5#1 := 0; 4435648#L620 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4435674#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4435673#L1325 assume !(0 != activate_threads_~tmp___4~0#1); 4435672#L1325-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4435603#L628 assume !(1 == ~t6_pc~0); 4434722#L628-2 is_transmit6_triggered_~__retres1~6#1 := 0; 4434721#L639 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4434594#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4434595#L1333 assume !(0 != activate_threads_~tmp___5~0#1); 4435669#L1333-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4435668#L647 assume !(1 == ~t7_pc~0); 4435527#L647-2 is_transmit7_triggered_~__retres1~7#1 := 0; 4435318#L658 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4435319#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 4435666#L1341 assume !(0 != activate_threads_~tmp___6~0#1); 4435581#L1341-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4435582#L666 assume !(1 == ~t8_pc~0); 4435664#L666-2 is_transmit8_triggered_~__retres1~8#1 := 0; 4435663#L677 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4435662#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 4435661#L1349 assume !(0 != activate_threads_~tmp___7~0#1); 4434558#L1349-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4434559#L685 assume !(1 == ~t9_pc~0); 4435660#L685-2 is_transmit9_triggered_~__retres1~9#1 := 0; 4435659#L696 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 4435658#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 4434584#L1357 assume !(0 != activate_threads_~tmp___8~0#1); 4434585#L1357-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 4435408#L704 assume !(1 == ~t10_pc~0); 4435471#L704-2 is_transmit10_triggered_~__retres1~10#1 := 0; 4435472#L715 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 4435655#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 4434127#L1365 assume !(0 != activate_threads_~tmp___9~0#1); 4434128#L1365-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4434383#L1154 assume !(1 == ~M_E~0); 4435129#L1154-2 assume !(1 == ~T1_E~0); 4435652#L1159-1 assume !(1 == ~T2_E~0); 4435622#L1164-1 assume !(1 == ~T3_E~0); 4434834#L1169-1 assume !(1 == ~T4_E~0); 4434682#L1174-1 assume !(1 == ~T5_E~0); 4434486#L1179-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 4434338#L1184-1 assume !(1 == ~T7_E~0); 4434339#L1189-1 assume !(1 == ~T8_E~0); 4434423#L1194-1 assume !(1 == ~T9_E~0); 4434544#L1199-1 assume !(1 == ~T10_E~0); 4434498#L1204-1 assume !(1 == ~E_M~0); 4434499#L1209-1 assume !(1 == ~E_1~0); 4435097#L1214-1 assume !(1 == ~E_2~0); 4435098#L1219-1 assume !(1 == ~E_3~0); 4435541#L1224-1 assume !(1 == ~E_4~0); 4434858#L1229-1 assume !(1 == ~E_5~0); 4434225#L1234-1 assume !(1 == ~E_6~0); 4434226#L1239-1 assume !(1 == ~E_7~0); 4434282#L1244-1 assume !(1 == ~E_8~0); 4434283#L1249-1 assume !(1 == ~E_9~0); 4435179#L1254-1 assume !(1 == ~E_10~0); 4434121#L1259-1 assume { :end_inline_reset_delta_events } true; 4434122#L1565-2 [2022-12-13 12:12:37,401 INFO L750 eck$LassoCheckResult]: Loop: 4434122#L1565-2 assume !false; 4523026#L1566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4523020#L1011 assume !false; 4523018#L862 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 4523016#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 4523004#L851 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 4523002#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 4523000#L866 assume !(0 != eval_~tmp~0#1); 4523001#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4564363#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4564361#L1036-3 assume !(0 == ~M_E~0); 4564359#L1036-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4564358#L1041-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4564357#L1046-3 assume !(0 == ~T3_E~0); 4564355#L1051-3 assume !(0 == ~T4_E~0); 4564353#L1056-3 assume !(0 == ~T5_E~0); 4564351#L1061-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 4564350#L1066-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 4564349#L1071-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 4564348#L1076-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 4564347#L1081-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 4564346#L1086-3 assume !(0 == ~E_M~0); 4564345#L1091-3 assume !(0 == ~E_1~0); 4564343#L1096-3 assume !(0 == ~E_2~0); 4564341#L1101-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4564339#L1106-3 assume 0 == ~E_4~0;~E_4~0 := 1; 4564336#L1111-3 assume 0 == ~E_5~0;~E_5~0 := 1; 4564334#L1116-3 assume 0 == ~E_6~0;~E_6~0 := 1; 4564332#L1121-3 assume 0 == ~E_7~0;~E_7~0 := 1; 4564330#L1126-3 assume !(0 == ~E_8~0); 4564328#L1131-3 assume !(0 == ~E_9~0); 4564326#L1136-3 assume !(0 == ~E_10~0); 4564323#L1141-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4564321#L514-36 assume !(1 == ~m_pc~0); 4564319#L514-38 is_master_triggered_~__retres1~0#1 := 0; 4564317#L525-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4564315#is_master_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4564314#L1285-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4564313#L1285-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4564312#L533-36 assume !(1 == ~t1_pc~0); 4564311#L533-38 is_transmit1_triggered_~__retres1~1#1 := 0; 4564309#L544-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4564308#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4564307#L1293-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4564306#L1293-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4564305#L552-36 assume !(1 == ~t2_pc~0); 4563752#L552-38 is_transmit2_triggered_~__retres1~2#1 := 0; 4564304#L563-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4564303#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4564302#L1301-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4564301#L1301-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4564300#L571-36 assume !(1 == ~t3_pc~0); 4548356#L571-38 is_transmit3_triggered_~__retres1~3#1 := 0; 4564299#L582-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4564298#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4564297#L1309-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4564296#L1309-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4564295#L590-36 assume 1 == ~t4_pc~0; 4564293#L591-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 4564292#L601-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4564291#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4564289#L1317-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 4564288#L1317-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4564287#L609-36 assume !(1 == ~t5_pc~0); 4564286#L609-38 is_transmit5_triggered_~__retres1~5#1 := 0; 4564285#L620-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4564284#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4564283#L1325-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 4564282#L1325-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4564281#L628-36 assume !(1 == ~t6_pc~0); 4564279#L628-38 is_transmit6_triggered_~__retres1~6#1 := 0; 4554809#L639-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4554810#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4554804#L1333-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 4554802#L1333-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4554801#L647-36 assume !(1 == ~t7_pc~0); 4554799#L647-38 is_transmit7_triggered_~__retres1~7#1 := 0; 4554797#L658-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4554795#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 4554793#L1341-36 assume !(0 != activate_threads_~tmp___6~0#1); 4554789#L1341-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4554787#L666-36 assume !(1 == ~t8_pc~0); 4554785#L666-38 is_transmit8_triggered_~__retres1~8#1 := 0; 4554782#L677-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4554779#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 4554777#L1349-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 4554775#L1349-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4523167#L685-36 assume !(1 == ~t9_pc~0); 4523164#L685-38 is_transmit9_triggered_~__retres1~9#1 := 0; 4523162#L696-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 4523160#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 4523158#L1357-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 4523156#L1357-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 4523153#L704-36 assume !(1 == ~t10_pc~0); 4523151#L704-38 is_transmit10_triggered_~__retres1~10#1 := 0; 4523148#L715-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 4523146#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 4523144#L1365-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 4523142#L1365-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4523140#L1154-3 assume !(1 == ~M_E~0); 4523137#L1154-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4523133#L1159-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4523131#L1164-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4523129#L1169-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4523127#L1174-3 assume !(1 == ~T5_E~0); 4523124#L1179-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 4523121#L1184-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 4523119#L1189-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 4523117#L1194-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 4523115#L1199-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 4523113#L1204-3 assume 1 == ~E_M~0;~E_M~0 := 2; 4523111#L1209-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4523109#L1214-3 assume !(1 == ~E_2~0); 4523107#L1219-3 assume !(1 == ~E_3~0); 4523104#L1224-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4523102#L1229-3 assume 1 == ~E_5~0;~E_5~0 := 2; 4523100#L1234-3 assume 1 == ~E_6~0;~E_6~0 := 2; 4523098#L1239-3 assume 1 == ~E_7~0;~E_7~0 := 2; 4523096#L1244-3 assume 1 == ~E_8~0;~E_8~0 := 2; 4523094#L1249-3 assume 1 == ~E_9~0;~E_9~0 := 2; 4523093#L1254-3 assume !(1 == ~E_10~0); 4523091#L1259-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 4523071#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 4523067#L851-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 4523065#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 4523062#L1584 assume !(0 == start_simulation_~tmp~3#1); 4523059#L1584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 4523051#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 4523040#L851-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 4523038#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 4523036#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4523034#L1546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4523032#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 4523030#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 4434122#L1565-2 [2022-12-13 12:12:37,401 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:12:37,401 INFO L85 PathProgramCache]: Analyzing trace with hash 800900745, now seen corresponding path program 1 times [2022-12-13 12:12:37,401 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:12:37,401 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [893831858] [2022-12-13 12:12:37,401 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:12:37,401 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:12:37,408 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:12:37,437 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:12:37,437 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:12:37,437 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [893831858] [2022-12-13 12:12:37,437 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [893831858] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:12:37,437 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:12:37,437 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:12:37,437 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [440602109] [2022-12-13 12:12:37,438 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:12:37,438 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 12:12:37,438 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:12:37,438 INFO L85 PathProgramCache]: Analyzing trace with hash 160775263, now seen corresponding path program 1 times [2022-12-13 12:12:37,438 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:12:37,438 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [676936158] [2022-12-13 12:12:37,439 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:12:37,439 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:12:37,445 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:12:37,460 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:12:37,460 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:12:37,460 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [676936158] [2022-12-13 12:12:37,460 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [676936158] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:12:37,460 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:12:37,460 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:12:37,460 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1783668005] [2022-12-13 12:12:37,460 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:12:37,460 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:12:37,460 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:12:37,461 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 12:12:37,461 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 12:12:37,461 INFO L87 Difference]: Start difference. First operand 133545 states and 187139 transitions. cyclomatic complexity: 53598 Second operand has 4 states, 4 states have (on average 32.0) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:12:37,861 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:12:37,861 INFO L93 Difference]: Finished difference Result 176984 states and 247179 transitions. [2022-12-13 12:12:37,861 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 176984 states and 247179 transitions. [2022-12-13 12:12:38,615 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 176544 [2022-12-13 12:12:38,920 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 176984 states to 176984 states and 247179 transitions. [2022-12-13 12:12:38,920 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 176984 [2022-12-13 12:12:38,983 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 176984 [2022-12-13 12:12:38,983 INFO L73 IsDeterministic]: Start isDeterministic. Operand 176984 states and 247179 transitions. [2022-12-13 12:12:39,054 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:12:39,055 INFO L218 hiAutomatonCegarLoop]: Abstraction has 176984 states and 247179 transitions. [2022-12-13 12:12:39,122 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 176984 states and 247179 transitions. [2022-12-13 12:12:39,987 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 176984 to 120648. [2022-12-13 12:12:40,056 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 120648 states, 120648 states have (on average 1.3993601220078244) internal successors, (168830), 120647 states have internal predecessors, (168830), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:12:40,217 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 120648 states to 120648 states and 168830 transitions. [2022-12-13 12:12:40,218 INFO L240 hiAutomatonCegarLoop]: Abstraction has 120648 states and 168830 transitions. [2022-12-13 12:12:40,218 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 12:12:40,219 INFO L428 stractBuchiCegarLoop]: Abstraction has 120648 states and 168830 transitions. [2022-12-13 12:12:40,219 INFO L335 stractBuchiCegarLoop]: ======== Iteration 28 ============ [2022-12-13 12:12:40,219 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 120648 states and 168830 transitions. [2022-12-13 12:12:40,521 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 120320 [2022-12-13 12:12:40,521 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:12:40,521 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:12:40,525 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:12:40,525 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:12:40,525 INFO L748 eck$LassoCheckResult]: Stem: 4744938#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 4744939#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 4745924#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4745925#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4746032#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 4745929#L731-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4745866#L736-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4745867#L741-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 4745914#L746-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 4744871#L751-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 4744872#L756-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 4744982#L761-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 4745228#L766-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 4745154#L771-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 4744873#L776-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 4744536#L781-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4744537#L1036 assume !(0 == ~M_E~0); 4744632#L1036-2 assume !(0 == ~T1_E~0); 4745562#L1041-1 assume !(0 == ~T2_E~0); 4745563#L1046-1 assume !(0 == ~T3_E~0); 4744914#L1051-1 assume !(0 == ~T4_E~0); 4744915#L1056-1 assume !(0 == ~T5_E~0); 4745717#L1061-1 assume !(0 == ~T6_E~0); 4744805#L1066-1 assume !(0 == ~T7_E~0); 4744806#L1071-1 assume !(0 == ~T8_E~0); 4745700#L1076-1 assume !(0 == ~T9_E~0); 4744694#L1081-1 assume !(0 == ~T10_E~0); 4744695#L1086-1 assume !(0 == ~E_M~0); 4745101#L1091-1 assume !(0 == ~E_1~0); 4745939#L1096-1 assume !(0 == ~E_2~0); 4745940#L1101-1 assume !(0 == ~E_3~0); 4745168#L1106-1 assume !(0 == ~E_4~0); 4745169#L1111-1 assume !(0 == ~E_5~0); 4745342#L1116-1 assume !(0 == ~E_6~0); 4745343#L1121-1 assume !(0 == ~E_7~0); 4745158#L1126-1 assume !(0 == ~E_8~0); 4745159#L1131-1 assume !(0 == ~E_9~0); 4745443#L1136-1 assume !(0 == ~E_10~0); 4745573#L1141-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4745755#L514 assume !(1 == ~m_pc~0); 4745756#L514-2 is_master_triggered_~__retres1~0#1 := 0; 4745174#L525 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4745175#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4745829#L1285 assume !(0 != activate_threads_~tmp~1#1); 4745999#L1285-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4744825#L533 assume !(1 == ~t1_pc~0); 4744826#L533-2 is_transmit1_triggered_~__retres1~1#1 := 0; 4745357#L544 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4744589#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4744590#L1293 assume !(0 != activate_threads_~tmp___0~0#1); 4745605#L1293-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4745606#L552 assume !(1 == ~t2_pc~0); 4745303#L552-2 is_transmit2_triggered_~__retres1~2#1 := 0; 4745304#L563 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4745162#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4745163#L1301 assume !(0 != activate_threads_~tmp___1~0#1); 4745191#L1301-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4745192#L571 assume !(1 == ~t3_pc~0); 4745411#L571-2 is_transmit3_triggered_~__retres1~3#1 := 0; 4745497#L582 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4744534#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4744535#L1309 assume !(0 != activate_threads_~tmp___2~0#1); 4745346#L1309-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4744617#L590 assume !(1 == ~t4_pc~0); 4744618#L590-2 is_transmit4_triggered_~__retres1~4#1 := 0; 4745409#L601 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4744712#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4744713#L1317 assume !(0 != activate_threads_~tmp___3~0#1); 4745636#L1317-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4745344#L609 assume !(1 == ~t5_pc~0); 4745345#L609-2 is_transmit5_triggered_~__retres1~5#1 := 0; 4745994#L620 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4745831#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4745832#L1325 assume !(0 != activate_threads_~tmp___4~0#1); 4745337#L1325-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4745338#L628 assume !(1 == ~t6_pc~0); 4745262#L628-2 is_transmit6_triggered_~__retres1~6#1 := 0; 4745261#L639 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4745138#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4745139#L1333 assume !(0 != activate_threads_~tmp___5~0#1); 4745677#L1333-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4745678#L647 assume !(1 == ~t7_pc~0); 4745811#L647-2 is_transmit7_triggered_~__retres1~7#1 := 0; 4745842#L658 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4745843#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 4745170#L1341 assume !(0 != activate_threads_~tmp___6~0#1); 4745171#L1341-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4746060#L666 assume !(1 == ~t8_pc~0); 4744962#L666-2 is_transmit8_triggered_~__retres1~8#1 := 0; 4744963#L677 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4745186#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 4745370#L1349 assume !(0 != activate_threads_~tmp___7~0#1); 4745097#L1349-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4745098#L685 assume !(1 == ~t9_pc~0); 4746010#L685-2 is_transmit9_triggered_~__retres1~9#1 := 0; 4745851#L696 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 4745221#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 4745124#L1357 assume !(0 != activate_threads_~tmp___8~0#1); 4745125#L1357-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 4745532#L704 assume !(1 == ~t10_pc~0); 4745118#L704-2 is_transmit10_triggered_~__retres1~10#1 := 0; 4745945#L715 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 4745383#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 4744665#L1365 assume !(0 != activate_threads_~tmp___9~0#1); 4744666#L1365-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4744921#L1154 assume !(1 == ~M_E~0); 4745660#L1154-2 assume !(1 == ~T1_E~0); 4744891#L1159-1 assume !(1 == ~T2_E~0); 4744892#L1164-1 assume !(1 == ~T3_E~0); 4745366#L1169-1 assume !(1 == ~T4_E~0); 4745223#L1174-1 assume !(1 == ~T5_E~0); 4745026#L1179-1 assume !(1 == ~T6_E~0); 4744877#L1184-1 assume !(1 == ~T7_E~0); 4744878#L1189-1 assume !(1 == ~T8_E~0); 4744960#L1194-1 assume !(1 == ~T9_E~0); 4745084#L1199-1 assume !(1 == ~T10_E~0); 4745038#L1204-1 assume !(1 == ~E_M~0); 4745039#L1209-1 assume !(1 == ~E_1~0); 4745630#L1214-1 assume !(1 == ~E_2~0); 4745631#L1219-1 assume !(1 == ~E_3~0); 4746040#L1224-1 assume !(1 == ~E_4~0); 4745388#L1229-1 assume !(1 == ~E_5~0); 4744761#L1234-1 assume !(1 == ~E_6~0); 4744762#L1239-1 assume !(1 == ~E_7~0); 4744819#L1244-1 assume !(1 == ~E_8~0); 4744820#L1249-1 assume !(1 == ~E_9~0); 4745709#L1254-1 assume !(1 == ~E_10~0); 4744662#L1259-1 assume { :end_inline_reset_delta_events } true; 4744663#L1565-2 [2022-12-13 12:12:40,526 INFO L750 eck$LassoCheckResult]: Loop: 4744663#L1565-2 assume !false; 4857229#L1566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4857220#L1011 assume !false; 4857215#L862 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 4857213#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 4857202#L851 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 4857201#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 4857198#L866 assume !(0 != eval_~tmp~0#1); 4857197#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4857196#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4857194#L1036-3 assume !(0 == ~M_E~0); 4857192#L1036-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4857190#L1041-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4857188#L1046-3 assume !(0 == ~T3_E~0); 4857187#L1051-3 assume !(0 == ~T4_E~0); 4857183#L1056-3 assume !(0 == ~T5_E~0); 4857181#L1061-3 assume !(0 == ~T6_E~0); 4857179#L1066-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 4857177#L1071-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 4857174#L1076-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 4857172#L1081-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 4857170#L1086-3 assume !(0 == ~E_M~0); 4857167#L1091-3 assume !(0 == ~E_1~0); 4857165#L1096-3 assume !(0 == ~E_2~0); 4857163#L1101-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4857161#L1106-3 assume 0 == ~E_4~0;~E_4~0 := 1; 4857159#L1111-3 assume 0 == ~E_5~0;~E_5~0 := 1; 4857157#L1116-3 assume 0 == ~E_6~0;~E_6~0 := 1; 4857154#L1121-3 assume 0 == ~E_7~0;~E_7~0 := 1; 4857152#L1126-3 assume !(0 == ~E_8~0); 4857150#L1131-3 assume !(0 == ~E_9~0); 4857148#L1136-3 assume !(0 == ~E_10~0); 4857146#L1141-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4857144#L514-36 assume !(1 == ~m_pc~0); 4857141#L514-38 is_master_triggered_~__retres1~0#1 := 0; 4857139#L525-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4857137#is_master_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4857135#L1285-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4857133#L1285-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4857131#L533-36 assume !(1 == ~t1_pc~0); 4857128#L533-38 is_transmit1_triggered_~__retres1~1#1 := 0; 4857125#L544-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4857122#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4857121#L1293-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4857120#L1293-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4857118#L552-36 assume !(1 == ~t2_pc~0); 4845588#L552-38 is_transmit2_triggered_~__retres1~2#1 := 0; 4854441#L563-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4854440#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4854439#L1301-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4854437#L1301-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4852938#L571-36 assume !(1 == ~t3_pc~0); 4852931#L571-38 is_transmit3_triggered_~__retres1~3#1 := 0; 4852912#L582-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4852909#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4852907#L1309-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4852905#L1309-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4852903#L590-36 assume 1 == ~t4_pc~0; 4852900#L591-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 4852898#L601-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4852887#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4852859#L1317-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 4852853#L1317-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4852845#L609-36 assume !(1 == ~t5_pc~0); 4852838#L609-38 is_transmit5_triggered_~__retres1~5#1 := 0; 4852832#L620-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4852685#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4852178#L1325-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 4852177#L1325-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4852176#L628-36 assume !(1 == ~t6_pc~0); 4852174#L628-38 is_transmit6_triggered_~__retres1~6#1 := 0; 4852173#L639-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4852171#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4852169#L1333-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 4852167#L1333-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4852165#L647-36 assume !(1 == ~t7_pc~0); 4833475#L647-38 is_transmit7_triggered_~__retres1~7#1 := 0; 4852151#L658-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4852126#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 4852123#L1341-36 assume !(0 != activate_threads_~tmp___6~0#1); 4852121#L1341-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4852119#L666-36 assume 1 == ~t8_pc~0; 4852114#L667-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 4852076#L677-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4851836#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 4851742#L1349-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 4851737#L1349-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4816776#L685-36 assume !(1 == ~t9_pc~0); 4816774#L685-38 is_transmit9_triggered_~__retres1~9#1 := 0; 4816772#L696-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 4816769#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 4816768#L1357-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 4816765#L1357-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 4816763#L704-36 assume !(1 == ~t10_pc~0); 4816760#L704-38 is_transmit10_triggered_~__retres1~10#1 := 0; 4816758#L715-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 4816756#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 4816754#L1365-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 4816751#L1365-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4816749#L1154-3 assume !(1 == ~M_E~0); 4787455#L1154-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4816746#L1159-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4816744#L1164-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4816742#L1169-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4816741#L1174-3 assume !(1 == ~T5_E~0); 4816739#L1179-3 assume !(1 == ~T6_E~0); 4816737#L1184-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 4816735#L1189-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 4816733#L1194-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 4816730#L1199-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 4816728#L1204-3 assume 1 == ~E_M~0;~E_M~0 := 2; 4816726#L1209-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4816724#L1214-3 assume !(1 == ~E_2~0); 4816722#L1219-3 assume !(1 == ~E_3~0); 4816720#L1224-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4816718#L1229-3 assume 1 == ~E_5~0;~E_5~0 := 2; 4816716#L1234-3 assume 1 == ~E_6~0;~E_6~0 := 2; 4816714#L1239-3 assume 1 == ~E_7~0;~E_7~0 := 2; 4816712#L1244-3 assume 1 == ~E_8~0;~E_8~0 := 2; 4816710#L1249-3 assume 1 == ~E_9~0;~E_9~0 := 2; 4816708#L1254-3 assume !(1 == ~E_10~0); 4816705#L1259-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 4816687#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 4816683#L851-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 4816681#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 4796721#L1584 assume !(0 == start_simulation_~tmp~3#1); 4796722#L1584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 4857447#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 4857428#L851-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 4857417#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 4857264#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4857260#L1546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4857255#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 4857244#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 4744663#L1565-2 [2022-12-13 12:12:40,526 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:12:40,526 INFO L85 PathProgramCache]: Analyzing trace with hash -1410728759, now seen corresponding path program 2 times [2022-12-13 12:12:40,526 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:12:40,526 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1386976277] [2022-12-13 12:12:40,526 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:12:40,526 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:12:40,533 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 12:12:40,534 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 12:12:40,539 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 12:12:40,562 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 12:12:40,562 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:12:40,562 INFO L85 PathProgramCache]: Analyzing trace with hash -21718562, now seen corresponding path program 1 times [2022-12-13 12:12:40,562 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:12:40,562 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1477540697] [2022-12-13 12:12:40,562 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:12:40,563 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:12:40,568 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:12:40,582 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:12:40,582 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:12:40,582 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1477540697] [2022-12-13 12:12:40,582 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1477540697] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:12:40,583 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:12:40,583 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:12:40,583 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1213419681] [2022-12-13 12:12:40,583 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:12:40,583 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:12:40,583 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:12:40,583 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 12:12:40,583 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 12:12:40,583 INFO L87 Difference]: Start difference. First operand 120648 states and 168830 transitions. cyclomatic complexity: 48186 Second operand has 3 states, 3 states have (on average 44.666666666666664) internal successors, (134), 3 states have internal predecessors, (134), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:12:41,245 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:12:41,245 INFO L93 Difference]: Finished difference Result 225113 states and 312403 transitions. [2022-12-13 12:12:41,245 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 225113 states and 312403 transitions. [2022-12-13 12:12:42,103 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 224496 [2022-12-13 12:12:42,732 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 225113 states to 225113 states and 312403 transitions. [2022-12-13 12:12:42,732 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 225113 [2022-12-13 12:12:42,818 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 225113 [2022-12-13 12:12:42,819 INFO L73 IsDeterministic]: Start isDeterministic. Operand 225113 states and 312403 transitions. [2022-12-13 12:12:42,895 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:12:42,896 INFO L218 hiAutomatonCegarLoop]: Abstraction has 225113 states and 312403 transitions. [2022-12-13 12:12:43,001 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 225113 states and 312403 transitions. [2022-12-13 12:12:44,448 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 225113 to 225049. [2022-12-13 12:12:44,581 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 225049 states, 225049 states have (on average 1.3878710858524144) internal successors, (312339), 225048 states have internal predecessors, (312339), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:12:45,088 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 225049 states to 225049 states and 312339 transitions. [2022-12-13 12:12:45,088 INFO L240 hiAutomatonCegarLoop]: Abstraction has 225049 states and 312339 transitions. [2022-12-13 12:12:45,088 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 12:12:45,089 INFO L428 stractBuchiCegarLoop]: Abstraction has 225049 states and 312339 transitions. [2022-12-13 12:12:45,089 INFO L335 stractBuchiCegarLoop]: ======== Iteration 29 ============ [2022-12-13 12:12:45,089 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 225049 states and 312339 transitions. [2022-12-13 12:12:45,517 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 224432 [2022-12-13 12:12:45,517 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:12:45,517 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:12:45,522 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:12:45,522 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:12:45,522 INFO L748 eck$LassoCheckResult]: Stem: 5090703#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 5090704#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 5091720#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5091721#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5091830#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 5091726#L731-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5091659#L736-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5091660#L741-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 5091708#L746-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 5090634#L751-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 5090635#L756-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 5090747#L761-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 5090997#L766-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 5090918#L771-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 5090636#L776-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 5090303#L781-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5090304#L1036 assume !(0 == ~M_E~0); 5090397#L1036-2 assume !(0 == ~T1_E~0); 5091338#L1041-1 assume !(0 == ~T2_E~0); 5091339#L1046-1 assume !(0 == ~T3_E~0); 5090678#L1051-1 assume !(0 == ~T4_E~0); 5090679#L1056-1 assume !(0 == ~T5_E~0); 5091494#L1061-1 assume !(0 == ~T6_E~0); 5090570#L1066-1 assume !(0 == ~T7_E~0); 5090571#L1071-1 assume !(0 == ~T8_E~0); 5091475#L1076-1 assume !(0 == ~T9_E~0); 5090460#L1081-1 assume !(0 == ~T10_E~0); 5090461#L1086-1 assume !(0 == ~E_M~0); 5090865#L1091-1 assume !(0 == ~E_1~0); 5091735#L1096-1 assume !(0 == ~E_2~0); 5091736#L1101-1 assume 0 == ~E_3~0;~E_3~0 := 1; 5091904#L1106-1 assume !(0 == ~E_4~0); 5091251#L1111-1 assume !(0 == ~E_5~0); 5091110#L1116-1 assume !(0 == ~E_6~0); 5091111#L1121-1 assume !(0 == ~E_7~0); 5090922#L1126-1 assume !(0 == ~E_8~0); 5090923#L1131-1 assume !(0 == ~E_9~0); 5091345#L1136-1 assume !(0 == ~E_10~0); 5091346#L1141-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5091533#L514 assume !(1 == ~m_pc~0); 5091534#L514-2 is_master_triggered_~__retres1~0#1 := 0; 5090938#L525 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5090939#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 5091611#L1285 assume !(0 != activate_threads_~tmp~1#1); 5091848#L1285-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5091849#L533 assume !(1 == ~t1_pc~0); 5091128#L533-2 is_transmit1_triggered_~__retres1~1#1 := 0; 5091127#L544 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5091171#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 5092005#L1293 assume !(0 != activate_threads_~tmp___0~0#1); 5091376#L1293-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5091377#L552 assume !(1 == ~t2_pc~0); 5091073#L552-2 is_transmit2_triggered_~__retres1~2#1 := 0; 5091074#L563 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5091661#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 5092001#L1301 assume !(0 != activate_threads_~tmp___1~0#1); 5092000#L1301-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5091999#L571 assume !(1 == ~t3_pc~0); 5091273#L571-2 is_transmit3_triggered_~__retres1~3#1 := 0; 5091274#L582 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5091422#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 5091386#L1309 assume !(0 != activate_threads_~tmp___2~0#1); 5091114#L1309-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5091115#L590 assume !(1 == ~t4_pc~0); 5091995#L590-2 is_transmit4_triggered_~__retres1~4#1 := 0; 5091993#L601 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5091990#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 5091802#L1317 assume !(0 != activate_threads_~tmp___3~0#1); 5091803#L1317-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5091988#L609 assume !(1 == ~t5_pc~0); 5091987#L609-2 is_transmit5_triggered_~__retres1~5#1 := 0; 5091792#L620 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5091614#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 5091615#L1325 assume !(0 != activate_threads_~tmp___4~0#1); 5091105#L1325-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 5091106#L628 assume !(1 == ~t6_pc~0); 5091983#L628-2 is_transmit6_triggered_~__retres1~6#1 := 0; 5091898#L639 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5091899#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 5091842#L1333 assume !(0 != activate_threads_~tmp___5~0#1); 5091450#L1333-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5091451#L647 assume !(1 == ~t7_pc~0); 5091593#L647-2 is_transmit7_triggered_~__retres1~7#1 := 0; 5091979#L658 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5091912#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 5090934#L1341 assume !(0 != activate_threads_~tmp___6~0#1); 5090935#L1341-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 5091866#L666 assume !(1 == ~t8_pc~0); 5090726#L666-2 is_transmit8_triggered_~__retres1~8#1 := 0; 5090727#L677 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 5090951#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 5091139#L1349 assume !(0 != activate_threads_~tmp___7~0#1); 5091140#L1349-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 5091810#L685 assume !(1 == ~t9_pc~0); 5091811#L685-2 is_transmit9_triggered_~__retres1~9#1 := 0; 5091645#L696 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 5090990#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 5090991#L1357 assume !(0 != activate_threads_~tmp___8~0#1); 5091969#L1357-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 5091306#L704 assume !(1 == ~t10_pc~0); 5090881#L704-2 is_transmit10_triggered_~__retres1~10#1 := 0; 5091744#L715 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 5091156#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 5091157#L1365 assume !(0 != activate_threads_~tmp___9~0#1); 5091965#L1365-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5091964#L1154 assume !(1 == ~M_E~0); 5091841#L1154-2 assume !(1 == ~T1_E~0); 5090656#L1159-1 assume !(1 == ~T2_E~0); 5090657#L1164-1 assume !(1 == ~T3_E~0); 5091962#L1169-1 assume !(1 == ~T4_E~0); 5091961#L1174-1 assume !(1 == ~T5_E~0); 5091960#L1179-1 assume !(1 == ~T6_E~0); 5091959#L1184-1 assume !(1 == ~T7_E~0); 5091958#L1189-1 assume !(1 == ~T8_E~0); 5090847#L1194-1 assume !(1 == ~T9_E~0); 5090848#L1199-1 assume !(1 == ~T10_E~0); 5091943#L1204-1 assume !(1 == ~E_M~0); 5091861#L1209-1 assume !(1 == ~E_1~0); 5091400#L1214-1 assume !(1 == ~E_2~0); 5091401#L1219-1 assume 1 == ~E_3~0;~E_3~0 := 2; 5091844#L1224-1 assume !(1 == ~E_4~0); 5091161#L1229-1 assume !(1 == ~E_5~0); 5090527#L1234-1 assume !(1 == ~E_6~0); 5090528#L1239-1 assume !(1 == ~E_7~0); 5090584#L1244-1 assume !(1 == ~E_8~0); 5090585#L1249-1 assume !(1 == ~E_9~0); 5091486#L1254-1 assume !(1 == ~E_10~0); 5090425#L1259-1 assume { :end_inline_reset_delta_events } true; 5090426#L1565-2 [2022-12-13 12:12:45,523 INFO L750 eck$LassoCheckResult]: Loop: 5090426#L1565-2 assume !false; 5161381#L1566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5161376#L1011 assume !false; 5161373#L862 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 5161371#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 5161355#L851 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 5161349#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 5161343#L866 assume !(0 != eval_~tmp~0#1); 5161344#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5185701#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5185699#L1036-3 assume !(0 == ~M_E~0); 5185697#L1036-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 5185695#L1041-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 5185692#L1046-3 assume !(0 == ~T3_E~0); 5185690#L1051-3 assume !(0 == ~T4_E~0); 5185688#L1056-3 assume !(0 == ~T5_E~0); 5185686#L1061-3 assume !(0 == ~T6_E~0); 5185684#L1066-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 5185683#L1071-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 5185682#L1076-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 5185681#L1081-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 5185512#L1086-3 assume !(0 == ~E_M~0); 5185509#L1091-3 assume !(0 == ~E_1~0); 5185507#L1096-3 assume !(0 == ~E_2~0); 5185503#L1101-3 assume !(0 == ~E_3~0); 5185499#L1106-3 assume 0 == ~E_4~0;~E_4~0 := 1; 5185500#L1111-3 assume 0 == ~E_5~0;~E_5~0 := 1; 5185491#L1116-3 assume 0 == ~E_6~0;~E_6~0 := 1; 5185492#L1121-3 assume 0 == ~E_7~0;~E_7~0 := 1; 5185480#L1126-3 assume !(0 == ~E_8~0); 5185481#L1131-3 assume !(0 == ~E_9~0); 5185472#L1136-3 assume !(0 == ~E_10~0); 5185473#L1141-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5185463#L514-36 assume !(1 == ~m_pc~0); 5185464#L514-38 is_master_triggered_~__retres1~0#1 := 0; 5185455#L525-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5185456#is_master_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 5185447#L1285-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 5185448#L1285-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5185438#L533-36 assume 1 == ~t1_pc~0; 5185439#L534-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 5185427#L544-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5185428#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 5185419#L1293-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 5185420#L1293-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5165225#L552-36 assume !(1 == ~t2_pc~0); 5165221#L552-38 is_transmit2_triggered_~__retres1~2#1 := 0; 5165217#L563-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5165214#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 5165211#L1301-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 5165208#L1301-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5160196#L571-36 assume !(1 == ~t3_pc~0); 5160195#L571-38 is_transmit3_triggered_~__retres1~3#1 := 0; 5160194#L582-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5160193#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 5160192#L1309-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 5160191#L1309-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5160190#L590-36 assume !(1 == ~t4_pc~0); 5160188#L590-38 is_transmit4_triggered_~__retres1~4#1 := 0; 5160186#L601-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5160184#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 5160183#L1317-36 assume !(0 != activate_threads_~tmp___3~0#1); 5160181#L1317-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5160179#L609-36 assume !(1 == ~t5_pc~0); 5160178#L609-38 is_transmit5_triggered_~__retres1~5#1 := 0; 5160177#L620-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5160175#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 5160174#L1325-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 5160173#L1325-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 5160172#L628-36 assume !(1 == ~t6_pc~0); 5160170#L628-38 is_transmit6_triggered_~__retres1~6#1 := 0; 5160169#L639-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5160168#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 5160167#L1333-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 5160166#L1333-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5160165#L647-36 assume !(1 == ~t7_pc~0); 5158803#L647-38 is_transmit7_triggered_~__retres1~7#1 := 0; 5160163#L658-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5160162#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 5160161#L1341-36 assume !(0 != activate_threads_~tmp___6~0#1); 5160159#L1341-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 5160158#L666-36 assume 1 == ~t8_pc~0; 5160156#L667-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 5160155#L677-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 5160153#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 5160151#L1349-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 5160149#L1349-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 5160147#L685-36 assume !(1 == ~t9_pc~0); 5151808#L685-38 is_transmit9_triggered_~__retres1~9#1 := 0; 5160144#L696-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 5160143#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 5160139#L1357-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 5160137#L1357-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 5160135#L704-36 assume !(1 == ~t10_pc~0); 5160132#L704-38 is_transmit10_triggered_~__retres1~10#1 := 0; 5160129#L715-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 5160127#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 5160125#L1365-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 5160123#L1365-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5160121#L1154-3 assume !(1 == ~M_E~0); 5159367#L1154-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5160118#L1159-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5160116#L1164-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 5160114#L1169-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5160111#L1174-3 assume !(1 == ~T5_E~0); 5160109#L1179-3 assume !(1 == ~T6_E~0); 5160107#L1184-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 5160105#L1189-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 5160103#L1194-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 5160101#L1199-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 5160100#L1204-3 assume 1 == ~E_M~0;~E_M~0 := 2; 5160098#L1209-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5160096#L1214-3 assume !(1 == ~E_2~0); 5160029#L1219-3 assume !(1 == ~E_3~0); 5160027#L1224-3 assume 1 == ~E_4~0;~E_4~0 := 2; 5160024#L1229-3 assume 1 == ~E_5~0;~E_5~0 := 2; 5160022#L1234-3 assume 1 == ~E_6~0;~E_6~0 := 2; 5160020#L1239-3 assume 1 == ~E_7~0;~E_7~0 := 2; 5160018#L1244-3 assume 1 == ~E_8~0;~E_8~0 := 2; 5160016#L1249-3 assume 1 == ~E_9~0;~E_9~0 := 2; 5160014#L1254-3 assume !(1 == ~E_10~0); 5160012#L1259-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 5159990#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 5159986#L851-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 5159984#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 5159981#L1584 assume !(0 == start_simulation_~tmp~3#1); 5159982#L1584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 5161518#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 5161506#L851-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 5161503#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 5161500#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5161497#L1546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5161492#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 5161491#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 5090426#L1565-2 [2022-12-13 12:12:45,523 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:12:45,523 INFO L85 PathProgramCache]: Analyzing trace with hash -184383863, now seen corresponding path program 1 times [2022-12-13 12:12:45,523 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:12:45,523 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1662916095] [2022-12-13 12:12:45,523 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:12:45,523 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:12:45,529 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:12:45,555 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:12:45,555 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:12:45,555 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1662916095] [2022-12-13 12:12:45,555 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1662916095] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:12:45,555 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:12:45,555 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:12:45,555 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1098444720] [2022-12-13 12:12:45,556 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:12:45,556 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 12:12:45,556 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:12:45,556 INFO L85 PathProgramCache]: Analyzing trace with hash -1484381858, now seen corresponding path program 1 times [2022-12-13 12:12:45,556 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:12:45,556 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [273789167] [2022-12-13 12:12:45,556 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:12:45,557 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:12:45,563 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:12:45,594 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:12:45,594 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:12:45,594 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [273789167] [2022-12-13 12:12:45,594 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [273789167] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:12:45,594 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:12:45,594 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-12-13 12:12:45,594 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2018154654] [2022-12-13 12:12:45,594 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:12:45,595 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:12:45,595 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:12:45,595 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 12:12:45,595 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 12:12:45,595 INFO L87 Difference]: Start difference. First operand 225049 states and 312339 transitions. cyclomatic complexity: 87294 Second operand has 4 states, 4 states have (on average 32.0) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:12:46,493 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:12:46,493 INFO L93 Difference]: Finished difference Result 329600 states and 456667 transitions. [2022-12-13 12:12:46,493 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 329600 states and 456667 transitions. [2022-12-13 12:12:47,676 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 321392 [2022-12-13 12:12:48,211 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 329600 states to 329600 states and 456667 transitions. [2022-12-13 12:12:48,211 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 329600 [2022-12-13 12:12:48,332 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 329600 [2022-12-13 12:12:48,332 INFO L73 IsDeterministic]: Start isDeterministic. Operand 329600 states and 456667 transitions. [2022-12-13 12:12:48,443 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:12:48,443 INFO L218 hiAutomatonCegarLoop]: Abstraction has 329600 states and 456667 transitions. [2022-12-13 12:12:48,593 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 329600 states and 456667 transitions. [2022-12-13 12:12:50,385 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 329600 to 224952. [2022-12-13 12:12:50,471 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 224952 states, 224952 states have (on average 1.3873048472563037) internal successors, (312077), 224951 states have internal predecessors, (312077), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:12:50,797 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 224952 states to 224952 states and 312077 transitions. [2022-12-13 12:12:50,797 INFO L240 hiAutomatonCegarLoop]: Abstraction has 224952 states and 312077 transitions. [2022-12-13 12:12:50,798 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 12:12:50,799 INFO L428 stractBuchiCegarLoop]: Abstraction has 224952 states and 312077 transitions. [2022-12-13 12:12:50,799 INFO L335 stractBuchiCegarLoop]: ======== Iteration 30 ============ [2022-12-13 12:12:50,799 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 224952 states and 312077 transitions. [2022-12-13 12:12:51,376 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 224432 [2022-12-13 12:12:51,377 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:12:51,377 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:12:51,383 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:12:51,383 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:12:51,383 INFO L748 eck$LassoCheckResult]: Stem: 5645368#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 5645369#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 5646377#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5646378#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5646483#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 5646382#L731-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5646313#L736-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5646314#L741-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 5646366#L746-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 5645299#L751-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 5645300#L756-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 5645410#L761-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 5645657#L766-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 5645580#L771-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 5645301#L776-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 5644964#L781-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5644965#L1036 assume !(0 == ~M_E~0); 5645059#L1036-2 assume !(0 == ~T1_E~0); 5645991#L1041-1 assume !(0 == ~T2_E~0); 5645992#L1046-1 assume !(0 == ~T3_E~0); 5645343#L1051-1 assume !(0 == ~T4_E~0); 5645344#L1056-1 assume !(0 == ~T5_E~0); 5646146#L1061-1 assume !(0 == ~T6_E~0); 5645233#L1066-1 assume !(0 == ~T7_E~0); 5645234#L1071-1 assume !(0 == ~T8_E~0); 5646128#L1076-1 assume !(0 == ~T9_E~0); 5645122#L1081-1 assume !(0 == ~T10_E~0); 5645123#L1086-1 assume !(0 == ~E_M~0); 5645527#L1091-1 assume !(0 == ~E_1~0); 5646393#L1096-1 assume !(0 == ~E_2~0); 5646394#L1101-1 assume !(0 == ~E_3~0); 5645594#L1106-1 assume !(0 == ~E_4~0); 5645595#L1111-1 assume !(0 == ~E_5~0); 5645772#L1116-1 assume !(0 == ~E_6~0); 5645773#L1121-1 assume !(0 == ~E_7~0); 5645584#L1126-1 assume !(0 == ~E_8~0); 5645585#L1131-1 assume !(0 == ~E_9~0); 5645872#L1136-1 assume !(0 == ~E_10~0); 5645997#L1141-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5646182#L514 assume !(1 == ~m_pc~0); 5646183#L514-2 is_master_triggered_~__retres1~0#1 := 0; 5645600#L525 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5645601#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 5646268#L1285 assume !(0 != activate_threads_~tmp~1#1); 5646450#L1285-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5645251#L533 assume !(1 == ~t1_pc~0); 5645252#L533-2 is_transmit1_triggered_~__retres1~1#1 := 0; 5645788#L544 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5645015#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 5645016#L1293 assume !(0 != activate_threads_~tmp___0~0#1); 5646027#L1293-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5646028#L552 assume !(1 == ~t2_pc~0); 5645731#L552-2 is_transmit2_triggered_~__retres1~2#1 := 0; 5645732#L563 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5645588#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 5645589#L1301 assume !(0 != activate_threads_~tmp___1~0#1); 5645613#L1301-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5645614#L571 assume !(1 == ~t3_pc~0); 5645840#L571-2 is_transmit3_triggered_~__retres1~3#1 := 0; 5645924#L582 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5644962#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 5644963#L1309 assume !(0 != activate_threads_~tmp___2~0#1); 5645777#L1309-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5645045#L590 assume !(1 == ~t4_pc~0); 5645046#L590-2 is_transmit4_triggered_~__retres1~4#1 := 0; 5645839#L601 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5645140#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 5645141#L1317 assume !(0 != activate_threads_~tmp___3~0#1); 5646057#L1317-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5645774#L609 assume !(1 == ~t5_pc~0); 5645775#L609-2 is_transmit5_triggered_~__retres1~5#1 := 0; 5646448#L620 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5646271#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 5646272#L1325 assume !(0 != activate_threads_~tmp___4~0#1); 5645767#L1325-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 5645768#L628 assume !(1 == ~t6_pc~0); 5645692#L628-2 is_transmit6_triggered_~__retres1~6#1 := 0; 5645691#L639 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5645560#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 5645561#L1333 assume !(0 != activate_threads_~tmp___5~0#1); 5646103#L1333-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5646104#L647 assume !(1 == ~t7_pc~0); 5646247#L647-2 is_transmit7_triggered_~__retres1~7#1 := 0; 5646282#L658 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5646283#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 5645596#L1341 assume !(0 != activate_threads_~tmp___6~0#1); 5645597#L1341-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 5646510#L666 assume !(1 == ~t8_pc~0); 5645391#L666-2 is_transmit8_triggered_~__retres1~8#1 := 0; 5645392#L677 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 5645612#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 5645799#L1349 assume !(0 != activate_threads_~tmp___7~0#1); 5645524#L1349-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 5645525#L685 assume !(1 == ~t9_pc~0); 5646465#L685-2 is_transmit9_triggered_~__retres1~9#1 := 0; 5646296#L696 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 5645650#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 5645549#L1357 assume !(0 != activate_threads_~tmp___8~0#1); 5645550#L1357-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 5645959#L704 assume !(1 == ~t10_pc~0); 5645543#L704-2 is_transmit10_triggered_~__retres1~10#1 := 0; 5646401#L715 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 5645813#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 5645093#L1365 assume !(0 != activate_threads_~tmp___9~0#1); 5645094#L1365-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5645353#L1154 assume !(1 == ~M_E~0); 5646087#L1154-2 assume !(1 == ~T1_E~0); 5645321#L1159-1 assume !(1 == ~T2_E~0); 5645322#L1164-1 assume !(1 == ~T3_E~0); 5645797#L1169-1 assume !(1 == ~T4_E~0); 5645651#L1174-1 assume !(1 == ~T5_E~0); 5645451#L1179-1 assume !(1 == ~T6_E~0); 5645306#L1184-1 assume !(1 == ~T7_E~0); 5645307#L1189-1 assume !(1 == ~T8_E~0); 5645389#L1194-1 assume !(1 == ~T9_E~0); 5645510#L1199-1 assume !(1 == ~T10_E~0); 5645464#L1204-1 assume !(1 == ~E_M~0); 5645465#L1209-1 assume !(1 == ~E_1~0); 5646051#L1214-1 assume !(1 == ~E_2~0); 5646052#L1219-1 assume !(1 == ~E_3~0); 5646495#L1224-1 assume !(1 == ~E_4~0); 5645817#L1229-1 assume !(1 == ~E_5~0); 5645189#L1234-1 assume !(1 == ~E_6~0); 5645190#L1239-1 assume !(1 == ~E_7~0); 5645247#L1244-1 assume !(1 == ~E_8~0); 5645248#L1249-1 assume !(1 == ~E_9~0); 5646139#L1254-1 assume !(1 == ~E_10~0); 5645087#L1259-1 assume { :end_inline_reset_delta_events } true; 5645088#L1565-2 [2022-12-13 12:12:51,383 INFO L750 eck$LassoCheckResult]: Loop: 5645088#L1565-2 assume !false; 5731578#L1566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5731572#L1011 assume !false; 5731570#L862 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 5731568#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 5731556#L851 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 5731554#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 5731550#L866 assume !(0 != eval_~tmp~0#1); 5731551#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5752357#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5752356#L1036-3 assume !(0 == ~M_E~0); 5752355#L1036-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 5752354#L1041-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 5752353#L1046-3 assume !(0 == ~T3_E~0); 5752352#L1051-3 assume !(0 == ~T4_E~0); 5752351#L1056-3 assume !(0 == ~T5_E~0); 5752350#L1061-3 assume !(0 == ~T6_E~0); 5752349#L1066-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 5752348#L1071-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 5752347#L1076-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 5752346#L1081-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 5752345#L1086-3 assume !(0 == ~E_M~0); 5752344#L1091-3 assume !(0 == ~E_1~0); 5752343#L1096-3 assume !(0 == ~E_2~0); 5752342#L1101-3 assume !(0 == ~E_3~0); 5752341#L1106-3 assume 0 == ~E_4~0;~E_4~0 := 1; 5752340#L1111-3 assume 0 == ~E_5~0;~E_5~0 := 1; 5752339#L1116-3 assume 0 == ~E_6~0;~E_6~0 := 1; 5752338#L1121-3 assume 0 == ~E_7~0;~E_7~0 := 1; 5752337#L1126-3 assume !(0 == ~E_8~0); 5752336#L1131-3 assume !(0 == ~E_9~0); 5752335#L1136-3 assume !(0 == ~E_10~0); 5752334#L1141-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5752333#L514-36 assume !(1 == ~m_pc~0); 5752332#L514-38 is_master_triggered_~__retres1~0#1 := 0; 5752331#L525-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5752330#is_master_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 5752329#L1285-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 5752328#L1285-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5752327#L533-36 assume !(1 == ~t1_pc~0); 5752326#L533-38 is_transmit1_triggered_~__retres1~1#1 := 0; 5752324#L544-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5752323#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 5752322#L1293-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 5752321#L1293-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5752320#L552-36 assume !(1 == ~t2_pc~0); 5747068#L552-38 is_transmit2_triggered_~__retres1~2#1 := 0; 5752319#L563-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5752318#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 5752317#L1301-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 5752316#L1301-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5752315#L571-36 assume !(1 == ~t3_pc~0); 5744147#L571-38 is_transmit3_triggered_~__retres1~3#1 := 0; 5752314#L582-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5752313#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 5752312#L1309-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 5752311#L1309-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5752310#L590-36 assume !(1 == ~t4_pc~0); 5752309#L590-38 is_transmit4_triggered_~__retres1~4#1 := 0; 5752307#L601-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5752305#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 5752303#L1317-36 assume !(0 != activate_threads_~tmp___3~0#1); 5752301#L1317-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5752300#L609-36 assume !(1 == ~t5_pc~0); 5752299#L609-38 is_transmit5_triggered_~__retres1~5#1 := 0; 5752298#L620-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5752297#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 5752296#L1325-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 5752295#L1325-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 5752294#L628-36 assume 1 == ~t6_pc~0; 5752293#L629-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 5752291#L639-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5752290#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 5752289#L1333-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 5752288#L1333-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5752287#L647-36 assume !(1 == ~t7_pc~0); 5701781#L647-38 is_transmit7_triggered_~__retres1~7#1 := 0; 5752286#L658-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5752285#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 5752284#L1341-36 assume !(0 != activate_threads_~tmp___6~0#1); 5752283#L1341-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 5752282#L666-36 assume !(1 == ~t8_pc~0); 5752281#L666-38 is_transmit8_triggered_~__retres1~8#1 := 0; 5752279#L677-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 5752278#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 5752277#L1349-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 5752276#L1349-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 5752275#L685-36 assume !(1 == ~t9_pc~0); 5689294#L685-38 is_transmit9_triggered_~__retres1~9#1 := 0; 5752274#L696-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 5752273#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 5752272#L1357-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 5752271#L1357-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 5752270#L704-36 assume !(1 == ~t10_pc~0); 5752268#L704-38 is_transmit10_triggered_~__retres1~10#1 := 0; 5752267#L715-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 5752266#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 5752265#L1365-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 5752264#L1365-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5752263#L1154-3 assume !(1 == ~M_E~0); 5687919#L1154-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5752262#L1159-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5752261#L1164-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 5752260#L1169-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5752259#L1174-3 assume !(1 == ~T5_E~0); 5752258#L1179-3 assume !(1 == ~T6_E~0); 5752257#L1184-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 5752256#L1189-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 5752255#L1194-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 5752254#L1199-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 5752253#L1204-3 assume 1 == ~E_M~0;~E_M~0 := 2; 5752252#L1209-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5752251#L1214-3 assume !(1 == ~E_2~0); 5646830#L1219-3 assume !(1 == ~E_3~0); 5646828#L1224-3 assume 1 == ~E_4~0;~E_4~0 := 2; 5646826#L1229-3 assume 1 == ~E_5~0;~E_5~0 := 2; 5646824#L1234-3 assume 1 == ~E_6~0;~E_6~0 := 2; 5646822#L1239-3 assume 1 == ~E_7~0;~E_7~0 := 2; 5646820#L1244-3 assume 1 == ~E_8~0;~E_8~0 := 2; 5646818#L1249-3 assume 1 == ~E_9~0;~E_9~0 := 2; 5646817#L1254-3 assume !(1 == ~E_10~0); 5646816#L1259-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 5646804#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 5646745#L851-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 5646739#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 5646732#L1584 assume !(0 == start_simulation_~tmp~3#1); 5646733#L1584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 5731612#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 5731599#L851-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 5731594#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 5731590#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5731585#L1546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5731582#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 5731581#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 5645088#L1565-2 [2022-12-13 12:12:51,384 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:12:51,384 INFO L85 PathProgramCache]: Analyzing trace with hash -1410728759, now seen corresponding path program 3 times [2022-12-13 12:12:51,384 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:12:51,384 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1287366089] [2022-12-13 12:12:51,384 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:12:51,384 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:12:51,393 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 12:12:51,393 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 12:12:51,398 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 12:12:51,423 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 12:12:51,424 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:12:51,424 INFO L85 PathProgramCache]: Analyzing trace with hash 2032087647, now seen corresponding path program 1 times [2022-12-13 12:12:51,424 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:12:51,424 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [368482062] [2022-12-13 12:12:51,424 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:12:51,425 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:12:51,431 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:12:51,453 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:12:51,453 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:12:51,453 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [368482062] [2022-12-13 12:12:51,453 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [368482062] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:12:51,453 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:12:51,453 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-12-13 12:12:51,453 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1653485429] [2022-12-13 12:12:51,453 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:12:51,454 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:12:51,454 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:12:51,454 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-12-13 12:12:51,454 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-12-13 12:12:51,454 INFO L87 Difference]: Start difference. First operand 224952 states and 312077 transitions. cyclomatic complexity: 87129 Second operand has 5 states, 5 states have (on average 26.8) internal successors, (134), 5 states have internal predecessors, (134), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:12:52,615 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:12:52,615 INFO L93 Difference]: Finished difference Result 417320 states and 574685 transitions. [2022-12-13 12:12:52,615 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 417320 states and 574685 transitions. [2022-12-13 12:12:54,453 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 416416