./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/token_ring.11.cil-2.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 2329fc70 Calling Ultimate with: /usr/lib/jvm/java-1.11.0-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_773dfbb0-07bc-44ef-ac12-0f75a05b450e/bin/uautomizer-uyxdKDjOR8/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_773dfbb0-07bc-44ef-ac12-0f75a05b450e/bin/uautomizer-uyxdKDjOR8/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_773dfbb0-07bc-44ef-ac12-0f75a05b450e/bin/uautomizer-uyxdKDjOR8/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_773dfbb0-07bc-44ef-ac12-0f75a05b450e/bin/uautomizer-uyxdKDjOR8/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/token_ring.11.cil-2.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_773dfbb0-07bc-44ef-ac12-0f75a05b450e/bin/uautomizer-uyxdKDjOR8/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_773dfbb0-07bc-44ef-ac12-0f75a05b450e/bin/uautomizer-uyxdKDjOR8 --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash c5f603027c62ff37561a520351662dbe2fd253b52e04e36028cb9a624978ef8e --- Real Ultimate output --- [0.001s][warning][os,container] Duplicate cpuset controllers detected. Picking /sys/fs/cgroup/cpuset, skipping /sys/fs/cgroup/cpuset. This is Ultimate 0.2.2-dev-2329fc7 [2022-12-13 17:13:23,101 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-12-13 17:13:23,103 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-12-13 17:13:23,122 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-12-13 17:13:23,122 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-12-13 17:13:23,123 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-12-13 17:13:23,124 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-12-13 17:13:23,126 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-12-13 17:13:23,127 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-12-13 17:13:23,128 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-12-13 17:13:23,129 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-12-13 17:13:23,130 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-12-13 17:13:23,130 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-12-13 17:13:23,131 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-12-13 17:13:23,132 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-12-13 17:13:23,133 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-12-13 17:13:23,134 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-12-13 17:13:23,135 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-12-13 17:13:23,136 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-12-13 17:13:23,138 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-12-13 17:13:23,140 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-12-13 17:13:23,141 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-12-13 17:13:23,148 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-12-13 17:13:23,149 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-12-13 17:13:23,153 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-12-13 17:13:23,153 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-12-13 17:13:23,153 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-12-13 17:13:23,154 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-12-13 17:13:23,155 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-12-13 17:13:23,156 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-12-13 17:13:23,156 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-12-13 17:13:23,156 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-12-13 17:13:23,157 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-12-13 17:13:23,158 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-12-13 17:13:23,159 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-12-13 17:13:23,159 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-12-13 17:13:23,160 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-12-13 17:13:23,160 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-12-13 17:13:23,160 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-12-13 17:13:23,161 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-12-13 17:13:23,161 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-12-13 17:13:23,162 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_773dfbb0-07bc-44ef-ac12-0f75a05b450e/bin/uautomizer-uyxdKDjOR8/config/svcomp-Termination-32bit-Automizer_Default.epf [2022-12-13 17:13:23,197 INFO L113 SettingsManager]: Loading preferences was successful [2022-12-13 17:13:23,197 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-12-13 17:13:23,197 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-12-13 17:13:23,198 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-12-13 17:13:23,199 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-12-13 17:13:23,199 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-12-13 17:13:23,199 INFO L138 SettingsManager]: * Use SBE=true [2022-12-13 17:13:23,199 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2022-12-13 17:13:23,199 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2022-12-13 17:13:23,199 INFO L138 SettingsManager]: * Use old map elimination=false [2022-12-13 17:13:23,200 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2022-12-13 17:13:23,200 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2022-12-13 17:13:23,200 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2022-12-13 17:13:23,200 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-12-13 17:13:23,200 INFO L138 SettingsManager]: * sizeof long=4 [2022-12-13 17:13:23,200 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2022-12-13 17:13:23,201 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-12-13 17:13:23,201 INFO L138 SettingsManager]: * sizeof POINTER=4 [2022-12-13 17:13:23,201 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-12-13 17:13:23,201 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2022-12-13 17:13:23,201 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2022-12-13 17:13:23,201 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2022-12-13 17:13:23,201 INFO L138 SettingsManager]: * sizeof long double=12 [2022-12-13 17:13:23,202 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-12-13 17:13:23,202 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2022-12-13 17:13:23,202 INFO L138 SettingsManager]: * Use constant arrays=true [2022-12-13 17:13:23,202 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2022-12-13 17:13:23,202 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-12-13 17:13:23,203 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-12-13 17:13:23,203 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-12-13 17:13:23,203 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-12-13 17:13:23,204 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-12-13 17:13:23,204 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_773dfbb0-07bc-44ef-ac12-0f75a05b450e/bin/uautomizer-uyxdKDjOR8/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_773dfbb0-07bc-44ef-ac12-0f75a05b450e/bin/uautomizer-uyxdKDjOR8 Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> c5f603027c62ff37561a520351662dbe2fd253b52e04e36028cb9a624978ef8e [2022-12-13 17:13:23,376 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-12-13 17:13:23,394 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-12-13 17:13:23,396 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-12-13 17:13:23,396 INFO L271 PluginConnector]: Initializing CDTParser... [2022-12-13 17:13:23,397 INFO L275 PluginConnector]: CDTParser initialized [2022-12-13 17:13:23,397 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_773dfbb0-07bc-44ef-ac12-0f75a05b450e/bin/uautomizer-uyxdKDjOR8/../../sv-benchmarks/c/systemc/token_ring.11.cil-2.c [2022-12-13 17:13:26,012 INFO L500 CDTParser]: Created temporary CDT project at NULL [2022-12-13 17:13:26,158 INFO L351 CDTParser]: Found 1 translation units. [2022-12-13 17:13:26,158 INFO L172 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_773dfbb0-07bc-44ef-ac12-0f75a05b450e/sv-benchmarks/c/systemc/token_ring.11.cil-2.c [2022-12-13 17:13:26,167 INFO L394 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_773dfbb0-07bc-44ef-ac12-0f75a05b450e/bin/uautomizer-uyxdKDjOR8/data/b530673e4/01151f8fd560455faead73c2b1f51f5f/FLAGbb926f0be [2022-12-13 17:13:26,177 INFO L402 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_773dfbb0-07bc-44ef-ac12-0f75a05b450e/bin/uautomizer-uyxdKDjOR8/data/b530673e4/01151f8fd560455faead73c2b1f51f5f [2022-12-13 17:13:26,179 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-12-13 17:13:26,180 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-12-13 17:13:26,181 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-12-13 17:13:26,181 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-12-13 17:13:26,184 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-12-13 17:13:26,185 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.12 05:13:26" (1/1) ... [2022-12-13 17:13:26,185 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@2e995e16 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 05:13:26, skipping insertion in model container [2022-12-13 17:13:26,186 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.12 05:13:26" (1/1) ... [2022-12-13 17:13:26,191 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-12-13 17:13:26,220 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-12-13 17:13:26,319 WARN L237 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_773dfbb0-07bc-44ef-ac12-0f75a05b450e/sv-benchmarks/c/systemc/token_ring.11.cil-2.c[671,684] [2022-12-13 17:13:26,397 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-12-13 17:13:26,407 INFO L203 MainTranslator]: Completed pre-run [2022-12-13 17:13:26,415 WARN L237 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_773dfbb0-07bc-44ef-ac12-0f75a05b450e/sv-benchmarks/c/systemc/token_ring.11.cil-2.c[671,684] [2022-12-13 17:13:26,458 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-12-13 17:13:26,471 INFO L208 MainTranslator]: Completed translation [2022-12-13 17:13:26,472 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 05:13:26 WrapperNode [2022-12-13 17:13:26,472 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-12-13 17:13:26,473 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-12-13 17:13:26,473 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-12-13 17:13:26,473 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-12-13 17:13:26,478 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 05:13:26" (1/1) ... [2022-12-13 17:13:26,487 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 05:13:26" (1/1) ... [2022-12-13 17:13:26,573 INFO L138 Inliner]: procedures = 50, calls = 64, calls flagged for inlining = 59, calls inlined = 238, statements flattened = 3645 [2022-12-13 17:13:26,573 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-12-13 17:13:26,574 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-12-13 17:13:26,574 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-12-13 17:13:26,574 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-12-13 17:13:26,583 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 05:13:26" (1/1) ... [2022-12-13 17:13:26,584 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 05:13:26" (1/1) ... [2022-12-13 17:13:26,592 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 05:13:26" (1/1) ... [2022-12-13 17:13:26,593 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 05:13:26" (1/1) ... [2022-12-13 17:13:26,626 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 05:13:26" (1/1) ... [2022-12-13 17:13:26,654 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 05:13:26" (1/1) ... [2022-12-13 17:13:26,660 INFO L185 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 05:13:26" (1/1) ... [2022-12-13 17:13:26,668 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 05:13:26" (1/1) ... [2022-12-13 17:13:26,679 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-12-13 17:13:26,680 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-12-13 17:13:26,680 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-12-13 17:13:26,680 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-12-13 17:13:26,681 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 05:13:26" (1/1) ... [2022-12-13 17:13:26,687 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-12-13 17:13:26,698 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_773dfbb0-07bc-44ef-ac12-0f75a05b450e/bin/uautomizer-uyxdKDjOR8/z3 [2022-12-13 17:13:26,709 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_773dfbb0-07bc-44ef-ac12-0f75a05b450e/bin/uautomizer-uyxdKDjOR8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-12-13 17:13:26,711 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_773dfbb0-07bc-44ef-ac12-0f75a05b450e/bin/uautomizer-uyxdKDjOR8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2022-12-13 17:13:26,745 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-12-13 17:13:26,745 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-12-13 17:13:26,745 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-12-13 17:13:26,746 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-12-13 17:13:26,834 INFO L235 CfgBuilder]: Building ICFG [2022-12-13 17:13:26,835 INFO L261 CfgBuilder]: Building CFG for each procedure with an implementation [2022-12-13 17:13:28,233 INFO L276 CfgBuilder]: Performing block encoding [2022-12-13 17:13:28,245 INFO L295 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-12-13 17:13:28,245 INFO L300 CfgBuilder]: Removed 14 assume(true) statements. [2022-12-13 17:13:28,248 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.12 05:13:28 BoogieIcfgContainer [2022-12-13 17:13:28,248 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-12-13 17:13:28,249 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2022-12-13 17:13:28,249 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2022-12-13 17:13:28,252 INFO L275 PluginConnector]: BuchiAutomizer initialized [2022-12-13 17:13:28,252 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-12-13 17:13:28,252 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 13.12 05:13:26" (1/3) ... [2022-12-13 17:13:28,253 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@7985b61b and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 13.12 05:13:28, skipping insertion in model container [2022-12-13 17:13:28,253 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-12-13 17:13:28,253 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 05:13:26" (2/3) ... [2022-12-13 17:13:28,253 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@7985b61b and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 13.12 05:13:28, skipping insertion in model container [2022-12-13 17:13:28,253 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-12-13 17:13:28,253 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.12 05:13:28" (3/3) ... [2022-12-13 17:13:28,255 INFO L332 chiAutomizerObserver]: Analyzing ICFG token_ring.11.cil-2.c [2022-12-13 17:13:28,308 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2022-12-13 17:13:28,309 INFO L304 stractBuchiCegarLoop]: Hoare is false [2022-12-13 17:13:28,309 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2022-12-13 17:13:28,309 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2022-12-13 17:13:28,309 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2022-12-13 17:13:28,309 INFO L308 stractBuchiCegarLoop]: Difference is false [2022-12-13 17:13:28,309 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2022-12-13 17:13:28,309 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2022-12-13 17:13:28,316 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1572 states, 1571 states have (on average 1.5022278803309994) internal successors, (2360), 1571 states have internal predecessors, (2360), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 17:13:28,370 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1417 [2022-12-13 17:13:28,370 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 17:13:28,370 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 17:13:28,382 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 17:13:28,383 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 17:13:28,383 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2022-12-13 17:13:28,386 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1572 states, 1571 states have (on average 1.5022278803309994) internal successors, (2360), 1571 states have internal predecessors, (2360), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 17:13:28,406 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1417 [2022-12-13 17:13:28,406 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 17:13:28,406 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 17:13:28,411 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 17:13:28,411 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 17:13:28,421 INFO L748 eck$LassoCheckResult]: Stem: 123#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 1513#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 604#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1509#update_channels_returnLabel#1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 109#L780true assume !(1 == ~m_i~0);~m_st~0 := 2; 1147#L780-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 1402#L785-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 1081#L790-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1400#L795-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 300#L800-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 578#L805-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 1091#L810-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 1023#L815-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 250#L820-1true assume 1 == ~t9_i~0;~t9_st~0 := 0; 726#L825-1true assume !(1 == ~t10_i~0);~t10_st~0 := 2; 193#L830-1true assume !(1 == ~t11_i~0);~t11_st~0 := 2; 914#L835-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1457#L1109true assume !(0 == ~M_E~0); 949#L1109-2true assume !(0 == ~T1_E~0); 198#L1114-1true assume 0 == ~T2_E~0;~T2_E~0 := 1; 1529#L1119-1true assume !(0 == ~T3_E~0); 1028#L1124-1true assume !(0 == ~T4_E~0); 21#L1129-1true assume !(0 == ~T5_E~0); 351#L1134-1true assume !(0 == ~T6_E~0); 933#L1139-1true assume !(0 == ~T7_E~0); 1005#L1144-1true assume !(0 == ~T8_E~0); 776#L1149-1true assume !(0 == ~T9_E~0); 72#L1154-1true assume 0 == ~T10_E~0;~T10_E~0 := 1; 908#L1159-1true assume !(0 == ~T11_E~0); 765#L1164-1true assume !(0 == ~E_M~0); 277#L1169-1true assume !(0 == ~E_1~0); 224#L1174-1true assume !(0 == ~E_2~0); 151#L1179-1true assume !(0 == ~E_3~0); 112#L1184-1true assume !(0 == ~E_4~0); 130#L1189-1true assume !(0 == ~E_5~0); 174#L1194-1true assume 0 == ~E_6~0;~E_6~0 := 1; 784#L1199-1true assume !(0 == ~E_7~0); 957#L1204-1true assume !(0 == ~E_8~0); 722#L1209-1true assume !(0 == ~E_9~0); 1174#L1214-1true assume !(0 == ~E_10~0); 1531#L1219-1true assume !(0 == ~E_11~0); 1477#L1224-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 288#L544true assume 1 == ~m_pc~0; 1019#L545true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1184#L555true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 514#is_master_triggered_returnLabel#1true activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 92#L1379true assume !(0 != activate_threads_~tmp~1#1); 1395#L1379-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 564#L563true assume !(1 == ~t1_pc~0); 1180#L563-2true is_transmit1_triggered_~__retres1~1#1 := 0; 26#L574true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 820#is_transmit1_triggered_returnLabel#1true activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 667#L1387true assume !(0 != activate_threads_~tmp___0~0#1); 24#L1387-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 410#L582true assume 1 == ~t2_pc~0; 877#L583true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 675#L593true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 196#is_transmit2_triggered_returnLabel#1true activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 833#L1395true assume !(0 != activate_threads_~tmp___1~0#1); 40#L1395-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 755#L601true assume !(1 == ~t3_pc~0); 469#L601-2true is_transmit3_triggered_~__retres1~3#1 := 0; 1000#L612true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 801#is_transmit3_triggered_returnLabel#1true activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 704#L1403true assume !(0 != activate_threads_~tmp___2~0#1); 1413#L1403-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 655#L620true assume 1 == ~t4_pc~0; 31#L621true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 368#L631true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 46#is_transmit4_triggered_returnLabel#1true activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 575#L1411true assume !(0 != activate_threads_~tmp___3~0#1); 756#L1411-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 739#L639true assume 1 == ~t5_pc~0; 632#L640true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 177#L650true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1271#is_transmit5_triggered_returnLabel#1true activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 590#L1419true assume !(0 != activate_threads_~tmp___4~0#1); 840#L1419-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 534#L658true assume !(1 == ~t6_pc~0); 286#L658-2true is_transmit6_triggered_~__retres1~6#1 := 0; 697#L669true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 191#is_transmit6_triggered_returnLabel#1true activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1485#L1427true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 708#L1427-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 203#L677true assume 1 == ~t7_pc~0; 1241#L678true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 880#L688true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1523#is_transmit7_triggered_returnLabel#1true activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1067#L1435true assume !(0 != activate_threads_~tmp___6~0#1); 1224#L1435-2true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1302#L696true assume !(1 == ~t8_pc~0); 323#L696-2true is_transmit8_triggered_~__retres1~8#1 := 0; 1144#L707true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1227#is_transmit8_triggered_returnLabel#1true activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1348#L1443true assume !(0 != activate_threads_~tmp___7~0#1); 1527#L1443-2true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 624#L715true assume 1 == ~t9_pc~0; 1216#L716true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 385#L726true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 223#is_transmit9_triggered_returnLabel#1true activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 609#L1451true assume !(0 != activate_threads_~tmp___8~0#1); 1393#L1451-2true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 878#L734true assume !(1 == ~t10_pc~0); 1029#L734-2true is_transmit10_triggered_~__retres1~10#1 := 0; 263#L745true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1078#is_transmit10_triggered_returnLabel#1true activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 804#L1459true assume !(0 != activate_threads_~tmp___9~0#1); 1253#L1459-2true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 308#L753true assume 1 == ~t11_pc~0; 714#L754true assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 1570#L764true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1161#is_transmit11_triggered_returnLabel#1true activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 482#L1467true assume !(0 != activate_threads_~tmp___10~0#1); 770#L1467-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 519#L1237true assume !(1 == ~M_E~0); 1295#L1237-2true assume !(1 == ~T1_E~0); 1425#L1242-1true assume !(1 == ~T2_E~0); 365#L1247-1true assume !(1 == ~T3_E~0); 1063#L1252-1true assume !(1 == ~T4_E~0); 232#L1257-1true assume !(1 == ~T5_E~0); 898#L1262-1true assume 1 == ~T6_E~0;~T6_E~0 := 2; 1051#L1267-1true assume !(1 == ~T7_E~0); 1052#L1272-1true assume !(1 == ~T8_E~0); 417#L1277-1true assume !(1 == ~T9_E~0); 813#L1282-1true assume !(1 == ~T10_E~0); 750#L1287-1true assume !(1 == ~T11_E~0); 785#L1292-1true assume !(1 == ~E_M~0); 707#L1297-1true assume !(1 == ~E_1~0); 302#L1302-1true assume 1 == ~E_2~0;~E_2~0 := 2; 1032#L1307-1true assume !(1 == ~E_3~0); 1359#L1312-1true assume !(1 == ~E_4~0); 445#L1317-1true assume !(1 == ~E_5~0); 618#L1322-1true assume !(1 == ~E_6~0); 270#L1327-1true assume !(1 == ~E_7~0); 666#L1332-1true assume !(1 == ~E_8~0); 1338#L1337-1true assume !(1 == ~E_9~0); 613#L1342-1true assume 1 == ~E_10~0;~E_10~0 := 2; 1230#L1347-1true assume !(1 == ~E_11~0); 1031#L1352-1true assume { :end_inline_reset_delta_events } true; 1567#L1678-2true [2022-12-13 17:13:28,425 INFO L750 eck$LassoCheckResult]: Loop: 1567#L1678-2true assume !false; 657#L1679true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 808#L1084true assume !true; 473#eval_returnLabel#1true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 299#update_channels_returnLabel#2true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1429#L1109-3true assume 0 == ~M_E~0;~M_E~0 := 1; 32#L1109-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 1209#L1114-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 709#L1119-3true assume !(0 == ~T3_E~0); 1562#L1124-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 736#L1129-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 941#L1134-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 1112#L1139-3true assume 0 == ~T7_E~0;~T7_E~0 := 1; 1017#L1144-3true assume 0 == ~T8_E~0;~T8_E~0 := 1; 293#L1149-3true assume 0 == ~T9_E~0;~T9_E~0 := 1; 1556#L1154-3true assume 0 == ~T10_E~0;~T10_E~0 := 1; 449#L1159-3true assume !(0 == ~T11_E~0); 1540#L1164-3true assume 0 == ~E_M~0;~E_M~0 := 1; 652#L1169-3true assume 0 == ~E_1~0;~E_1~0 := 1; 973#L1174-3true assume 0 == ~E_2~0;~E_2~0 := 1; 698#L1179-3true assume 0 == ~E_3~0;~E_3~0 := 1; 1304#L1184-3true assume 0 == ~E_4~0;~E_4~0 := 1; 859#L1189-3true assume 0 == ~E_5~0;~E_5~0 := 1; 558#L1194-3true assume 0 == ~E_6~0;~E_6~0 := 1; 163#L1199-3true assume !(0 == ~E_7~0); 787#L1204-3true assume 0 == ~E_8~0;~E_8~0 := 1; 282#L1209-3true assume 0 == ~E_9~0;~E_9~0 := 1; 10#L1214-3true assume 0 == ~E_10~0;~E_10~0 := 1; 603#L1219-3true assume 0 == ~E_11~0;~E_11~0 := 1; 392#L1224-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 645#L544-39true assume !(1 == ~m_pc~0); 4#L544-41true is_master_triggered_~__retres1~0#1 := 0; 738#L555-13true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 625#is_master_triggered_returnLabel#14true activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 207#L1379-39true assume !(0 != activate_threads_~tmp~1#1); 839#L1379-41true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1315#L563-39true assume 1 == ~t1_pc~0; 851#L564-13true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1541#L574-13true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1406#is_transmit1_triggered_returnLabel#14true activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1439#L1387-39true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1450#L1387-41true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 986#L582-39true assume !(1 == ~t2_pc~0); 1238#L582-41true is_transmit2_triggered_~__retres1~2#1 := 0; 757#L593-13true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 430#is_transmit2_triggered_returnLabel#14true activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 959#L1395-39true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 117#L1395-41true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 15#L601-39true assume !(1 == ~t3_pc~0); 37#L601-41true is_transmit3_triggered_~__retres1~3#1 := 0; 798#L612-13true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1552#is_transmit3_triggered_returnLabel#14true activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1498#L1403-39true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 847#L1403-41true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 532#L620-39true assume !(1 == ~t4_pc~0); 1547#L620-41true is_transmit4_triggered_~__retres1~4#1 := 0; 927#L631-13true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 550#is_transmit4_triggered_returnLabel#14true activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 809#L1411-39true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1550#L1411-41true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1545#L639-39true assume !(1 == ~t5_pc~0); 1283#L639-41true is_transmit5_triggered_~__retres1~5#1 := 0; 369#L650-13true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 567#is_transmit5_triggered_returnLabel#14true activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 27#L1419-39true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1379#L1419-41true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 562#L658-39true assume !(1 == ~t6_pc~0); 1434#L658-41true is_transmit6_triggered_~__retres1~6#1 := 0; 1061#L669-13true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1482#is_transmit6_triggered_returnLabel#14true activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 719#L1427-39true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 693#L1427-41true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1234#L677-39true assume !(1 == ~t7_pc~0); 415#L677-41true is_transmit7_triggered_~__retres1~7#1 := 0; 111#L688-13true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 810#is_transmit7_triggered_returnLabel#14true activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 141#L1435-39true assume !(0 != activate_threads_~tmp___6~0#1); 1369#L1435-41true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 484#L696-39true assume 1 == ~t8_pc~0; 456#L697-13true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 380#L707-13true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 928#is_transmit8_triggered_returnLabel#14true activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 585#L1443-39true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 554#L1443-41true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 467#L715-39true assume 1 == ~t9_pc~0; 17#L716-13true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 806#L726-13true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 53#is_transmit9_triggered_returnLabel#14true activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1569#L1451-39true assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 742#L1451-41true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1136#L734-39true assume 1 == ~t10_pc~0; 671#L735-13true assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 486#L745-13true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1157#is_transmit10_triggered_returnLabel#14true activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 87#L1459-39true assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1463#L1459-41true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1087#L753-39true assume 1 == ~t11_pc~0; 440#L754-13true assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 1002#L764-13true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 583#is_transmit11_triggered_returnLabel#14true activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 460#L1467-39true assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 749#L1467-41true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 530#L1237-3true assume 1 == ~M_E~0;~M_E~0 := 2; 1082#L1237-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 767#L1242-3true assume !(1 == ~T2_E~0); 1517#L1247-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 1050#L1252-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 689#L1257-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 1008#L1262-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 1094#L1267-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 1532#L1272-3true assume 1 == ~T8_E~0;~T8_E~0 := 2; 1336#L1277-3true assume 1 == ~T9_E~0;~T9_E~0 := 2; 126#L1282-3true assume !(1 == ~T10_E~0); 668#L1287-3true assume 1 == ~T11_E~0;~T11_E~0 := 2; 79#L1292-3true assume 1 == ~E_M~0;~E_M~0 := 2; 1495#L1297-3true assume 1 == ~E_1~0;~E_1~0 := 2; 892#L1302-3true assume 1 == ~E_2~0;~E_2~0 := 2; 1221#L1307-3true assume 1 == ~E_3~0;~E_3~0 := 2; 1515#L1312-3true assume 1 == ~E_4~0;~E_4~0 := 2; 1506#L1317-3true assume 1 == ~E_5~0;~E_5~0 := 2; 788#L1322-3true assume !(1 == ~E_6~0); 1560#L1327-3true assume 1 == ~E_7~0;~E_7~0 := 2; 107#L1332-3true assume 1 == ~E_8~0;~E_8~0 := 2; 95#L1337-3true assume 1 == ~E_9~0;~E_9~0 := 2; 509#L1342-3true assume 1 == ~E_10~0;~E_10~0 := 2; 931#L1347-3true assume 1 == ~E_11~0;~E_11~0 := 2; 608#L1352-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 882#L848-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 212#L910-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 178#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 740#L1697true assume !(0 == start_simulation_~tmp~3#1); 525#L1697-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 1307#L848-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 848#L910-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 22#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; 1116#L1652true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 581#L1659true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1097#stop_simulation_returnLabel#1true start_simulation_#t~ret32#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 879#L1710true assume !(0 != start_simulation_~tmp___0~1#1); 1567#L1678-2true [2022-12-13 17:13:28,431 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 17:13:28,432 INFO L85 PathProgramCache]: Analyzing trace with hash 430082112, now seen corresponding path program 1 times [2022-12-13 17:13:28,441 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 17:13:28,442 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [627228619] [2022-12-13 17:13:28,442 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 17:13:28,443 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 17:13:28,556 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 17:13:28,700 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 17:13:28,701 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 17:13:28,701 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [627228619] [2022-12-13 17:13:28,702 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [627228619] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 17:13:28,702 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 17:13:28,702 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 17:13:28,704 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1829193304] [2022-12-13 17:13:28,705 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 17:13:28,708 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 17:13:28,709 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 17:13:28,709 INFO L85 PathProgramCache]: Analyzing trace with hash 1723819851, now seen corresponding path program 1 times [2022-12-13 17:13:28,709 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 17:13:28,710 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1665863700] [2022-12-13 17:13:28,710 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 17:13:28,710 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 17:13:28,728 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 17:13:28,772 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 17:13:28,772 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 17:13:28,773 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1665863700] [2022-12-13 17:13:28,773 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1665863700] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 17:13:28,773 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 17:13:28,773 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-12-13 17:13:28,773 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [929266707] [2022-12-13 17:13:28,774 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 17:13:28,775 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 17:13:28,776 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 17:13:28,806 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2022-12-13 17:13:28,807 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2022-12-13 17:13:28,811 INFO L87 Difference]: Start difference. First operand has 1572 states, 1571 states have (on average 1.5022278803309994) internal successors, (2360), 1571 states have internal predecessors, (2360), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 2 states, 2 states have (on average 69.5) internal successors, (139), 2 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 17:13:28,860 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 17:13:28,860 INFO L93 Difference]: Finished difference Result 1571 states and 2330 transitions. [2022-12-13 17:13:28,862 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1571 states and 2330 transitions. [2022-12-13 17:13:28,877 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1415 [2022-12-13 17:13:28,893 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1571 states to 1566 states and 2325 transitions. [2022-12-13 17:13:28,894 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1566 [2022-12-13 17:13:28,895 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1566 [2022-12-13 17:13:28,896 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1566 states and 2325 transitions. [2022-12-13 17:13:28,901 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 17:13:28,901 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1566 states and 2325 transitions. [2022-12-13 17:13:28,916 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1566 states and 2325 transitions. [2022-12-13 17:13:28,951 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1566 to 1566. [2022-12-13 17:13:28,953 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1566 states, 1566 states have (on average 1.4846743295019158) internal successors, (2325), 1565 states have internal predecessors, (2325), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 17:13:28,956 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1566 states to 1566 states and 2325 transitions. [2022-12-13 17:13:28,957 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1566 states and 2325 transitions. [2022-12-13 17:13:28,958 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2022-12-13 17:13:28,960 INFO L428 stractBuchiCegarLoop]: Abstraction has 1566 states and 2325 transitions. [2022-12-13 17:13:28,960 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2022-12-13 17:13:28,961 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1566 states and 2325 transitions. [2022-12-13 17:13:28,966 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1415 [2022-12-13 17:13:28,966 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 17:13:28,966 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 17:13:28,967 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 17:13:28,968 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 17:13:28,968 INFO L748 eck$LassoCheckResult]: Stem: 3408#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 3409#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 4183#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4184#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3382#L780 assume !(1 == ~m_i~0);~m_st~0 := 2; 3383#L780-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4612#L785-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 4579#L790-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 4580#L795-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 3737#L800-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 3738#L805-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 4152#L810-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 4548#L815-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 3645#L820-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 3646#L825-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 3536#L830-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 3537#L835-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4479#L1109 assume !(0 == ~M_E~0); 4495#L1109-2 assume !(0 == ~T1_E~0); 3545#L1114-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3546#L1119-1 assume !(0 == ~T3_E~0); 4551#L1124-1 assume !(0 == ~T4_E~0); 3196#L1129-1 assume !(0 == ~T5_E~0); 3197#L1134-1 assume !(0 == ~T6_E~0); 3824#L1139-1 assume !(0 == ~T7_E~0); 4486#L1144-1 assume !(0 == ~T8_E~0); 4362#L1149-1 assume !(0 == ~T9_E~0); 3307#L1154-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 3308#L1159-1 assume !(0 == ~T11_E~0); 4352#L1164-1 assume !(0 == ~E_M~0); 3699#L1169-1 assume !(0 == ~E_1~0); 3597#L1174-1 assume !(0 == ~E_2~0); 3461#L1179-1 assume !(0 == ~E_3~0); 3388#L1184-1 assume !(0 == ~E_4~0); 3389#L1189-1 assume !(0 == ~E_5~0); 3421#L1194-1 assume 0 == ~E_6~0;~E_6~0 := 1; 3504#L1199-1 assume !(0 == ~E_7~0); 4371#L1204-1 assume !(0 == ~E_8~0); 4312#L1209-1 assume !(0 == ~E_9~0); 4313#L1214-1 assume !(0 == ~E_10~0); 4625#L1219-1 assume !(0 == ~E_11~0); 4711#L1224-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3716#L544 assume 1 == ~m_pc~0; 3717#L545 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 4534#L555 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4072#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3350#L1379 assume !(0 != activate_threads_~tmp~1#1); 3351#L1379-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4139#L563 assume !(1 == ~t1_pc~0); 3941#L563-2 is_transmit1_triggered_~__retres1~1#1 := 0; 3206#L574 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3207#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4259#L1387 assume !(0 != activate_threads_~tmp___0~0#1); 3202#L1387-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3203#L582 assume 1 == ~t2_pc~0; 3919#L583 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4264#L593 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3541#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3542#L1395 assume !(0 != activate_threads_~tmp___1~0#1); 3235#L1395-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3236#L601 assume !(1 == ~t3_pc~0); 3936#L601-2 is_transmit3_triggered_~__retres1~3#1 := 0; 3935#L612 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4390#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4297#L1403 assume !(0 != activate_threads_~tmp___2~0#1); 4298#L1403-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4245#L620 assume 1 == ~t4_pc~0; 3216#L621 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3217#L631 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3249#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3250#L1411 assume !(0 != activate_threads_~tmp___3~0#1); 4149#L1411-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4330#L639 assume 1 == ~t5_pc~0; 4219#L640 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 3509#L650 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3510#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4169#L1419 assume !(0 != activate_threads_~tmp___4~0#1); 4170#L1419-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4104#L658 assume !(1 == ~t6_pc~0); 3713#L658-2 is_transmit6_triggered_~__retres1~6#1 := 0; 3714#L669 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3533#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3534#L1427 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 4301#L1427-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3556#L677 assume 1 == ~t7_pc~0; 3557#L678 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 3454#L688 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4451#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 4573#L1435 assume !(0 != activate_threads_~tmp___6~0#1); 4574#L1435-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4644#L696 assume !(1 == ~t8_pc~0); 3777#L696-2 is_transmit8_triggered_~__retres1~8#1 := 0; 3778#L707 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4610#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 4647#L1443 assume !(0 != activate_threads_~tmp___7~0#1); 4691#L1443-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4207#L715 assume 1 == ~t9_pc~0; 4208#L716 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 3877#L726 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3595#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 3596#L1451 assume !(0 != activate_threads_~tmp___8~0#1); 4190#L1451-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 4446#L734 assume !(1 == ~t10_pc~0); 4447#L734-2 is_transmit10_triggered_~__retres1~10#1 := 0; 3671#L745 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 3672#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 4392#L1459 assume !(0 != activate_threads_~tmp___9~0#1); 4393#L1459-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 3751#L753 assume 1 == ~t11_pc~0; 3752#L754 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 4306#L764 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 4619#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 4022#L1467 assume !(0 != activate_threads_~tmp___10~0#1); 4023#L1467-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4079#L1237 assume !(1 == ~M_E~0); 4080#L1237-2 assume !(1 == ~T1_E~0); 4674#L1242-1 assume !(1 == ~T2_E~0); 3845#L1247-1 assume !(1 == ~T3_E~0); 3846#L1252-1 assume !(1 == ~T4_E~0); 3614#L1257-1 assume !(1 == ~T5_E~0); 3615#L1262-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 4468#L1267-1 assume !(1 == ~T7_E~0); 4566#L1272-1 assume !(1 == ~T8_E~0); 3930#L1277-1 assume !(1 == ~T9_E~0); 3931#L1282-1 assume !(1 == ~T10_E~0); 4339#L1287-1 assume !(1 == ~T11_E~0); 4340#L1292-1 assume !(1 == ~E_M~0); 4300#L1297-1 assume !(1 == ~E_1~0); 3742#L1302-1 assume 1 == ~E_2~0;~E_2~0 := 2; 3743#L1307-1 assume !(1 == ~E_3~0); 4555#L1312-1 assume !(1 == ~E_4~0); 3976#L1317-1 assume !(1 == ~E_5~0); 3977#L1322-1 assume !(1 == ~E_6~0); 3686#L1327-1 assume !(1 == ~E_7~0); 3687#L1332-1 assume !(1 == ~E_8~0); 4258#L1337-1 assume !(1 == ~E_9~0); 4193#L1342-1 assume 1 == ~E_10~0;~E_10~0 := 2; 4194#L1347-1 assume !(1 == ~E_11~0); 4554#L1352-1 assume { :end_inline_reset_delta_events } true; 4450#L1678-2 [2022-12-13 17:13:28,969 INFO L750 eck$LassoCheckResult]: Loop: 4450#L1678-2 assume !false; 4248#L1679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4108#L1084 assume !false; 4043#L921 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 4044#L848 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 3326#L910 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 4540#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 3246#L925 assume !(0 != eval_~tmp~0#1); 3248#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3735#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3736#L1109-3 assume 0 == ~M_E~0;~M_E~0 := 1; 3219#L1109-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3220#L1114-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4302#L1119-3 assume !(0 == ~T3_E~0); 4303#L1124-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4327#L1129-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 4328#L1134-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 4491#L1139-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 4543#L1144-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 3726#L1149-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 3727#L1154-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 3983#L1159-3 assume !(0 == ~T11_E~0); 3984#L1164-3 assume 0 == ~E_M~0;~E_M~0 := 1; 4241#L1169-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4242#L1174-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4290#L1179-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4291#L1184-3 assume 0 == ~E_4~0;~E_4~0 := 1; 4431#L1189-3 assume 0 == ~E_5~0;~E_5~0 := 1; 4133#L1194-3 assume 0 == ~E_6~0;~E_6~0 := 1; 3483#L1199-3 assume !(0 == ~E_7~0); 3484#L1204-3 assume 0 == ~E_8~0;~E_8~0 := 1; 3706#L1209-3 assume 0 == ~E_9~0;~E_9~0 := 1; 3169#L1214-3 assume 0 == ~E_10~0;~E_10~0 := 1; 3170#L1219-3 assume 0 == ~E_11~0;~E_11~0 := 1; 3887#L1224-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3888#L544-39 assume !(1 == ~m_pc~0); 3157#L544-41 is_master_triggered_~__retres1~0#1 := 0; 3158#L555-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4210#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3564#L1379-39 assume !(0 != activate_threads_~tmp~1#1); 3565#L1379-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4418#L563-39 assume !(1 == ~t1_pc~0); 3302#L563-41 is_transmit1_triggered_~__retres1~1#1 := 0; 3303#L574-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4702#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4703#L1387-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4706#L1387-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4525#L582-39 assume 1 == ~t2_pc~0; 3626#L583-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3628#L593-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3953#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3954#L1395-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3397#L1395-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3181#L601-39 assume 1 == ~t3_pc~0; 3182#L602-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3230#L612-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4388#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4713#L1403-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4422#L1403-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4099#L620-39 assume !(1 == ~t4_pc~0); 4100#L620-41 is_transmit4_triggered_~__retres1~4#1 := 0; 4289#L631-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4124#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4125#L1411-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 4396#L1411-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4717#L639-39 assume 1 == ~t5_pc~0; 4508#L640-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 3848#L650-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3849#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3208#L1419-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 3209#L1419-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4136#L658-39 assume 1 == ~t6_pc~0; 4119#L659-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 4120#L669-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4569#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4311#L1427-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 4286#L1427-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4287#L677-39 assume !(1 == ~t7_pc~0); 3928#L677-41 is_transmit7_triggered_~__retres1~7#1 := 0; 3386#L688-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3387#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 3442#L1435-39 assume !(0 != activate_threads_~tmp___6~0#1); 3443#L1435-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4025#L696-39 assume 1 == ~t8_pc~0; 3991#L697-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 3871#L707-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3872#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 4161#L1443-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 4129#L1443-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4005#L715-39 assume 1 == ~t9_pc~0; 3186#L716-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 3187#L726-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3263#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 3264#L1451-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 4333#L1451-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 4334#L734-39 assume !(1 == ~t10_pc~0); 3697#L734-41 is_transmit10_triggered_~__retres1~10#1 := 0; 3698#L745-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 4028#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 3340#L1459-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 3341#L1459-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 4582#L753-39 assume 1 == ~t11_pc~0; 3970#L754-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 3260#L764-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 4158#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 3996#L1467-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 3997#L1467-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4096#L1237-3 assume 1 == ~M_E~0;~M_E~0 := 2; 4097#L1237-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4354#L1242-3 assume !(1 == ~T2_E~0); 4355#L1247-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4565#L1252-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4279#L1257-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 4280#L1262-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 4538#L1267-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 4586#L1272-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 4688#L1277-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 3413#L1282-3 assume !(1 == ~T10_E~0); 3414#L1287-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 3323#L1292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 3324#L1297-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4460#L1302-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4461#L1307-3 assume 1 == ~E_3~0;~E_3~0 := 2; 4641#L1312-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4714#L1317-3 assume 1 == ~E_5~0;~E_5~0 := 2; 4374#L1322-3 assume !(1 == ~E_6~0); 4375#L1327-3 assume 1 == ~E_7~0;~E_7~0 := 2; 3379#L1332-3 assume 1 == ~E_8~0;~E_8~0 := 2; 3356#L1337-3 assume 1 == ~E_9~0;~E_9~0 := 2; 3357#L1342-3 assume 1 == ~E_10~0;~E_10~0 := 2; 4066#L1347-3 assume 1 == ~E_11~0;~E_11~0 := 2; 4188#L1352-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 4189#L848-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 3305#L910-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 3511#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 3512#L1697 assume !(0 == start_simulation_~tmp~3#1); 4086#L1697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 4087#L848-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 3430#L910-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 3198#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; 3199#L1652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4155#L1659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4156#stop_simulation_returnLabel#1 start_simulation_#t~ret32#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 4449#L1710 assume !(0 != start_simulation_~tmp___0~1#1); 4450#L1678-2 [2022-12-13 17:13:28,969 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 17:13:28,969 INFO L85 PathProgramCache]: Analyzing trace with hash 430082112, now seen corresponding path program 2 times [2022-12-13 17:13:28,969 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 17:13:28,970 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [55823441] [2022-12-13 17:13:28,970 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 17:13:28,970 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 17:13:28,981 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 17:13:29,019 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 17:13:29,019 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 17:13:29,019 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [55823441] [2022-12-13 17:13:29,019 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [55823441] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 17:13:29,020 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 17:13:29,020 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 17:13:29,020 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [509181304] [2022-12-13 17:13:29,020 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 17:13:29,021 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 17:13:29,021 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 17:13:29,021 INFO L85 PathProgramCache]: Analyzing trace with hash -1639996467, now seen corresponding path program 1 times [2022-12-13 17:13:29,022 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 17:13:29,022 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [894884569] [2022-12-13 17:13:29,022 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 17:13:29,022 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 17:13:29,043 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 17:13:29,124 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 17:13:29,124 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 17:13:29,124 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [894884569] [2022-12-13 17:13:29,124 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [894884569] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 17:13:29,124 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 17:13:29,125 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 17:13:29,125 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [410762435] [2022-12-13 17:13:29,125 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 17:13:29,125 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 17:13:29,126 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 17:13:29,126 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 17:13:29,126 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 17:13:29,127 INFO L87 Difference]: Start difference. First operand 1566 states and 2325 transitions. cyclomatic complexity: 760 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 17:13:29,157 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 17:13:29,158 INFO L93 Difference]: Finished difference Result 1566 states and 2324 transitions. [2022-12-13 17:13:29,158 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1566 states and 2324 transitions. [2022-12-13 17:13:29,163 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1415 [2022-12-13 17:13:29,168 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1566 states to 1566 states and 2324 transitions. [2022-12-13 17:13:29,168 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1566 [2022-12-13 17:13:29,169 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1566 [2022-12-13 17:13:29,169 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1566 states and 2324 transitions. [2022-12-13 17:13:29,170 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 17:13:29,170 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1566 states and 2324 transitions. [2022-12-13 17:13:29,172 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1566 states and 2324 transitions. [2022-12-13 17:13:29,185 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1566 to 1566. [2022-12-13 17:13:29,187 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1566 states, 1566 states have (on average 1.4840357598978289) internal successors, (2324), 1565 states have internal predecessors, (2324), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 17:13:29,190 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1566 states to 1566 states and 2324 transitions. [2022-12-13 17:13:29,190 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1566 states and 2324 transitions. [2022-12-13 17:13:29,191 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 17:13:29,191 INFO L428 stractBuchiCegarLoop]: Abstraction has 1566 states and 2324 transitions. [2022-12-13 17:13:29,191 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2022-12-13 17:13:29,191 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1566 states and 2324 transitions. [2022-12-13 17:13:29,196 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1415 [2022-12-13 17:13:29,196 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 17:13:29,196 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 17:13:29,197 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 17:13:29,197 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 17:13:29,198 INFO L748 eck$LassoCheckResult]: Stem: 6547#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 6548#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 7322#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 7323#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6521#L780 assume 1 == ~m_i~0;~m_st~0 := 0; 6522#L780-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7751#L785-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 7718#L790-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 7719#L795-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 6876#L800-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 6877#L805-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 7291#L810-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 7687#L815-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 6784#L820-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 6785#L825-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 6675#L830-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 6676#L835-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7618#L1109 assume !(0 == ~M_E~0); 7634#L1109-2 assume !(0 == ~T1_E~0); 6684#L1114-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 6685#L1119-1 assume !(0 == ~T3_E~0); 7690#L1124-1 assume !(0 == ~T4_E~0); 6335#L1129-1 assume !(0 == ~T5_E~0); 6336#L1134-1 assume !(0 == ~T6_E~0); 6963#L1139-1 assume !(0 == ~T7_E~0); 7625#L1144-1 assume !(0 == ~T8_E~0); 7501#L1149-1 assume !(0 == ~T9_E~0); 6446#L1154-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 6447#L1159-1 assume !(0 == ~T11_E~0); 7491#L1164-1 assume !(0 == ~E_M~0); 6838#L1169-1 assume !(0 == ~E_1~0); 6736#L1174-1 assume !(0 == ~E_2~0); 6600#L1179-1 assume !(0 == ~E_3~0); 6527#L1184-1 assume !(0 == ~E_4~0); 6528#L1189-1 assume !(0 == ~E_5~0); 6560#L1194-1 assume 0 == ~E_6~0;~E_6~0 := 1; 6643#L1199-1 assume !(0 == ~E_7~0); 7510#L1204-1 assume !(0 == ~E_8~0); 7451#L1209-1 assume !(0 == ~E_9~0); 7452#L1214-1 assume !(0 == ~E_10~0); 7764#L1219-1 assume !(0 == ~E_11~0); 7850#L1224-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6855#L544 assume 1 == ~m_pc~0; 6856#L545 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 7673#L555 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7211#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6489#L1379 assume !(0 != activate_threads_~tmp~1#1); 6490#L1379-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7278#L563 assume !(1 == ~t1_pc~0); 7080#L563-2 is_transmit1_triggered_~__retres1~1#1 := 0; 6345#L574 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6346#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 7398#L1387 assume !(0 != activate_threads_~tmp___0~0#1); 6341#L1387-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6342#L582 assume 1 == ~t2_pc~0; 7058#L583 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 7403#L593 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6680#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 6681#L1395 assume !(0 != activate_threads_~tmp___1~0#1); 6374#L1395-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6375#L601 assume !(1 == ~t3_pc~0); 7075#L601-2 is_transmit3_triggered_~__retres1~3#1 := 0; 7074#L612 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7529#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 7436#L1403 assume !(0 != activate_threads_~tmp___2~0#1); 7437#L1403-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7384#L620 assume 1 == ~t4_pc~0; 6355#L621 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 6356#L631 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6388#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 6389#L1411 assume !(0 != activate_threads_~tmp___3~0#1); 7288#L1411-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7469#L639 assume 1 == ~t5_pc~0; 7358#L640 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 6648#L650 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6649#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 7308#L1419 assume !(0 != activate_threads_~tmp___4~0#1); 7309#L1419-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7243#L658 assume !(1 == ~t6_pc~0); 6852#L658-2 is_transmit6_triggered_~__retres1~6#1 := 0; 6853#L669 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6672#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 6673#L1427 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 7440#L1427-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6695#L677 assume 1 == ~t7_pc~0; 6696#L678 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 6593#L688 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 7590#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 7712#L1435 assume !(0 != activate_threads_~tmp___6~0#1); 7713#L1435-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 7783#L696 assume !(1 == ~t8_pc~0); 6916#L696-2 is_transmit8_triggered_~__retres1~8#1 := 0; 6917#L707 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 7749#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 7786#L1443 assume !(0 != activate_threads_~tmp___7~0#1); 7830#L1443-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 7346#L715 assume 1 == ~t9_pc~0; 7347#L716 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 7016#L726 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 6734#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 6735#L1451 assume !(0 != activate_threads_~tmp___8~0#1); 7329#L1451-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 7585#L734 assume !(1 == ~t10_pc~0); 7586#L734-2 is_transmit10_triggered_~__retres1~10#1 := 0; 6810#L745 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 6811#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 7531#L1459 assume !(0 != activate_threads_~tmp___9~0#1); 7532#L1459-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 6890#L753 assume 1 == ~t11_pc~0; 6891#L754 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 7445#L764 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 7758#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 7161#L1467 assume !(0 != activate_threads_~tmp___10~0#1); 7162#L1467-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7218#L1237 assume !(1 == ~M_E~0); 7219#L1237-2 assume !(1 == ~T1_E~0); 7813#L1242-1 assume !(1 == ~T2_E~0); 6984#L1247-1 assume !(1 == ~T3_E~0); 6985#L1252-1 assume !(1 == ~T4_E~0); 6753#L1257-1 assume !(1 == ~T5_E~0); 6754#L1262-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 7607#L1267-1 assume !(1 == ~T7_E~0); 7705#L1272-1 assume !(1 == ~T8_E~0); 7069#L1277-1 assume !(1 == ~T9_E~0); 7070#L1282-1 assume !(1 == ~T10_E~0); 7478#L1287-1 assume !(1 == ~T11_E~0); 7479#L1292-1 assume !(1 == ~E_M~0); 7439#L1297-1 assume !(1 == ~E_1~0); 6881#L1302-1 assume 1 == ~E_2~0;~E_2~0 := 2; 6882#L1307-1 assume !(1 == ~E_3~0); 7694#L1312-1 assume !(1 == ~E_4~0); 7115#L1317-1 assume !(1 == ~E_5~0); 7116#L1322-1 assume !(1 == ~E_6~0); 6825#L1327-1 assume !(1 == ~E_7~0); 6826#L1332-1 assume !(1 == ~E_8~0); 7397#L1337-1 assume !(1 == ~E_9~0); 7332#L1342-1 assume 1 == ~E_10~0;~E_10~0 := 2; 7333#L1347-1 assume !(1 == ~E_11~0); 7693#L1352-1 assume { :end_inline_reset_delta_events } true; 7589#L1678-2 [2022-12-13 17:13:29,198 INFO L750 eck$LassoCheckResult]: Loop: 7589#L1678-2 assume !false; 7387#L1679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 7247#L1084 assume !false; 7182#L921 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 7183#L848 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 6465#L910 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 7679#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 6385#L925 assume !(0 != eval_~tmp~0#1); 6387#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 6874#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 6875#L1109-3 assume 0 == ~M_E~0;~M_E~0 := 1; 6358#L1109-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 6359#L1114-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7441#L1119-3 assume !(0 == ~T3_E~0); 7442#L1124-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 7466#L1129-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 7467#L1134-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 7630#L1139-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 7682#L1144-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 6865#L1149-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 6866#L1154-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 7122#L1159-3 assume !(0 == ~T11_E~0); 7123#L1164-3 assume 0 == ~E_M~0;~E_M~0 := 1; 7380#L1169-3 assume 0 == ~E_1~0;~E_1~0 := 1; 7381#L1174-3 assume 0 == ~E_2~0;~E_2~0 := 1; 7429#L1179-3 assume 0 == ~E_3~0;~E_3~0 := 1; 7430#L1184-3 assume 0 == ~E_4~0;~E_4~0 := 1; 7570#L1189-3 assume 0 == ~E_5~0;~E_5~0 := 1; 7272#L1194-3 assume 0 == ~E_6~0;~E_6~0 := 1; 6622#L1199-3 assume !(0 == ~E_7~0); 6623#L1204-3 assume 0 == ~E_8~0;~E_8~0 := 1; 6845#L1209-3 assume 0 == ~E_9~0;~E_9~0 := 1; 6308#L1214-3 assume 0 == ~E_10~0;~E_10~0 := 1; 6309#L1219-3 assume 0 == ~E_11~0;~E_11~0 := 1; 7026#L1224-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7027#L544-39 assume !(1 == ~m_pc~0); 6296#L544-41 is_master_triggered_~__retres1~0#1 := 0; 6297#L555-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7349#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6703#L1379-39 assume !(0 != activate_threads_~tmp~1#1); 6704#L1379-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7557#L563-39 assume !(1 == ~t1_pc~0); 6441#L563-41 is_transmit1_triggered_~__retres1~1#1 := 0; 6442#L574-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7841#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 7842#L1387-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 7845#L1387-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7664#L582-39 assume 1 == ~t2_pc~0; 6765#L583-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 6767#L593-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7092#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 7093#L1395-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 6536#L1395-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6320#L601-39 assume 1 == ~t3_pc~0; 6321#L602-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 6369#L612-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7527#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 7852#L1403-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 7561#L1403-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7238#L620-39 assume !(1 == ~t4_pc~0); 7239#L620-41 is_transmit4_triggered_~__retres1~4#1 := 0; 7428#L631-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7263#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 7264#L1411-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 7535#L1411-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7856#L639-39 assume !(1 == ~t5_pc~0); 7648#L639-41 is_transmit5_triggered_~__retres1~5#1 := 0; 6987#L650-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6988#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 6347#L1419-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 6348#L1419-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7275#L658-39 assume 1 == ~t6_pc~0; 7258#L659-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 7259#L669-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 7708#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 7450#L1427-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 7425#L1427-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 7426#L677-39 assume !(1 == ~t7_pc~0); 7067#L677-41 is_transmit7_triggered_~__retres1~7#1 := 0; 6525#L688-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 6526#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 6581#L1435-39 assume !(0 != activate_threads_~tmp___6~0#1); 6582#L1435-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 7164#L696-39 assume 1 == ~t8_pc~0; 7130#L697-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 7010#L707-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 7011#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 7300#L1443-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 7268#L1443-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 7144#L715-39 assume 1 == ~t9_pc~0; 6325#L716-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 6326#L726-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 6402#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 6403#L1451-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 7472#L1451-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 7473#L734-39 assume !(1 == ~t10_pc~0); 6836#L734-41 is_transmit10_triggered_~__retres1~10#1 := 0; 6837#L745-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 7167#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 6479#L1459-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 6480#L1459-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 7721#L753-39 assume 1 == ~t11_pc~0; 7109#L754-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 6399#L764-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 7297#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 7135#L1467-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 7136#L1467-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7235#L1237-3 assume 1 == ~M_E~0;~M_E~0 := 2; 7236#L1237-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 7493#L1242-3 assume !(1 == ~T2_E~0); 7494#L1247-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 7704#L1252-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 7418#L1257-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 7419#L1262-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 7677#L1267-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 7725#L1272-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 7827#L1277-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 6552#L1282-3 assume !(1 == ~T10_E~0); 6553#L1287-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 6462#L1292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 6463#L1297-3 assume 1 == ~E_1~0;~E_1~0 := 2; 7599#L1302-3 assume 1 == ~E_2~0;~E_2~0 := 2; 7600#L1307-3 assume 1 == ~E_3~0;~E_3~0 := 2; 7780#L1312-3 assume 1 == ~E_4~0;~E_4~0 := 2; 7853#L1317-3 assume 1 == ~E_5~0;~E_5~0 := 2; 7513#L1322-3 assume !(1 == ~E_6~0); 7514#L1327-3 assume 1 == ~E_7~0;~E_7~0 := 2; 6518#L1332-3 assume 1 == ~E_8~0;~E_8~0 := 2; 6495#L1337-3 assume 1 == ~E_9~0;~E_9~0 := 2; 6496#L1342-3 assume 1 == ~E_10~0;~E_10~0 := 2; 7205#L1347-3 assume 1 == ~E_11~0;~E_11~0 := 2; 7327#L1352-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 7328#L848-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 6444#L910-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 6650#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 6651#L1697 assume !(0 == start_simulation_~tmp~3#1); 7225#L1697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 7226#L848-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 6569#L910-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 6337#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; 6338#L1652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 7294#L1659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 7295#stop_simulation_returnLabel#1 start_simulation_#t~ret32#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 7588#L1710 assume !(0 != start_simulation_~tmp___0~1#1); 7589#L1678-2 [2022-12-13 17:13:29,198 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 17:13:29,199 INFO L85 PathProgramCache]: Analyzing trace with hash -968871490, now seen corresponding path program 1 times [2022-12-13 17:13:29,199 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 17:13:29,199 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1943367135] [2022-12-13 17:13:29,199 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 17:13:29,199 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 17:13:29,208 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 17:13:29,235 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 17:13:29,236 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 17:13:29,236 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1943367135] [2022-12-13 17:13:29,236 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1943367135] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 17:13:29,236 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 17:13:29,236 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 17:13:29,236 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [31924415] [2022-12-13 17:13:29,237 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 17:13:29,237 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 17:13:29,237 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 17:13:29,238 INFO L85 PathProgramCache]: Analyzing trace with hash 1717943630, now seen corresponding path program 1 times [2022-12-13 17:13:29,238 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 17:13:29,238 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [678979864] [2022-12-13 17:13:29,238 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 17:13:29,238 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 17:13:29,250 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 17:13:29,289 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 17:13:29,289 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 17:13:29,289 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [678979864] [2022-12-13 17:13:29,290 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [678979864] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 17:13:29,290 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 17:13:29,290 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 17:13:29,290 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [148050120] [2022-12-13 17:13:29,290 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 17:13:29,291 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 17:13:29,291 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 17:13:29,291 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 17:13:29,291 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 17:13:29,292 INFO L87 Difference]: Start difference. First operand 1566 states and 2324 transitions. cyclomatic complexity: 759 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 17:13:29,318 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 17:13:29,318 INFO L93 Difference]: Finished difference Result 1566 states and 2323 transitions. [2022-12-13 17:13:29,318 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1566 states and 2323 transitions. [2022-12-13 17:13:29,324 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1415 [2022-12-13 17:13:29,328 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1566 states to 1566 states and 2323 transitions. [2022-12-13 17:13:29,328 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1566 [2022-12-13 17:13:29,329 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1566 [2022-12-13 17:13:29,329 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1566 states and 2323 transitions. [2022-12-13 17:13:29,331 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 17:13:29,331 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1566 states and 2323 transitions. [2022-12-13 17:13:29,332 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1566 states and 2323 transitions. [2022-12-13 17:13:29,344 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1566 to 1566. [2022-12-13 17:13:29,346 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1566 states, 1566 states have (on average 1.483397190293742) internal successors, (2323), 1565 states have internal predecessors, (2323), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 17:13:29,349 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1566 states to 1566 states and 2323 transitions. [2022-12-13 17:13:29,349 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1566 states and 2323 transitions. [2022-12-13 17:13:29,349 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 17:13:29,350 INFO L428 stractBuchiCegarLoop]: Abstraction has 1566 states and 2323 transitions. [2022-12-13 17:13:29,350 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2022-12-13 17:13:29,350 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1566 states and 2323 transitions. [2022-12-13 17:13:29,354 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1415 [2022-12-13 17:13:29,354 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 17:13:29,354 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 17:13:29,355 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 17:13:29,355 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 17:13:29,356 INFO L748 eck$LassoCheckResult]: Stem: 9686#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 9687#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 10462#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 10463#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 9660#L780 assume 1 == ~m_i~0;~m_st~0 := 0; 9661#L780-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 10890#L785-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 10857#L790-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 10858#L795-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 10015#L800-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 10016#L805-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 10430#L810-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 10826#L815-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 9925#L820-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 9926#L825-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 9814#L830-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 9815#L835-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 10759#L1109 assume !(0 == ~M_E~0); 10773#L1109-2 assume !(0 == ~T1_E~0); 9823#L1114-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 9824#L1119-1 assume !(0 == ~T3_E~0); 10829#L1124-1 assume !(0 == ~T4_E~0); 9474#L1129-1 assume !(0 == ~T5_E~0); 9475#L1134-1 assume !(0 == ~T6_E~0); 10102#L1139-1 assume !(0 == ~T7_E~0); 10764#L1144-1 assume !(0 == ~T8_E~0); 10640#L1149-1 assume !(0 == ~T9_E~0); 9587#L1154-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 9588#L1159-1 assume !(0 == ~T11_E~0); 10630#L1164-1 assume !(0 == ~E_M~0); 9977#L1169-1 assume !(0 == ~E_1~0); 9875#L1174-1 assume !(0 == ~E_2~0); 9744#L1179-1 assume !(0 == ~E_3~0); 9666#L1184-1 assume !(0 == ~E_4~0); 9667#L1189-1 assume !(0 == ~E_5~0); 9699#L1194-1 assume 0 == ~E_6~0;~E_6~0 := 1; 9786#L1199-1 assume !(0 == ~E_7~0); 10649#L1204-1 assume !(0 == ~E_8~0); 10591#L1209-1 assume !(0 == ~E_9~0); 10592#L1214-1 assume !(0 == ~E_10~0); 10903#L1219-1 assume !(0 == ~E_11~0); 10989#L1224-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9996#L544 assume 1 == ~m_pc~0; 9997#L545 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 10812#L555 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10350#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 9628#L1379 assume !(0 != activate_threads_~tmp~1#1); 9629#L1379-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10419#L563 assume !(1 == ~t1_pc~0); 10219#L563-2 is_transmit1_triggered_~__retres1~1#1 := 0; 9484#L574 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9485#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 10537#L1387 assume !(0 != activate_threads_~tmp___0~0#1); 9480#L1387-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9481#L582 assume 1 == ~t2_pc~0; 10197#L583 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 10542#L593 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9819#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 9820#L1395 assume !(0 != activate_threads_~tmp___1~0#1); 9513#L1395-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9514#L601 assume !(1 == ~t3_pc~0); 10214#L601-2 is_transmit3_triggered_~__retres1~3#1 := 0; 10213#L612 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10668#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 10575#L1403 assume !(0 != activate_threads_~tmp___2~0#1); 10576#L1403-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10523#L620 assume 1 == ~t4_pc~0; 9494#L621 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 9495#L631 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9527#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 9528#L1411 assume !(0 != activate_threads_~tmp___3~0#1); 10427#L1411-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10609#L639 assume 1 == ~t5_pc~0; 10497#L640 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 9789#L650 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9790#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 10447#L1419 assume !(0 != activate_threads_~tmp___4~0#1); 10448#L1419-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 10384#L658 assume !(1 == ~t6_pc~0); 9991#L658-2 is_transmit6_triggered_~__retres1~6#1 := 0; 9992#L669 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 9811#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 9812#L1427 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 10579#L1427-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9836#L677 assume 1 == ~t7_pc~0; 9837#L678 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 9735#L688 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 10729#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 10851#L1435 assume !(0 != activate_threads_~tmp___6~0#1); 10852#L1435-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 10922#L696 assume !(1 == ~t8_pc~0); 10056#L696-2 is_transmit8_triggered_~__retres1~8#1 := 0; 10057#L707 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 10888#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 10925#L1443 assume !(0 != activate_threads_~tmp___7~0#1); 10969#L1443-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 10485#L715 assume 1 == ~t9_pc~0; 10486#L716 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 10155#L726 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 9873#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 9874#L1451 assume !(0 != activate_threads_~tmp___8~0#1); 10468#L1451-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 10726#L734 assume !(1 == ~t10_pc~0); 10727#L734-2 is_transmit10_triggered_~__retres1~10#1 := 0; 9949#L745 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 9950#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 10670#L1459 assume !(0 != activate_threads_~tmp___9~0#1); 10671#L1459-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 10029#L753 assume 1 == ~t11_pc~0; 10030#L754 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 10584#L764 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 10897#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 10302#L1467 assume !(0 != activate_threads_~tmp___10~0#1); 10303#L1467-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10359#L1237 assume !(1 == ~M_E~0); 10360#L1237-2 assume !(1 == ~T1_E~0); 10953#L1242-1 assume !(1 == ~T2_E~0); 10123#L1247-1 assume !(1 == ~T3_E~0); 10124#L1252-1 assume !(1 == ~T4_E~0); 9892#L1257-1 assume !(1 == ~T5_E~0); 9893#L1262-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 10746#L1267-1 assume !(1 == ~T7_E~0); 10844#L1272-1 assume !(1 == ~T8_E~0); 10208#L1277-1 assume !(1 == ~T9_E~0); 10209#L1282-1 assume !(1 == ~T10_E~0); 10617#L1287-1 assume !(1 == ~T11_E~0); 10618#L1292-1 assume !(1 == ~E_M~0); 10578#L1297-1 assume !(1 == ~E_1~0); 10020#L1302-1 assume 1 == ~E_2~0;~E_2~0 := 2; 10021#L1307-1 assume !(1 == ~E_3~0); 10833#L1312-1 assume !(1 == ~E_4~0); 10254#L1317-1 assume !(1 == ~E_5~0); 10255#L1322-1 assume !(1 == ~E_6~0); 9964#L1327-1 assume !(1 == ~E_7~0); 9965#L1332-1 assume !(1 == ~E_8~0); 10536#L1337-1 assume !(1 == ~E_9~0); 10471#L1342-1 assume 1 == ~E_10~0;~E_10~0 := 2; 10472#L1347-1 assume !(1 == ~E_11~0); 10832#L1352-1 assume { :end_inline_reset_delta_events } true; 10725#L1678-2 [2022-12-13 17:13:29,356 INFO L750 eck$LassoCheckResult]: Loop: 10725#L1678-2 assume !false; 10528#L1679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 10386#L1084 assume !false; 10321#L921 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 10322#L848 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 9604#L910 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 10818#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 9524#L925 assume !(0 != eval_~tmp~0#1); 9526#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 10013#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 10014#L1109-3 assume 0 == ~M_E~0;~M_E~0 := 1; 9497#L1109-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 9498#L1114-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 10580#L1119-3 assume !(0 == ~T3_E~0); 10581#L1124-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 10606#L1129-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 10607#L1134-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 10769#L1139-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 10821#L1144-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 10004#L1149-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 10005#L1154-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 10263#L1159-3 assume !(0 == ~T11_E~0); 10264#L1164-3 assume 0 == ~E_M~0;~E_M~0 := 1; 10519#L1169-3 assume 0 == ~E_1~0;~E_1~0 := 1; 10520#L1174-3 assume 0 == ~E_2~0;~E_2~0 := 1; 10568#L1179-3 assume 0 == ~E_3~0;~E_3~0 := 1; 10569#L1184-3 assume 0 == ~E_4~0;~E_4~0 := 1; 10709#L1189-3 assume 0 == ~E_5~0;~E_5~0 := 1; 10411#L1194-3 assume 0 == ~E_6~0;~E_6~0 := 1; 9761#L1199-3 assume !(0 == ~E_7~0); 9762#L1204-3 assume 0 == ~E_8~0;~E_8~0 := 1; 9984#L1209-3 assume 0 == ~E_9~0;~E_9~0 := 1; 9447#L1214-3 assume 0 == ~E_10~0;~E_10~0 := 1; 9448#L1219-3 assume 0 == ~E_11~0;~E_11~0 := 1; 10165#L1224-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10166#L544-39 assume !(1 == ~m_pc~0); 9435#L544-41 is_master_triggered_~__retres1~0#1 := 0; 9436#L555-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10488#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 9842#L1379-39 assume !(0 != activate_threads_~tmp~1#1); 9843#L1379-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10696#L563-39 assume !(1 == ~t1_pc~0); 9580#L563-41 is_transmit1_triggered_~__retres1~1#1 := 0; 9581#L574-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10980#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 10981#L1387-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 10984#L1387-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10803#L582-39 assume 1 == ~t2_pc~0; 9904#L583-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 9906#L593-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10231#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 10232#L1395-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 9675#L1395-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9459#L601-39 assume 1 == ~t3_pc~0; 9460#L602-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 9508#L612-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10666#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 10991#L1403-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 10700#L1403-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10377#L620-39 assume !(1 == ~t4_pc~0); 10378#L620-41 is_transmit4_triggered_~__retres1~4#1 := 0; 10567#L631-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10402#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 10403#L1411-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 10674#L1411-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10995#L639-39 assume 1 == ~t5_pc~0; 10786#L640-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 10126#L650-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10127#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 9486#L1419-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 9487#L1419-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 10414#L658-39 assume 1 == ~t6_pc~0; 10397#L659-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 10398#L669-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 10847#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 10589#L1427-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 10564#L1427-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 10565#L677-39 assume 1 == ~t7_pc~0; 10529#L678-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 9664#L688-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 9665#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 9720#L1435-39 assume !(0 != activate_threads_~tmp___6~0#1); 9721#L1435-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 10301#L696-39 assume 1 == ~t8_pc~0; 10269#L697-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 10149#L707-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 10150#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 10439#L1443-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 10407#L1443-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 10283#L715-39 assume 1 == ~t9_pc~0; 9464#L716-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 9465#L726-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 9541#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 9542#L1451-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 10611#L1451-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 10612#L734-39 assume !(1 == ~t10_pc~0); 9975#L734-41 is_transmit10_triggered_~__retres1~10#1 := 0; 9976#L745-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 10306#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 9618#L1459-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 9619#L1459-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 10860#L753-39 assume !(1 == ~t11_pc~0); 9537#L753-41 is_transmit11_triggered_~__retres1~11#1 := 0; 9538#L764-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 10436#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 10274#L1467-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 10275#L1467-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10374#L1237-3 assume 1 == ~M_E~0;~M_E~0 := 2; 10375#L1237-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 10632#L1242-3 assume !(1 == ~T2_E~0); 10633#L1247-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 10843#L1252-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 10557#L1257-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 10558#L1262-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 10815#L1267-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 10864#L1272-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 10966#L1277-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 9691#L1282-3 assume !(1 == ~T10_E~0); 9692#L1287-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 9601#L1292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 9602#L1297-3 assume 1 == ~E_1~0;~E_1~0 := 2; 10738#L1302-3 assume 1 == ~E_2~0;~E_2~0 := 2; 10739#L1307-3 assume 1 == ~E_3~0;~E_3~0 := 2; 10919#L1312-3 assume 1 == ~E_4~0;~E_4~0 := 2; 10992#L1317-3 assume 1 == ~E_5~0;~E_5~0 := 2; 10652#L1322-3 assume !(1 == ~E_6~0); 10653#L1327-3 assume 1 == ~E_7~0;~E_7~0 := 2; 9657#L1332-3 assume 1 == ~E_8~0;~E_8~0 := 2; 9634#L1337-3 assume 1 == ~E_9~0;~E_9~0 := 2; 9635#L1342-3 assume 1 == ~E_10~0;~E_10~0 := 2; 10344#L1347-3 assume 1 == ~E_11~0;~E_11~0 := 2; 10466#L1352-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 10467#L848-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 9583#L910-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 9787#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 9788#L1697 assume !(0 == start_simulation_~tmp~3#1); 10364#L1697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 10365#L848-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 9708#L910-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 9476#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; 9477#L1652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 10433#L1659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 10434#stop_simulation_returnLabel#1 start_simulation_#t~ret32#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 10724#L1710 assume !(0 != start_simulation_~tmp___0~1#1); 10725#L1678-2 [2022-12-13 17:13:29,357 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 17:13:29,357 INFO L85 PathProgramCache]: Analyzing trace with hash -1332337988, now seen corresponding path program 1 times [2022-12-13 17:13:29,357 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 17:13:29,357 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1874112126] [2022-12-13 17:13:29,357 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 17:13:29,357 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 17:13:29,366 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 17:13:29,409 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 17:13:29,409 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 17:13:29,409 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1874112126] [2022-12-13 17:13:29,409 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1874112126] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 17:13:29,409 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 17:13:29,410 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 17:13:29,410 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [626383263] [2022-12-13 17:13:29,410 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 17:13:29,410 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 17:13:29,411 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 17:13:29,411 INFO L85 PathProgramCache]: Analyzing trace with hash -1878960435, now seen corresponding path program 1 times [2022-12-13 17:13:29,411 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 17:13:29,411 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1018697113] [2022-12-13 17:13:29,411 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 17:13:29,412 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 17:13:29,423 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 17:13:29,455 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 17:13:29,456 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 17:13:29,456 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1018697113] [2022-12-13 17:13:29,456 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1018697113] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 17:13:29,456 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 17:13:29,456 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 17:13:29,457 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1343939452] [2022-12-13 17:13:29,457 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 17:13:29,457 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 17:13:29,457 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 17:13:29,458 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 17:13:29,458 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 17:13:29,458 INFO L87 Difference]: Start difference. First operand 1566 states and 2323 transitions. cyclomatic complexity: 758 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 17:13:29,483 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 17:13:29,483 INFO L93 Difference]: Finished difference Result 1566 states and 2322 transitions. [2022-12-13 17:13:29,483 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1566 states and 2322 transitions. [2022-12-13 17:13:29,494 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1415 [2022-12-13 17:13:29,498 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1566 states to 1566 states and 2322 transitions. [2022-12-13 17:13:29,498 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1566 [2022-12-13 17:13:29,499 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1566 [2022-12-13 17:13:29,499 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1566 states and 2322 transitions. [2022-12-13 17:13:29,501 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 17:13:29,501 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1566 states and 2322 transitions. [2022-12-13 17:13:29,502 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1566 states and 2322 transitions. [2022-12-13 17:13:29,516 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1566 to 1566. [2022-12-13 17:13:29,519 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1566 states, 1566 states have (on average 1.4827586206896552) internal successors, (2322), 1565 states have internal predecessors, (2322), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 17:13:29,521 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1566 states to 1566 states and 2322 transitions. [2022-12-13 17:13:29,521 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1566 states and 2322 transitions. [2022-12-13 17:13:29,522 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 17:13:29,523 INFO L428 stractBuchiCegarLoop]: Abstraction has 1566 states and 2322 transitions. [2022-12-13 17:13:29,523 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2022-12-13 17:13:29,523 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1566 states and 2322 transitions. [2022-12-13 17:13:29,529 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1415 [2022-12-13 17:13:29,529 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 17:13:29,529 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 17:13:29,531 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 17:13:29,531 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 17:13:29,532 INFO L748 eck$LassoCheckResult]: Stem: 12825#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 12826#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 13600#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 13601#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 12799#L780 assume 1 == ~m_i~0;~m_st~0 := 0; 12800#L780-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 14029#L785-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 13996#L790-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 13997#L795-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 13154#L800-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 13155#L805-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 13569#L810-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 13965#L815-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 13062#L820-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 13063#L825-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 12953#L830-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 12954#L835-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 13896#L1109 assume !(0 == ~M_E~0); 13912#L1109-2 assume !(0 == ~T1_E~0); 12962#L1114-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 12963#L1119-1 assume !(0 == ~T3_E~0); 13968#L1124-1 assume !(0 == ~T4_E~0); 12613#L1129-1 assume !(0 == ~T5_E~0); 12614#L1134-1 assume !(0 == ~T6_E~0); 13241#L1139-1 assume !(0 == ~T7_E~0); 13903#L1144-1 assume !(0 == ~T8_E~0); 13779#L1149-1 assume !(0 == ~T9_E~0); 12724#L1154-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 12725#L1159-1 assume !(0 == ~T11_E~0); 13769#L1164-1 assume !(0 == ~E_M~0); 13116#L1169-1 assume !(0 == ~E_1~0); 13014#L1174-1 assume !(0 == ~E_2~0); 12880#L1179-1 assume !(0 == ~E_3~0); 12805#L1184-1 assume !(0 == ~E_4~0); 12806#L1189-1 assume !(0 == ~E_5~0); 12838#L1194-1 assume 0 == ~E_6~0;~E_6~0 := 1; 12921#L1199-1 assume !(0 == ~E_7~0); 13788#L1204-1 assume !(0 == ~E_8~0); 13729#L1209-1 assume !(0 == ~E_9~0); 13730#L1214-1 assume !(0 == ~E_10~0); 14042#L1219-1 assume !(0 == ~E_11~0); 14128#L1224-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13133#L544 assume 1 == ~m_pc~0; 13134#L545 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 13951#L555 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13489#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 12767#L1379 assume !(0 != activate_threads_~tmp~1#1); 12768#L1379-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 13556#L563 assume !(1 == ~t1_pc~0); 13358#L563-2 is_transmit1_triggered_~__retres1~1#1 := 0; 12623#L574 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12624#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 13676#L1387 assume !(0 != activate_threads_~tmp___0~0#1); 12619#L1387-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12620#L582 assume 1 == ~t2_pc~0; 13336#L583 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 13681#L593 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12958#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 12959#L1395 assume !(0 != activate_threads_~tmp___1~0#1); 12652#L1395-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12653#L601 assume !(1 == ~t3_pc~0); 13353#L601-2 is_transmit3_triggered_~__retres1~3#1 := 0; 13352#L612 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13807#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 13714#L1403 assume !(0 != activate_threads_~tmp___2~0#1); 13715#L1403-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13662#L620 assume 1 == ~t4_pc~0; 12633#L621 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 12634#L631 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12666#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 12667#L1411 assume !(0 != activate_threads_~tmp___3~0#1); 13566#L1411-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 13748#L639 assume 1 == ~t5_pc~0; 13636#L640 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 12928#L650 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12929#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 13586#L1419 assume !(0 != activate_threads_~tmp___4~0#1); 13587#L1419-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 13521#L658 assume !(1 == ~t6_pc~0); 13130#L658-2 is_transmit6_triggered_~__retres1~6#1 := 0; 13131#L669 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12950#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 12951#L1427 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 13718#L1427-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12973#L677 assume 1 == ~t7_pc~0; 12974#L678 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 12871#L688 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 13868#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 13990#L1435 assume !(0 != activate_threads_~tmp___6~0#1); 13991#L1435-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 14061#L696 assume !(1 == ~t8_pc~0); 13194#L696-2 is_transmit8_triggered_~__retres1~8#1 := 0; 13195#L707 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 14027#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 14064#L1443 assume !(0 != activate_threads_~tmp___7~0#1); 14108#L1443-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 13624#L715 assume 1 == ~t9_pc~0; 13625#L716 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 13294#L726 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 13012#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 13013#L1451 assume !(0 != activate_threads_~tmp___8~0#1); 13607#L1451-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 13865#L734 assume !(1 == ~t10_pc~0); 13866#L734-2 is_transmit10_triggered_~__retres1~10#1 := 0; 13088#L745 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 13089#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 13809#L1459 assume !(0 != activate_threads_~tmp___9~0#1); 13810#L1459-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 13168#L753 assume 1 == ~t11_pc~0; 13169#L754 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 13723#L764 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 14036#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 13439#L1467 assume !(0 != activate_threads_~tmp___10~0#1); 13440#L1467-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13496#L1237 assume !(1 == ~M_E~0); 13497#L1237-2 assume !(1 == ~T1_E~0); 14091#L1242-1 assume !(1 == ~T2_E~0); 13262#L1247-1 assume !(1 == ~T3_E~0); 13263#L1252-1 assume !(1 == ~T4_E~0); 13031#L1257-1 assume !(1 == ~T5_E~0); 13032#L1262-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 13885#L1267-1 assume !(1 == ~T7_E~0); 13983#L1272-1 assume !(1 == ~T8_E~0); 13347#L1277-1 assume !(1 == ~T9_E~0); 13348#L1282-1 assume !(1 == ~T10_E~0); 13756#L1287-1 assume !(1 == ~T11_E~0); 13757#L1292-1 assume !(1 == ~E_M~0); 13717#L1297-1 assume !(1 == ~E_1~0); 13159#L1302-1 assume 1 == ~E_2~0;~E_2~0 := 2; 13160#L1307-1 assume !(1 == ~E_3~0); 13972#L1312-1 assume !(1 == ~E_4~0); 13393#L1317-1 assume !(1 == ~E_5~0); 13394#L1322-1 assume !(1 == ~E_6~0); 13103#L1327-1 assume !(1 == ~E_7~0); 13104#L1332-1 assume !(1 == ~E_8~0); 13675#L1337-1 assume !(1 == ~E_9~0); 13610#L1342-1 assume 1 == ~E_10~0;~E_10~0 := 2; 13611#L1347-1 assume !(1 == ~E_11~0); 13971#L1352-1 assume { :end_inline_reset_delta_events } true; 13864#L1678-2 [2022-12-13 17:13:29,532 INFO L750 eck$LassoCheckResult]: Loop: 13864#L1678-2 assume !false; 13665#L1679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 13525#L1084 assume !false; 13460#L921 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 13461#L848 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 12743#L910 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 13957#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 12663#L925 assume !(0 != eval_~tmp~0#1); 12665#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 13152#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 13153#L1109-3 assume 0 == ~M_E~0;~M_E~0 := 1; 12636#L1109-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 12637#L1114-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 13719#L1119-3 assume !(0 == ~T3_E~0); 13720#L1124-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 13744#L1129-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 13745#L1134-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 13908#L1139-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 13960#L1144-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 13143#L1149-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 13144#L1154-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 13400#L1159-3 assume !(0 == ~T11_E~0); 13401#L1164-3 assume 0 == ~E_M~0;~E_M~0 := 1; 13658#L1169-3 assume 0 == ~E_1~0;~E_1~0 := 1; 13659#L1174-3 assume 0 == ~E_2~0;~E_2~0 := 1; 13707#L1179-3 assume 0 == ~E_3~0;~E_3~0 := 1; 13708#L1184-3 assume 0 == ~E_4~0;~E_4~0 := 1; 13848#L1189-3 assume 0 == ~E_5~0;~E_5~0 := 1; 13550#L1194-3 assume 0 == ~E_6~0;~E_6~0 := 1; 12900#L1199-3 assume !(0 == ~E_7~0); 12901#L1204-3 assume 0 == ~E_8~0;~E_8~0 := 1; 13125#L1209-3 assume 0 == ~E_9~0;~E_9~0 := 1; 12586#L1214-3 assume 0 == ~E_10~0;~E_10~0 := 1; 12587#L1219-3 assume 0 == ~E_11~0;~E_11~0 := 1; 13304#L1224-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13305#L544-39 assume 1 == ~m_pc~0; 13651#L545-13 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 12575#L555-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13627#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 12981#L1379-39 assume !(0 != activate_threads_~tmp~1#1); 12982#L1379-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 13835#L563-39 assume 1 == ~t1_pc~0; 13841#L564-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 12723#L574-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14119#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 14120#L1387-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 14123#L1387-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 13942#L582-39 assume 1 == ~t2_pc~0; 13043#L583-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 13045#L593-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13370#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 13371#L1395-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 12814#L1395-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12598#L601-39 assume 1 == ~t3_pc~0; 12599#L602-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 12647#L612-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13805#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 14130#L1403-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 13839#L1403-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13516#L620-39 assume !(1 == ~t4_pc~0); 13517#L620-41 is_transmit4_triggered_~__retres1~4#1 := 0; 13706#L631-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 13541#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 13542#L1411-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 13813#L1411-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14134#L639-39 assume 1 == ~t5_pc~0; 13925#L640-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 13265#L650-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 13266#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 12625#L1419-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 12626#L1419-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 13553#L658-39 assume 1 == ~t6_pc~0; 13536#L659-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 13537#L669-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 13986#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 13728#L1427-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 13703#L1427-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 13704#L677-39 assume !(1 == ~t7_pc~0); 13345#L677-41 is_transmit7_triggered_~__retres1~7#1 := 0; 12803#L688-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 12804#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 12859#L1435-39 assume !(0 != activate_threads_~tmp___6~0#1); 12860#L1435-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 13442#L696-39 assume 1 == ~t8_pc~0; 13408#L697-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 13288#L707-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 13289#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 13578#L1443-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 13546#L1443-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 13420#L715-39 assume 1 == ~t9_pc~0; 12601#L716-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 12602#L726-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 12678#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 12679#L1451-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 13750#L1451-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 13751#L734-39 assume !(1 == ~t10_pc~0); 13113#L734-41 is_transmit10_triggered_~__retres1~10#1 := 0; 13114#L745-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 13445#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 12757#L1459-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 12758#L1459-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 13998#L753-39 assume !(1 == ~t11_pc~0); 12676#L753-41 is_transmit11_triggered_~__retres1~11#1 := 0; 12677#L764-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 13575#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 13413#L1467-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 13414#L1467-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13509#L1237-3 assume 1 == ~M_E~0;~M_E~0 := 2; 13510#L1237-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 13771#L1242-3 assume !(1 == ~T2_E~0); 13772#L1247-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 13981#L1252-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 13696#L1257-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 13697#L1262-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 13953#L1267-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 14003#L1272-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 14105#L1277-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 12829#L1282-3 assume !(1 == ~T10_E~0); 12830#L1287-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 12740#L1292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 12741#L1297-3 assume 1 == ~E_1~0;~E_1~0 := 2; 13874#L1302-3 assume 1 == ~E_2~0;~E_2~0 := 2; 13875#L1307-3 assume 1 == ~E_3~0;~E_3~0 := 2; 14058#L1312-3 assume 1 == ~E_4~0;~E_4~0 := 2; 14131#L1317-3 assume 1 == ~E_5~0;~E_5~0 := 2; 13791#L1322-3 assume !(1 == ~E_6~0); 13792#L1327-3 assume 1 == ~E_7~0;~E_7~0 := 2; 12796#L1332-3 assume 1 == ~E_8~0;~E_8~0 := 2; 12773#L1337-3 assume 1 == ~E_9~0;~E_9~0 := 2; 12774#L1342-3 assume 1 == ~E_10~0;~E_10~0 := 2; 13483#L1347-3 assume 1 == ~E_11~0;~E_11~0 := 2; 13603#L1352-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 13604#L848-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 12717#L910-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 12926#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 12927#L1697 assume !(0 == start_simulation_~tmp~3#1); 13503#L1697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 13504#L848-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 12847#L910-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 12615#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; 12616#L1652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 13572#L1659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 13573#stop_simulation_returnLabel#1 start_simulation_#t~ret32#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 13863#L1710 assume !(0 != start_simulation_~tmp___0~1#1); 13864#L1678-2 [2022-12-13 17:13:29,532 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 17:13:29,533 INFO L85 PathProgramCache]: Analyzing trace with hash -1621157378, now seen corresponding path program 1 times [2022-12-13 17:13:29,533 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 17:13:29,533 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1076709254] [2022-12-13 17:13:29,533 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 17:13:29,533 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 17:13:29,545 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 17:13:29,579 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 17:13:29,579 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 17:13:29,579 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1076709254] [2022-12-13 17:13:29,579 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1076709254] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 17:13:29,580 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 17:13:29,580 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 17:13:29,580 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1329145359] [2022-12-13 17:13:29,580 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 17:13:29,580 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 17:13:29,580 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 17:13:29,580 INFO L85 PathProgramCache]: Analyzing trace with hash -1092238964, now seen corresponding path program 1 times [2022-12-13 17:13:29,581 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 17:13:29,581 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [241242217] [2022-12-13 17:13:29,581 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 17:13:29,581 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 17:13:29,592 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 17:13:29,624 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 17:13:29,625 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 17:13:29,625 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [241242217] [2022-12-13 17:13:29,625 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [241242217] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 17:13:29,625 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 17:13:29,625 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 17:13:29,625 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [725692108] [2022-12-13 17:13:29,625 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 17:13:29,626 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 17:13:29,626 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 17:13:29,626 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 17:13:29,626 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 17:13:29,627 INFO L87 Difference]: Start difference. First operand 1566 states and 2322 transitions. cyclomatic complexity: 757 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 17:13:29,651 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 17:13:29,651 INFO L93 Difference]: Finished difference Result 1566 states and 2321 transitions. [2022-12-13 17:13:29,651 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1566 states and 2321 transitions. [2022-12-13 17:13:29,656 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1415 [2022-12-13 17:13:29,660 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1566 states to 1566 states and 2321 transitions. [2022-12-13 17:13:29,660 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1566 [2022-12-13 17:13:29,661 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1566 [2022-12-13 17:13:29,661 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1566 states and 2321 transitions. [2022-12-13 17:13:29,663 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 17:13:29,663 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1566 states and 2321 transitions. [2022-12-13 17:13:29,664 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1566 states and 2321 transitions. [2022-12-13 17:13:29,691 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1566 to 1566. [2022-12-13 17:13:29,694 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1566 states, 1566 states have (on average 1.4821200510855683) internal successors, (2321), 1565 states have internal predecessors, (2321), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 17:13:29,699 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1566 states to 1566 states and 2321 transitions. [2022-12-13 17:13:29,699 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1566 states and 2321 transitions. [2022-12-13 17:13:29,699 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 17:13:29,700 INFO L428 stractBuchiCegarLoop]: Abstraction has 1566 states and 2321 transitions. [2022-12-13 17:13:29,700 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2022-12-13 17:13:29,700 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1566 states and 2321 transitions. [2022-12-13 17:13:29,705 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1415 [2022-12-13 17:13:29,706 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 17:13:29,706 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 17:13:29,707 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 17:13:29,707 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 17:13:29,707 INFO L748 eck$LassoCheckResult]: Stem: 15964#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 15965#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 16739#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 16740#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 15938#L780 assume 1 == ~m_i~0;~m_st~0 := 0; 15939#L780-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 17168#L785-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 17135#L790-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 17136#L795-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 16293#L800-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 16294#L805-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 16708#L810-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 17104#L815-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 16201#L820-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 16202#L825-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 16092#L830-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 16093#L835-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 17035#L1109 assume !(0 == ~M_E~0); 17051#L1109-2 assume !(0 == ~T1_E~0); 16101#L1114-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 16102#L1119-1 assume !(0 == ~T3_E~0); 17107#L1124-1 assume !(0 == ~T4_E~0); 15752#L1129-1 assume !(0 == ~T5_E~0); 15753#L1134-1 assume !(0 == ~T6_E~0); 16380#L1139-1 assume !(0 == ~T7_E~0); 17042#L1144-1 assume !(0 == ~T8_E~0); 16918#L1149-1 assume !(0 == ~T9_E~0); 15863#L1154-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 15864#L1159-1 assume !(0 == ~T11_E~0); 16908#L1164-1 assume !(0 == ~E_M~0); 16255#L1169-1 assume !(0 == ~E_1~0); 16153#L1174-1 assume !(0 == ~E_2~0); 16017#L1179-1 assume !(0 == ~E_3~0); 15944#L1184-1 assume !(0 == ~E_4~0); 15945#L1189-1 assume !(0 == ~E_5~0); 15977#L1194-1 assume 0 == ~E_6~0;~E_6~0 := 1; 16060#L1199-1 assume !(0 == ~E_7~0); 16927#L1204-1 assume !(0 == ~E_8~0); 16868#L1209-1 assume !(0 == ~E_9~0); 16869#L1214-1 assume !(0 == ~E_10~0); 17181#L1219-1 assume !(0 == ~E_11~0); 17267#L1224-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16272#L544 assume 1 == ~m_pc~0; 16273#L545 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 17090#L555 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16628#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 15906#L1379 assume !(0 != activate_threads_~tmp~1#1); 15907#L1379-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16695#L563 assume !(1 == ~t1_pc~0); 16497#L563-2 is_transmit1_triggered_~__retres1~1#1 := 0; 15762#L574 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 15763#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 16815#L1387 assume !(0 != activate_threads_~tmp___0~0#1); 15758#L1387-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15759#L582 assume 1 == ~t2_pc~0; 16475#L583 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 16820#L593 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 16097#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 16098#L1395 assume !(0 != activate_threads_~tmp___1~0#1); 15791#L1395-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 15792#L601 assume !(1 == ~t3_pc~0); 16492#L601-2 is_transmit3_triggered_~__retres1~3#1 := 0; 16491#L612 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 16946#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 16853#L1403 assume !(0 != activate_threads_~tmp___2~0#1); 16854#L1403-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 16801#L620 assume 1 == ~t4_pc~0; 15772#L621 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 15773#L631 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 15805#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 15806#L1411 assume !(0 != activate_threads_~tmp___3~0#1); 16705#L1411-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 16886#L639 assume 1 == ~t5_pc~0; 16775#L640 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 16065#L650 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 16066#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 16725#L1419 assume !(0 != activate_threads_~tmp___4~0#1); 16726#L1419-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 16660#L658 assume !(1 == ~t6_pc~0); 16269#L658-2 is_transmit6_triggered_~__retres1~6#1 := 0; 16270#L669 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 16089#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 16090#L1427 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 16857#L1427-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 16112#L677 assume 1 == ~t7_pc~0; 16113#L678 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 16010#L688 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 17007#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 17129#L1435 assume !(0 != activate_threads_~tmp___6~0#1); 17130#L1435-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 17200#L696 assume !(1 == ~t8_pc~0); 16333#L696-2 is_transmit8_triggered_~__retres1~8#1 := 0; 16334#L707 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 17166#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 17203#L1443 assume !(0 != activate_threads_~tmp___7~0#1); 17247#L1443-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 16763#L715 assume 1 == ~t9_pc~0; 16764#L716 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 16433#L726 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 16151#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 16152#L1451 assume !(0 != activate_threads_~tmp___8~0#1); 16746#L1451-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 17002#L734 assume !(1 == ~t10_pc~0); 17003#L734-2 is_transmit10_triggered_~__retres1~10#1 := 0; 16227#L745 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 16228#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 16948#L1459 assume !(0 != activate_threads_~tmp___9~0#1); 16949#L1459-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 16307#L753 assume 1 == ~t11_pc~0; 16308#L754 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 16862#L764 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 17175#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 16578#L1467 assume !(0 != activate_threads_~tmp___10~0#1); 16579#L1467-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16635#L1237 assume !(1 == ~M_E~0); 16636#L1237-2 assume !(1 == ~T1_E~0); 17230#L1242-1 assume !(1 == ~T2_E~0); 16401#L1247-1 assume !(1 == ~T3_E~0); 16402#L1252-1 assume !(1 == ~T4_E~0); 16170#L1257-1 assume !(1 == ~T5_E~0); 16171#L1262-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 17024#L1267-1 assume !(1 == ~T7_E~0); 17122#L1272-1 assume !(1 == ~T8_E~0); 16486#L1277-1 assume !(1 == ~T9_E~0); 16487#L1282-1 assume !(1 == ~T10_E~0); 16895#L1287-1 assume !(1 == ~T11_E~0); 16896#L1292-1 assume !(1 == ~E_M~0); 16856#L1297-1 assume !(1 == ~E_1~0); 16298#L1302-1 assume 1 == ~E_2~0;~E_2~0 := 2; 16299#L1307-1 assume !(1 == ~E_3~0); 17111#L1312-1 assume !(1 == ~E_4~0); 16532#L1317-1 assume !(1 == ~E_5~0); 16533#L1322-1 assume !(1 == ~E_6~0); 16242#L1327-1 assume !(1 == ~E_7~0); 16243#L1332-1 assume !(1 == ~E_8~0); 16814#L1337-1 assume !(1 == ~E_9~0); 16749#L1342-1 assume 1 == ~E_10~0;~E_10~0 := 2; 16750#L1347-1 assume !(1 == ~E_11~0); 17110#L1352-1 assume { :end_inline_reset_delta_events } true; 17006#L1678-2 [2022-12-13 17:13:29,707 INFO L750 eck$LassoCheckResult]: Loop: 17006#L1678-2 assume !false; 16804#L1679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 16664#L1084 assume !false; 16599#L921 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 16600#L848 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 15882#L910 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 17096#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 15802#L925 assume !(0 != eval_~tmp~0#1); 15804#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 16291#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 16292#L1109-3 assume 0 == ~M_E~0;~M_E~0 := 1; 15775#L1109-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 15776#L1114-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 16858#L1119-3 assume !(0 == ~T3_E~0); 16859#L1124-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 16883#L1129-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 16884#L1134-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 17047#L1139-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 17099#L1144-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 16282#L1149-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 16283#L1154-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 16539#L1159-3 assume !(0 == ~T11_E~0); 16540#L1164-3 assume 0 == ~E_M~0;~E_M~0 := 1; 16797#L1169-3 assume 0 == ~E_1~0;~E_1~0 := 1; 16798#L1174-3 assume 0 == ~E_2~0;~E_2~0 := 1; 16846#L1179-3 assume 0 == ~E_3~0;~E_3~0 := 1; 16847#L1184-3 assume 0 == ~E_4~0;~E_4~0 := 1; 16987#L1189-3 assume 0 == ~E_5~0;~E_5~0 := 1; 16689#L1194-3 assume 0 == ~E_6~0;~E_6~0 := 1; 16039#L1199-3 assume !(0 == ~E_7~0); 16040#L1204-3 assume 0 == ~E_8~0;~E_8~0 := 1; 16262#L1209-3 assume 0 == ~E_9~0;~E_9~0 := 1; 15725#L1214-3 assume 0 == ~E_10~0;~E_10~0 := 1; 15726#L1219-3 assume 0 == ~E_11~0;~E_11~0 := 1; 16443#L1224-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16444#L544-39 assume !(1 == ~m_pc~0); 15713#L544-41 is_master_triggered_~__retres1~0#1 := 0; 15714#L555-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16766#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 16120#L1379-39 assume !(0 != activate_threads_~tmp~1#1); 16121#L1379-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16974#L563-39 assume !(1 == ~t1_pc~0); 15858#L563-41 is_transmit1_triggered_~__retres1~1#1 := 0; 15859#L574-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 17258#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 17259#L1387-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 17262#L1387-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 17081#L582-39 assume 1 == ~t2_pc~0; 16182#L583-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 16184#L593-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 16509#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 16510#L1395-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 15953#L1395-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 15737#L601-39 assume 1 == ~t3_pc~0; 15738#L602-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 15786#L612-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 16944#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 17269#L1403-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 16978#L1403-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 16655#L620-39 assume !(1 == ~t4_pc~0); 16656#L620-41 is_transmit4_triggered_~__retres1~4#1 := 0; 16845#L631-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 16680#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 16681#L1411-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 16952#L1411-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 17273#L639-39 assume 1 == ~t5_pc~0; 17064#L640-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 16404#L650-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 16405#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 15764#L1419-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 15765#L1419-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 16692#L658-39 assume 1 == ~t6_pc~0; 16675#L659-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 16676#L669-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 17125#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 16867#L1427-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 16842#L1427-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 16843#L677-39 assume !(1 == ~t7_pc~0); 16484#L677-41 is_transmit7_triggered_~__retres1~7#1 := 0; 15942#L688-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 15943#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 15998#L1435-39 assume !(0 != activate_threads_~tmp___6~0#1); 15999#L1435-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 16581#L696-39 assume 1 == ~t8_pc~0; 16547#L697-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 16427#L707-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 16428#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 16717#L1443-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 16685#L1443-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 16561#L715-39 assume !(1 == ~t9_pc~0); 15744#L715-41 is_transmit9_triggered_~__retres1~9#1 := 0; 15743#L726-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 15819#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 15820#L1451-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 16889#L1451-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 16890#L734-39 assume 1 == ~t10_pc~0; 16818#L735-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 16254#L745-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 16584#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 15896#L1459-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 15897#L1459-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 17138#L753-39 assume !(1 == ~t11_pc~0); 15815#L753-41 is_transmit11_triggered_~__retres1~11#1 := 0; 15816#L764-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 16714#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 16552#L1467-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 16553#L1467-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16652#L1237-3 assume 1 == ~M_E~0;~M_E~0 := 2; 16653#L1237-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 16910#L1242-3 assume !(1 == ~T2_E~0); 16911#L1247-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 17121#L1252-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 16835#L1257-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 16836#L1262-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 17094#L1267-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 17142#L1272-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 17244#L1277-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 15969#L1282-3 assume !(1 == ~T10_E~0); 15970#L1287-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 15879#L1292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 15880#L1297-3 assume 1 == ~E_1~0;~E_1~0 := 2; 17016#L1302-3 assume 1 == ~E_2~0;~E_2~0 := 2; 17017#L1307-3 assume 1 == ~E_3~0;~E_3~0 := 2; 17197#L1312-3 assume 1 == ~E_4~0;~E_4~0 := 2; 17270#L1317-3 assume 1 == ~E_5~0;~E_5~0 := 2; 16930#L1322-3 assume !(1 == ~E_6~0); 16931#L1327-3 assume 1 == ~E_7~0;~E_7~0 := 2; 15935#L1332-3 assume 1 == ~E_8~0;~E_8~0 := 2; 15912#L1337-3 assume 1 == ~E_9~0;~E_9~0 := 2; 15913#L1342-3 assume 1 == ~E_10~0;~E_10~0 := 2; 16622#L1347-3 assume 1 == ~E_11~0;~E_11~0 := 2; 16744#L1352-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 16745#L848-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 15861#L910-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 16067#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 16068#L1697 assume !(0 == start_simulation_~tmp~3#1); 16642#L1697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 16643#L848-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 15986#L910-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 15754#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; 15755#L1652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 16711#L1659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 16712#stop_simulation_returnLabel#1 start_simulation_#t~ret32#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 17005#L1710 assume !(0 != start_simulation_~tmp___0~1#1); 17006#L1678-2 [2022-12-13 17:13:29,708 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 17:13:29,708 INFO L85 PathProgramCache]: Analyzing trace with hash -1076284804, now seen corresponding path program 1 times [2022-12-13 17:13:29,708 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 17:13:29,708 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1426374470] [2022-12-13 17:13:29,708 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 17:13:29,708 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 17:13:29,717 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 17:13:29,741 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 17:13:29,742 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 17:13:29,742 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1426374470] [2022-12-13 17:13:29,742 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1426374470] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 17:13:29,742 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 17:13:29,742 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 17:13:29,742 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [174049366] [2022-12-13 17:13:29,742 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 17:13:29,743 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 17:13:29,743 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 17:13:29,743 INFO L85 PathProgramCache]: Analyzing trace with hash 1977169166, now seen corresponding path program 1 times [2022-12-13 17:13:29,743 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 17:13:29,743 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1378370767] [2022-12-13 17:13:29,744 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 17:13:29,744 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 17:13:29,755 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 17:13:29,785 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 17:13:29,786 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 17:13:29,786 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1378370767] [2022-12-13 17:13:29,786 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1378370767] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 17:13:29,786 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 17:13:29,786 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 17:13:29,786 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1096790536] [2022-12-13 17:13:29,786 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 17:13:29,787 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 17:13:29,787 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 17:13:29,787 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 17:13:29,787 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 17:13:29,788 INFO L87 Difference]: Start difference. First operand 1566 states and 2321 transitions. cyclomatic complexity: 756 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 17:13:29,808 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 17:13:29,808 INFO L93 Difference]: Finished difference Result 1566 states and 2320 transitions. [2022-12-13 17:13:29,808 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1566 states and 2320 transitions. [2022-12-13 17:13:29,814 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1415 [2022-12-13 17:13:29,818 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1566 states to 1566 states and 2320 transitions. [2022-12-13 17:13:29,818 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1566 [2022-12-13 17:13:29,819 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1566 [2022-12-13 17:13:29,819 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1566 states and 2320 transitions. [2022-12-13 17:13:29,821 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 17:13:29,821 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1566 states and 2320 transitions. [2022-12-13 17:13:29,822 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1566 states and 2320 transitions. [2022-12-13 17:13:29,834 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1566 to 1566. [2022-12-13 17:13:29,836 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1566 states, 1566 states have (on average 1.4814814814814814) internal successors, (2320), 1565 states have internal predecessors, (2320), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 17:13:29,838 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1566 states to 1566 states and 2320 transitions. [2022-12-13 17:13:29,838 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1566 states and 2320 transitions. [2022-12-13 17:13:29,839 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 17:13:29,839 INFO L428 stractBuchiCegarLoop]: Abstraction has 1566 states and 2320 transitions. [2022-12-13 17:13:29,840 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2022-12-13 17:13:29,840 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1566 states and 2320 transitions. [2022-12-13 17:13:29,845 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1415 [2022-12-13 17:13:29,846 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 17:13:29,846 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 17:13:29,848 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 17:13:29,848 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 17:13:29,848 INFO L748 eck$LassoCheckResult]: Stem: 19103#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 19104#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 19878#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 19879#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 19077#L780 assume 1 == ~m_i~0;~m_st~0 := 0; 19078#L780-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 20307#L785-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 20274#L790-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 20275#L795-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 19432#L800-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 19433#L805-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 19847#L810-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 20243#L815-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 19340#L820-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 19341#L825-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 19231#L830-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 19232#L835-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 20174#L1109 assume !(0 == ~M_E~0); 20190#L1109-2 assume !(0 == ~T1_E~0); 19240#L1114-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 19241#L1119-1 assume !(0 == ~T3_E~0); 20246#L1124-1 assume !(0 == ~T4_E~0); 18891#L1129-1 assume !(0 == ~T5_E~0); 18892#L1134-1 assume !(0 == ~T6_E~0); 19519#L1139-1 assume !(0 == ~T7_E~0); 20181#L1144-1 assume !(0 == ~T8_E~0); 20057#L1149-1 assume !(0 == ~T9_E~0); 19002#L1154-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 19003#L1159-1 assume !(0 == ~T11_E~0); 20047#L1164-1 assume !(0 == ~E_M~0); 19394#L1169-1 assume !(0 == ~E_1~0); 19292#L1174-1 assume !(0 == ~E_2~0); 19156#L1179-1 assume !(0 == ~E_3~0); 19083#L1184-1 assume !(0 == ~E_4~0); 19084#L1189-1 assume !(0 == ~E_5~0); 19116#L1194-1 assume 0 == ~E_6~0;~E_6~0 := 1; 19199#L1199-1 assume !(0 == ~E_7~0); 20066#L1204-1 assume !(0 == ~E_8~0); 20007#L1209-1 assume !(0 == ~E_9~0); 20008#L1214-1 assume !(0 == ~E_10~0); 20320#L1219-1 assume !(0 == ~E_11~0); 20406#L1224-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 19411#L544 assume 1 == ~m_pc~0; 19412#L545 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 20229#L555 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 19767#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 19045#L1379 assume !(0 != activate_threads_~tmp~1#1); 19046#L1379-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 19834#L563 assume !(1 == ~t1_pc~0); 19636#L563-2 is_transmit1_triggered_~__retres1~1#1 := 0; 18901#L574 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 18902#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 19954#L1387 assume !(0 != activate_threads_~tmp___0~0#1); 18897#L1387-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 18898#L582 assume 1 == ~t2_pc~0; 19614#L583 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 19959#L593 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 19236#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 19237#L1395 assume !(0 != activate_threads_~tmp___1~0#1); 18930#L1395-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 18931#L601 assume !(1 == ~t3_pc~0); 19631#L601-2 is_transmit3_triggered_~__retres1~3#1 := 0; 19630#L612 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 20085#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 19992#L1403 assume !(0 != activate_threads_~tmp___2~0#1); 19993#L1403-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19940#L620 assume 1 == ~t4_pc~0; 18911#L621 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 18912#L631 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 18944#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 18945#L1411 assume !(0 != activate_threads_~tmp___3~0#1); 19844#L1411-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 20025#L639 assume 1 == ~t5_pc~0; 19914#L640 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 19204#L650 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 19205#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 19864#L1419 assume !(0 != activate_threads_~tmp___4~0#1); 19865#L1419-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 19799#L658 assume !(1 == ~t6_pc~0); 19408#L658-2 is_transmit6_triggered_~__retres1~6#1 := 0; 19409#L669 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 19228#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 19229#L1427 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 19996#L1427-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 19251#L677 assume 1 == ~t7_pc~0; 19252#L678 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 19149#L688 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 20146#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 20268#L1435 assume !(0 != activate_threads_~tmp___6~0#1); 20269#L1435-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 20339#L696 assume !(1 == ~t8_pc~0); 19472#L696-2 is_transmit8_triggered_~__retres1~8#1 := 0; 19473#L707 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 20305#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 20342#L1443 assume !(0 != activate_threads_~tmp___7~0#1); 20386#L1443-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 19902#L715 assume 1 == ~t9_pc~0; 19903#L716 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 19572#L726 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 19290#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 19291#L1451 assume !(0 != activate_threads_~tmp___8~0#1); 19885#L1451-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 20141#L734 assume !(1 == ~t10_pc~0); 20142#L734-2 is_transmit10_triggered_~__retres1~10#1 := 0; 19366#L745 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 19367#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 20087#L1459 assume !(0 != activate_threads_~tmp___9~0#1); 20088#L1459-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 19446#L753 assume 1 == ~t11_pc~0; 19447#L754 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 20001#L764 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 20314#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 19717#L1467 assume !(0 != activate_threads_~tmp___10~0#1); 19718#L1467-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19774#L1237 assume !(1 == ~M_E~0); 19775#L1237-2 assume !(1 == ~T1_E~0); 20369#L1242-1 assume !(1 == ~T2_E~0); 19540#L1247-1 assume !(1 == ~T3_E~0); 19541#L1252-1 assume !(1 == ~T4_E~0); 19309#L1257-1 assume !(1 == ~T5_E~0); 19310#L1262-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 20163#L1267-1 assume !(1 == ~T7_E~0); 20261#L1272-1 assume !(1 == ~T8_E~0); 19625#L1277-1 assume !(1 == ~T9_E~0); 19626#L1282-1 assume !(1 == ~T10_E~0); 20034#L1287-1 assume !(1 == ~T11_E~0); 20035#L1292-1 assume !(1 == ~E_M~0); 19995#L1297-1 assume !(1 == ~E_1~0); 19437#L1302-1 assume 1 == ~E_2~0;~E_2~0 := 2; 19438#L1307-1 assume !(1 == ~E_3~0); 20250#L1312-1 assume !(1 == ~E_4~0); 19671#L1317-1 assume !(1 == ~E_5~0); 19672#L1322-1 assume !(1 == ~E_6~0); 19381#L1327-1 assume !(1 == ~E_7~0); 19382#L1332-1 assume !(1 == ~E_8~0); 19953#L1337-1 assume !(1 == ~E_9~0); 19888#L1342-1 assume 1 == ~E_10~0;~E_10~0 := 2; 19889#L1347-1 assume !(1 == ~E_11~0); 20249#L1352-1 assume { :end_inline_reset_delta_events } true; 20145#L1678-2 [2022-12-13 17:13:29,849 INFO L750 eck$LassoCheckResult]: Loop: 20145#L1678-2 assume !false; 19943#L1679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 19803#L1084 assume !false; 19738#L921 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 19739#L848 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 19021#L910 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 20235#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 18941#L925 assume !(0 != eval_~tmp~0#1); 18943#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 19430#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 19431#L1109-3 assume 0 == ~M_E~0;~M_E~0 := 1; 18914#L1109-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 18915#L1114-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 19997#L1119-3 assume !(0 == ~T3_E~0); 19998#L1124-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 20022#L1129-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 20023#L1134-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 20186#L1139-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 20238#L1144-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 19421#L1149-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 19422#L1154-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 19678#L1159-3 assume !(0 == ~T11_E~0); 19679#L1164-3 assume 0 == ~E_M~0;~E_M~0 := 1; 19936#L1169-3 assume 0 == ~E_1~0;~E_1~0 := 1; 19937#L1174-3 assume 0 == ~E_2~0;~E_2~0 := 1; 19985#L1179-3 assume 0 == ~E_3~0;~E_3~0 := 1; 19986#L1184-3 assume 0 == ~E_4~0;~E_4~0 := 1; 20126#L1189-3 assume 0 == ~E_5~0;~E_5~0 := 1; 19828#L1194-3 assume 0 == ~E_6~0;~E_6~0 := 1; 19178#L1199-3 assume !(0 == ~E_7~0); 19179#L1204-3 assume 0 == ~E_8~0;~E_8~0 := 1; 19401#L1209-3 assume 0 == ~E_9~0;~E_9~0 := 1; 18864#L1214-3 assume 0 == ~E_10~0;~E_10~0 := 1; 18865#L1219-3 assume 0 == ~E_11~0;~E_11~0 := 1; 19582#L1224-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 19583#L544-39 assume !(1 == ~m_pc~0); 18852#L544-41 is_master_triggered_~__retres1~0#1 := 0; 18853#L555-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 19905#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 19259#L1379-39 assume !(0 != activate_threads_~tmp~1#1); 19260#L1379-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 20113#L563-39 assume !(1 == ~t1_pc~0); 18997#L563-41 is_transmit1_triggered_~__retres1~1#1 := 0; 18998#L574-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 20397#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 20398#L1387-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 20401#L1387-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 20220#L582-39 assume 1 == ~t2_pc~0; 19321#L583-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 19323#L593-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 19648#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 19649#L1395-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 19092#L1395-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 18876#L601-39 assume 1 == ~t3_pc~0; 18877#L602-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 18925#L612-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 20083#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 20408#L1403-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 20117#L1403-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19794#L620-39 assume !(1 == ~t4_pc~0); 19795#L620-41 is_transmit4_triggered_~__retres1~4#1 := 0; 19984#L631-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 19819#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 19820#L1411-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 20091#L1411-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 20412#L639-39 assume 1 == ~t5_pc~0; 20203#L640-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 19543#L650-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 19544#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 18903#L1419-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 18904#L1419-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 19831#L658-39 assume 1 == ~t6_pc~0; 19814#L659-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 19815#L669-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 20264#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 20006#L1427-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 19981#L1427-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 19982#L677-39 assume !(1 == ~t7_pc~0); 19623#L677-41 is_transmit7_triggered_~__retres1~7#1 := 0; 19081#L688-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 19082#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 19137#L1435-39 assume !(0 != activate_threads_~tmp___6~0#1); 19138#L1435-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 19720#L696-39 assume 1 == ~t8_pc~0; 19686#L697-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 19566#L707-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 19567#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 19856#L1443-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 19824#L1443-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 19700#L715-39 assume 1 == ~t9_pc~0; 18881#L716-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 18882#L726-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 18958#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 18959#L1451-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 20028#L1451-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 20029#L734-39 assume !(1 == ~t10_pc~0); 19392#L734-41 is_transmit10_triggered_~__retres1~10#1 := 0; 19393#L745-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 19723#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 19035#L1459-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 19036#L1459-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 20277#L753-39 assume 1 == ~t11_pc~0; 19665#L754-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 18955#L764-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 19853#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 19691#L1467-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 19692#L1467-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19791#L1237-3 assume 1 == ~M_E~0;~M_E~0 := 2; 19792#L1237-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 20049#L1242-3 assume !(1 == ~T2_E~0); 20050#L1247-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 20260#L1252-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 19974#L1257-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 19975#L1262-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 20233#L1267-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 20281#L1272-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 20383#L1277-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 19108#L1282-3 assume !(1 == ~T10_E~0); 19109#L1287-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 19018#L1292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 19019#L1297-3 assume 1 == ~E_1~0;~E_1~0 := 2; 20155#L1302-3 assume 1 == ~E_2~0;~E_2~0 := 2; 20156#L1307-3 assume 1 == ~E_3~0;~E_3~0 := 2; 20336#L1312-3 assume 1 == ~E_4~0;~E_4~0 := 2; 20409#L1317-3 assume 1 == ~E_5~0;~E_5~0 := 2; 20069#L1322-3 assume !(1 == ~E_6~0); 20070#L1327-3 assume 1 == ~E_7~0;~E_7~0 := 2; 19074#L1332-3 assume 1 == ~E_8~0;~E_8~0 := 2; 19051#L1337-3 assume 1 == ~E_9~0;~E_9~0 := 2; 19052#L1342-3 assume 1 == ~E_10~0;~E_10~0 := 2; 19761#L1347-3 assume 1 == ~E_11~0;~E_11~0 := 2; 19883#L1352-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 19884#L848-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 19000#L910-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 19206#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 19207#L1697 assume !(0 == start_simulation_~tmp~3#1); 19781#L1697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 19782#L848-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 19125#L910-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 18893#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; 18894#L1652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 19850#L1659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 19851#stop_simulation_returnLabel#1 start_simulation_#t~ret32#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 20144#L1710 assume !(0 != start_simulation_~tmp___0~1#1); 20145#L1678-2 [2022-12-13 17:13:29,849 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 17:13:29,849 INFO L85 PathProgramCache]: Analyzing trace with hash -1751444930, now seen corresponding path program 1 times [2022-12-13 17:13:29,849 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 17:13:29,849 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [272487271] [2022-12-13 17:13:29,850 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 17:13:29,850 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 17:13:29,861 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 17:13:29,892 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 17:13:29,893 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 17:13:29,893 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [272487271] [2022-12-13 17:13:29,893 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [272487271] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 17:13:29,893 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 17:13:29,893 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 17:13:29,893 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1511692480] [2022-12-13 17:13:29,894 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 17:13:29,894 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 17:13:29,894 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 17:13:29,894 INFO L85 PathProgramCache]: Analyzing trace with hash -1639996467, now seen corresponding path program 2 times [2022-12-13 17:13:29,894 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 17:13:29,895 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1014669357] [2022-12-13 17:13:29,895 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 17:13:29,895 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 17:13:29,909 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 17:13:29,951 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 17:13:29,951 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 17:13:29,951 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1014669357] [2022-12-13 17:13:29,951 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1014669357] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 17:13:29,952 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 17:13:29,952 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 17:13:29,952 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [507633143] [2022-12-13 17:13:29,952 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 17:13:29,952 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 17:13:29,952 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 17:13:29,953 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 17:13:29,953 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 17:13:29,953 INFO L87 Difference]: Start difference. First operand 1566 states and 2320 transitions. cyclomatic complexity: 755 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 17:13:29,999 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 17:13:29,999 INFO L93 Difference]: Finished difference Result 1566 states and 2319 transitions. [2022-12-13 17:13:29,999 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1566 states and 2319 transitions. [2022-12-13 17:13:30,005 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1415 [2022-12-13 17:13:30,010 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1566 states to 1566 states and 2319 transitions. [2022-12-13 17:13:30,010 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1566 [2022-12-13 17:13:30,011 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1566 [2022-12-13 17:13:30,011 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1566 states and 2319 transitions. [2022-12-13 17:13:30,013 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 17:13:30,013 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1566 states and 2319 transitions. [2022-12-13 17:13:30,015 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1566 states and 2319 transitions. [2022-12-13 17:13:30,030 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1566 to 1566. [2022-12-13 17:13:30,033 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1566 states, 1566 states have (on average 1.4808429118773947) internal successors, (2319), 1565 states have internal predecessors, (2319), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 17:13:30,037 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1566 states to 1566 states and 2319 transitions. [2022-12-13 17:13:30,038 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1566 states and 2319 transitions. [2022-12-13 17:13:30,038 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 17:13:30,039 INFO L428 stractBuchiCegarLoop]: Abstraction has 1566 states and 2319 transitions. [2022-12-13 17:13:30,039 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2022-12-13 17:13:30,039 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1566 states and 2319 transitions. [2022-12-13 17:13:30,044 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1415 [2022-12-13 17:13:30,044 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 17:13:30,045 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 17:13:30,046 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 17:13:30,046 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 17:13:30,047 INFO L748 eck$LassoCheckResult]: Stem: 22242#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 22243#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 23018#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 23019#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 22216#L780 assume 1 == ~m_i~0;~m_st~0 := 0; 22217#L780-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 23446#L785-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 23413#L790-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 23414#L795-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 22571#L800-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 22572#L805-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 22986#L810-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 23382#L815-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 22481#L820-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 22482#L825-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 22370#L830-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 22371#L835-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 23315#L1109 assume !(0 == ~M_E~0); 23330#L1109-2 assume !(0 == ~T1_E~0); 22379#L1114-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 22380#L1119-1 assume !(0 == ~T3_E~0); 23385#L1124-1 assume !(0 == ~T4_E~0); 22030#L1129-1 assume !(0 == ~T5_E~0); 22031#L1134-1 assume !(0 == ~T6_E~0); 22658#L1139-1 assume !(0 == ~T7_E~0); 23320#L1144-1 assume !(0 == ~T8_E~0); 23196#L1149-1 assume !(0 == ~T9_E~0); 22143#L1154-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 22144#L1159-1 assume !(0 == ~T11_E~0); 23186#L1164-1 assume !(0 == ~E_M~0); 22533#L1169-1 assume !(0 == ~E_1~0); 22431#L1174-1 assume !(0 == ~E_2~0); 22300#L1179-1 assume !(0 == ~E_3~0); 22222#L1184-1 assume !(0 == ~E_4~0); 22223#L1189-1 assume !(0 == ~E_5~0); 22255#L1194-1 assume 0 == ~E_6~0;~E_6~0 := 1; 22342#L1199-1 assume !(0 == ~E_7~0); 23205#L1204-1 assume !(0 == ~E_8~0); 23147#L1209-1 assume !(0 == ~E_9~0); 23148#L1214-1 assume !(0 == ~E_10~0); 23459#L1219-1 assume !(0 == ~E_11~0); 23545#L1224-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 22552#L544 assume 1 == ~m_pc~0; 22553#L545 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 23368#L555 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 22906#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 22186#L1379 assume !(0 != activate_threads_~tmp~1#1); 22187#L1379-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 22975#L563 assume !(1 == ~t1_pc~0); 22775#L563-2 is_transmit1_triggered_~__retres1~1#1 := 0; 22040#L574 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 22041#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 23093#L1387 assume !(0 != activate_threads_~tmp___0~0#1); 22036#L1387-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 22037#L582 assume 1 == ~t2_pc~0; 22753#L583 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 23100#L593 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 22375#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 22376#L1395 assume !(0 != activate_threads_~tmp___1~0#1); 22069#L1395-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 22070#L601 assume !(1 == ~t3_pc~0); 22770#L601-2 is_transmit3_triggered_~__retres1~3#1 := 0; 22769#L612 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 23224#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 23131#L1403 assume !(0 != activate_threads_~tmp___2~0#1); 23132#L1403-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 23079#L620 assume 1 == ~t4_pc~0; 22050#L621 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 22051#L631 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 22083#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 22084#L1411 assume !(0 != activate_threads_~tmp___3~0#1); 22983#L1411-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 23164#L639 assume 1 == ~t5_pc~0; 23053#L640 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 22343#L650 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 22344#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 23003#L1419 assume !(0 != activate_threads_~tmp___4~0#1); 23004#L1419-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 22938#L658 assume !(1 == ~t6_pc~0); 22547#L658-2 is_transmit6_triggered_~__retres1~6#1 := 0; 22548#L669 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 22367#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 22368#L1427 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 23135#L1427-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 22390#L677 assume 1 == ~t7_pc~0; 22391#L678 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 22288#L688 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 23285#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 23407#L1435 assume !(0 != activate_threads_~tmp___6~0#1); 23408#L1435-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 23478#L696 assume !(1 == ~t8_pc~0); 22611#L696-2 is_transmit8_triggered_~__retres1~8#1 := 0; 22612#L707 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 23444#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 23481#L1443 assume !(0 != activate_threads_~tmp___7~0#1); 23525#L1443-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 23041#L715 assume 1 == ~t9_pc~0; 23042#L716 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 22711#L726 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 22429#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 22430#L1451 assume !(0 != activate_threads_~tmp___8~0#1); 23024#L1451-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 23280#L734 assume !(1 == ~t10_pc~0); 23281#L734-2 is_transmit10_triggered_~__retres1~10#1 := 0; 22505#L745 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 22506#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 23226#L1459 assume !(0 != activate_threads_~tmp___9~0#1); 23227#L1459-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 22585#L753 assume 1 == ~t11_pc~0; 22586#L754 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 23140#L764 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 23453#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 22856#L1467 assume !(0 != activate_threads_~tmp___10~0#1); 22857#L1467-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 22913#L1237 assume !(1 == ~M_E~0); 22914#L1237-2 assume !(1 == ~T1_E~0); 23508#L1242-1 assume !(1 == ~T2_E~0); 22679#L1247-1 assume !(1 == ~T3_E~0); 22680#L1252-1 assume !(1 == ~T4_E~0); 22448#L1257-1 assume !(1 == ~T5_E~0); 22449#L1262-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 23302#L1267-1 assume !(1 == ~T7_E~0); 23400#L1272-1 assume !(1 == ~T8_E~0); 22764#L1277-1 assume !(1 == ~T9_E~0); 22765#L1282-1 assume !(1 == ~T10_E~0); 23173#L1287-1 assume !(1 == ~T11_E~0); 23174#L1292-1 assume !(1 == ~E_M~0); 23134#L1297-1 assume !(1 == ~E_1~0); 22576#L1302-1 assume 1 == ~E_2~0;~E_2~0 := 2; 22577#L1307-1 assume !(1 == ~E_3~0); 23389#L1312-1 assume !(1 == ~E_4~0); 22810#L1317-1 assume !(1 == ~E_5~0); 22811#L1322-1 assume !(1 == ~E_6~0); 22520#L1327-1 assume !(1 == ~E_7~0); 22521#L1332-1 assume !(1 == ~E_8~0); 23092#L1337-1 assume !(1 == ~E_9~0); 23027#L1342-1 assume 1 == ~E_10~0;~E_10~0 := 2; 23028#L1347-1 assume !(1 == ~E_11~0); 23388#L1352-1 assume { :end_inline_reset_delta_events } true; 23284#L1678-2 [2022-12-13 17:13:30,047 INFO L750 eck$LassoCheckResult]: Loop: 23284#L1678-2 assume !false; 23082#L1679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 22942#L1084 assume !false; 22877#L921 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 22878#L848 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 22160#L910 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 23374#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 22080#L925 assume !(0 != eval_~tmp~0#1); 22082#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 22569#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 22570#L1109-3 assume 0 == ~M_E~0;~M_E~0 := 1; 22053#L1109-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 22054#L1114-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 23136#L1119-3 assume !(0 == ~T3_E~0); 23137#L1124-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 23161#L1129-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 23162#L1134-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 23325#L1139-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 23377#L1144-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 22560#L1149-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 22561#L1154-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 22817#L1159-3 assume !(0 == ~T11_E~0); 22818#L1164-3 assume 0 == ~E_M~0;~E_M~0 := 1; 23075#L1169-3 assume 0 == ~E_1~0;~E_1~0 := 1; 23076#L1174-3 assume 0 == ~E_2~0;~E_2~0 := 1; 23124#L1179-3 assume 0 == ~E_3~0;~E_3~0 := 1; 23125#L1184-3 assume 0 == ~E_4~0;~E_4~0 := 1; 23265#L1189-3 assume 0 == ~E_5~0;~E_5~0 := 1; 22967#L1194-3 assume 0 == ~E_6~0;~E_6~0 := 1; 22317#L1199-3 assume !(0 == ~E_7~0); 22318#L1204-3 assume 0 == ~E_8~0;~E_8~0 := 1; 22540#L1209-3 assume 0 == ~E_9~0;~E_9~0 := 1; 22003#L1214-3 assume 0 == ~E_10~0;~E_10~0 := 1; 22004#L1219-3 assume 0 == ~E_11~0;~E_11~0 := 1; 22721#L1224-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 22722#L544-39 assume !(1 == ~m_pc~0); 21991#L544-41 is_master_triggered_~__retres1~0#1 := 0; 21992#L555-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 23044#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 22398#L1379-39 assume !(0 != activate_threads_~tmp~1#1); 22399#L1379-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 23252#L563-39 assume !(1 == ~t1_pc~0); 22136#L563-41 is_transmit1_triggered_~__retres1~1#1 := 0; 22137#L574-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 23536#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 23537#L1387-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 23540#L1387-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 23359#L582-39 assume 1 == ~t2_pc~0; 22460#L583-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 22462#L593-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 22787#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 22788#L1395-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 22231#L1395-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 22015#L601-39 assume 1 == ~t3_pc~0; 22016#L602-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 22064#L612-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 23222#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 23547#L1403-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 23256#L1403-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 22933#L620-39 assume !(1 == ~t4_pc~0); 22934#L620-41 is_transmit4_triggered_~__retres1~4#1 := 0; 23123#L631-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 22958#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 22959#L1411-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 23230#L1411-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 23551#L639-39 assume 1 == ~t5_pc~0; 23342#L640-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 22682#L650-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 22683#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 22042#L1419-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 22043#L1419-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 22970#L658-39 assume 1 == ~t6_pc~0; 22953#L659-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 22954#L669-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 23403#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 23145#L1427-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 23120#L1427-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 23121#L677-39 assume !(1 == ~t7_pc~0); 22762#L677-41 is_transmit7_triggered_~__retres1~7#1 := 0; 22220#L688-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 22221#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 22276#L1435-39 assume !(0 != activate_threads_~tmp___6~0#1); 22277#L1435-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 22859#L696-39 assume 1 == ~t8_pc~0; 22825#L697-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 22705#L707-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 22706#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 22995#L1443-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 22963#L1443-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 22839#L715-39 assume 1 == ~t9_pc~0; 22020#L716-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 22021#L726-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 22097#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 22098#L1451-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 23167#L1451-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 23168#L734-39 assume !(1 == ~t10_pc~0); 22531#L734-41 is_transmit10_triggered_~__retres1~10#1 := 0; 22532#L745-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 22862#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 22174#L1459-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 22175#L1459-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 23416#L753-39 assume 1 == ~t11_pc~0; 22804#L754-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 22094#L764-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 22992#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 22830#L1467-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 22831#L1467-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 22930#L1237-3 assume 1 == ~M_E~0;~M_E~0 := 2; 22931#L1237-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 23188#L1242-3 assume !(1 == ~T2_E~0); 23189#L1247-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 23399#L1252-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 23113#L1257-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 23114#L1262-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 23372#L1267-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 23420#L1272-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 23522#L1277-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 22247#L1282-3 assume !(1 == ~T10_E~0); 22248#L1287-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 22157#L1292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 22158#L1297-3 assume 1 == ~E_1~0;~E_1~0 := 2; 23294#L1302-3 assume 1 == ~E_2~0;~E_2~0 := 2; 23295#L1307-3 assume 1 == ~E_3~0;~E_3~0 := 2; 23475#L1312-3 assume 1 == ~E_4~0;~E_4~0 := 2; 23548#L1317-3 assume 1 == ~E_5~0;~E_5~0 := 2; 23208#L1322-3 assume !(1 == ~E_6~0); 23209#L1327-3 assume 1 == ~E_7~0;~E_7~0 := 2; 22213#L1332-3 assume 1 == ~E_8~0;~E_8~0 := 2; 22190#L1337-3 assume 1 == ~E_9~0;~E_9~0 := 2; 22191#L1342-3 assume 1 == ~E_10~0;~E_10~0 := 2; 22900#L1347-3 assume 1 == ~E_11~0;~E_11~0 := 2; 23022#L1352-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 23023#L848-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 22139#L910-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 22345#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 22346#L1697 assume !(0 == start_simulation_~tmp~3#1); 22920#L1697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 22921#L848-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 22264#L910-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 22032#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; 22033#L1652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 22989#L1659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 22990#stop_simulation_returnLabel#1 start_simulation_#t~ret32#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 23283#L1710 assume !(0 != start_simulation_~tmp___0~1#1); 23284#L1678-2 [2022-12-13 17:13:30,048 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 17:13:30,048 INFO L85 PathProgramCache]: Analyzing trace with hash -803392964, now seen corresponding path program 1 times [2022-12-13 17:13:30,048 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 17:13:30,048 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1201913781] [2022-12-13 17:13:30,049 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 17:13:30,049 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 17:13:30,059 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 17:13:30,085 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 17:13:30,085 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 17:13:30,085 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1201913781] [2022-12-13 17:13:30,085 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1201913781] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 17:13:30,086 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 17:13:30,086 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 17:13:30,086 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1162197206] [2022-12-13 17:13:30,086 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 17:13:30,086 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 17:13:30,087 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 17:13:30,087 INFO L85 PathProgramCache]: Analyzing trace with hash -1639996467, now seen corresponding path program 3 times [2022-12-13 17:13:30,087 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 17:13:30,087 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [761487877] [2022-12-13 17:13:30,088 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 17:13:30,088 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 17:13:30,097 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 17:13:30,124 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 17:13:30,124 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 17:13:30,125 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [761487877] [2022-12-13 17:13:30,125 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [761487877] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 17:13:30,125 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 17:13:30,125 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 17:13:30,125 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1380046151] [2022-12-13 17:13:30,125 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 17:13:30,126 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 17:13:30,126 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 17:13:30,126 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 17:13:30,126 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 17:13:30,126 INFO L87 Difference]: Start difference. First operand 1566 states and 2319 transitions. cyclomatic complexity: 754 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 17:13:30,158 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 17:13:30,158 INFO L93 Difference]: Finished difference Result 1566 states and 2318 transitions. [2022-12-13 17:13:30,158 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1566 states and 2318 transitions. [2022-12-13 17:13:30,165 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1415 [2022-12-13 17:13:30,171 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1566 states to 1566 states and 2318 transitions. [2022-12-13 17:13:30,172 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1566 [2022-12-13 17:13:30,173 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1566 [2022-12-13 17:13:30,173 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1566 states and 2318 transitions. [2022-12-13 17:13:30,175 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 17:13:30,176 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1566 states and 2318 transitions. [2022-12-13 17:13:30,178 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1566 states and 2318 transitions. [2022-12-13 17:13:30,190 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1566 to 1566. [2022-12-13 17:13:30,192 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1566 states, 1566 states have (on average 1.4802043422733078) internal successors, (2318), 1565 states have internal predecessors, (2318), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 17:13:30,194 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1566 states to 1566 states and 2318 transitions. [2022-12-13 17:13:30,195 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1566 states and 2318 transitions. [2022-12-13 17:13:30,195 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 17:13:30,195 INFO L428 stractBuchiCegarLoop]: Abstraction has 1566 states and 2318 transitions. [2022-12-13 17:13:30,195 INFO L335 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2022-12-13 17:13:30,195 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1566 states and 2318 transitions. [2022-12-13 17:13:30,199 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1415 [2022-12-13 17:13:30,199 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 17:13:30,199 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 17:13:30,200 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 17:13:30,201 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 17:13:30,201 INFO L748 eck$LassoCheckResult]: Stem: 25381#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 25382#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 26156#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 26157#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 25355#L780 assume 1 == ~m_i~0;~m_st~0 := 0; 25356#L780-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 26585#L785-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 26552#L790-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 26553#L795-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 25710#L800-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 25711#L805-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 26125#L810-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 26521#L815-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 25618#L820-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 25619#L825-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 25509#L830-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 25510#L835-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 26452#L1109 assume !(0 == ~M_E~0); 26468#L1109-2 assume !(0 == ~T1_E~0); 25518#L1114-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 25519#L1119-1 assume !(0 == ~T3_E~0); 26524#L1124-1 assume !(0 == ~T4_E~0); 25169#L1129-1 assume !(0 == ~T5_E~0); 25170#L1134-1 assume !(0 == ~T6_E~0); 25797#L1139-1 assume !(0 == ~T7_E~0); 26459#L1144-1 assume !(0 == ~T8_E~0); 26335#L1149-1 assume !(0 == ~T9_E~0); 25282#L1154-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 25283#L1159-1 assume !(0 == ~T11_E~0); 26325#L1164-1 assume !(0 == ~E_M~0); 25672#L1169-1 assume !(0 == ~E_1~0); 25570#L1174-1 assume !(0 == ~E_2~0); 25436#L1179-1 assume !(0 == ~E_3~0); 25361#L1184-1 assume !(0 == ~E_4~0); 25362#L1189-1 assume !(0 == ~E_5~0); 25394#L1194-1 assume 0 == ~E_6~0;~E_6~0 := 1; 25477#L1199-1 assume !(0 == ~E_7~0); 26344#L1204-1 assume !(0 == ~E_8~0); 26285#L1209-1 assume !(0 == ~E_9~0); 26286#L1214-1 assume !(0 == ~E_10~0); 26598#L1219-1 assume !(0 == ~E_11~0); 26684#L1224-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 25689#L544 assume 1 == ~m_pc~0; 25690#L545 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 26507#L555 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 26045#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 25323#L1379 assume !(0 != activate_threads_~tmp~1#1); 25324#L1379-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 26112#L563 assume !(1 == ~t1_pc~0); 25914#L563-2 is_transmit1_triggered_~__retres1~1#1 := 0; 25179#L574 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 25180#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 26232#L1387 assume !(0 != activate_threads_~tmp___0~0#1); 25175#L1387-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 25176#L582 assume 1 == ~t2_pc~0; 25892#L583 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 26237#L593 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 25514#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 25515#L1395 assume !(0 != activate_threads_~tmp___1~0#1); 25208#L1395-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 25209#L601 assume !(1 == ~t3_pc~0); 25909#L601-2 is_transmit3_triggered_~__retres1~3#1 := 0; 25908#L612 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 26363#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 26270#L1403 assume !(0 != activate_threads_~tmp___2~0#1); 26271#L1403-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 26218#L620 assume 1 == ~t4_pc~0; 25189#L621 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 25190#L631 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 25222#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 25223#L1411 assume !(0 != activate_threads_~tmp___3~0#1); 26122#L1411-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 26304#L639 assume 1 == ~t5_pc~0; 26192#L640 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 25484#L650 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 25485#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 26142#L1419 assume !(0 != activate_threads_~tmp___4~0#1); 26143#L1419-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 26077#L658 assume !(1 == ~t6_pc~0); 25686#L658-2 is_transmit6_triggered_~__retres1~6#1 := 0; 25687#L669 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 25506#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 25507#L1427 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 26274#L1427-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 25529#L677 assume 1 == ~t7_pc~0; 25530#L678 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 25427#L688 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 26424#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 26546#L1435 assume !(0 != activate_threads_~tmp___6~0#1); 26547#L1435-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 26617#L696 assume !(1 == ~t8_pc~0); 25751#L696-2 is_transmit8_triggered_~__retres1~8#1 := 0; 25752#L707 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 26583#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 26620#L1443 assume !(0 != activate_threads_~tmp___7~0#1); 26664#L1443-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 26180#L715 assume 1 == ~t9_pc~0; 26181#L716 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 25850#L726 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 25568#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 25569#L1451 assume !(0 != activate_threads_~tmp___8~0#1); 26163#L1451-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 26421#L734 assume !(1 == ~t10_pc~0); 26422#L734-2 is_transmit10_triggered_~__retres1~10#1 := 0; 25644#L745 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 25645#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 26365#L1459 assume !(0 != activate_threads_~tmp___9~0#1); 26366#L1459-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 25724#L753 assume 1 == ~t11_pc~0; 25725#L754 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 26279#L764 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 26592#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 25997#L1467 assume !(0 != activate_threads_~tmp___10~0#1); 25998#L1467-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 26052#L1237 assume !(1 == ~M_E~0); 26053#L1237-2 assume !(1 == ~T1_E~0); 26648#L1242-1 assume !(1 == ~T2_E~0); 25818#L1247-1 assume !(1 == ~T3_E~0); 25819#L1252-1 assume !(1 == ~T4_E~0); 25587#L1257-1 assume !(1 == ~T5_E~0); 25588#L1262-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 26441#L1267-1 assume !(1 == ~T7_E~0); 26539#L1272-1 assume !(1 == ~T8_E~0); 25903#L1277-1 assume !(1 == ~T9_E~0); 25904#L1282-1 assume !(1 == ~T10_E~0); 26312#L1287-1 assume !(1 == ~T11_E~0); 26313#L1292-1 assume !(1 == ~E_M~0); 26273#L1297-1 assume !(1 == ~E_1~0); 25715#L1302-1 assume 1 == ~E_2~0;~E_2~0 := 2; 25716#L1307-1 assume !(1 == ~E_3~0); 26528#L1312-1 assume !(1 == ~E_4~0); 25949#L1317-1 assume !(1 == ~E_5~0); 25950#L1322-1 assume !(1 == ~E_6~0); 25659#L1327-1 assume !(1 == ~E_7~0); 25660#L1332-1 assume !(1 == ~E_8~0); 26231#L1337-1 assume !(1 == ~E_9~0); 26166#L1342-1 assume 1 == ~E_10~0;~E_10~0 := 2; 26167#L1347-1 assume !(1 == ~E_11~0); 26527#L1352-1 assume { :end_inline_reset_delta_events } true; 26420#L1678-2 [2022-12-13 17:13:30,201 INFO L750 eck$LassoCheckResult]: Loop: 26420#L1678-2 assume !false; 26221#L1679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 26081#L1084 assume !false; 26016#L921 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 26017#L848 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 25299#L910 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 26513#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 25219#L925 assume !(0 != eval_~tmp~0#1); 25221#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 25708#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 25709#L1109-3 assume 0 == ~M_E~0;~M_E~0 := 1; 25192#L1109-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 25193#L1114-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 26275#L1119-3 assume !(0 == ~T3_E~0); 26276#L1124-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 26300#L1129-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 26301#L1134-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 26464#L1139-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 26516#L1144-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 25699#L1149-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 25700#L1154-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 25957#L1159-3 assume !(0 == ~T11_E~0); 25958#L1164-3 assume 0 == ~E_M~0;~E_M~0 := 1; 26214#L1169-3 assume 0 == ~E_1~0;~E_1~0 := 1; 26215#L1174-3 assume 0 == ~E_2~0;~E_2~0 := 1; 26263#L1179-3 assume 0 == ~E_3~0;~E_3~0 := 1; 26264#L1184-3 assume 0 == ~E_4~0;~E_4~0 := 1; 26404#L1189-3 assume 0 == ~E_5~0;~E_5~0 := 1; 26106#L1194-3 assume 0 == ~E_6~0;~E_6~0 := 1; 25459#L1199-3 assume !(0 == ~E_7~0); 25460#L1204-3 assume 0 == ~E_8~0;~E_8~0 := 1; 25683#L1209-3 assume 0 == ~E_9~0;~E_9~0 := 1; 25145#L1214-3 assume 0 == ~E_10~0;~E_10~0 := 1; 25146#L1219-3 assume 0 == ~E_11~0;~E_11~0 := 1; 25860#L1224-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 25861#L544-39 assume !(1 == ~m_pc~0); 25130#L544-41 is_master_triggered_~__retres1~0#1 := 0; 25131#L555-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 26183#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 25537#L1379-39 assume !(0 != activate_threads_~tmp~1#1); 25538#L1379-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 26391#L563-39 assume 1 == ~t1_pc~0; 26397#L564-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 25279#L574-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 26675#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 26676#L1387-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 26679#L1387-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 26498#L582-39 assume !(1 == ~t2_pc~0); 25600#L582-41 is_transmit2_triggered_~__retres1~2#1 := 0; 25601#L593-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 25926#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 25927#L1395-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 25372#L1395-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 25154#L601-39 assume 1 == ~t3_pc~0; 25155#L602-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 25203#L612-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 26361#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 26686#L1403-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 26395#L1403-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 26074#L620-39 assume !(1 == ~t4_pc~0); 26075#L620-41 is_transmit4_triggered_~__retres1~4#1 := 0; 26262#L631-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 26097#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 26098#L1411-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 26369#L1411-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 26690#L639-39 assume 1 == ~t5_pc~0; 26481#L640-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 25821#L650-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 25822#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 25181#L1419-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 25182#L1419-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 26109#L658-39 assume 1 == ~t6_pc~0; 26092#L659-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 26093#L669-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 26542#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 26284#L1427-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 26259#L1427-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 26260#L677-39 assume 1 == ~t7_pc~0; 26224#L678-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 25357#L688-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 25358#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 25415#L1435-39 assume !(0 != activate_threads_~tmp___6~0#1); 25416#L1435-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 25996#L696-39 assume 1 == ~t8_pc~0; 25964#L697-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 25844#L707-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 25845#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 26134#L1443-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 26102#L1443-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 25978#L715-39 assume 1 == ~t9_pc~0; 25157#L716-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 25158#L726-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 25234#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 25235#L1451-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 26306#L1451-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 26307#L734-39 assume !(1 == ~t10_pc~0); 25670#L734-41 is_transmit10_triggered_~__retres1~10#1 := 0; 25671#L745-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 26001#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 25313#L1459-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 25314#L1459-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 26555#L753-39 assume !(1 == ~t11_pc~0); 25232#L753-41 is_transmit11_triggered_~__retres1~11#1 := 0; 25233#L764-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 26131#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 25969#L1467-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 25970#L1467-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 26065#L1237-3 assume 1 == ~M_E~0;~M_E~0 := 2; 26066#L1237-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 26327#L1242-3 assume !(1 == ~T2_E~0); 26328#L1247-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 26537#L1252-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 26252#L1257-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 26253#L1262-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 26509#L1267-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 26559#L1272-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 26661#L1277-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 25385#L1282-3 assume !(1 == ~T10_E~0); 25386#L1287-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 25296#L1292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 25297#L1297-3 assume 1 == ~E_1~0;~E_1~0 := 2; 26431#L1302-3 assume 1 == ~E_2~0;~E_2~0 := 2; 26432#L1307-3 assume 1 == ~E_3~0;~E_3~0 := 2; 26614#L1312-3 assume 1 == ~E_4~0;~E_4~0 := 2; 26687#L1317-3 assume 1 == ~E_5~0;~E_5~0 := 2; 26347#L1322-3 assume !(1 == ~E_6~0); 26348#L1327-3 assume 1 == ~E_7~0;~E_7~0 := 2; 25352#L1332-3 assume 1 == ~E_8~0;~E_8~0 := 2; 25329#L1337-3 assume 1 == ~E_9~0;~E_9~0 := 2; 25330#L1342-3 assume 1 == ~E_10~0;~E_10~0 := 2; 26039#L1347-3 assume 1 == ~E_11~0;~E_11~0 := 2; 26161#L1352-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 26162#L848-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 25273#L910-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 25482#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 25483#L1697 assume !(0 == start_simulation_~tmp~3#1); 26059#L1697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 26060#L848-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 25403#L910-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 25171#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; 25172#L1652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 26128#L1659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 26129#stop_simulation_returnLabel#1 start_simulation_#t~ret32#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 26419#L1710 assume !(0 != start_simulation_~tmp___0~1#1); 26420#L1678-2 [2022-12-13 17:13:30,201 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 17:13:30,201 INFO L85 PathProgramCache]: Analyzing trace with hash -218621314, now seen corresponding path program 1 times [2022-12-13 17:13:30,201 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 17:13:30,201 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2098835984] [2022-12-13 17:13:30,202 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 17:13:30,202 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 17:13:30,209 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 17:13:30,227 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 17:13:30,227 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 17:13:30,228 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2098835984] [2022-12-13 17:13:30,228 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2098835984] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 17:13:30,228 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 17:13:30,228 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 17:13:30,228 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1141099473] [2022-12-13 17:13:30,228 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 17:13:30,228 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 17:13:30,228 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 17:13:30,228 INFO L85 PathProgramCache]: Analyzing trace with hash -1760785523, now seen corresponding path program 1 times [2022-12-13 17:13:30,229 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 17:13:30,229 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [274319676] [2022-12-13 17:13:30,229 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 17:13:30,229 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 17:13:30,237 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 17:13:30,267 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 17:13:30,267 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 17:13:30,267 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [274319676] [2022-12-13 17:13:30,267 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [274319676] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 17:13:30,268 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 17:13:30,268 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 17:13:30,268 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [493516195] [2022-12-13 17:13:30,268 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 17:13:30,268 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 17:13:30,268 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 17:13:30,268 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 17:13:30,268 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 17:13:30,269 INFO L87 Difference]: Start difference. First operand 1566 states and 2318 transitions. cyclomatic complexity: 753 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 17:13:30,287 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 17:13:30,288 INFO L93 Difference]: Finished difference Result 1566 states and 2317 transitions. [2022-12-13 17:13:30,288 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1566 states and 2317 transitions. [2022-12-13 17:13:30,292 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1415 [2022-12-13 17:13:30,296 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1566 states to 1566 states and 2317 transitions. [2022-12-13 17:13:30,296 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1566 [2022-12-13 17:13:30,297 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1566 [2022-12-13 17:13:30,297 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1566 states and 2317 transitions. [2022-12-13 17:13:30,298 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 17:13:30,298 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1566 states and 2317 transitions. [2022-12-13 17:13:30,300 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1566 states and 2317 transitions. [2022-12-13 17:13:30,311 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1566 to 1566. [2022-12-13 17:13:30,313 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1566 states, 1566 states have (on average 1.4795657726692208) internal successors, (2317), 1565 states have internal predecessors, (2317), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 17:13:30,315 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1566 states to 1566 states and 2317 transitions. [2022-12-13 17:13:30,315 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1566 states and 2317 transitions. [2022-12-13 17:13:30,315 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 17:13:30,316 INFO L428 stractBuchiCegarLoop]: Abstraction has 1566 states and 2317 transitions. [2022-12-13 17:13:30,316 INFO L335 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2022-12-13 17:13:30,316 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1566 states and 2317 transitions. [2022-12-13 17:13:30,326 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1415 [2022-12-13 17:13:30,326 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 17:13:30,326 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 17:13:30,328 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 17:13:30,328 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 17:13:30,329 INFO L748 eck$LassoCheckResult]: Stem: 28520#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 28521#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 29295#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 29296#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 28494#L780 assume 1 == ~m_i~0;~m_st~0 := 0; 28495#L780-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 29724#L785-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 29691#L790-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 29692#L795-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 28849#L800-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 28850#L805-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 29264#L810-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 29660#L815-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 28757#L820-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 28758#L825-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 28648#L830-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 28649#L835-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 29591#L1109 assume !(0 == ~M_E~0); 29607#L1109-2 assume !(0 == ~T1_E~0); 28657#L1114-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 28658#L1119-1 assume !(0 == ~T3_E~0); 29663#L1124-1 assume !(0 == ~T4_E~0); 28308#L1129-1 assume !(0 == ~T5_E~0); 28309#L1134-1 assume !(0 == ~T6_E~0); 28936#L1139-1 assume !(0 == ~T7_E~0); 29598#L1144-1 assume !(0 == ~T8_E~0); 29474#L1149-1 assume !(0 == ~T9_E~0); 28419#L1154-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 28420#L1159-1 assume !(0 == ~T11_E~0); 29464#L1164-1 assume !(0 == ~E_M~0); 28811#L1169-1 assume !(0 == ~E_1~0); 28709#L1174-1 assume !(0 == ~E_2~0); 28573#L1179-1 assume !(0 == ~E_3~0); 28500#L1184-1 assume !(0 == ~E_4~0); 28501#L1189-1 assume !(0 == ~E_5~0); 28533#L1194-1 assume 0 == ~E_6~0;~E_6~0 := 1; 28616#L1199-1 assume !(0 == ~E_7~0); 29483#L1204-1 assume !(0 == ~E_8~0); 29424#L1209-1 assume !(0 == ~E_9~0); 29425#L1214-1 assume !(0 == ~E_10~0); 29737#L1219-1 assume !(0 == ~E_11~0); 29823#L1224-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 28828#L544 assume 1 == ~m_pc~0; 28829#L545 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 29646#L555 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 29184#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 28462#L1379 assume !(0 != activate_threads_~tmp~1#1); 28463#L1379-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 29251#L563 assume !(1 == ~t1_pc~0); 29053#L563-2 is_transmit1_triggered_~__retres1~1#1 := 0; 28318#L574 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 28319#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 29371#L1387 assume !(0 != activate_threads_~tmp___0~0#1); 28314#L1387-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 28315#L582 assume 1 == ~t2_pc~0; 29031#L583 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 29376#L593 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 28653#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 28654#L1395 assume !(0 != activate_threads_~tmp___1~0#1); 28347#L1395-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 28348#L601 assume !(1 == ~t3_pc~0); 29048#L601-2 is_transmit3_triggered_~__retres1~3#1 := 0; 29047#L612 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 29502#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 29409#L1403 assume !(0 != activate_threads_~tmp___2~0#1); 29410#L1403-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 29357#L620 assume 1 == ~t4_pc~0; 28328#L621 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 28329#L631 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 28361#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 28362#L1411 assume !(0 != activate_threads_~tmp___3~0#1); 29261#L1411-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 29442#L639 assume 1 == ~t5_pc~0; 29331#L640 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 28621#L650 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 28622#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 29281#L1419 assume !(0 != activate_threads_~tmp___4~0#1); 29282#L1419-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 29216#L658 assume !(1 == ~t6_pc~0); 28825#L658-2 is_transmit6_triggered_~__retres1~6#1 := 0; 28826#L669 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 28645#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 28646#L1427 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 29413#L1427-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 28668#L677 assume 1 == ~t7_pc~0; 28669#L678 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 28566#L688 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 29563#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 29685#L1435 assume !(0 != activate_threads_~tmp___6~0#1); 29686#L1435-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 29756#L696 assume !(1 == ~t8_pc~0); 28889#L696-2 is_transmit8_triggered_~__retres1~8#1 := 0; 28890#L707 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 29722#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 29759#L1443 assume !(0 != activate_threads_~tmp___7~0#1); 29803#L1443-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 29319#L715 assume 1 == ~t9_pc~0; 29320#L716 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 28989#L726 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 28707#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 28708#L1451 assume !(0 != activate_threads_~tmp___8~0#1); 29302#L1451-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 29558#L734 assume !(1 == ~t10_pc~0); 29559#L734-2 is_transmit10_triggered_~__retres1~10#1 := 0; 28783#L745 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 28784#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 29504#L1459 assume !(0 != activate_threads_~tmp___9~0#1); 29505#L1459-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 28863#L753 assume 1 == ~t11_pc~0; 28864#L754 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 29418#L764 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 29731#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 29134#L1467 assume !(0 != activate_threads_~tmp___10~0#1); 29135#L1467-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 29191#L1237 assume !(1 == ~M_E~0); 29192#L1237-2 assume !(1 == ~T1_E~0); 29786#L1242-1 assume !(1 == ~T2_E~0); 28957#L1247-1 assume !(1 == ~T3_E~0); 28958#L1252-1 assume !(1 == ~T4_E~0); 28726#L1257-1 assume !(1 == ~T5_E~0); 28727#L1262-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 29580#L1267-1 assume !(1 == ~T7_E~0); 29678#L1272-1 assume !(1 == ~T8_E~0); 29042#L1277-1 assume !(1 == ~T9_E~0); 29043#L1282-1 assume !(1 == ~T10_E~0); 29451#L1287-1 assume !(1 == ~T11_E~0); 29452#L1292-1 assume !(1 == ~E_M~0); 29412#L1297-1 assume !(1 == ~E_1~0); 28854#L1302-1 assume 1 == ~E_2~0;~E_2~0 := 2; 28855#L1307-1 assume !(1 == ~E_3~0); 29667#L1312-1 assume !(1 == ~E_4~0); 29088#L1317-1 assume !(1 == ~E_5~0); 29089#L1322-1 assume !(1 == ~E_6~0); 28798#L1327-1 assume !(1 == ~E_7~0); 28799#L1332-1 assume !(1 == ~E_8~0); 29370#L1337-1 assume !(1 == ~E_9~0); 29305#L1342-1 assume 1 == ~E_10~0;~E_10~0 := 2; 29306#L1347-1 assume !(1 == ~E_11~0); 29666#L1352-1 assume { :end_inline_reset_delta_events } true; 29562#L1678-2 [2022-12-13 17:13:30,329 INFO L750 eck$LassoCheckResult]: Loop: 29562#L1678-2 assume !false; 29360#L1679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 29220#L1084 assume !false; 29155#L921 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 29156#L848 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 28438#L910 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 29652#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 28358#L925 assume !(0 != eval_~tmp~0#1); 28360#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 28847#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 28848#L1109-3 assume 0 == ~M_E~0;~M_E~0 := 1; 28331#L1109-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 28332#L1114-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 29414#L1119-3 assume !(0 == ~T3_E~0); 29415#L1124-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 29439#L1129-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 29440#L1134-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 29603#L1139-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 29655#L1144-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 28838#L1149-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 28839#L1154-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 29095#L1159-3 assume !(0 == ~T11_E~0); 29096#L1164-3 assume 0 == ~E_M~0;~E_M~0 := 1; 29353#L1169-3 assume 0 == ~E_1~0;~E_1~0 := 1; 29354#L1174-3 assume 0 == ~E_2~0;~E_2~0 := 1; 29402#L1179-3 assume 0 == ~E_3~0;~E_3~0 := 1; 29403#L1184-3 assume 0 == ~E_4~0;~E_4~0 := 1; 29543#L1189-3 assume 0 == ~E_5~0;~E_5~0 := 1; 29245#L1194-3 assume 0 == ~E_6~0;~E_6~0 := 1; 28595#L1199-3 assume !(0 == ~E_7~0); 28596#L1204-3 assume 0 == ~E_8~0;~E_8~0 := 1; 28818#L1209-3 assume 0 == ~E_9~0;~E_9~0 := 1; 28281#L1214-3 assume 0 == ~E_10~0;~E_10~0 := 1; 28282#L1219-3 assume 0 == ~E_11~0;~E_11~0 := 1; 28999#L1224-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 29000#L544-39 assume 1 == ~m_pc~0; 29345#L545-13 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 28270#L555-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 29322#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 28676#L1379-39 assume !(0 != activate_threads_~tmp~1#1); 28677#L1379-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 29530#L563-39 assume 1 == ~t1_pc~0; 29536#L564-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 28415#L574-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 29814#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 29815#L1387-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 29818#L1387-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 29637#L582-39 assume 1 == ~t2_pc~0; 28738#L583-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 28740#L593-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 29065#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 29066#L1395-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 28509#L1395-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 28293#L601-39 assume 1 == ~t3_pc~0; 28294#L602-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 28342#L612-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 29500#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 29825#L1403-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 29534#L1403-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 29211#L620-39 assume !(1 == ~t4_pc~0); 29212#L620-41 is_transmit4_triggered_~__retres1~4#1 := 0; 29401#L631-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 29236#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 29237#L1411-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 29508#L1411-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 29829#L639-39 assume 1 == ~t5_pc~0; 29620#L640-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 28960#L650-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 28961#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 28320#L1419-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 28321#L1419-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 29248#L658-39 assume !(1 == ~t6_pc~0); 29233#L658-41 is_transmit6_triggered_~__retres1~6#1 := 0; 29232#L669-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 29681#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 29423#L1427-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 29398#L1427-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 29399#L677-39 assume !(1 == ~t7_pc~0); 29040#L677-41 is_transmit7_triggered_~__retres1~7#1 := 0; 28498#L688-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 28499#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 28554#L1435-39 assume !(0 != activate_threads_~tmp___6~0#1); 28555#L1435-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 29137#L696-39 assume !(1 == ~t8_pc~0); 29104#L696-41 is_transmit8_triggered_~__retres1~8#1 := 0; 28983#L707-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 28984#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 29273#L1443-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 29241#L1443-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 29117#L715-39 assume 1 == ~t9_pc~0; 28298#L716-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 28299#L726-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 28375#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 28376#L1451-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 29445#L1451-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 29446#L734-39 assume !(1 == ~t10_pc~0); 28809#L734-41 is_transmit10_triggered_~__retres1~10#1 := 0; 28810#L745-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 29140#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 28452#L1459-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 28453#L1459-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 29694#L753-39 assume !(1 == ~t11_pc~0); 28371#L753-41 is_transmit11_triggered_~__retres1~11#1 := 0; 28372#L764-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 29270#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 29108#L1467-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 29109#L1467-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 29208#L1237-3 assume 1 == ~M_E~0;~M_E~0 := 2; 29209#L1237-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 29466#L1242-3 assume !(1 == ~T2_E~0); 29467#L1247-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 29677#L1252-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 29391#L1257-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 29392#L1262-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 29650#L1267-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 29698#L1272-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 29800#L1277-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 28525#L1282-3 assume !(1 == ~T10_E~0); 28526#L1287-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 28435#L1292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 28436#L1297-3 assume 1 == ~E_1~0;~E_1~0 := 2; 29572#L1302-3 assume 1 == ~E_2~0;~E_2~0 := 2; 29573#L1307-3 assume 1 == ~E_3~0;~E_3~0 := 2; 29753#L1312-3 assume 1 == ~E_4~0;~E_4~0 := 2; 29826#L1317-3 assume 1 == ~E_5~0;~E_5~0 := 2; 29486#L1322-3 assume !(1 == ~E_6~0); 29487#L1327-3 assume 1 == ~E_7~0;~E_7~0 := 2; 28491#L1332-3 assume 1 == ~E_8~0;~E_8~0 := 2; 28468#L1337-3 assume 1 == ~E_9~0;~E_9~0 := 2; 28469#L1342-3 assume 1 == ~E_10~0;~E_10~0 := 2; 29178#L1347-3 assume 1 == ~E_11~0;~E_11~0 := 2; 29300#L1352-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 29301#L848-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 28417#L910-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 28623#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 28624#L1697 assume !(0 == start_simulation_~tmp~3#1); 29198#L1697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 29199#L848-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 28542#L910-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 28310#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; 28311#L1652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 29267#L1659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 29268#stop_simulation_returnLabel#1 start_simulation_#t~ret32#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 29561#L1710 assume !(0 != start_simulation_~tmp___0~1#1); 29562#L1678-2 [2022-12-13 17:13:30,329 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 17:13:30,329 INFO L85 PathProgramCache]: Analyzing trace with hash 215884284, now seen corresponding path program 1 times [2022-12-13 17:13:30,329 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 17:13:30,330 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2105544423] [2022-12-13 17:13:30,330 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 17:13:30,330 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 17:13:30,340 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 17:13:30,367 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 17:13:30,367 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 17:13:30,367 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2105544423] [2022-12-13 17:13:30,367 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2105544423] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 17:13:30,368 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 17:13:30,368 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 17:13:30,368 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [354145209] [2022-12-13 17:13:30,368 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 17:13:30,368 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 17:13:30,368 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 17:13:30,368 INFO L85 PathProgramCache]: Analyzing trace with hash 2068281230, now seen corresponding path program 1 times [2022-12-13 17:13:30,368 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 17:13:30,369 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1879527974] [2022-12-13 17:13:30,369 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 17:13:30,369 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 17:13:30,377 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 17:13:30,401 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 17:13:30,401 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 17:13:30,401 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1879527974] [2022-12-13 17:13:30,401 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1879527974] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 17:13:30,401 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 17:13:30,402 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 17:13:30,402 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [885058703] [2022-12-13 17:13:30,402 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 17:13:30,402 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 17:13:30,402 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 17:13:30,402 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 17:13:30,402 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 17:13:30,402 INFO L87 Difference]: Start difference. First operand 1566 states and 2317 transitions. cyclomatic complexity: 752 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 17:13:30,421 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 17:13:30,421 INFO L93 Difference]: Finished difference Result 1566 states and 2316 transitions. [2022-12-13 17:13:30,422 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1566 states and 2316 transitions. [2022-12-13 17:13:30,426 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1415 [2022-12-13 17:13:30,430 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1566 states to 1566 states and 2316 transitions. [2022-12-13 17:13:30,430 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1566 [2022-12-13 17:13:30,430 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1566 [2022-12-13 17:13:30,431 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1566 states and 2316 transitions. [2022-12-13 17:13:30,432 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 17:13:30,432 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1566 states and 2316 transitions. [2022-12-13 17:13:30,433 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1566 states and 2316 transitions. [2022-12-13 17:13:30,444 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1566 to 1566. [2022-12-13 17:13:30,446 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1566 states, 1566 states have (on average 1.4789272030651341) internal successors, (2316), 1565 states have internal predecessors, (2316), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 17:13:30,448 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1566 states to 1566 states and 2316 transitions. [2022-12-13 17:13:30,448 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1566 states and 2316 transitions. [2022-12-13 17:13:30,449 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 17:13:30,449 INFO L428 stractBuchiCegarLoop]: Abstraction has 1566 states and 2316 transitions. [2022-12-13 17:13:30,449 INFO L335 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2022-12-13 17:13:30,449 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1566 states and 2316 transitions. [2022-12-13 17:13:30,453 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1415 [2022-12-13 17:13:30,453 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 17:13:30,453 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 17:13:30,454 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 17:13:30,454 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 17:13:30,454 INFO L748 eck$LassoCheckResult]: Stem: 31659#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 31660#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 32434#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 32435#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 31633#L780 assume 1 == ~m_i~0;~m_st~0 := 0; 31634#L780-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 32863#L785-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 32830#L790-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 32831#L795-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 31988#L800-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 31989#L805-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 32403#L810-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 32799#L815-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 31896#L820-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 31897#L825-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 31787#L830-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 31788#L835-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 32730#L1109 assume !(0 == ~M_E~0); 32746#L1109-2 assume !(0 == ~T1_E~0); 31796#L1114-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 31797#L1119-1 assume !(0 == ~T3_E~0); 32802#L1124-1 assume !(0 == ~T4_E~0); 31447#L1129-1 assume !(0 == ~T5_E~0); 31448#L1134-1 assume !(0 == ~T6_E~0); 32075#L1139-1 assume !(0 == ~T7_E~0); 32737#L1144-1 assume !(0 == ~T8_E~0); 32613#L1149-1 assume !(0 == ~T9_E~0); 31558#L1154-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 31559#L1159-1 assume !(0 == ~T11_E~0); 32603#L1164-1 assume !(0 == ~E_M~0); 31950#L1169-1 assume !(0 == ~E_1~0); 31848#L1174-1 assume !(0 == ~E_2~0); 31712#L1179-1 assume !(0 == ~E_3~0); 31639#L1184-1 assume !(0 == ~E_4~0); 31640#L1189-1 assume !(0 == ~E_5~0); 31672#L1194-1 assume 0 == ~E_6~0;~E_6~0 := 1; 31755#L1199-1 assume !(0 == ~E_7~0); 32622#L1204-1 assume !(0 == ~E_8~0); 32563#L1209-1 assume !(0 == ~E_9~0); 32564#L1214-1 assume !(0 == ~E_10~0); 32876#L1219-1 assume !(0 == ~E_11~0); 32962#L1224-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 31967#L544 assume 1 == ~m_pc~0; 31968#L545 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 32785#L555 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 32323#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 31601#L1379 assume !(0 != activate_threads_~tmp~1#1); 31602#L1379-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 32390#L563 assume !(1 == ~t1_pc~0); 32192#L563-2 is_transmit1_triggered_~__retres1~1#1 := 0; 31457#L574 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 31458#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 32510#L1387 assume !(0 != activate_threads_~tmp___0~0#1); 31453#L1387-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 31454#L582 assume 1 == ~t2_pc~0; 32170#L583 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 32515#L593 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 31792#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 31793#L1395 assume !(0 != activate_threads_~tmp___1~0#1); 31486#L1395-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 31487#L601 assume !(1 == ~t3_pc~0); 32187#L601-2 is_transmit3_triggered_~__retres1~3#1 := 0; 32186#L612 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 32641#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 32548#L1403 assume !(0 != activate_threads_~tmp___2~0#1); 32549#L1403-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 32496#L620 assume 1 == ~t4_pc~0; 31467#L621 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 31468#L631 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 31500#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 31501#L1411 assume !(0 != activate_threads_~tmp___3~0#1); 32400#L1411-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 32581#L639 assume 1 == ~t5_pc~0; 32470#L640 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 31760#L650 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 31761#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 32420#L1419 assume !(0 != activate_threads_~tmp___4~0#1); 32421#L1419-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 32355#L658 assume !(1 == ~t6_pc~0); 31964#L658-2 is_transmit6_triggered_~__retres1~6#1 := 0; 31965#L669 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 31784#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 31785#L1427 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 32552#L1427-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 31807#L677 assume 1 == ~t7_pc~0; 31808#L678 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 31705#L688 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 32702#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 32824#L1435 assume !(0 != activate_threads_~tmp___6~0#1); 32825#L1435-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 32895#L696 assume !(1 == ~t8_pc~0); 32028#L696-2 is_transmit8_triggered_~__retres1~8#1 := 0; 32029#L707 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 32861#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 32898#L1443 assume !(0 != activate_threads_~tmp___7~0#1); 32942#L1443-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 32458#L715 assume 1 == ~t9_pc~0; 32459#L716 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 32128#L726 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 31846#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 31847#L1451 assume !(0 != activate_threads_~tmp___8~0#1); 32441#L1451-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 32697#L734 assume !(1 == ~t10_pc~0); 32698#L734-2 is_transmit10_triggered_~__retres1~10#1 := 0; 31922#L745 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 31923#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 32643#L1459 assume !(0 != activate_threads_~tmp___9~0#1); 32644#L1459-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 32002#L753 assume 1 == ~t11_pc~0; 32003#L754 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 32557#L764 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 32870#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 32273#L1467 assume !(0 != activate_threads_~tmp___10~0#1); 32274#L1467-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 32330#L1237 assume !(1 == ~M_E~0); 32331#L1237-2 assume !(1 == ~T1_E~0); 32925#L1242-1 assume !(1 == ~T2_E~0); 32096#L1247-1 assume !(1 == ~T3_E~0); 32097#L1252-1 assume !(1 == ~T4_E~0); 31865#L1257-1 assume !(1 == ~T5_E~0); 31866#L1262-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 32719#L1267-1 assume !(1 == ~T7_E~0); 32817#L1272-1 assume !(1 == ~T8_E~0); 32181#L1277-1 assume !(1 == ~T9_E~0); 32182#L1282-1 assume !(1 == ~T10_E~0); 32590#L1287-1 assume !(1 == ~T11_E~0); 32591#L1292-1 assume !(1 == ~E_M~0); 32551#L1297-1 assume !(1 == ~E_1~0); 31993#L1302-1 assume 1 == ~E_2~0;~E_2~0 := 2; 31994#L1307-1 assume !(1 == ~E_3~0); 32806#L1312-1 assume !(1 == ~E_4~0); 32227#L1317-1 assume !(1 == ~E_5~0); 32228#L1322-1 assume !(1 == ~E_6~0); 31937#L1327-1 assume !(1 == ~E_7~0); 31938#L1332-1 assume !(1 == ~E_8~0); 32509#L1337-1 assume !(1 == ~E_9~0); 32444#L1342-1 assume 1 == ~E_10~0;~E_10~0 := 2; 32445#L1347-1 assume !(1 == ~E_11~0); 32805#L1352-1 assume { :end_inline_reset_delta_events } true; 32701#L1678-2 [2022-12-13 17:13:30,455 INFO L750 eck$LassoCheckResult]: Loop: 32701#L1678-2 assume !false; 32499#L1679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 32359#L1084 assume !false; 32294#L921 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 32295#L848 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 31577#L910 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 32791#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 31497#L925 assume !(0 != eval_~tmp~0#1); 31499#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 31986#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 31987#L1109-3 assume 0 == ~M_E~0;~M_E~0 := 1; 31470#L1109-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 31471#L1114-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 32553#L1119-3 assume !(0 == ~T3_E~0); 32554#L1124-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 32578#L1129-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 32579#L1134-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 32742#L1139-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 32794#L1144-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 31977#L1149-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 31978#L1154-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 32234#L1159-3 assume !(0 == ~T11_E~0); 32235#L1164-3 assume 0 == ~E_M~0;~E_M~0 := 1; 32492#L1169-3 assume 0 == ~E_1~0;~E_1~0 := 1; 32493#L1174-3 assume 0 == ~E_2~0;~E_2~0 := 1; 32541#L1179-3 assume 0 == ~E_3~0;~E_3~0 := 1; 32542#L1184-3 assume 0 == ~E_4~0;~E_4~0 := 1; 32682#L1189-3 assume 0 == ~E_5~0;~E_5~0 := 1; 32384#L1194-3 assume 0 == ~E_6~0;~E_6~0 := 1; 31734#L1199-3 assume !(0 == ~E_7~0); 31735#L1204-3 assume 0 == ~E_8~0;~E_8~0 := 1; 31957#L1209-3 assume 0 == ~E_9~0;~E_9~0 := 1; 31420#L1214-3 assume 0 == ~E_10~0;~E_10~0 := 1; 31421#L1219-3 assume 0 == ~E_11~0;~E_11~0 := 1; 32138#L1224-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 32139#L544-39 assume !(1 == ~m_pc~0); 31408#L544-41 is_master_triggered_~__retres1~0#1 := 0; 31409#L555-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 32461#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 31815#L1379-39 assume !(0 != activate_threads_~tmp~1#1); 31816#L1379-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 32669#L563-39 assume !(1 == ~t1_pc~0); 31553#L563-41 is_transmit1_triggered_~__retres1~1#1 := 0; 31554#L574-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 32953#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 32954#L1387-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 32957#L1387-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 32776#L582-39 assume 1 == ~t2_pc~0; 31877#L583-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 31879#L593-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 32204#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 32205#L1395-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 31648#L1395-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 31432#L601-39 assume 1 == ~t3_pc~0; 31433#L602-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 31481#L612-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 32639#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 32964#L1403-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 32673#L1403-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 32350#L620-39 assume 1 == ~t4_pc~0; 32352#L621-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 32540#L631-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 32375#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 32376#L1411-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 32647#L1411-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 32968#L639-39 assume 1 == ~t5_pc~0; 32759#L640-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 32099#L650-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 32100#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 31459#L1419-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 31460#L1419-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 32387#L658-39 assume 1 == ~t6_pc~0; 32370#L659-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 32371#L669-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 32820#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 32562#L1427-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 32537#L1427-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 32538#L677-39 assume !(1 == ~t7_pc~0); 32179#L677-41 is_transmit7_triggered_~__retres1~7#1 := 0; 31637#L688-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 31638#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 31693#L1435-39 assume !(0 != activate_threads_~tmp___6~0#1); 31694#L1435-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 32276#L696-39 assume 1 == ~t8_pc~0; 32242#L697-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 32122#L707-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 32123#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 32412#L1443-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 32380#L1443-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 32256#L715-39 assume 1 == ~t9_pc~0; 31437#L716-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 31438#L726-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 31514#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 31515#L1451-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 32584#L1451-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 32585#L734-39 assume 1 == ~t10_pc~0; 32513#L735-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 31949#L745-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 32279#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 31591#L1459-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 31592#L1459-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 32833#L753-39 assume !(1 == ~t11_pc~0); 31510#L753-41 is_transmit11_triggered_~__retres1~11#1 := 0; 31511#L764-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 32409#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 32247#L1467-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 32248#L1467-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 32347#L1237-3 assume 1 == ~M_E~0;~M_E~0 := 2; 32348#L1237-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 32605#L1242-3 assume !(1 == ~T2_E~0); 32606#L1247-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 32816#L1252-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 32530#L1257-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 32531#L1262-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 32789#L1267-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 32837#L1272-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 32939#L1277-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 31664#L1282-3 assume !(1 == ~T10_E~0); 31665#L1287-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 31574#L1292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 31575#L1297-3 assume 1 == ~E_1~0;~E_1~0 := 2; 32711#L1302-3 assume 1 == ~E_2~0;~E_2~0 := 2; 32712#L1307-3 assume 1 == ~E_3~0;~E_3~0 := 2; 32892#L1312-3 assume 1 == ~E_4~0;~E_4~0 := 2; 32965#L1317-3 assume 1 == ~E_5~0;~E_5~0 := 2; 32625#L1322-3 assume !(1 == ~E_6~0); 32626#L1327-3 assume 1 == ~E_7~0;~E_7~0 := 2; 31630#L1332-3 assume 1 == ~E_8~0;~E_8~0 := 2; 31607#L1337-3 assume 1 == ~E_9~0;~E_9~0 := 2; 31608#L1342-3 assume 1 == ~E_10~0;~E_10~0 := 2; 32317#L1347-3 assume 1 == ~E_11~0;~E_11~0 := 2; 32439#L1352-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 32440#L848-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 31556#L910-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 31762#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 31763#L1697 assume !(0 == start_simulation_~tmp~3#1); 32337#L1697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 32338#L848-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 31681#L910-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 31449#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; 31450#L1652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 32406#L1659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 32407#stop_simulation_returnLabel#1 start_simulation_#t~ret32#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 32700#L1710 assume !(0 != start_simulation_~tmp___0~1#1); 32701#L1678-2 [2022-12-13 17:13:30,455 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 17:13:30,455 INFO L85 PathProgramCache]: Analyzing trace with hash 922480890, now seen corresponding path program 1 times [2022-12-13 17:13:30,455 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 17:13:30,455 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [126136982] [2022-12-13 17:13:30,455 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 17:13:30,455 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 17:13:30,462 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 17:13:30,481 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 17:13:30,481 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 17:13:30,481 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [126136982] [2022-12-13 17:13:30,481 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [126136982] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 17:13:30,482 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 17:13:30,482 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 17:13:30,482 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2121186332] [2022-12-13 17:13:30,482 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 17:13:30,482 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 17:13:30,482 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 17:13:30,482 INFO L85 PathProgramCache]: Analyzing trace with hash 7517132, now seen corresponding path program 1 times [2022-12-13 17:13:30,482 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 17:13:30,482 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1998604577] [2022-12-13 17:13:30,483 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 17:13:30,483 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 17:13:30,491 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 17:13:30,518 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 17:13:30,518 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 17:13:30,519 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1998604577] [2022-12-13 17:13:30,519 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1998604577] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 17:13:30,519 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 17:13:30,519 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 17:13:30,519 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1988357111] [2022-12-13 17:13:30,519 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 17:13:30,519 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 17:13:30,519 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 17:13:30,519 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 17:13:30,520 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 17:13:30,520 INFO L87 Difference]: Start difference. First operand 1566 states and 2316 transitions. cyclomatic complexity: 751 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 17:13:30,541 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 17:13:30,541 INFO L93 Difference]: Finished difference Result 1566 states and 2315 transitions. [2022-12-13 17:13:30,541 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1566 states and 2315 transitions. [2022-12-13 17:13:30,545 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1415 [2022-12-13 17:13:30,549 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1566 states to 1566 states and 2315 transitions. [2022-12-13 17:13:30,549 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1566 [2022-12-13 17:13:30,550 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1566 [2022-12-13 17:13:30,550 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1566 states and 2315 transitions. [2022-12-13 17:13:30,551 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 17:13:30,551 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1566 states and 2315 transitions. [2022-12-13 17:13:30,552 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1566 states and 2315 transitions. [2022-12-13 17:13:30,564 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1566 to 1566. [2022-12-13 17:13:30,566 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1566 states, 1566 states have (on average 1.4782886334610472) internal successors, (2315), 1565 states have internal predecessors, (2315), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 17:13:30,568 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1566 states to 1566 states and 2315 transitions. [2022-12-13 17:13:30,568 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1566 states and 2315 transitions. [2022-12-13 17:13:30,568 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 17:13:30,569 INFO L428 stractBuchiCegarLoop]: Abstraction has 1566 states and 2315 transitions. [2022-12-13 17:13:30,569 INFO L335 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2022-12-13 17:13:30,569 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1566 states and 2315 transitions. [2022-12-13 17:13:30,572 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1415 [2022-12-13 17:13:30,573 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 17:13:30,573 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 17:13:30,574 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 17:13:30,574 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 17:13:30,574 INFO L748 eck$LassoCheckResult]: Stem: 34798#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 34799#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 35573#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 35574#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 34772#L780 assume 1 == ~m_i~0;~m_st~0 := 0; 34773#L780-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 36002#L785-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 35969#L790-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 35970#L795-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 35127#L800-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 35128#L805-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 35542#L810-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 35938#L815-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 35035#L820-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 35036#L825-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 34926#L830-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 34927#L835-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 35869#L1109 assume !(0 == ~M_E~0); 35885#L1109-2 assume !(0 == ~T1_E~0); 34935#L1114-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 34936#L1119-1 assume !(0 == ~T3_E~0); 35941#L1124-1 assume !(0 == ~T4_E~0); 34586#L1129-1 assume !(0 == ~T5_E~0); 34587#L1134-1 assume !(0 == ~T6_E~0); 35214#L1139-1 assume !(0 == ~T7_E~0); 35876#L1144-1 assume !(0 == ~T8_E~0); 35752#L1149-1 assume !(0 == ~T9_E~0); 34697#L1154-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 34698#L1159-1 assume !(0 == ~T11_E~0); 35742#L1164-1 assume !(0 == ~E_M~0); 35089#L1169-1 assume !(0 == ~E_1~0); 34987#L1174-1 assume !(0 == ~E_2~0); 34851#L1179-1 assume !(0 == ~E_3~0); 34778#L1184-1 assume !(0 == ~E_4~0); 34779#L1189-1 assume !(0 == ~E_5~0); 34811#L1194-1 assume 0 == ~E_6~0;~E_6~0 := 1; 34894#L1199-1 assume !(0 == ~E_7~0); 35761#L1204-1 assume !(0 == ~E_8~0); 35702#L1209-1 assume !(0 == ~E_9~0); 35703#L1214-1 assume !(0 == ~E_10~0); 36015#L1219-1 assume !(0 == ~E_11~0); 36101#L1224-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 35106#L544 assume 1 == ~m_pc~0; 35107#L545 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 35924#L555 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 35462#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 34740#L1379 assume !(0 != activate_threads_~tmp~1#1); 34741#L1379-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 35529#L563 assume !(1 == ~t1_pc~0); 35331#L563-2 is_transmit1_triggered_~__retres1~1#1 := 0; 34596#L574 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 34597#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 35649#L1387 assume !(0 != activate_threads_~tmp___0~0#1); 34592#L1387-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 34593#L582 assume 1 == ~t2_pc~0; 35309#L583 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 35654#L593 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 34931#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 34932#L1395 assume !(0 != activate_threads_~tmp___1~0#1); 34625#L1395-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 34626#L601 assume !(1 == ~t3_pc~0); 35326#L601-2 is_transmit3_triggered_~__retres1~3#1 := 0; 35325#L612 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 35780#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 35687#L1403 assume !(0 != activate_threads_~tmp___2~0#1); 35688#L1403-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 35635#L620 assume 1 == ~t4_pc~0; 34606#L621 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 34607#L631 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 34639#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 34640#L1411 assume !(0 != activate_threads_~tmp___3~0#1); 35539#L1411-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 35720#L639 assume 1 == ~t5_pc~0; 35609#L640 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 34899#L650 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 34900#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 35559#L1419 assume !(0 != activate_threads_~tmp___4~0#1); 35560#L1419-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 35494#L658 assume !(1 == ~t6_pc~0); 35103#L658-2 is_transmit6_triggered_~__retres1~6#1 := 0; 35104#L669 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 34923#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 34924#L1427 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 35691#L1427-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 34946#L677 assume 1 == ~t7_pc~0; 34947#L678 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 34844#L688 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 35841#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 35963#L1435 assume !(0 != activate_threads_~tmp___6~0#1); 35964#L1435-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 36034#L696 assume !(1 == ~t8_pc~0); 35167#L696-2 is_transmit8_triggered_~__retres1~8#1 := 0; 35168#L707 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 36000#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 36037#L1443 assume !(0 != activate_threads_~tmp___7~0#1); 36081#L1443-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 35597#L715 assume 1 == ~t9_pc~0; 35598#L716 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 35267#L726 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 34985#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 34986#L1451 assume !(0 != activate_threads_~tmp___8~0#1); 35580#L1451-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 35836#L734 assume !(1 == ~t10_pc~0); 35837#L734-2 is_transmit10_triggered_~__retres1~10#1 := 0; 35061#L745 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 35062#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 35782#L1459 assume !(0 != activate_threads_~tmp___9~0#1); 35783#L1459-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 35141#L753 assume 1 == ~t11_pc~0; 35142#L754 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 35696#L764 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 36009#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 35412#L1467 assume !(0 != activate_threads_~tmp___10~0#1); 35413#L1467-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 35469#L1237 assume !(1 == ~M_E~0); 35470#L1237-2 assume !(1 == ~T1_E~0); 36064#L1242-1 assume !(1 == ~T2_E~0); 35235#L1247-1 assume !(1 == ~T3_E~0); 35236#L1252-1 assume !(1 == ~T4_E~0); 35004#L1257-1 assume !(1 == ~T5_E~0); 35005#L1262-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 35858#L1267-1 assume !(1 == ~T7_E~0); 35956#L1272-1 assume !(1 == ~T8_E~0); 35320#L1277-1 assume !(1 == ~T9_E~0); 35321#L1282-1 assume !(1 == ~T10_E~0); 35729#L1287-1 assume !(1 == ~T11_E~0); 35730#L1292-1 assume !(1 == ~E_M~0); 35690#L1297-1 assume !(1 == ~E_1~0); 35132#L1302-1 assume 1 == ~E_2~0;~E_2~0 := 2; 35133#L1307-1 assume !(1 == ~E_3~0); 35945#L1312-1 assume !(1 == ~E_4~0); 35366#L1317-1 assume !(1 == ~E_5~0); 35367#L1322-1 assume !(1 == ~E_6~0); 35076#L1327-1 assume !(1 == ~E_7~0); 35077#L1332-1 assume !(1 == ~E_8~0); 35648#L1337-1 assume !(1 == ~E_9~0); 35583#L1342-1 assume 1 == ~E_10~0;~E_10~0 := 2; 35584#L1347-1 assume !(1 == ~E_11~0); 35944#L1352-1 assume { :end_inline_reset_delta_events } true; 35840#L1678-2 [2022-12-13 17:13:30,574 INFO L750 eck$LassoCheckResult]: Loop: 35840#L1678-2 assume !false; 35638#L1679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 35498#L1084 assume !false; 35433#L921 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 35434#L848 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 34716#L910 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 35930#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 34636#L925 assume !(0 != eval_~tmp~0#1); 34638#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 35125#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 35126#L1109-3 assume 0 == ~M_E~0;~M_E~0 := 1; 34609#L1109-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 34610#L1114-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 35692#L1119-3 assume !(0 == ~T3_E~0); 35693#L1124-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 35717#L1129-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 35718#L1134-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 35881#L1139-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 35933#L1144-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 35116#L1149-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 35117#L1154-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 35373#L1159-3 assume !(0 == ~T11_E~0); 35374#L1164-3 assume 0 == ~E_M~0;~E_M~0 := 1; 35631#L1169-3 assume 0 == ~E_1~0;~E_1~0 := 1; 35632#L1174-3 assume 0 == ~E_2~0;~E_2~0 := 1; 35680#L1179-3 assume 0 == ~E_3~0;~E_3~0 := 1; 35681#L1184-3 assume 0 == ~E_4~0;~E_4~0 := 1; 35821#L1189-3 assume 0 == ~E_5~0;~E_5~0 := 1; 35523#L1194-3 assume 0 == ~E_6~0;~E_6~0 := 1; 34873#L1199-3 assume !(0 == ~E_7~0); 34874#L1204-3 assume 0 == ~E_8~0;~E_8~0 := 1; 35096#L1209-3 assume 0 == ~E_9~0;~E_9~0 := 1; 34559#L1214-3 assume 0 == ~E_10~0;~E_10~0 := 1; 34560#L1219-3 assume 0 == ~E_11~0;~E_11~0 := 1; 35277#L1224-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 35278#L544-39 assume !(1 == ~m_pc~0); 34547#L544-41 is_master_triggered_~__retres1~0#1 := 0; 34548#L555-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 35600#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 34954#L1379-39 assume !(0 != activate_threads_~tmp~1#1); 34955#L1379-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 35808#L563-39 assume !(1 == ~t1_pc~0); 34692#L563-41 is_transmit1_triggered_~__retres1~1#1 := 0; 34693#L574-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 36092#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 36093#L1387-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 36096#L1387-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 35915#L582-39 assume 1 == ~t2_pc~0; 35016#L583-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 35018#L593-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 35343#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 35344#L1395-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 34787#L1395-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 34571#L601-39 assume 1 == ~t3_pc~0; 34572#L602-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 34620#L612-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 35778#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 36103#L1403-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 35812#L1403-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 35489#L620-39 assume !(1 == ~t4_pc~0); 35490#L620-41 is_transmit4_triggered_~__retres1~4#1 := 0; 35679#L631-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 35514#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 35515#L1411-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 35786#L1411-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 36107#L639-39 assume 1 == ~t5_pc~0; 35898#L640-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 35238#L650-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 35239#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 34598#L1419-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 34599#L1419-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 35526#L658-39 assume 1 == ~t6_pc~0; 35509#L659-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 35510#L669-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 35959#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 35701#L1427-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 35676#L1427-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 35677#L677-39 assume !(1 == ~t7_pc~0); 35318#L677-41 is_transmit7_triggered_~__retres1~7#1 := 0; 34776#L688-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 34777#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 34832#L1435-39 assume !(0 != activate_threads_~tmp___6~0#1); 34833#L1435-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 35415#L696-39 assume 1 == ~t8_pc~0; 35381#L697-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 35261#L707-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 35262#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 35551#L1443-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 35519#L1443-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 35395#L715-39 assume 1 == ~t9_pc~0; 34576#L716-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 34577#L726-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 34653#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 34654#L1451-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 35723#L1451-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 35724#L734-39 assume 1 == ~t10_pc~0; 35652#L735-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 35088#L745-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 35418#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 34730#L1459-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 34731#L1459-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 35972#L753-39 assume 1 == ~t11_pc~0; 35360#L754-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 34650#L764-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 35548#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 35386#L1467-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 35387#L1467-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 35486#L1237-3 assume 1 == ~M_E~0;~M_E~0 := 2; 35487#L1237-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 35744#L1242-3 assume !(1 == ~T2_E~0); 35745#L1247-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 35955#L1252-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 35669#L1257-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 35670#L1262-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 35928#L1267-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 35976#L1272-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 36078#L1277-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 34803#L1282-3 assume !(1 == ~T10_E~0); 34804#L1287-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 34713#L1292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 34714#L1297-3 assume 1 == ~E_1~0;~E_1~0 := 2; 35850#L1302-3 assume 1 == ~E_2~0;~E_2~0 := 2; 35851#L1307-3 assume 1 == ~E_3~0;~E_3~0 := 2; 36031#L1312-3 assume 1 == ~E_4~0;~E_4~0 := 2; 36104#L1317-3 assume 1 == ~E_5~0;~E_5~0 := 2; 35764#L1322-3 assume !(1 == ~E_6~0); 35765#L1327-3 assume 1 == ~E_7~0;~E_7~0 := 2; 34769#L1332-3 assume 1 == ~E_8~0;~E_8~0 := 2; 34746#L1337-3 assume 1 == ~E_9~0;~E_9~0 := 2; 34747#L1342-3 assume 1 == ~E_10~0;~E_10~0 := 2; 35456#L1347-3 assume 1 == ~E_11~0;~E_11~0 := 2; 35578#L1352-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 35579#L848-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 34695#L910-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 34901#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 34902#L1697 assume !(0 == start_simulation_~tmp~3#1); 35476#L1697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 35477#L848-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 34820#L910-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 34588#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; 34589#L1652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 35545#L1659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 35546#stop_simulation_returnLabel#1 start_simulation_#t~ret32#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 35839#L1710 assume !(0 != start_simulation_~tmp___0~1#1); 35840#L1678-2 [2022-12-13 17:13:30,574 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 17:13:30,575 INFO L85 PathProgramCache]: Analyzing trace with hash -24556996, now seen corresponding path program 1 times [2022-12-13 17:13:30,575 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 17:13:30,575 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1869115970] [2022-12-13 17:13:30,575 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 17:13:30,575 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 17:13:30,584 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 17:13:30,629 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 17:13:30,629 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 17:13:30,629 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1869115970] [2022-12-13 17:13:30,629 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1869115970] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 17:13:30,629 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 17:13:30,629 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 17:13:30,629 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1018674421] [2022-12-13 17:13:30,629 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 17:13:30,630 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 17:13:30,630 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 17:13:30,630 INFO L85 PathProgramCache]: Analyzing trace with hash 1186767500, now seen corresponding path program 1 times [2022-12-13 17:13:30,630 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 17:13:30,631 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1872232746] [2022-12-13 17:13:30,631 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 17:13:30,631 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 17:13:30,648 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 17:13:30,672 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 17:13:30,672 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 17:13:30,672 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1872232746] [2022-12-13 17:13:30,672 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1872232746] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 17:13:30,672 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 17:13:30,672 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 17:13:30,672 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [68231455] [2022-12-13 17:13:30,672 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 17:13:30,673 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 17:13:30,673 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 17:13:30,673 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 17:13:30,673 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 17:13:30,674 INFO L87 Difference]: Start difference. First operand 1566 states and 2315 transitions. cyclomatic complexity: 750 Second operand has 4 states, 4 states have (on average 34.75) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 17:13:30,812 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 17:13:30,812 INFO L93 Difference]: Finished difference Result 2895 states and 4265 transitions. [2022-12-13 17:13:30,812 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2895 states and 4265 transitions. [2022-12-13 17:13:30,824 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2720 [2022-12-13 17:13:30,836 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2895 states to 2895 states and 4265 transitions. [2022-12-13 17:13:30,836 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2895 [2022-12-13 17:13:30,838 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2895 [2022-12-13 17:13:30,839 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2895 states and 4265 transitions. [2022-12-13 17:13:30,843 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 17:13:30,843 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2895 states and 4265 transitions. [2022-12-13 17:13:30,846 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2895 states and 4265 transitions. [2022-12-13 17:13:30,888 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2895 to 2895. [2022-12-13 17:13:30,893 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2895 states, 2895 states have (on average 1.4732297063903281) internal successors, (4265), 2894 states have internal predecessors, (4265), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 17:13:30,900 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2895 states to 2895 states and 4265 transitions. [2022-12-13 17:13:30,900 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2895 states and 4265 transitions. [2022-12-13 17:13:30,900 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 17:13:30,901 INFO L428 stractBuchiCegarLoop]: Abstraction has 2895 states and 4265 transitions. [2022-12-13 17:13:30,901 INFO L335 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2022-12-13 17:13:30,901 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2895 states and 4265 transitions. [2022-12-13 17:13:30,910 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2720 [2022-12-13 17:13:30,910 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 17:13:30,911 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 17:13:30,913 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 17:13:30,913 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 17:13:30,913 INFO L748 eck$LassoCheckResult]: Stem: 39269#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 39270#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 40079#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 40080#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 39243#L780 assume 1 == ~m_i~0;~m_st~0 := 0; 39244#L780-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 40595#L785-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 40553#L790-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 40554#L795-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 39608#L800-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 39609#L805-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 40047#L810-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 40511#L815-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 39517#L820-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 39518#L825-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 39402#L830-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 39403#L835-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 40426#L1109 assume !(0 == ~M_E~0); 40445#L1109-2 assume !(0 == ~T1_E~0); 39411#L1114-1 assume !(0 == ~T2_E~0); 39412#L1119-1 assume !(0 == ~T3_E~0); 40516#L1124-1 assume !(0 == ~T4_E~0); 39057#L1129-1 assume !(0 == ~T5_E~0); 39058#L1134-1 assume !(0 == ~T6_E~0); 39698#L1139-1 assume !(0 == ~T7_E~0); 40431#L1144-1 assume !(0 == ~T8_E~0); 40283#L1149-1 assume !(0 == ~T9_E~0); 39170#L1154-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 39171#L1159-1 assume !(0 == ~T11_E~0); 40272#L1164-1 assume !(0 == ~E_M~0); 39569#L1169-1 assume !(0 == ~E_1~0); 39466#L1174-1 assume !(0 == ~E_2~0); 39326#L1179-1 assume !(0 == ~E_3~0); 39249#L1184-1 assume !(0 == ~E_4~0); 39250#L1189-1 assume !(0 == ~E_5~0); 39282#L1194-1 assume 0 == ~E_6~0;~E_6~0 := 1; 39371#L1199-1 assume !(0 == ~E_7~0); 40294#L1204-1 assume !(0 == ~E_8~0); 40227#L1209-1 assume !(0 == ~E_9~0); 40228#L1214-1 assume !(0 == ~E_10~0); 40614#L1219-1 assume !(0 == ~E_11~0); 40746#L1224-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 39588#L544 assume 1 == ~m_pc~0; 39589#L545 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 40492#L555 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 39958#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 39211#L1379 assume !(0 != activate_threads_~tmp~1#1); 39212#L1379-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 40033#L563 assume !(1 == ~t1_pc~0); 39821#L563-2 is_transmit1_triggered_~__retres1~1#1 := 0; 39067#L574 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 39068#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 40162#L1387 assume !(0 != activate_threads_~tmp___0~0#1); 39063#L1387-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 39064#L582 assume 1 == ~t2_pc~0; 39797#L583 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 40169#L593 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 39407#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 39408#L1395 assume !(0 != activate_threads_~tmp___1~0#1); 39096#L1395-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 39097#L601 assume !(1 == ~t3_pc~0); 39816#L601-2 is_transmit3_triggered_~__retres1~3#1 := 0; 39815#L612 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 40315#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 40207#L1403 assume !(0 != activate_threads_~tmp___2~0#1); 40208#L1403-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 40146#L620 assume 1 == ~t4_pc~0; 39077#L621 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 39078#L631 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 39110#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 39111#L1411 assume !(0 != activate_threads_~tmp___3~0#1); 40044#L1411-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 40250#L639 assume 1 == ~t5_pc~0; 40116#L640 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 39374#L650 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 39375#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 40064#L1419 assume !(0 != activate_threads_~tmp___4~0#1); 40065#L1419-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 39992#L658 assume !(1 == ~t6_pc~0); 39583#L658-2 is_transmit6_triggered_~__retres1~6#1 := 0; 39584#L669 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 39399#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 39400#L1427 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 40214#L1427-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 39424#L677 assume 1 == ~t7_pc~0; 39425#L678 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 39320#L688 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 40389#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 40545#L1435 assume !(0 != activate_threads_~tmp___6~0#1); 40546#L1435-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 40640#L696 assume !(1 == ~t8_pc~0); 39651#L696-2 is_transmit8_triggered_~__retres1~8#1 := 0; 39652#L707 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 40593#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 40643#L1443 assume !(0 != activate_threads_~tmp___7~0#1); 40708#L1443-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 40103#L715 assume 1 == ~t9_pc~0; 40104#L716 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 39755#L726 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 39464#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 39465#L1451 assume !(0 != activate_threads_~tmp___8~0#1); 40085#L1451-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 40386#L734 assume !(1 == ~t10_pc~0); 40387#L734-2 is_transmit10_triggered_~__retres1~10#1 := 0; 39541#L745 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 39542#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 40317#L1459 assume !(0 != activate_threads_~tmp___9~0#1); 40318#L1459-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 39622#L753 assume 1 == ~t11_pc~0; 39623#L754 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 40220#L764 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 40606#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 39907#L1467 assume !(0 != activate_threads_~tmp___10~0#1); 39908#L1467-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 39967#L1237 assume 1 == ~M_E~0;~M_E~0 := 2; 39968#L1237-2 assume !(1 == ~T1_E~0); 40688#L1242-1 assume !(1 == ~T2_E~0); 40730#L1247-1 assume !(1 == ~T3_E~0); 40543#L1252-1 assume !(1 == ~T4_E~0); 39484#L1257-1 assume !(1 == ~T5_E~0); 39485#L1262-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 40411#L1267-1 assume !(1 == ~T7_E~0); 40534#L1272-1 assume !(1 == ~T8_E~0); 39810#L1277-1 assume !(1 == ~T9_E~0); 39811#L1282-1 assume !(1 == ~T10_E~0); 40326#L1287-1 assume !(1 == ~T11_E~0); 40295#L1292-1 assume !(1 == ~E_M~0); 40212#L1297-1 assume !(1 == ~E_1~0); 40213#L1302-1 assume 1 == ~E_2~0;~E_2~0 := 2; 40856#L1307-1 assume !(1 == ~E_3~0); 40855#L1312-1 assume !(1 == ~E_4~0); 40854#L1317-1 assume !(1 == ~E_5~0); 40853#L1322-1 assume !(1 == ~E_6~0); 40852#L1327-1 assume !(1 == ~E_7~0); 40851#L1332-1 assume !(1 == ~E_8~0); 40850#L1337-1 assume !(1 == ~E_9~0); 40088#L1342-1 assume 1 == ~E_10~0;~E_10~0 := 2; 40089#L1347-1 assume !(1 == ~E_11~0); 40519#L1352-1 assume { :end_inline_reset_delta_events } true; 40385#L1678-2 [2022-12-13 17:13:30,913 INFO L750 eck$LassoCheckResult]: Loop: 40385#L1678-2 assume !false; 40784#L1679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 40322#L1084 assume !false; 40323#L921 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 40632#L848 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 39187#L910 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 40722#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 39107#L925 assume !(0 != eval_~tmp~0#1); 39109#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 39606#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 39607#L1109-3 assume 0 == ~M_E~0;~M_E~0 := 1; 40770#L1109-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 41022#L1114-3 assume !(0 == ~T2_E~0); 41021#L1119-3 assume !(0 == ~T3_E~0); 41020#L1124-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 41019#L1129-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 41018#L1134-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 41017#L1139-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 41016#L1144-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 41015#L1149-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 41014#L1154-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 41013#L1159-3 assume !(0 == ~T11_E~0); 41012#L1164-3 assume 0 == ~E_M~0;~E_M~0 := 1; 41011#L1169-3 assume 0 == ~E_1~0;~E_1~0 := 1; 41010#L1174-3 assume 0 == ~E_2~0;~E_2~0 := 1; 41009#L1179-3 assume 0 == ~E_3~0;~E_3~0 := 1; 41008#L1184-3 assume 0 == ~E_4~0;~E_4~0 := 1; 41007#L1189-3 assume 0 == ~E_5~0;~E_5~0 := 1; 41006#L1194-3 assume 0 == ~E_6~0;~E_6~0 := 1; 41005#L1199-3 assume !(0 == ~E_7~0); 41004#L1204-3 assume 0 == ~E_8~0;~E_8~0 := 1; 41003#L1209-3 assume 0 == ~E_9~0;~E_9~0 := 1; 41002#L1214-3 assume 0 == ~E_10~0;~E_10~0 := 1; 41001#L1219-3 assume 0 == ~E_11~0;~E_11~0 := 1; 41000#L1224-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 40999#L544-39 assume 1 == ~m_pc~0; 40997#L545-13 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 40996#L555-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 40995#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 40994#L1379-39 assume !(0 != activate_threads_~tmp~1#1); 40993#L1379-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 40992#L563-39 assume 1 == ~t1_pc~0; 40990#L564-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 40989#L574-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 40988#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 40987#L1387-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 40986#L1387-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 40985#L582-39 assume !(1 == ~t2_pc~0); 40983#L582-41 is_transmit2_triggered_~__retres1~2#1 := 0; 40982#L593-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 40981#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 40980#L1395-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 40979#L1395-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 40978#L601-39 assume 1 == ~t3_pc~0; 40976#L602-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 40975#L612-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 40974#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 40973#L1403-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 40972#L1403-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 40971#L620-39 assume 1 == ~t4_pc~0; 40197#L621-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 40198#L631-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 40014#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 40015#L1411-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 40324#L1411-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 40762#L639-39 assume !(1 == ~t5_pc~0); 40464#L639-41 is_transmit5_triggered_~__retres1~5#1 := 0; 39725#L650-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 39726#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 39069#L1419-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 39070#L1419-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 40028#L658-39 assume 1 == ~t6_pc~0; 40009#L659-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 40010#L669-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 40540#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 40225#L1427-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 40194#L1427-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 40195#L677-39 assume !(1 == ~t7_pc~0); 39808#L677-41 is_transmit7_triggered_~__retres1~7#1 := 0; 39247#L688-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 39248#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 39303#L1435-39 assume !(0 != activate_threads_~tmp___6~0#1); 39304#L1435-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 39906#L696-39 assume !(1 == ~t8_pc~0); 39872#L696-41 is_transmit8_triggered_~__retres1~8#1 := 0; 39748#L707-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 39749#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 40056#L1443-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 40020#L1443-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 39886#L715-39 assume 1 == ~t9_pc~0; 39047#L716-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 39048#L726-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 39124#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 39125#L1451-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 40253#L1451-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 40254#L734-39 assume 1 == ~t10_pc~0; 40167#L735-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 39568#L745-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 39911#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 39201#L1459-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 39202#L1459-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 40556#L753-39 assume !(1 == ~t11_pc~0); 39120#L753-41 is_transmit11_triggered_~__retres1~11#1 := 0; 39121#L764-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 40053#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 39877#L1467-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 39878#L1467-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 39984#L1237-3 assume 1 == ~M_E~0;~M_E~0 := 2; 39985#L1237-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 40274#L1242-3 assume !(1 == ~T2_E~0); 40275#L1247-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 40533#L1252-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 40187#L1257-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 40188#L1262-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 40497#L1267-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 40560#L1272-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 40703#L1277-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 39274#L1282-3 assume !(1 == ~T10_E~0); 39275#L1287-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 39184#L1292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 39185#L1297-3 assume 1 == ~E_1~0;~E_1~0 := 2; 40403#L1302-3 assume 1 == ~E_2~0;~E_2~0 := 2; 40404#L1307-3 assume 1 == ~E_3~0;~E_3~0 := 2; 40637#L1312-3 assume 1 == ~E_4~0;~E_4~0 := 2; 40756#L1317-3 assume 1 == ~E_5~0;~E_5~0 := 2; 40298#L1322-3 assume !(1 == ~E_6~0); 40299#L1327-3 assume 1 == ~E_7~0;~E_7~0 := 2; 39240#L1332-3 assume 1 == ~E_8~0;~E_8~0 := 2; 39217#L1337-3 assume 1 == ~E_9~0;~E_9~0 := 2; 39218#L1342-3 assume 1 == ~E_10~0;~E_10~0 := 2; 39952#L1347-3 assume 1 == ~E_11~0;~E_11~0 := 2; 40083#L1352-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 40084#L848-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 39441#L910-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 39442#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 40247#L1697 assume !(0 == start_simulation_~tmp~3#1); 40248#L1697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 40693#L848-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 39291#L910-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 39059#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; 39060#L1652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 40050#L1659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 40051#stop_simulation_returnLabel#1 start_simulation_#t~ret32#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 40384#L1710 assume !(0 != start_simulation_~tmp___0~1#1); 40385#L1678-2 [2022-12-13 17:13:30,914 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 17:13:30,914 INFO L85 PathProgramCache]: Analyzing trace with hash -1257740808, now seen corresponding path program 1 times [2022-12-13 17:13:30,914 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 17:13:30,914 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [193602060] [2022-12-13 17:13:30,914 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 17:13:30,914 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 17:13:30,925 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 17:13:30,972 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 17:13:30,972 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 17:13:30,972 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [193602060] [2022-12-13 17:13:30,972 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [193602060] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 17:13:30,972 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 17:13:30,973 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 17:13:30,973 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1890852138] [2022-12-13 17:13:30,973 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 17:13:30,973 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 17:13:30,973 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 17:13:30,974 INFO L85 PathProgramCache]: Analyzing trace with hash 1470623947, now seen corresponding path program 1 times [2022-12-13 17:13:30,974 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 17:13:30,974 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [754189968] [2022-12-13 17:13:30,974 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 17:13:30,974 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 17:13:30,986 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 17:13:31,019 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 17:13:31,019 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 17:13:31,019 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [754189968] [2022-12-13 17:13:31,019 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [754189968] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 17:13:31,019 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 17:13:31,020 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 17:13:31,020 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1715200426] [2022-12-13 17:13:31,020 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 17:13:31,020 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 17:13:31,020 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 17:13:31,021 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 17:13:31,021 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 17:13:31,021 INFO L87 Difference]: Start difference. First operand 2895 states and 4265 transitions. cyclomatic complexity: 1372 Second operand has 4 states, 4 states have (on average 34.75) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 17:13:31,128 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 17:13:31,129 INFO L93 Difference]: Finished difference Result 5541 states and 8142 transitions. [2022-12-13 17:13:31,129 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5541 states and 8142 transitions. [2022-12-13 17:13:31,144 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 5330 [2022-12-13 17:13:31,155 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5541 states to 5541 states and 8142 transitions. [2022-12-13 17:13:31,156 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5541 [2022-12-13 17:13:31,159 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5541 [2022-12-13 17:13:31,159 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5541 states and 8142 transitions. [2022-12-13 17:13:31,163 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 17:13:31,163 INFO L218 hiAutomatonCegarLoop]: Abstraction has 5541 states and 8142 transitions. [2022-12-13 17:13:31,167 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5541 states and 8142 transitions. [2022-12-13 17:13:31,216 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5541 to 5541. [2022-12-13 17:13:31,222 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5541 states, 5541 states have (on average 1.4694098538170006) internal successors, (8142), 5540 states have internal predecessors, (8142), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 17:13:31,230 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5541 states to 5541 states and 8142 transitions. [2022-12-13 17:13:31,230 INFO L240 hiAutomatonCegarLoop]: Abstraction has 5541 states and 8142 transitions. [2022-12-13 17:13:31,231 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 17:13:31,231 INFO L428 stractBuchiCegarLoop]: Abstraction has 5541 states and 8142 transitions. [2022-12-13 17:13:31,231 INFO L335 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2022-12-13 17:13:31,231 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5541 states and 8142 transitions. [2022-12-13 17:13:31,244 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 5330 [2022-12-13 17:13:31,244 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 17:13:31,244 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 17:13:31,245 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 17:13:31,246 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 17:13:31,246 INFO L748 eck$LassoCheckResult]: Stem: 47715#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 47716#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 48499#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 48500#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 47689#L780 assume 1 == ~m_i~0;~m_st~0 := 0; 47690#L780-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 48957#L785-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 48919#L790-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 48920#L795-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 48046#L800-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 48047#L805-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 48467#L810-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 48885#L815-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 47953#L820-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 47954#L825-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 47844#L830-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 47845#L835-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 48809#L1109 assume !(0 == ~M_E~0); 48825#L1109-2 assume !(0 == ~T1_E~0); 47853#L1114-1 assume !(0 == ~T2_E~0); 47854#L1119-1 assume !(0 == ~T3_E~0); 48888#L1124-1 assume !(0 == ~T4_E~0); 47503#L1129-1 assume !(0 == ~T5_E~0); 47504#L1134-1 assume !(0 == ~T6_E~0); 48133#L1139-1 assume !(0 == ~T7_E~0); 48816#L1144-1 assume !(0 == ~T8_E~0); 48685#L1149-1 assume !(0 == ~T9_E~0); 47614#L1154-1 assume !(0 == ~T10_E~0); 47615#L1159-1 assume !(0 == ~T11_E~0); 48674#L1164-1 assume !(0 == ~E_M~0); 48007#L1169-1 assume !(0 == ~E_1~0); 47905#L1174-1 assume !(0 == ~E_2~0); 47769#L1179-1 assume !(0 == ~E_3~0); 47695#L1184-1 assume !(0 == ~E_4~0); 47696#L1189-1 assume !(0 == ~E_5~0); 47729#L1194-1 assume 0 == ~E_6~0;~E_6~0 := 1; 47812#L1199-1 assume !(0 == ~E_7~0); 48694#L1204-1 assume !(0 == ~E_8~0); 48633#L1209-1 assume !(0 == ~E_9~0); 48634#L1214-1 assume !(0 == ~E_10~0); 48971#L1219-1 assume !(0 == ~E_11~0); 49078#L1224-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 48025#L544 assume 1 == ~m_pc~0; 48026#L545 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 48867#L555 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 48383#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 47657#L1379 assume !(0 != activate_threads_~tmp~1#1); 47658#L1379-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 48454#L563 assume !(1 == ~t1_pc~0); 48251#L563-2 is_transmit1_triggered_~__retres1~1#1 := 0; 47513#L574 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 47514#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 48579#L1387 assume !(0 != activate_threads_~tmp___0~0#1); 47509#L1387-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 47510#L582 assume 1 == ~t2_pc~0; 48228#L583 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 48584#L593 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 47849#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 47850#L1395 assume !(0 != activate_threads_~tmp___1~0#1); 47542#L1395-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 47543#L601 assume !(1 == ~t3_pc~0); 48246#L601-2 is_transmit3_triggered_~__retres1~3#1 := 0; 48245#L612 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 48716#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 48617#L1403 assume !(0 != activate_threads_~tmp___2~0#1); 48618#L1403-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 48564#L620 assume 1 == ~t4_pc~0; 47523#L621 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 47524#L631 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 47556#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 47557#L1411 assume !(0 != activate_threads_~tmp___3~0#1); 48464#L1411-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 48651#L639 assume 1 == ~t5_pc~0; 48536#L640 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 47817#L650 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 47818#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 48485#L1419 assume !(0 != activate_threads_~tmp___4~0#1); 48486#L1419-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 48417#L658 assume !(1 == ~t6_pc~0); 48022#L658-2 is_transmit6_triggered_~__retres1~6#1 := 0; 48023#L669 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 47841#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 47842#L1427 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 48621#L1427-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 47864#L677 assume 1 == ~t7_pc~0; 47865#L678 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 47762#L688 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 48780#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 48913#L1435 assume !(0 != activate_threads_~tmp___6~0#1); 48914#L1435-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 48994#L696 assume !(1 == ~t8_pc~0); 48086#L696-2 is_transmit8_triggered_~__retres1~8#1 := 0; 48087#L707 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 48955#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 48997#L1443 assume !(0 != activate_threads_~tmp___7~0#1); 49047#L1443-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 48523#L715 assume 1 == ~t9_pc~0; 48524#L716 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 48186#L726 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 47903#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 47904#L1451 assume !(0 != activate_threads_~tmp___8~0#1); 48506#L1451-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 48775#L734 assume !(1 == ~t10_pc~0); 48776#L734-2 is_transmit10_triggered_~__retres1~10#1 := 0; 47979#L745 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 47980#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 48718#L1459 assume !(0 != activate_threads_~tmp___9~0#1); 48719#L1459-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 48060#L753 assume 1 == ~t11_pc~0; 48061#L754 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 48627#L764 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 48965#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 48332#L1467 assume !(0 != activate_threads_~tmp___10~0#1); 48333#L1467-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 48390#L1237 assume 1 == ~M_E~0;~M_E~0 := 2; 48391#L1237-2 assume !(1 == ~T1_E~0); 49026#L1242-1 assume !(1 == ~T2_E~0); 48154#L1247-1 assume !(1 == ~T3_E~0); 48155#L1252-1 assume !(1 == ~T4_E~0); 49332#L1257-1 assume !(1 == ~T5_E~0); 49329#L1262-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 49327#L1267-1 assume !(1 == ~T7_E~0); 49326#L1272-1 assume !(1 == ~T8_E~0); 48240#L1277-1 assume !(1 == ~T9_E~0); 48241#L1282-1 assume !(1 == ~T10_E~0); 49251#L1287-1 assume !(1 == ~T11_E~0); 49250#L1292-1 assume !(1 == ~E_M~0); 49249#L1297-1 assume !(1 == ~E_1~0); 49248#L1302-1 assume 1 == ~E_2~0;~E_2~0 := 2; 49246#L1307-1 assume !(1 == ~E_3~0); 49244#L1312-1 assume !(1 == ~E_4~0); 49218#L1317-1 assume !(1 == ~E_5~0); 49192#L1322-1 assume !(1 == ~E_6~0); 49190#L1327-1 assume !(1 == ~E_7~0); 49187#L1332-1 assume !(1 == ~E_8~0); 49173#L1337-1 assume !(1 == ~E_9~0); 49154#L1342-1 assume 1 == ~E_10~0;~E_10~0 := 2; 49140#L1347-1 assume !(1 == ~E_11~0); 49131#L1352-1 assume { :end_inline_reset_delta_events } true; 49123#L1678-2 [2022-12-13 17:13:31,246 INFO L750 eck$LassoCheckResult]: Loop: 49123#L1678-2 assume !false; 49116#L1679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 49113#L1084 assume !false; 49112#L921 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 49102#L848 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 49099#L910 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 49098#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 49096#L925 assume !(0 != eval_~tmp~0#1); 49095#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 49094#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 49092#L1109-3 assume 0 == ~M_E~0;~M_E~0 := 1; 49093#L1109-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 50623#L1114-3 assume !(0 == ~T2_E~0); 50621#L1119-3 assume !(0 == ~T3_E~0); 50619#L1124-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 50617#L1129-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 50615#L1134-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 50613#L1139-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 50610#L1144-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 50608#L1149-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 50606#L1154-3 assume !(0 == ~T10_E~0); 50603#L1159-3 assume !(0 == ~T11_E~0); 50601#L1164-3 assume 0 == ~E_M~0;~E_M~0 := 1; 50598#L1169-3 assume 0 == ~E_1~0;~E_1~0 := 1; 50595#L1174-3 assume 0 == ~E_2~0;~E_2~0 := 1; 50593#L1179-3 assume 0 == ~E_3~0;~E_3~0 := 1; 50591#L1184-3 assume 0 == ~E_4~0;~E_4~0 := 1; 50588#L1189-3 assume 0 == ~E_5~0;~E_5~0 := 1; 50586#L1194-3 assume 0 == ~E_6~0;~E_6~0 := 1; 50583#L1199-3 assume !(0 == ~E_7~0); 50580#L1204-3 assume 0 == ~E_8~0;~E_8~0 := 1; 50578#L1209-3 assume 0 == ~E_9~0;~E_9~0 := 1; 50574#L1214-3 assume 0 == ~E_10~0;~E_10~0 := 1; 50569#L1219-3 assume 0 == ~E_11~0;~E_11~0 := 1; 50565#L1224-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 50561#L544-39 assume 1 == ~m_pc~0; 50556#L545-13 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 50553#L555-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 50551#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 50541#L1379-39 assume !(0 != activate_threads_~tmp~1#1); 50537#L1379-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 50531#L563-39 assume 1 == ~t1_pc~0; 50524#L564-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 50519#L574-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 50512#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 50507#L1387-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 50502#L1387-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 50496#L582-39 assume !(1 == ~t2_pc~0); 50489#L582-41 is_transmit2_triggered_~__retres1~2#1 := 0; 50483#L593-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 50474#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 50468#L1395-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 50462#L1395-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 50455#L601-39 assume !(1 == ~t3_pc~0); 50448#L601-41 is_transmit3_triggered_~__retres1~3#1 := 0; 50441#L612-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 50432#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 50426#L1403-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 50420#L1403-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 50413#L620-39 assume !(1 == ~t4_pc~0); 50405#L620-41 is_transmit4_triggered_~__retres1~4#1 := 0; 50400#L631-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 50391#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 50385#L1411-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 50379#L1411-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 50372#L639-39 assume 1 == ~t5_pc~0; 50364#L640-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 50357#L650-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 50349#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 50343#L1419-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 50337#L1419-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 50330#L658-39 assume !(1 == ~t6_pc~0); 50323#L658-41 is_transmit6_triggered_~__retres1~6#1 := 0; 50321#L669-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 50312#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 50306#L1427-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 50300#L1427-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 50294#L677-39 assume 1 == ~t7_pc~0; 50285#L678-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 50280#L688-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 50272#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 50265#L1435-39 assume !(0 != activate_threads_~tmp___6~0#1); 50259#L1435-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 50254#L696-39 assume 1 == ~t8_pc~0; 50246#L697-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 50240#L707-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 50232#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 50225#L1443-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 50219#L1443-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 50213#L715-39 assume 1 == ~t9_pc~0; 50205#L716-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 50199#L726-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 50191#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 50189#L1451-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 50186#L1451-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 50183#L734-39 assume 1 == ~t10_pc~0; 50178#L735-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 50176#L745-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 50172#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 50169#L1459-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 50166#L1459-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 50163#L753-39 assume !(1 == ~t11_pc~0); 50158#L753-41 is_transmit11_triggered_~__retres1~11#1 := 0; 50155#L764-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 50152#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 50149#L1467-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 50147#L1467-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 50144#L1237-3 assume 1 == ~M_E~0;~M_E~0 := 2; 48409#L1237-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 50138#L1242-3 assume !(1 == ~T2_E~0); 50137#L1247-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 50136#L1252-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 50134#L1257-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 50131#L1262-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 50041#L1267-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 50034#L1272-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 50027#L1277-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 50018#L1282-3 assume !(1 == ~T10_E~0); 50011#L1287-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 50003#L1292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 49997#L1297-3 assume 1 == ~E_1~0;~E_1~0 := 2; 49992#L1302-3 assume 1 == ~E_2~0;~E_2~0 := 2; 49987#L1307-3 assume 1 == ~E_3~0;~E_3~0 := 2; 49408#L1312-3 assume 1 == ~E_4~0;~E_4~0 := 2; 49382#L1317-3 assume 1 == ~E_5~0;~E_5~0 := 2; 49355#L1322-3 assume !(1 == ~E_6~0); 49324#L1327-3 assume 1 == ~E_7~0;~E_7~0 := 2; 49323#L1332-3 assume 1 == ~E_8~0;~E_8~0 := 2; 49322#L1337-3 assume 1 == ~E_9~0;~E_9~0 := 2; 49321#L1342-3 assume 1 == ~E_10~0;~E_10~0 := 2; 49320#L1347-3 assume 1 == ~E_11~0;~E_11~0 := 2; 49319#L1352-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 49282#L848-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 49277#L910-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 49275#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 49273#L1697 assume !(0 == start_simulation_~tmp~3#1); 48855#L1697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 49212#L848-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 49202#L910-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 49185#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; 49171#L1652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 49153#L1659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 49139#stop_simulation_returnLabel#1 start_simulation_#t~ret32#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 49130#L1710 assume !(0 != start_simulation_~tmp___0~1#1); 49123#L1678-2 [2022-12-13 17:13:31,246 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 17:13:31,247 INFO L85 PathProgramCache]: Analyzing trace with hash -786384458, now seen corresponding path program 1 times [2022-12-13 17:13:31,247 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 17:13:31,247 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1821306302] [2022-12-13 17:13:31,247 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 17:13:31,247 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 17:13:31,257 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 17:13:31,290 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 17:13:31,290 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 17:13:31,290 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1821306302] [2022-12-13 17:13:31,290 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1821306302] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 17:13:31,290 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 17:13:31,290 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 17:13:31,290 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1057931145] [2022-12-13 17:13:31,291 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 17:13:31,291 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 17:13:31,291 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 17:13:31,291 INFO L85 PathProgramCache]: Analyzing trace with hash -57383351, now seen corresponding path program 1 times [2022-12-13 17:13:31,291 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 17:13:31,291 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1221001096] [2022-12-13 17:13:31,292 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 17:13:31,292 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 17:13:31,299 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 17:13:31,321 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 17:13:31,321 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 17:13:31,321 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1221001096] [2022-12-13 17:13:31,322 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1221001096] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 17:13:31,322 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 17:13:31,322 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 17:13:31,322 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [306826581] [2022-12-13 17:13:31,322 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 17:13:31,322 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 17:13:31,323 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 17:13:31,323 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 17:13:31,323 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 17:13:31,324 INFO L87 Difference]: Start difference. First operand 5541 states and 8142 transitions. cyclomatic complexity: 2605 Second operand has 4 states, 4 states have (on average 34.75) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 17:13:31,486 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 17:13:31,486 INFO L93 Difference]: Finished difference Result 10453 states and 15329 transitions. [2022-12-13 17:13:31,486 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 10453 states and 15329 transitions. [2022-12-13 17:13:31,525 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 10206 [2022-12-13 17:13:31,550 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 10453 states to 10453 states and 15329 transitions. [2022-12-13 17:13:31,551 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10453 [2022-12-13 17:13:31,557 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10453 [2022-12-13 17:13:31,557 INFO L73 IsDeterministic]: Start isDeterministic. Operand 10453 states and 15329 transitions. [2022-12-13 17:13:31,567 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 17:13:31,567 INFO L218 hiAutomatonCegarLoop]: Abstraction has 10453 states and 15329 transitions. [2022-12-13 17:13:31,575 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10453 states and 15329 transitions. [2022-12-13 17:13:31,644 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10453 to 10449. [2022-12-13 17:13:31,654 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 10449 states, 10449 states have (on average 1.4666475260790506) internal successors, (15325), 10448 states have internal predecessors, (15325), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 17:13:31,668 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10449 states to 10449 states and 15325 transitions. [2022-12-13 17:13:31,668 INFO L240 hiAutomatonCegarLoop]: Abstraction has 10449 states and 15325 transitions. [2022-12-13 17:13:31,669 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 17:13:31,669 INFO L428 stractBuchiCegarLoop]: Abstraction has 10449 states and 15325 transitions. [2022-12-13 17:13:31,669 INFO L335 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2022-12-13 17:13:31,669 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 10449 states and 15325 transitions. [2022-12-13 17:13:31,691 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 10206 [2022-12-13 17:13:31,691 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 17:13:31,691 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 17:13:31,692 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 17:13:31,692 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 17:13:31,693 INFO L748 eck$LassoCheckResult]: Stem: 63719#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 63720#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 64501#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 64502#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 63693#L780 assume 1 == ~m_i~0;~m_st~0 := 0; 63694#L780-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 64954#L785-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 64917#L790-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 64918#L795-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 64049#L800-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 64050#L805-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 64470#L810-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 64882#L815-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 63957#L820-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 63958#L825-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 63847#L830-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 63848#L835-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 64808#L1109 assume !(0 == ~M_E~0); 64826#L1109-2 assume !(0 == ~T1_E~0); 63856#L1114-1 assume !(0 == ~T2_E~0); 63857#L1119-1 assume !(0 == ~T3_E~0); 64885#L1124-1 assume !(0 == ~T4_E~0); 63507#L1129-1 assume !(0 == ~T5_E~0); 63508#L1134-1 assume !(0 == ~T6_E~0); 64138#L1139-1 assume !(0 == ~T7_E~0); 64815#L1144-1 assume !(0 == ~T8_E~0); 64684#L1149-1 assume !(0 == ~T9_E~0); 63618#L1154-1 assume !(0 == ~T10_E~0); 63619#L1159-1 assume !(0 == ~T11_E~0); 64673#L1164-1 assume !(0 == ~E_M~0); 64011#L1169-1 assume !(0 == ~E_1~0); 63909#L1174-1 assume !(0 == ~E_2~0); 63772#L1179-1 assume !(0 == ~E_3~0); 63699#L1184-1 assume !(0 == ~E_4~0); 63700#L1189-1 assume !(0 == ~E_5~0); 63732#L1194-1 assume !(0 == ~E_6~0); 63815#L1199-1 assume !(0 == ~E_7~0); 64693#L1204-1 assume !(0 == ~E_8~0); 64632#L1209-1 assume !(0 == ~E_9~0); 64633#L1214-1 assume !(0 == ~E_10~0); 64970#L1219-1 assume !(0 == ~E_11~0); 65070#L1224-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 64028#L544 assume 1 == ~m_pc~0; 64029#L545 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 64866#L555 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 64388#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 63661#L1379 assume !(0 != activate_threads_~tmp~1#1); 63662#L1379-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 64457#L563 assume !(1 == ~t1_pc~0); 64256#L563-2 is_transmit1_triggered_~__retres1~1#1 := 0; 63517#L574 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 63518#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 64579#L1387 assume !(0 != activate_threads_~tmp___0~0#1); 63513#L1387-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 63514#L582 assume 1 == ~t2_pc~0; 64234#L583 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 64584#L593 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 63852#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 63853#L1395 assume !(0 != activate_threads_~tmp___1~0#1); 63546#L1395-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 63547#L601 assume !(1 == ~t3_pc~0); 64251#L601-2 is_transmit3_triggered_~__retres1~3#1 := 0; 64250#L612 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 64713#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 64617#L1403 assume !(0 != activate_threads_~tmp___2~0#1); 64618#L1403-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 64565#L620 assume 1 == ~t4_pc~0; 63527#L621 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 63528#L631 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 63560#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 63561#L1411 assume !(0 != activate_threads_~tmp___3~0#1); 64467#L1411-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 64650#L639 assume 1 == ~t5_pc~0; 64539#L640 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 63820#L650 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 63821#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 64487#L1419 assume !(0 != activate_threads_~tmp___4~0#1); 64488#L1419-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 64422#L658 assume !(1 == ~t6_pc~0); 64025#L658-2 is_transmit6_triggered_~__retres1~6#1 := 0; 64026#L669 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 63844#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 63845#L1427 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 64621#L1427-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 63867#L677 assume 1 == ~t7_pc~0; 63868#L678 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 63765#L688 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 64779#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 64910#L1435 assume !(0 != activate_threads_~tmp___6~0#1); 64911#L1435-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 64991#L696 assume !(1 == ~t8_pc~0); 64089#L696-2 is_transmit8_triggered_~__retres1~8#1 := 0; 64090#L707 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 64952#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 64994#L1443 assume !(0 != activate_threads_~tmp___7~0#1); 65043#L1443-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 64526#L715 assume 1 == ~t9_pc~0; 64527#L716 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 64192#L726 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 63907#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 63908#L1451 assume !(0 != activate_threads_~tmp___8~0#1); 64508#L1451-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 64774#L734 assume !(1 == ~t10_pc~0); 64775#L734-2 is_transmit10_triggered_~__retres1~10#1 := 0; 63983#L745 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 63984#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 64715#L1459 assume !(0 != activate_threads_~tmp___9~0#1); 64716#L1459-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 64063#L753 assume 1 == ~t11_pc~0; 64064#L754 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 64626#L764 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 64963#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 64338#L1467 assume !(0 != activate_threads_~tmp___10~0#1); 64339#L1467-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 64395#L1237 assume 1 == ~M_E~0;~M_E~0 := 2; 64396#L1237-2 assume !(1 == ~T1_E~0); 65025#L1242-1 assume !(1 == ~T2_E~0); 65058#L1247-1 assume !(1 == ~T3_E~0); 65501#L1252-1 assume !(1 == ~T4_E~0); 65499#L1257-1 assume !(1 == ~T5_E~0); 65497#L1262-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 65495#L1267-1 assume !(1 == ~T7_E~0); 65493#L1272-1 assume !(1 == ~T8_E~0); 65491#L1277-1 assume !(1 == ~T9_E~0); 65488#L1282-1 assume !(1 == ~T10_E~0); 65374#L1287-1 assume !(1 == ~T11_E~0); 65284#L1292-1 assume !(1 == ~E_M~0); 65238#L1297-1 assume !(1 == ~E_1~0); 65236#L1302-1 assume 1 == ~E_2~0;~E_2~0 := 2; 65234#L1307-1 assume !(1 == ~E_3~0); 65232#L1312-1 assume !(1 == ~E_4~0); 65230#L1317-1 assume !(1 == ~E_5~0); 65229#L1322-1 assume !(1 == ~E_6~0); 65226#L1327-1 assume !(1 == ~E_7~0); 65225#L1332-1 assume !(1 == ~E_8~0); 65192#L1337-1 assume !(1 == ~E_9~0); 65153#L1342-1 assume 1 == ~E_10~0;~E_10~0 := 2; 65132#L1347-1 assume !(1 == ~E_11~0); 65123#L1352-1 assume { :end_inline_reset_delta_events } true; 65115#L1678-2 [2022-12-13 17:13:31,693 INFO L750 eck$LassoCheckResult]: Loop: 65115#L1678-2 assume !false; 65108#L1679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 65105#L1084 assume !false; 65104#L921 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 65094#L848 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 65091#L910 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 65090#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 65088#L925 assume !(0 != eval_~tmp~0#1); 65087#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 65086#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 65085#L1109-3 assume 0 == ~M_E~0;~M_E~0 := 1; 63530#L1109-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 63531#L1114-3 assume !(0 == ~T2_E~0); 64622#L1119-3 assume !(0 == ~T3_E~0); 64623#L1124-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 64647#L1129-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 64648#L1134-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 64821#L1139-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 64877#L1144-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 64038#L1149-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 64039#L1154-3 assume !(0 == ~T10_E~0); 64298#L1159-3 assume !(0 == ~T11_E~0); 64299#L1164-3 assume 0 == ~E_M~0;~E_M~0 := 1; 64561#L1169-3 assume 0 == ~E_1~0;~E_1~0 := 1; 64562#L1174-3 assume 0 == ~E_2~0;~E_2~0 := 1; 64610#L1179-3 assume 0 == ~E_3~0;~E_3~0 := 1; 64611#L1184-3 assume 0 == ~E_4~0;~E_4~0 := 1; 64756#L1189-3 assume 0 == ~E_5~0;~E_5~0 := 1; 64451#L1194-3 assume !(0 == ~E_6~0); 63794#L1199-3 assume !(0 == ~E_7~0); 63795#L1204-3 assume 0 == ~E_8~0;~E_8~0 := 1; 64018#L1209-3 assume 0 == ~E_9~0;~E_9~0 := 1; 63480#L1214-3 assume 0 == ~E_10~0;~E_10~0 := 1; 63481#L1219-3 assume 0 == ~E_11~0;~E_11~0 := 1; 64202#L1224-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 64203#L544-39 assume 1 == ~m_pc~0; 64553#L545-13 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 63469#L555-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 64529#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 63875#L1379-39 assume !(0 != activate_threads_~tmp~1#1); 63876#L1379-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 64743#L563-39 assume 1 == ~t1_pc~0; 64749#L564-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 63614#L574-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 65055#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 65056#L1387-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 65061#L1387-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 64857#L582-39 assume 1 == ~t2_pc~0; 63938#L583-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 63940#L593-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 64268#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 64269#L1395-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 63708#L1395-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 63492#L601-39 assume 1 == ~t3_pc~0; 63493#L602-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 63541#L612-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 64711#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 65073#L1403-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 64747#L1403-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 64417#L620-39 assume !(1 == ~t4_pc~0); 64418#L620-41 is_transmit4_triggered_~__retres1~4#1 := 0; 64609#L631-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 64442#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 64443#L1411-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 64719#L1411-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 65082#L639-39 assume 1 == ~t5_pc~0; 64839#L640-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 64162#L650-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 64163#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 63519#L1419-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 63520#L1419-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 64454#L658-39 assume 1 == ~t6_pc~0; 64437#L659-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 64438#L669-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 64905#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 64631#L1427-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 64606#L1427-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 64607#L677-39 assume !(1 == ~t7_pc~0); 64243#L677-41 is_transmit7_triggered_~__retres1~7#1 := 0; 63697#L688-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 63698#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 63753#L1435-39 assume !(0 != activate_threads_~tmp___6~0#1); 63754#L1435-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 64341#L696-39 assume 1 == ~t8_pc~0; 64306#L697-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 64185#L707-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 64186#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 64479#L1443-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 64447#L1443-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 64321#L715-39 assume 1 == ~t9_pc~0; 63497#L716-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 63498#L726-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 63574#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 63575#L1451-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 64654#L1451-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 64655#L734-39 assume 1 == ~t10_pc~0; 64582#L735-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 64010#L745-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 64344#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 63651#L1459-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 63652#L1459-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 64922#L753-39 assume !(1 == ~t11_pc~0); 63570#L753-41 is_transmit11_triggered_~__retres1~11#1 := 0; 63571#L764-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 64867#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 66025#L1467-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 65842#L1467-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 65839#L1237-3 assume 1 == ~M_E~0;~M_E~0 := 2; 64414#L1237-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 65836#L1242-3 assume !(1 == ~T2_E~0); 64677#L1247-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 65833#L1252-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 65831#L1257-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 65663#L1262-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 65660#L1267-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 65658#L1272-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 65656#L1277-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 65553#L1282-3 assume !(1 == ~T10_E~0); 65551#L1287-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 65549#L1292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 65547#L1297-3 assume 1 == ~E_1~0;~E_1~0 := 2; 65545#L1302-3 assume 1 == ~E_2~0;~E_2~0 := 2; 65543#L1307-3 assume 1 == ~E_3~0;~E_3~0 := 2; 65541#L1312-3 assume 1 == ~E_4~0;~E_4~0 := 2; 65540#L1317-3 assume 1 == ~E_5~0;~E_5~0 := 2; 65401#L1322-3 assume !(1 == ~E_6~0); 65398#L1327-3 assume 1 == ~E_7~0;~E_7~0 := 2; 65396#L1332-3 assume 1 == ~E_8~0;~E_8~0 := 2; 65394#L1337-3 assume 1 == ~E_9~0;~E_9~0 := 2; 65392#L1342-3 assume 1 == ~E_10~0;~E_10~0 := 2; 65390#L1347-3 assume 1 == ~E_11~0;~E_11~0 := 2; 65389#L1352-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 65320#L848-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 65315#L910-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 65313#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 65311#L1697 assume !(0 == start_simulation_~tmp~3#1); 64854#L1697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 65265#L848-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 65255#L910-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 65253#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; 65189#L1652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 65152#L1659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 65131#stop_simulation_returnLabel#1 start_simulation_#t~ret32#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 65122#L1710 assume !(0 != start_simulation_~tmp___0~1#1); 65115#L1678-2 [2022-12-13 17:13:31,693 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 17:13:31,693 INFO L85 PathProgramCache]: Analyzing trace with hash 602909556, now seen corresponding path program 1 times [2022-12-13 17:13:31,693 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 17:13:31,693 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1785971136] [2022-12-13 17:13:31,693 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 17:13:31,693 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 17:13:31,701 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 17:13:31,730 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 17:13:31,730 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 17:13:31,730 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1785971136] [2022-12-13 17:13:31,730 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1785971136] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 17:13:31,730 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 17:13:31,730 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-12-13 17:13:31,730 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1240085869] [2022-12-13 17:13:31,730 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 17:13:31,731 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 17:13:31,731 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 17:13:31,731 INFO L85 PathProgramCache]: Analyzing trace with hash -1657228155, now seen corresponding path program 1 times [2022-12-13 17:13:31,731 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 17:13:31,731 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [284453703] [2022-12-13 17:13:31,731 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 17:13:31,732 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 17:13:31,743 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 17:13:31,762 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 17:13:31,762 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 17:13:31,762 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [284453703] [2022-12-13 17:13:31,762 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [284453703] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 17:13:31,763 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 17:13:31,763 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 17:13:31,763 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1591206009] [2022-12-13 17:13:31,763 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 17:13:31,763 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 17:13:31,763 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 17:13:31,764 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 17:13:31,764 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 17:13:31,764 INFO L87 Difference]: Start difference. First operand 10449 states and 15325 transitions. cyclomatic complexity: 4884 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 2 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 17:13:31,898 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 17:13:31,898 INFO L93 Difference]: Finished difference Result 20529 states and 29894 transitions. [2022-12-13 17:13:31,898 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 20529 states and 29894 transitions. [2022-12-13 17:13:31,957 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 20279 [2022-12-13 17:13:32,002 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 20529 states to 20529 states and 29894 transitions. [2022-12-13 17:13:32,003 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 20529 [2022-12-13 17:13:32,014 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 20529 [2022-12-13 17:13:32,014 INFO L73 IsDeterministic]: Start isDeterministic. Operand 20529 states and 29894 transitions. [2022-12-13 17:13:32,025 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 17:13:32,025 INFO L218 hiAutomatonCegarLoop]: Abstraction has 20529 states and 29894 transitions. [2022-12-13 17:13:32,040 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 20529 states and 29894 transitions. [2022-12-13 17:13:32,236 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 20529 to 19865. [2022-12-13 17:13:32,256 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 19865 states, 19865 states have (on average 1.4577397432670527) internal successors, (28958), 19864 states have internal predecessors, (28958), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 17:13:32,283 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19865 states to 19865 states and 28958 transitions. [2022-12-13 17:13:32,283 INFO L240 hiAutomatonCegarLoop]: Abstraction has 19865 states and 28958 transitions. [2022-12-13 17:13:32,283 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 17:13:32,284 INFO L428 stractBuchiCegarLoop]: Abstraction has 19865 states and 28958 transitions. [2022-12-13 17:13:32,284 INFO L335 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2022-12-13 17:13:32,284 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 19865 states and 28958 transitions. [2022-12-13 17:13:32,339 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 19615 [2022-12-13 17:13:32,339 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 17:13:32,339 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 17:13:32,340 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 17:13:32,340 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 17:13:32,340 INFO L748 eck$LassoCheckResult]: Stem: 94705#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 94706#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 95522#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 95523#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 94678#L780 assume 1 == ~m_i~0;~m_st~0 := 0; 94679#L780-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 96052#L785-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 96004#L790-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 96005#L795-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 95044#L800-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 95045#L805-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 95482#L810-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 95962#L815-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 94949#L820-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 94950#L825-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 94837#L830-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 94838#L835-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 95870#L1109 assume !(0 == ~M_E~0); 95894#L1109-2 assume !(0 == ~T1_E~0); 94846#L1114-1 assume !(0 == ~T2_E~0); 94847#L1119-1 assume !(0 == ~T3_E~0); 95965#L1124-1 assume !(0 == ~T4_E~0); 94492#L1129-1 assume !(0 == ~T5_E~0); 94493#L1134-1 assume !(0 == ~T6_E~0); 95134#L1139-1 assume !(0 == ~T7_E~0); 95879#L1144-1 assume !(0 == ~T8_E~0); 95724#L1149-1 assume !(0 == ~T9_E~0); 94603#L1154-1 assume !(0 == ~T10_E~0); 94604#L1159-1 assume !(0 == ~T11_E~0); 95713#L1164-1 assume !(0 == ~E_M~0); 95005#L1169-1 assume !(0 == ~E_1~0); 94899#L1174-1 assume !(0 == ~E_2~0); 94759#L1179-1 assume !(0 == ~E_3~0); 94684#L1184-1 assume !(0 == ~E_4~0); 94685#L1189-1 assume !(0 == ~E_5~0); 94718#L1194-1 assume !(0 == ~E_6~0); 94805#L1199-1 assume !(0 == ~E_7~0); 95733#L1204-1 assume !(0 == ~E_8~0); 95667#L1209-1 assume !(0 == ~E_9~0); 95668#L1214-1 assume !(0 == ~E_10~0); 96070#L1219-1 assume !(0 == ~E_11~0); 96222#L1224-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 95022#L544 assume !(1 == ~m_pc~0); 95023#L544-2 is_master_triggered_~__retres1~0#1 := 0; 95944#L555 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 95393#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 94645#L1379 assume !(0 != activate_threads_~tmp~1#1); 94646#L1379-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 95465#L563 assume !(1 == ~t1_pc~0); 95254#L563-2 is_transmit1_triggered_~__retres1~1#1 := 0; 94502#L574 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 94503#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 95610#L1387 assume !(0 != activate_threads_~tmp___0~0#1); 94498#L1387-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 94499#L582 assume 1 == ~t2_pc~0; 95231#L583 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 95616#L593 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 94842#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 94843#L1395 assume !(0 != activate_threads_~tmp___1~0#1); 94531#L1395-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 94532#L601 assume !(1 == ~t3_pc~0); 95249#L601-2 is_transmit3_triggered_~__retres1~3#1 := 0; 95248#L612 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 95754#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 95652#L1403 assume !(0 != activate_threads_~tmp___2~0#1); 95653#L1403-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 95595#L620 assume 1 == ~t4_pc~0; 94512#L621 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 94513#L631 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 94545#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 94546#L1411 assume !(0 != activate_threads_~tmp___3~0#1); 95476#L1411-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 95688#L639 assume 1 == ~t5_pc~0; 95565#L640 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 94810#L650 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 94811#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 95501#L1419 assume !(0 != activate_threads_~tmp___4~0#1); 95502#L1419-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 95429#L658 assume !(1 == ~t6_pc~0); 95019#L658-2 is_transmit6_triggered_~__retres1~6#1 := 0; 95020#L669 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 94834#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 94835#L1427 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 95656#L1427-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 94857#L677 assume 1 == ~t7_pc~0; 94858#L678 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 94751#L688 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 95835#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 95995#L1435 assume !(0 != activate_threads_~tmp___6~0#1); 95996#L1435-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 96098#L696 assume !(1 == ~t8_pc~0); 95086#L696-2 is_transmit8_triggered_~__retres1~8#1 := 0; 95087#L707 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 96050#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 96101#L1443 assume !(0 != activate_threads_~tmp___7~0#1); 96172#L1443-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 95551#L715 assume 1 == ~t9_pc~0; 95552#L716 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 95188#L726 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 94897#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 94898#L1451 assume !(0 != activate_threads_~tmp___8~0#1); 95529#L1451-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 95830#L734 assume !(1 == ~t10_pc~0); 95831#L734-2 is_transmit10_triggered_~__retres1~10#1 := 0; 94977#L745 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 94978#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 95757#L1459 assume !(0 != activate_threads_~tmp___9~0#1); 95758#L1459-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 95059#L753 assume 1 == ~t11_pc~0; 95060#L754 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 95661#L764 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 96060#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 95341#L1467 assume !(0 != activate_threads_~tmp___10~0#1); 95342#L1467-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 95400#L1237 assume 1 == ~M_E~0;~M_E~0 := 2; 95401#L1237-2 assume !(1 == ~T1_E~0); 96145#L1242-1 assume !(1 == ~T2_E~0); 95155#L1247-1 assume !(1 == ~T3_E~0); 95156#L1252-1 assume !(1 == ~T4_E~0); 95993#L1257-1 assume !(1 == ~T5_E~0); 95852#L1262-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 95853#L1267-1 assume !(1 == ~T7_E~0); 95987#L1272-1 assume !(1 == ~T8_E~0); 95243#L1277-1 assume !(1 == ~T9_E~0); 95244#L1282-1 assume !(1 == ~T10_E~0); 97441#L1287-1 assume !(1 == ~T11_E~0); 97439#L1292-1 assume !(1 == ~E_M~0); 97406#L1297-1 assume !(1 == ~E_1~0); 97404#L1302-1 assume 1 == ~E_2~0;~E_2~0 := 2; 97401#L1307-1 assume !(1 == ~E_3~0); 97366#L1312-1 assume !(1 == ~E_4~0); 97327#L1317-1 assume !(1 == ~E_5~0); 97324#L1322-1 assume !(1 == ~E_6~0); 97320#L1327-1 assume !(1 == ~E_7~0); 97278#L1332-1 assume !(1 == ~E_8~0); 97248#L1337-1 assume !(1 == ~E_9~0); 97227#L1342-1 assume 1 == ~E_10~0;~E_10~0 := 2; 97213#L1347-1 assume !(1 == ~E_11~0); 97204#L1352-1 assume { :end_inline_reset_delta_events } true; 97196#L1678-2 [2022-12-13 17:13:32,340 INFO L750 eck$LassoCheckResult]: Loop: 97196#L1678-2 assume !false; 97189#L1679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 97186#L1084 assume !false; 97185#L921 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 97163#L848 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 97159#L910 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 97157#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 97152#L925 assume !(0 != eval_~tmp~0#1); 97154#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 103661#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 103659#L1109-3 assume 0 == ~M_E~0;~M_E~0 := 1; 103657#L1109-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 103655#L1114-3 assume !(0 == ~T2_E~0); 103653#L1119-3 assume !(0 == ~T3_E~0); 103651#L1124-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 103649#L1129-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 103647#L1134-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 103645#L1139-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 103643#L1144-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 103641#L1149-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 103638#L1154-3 assume !(0 == ~T10_E~0); 103636#L1159-3 assume !(0 == ~T11_E~0); 103634#L1164-3 assume 0 == ~E_M~0;~E_M~0 := 1; 103632#L1169-3 assume 0 == ~E_1~0;~E_1~0 := 1; 103630#L1174-3 assume 0 == ~E_2~0;~E_2~0 := 1; 103628#L1179-3 assume 0 == ~E_3~0;~E_3~0 := 1; 103625#L1184-3 assume 0 == ~E_4~0;~E_4~0 := 1; 103623#L1189-3 assume 0 == ~E_5~0;~E_5~0 := 1; 103621#L1194-3 assume !(0 == ~E_6~0); 103619#L1199-3 assume !(0 == ~E_7~0); 103617#L1204-3 assume 0 == ~E_8~0;~E_8~0 := 1; 103615#L1209-3 assume 0 == ~E_9~0;~E_9~0 := 1; 103612#L1214-3 assume 0 == ~E_10~0;~E_10~0 := 1; 103610#L1219-3 assume 0 == ~E_11~0;~E_11~0 := 1; 103608#L1224-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 103606#L544-39 assume !(1 == ~m_pc~0); 103604#L544-41 is_master_triggered_~__retres1~0#1 := 0; 103602#L555-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 103599#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 103597#L1379-39 assume !(0 != activate_threads_~tmp~1#1); 103596#L1379-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 103592#L563-39 assume 1 == ~t1_pc~0; 103589#L564-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 103587#L574-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 103586#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 103585#L1387-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 103584#L1387-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 103583#L582-39 assume !(1 == ~t2_pc~0); 103581#L582-41 is_transmit2_triggered_~__retres1~2#1 := 0; 103580#L593-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 103579#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 103577#L1395-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 103575#L1395-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 103573#L601-39 assume !(1 == ~t3_pc~0); 103571#L601-41 is_transmit3_triggered_~__retres1~3#1 := 0; 103568#L612-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 103566#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 103564#L1403-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 103561#L1403-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 103559#L620-39 assume 1 == ~t4_pc~0; 103557#L621-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 103554#L631-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 103552#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 103550#L1411-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 103547#L1411-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 103522#L639-39 assume !(1 == ~t5_pc~0); 98183#L639-41 is_transmit5_triggered_~__retres1~5#1 := 0; 98180#L650-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 98178#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 98175#L1419-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 98173#L1419-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 98171#L658-39 assume 1 == ~t6_pc~0; 98169#L659-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 98166#L669-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 98164#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 98161#L1427-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 98159#L1427-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 98157#L677-39 assume 1 == ~t7_pc~0; 98153#L678-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 98151#L688-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 98148#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 98146#L1435-39 assume !(0 != activate_threads_~tmp___6~0#1); 98144#L1435-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 98142#L696-39 assume 1 == ~t8_pc~0; 98137#L697-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 98135#L707-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 98133#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 98131#L1443-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 98129#L1443-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 98127#L715-39 assume !(1 == ~t9_pc~0); 98125#L715-41 is_transmit9_triggered_~__retres1~9#1 := 0; 98123#L726-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 98120#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 98118#L1451-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 98116#L1451-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 98037#L734-39 assume 1 == ~t10_pc~0; 97963#L735-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 97961#L745-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 97959#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 97895#L1459-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 97842#L1459-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 97841#L753-39 assume 1 == ~t11_pc~0; 97793#L754-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 97790#L764-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 97788#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 97729#L1467-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 97686#L1467-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 97654#L1237-3 assume 1 == ~M_E~0;~M_E~0 := 2; 97650#L1237-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 97619#L1242-3 assume !(1 == ~T2_E~0); 97617#L1247-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 97615#L1252-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 97612#L1257-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 97610#L1262-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 97608#L1267-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 97606#L1272-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 97604#L1277-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 97580#L1282-3 assume !(1 == ~T10_E~0); 97547#L1287-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 97514#L1292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 97512#L1297-3 assume 1 == ~E_1~0;~E_1~0 := 2; 97482#L1302-3 assume 1 == ~E_2~0;~E_2~0 := 2; 97453#L1307-3 assume 1 == ~E_3~0;~E_3~0 := 2; 97451#L1312-3 assume 1 == ~E_4~0;~E_4~0 := 2; 97449#L1317-3 assume 1 == ~E_5~0;~E_5~0 := 2; 97420#L1322-3 assume !(1 == ~E_6~0); 97398#L1327-3 assume 1 == ~E_7~0;~E_7~0 := 2; 97395#L1332-3 assume 1 == ~E_8~0;~E_8~0 := 2; 97393#L1337-3 assume 1 == ~E_9~0;~E_9~0 := 2; 97391#L1342-3 assume 1 == ~E_10~0;~E_10~0 := 2; 97352#L1347-3 assume 1 == ~E_11~0;~E_11~0 := 2; 97350#L1352-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 97310#L848-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 97307#L910-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 97306#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 97303#L1697 assume !(0 == start_simulation_~tmp~3#1); 95928#L1697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 97274#L848-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 97247#L910-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 97245#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; 97243#L1652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 97226#L1659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 97212#stop_simulation_returnLabel#1 start_simulation_#t~ret32#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 97203#L1710 assume !(0 != start_simulation_~tmp___0~1#1); 97196#L1678-2 [2022-12-13 17:13:32,341 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 17:13:32,341 INFO L85 PathProgramCache]: Analyzing trace with hash -1258502475, now seen corresponding path program 1 times [2022-12-13 17:13:32,341 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 17:13:32,341 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1380354613] [2022-12-13 17:13:32,341 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 17:13:32,341 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 17:13:32,381 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 17:13:32,416 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 17:13:32,416 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 17:13:32,416 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1380354613] [2022-12-13 17:13:32,416 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1380354613] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 17:13:32,416 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 17:13:32,417 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 17:13:32,417 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [190023721] [2022-12-13 17:13:32,417 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 17:13:32,417 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 17:13:32,417 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 17:13:32,417 INFO L85 PathProgramCache]: Analyzing trace with hash -1918154297, now seen corresponding path program 1 times [2022-12-13 17:13:32,417 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 17:13:32,417 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [783840605] [2022-12-13 17:13:32,417 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 17:13:32,417 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 17:13:32,425 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 17:13:32,444 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 17:13:32,444 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 17:13:32,444 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [783840605] [2022-12-13 17:13:32,444 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [783840605] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 17:13:32,444 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 17:13:32,445 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 17:13:32,445 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1969685833] [2022-12-13 17:13:32,445 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 17:13:32,445 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 17:13:32,445 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 17:13:32,445 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 17:13:32,445 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 17:13:32,445 INFO L87 Difference]: Start difference. First operand 19865 states and 28958 transitions. cyclomatic complexity: 9109 Second operand has 4 states, 4 states have (on average 34.75) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 17:13:32,868 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 17:13:32,868 INFO L93 Difference]: Finished difference Result 48329 states and 69889 transitions. [2022-12-13 17:13:32,868 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 48329 states and 69889 transitions. [2022-12-13 17:13:33,118 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 47352 [2022-12-13 17:13:33,211 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 48329 states to 48329 states and 69889 transitions. [2022-12-13 17:13:33,212 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 48329 [2022-12-13 17:13:33,232 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 48329 [2022-12-13 17:13:33,232 INFO L73 IsDeterministic]: Start isDeterministic. Operand 48329 states and 69889 transitions. [2022-12-13 17:13:33,257 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 17:13:33,257 INFO L218 hiAutomatonCegarLoop]: Abstraction has 48329 states and 69889 transitions. [2022-12-13 17:13:33,291 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 48329 states and 69889 transitions. [2022-12-13 17:13:33,650 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 48329 to 37893. [2022-12-13 17:13:33,672 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 37893 states, 37893 states have (on average 1.4509276119599925) internal successors, (54980), 37892 states have internal predecessors, (54980), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 17:13:33,727 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 37893 states to 37893 states and 54980 transitions. [2022-12-13 17:13:33,727 INFO L240 hiAutomatonCegarLoop]: Abstraction has 37893 states and 54980 transitions. [2022-12-13 17:13:33,728 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 17:13:33,728 INFO L428 stractBuchiCegarLoop]: Abstraction has 37893 states and 54980 transitions. [2022-12-13 17:13:33,728 INFO L335 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2022-12-13 17:13:33,728 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 37893 states and 54980 transitions. [2022-12-13 17:13:33,838 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 37636 [2022-12-13 17:13:33,838 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 17:13:33,838 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 17:13:33,840 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 17:13:33,840 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 17:13:33,841 INFO L748 eck$LassoCheckResult]: Stem: 162912#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 162913#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 163746#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 163747#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 162886#L780 assume 1 == ~m_i~0;~m_st~0 := 0; 162887#L780-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 164294#L785-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 164252#L790-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 164253#L795-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 163250#L800-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 163251#L805-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 163703#L810-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 164199#L815-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 163159#L820-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 163160#L825-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 163043#L830-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 163044#L835-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 164107#L1109 assume !(0 == ~M_E~0); 164136#L1109-2 assume !(0 == ~T1_E~0); 163052#L1114-1 assume !(0 == ~T2_E~0); 163053#L1119-1 assume !(0 == ~T3_E~0); 164202#L1124-1 assume !(0 == ~T4_E~0); 162696#L1129-1 assume !(0 == ~T5_E~0); 162697#L1134-1 assume !(0 == ~T6_E~0); 163349#L1139-1 assume !(0 == ~T7_E~0); 164117#L1144-1 assume !(0 == ~T8_E~0); 163959#L1149-1 assume !(0 == ~T9_E~0); 162810#L1154-1 assume !(0 == ~T10_E~0); 162811#L1159-1 assume !(0 == ~T11_E~0); 163948#L1164-1 assume !(0 == ~E_M~0); 163211#L1169-1 assume !(0 == ~E_1~0); 163105#L1174-1 assume !(0 == ~E_2~0); 162973#L1179-1 assume !(0 == ~E_3~0); 162892#L1184-1 assume !(0 == ~E_4~0); 162893#L1189-1 assume !(0 == ~E_5~0); 162926#L1194-1 assume !(0 == ~E_6~0); 163014#L1199-1 assume !(0 == ~E_7~0); 163968#L1204-1 assume !(0 == ~E_8~0); 163898#L1209-1 assume !(0 == ~E_9~0); 163899#L1214-1 assume !(0 == ~E_10~0); 164314#L1219-1 assume !(0 == ~E_11~0); 164492#L1224-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 163231#L544 assume !(1 == ~m_pc~0); 163232#L544-2 is_master_triggered_~__retres1~0#1 := 0; 164184#L555 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 163610#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 162853#L1379 assume !(0 != activate_threads_~tmp~1#1); 162854#L1379-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 163689#L563 assume !(1 == ~t1_pc~0); 163470#L563-2 is_transmit1_triggered_~__retres1~1#1 := 0; 162706#L574 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 162707#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 163837#L1387 assume !(0 != activate_threads_~tmp___0~0#1); 162702#L1387-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 162703#L582 assume !(1 == ~t2_pc~0); 163448#L582-2 is_transmit2_triggered_~__retres1~2#1 := 0; 163846#L593 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 163048#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 163049#L1395 assume !(0 != activate_threads_~tmp___1~0#1); 162736#L1395-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 162737#L601 assume !(1 == ~t3_pc~0); 163465#L601-2 is_transmit3_triggered_~__retres1~3#1 := 0; 163464#L612 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 163988#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 163879#L1403 assume !(0 != activate_threads_~tmp___2~0#1); 163880#L1403-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 163821#L620 assume 1 == ~t4_pc~0; 162718#L621 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 162719#L631 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 162750#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 162751#L1411 assume !(0 != activate_threads_~tmp___3~0#1); 163697#L1411-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 163921#L639 assume 1 == ~t5_pc~0; 163791#L640 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 163017#L650 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 163018#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 163723#L1419 assume !(0 != activate_threads_~tmp___4~0#1); 163724#L1419-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 163646#L658 assume !(1 == ~t6_pc~0); 163225#L658-2 is_transmit6_triggered_~__retres1~6#1 := 0; 163226#L669 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 163040#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 163041#L1427 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 163883#L1427-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 163065#L677 assume 1 == ~t7_pc~0; 163066#L678 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 162965#L688 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 164069#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 164242#L1435 assume !(0 != activate_threads_~tmp___6~0#1); 164243#L1435-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 164350#L696 assume !(1 == ~t8_pc~0); 163298#L696-2 is_transmit8_triggered_~__retres1~8#1 := 0; 163299#L707 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 164292#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 164354#L1443 assume !(0 != activate_threads_~tmp___7~0#1); 164436#L1443-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 163775#L715 assume 1 == ~t9_pc~0; 163776#L716 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 163405#L726 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 163103#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 163104#L1451 assume !(0 != activate_threads_~tmp___8~0#1); 163752#L1451-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 164066#L734 assume !(1 == ~t10_pc~0); 164067#L734-2 is_transmit10_triggered_~__retres1~10#1 := 0; 163183#L745 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 163184#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 163991#L1459 assume !(0 != activate_threads_~tmp___9~0#1); 163992#L1459-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 163266#L753 assume 1 == ~t11_pc~0; 163267#L754 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 163889#L764 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 164307#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 163560#L1467 assume !(0 != activate_threads_~tmp___10~0#1); 163561#L1467-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 163620#L1237 assume 1 == ~M_E~0;~M_E~0 := 2; 163621#L1237-2 assume !(1 == ~T1_E~0); 164466#L1242-1 assume !(1 == ~T2_E~0); 163370#L1247-1 assume !(1 == ~T3_E~0); 163371#L1252-1 assume !(1 == ~T4_E~0); 174244#L1257-1 assume !(1 == ~T5_E~0); 174238#L1262-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 174239#L1267-1 assume !(1 == ~T7_E~0); 164228#L1272-1 assume !(1 == ~T8_E~0); 164229#L1277-1 assume !(1 == ~T9_E~0); 174100#L1282-1 assume !(1 == ~T10_E~0); 174096#L1287-1 assume !(1 == ~T11_E~0); 174092#L1292-1 assume !(1 == ~E_M~0); 174089#L1297-1 assume !(1 == ~E_1~0); 174086#L1302-1 assume 1 == ~E_2~0;~E_2~0 := 2; 174083#L1307-1 assume !(1 == ~E_3~0); 174080#L1312-1 assume !(1 == ~E_4~0); 174076#L1317-1 assume !(1 == ~E_5~0); 173991#L1322-1 assume !(1 == ~E_6~0); 173986#L1327-1 assume !(1 == ~E_7~0); 173983#L1332-1 assume !(1 == ~E_8~0); 173980#L1337-1 assume !(1 == ~E_9~0); 173975#L1342-1 assume 1 == ~E_10~0;~E_10~0 := 2; 173957#L1347-1 assume !(1 == ~E_11~0); 173943#L1352-1 assume { :end_inline_reset_delta_events } true; 173934#L1678-2 [2022-12-13 17:13:33,841 INFO L750 eck$LassoCheckResult]: Loop: 173934#L1678-2 assume !false; 173926#L1679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 173922#L1084 assume !false; 173919#L921 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 173906#L848 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 173902#L910 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 173900#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 173896#L925 assume !(0 != eval_~tmp~0#1); 173897#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 178003#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 178001#L1109-3 assume 0 == ~M_E~0;~M_E~0 := 1; 177999#L1109-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 177997#L1114-3 assume !(0 == ~T2_E~0); 177995#L1119-3 assume !(0 == ~T3_E~0); 177992#L1124-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 177990#L1129-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 177988#L1134-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 177986#L1139-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 177984#L1144-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 177983#L1149-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 177979#L1154-3 assume !(0 == ~T10_E~0); 177977#L1159-3 assume !(0 == ~T11_E~0); 177975#L1164-3 assume 0 == ~E_M~0;~E_M~0 := 1; 177974#L1169-3 assume 0 == ~E_1~0;~E_1~0 := 1; 177968#L1174-3 assume 0 == ~E_2~0;~E_2~0 := 1; 177966#L1179-3 assume 0 == ~E_3~0;~E_3~0 := 1; 177964#L1184-3 assume 0 == ~E_4~0;~E_4~0 := 1; 177963#L1189-3 assume 0 == ~E_5~0;~E_5~0 := 1; 177962#L1194-3 assume !(0 == ~E_6~0); 177961#L1199-3 assume !(0 == ~E_7~0); 177960#L1204-3 assume 0 == ~E_8~0;~E_8~0 := 1; 177959#L1209-3 assume 0 == ~E_9~0;~E_9~0 := 1; 177958#L1214-3 assume 0 == ~E_10~0;~E_10~0 := 1; 177957#L1219-3 assume 0 == ~E_11~0;~E_11~0 := 1; 177956#L1224-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 177955#L544-39 assume !(1 == ~m_pc~0); 177954#L544-41 is_master_triggered_~__retres1~0#1 := 0; 177941#L555-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 177939#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 177937#L1379-39 assume !(0 != activate_threads_~tmp~1#1); 177934#L1379-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 177932#L563-39 assume !(1 == ~t1_pc~0); 177930#L563-41 is_transmit1_triggered_~__retres1~1#1 := 0; 177927#L574-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 177925#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 177923#L1387-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 177921#L1387-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 177919#L582-39 assume !(1 == ~t2_pc~0); 167706#L582-41 is_transmit2_triggered_~__retres1~2#1 := 0; 177916#L593-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 177914#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 177912#L1395-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 177910#L1395-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 177908#L601-39 assume !(1 == ~t3_pc~0); 177906#L601-41 is_transmit3_triggered_~__retres1~3#1 := 0; 177903#L612-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 177901#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 177899#L1403-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 177897#L1403-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 177895#L620-39 assume !(1 == ~t4_pc~0); 177892#L620-41 is_transmit4_triggered_~__retres1~4#1 := 0; 177890#L631-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 177888#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 177886#L1411-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 177884#L1411-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 177882#L639-39 assume 1 == ~t5_pc~0; 177879#L640-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 177877#L650-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 177875#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 177873#L1419-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 177871#L1419-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 177869#L658-39 assume !(1 == ~t6_pc~0); 177866#L658-41 is_transmit6_triggered_~__retres1~6#1 := 0; 177864#L669-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 177862#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 177859#L1427-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 177857#L1427-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 177855#L677-39 assume 1 == ~t7_pc~0; 177852#L678-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 177850#L688-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 177848#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 177847#L1435-39 assume !(0 != activate_threads_~tmp___6~0#1); 177845#L1435-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 177843#L696-39 assume 1 == ~t8_pc~0; 177840#L697-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 177838#L707-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 177836#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 177833#L1443-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 177831#L1443-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 177829#L715-39 assume 1 == ~t9_pc~0; 177826#L716-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 177824#L726-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 177822#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 177819#L1451-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 177817#L1451-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 177815#L734-39 assume 1 == ~t10_pc~0; 177812#L735-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 177810#L745-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 177808#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 177805#L1459-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 177803#L1459-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 177801#L753-39 assume !(1 == ~t11_pc~0); 177798#L753-41 is_transmit11_triggered_~__retres1~11#1 := 0; 177796#L764-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 177794#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 177791#L1467-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 177789#L1467-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 177787#L1237-3 assume 1 == ~M_E~0;~M_E~0 := 2; 163632#L1237-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 177720#L1242-3 assume !(1 == ~T2_E~0); 177718#L1247-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 177715#L1252-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 177713#L1257-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 177711#L1262-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 177709#L1267-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 177707#L1272-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 177705#L1277-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 176673#L1282-3 assume !(1 == ~T10_E~0); 176671#L1287-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 176669#L1292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 176667#L1297-3 assume 1 == ~E_1~0;~E_1~0 := 2; 176224#L1302-3 assume 1 == ~E_2~0;~E_2~0 := 2; 176223#L1307-3 assume 1 == ~E_3~0;~E_3~0 := 2; 176222#L1312-3 assume 1 == ~E_4~0;~E_4~0 := 2; 176218#L1317-3 assume 1 == ~E_5~0;~E_5~0 := 2; 174780#L1322-3 assume !(1 == ~E_6~0); 174778#L1327-3 assume 1 == ~E_7~0;~E_7~0 := 2; 174776#L1332-3 assume 1 == ~E_8~0;~E_8~0 := 2; 174774#L1337-3 assume 1 == ~E_9~0;~E_9~0 := 2; 174772#L1342-3 assume 1 == ~E_10~0;~E_10~0 := 2; 174770#L1347-3 assume 1 == ~E_11~0;~E_11~0 := 2; 174769#L1352-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 174521#L848-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 174511#L910-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 174507#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 174504#L1697 assume !(0 == start_simulation_~tmp~3#1); 174498#L1697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 174483#L848-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 174473#L910-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 174112#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; 174108#L1652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 174106#L1659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 174067#stop_simulation_returnLabel#1 start_simulation_#t~ret32#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 173942#L1710 assume !(0 != start_simulation_~tmp___0~1#1); 173934#L1678-2 [2022-12-13 17:13:33,842 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 17:13:33,842 INFO L85 PathProgramCache]: Analyzing trace with hash 1819278198, now seen corresponding path program 1 times [2022-12-13 17:13:33,842 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 17:13:33,842 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [205618490] [2022-12-13 17:13:33,842 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 17:13:33,843 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 17:13:33,860 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 17:13:33,916 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 17:13:33,916 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 17:13:33,917 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [205618490] [2022-12-13 17:13:33,917 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [205618490] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 17:13:33,917 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 17:13:33,917 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-12-13 17:13:33,917 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [703222014] [2022-12-13 17:13:33,917 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 17:13:33,918 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 17:13:33,918 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 17:13:33,918 INFO L85 PathProgramCache]: Analyzing trace with hash 960746313, now seen corresponding path program 1 times [2022-12-13 17:13:33,918 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 17:13:33,918 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1710606094] [2022-12-13 17:13:33,919 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 17:13:33,919 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 17:13:33,934 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 17:13:33,978 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 17:13:33,978 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 17:13:33,978 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1710606094] [2022-12-13 17:13:33,978 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1710606094] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 17:13:33,979 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 17:13:33,979 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-12-13 17:13:33,979 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [913231726] [2022-12-13 17:13:33,979 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 17:13:33,979 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 17:13:33,979 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 17:13:33,980 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 17:13:33,980 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 17:13:33,980 INFO L87 Difference]: Start difference. First operand 37893 states and 54980 transitions. cyclomatic complexity: 17103 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 2 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 17:13:34,274 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 17:13:34,274 INFO L93 Difference]: Finished difference Result 72452 states and 104661 transitions. [2022-12-13 17:13:34,274 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 72452 states and 104661 transitions. [2022-12-13 17:13:34,550 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 72116 [2022-12-13 17:13:34,695 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 72452 states to 72452 states and 104661 transitions. [2022-12-13 17:13:34,695 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 72452 [2022-12-13 17:13:34,722 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 72452 [2022-12-13 17:13:34,722 INFO L73 IsDeterministic]: Start isDeterministic. Operand 72452 states and 104661 transitions. [2022-12-13 17:13:34,750 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 17:13:34,750 INFO L218 hiAutomatonCegarLoop]: Abstraction has 72452 states and 104661 transitions. [2022-12-13 17:13:34,780 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 72452 states and 104661 transitions. [2022-12-13 17:13:35,224 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 72452 to 72388. [2022-12-13 17:13:35,277 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 72388 states, 72388 states have (on average 1.444949439133558) internal successors, (104597), 72387 states have internal predecessors, (104597), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 17:13:35,430 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 72388 states to 72388 states and 104597 transitions. [2022-12-13 17:13:35,430 INFO L240 hiAutomatonCegarLoop]: Abstraction has 72388 states and 104597 transitions. [2022-12-13 17:13:35,430 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 17:13:35,431 INFO L428 stractBuchiCegarLoop]: Abstraction has 72388 states and 104597 transitions. [2022-12-13 17:13:35,431 INFO L335 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2022-12-13 17:13:35,431 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 72388 states and 104597 transitions. [2022-12-13 17:13:35,560 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 72052 [2022-12-13 17:13:35,561 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 17:13:35,561 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 17:13:35,562 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 17:13:35,562 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 17:13:35,562 INFO L748 eck$LassoCheckResult]: Stem: 273258#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 273259#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 274054#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 274055#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 273232#L780 assume 1 == ~m_i~0;~m_st~0 := 0; 273233#L780-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 274595#L785-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 274555#L790-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 274556#L795-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 273589#L800-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 273590#L805-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 274023#L810-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 274504#L815-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 273496#L820-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 273497#L825-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 273386#L830-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 273387#L835-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 274405#L1109 assume !(0 == ~M_E~0); 274431#L1109-2 assume !(0 == ~T1_E~0); 273395#L1114-1 assume !(0 == ~T2_E~0); 273396#L1119-1 assume !(0 == ~T3_E~0); 274509#L1124-1 assume !(0 == ~T4_E~0); 273049#L1129-1 assume !(0 == ~T5_E~0); 273050#L1134-1 assume !(0 == ~T6_E~0); 273680#L1139-1 assume !(0 == ~T7_E~0); 274414#L1144-1 assume !(0 == ~T8_E~0); 274266#L1149-1 assume !(0 == ~T9_E~0); 273157#L1154-1 assume !(0 == ~T10_E~0); 273158#L1159-1 assume !(0 == ~T11_E~0); 274256#L1164-1 assume !(0 == ~E_M~0); 273551#L1169-1 assume !(0 == ~E_1~0); 273448#L1174-1 assume !(0 == ~E_2~0); 273313#L1179-1 assume !(0 == ~E_3~0); 273238#L1184-1 assume !(0 == ~E_4~0); 273239#L1189-1 assume !(0 == ~E_5~0); 273271#L1194-1 assume !(0 == ~E_6~0); 273352#L1199-1 assume !(0 == ~E_7~0); 274275#L1204-1 assume !(0 == ~E_8~0); 274207#L1209-1 assume !(0 == ~E_9~0); 274208#L1214-1 assume !(0 == ~E_10~0); 274609#L1219-1 assume !(0 == ~E_11~0); 274756#L1224-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 273569#L544 assume !(1 == ~m_pc~0); 273570#L544-2 is_master_triggered_~__retres1~0#1 := 0; 274489#L555 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 273940#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 273199#L1379 assume !(0 != activate_threads_~tmp~1#1); 273200#L1379-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 274010#L563 assume !(1 == ~t1_pc~0); 273803#L563-2 is_transmit1_triggered_~__retres1~1#1 := 0; 273059#L574 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 273060#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 274143#L1387 assume !(0 != activate_threads_~tmp___0~0#1); 273055#L1387-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 273056#L582 assume !(1 == ~t2_pc~0); 273779#L582-2 is_transmit2_triggered_~__retres1~2#1 := 0; 274148#L593 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 273391#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 273392#L1395 assume !(0 != activate_threads_~tmp___1~0#1); 273085#L1395-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 273086#L601 assume !(1 == ~t3_pc~0); 273795#L601-2 is_transmit3_triggered_~__retres1~3#1 := 0; 273794#L612 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 274293#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 274187#L1403 assume !(0 != activate_threads_~tmp___2~0#1); 274188#L1403-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 274128#L620 assume !(1 == ~t4_pc~0); 274129#L620-2 is_transmit4_triggered_~__retres1~4#1 := 0; 273704#L631 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 273099#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 273100#L1411 assume !(0 != activate_threads_~tmp___3~0#1); 274020#L1411-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 274229#L639 assume 1 == ~t5_pc~0; 274096#L640 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 273359#L650 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 273360#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 274040#L1419 assume !(0 != activate_threads_~tmp___4~0#1); 274041#L1419-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 273973#L658 assume !(1 == ~t6_pc~0); 273565#L658-2 is_transmit6_triggered_~__retres1~6#1 := 0; 273566#L669 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 273383#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 273384#L1427 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 274194#L1427-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 273406#L677 assume 1 == ~t7_pc~0; 273407#L678 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 273304#L688 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 274373#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 274541#L1435 assume !(0 != activate_threads_~tmp___6~0#1); 274542#L1435-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 274638#L696 assume !(1 == ~t8_pc~0); 273629#L696-2 is_transmit8_triggered_~__retres1~8#1 := 0; 273630#L707 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 274593#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 274642#L1443 assume !(0 != activate_threads_~tmp___7~0#1); 274710#L1443-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 274083#L715 assume 1 == ~t9_pc~0; 274084#L716 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 273735#L726 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 273446#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 273447#L1451 assume !(0 != activate_threads_~tmp___8~0#1); 274062#L1451-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 274370#L734 assume !(1 == ~t10_pc~0); 274371#L734-2 is_transmit10_triggered_~__retres1~10#1 := 0; 273523#L745 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 273524#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 274295#L1459 assume !(0 != activate_threads_~tmp___9~0#1); 274296#L1459-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 273603#L753 assume 1 == ~t11_pc~0; 273604#L754 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 274200#L764 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 274602#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 273891#L1467 assume !(0 != activate_threads_~tmp___10~0#1); 273892#L1467-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 273949#L1237 assume 1 == ~M_E~0;~M_E~0 := 2; 273950#L1237-2 assume !(1 == ~T1_E~0); 274735#L1242-1 assume !(1 == ~T2_E~0); 274736#L1247-1 assume !(1 == ~T3_E~0); 316082#L1252-1 assume !(1 == ~T4_E~0); 316080#L1257-1 assume !(1 == ~T5_E~0); 316077#L1262-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 316075#L1267-1 assume !(1 == ~T7_E~0); 316073#L1272-1 assume !(1 == ~T8_E~0); 316071#L1277-1 assume !(1 == ~T9_E~0); 316069#L1282-1 assume !(1 == ~T10_E~0); 316067#L1287-1 assume !(1 == ~T11_E~0); 316064#L1292-1 assume !(1 == ~E_M~0); 316062#L1297-1 assume !(1 == ~E_1~0); 316060#L1302-1 assume 1 == ~E_2~0;~E_2~0 := 2; 316058#L1307-1 assume !(1 == ~E_3~0); 316056#L1312-1 assume !(1 == ~E_4~0); 316054#L1317-1 assume !(1 == ~E_5~0); 316051#L1322-1 assume !(1 == ~E_6~0); 316047#L1327-1 assume !(1 == ~E_7~0); 316045#L1332-1 assume !(1 == ~E_8~0); 316043#L1337-1 assume !(1 == ~E_9~0); 316041#L1342-1 assume 1 == ~E_10~0;~E_10~0 := 2; 316040#L1347-1 assume !(1 == ~E_11~0); 316036#L1352-1 assume { :end_inline_reset_delta_events } true; 316033#L1678-2 [2022-12-13 17:13:35,562 INFO L750 eck$LassoCheckResult]: Loop: 316033#L1678-2 assume !false; 316019#L1679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 316016#L1084 assume !false; 316015#L921 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 315996#L848 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 315992#L910 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 315988#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 315985#L925 assume !(0 != eval_~tmp~0#1); 315986#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 343036#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 343033#L1109-3 assume 0 == ~M_E~0;~M_E~0 := 1; 273069#L1109-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 273070#L1114-3 assume !(0 == ~T2_E~0); 274195#L1119-3 assume !(0 == ~T3_E~0); 274196#L1124-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 274224#L1129-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 274225#L1134-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 274425#L1139-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 274499#L1144-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 273578#L1149-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 273579#L1154-3 assume !(0 == ~T10_E~0); 273850#L1159-3 assume !(0 == ~T11_E~0); 273851#L1164-3 assume 0 == ~E_M~0;~E_M~0 := 1; 274124#L1169-3 assume 0 == ~E_1~0;~E_1~0 := 1; 274125#L1174-3 assume 0 == ~E_2~0;~E_2~0 := 1; 274180#L1179-3 assume 0 == ~E_3~0;~E_3~0 := 1; 274181#L1184-3 assume 0 == ~E_4~0;~E_4~0 := 1; 274350#L1189-3 assume 0 == ~E_5~0;~E_5~0 := 1; 274004#L1194-3 assume !(0 == ~E_6~0); 273334#L1199-3 assume !(0 == ~E_7~0); 273335#L1204-3 assume 0 == ~E_8~0;~E_8~0 := 1; 273560#L1209-3 assume 0 == ~E_9~0;~E_9~0 := 1; 273026#L1214-3 assume 0 == ~E_10~0;~E_10~0 := 1; 273027#L1219-3 assume 0 == ~E_11~0;~E_11~0 := 1; 273746#L1224-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 273747#L544-39 assume !(1 == ~m_pc~0); 274114#L544-41 is_master_triggered_~__retres1~0#1 := 0; 343254#L555-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 343252#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 343250#L1379-39 assume !(0 != activate_threads_~tmp~1#1); 343248#L1379-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 343246#L563-39 assume !(1 == ~t1_pc~0); 343244#L563-41 is_transmit1_triggered_~__retres1~1#1 := 0; 343241#L574-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 343239#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 343237#L1387-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 343235#L1387-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 319558#L582-39 assume !(1 == ~t2_pc~0); 319556#L582-41 is_transmit2_triggered_~__retres1~2#1 := 0; 319554#L593-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 319552#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 319550#L1395-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 319549#L1395-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 319547#L601-39 assume 1 == ~t3_pc~0; 319544#L602-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 319542#L612-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 319540#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 319538#L1403-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 319535#L1403-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 319533#L620-39 assume !(1 == ~t4_pc~0); 319531#L620-41 is_transmit4_triggered_~__retres1~4#1 := 0; 319529#L631-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 319527#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 319525#L1411-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 319523#L1411-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 319521#L639-39 assume 1 == ~t5_pc~0; 319518#L640-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 319516#L650-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 319514#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 319512#L1419-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 319509#L1419-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 319507#L658-39 assume !(1 == ~t6_pc~0); 319504#L658-41 is_transmit6_triggered_~__retres1~6#1 := 0; 319502#L669-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 319500#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 319498#L1427-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 319495#L1427-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 319493#L677-39 assume 1 == ~t7_pc~0; 319490#L678-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 319488#L688-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 319486#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 319484#L1435-39 assume !(0 != activate_threads_~tmp___6~0#1); 319481#L1435-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 319479#L696-39 assume 1 == ~t8_pc~0; 319476#L697-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 319474#L707-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 319472#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 319470#L1443-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 319467#L1443-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 319465#L715-39 assume 1 == ~t9_pc~0; 319462#L716-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 319460#L726-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 319458#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 319456#L1451-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 319453#L1451-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 319451#L734-39 assume 1 == ~t10_pc~0; 319448#L735-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 319446#L745-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 319444#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 319442#L1459-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 319439#L1459-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 319437#L753-39 assume !(1 == ~t11_pc~0); 319434#L753-41 is_transmit11_triggered_~__retres1~11#1 := 0; 319432#L764-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 319430#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 319428#L1467-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 319425#L1467-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 319423#L1237-3 assume 1 == ~M_E~0;~M_E~0 := 2; 275007#L1237-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 319420#L1242-3 assume !(1 == ~T2_E~0); 313076#L1247-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 319418#L1252-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 319414#L1257-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 319412#L1262-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 319410#L1267-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 319409#L1272-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 319404#L1277-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 319403#L1282-3 assume !(1 == ~T10_E~0); 274983#L1287-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 319402#L1292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 319401#L1297-3 assume 1 == ~E_1~0;~E_1~0 := 2; 319400#L1302-3 assume 1 == ~E_2~0;~E_2~0 := 2; 319399#L1307-3 assume 1 == ~E_3~0;~E_3~0 := 2; 319398#L1312-3 assume 1 == ~E_4~0;~E_4~0 := 2; 319397#L1317-3 assume 1 == ~E_5~0;~E_5~0 := 2; 316199#L1322-3 assume !(1 == ~E_6~0); 316197#L1327-3 assume 1 == ~E_7~0;~E_7~0 := 2; 316195#L1332-3 assume 1 == ~E_8~0;~E_8~0 := 2; 316193#L1337-3 assume 1 == ~E_9~0;~E_9~0 := 2; 316191#L1342-3 assume 1 == ~E_10~0;~E_10~0 := 2; 316189#L1347-3 assume 1 == ~E_11~0;~E_11~0 := 2; 316187#L1352-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 316166#L848-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 316162#L910-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 316160#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 316151#L1697 assume !(0 == start_simulation_~tmp~3#1); 316149#L1697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 316138#L848-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 316128#L910-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 316126#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; 316124#L1652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 316122#L1659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 316120#stop_simulation_returnLabel#1 start_simulation_#t~ret32#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 316035#L1710 assume !(0 != start_simulation_~tmp___0~1#1); 316033#L1678-2 [2022-12-13 17:13:35,563 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 17:13:35,563 INFO L85 PathProgramCache]: Analyzing trace with hash -343701065, now seen corresponding path program 1 times [2022-12-13 17:13:35,563 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 17:13:35,563 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1786433319] [2022-12-13 17:13:35,563 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 17:13:35,563 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 17:13:35,573 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 17:13:35,603 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 17:13:35,603 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 17:13:35,603 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1786433319] [2022-12-13 17:13:35,603 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1786433319] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 17:13:35,603 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 17:13:35,603 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-12-13 17:13:35,604 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [278582563] [2022-12-13 17:13:35,604 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 17:13:35,604 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 17:13:35,604 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 17:13:35,604 INFO L85 PathProgramCache]: Analyzing trace with hash 2121593672, now seen corresponding path program 1 times [2022-12-13 17:13:35,604 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 17:13:35,604 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1274389709] [2022-12-13 17:13:35,604 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 17:13:35,604 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 17:13:35,613 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 17:13:35,720 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 17:13:35,720 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 17:13:35,720 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1274389709] [2022-12-13 17:13:35,720 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1274389709] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 17:13:35,720 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 17:13:35,720 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-12-13 17:13:35,721 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [456239199] [2022-12-13 17:13:35,721 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 17:13:35,721 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 17:13:35,721 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 17:13:35,722 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 17:13:35,722 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 17:13:35,722 INFO L87 Difference]: Start difference. First operand 72388 states and 104597 transitions. cyclomatic complexity: 32241 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 2 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 17:13:36,173 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 17:13:36,173 INFO L93 Difference]: Finished difference Result 141087 states and 202862 transitions. [2022-12-13 17:13:36,173 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 141087 states and 202862 transitions. [2022-12-13 17:13:36,769 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 140528 [2022-12-13 17:13:37,032 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 141087 states to 141087 states and 202862 transitions. [2022-12-13 17:13:37,033 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 141087 [2022-12-13 17:13:37,058 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 141087 [2022-12-13 17:13:37,059 INFO L73 IsDeterministic]: Start isDeterministic. Operand 141087 states and 202862 transitions. [2022-12-13 17:13:37,101 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 17:13:37,101 INFO L218 hiAutomatonCegarLoop]: Abstraction has 141087 states and 202862 transitions. [2022-12-13 17:13:37,149 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 141087 states and 202862 transitions. [2022-12-13 17:13:37,897 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 141087 to 140959. [2022-12-13 17:13:37,990 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 140959 states, 140959 states have (on average 1.438248001191836) internal successors, (202734), 140958 states have internal predecessors, (202734), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 17:13:38,164 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 140959 states to 140959 states and 202734 transitions. [2022-12-13 17:13:38,164 INFO L240 hiAutomatonCegarLoop]: Abstraction has 140959 states and 202734 transitions. [2022-12-13 17:13:38,165 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 17:13:38,165 INFO L428 stractBuchiCegarLoop]: Abstraction has 140959 states and 202734 transitions. [2022-12-13 17:13:38,165 INFO L335 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2022-12-13 17:13:38,165 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 140959 states and 202734 transitions. [2022-12-13 17:13:38,629 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 140400 [2022-12-13 17:13:38,629 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 17:13:38,629 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 17:13:38,631 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 17:13:38,631 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 17:13:38,631 INFO L748 eck$LassoCheckResult]: Stem: 486743#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 486744#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 487539#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 487540#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 486716#L780 assume 1 == ~m_i~0;~m_st~0 := 0; 486717#L780-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 488068#L785-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 488028#L790-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 488029#L795-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 487072#L800-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 487073#L805-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 487507#L810-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 487984#L815-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 486981#L820-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 486982#L825-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 486871#L830-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 486872#L835-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 487879#L1109 assume !(0 == ~M_E~0); 487911#L1109-2 assume !(0 == ~T1_E~0); 486880#L1114-1 assume !(0 == ~T2_E~0); 486881#L1119-1 assume !(0 == ~T3_E~0); 487987#L1124-1 assume !(0 == ~T4_E~0); 486534#L1129-1 assume !(0 == ~T5_E~0); 486535#L1134-1 assume !(0 == ~T6_E~0); 487163#L1139-1 assume !(0 == ~T7_E~0); 487894#L1144-1 assume !(0 == ~T8_E~0); 487740#L1149-1 assume !(0 == ~T9_E~0); 486642#L1154-1 assume !(0 == ~T10_E~0); 486643#L1159-1 assume !(0 == ~T11_E~0); 487728#L1164-1 assume !(0 == ~E_M~0); 487035#L1169-1 assume !(0 == ~E_1~0); 486933#L1174-1 assume !(0 == ~E_2~0); 486797#L1179-1 assume !(0 == ~E_3~0); 486722#L1184-1 assume !(0 == ~E_4~0); 486723#L1189-1 assume !(0 == ~E_5~0); 486756#L1194-1 assume !(0 == ~E_6~0); 486838#L1199-1 assume !(0 == ~E_7~0); 487750#L1204-1 assume !(0 == ~E_8~0); 487684#L1209-1 assume !(0 == ~E_9~0); 487685#L1214-1 assume !(0 == ~E_10~0); 488086#L1219-1 assume !(0 == ~E_11~0); 488239#L1224-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 487052#L544 assume !(1 == ~m_pc~0); 487053#L544-2 is_master_triggered_~__retres1~0#1 := 0; 487967#L555 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 487414#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 486684#L1379 assume !(0 != activate_threads_~tmp~1#1); 486685#L1379-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 487492#L563 assume !(1 == ~t1_pc~0); 487280#L563-2 is_transmit1_triggered_~__retres1~1#1 := 0; 486544#L574 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 486545#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 487624#L1387 assume !(0 != activate_threads_~tmp___0~0#1); 486540#L1387-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 486541#L582 assume !(1 == ~t2_pc~0); 487259#L582-2 is_transmit2_triggered_~__retres1~2#1 := 0; 487629#L593 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 486876#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 486877#L1395 assume !(0 != activate_threads_~tmp___1~0#1); 486570#L1395-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 486571#L601 assume !(1 == ~t3_pc~0); 487275#L601-2 is_transmit3_triggered_~__retres1~3#1 := 0; 487274#L612 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 487770#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 487663#L1403 assume !(0 != activate_threads_~tmp___2~0#1); 487664#L1403-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 487608#L620 assume !(1 == ~t4_pc~0); 487609#L620-2 is_transmit4_triggered_~__retres1~4#1 := 0; 487187#L631 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 486584#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 486585#L1411 assume !(0 != activate_threads_~tmp___3~0#1); 487504#L1411-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 487702#L639 assume !(1 == ~t5_pc~0); 487703#L639-2 is_transmit5_triggered_~__retres1~5#1 := 0; 486843#L650 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 486844#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 487525#L1419 assume !(0 != activate_threads_~tmp___4~0#1); 487526#L1419-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 487450#L658 assume !(1 == ~t6_pc~0); 487049#L658-2 is_transmit6_triggered_~__retres1~6#1 := 0; 487050#L669 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 486868#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 486869#L1427 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 487668#L1427-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 486891#L677 assume 1 == ~t7_pc~0; 486892#L678 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 486789#L688 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 487847#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 488017#L1435 assume !(0 != activate_threads_~tmp___6~0#1); 488018#L1435-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 488113#L696 assume !(1 == ~t8_pc~0); 487113#L696-2 is_transmit8_triggered_~__retres1~8#1 := 0; 487114#L707 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 488065#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 488116#L1443 assume !(0 != activate_threads_~tmp___7~0#1); 488189#L1443-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 487568#L715 assume 1 == ~t9_pc~0; 487569#L716 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 487217#L726 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 486931#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 486932#L1451 assume !(0 != activate_threads_~tmp___8~0#1); 487547#L1451-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 487842#L734 assume !(1 == ~t10_pc~0); 487843#L734-2 is_transmit10_triggered_~__retres1~10#1 := 0; 487008#L745 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 487009#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 487772#L1459 assume !(0 != activate_threads_~tmp___9~0#1); 487773#L1459-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 487086#L753 assume 1 == ~t11_pc~0; 487087#L754 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 487676#L764 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 488076#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 487363#L1467 assume !(0 != activate_threads_~tmp___10~0#1); 487364#L1467-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 487422#L1237 assume 1 == ~M_E~0;~M_E~0 := 2; 487423#L1237-2 assume !(1 == ~T1_E~0); 488218#L1242-1 assume !(1 == ~T2_E~0); 487184#L1247-1 assume !(1 == ~T3_E~0); 487185#L1252-1 assume !(1 == ~T4_E~0); 486950#L1257-1 assume !(1 == ~T5_E~0); 486951#L1262-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 487866#L1267-1 assume !(1 == ~T7_E~0); 488005#L1272-1 assume !(1 == ~T8_E~0); 497828#L1277-1 assume !(1 == ~T9_E~0); 497826#L1282-1 assume !(1 == ~T10_E~0); 493256#L1287-1 assume !(1 == ~T11_E~0); 493254#L1292-1 assume !(1 == ~E_M~0); 493252#L1297-1 assume !(1 == ~E_1~0); 493250#L1302-1 assume 1 == ~E_2~0;~E_2~0 := 2; 493248#L1307-1 assume !(1 == ~E_3~0); 493246#L1312-1 assume !(1 == ~E_4~0); 493244#L1317-1 assume !(1 == ~E_5~0); 493243#L1322-1 assume !(1 == ~E_6~0); 493240#L1327-1 assume !(1 == ~E_7~0); 493235#L1332-1 assume !(1 == ~E_8~0); 493234#L1337-1 assume !(1 == ~E_9~0); 493233#L1342-1 assume 1 == ~E_10~0;~E_10~0 := 2; 491267#L1347-1 assume !(1 == ~E_11~0); 491263#L1352-1 assume { :end_inline_reset_delta_events } true; 491260#L1678-2 [2022-12-13 17:13:38,631 INFO L750 eck$LassoCheckResult]: Loop: 491260#L1678-2 assume !false; 491256#L1679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 491252#L1084 assume !false; 491250#L921 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 491041#L848 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 491036#L910 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 490586#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 490582#L925 assume !(0 != eval_~tmp~0#1); 490583#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 521296#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 521293#L1109-3 assume 0 == ~M_E~0;~M_E~0 := 1; 521289#L1109-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 521286#L1114-3 assume !(0 == ~T2_E~0); 521283#L1119-3 assume !(0 == ~T3_E~0); 521280#L1124-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 521277#L1129-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 521274#L1134-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 521270#L1139-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 521267#L1144-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 521264#L1149-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 520957#L1154-3 assume !(0 == ~T10_E~0); 520956#L1159-3 assume !(0 == ~T11_E~0); 520955#L1164-3 assume 0 == ~E_M~0;~E_M~0 := 1; 520954#L1169-3 assume 0 == ~E_1~0;~E_1~0 := 1; 520953#L1174-3 assume 0 == ~E_2~0;~E_2~0 := 1; 520951#L1179-3 assume 0 == ~E_3~0;~E_3~0 := 1; 520949#L1184-3 assume 0 == ~E_4~0;~E_4~0 := 1; 520947#L1189-3 assume 0 == ~E_5~0;~E_5~0 := 1; 520945#L1194-3 assume !(0 == ~E_6~0); 520943#L1199-3 assume !(0 == ~E_7~0); 520941#L1204-3 assume 0 == ~E_8~0;~E_8~0 := 1; 520939#L1209-3 assume 0 == ~E_9~0;~E_9~0 := 1; 520936#L1214-3 assume 0 == ~E_10~0;~E_10~0 := 1; 520934#L1219-3 assume 0 == ~E_11~0;~E_11~0 := 1; 520932#L1224-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 520930#L544-39 assume !(1 == ~m_pc~0); 520928#L544-41 is_master_triggered_~__retres1~0#1 := 0; 520926#L555-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 520925#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 520923#L1379-39 assume !(0 != activate_threads_~tmp~1#1); 520921#L1379-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 520919#L563-39 assume !(1 == ~t1_pc~0); 520918#L563-41 is_transmit1_triggered_~__retres1~1#1 := 0; 520916#L574-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 520915#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 520914#L1387-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 520913#L1387-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 520912#L582-39 assume !(1 == ~t2_pc~0); 502889#L582-41 is_transmit2_triggered_~__retres1~2#1 := 0; 520909#L593-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 520907#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 520905#L1395-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 520903#L1395-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 520901#L601-39 assume !(1 == ~t3_pc~0); 520899#L601-41 is_transmit3_triggered_~__retres1~3#1 := 0; 520895#L612-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 520893#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 520891#L1403-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 520889#L1403-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 520887#L620-39 assume !(1 == ~t4_pc~0); 520885#L620-41 is_transmit4_triggered_~__retres1~4#1 := 0; 520884#L631-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 520882#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 520880#L1411-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 520878#L1411-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 520868#L639-39 assume !(1 == ~t5_pc~0); 520865#L639-41 is_transmit5_triggered_~__retres1~5#1 := 0; 520863#L650-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 520861#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 520859#L1419-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 520857#L1419-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 520855#L658-39 assume 1 == ~t6_pc~0; 520852#L659-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 520849#L669-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 520847#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 520845#L1427-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 520843#L1427-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 520841#L677-39 assume !(1 == ~t7_pc~0); 520838#L677-41 is_transmit7_triggered_~__retres1~7#1 := 0; 520835#L688-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 520833#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 520831#L1435-39 assume !(0 != activate_threads_~tmp___6~0#1); 520829#L1435-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 520827#L696-39 assume 1 == ~t8_pc~0; 520823#L697-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 520821#L707-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 520819#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 520817#L1443-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 520815#L1443-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 520813#L715-39 assume !(1 == ~t9_pc~0); 520811#L715-41 is_transmit9_triggered_~__retres1~9#1 := 0; 520808#L726-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 520806#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 520804#L1451-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 520802#L1451-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 520800#L734-39 assume !(1 == ~t10_pc~0); 520797#L734-41 is_transmit10_triggered_~__retres1~10#1 := 0; 520794#L745-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 520792#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 520790#L1459-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 520788#L1459-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 520786#L753-39 assume 1 == ~t11_pc~0; 520782#L754-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 520779#L764-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 520777#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 520775#L1467-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 520773#L1467-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 520770#L1237-3 assume 1 == ~M_E~0;~M_E~0 := 2; 502596#L1237-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 520766#L1242-3 assume !(1 == ~T2_E~0); 518392#L1247-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 520763#L1252-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 520761#L1257-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 520759#L1262-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 520757#L1267-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 520755#L1272-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 520753#L1277-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 519090#L1282-3 assume !(1 == ~T10_E~0); 513871#L1287-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 519076#L1292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 519074#L1297-3 assume 1 == ~E_1~0;~E_1~0 := 2; 519071#L1302-3 assume 1 == ~E_2~0;~E_2~0 := 2; 519069#L1307-3 assume 1 == ~E_3~0;~E_3~0 := 2; 488966#L1312-3 assume 1 == ~E_4~0;~E_4~0 := 2; 488959#L1317-3 assume 1 == ~E_5~0;~E_5~0 := 2; 488953#L1322-3 assume !(1 == ~E_6~0); 488954#L1327-3 assume 1 == ~E_7~0;~E_7~0 := 2; 518619#L1332-3 assume 1 == ~E_8~0;~E_8~0 := 2; 517179#L1337-3 assume 1 == ~E_9~0;~E_9~0 := 2; 517178#L1342-3 assume 1 == ~E_10~0;~E_10~0 := 2; 517177#L1347-3 assume 1 == ~E_11~0;~E_11~0 := 2; 517176#L1352-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 497838#L848-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 497834#L910-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 497832#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 493260#L1697 assume !(0 == start_simulation_~tmp~3#1); 493258#L1697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 491292#L848-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 491282#L910-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 491280#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; 491278#L1652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 491276#L1659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 491274#stop_simulation_returnLabel#1 start_simulation_#t~ret32#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 491262#L1710 assume !(0 != start_simulation_~tmp___0~1#1); 491260#L1678-2 [2022-12-13 17:13:38,632 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 17:13:38,632 INFO L85 PathProgramCache]: Analyzing trace with hash 1793793208, now seen corresponding path program 1 times [2022-12-13 17:13:38,632 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 17:13:38,632 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1944154690] [2022-12-13 17:13:38,632 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 17:13:38,632 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 17:13:38,643 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 17:13:38,687 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 17:13:38,688 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 17:13:38,688 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1944154690] [2022-12-13 17:13:38,688 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1944154690] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 17:13:38,688 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 17:13:38,688 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-12-13 17:13:38,688 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1353803427] [2022-12-13 17:13:38,688 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 17:13:38,689 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 17:13:38,689 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 17:13:38,689 INFO L85 PathProgramCache]: Analyzing trace with hash -1509230261, now seen corresponding path program 1 times [2022-12-13 17:13:38,689 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 17:13:38,689 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1166945606] [2022-12-13 17:13:38,690 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 17:13:38,690 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 17:13:38,704 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 17:13:38,732 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 17:13:38,732 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 17:13:38,732 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1166945606] [2022-12-13 17:13:38,732 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1166945606] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 17:13:38,732 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 17:13:38,732 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 17:13:38,733 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [41078463] [2022-12-13 17:13:38,733 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 17:13:38,733 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 17:13:38,733 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 17:13:38,734 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-12-13 17:13:38,734 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-12-13 17:13:38,734 INFO L87 Difference]: Start difference. First operand 140959 states and 202734 transitions. cyclomatic complexity: 61839 Second operand has 5 states, 5 states have (on average 27.8) internal successors, (139), 5 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 17:13:39,813 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 17:13:39,814 INFO L93 Difference]: Finished difference Result 354324 states and 511515 transitions. [2022-12-13 17:13:39,814 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 354324 states and 511515 transitions. [2022-12-13 17:13:40,998 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 352816 [2022-12-13 17:13:41,631 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 354324 states to 354324 states and 511515 transitions. [2022-12-13 17:13:41,631 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 354324 [2022-12-13 17:13:41,727 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 354324 [2022-12-13 17:13:41,727 INFO L73 IsDeterministic]: Start isDeterministic. Operand 354324 states and 511515 transitions. [2022-12-13 17:13:41,863 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 17:13:41,863 INFO L218 hiAutomatonCegarLoop]: Abstraction has 354324 states and 511515 transitions. [2022-12-13 17:13:42,007 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 354324 states and 511515 transitions. [2022-12-13 17:13:43,345 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 354324 to 145138. [2022-12-13 17:13:43,425 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 145138 states, 145138 states have (on average 1.4256294009838912) internal successors, (206913), 145137 states have internal predecessors, (206913), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 17:13:43,633 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 145138 states to 145138 states and 206913 transitions. [2022-12-13 17:13:43,633 INFO L240 hiAutomatonCegarLoop]: Abstraction has 145138 states and 206913 transitions. [2022-12-13 17:13:43,633 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-12-13 17:13:43,634 INFO L428 stractBuchiCegarLoop]: Abstraction has 145138 states and 206913 transitions. [2022-12-13 17:13:43,634 INFO L335 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2022-12-13 17:13:43,634 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 145138 states and 206913 transitions. [2022-12-13 17:13:43,993 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 144576 [2022-12-13 17:13:43,993 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 17:13:43,993 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 17:13:43,994 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 17:13:43,994 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 17:13:43,994 INFO L748 eck$LassoCheckResult]: Stem: 982042#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 982043#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 982850#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 982851#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 982015#L780 assume 1 == ~m_i~0;~m_st~0 := 0; 982016#L780-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 983392#L785-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 983352#L790-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 983353#L795-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 982375#L800-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 982376#L805-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 982816#L810-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 983305#L815-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 982283#L820-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 982284#L825-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 982172#L830-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 982173#L835-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 983206#L1109 assume !(0 == ~M_E~0); 983233#L1109-2 assume !(0 == ~T1_E~0); 982181#L1114-1 assume !(0 == ~T2_E~0); 982182#L1119-1 assume !(0 == ~T3_E~0); 983308#L1124-1 assume !(0 == ~T4_E~0); 981829#L1129-1 assume !(0 == ~T5_E~0); 981830#L1134-1 assume !(0 == ~T6_E~0); 982468#L1139-1 assume !(0 == ~T7_E~0); 983217#L1144-1 assume !(0 == ~T8_E~0); 983058#L1149-1 assume !(0 == ~T9_E~0); 981937#L1154-1 assume !(0 == ~T10_E~0); 981938#L1159-1 assume !(0 == ~T11_E~0); 983047#L1164-1 assume !(0 == ~E_M~0); 982338#L1169-1 assume !(0 == ~E_1~0); 982234#L1174-1 assume !(0 == ~E_2~0); 982096#L1179-1 assume !(0 == ~E_3~0); 982021#L1184-1 assume !(0 == ~E_4~0); 982022#L1189-1 assume !(0 == ~E_5~0); 982056#L1194-1 assume !(0 == ~E_6~0); 982139#L1199-1 assume !(0 == ~E_7~0); 983070#L1204-1 assume !(0 == ~E_8~0); 983001#L1209-1 assume !(0 == ~E_9~0); 983002#L1214-1 assume !(0 == ~E_10~0); 983408#L1219-1 assume !(0 == ~E_11~0); 983555#L1224-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 982355#L544 assume !(1 == ~m_pc~0); 982356#L544-2 is_master_triggered_~__retres1~0#1 := 0; 983289#L555 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 982723#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 981981#L1379 assume !(0 != activate_threads_~tmp~1#1); 981982#L1379-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 982802#L563 assume !(1 == ~t1_pc~0); 982587#L563-2 is_transmit1_triggered_~__retres1~1#1 := 0; 981839#L574 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 981840#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 982940#L1387 assume !(0 != activate_threads_~tmp___0~0#1); 981835#L1387-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 981836#L582 assume !(1 == ~t2_pc~0); 982564#L582-2 is_transmit2_triggered_~__retres1~2#1 := 0; 982945#L593 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 982177#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 982178#L1395 assume !(0 != activate_threads_~tmp___1~0#1); 981865#L1395-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 981866#L601 assume !(1 == ~t3_pc~0); 982581#L601-2 is_transmit3_triggered_~__retres1~3#1 := 0; 982580#L612 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 983088#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 982982#L1403 assume !(0 != activate_threads_~tmp___2~0#1); 982983#L1403-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 982923#L620 assume !(1 == ~t4_pc~0); 982924#L620-2 is_transmit4_triggered_~__retres1~4#1 := 0; 982492#L631 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 981879#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 981880#L1411 assume !(0 != activate_threads_~tmp___3~0#1); 982813#L1411-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 983021#L639 assume !(1 == ~t5_pc~0); 983022#L639-2 is_transmit5_triggered_~__retres1~5#1 := 0; 982144#L650 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 982145#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 982834#L1419 assume !(0 != activate_threads_~tmp___4~0#1); 982835#L1419-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 982757#L658 assume !(1 == ~t6_pc~0); 982352#L658-2 is_transmit6_triggered_~__retres1~6#1 := 0; 982353#L669 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 982975#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 983558#L1427 assume !(0 != activate_threads_~tmp___5~0#1); 982989#L1427-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 982192#L677 assume 1 == ~t7_pc~0; 982193#L678 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 982089#L688 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 983173#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 983340#L1435 assume !(0 != activate_threads_~tmp___6~0#1); 983341#L1435-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 983433#L696 assume !(1 == ~t8_pc~0); 982413#L696-2 is_transmit8_triggered_~__retres1~8#1 := 0; 982414#L707 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 983390#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 983436#L1443 assume !(0 != activate_threads_~tmp___7~0#1); 983506#L1443-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 982879#L715 assume 1 == ~t9_pc~0; 982880#L716 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 982522#L726 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 982232#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 982233#L1451 assume !(0 != activate_threads_~tmp___8~0#1); 982858#L1451-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 983168#L734 assume !(1 == ~t10_pc~0); 983169#L734-2 is_transmit10_triggered_~__retres1~10#1 := 0; 982310#L745 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 982311#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 983090#L1459 assume !(0 != activate_threads_~tmp___9~0#1); 983091#L1459-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 982388#L753 assume 1 == ~t11_pc~0; 982389#L754 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 982994#L764 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 983400#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 982673#L1467 assume !(0 != activate_threads_~tmp___10~0#1); 982674#L1467-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 982730#L1237 assume 1 == ~M_E~0;~M_E~0 := 2; 982731#L1237-2 assume !(1 == ~T1_E~0); 991112#L1242-1 assume !(1 == ~T2_E~0); 991110#L1247-1 assume !(1 == ~T3_E~0); 991108#L1252-1 assume !(1 == ~T4_E~0); 991106#L1257-1 assume !(1 == ~T5_E~0); 991103#L1262-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 991101#L1267-1 assume !(1 == ~T7_E~0); 991099#L1272-1 assume !(1 == ~T8_E~0); 991097#L1277-1 assume !(1 == ~T9_E~0); 991095#L1282-1 assume !(1 == ~T10_E~0); 991093#L1287-1 assume !(1 == ~T11_E~0); 991090#L1292-1 assume !(1 == ~E_M~0); 991088#L1297-1 assume !(1 == ~E_1~0); 991086#L1302-1 assume 1 == ~E_2~0;~E_2~0 := 2; 991084#L1307-1 assume !(1 == ~E_3~0); 991082#L1312-1 assume !(1 == ~E_4~0); 991080#L1317-1 assume !(1 == ~E_5~0); 991077#L1322-1 assume !(1 == ~E_6~0); 991073#L1327-1 assume !(1 == ~E_7~0); 991071#L1332-1 assume !(1 == ~E_8~0); 991069#L1337-1 assume !(1 == ~E_9~0); 991067#L1342-1 assume 1 == ~E_10~0;~E_10~0 := 2; 991065#L1347-1 assume !(1 == ~E_11~0); 991062#L1352-1 assume { :end_inline_reset_delta_events } true; 991059#L1678-2 [2022-12-13 17:13:43,995 INFO L750 eck$LassoCheckResult]: Loop: 991059#L1678-2 assume !false; 989532#L1679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 989529#L1084 assume !false; 989528#L921 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 988974#L848 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 988970#L910 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 988969#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 988964#L925 assume !(0 != eval_~tmp~0#1); 988965#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1045092#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1045037#L1109-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1045032#L1109-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1045026#L1114-3 assume !(0 == ~T2_E~0); 1045020#L1119-3 assume !(0 == ~T3_E~0); 1045015#L1124-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1045010#L1129-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1045003#L1134-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1044998#L1139-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1044992#L1144-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1044986#L1149-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 1044980#L1154-3 assume !(0 == ~T10_E~0); 1044974#L1159-3 assume !(0 == ~T11_E~0); 1044966#L1164-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1044960#L1169-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1044953#L1174-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1044946#L1179-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1044940#L1184-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1044934#L1189-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1044926#L1194-3 assume !(0 == ~E_6~0); 1044922#L1199-3 assume !(0 == ~E_7~0); 1044272#L1204-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1044268#L1209-3 assume 0 == ~E_9~0;~E_9~0 := 1; 1044264#L1214-3 assume 0 == ~E_10~0;~E_10~0 := 1; 1044260#L1219-3 assume 0 == ~E_11~0;~E_11~0 := 1; 1044256#L1224-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1044255#L544-39 assume !(1 == ~m_pc~0); 1044254#L544-41 is_master_triggered_~__retres1~0#1 := 0; 1044253#L555-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1044252#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1044251#L1379-39 assume !(0 != activate_threads_~tmp~1#1); 1044250#L1379-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1044249#L563-39 assume !(1 == ~t1_pc~0); 1044248#L563-41 is_transmit1_triggered_~__retres1~1#1 := 0; 1044246#L574-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1044245#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1044244#L1387-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1044243#L1387-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1044242#L582-39 assume !(1 == ~t2_pc~0); 1026304#L582-41 is_transmit2_triggered_~__retres1~2#1 := 0; 1044241#L593-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1044240#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1044239#L1395-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1044238#L1395-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1044237#L601-39 assume !(1 == ~t3_pc~0); 1044236#L601-41 is_transmit3_triggered_~__retres1~3#1 := 0; 1044234#L612-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1044233#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1044232#L1403-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1044231#L1403-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1044230#L620-39 assume !(1 == ~t4_pc~0); 1044229#L620-41 is_transmit4_triggered_~__retres1~4#1 := 0; 1044228#L631-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1044227#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1044226#L1411-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1044225#L1411-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1044224#L639-39 assume !(1 == ~t5_pc~0); 1044223#L639-41 is_transmit5_triggered_~__retres1~5#1 := 0; 1044222#L650-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1044221#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1044220#L1419-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1044219#L1419-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1044218#L658-39 assume !(1 == ~t6_pc~0); 1044217#L658-41 is_transmit6_triggered_~__retres1~6#1 := 0; 1044215#L669-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1044213#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1044211#L1427-39 assume !(0 != activate_threads_~tmp___5~0#1); 1044160#L1427-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1044107#L677-39 assume !(1 == ~t7_pc~0); 1044102#L677-41 is_transmit7_triggered_~__retres1~7#1 := 0; 1044095#L688-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1044089#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1044086#L1435-39 assume !(0 != activate_threads_~tmp___6~0#1); 1044082#L1435-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1044063#L696-39 assume !(1 == ~t8_pc~0); 1044060#L696-41 is_transmit8_triggered_~__retres1~8#1 := 0; 1044056#L707-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1044054#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1044052#L1443-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1044050#L1443-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1044048#L715-39 assume !(1 == ~t9_pc~0); 1044046#L715-41 is_transmit9_triggered_~__retres1~9#1 := 0; 1044042#L726-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1044040#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1044038#L1451-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1044036#L1451-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1044034#L734-39 assume 1 == ~t10_pc~0; 1044031#L735-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 1044028#L745-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1044026#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1044024#L1459-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1044018#L1459-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1044014#L753-39 assume 1 == ~t11_pc~0; 1044010#L754-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 1044004#L764-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1043951#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1043945#L1467-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 1043941#L1467-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1043848#L1237-3 assume 1 == ~M_E~0;~M_E~0 := 2; 992250#L1237-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1038883#L1242-3 assume !(1 == ~T2_E~0); 1038881#L1247-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1038879#L1252-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1038877#L1257-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1038875#L1262-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1038872#L1267-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1038870#L1272-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1038868#L1277-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 994659#L1282-3 assume !(1 == ~T10_E~0); 994657#L1287-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 994655#L1292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 994653#L1297-3 assume 1 == ~E_1~0;~E_1~0 := 2; 994651#L1302-3 assume 1 == ~E_2~0;~E_2~0 := 2; 994650#L1307-3 assume 1 == ~E_3~0;~E_3~0 := 2; 994649#L1312-3 assume 1 == ~E_4~0;~E_4~0 := 2; 994648#L1317-3 assume 1 == ~E_5~0;~E_5~0 := 2; 992204#L1322-3 assume !(1 == ~E_6~0); 992201#L1327-3 assume 1 == ~E_7~0;~E_7~0 := 2; 992199#L1332-3 assume 1 == ~E_8~0;~E_8~0 := 2; 992197#L1337-3 assume 1 == ~E_9~0;~E_9~0 := 2; 992195#L1342-3 assume 1 == ~E_10~0;~E_10~0 := 2; 992193#L1347-3 assume 1 == ~E_11~0;~E_11~0 := 2; 992191#L1352-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 991913#L848-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 991910#L910-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 991909#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 991852#L1697 assume !(0 == start_simulation_~tmp~3#1); 991850#L1697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 991839#L848-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 991829#L910-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 991827#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; 991825#L1652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 991823#L1659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 991820#stop_simulation_returnLabel#1 start_simulation_#t~ret32#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 991061#L1710 assume !(0 != start_simulation_~tmp___0~1#1); 991059#L1678-2 [2022-12-13 17:13:43,995 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 17:13:43,995 INFO L85 PathProgramCache]: Analyzing trace with hash -1240256838, now seen corresponding path program 1 times [2022-12-13 17:13:43,995 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 17:13:43,995 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [164285119] [2022-12-13 17:13:43,995 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 17:13:43,995 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 17:13:44,004 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 17:13:44,037 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 17:13:44,037 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 17:13:44,037 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [164285119] [2022-12-13 17:13:44,037 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [164285119] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 17:13:44,037 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 17:13:44,037 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 17:13:44,037 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1922105539] [2022-12-13 17:13:44,037 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 17:13:44,038 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 17:13:44,038 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 17:13:44,038 INFO L85 PathProgramCache]: Analyzing trace with hash -309539570, now seen corresponding path program 1 times [2022-12-13 17:13:44,038 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 17:13:44,038 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1162209764] [2022-12-13 17:13:44,038 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 17:13:44,038 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 17:13:44,046 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 17:13:44,075 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 17:13:44,075 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 17:13:44,075 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1162209764] [2022-12-13 17:13:44,075 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1162209764] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 17:13:44,076 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 17:13:44,076 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-12-13 17:13:44,076 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1369445012] [2022-12-13 17:13:44,076 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 17:13:44,076 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 17:13:44,076 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 17:13:44,077 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 17:13:44,077 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 17:13:44,077 INFO L87 Difference]: Start difference. First operand 145138 states and 206913 transitions. cyclomatic complexity: 61839 Second operand has 4 states, 4 states have (on average 34.75) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 17:13:45,146 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 17:13:45,146 INFO L93 Difference]: Finished difference Result 350285 states and 496218 transitions. [2022-12-13 17:13:45,146 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 350285 states and 496218 transitions. [2022-12-13 17:13:46,416 INFO L131 ngComponentsAnalysis]: Automaton has 96 accepting balls. 343420 [2022-12-13 17:13:47,072 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 350285 states to 350285 states and 496218 transitions. [2022-12-13 17:13:47,072 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 350285 [2022-12-13 17:13:47,188 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 350285 [2022-12-13 17:13:47,188 INFO L73 IsDeterministic]: Start isDeterministic. Operand 350285 states and 496218 transitions. [2022-12-13 17:13:47,294 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 17:13:47,294 INFO L218 hiAutomatonCegarLoop]: Abstraction has 350285 states and 496218 transitions. [2022-12-13 17:13:47,431 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 350285 states and 496218 transitions. [2022-12-13 17:13:49,166 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 350285 to 277249. [2022-12-13 17:13:49,309 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 277249 states, 277249 states have (on average 1.4206940331615263) internal successors, (393886), 277248 states have internal predecessors, (393886), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 17:13:49,956 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 277249 states to 277249 states and 393886 transitions. [2022-12-13 17:13:49,956 INFO L240 hiAutomatonCegarLoop]: Abstraction has 277249 states and 393886 transitions. [2022-12-13 17:13:49,957 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 17:13:49,957 INFO L428 stractBuchiCegarLoop]: Abstraction has 277249 states and 393886 transitions. [2022-12-13 17:13:49,957 INFO L335 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2022-12-13 17:13:49,957 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 277249 states and 393886 transitions. [2022-12-13 17:13:50,525 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 276368 [2022-12-13 17:13:50,525 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 17:13:50,525 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 17:13:50,527 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 17:13:50,527 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 17:13:50,527 INFO L748 eck$LassoCheckResult]: Stem: 1477475#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 1477476#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 1478284#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1478285#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1477449#L780 assume 1 == ~m_i~0;~m_st~0 := 0; 1477450#L780-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1478793#L785-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1478753#L790-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1478754#L795-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1477812#L800-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1477813#L805-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1478250#L810-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1478717#L815-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1477717#L820-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1477718#L825-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 1477606#L830-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 1477607#L835-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1478615#L1109 assume !(0 == ~M_E~0); 1478642#L1109-2 assume !(0 == ~T1_E~0); 1477615#L1114-1 assume !(0 == ~T2_E~0); 1477616#L1119-1 assume !(0 == ~T3_E~0); 1478720#L1124-1 assume !(0 == ~T4_E~0); 1477265#L1129-1 assume !(0 == ~T5_E~0); 1477266#L1134-1 assume !(0 == ~T6_E~0); 1477903#L1139-1 assume !(0 == ~T7_E~0); 1478625#L1144-1 assume !(0 == ~T8_E~0); 1478484#L1149-1 assume !(0 == ~T9_E~0); 1477373#L1154-1 assume !(0 == ~T10_E~0); 1477374#L1159-1 assume !(0 == ~T11_E~0); 1478474#L1164-1 assume !(0 == ~E_M~0); 1477772#L1169-1 assume !(0 == ~E_1~0); 1477666#L1174-1 assume !(0 == ~E_2~0); 1477530#L1179-1 assume !(0 == ~E_3~0); 1477455#L1184-1 assume !(0 == ~E_4~0); 1477456#L1189-1 assume !(0 == ~E_5~0); 1477489#L1194-1 assume !(0 == ~E_6~0); 1477573#L1199-1 assume !(0 == ~E_7~0); 1478493#L1204-1 assume !(0 == ~E_8~0); 1478426#L1209-1 assume !(0 == ~E_9~0); 1478427#L1214-1 assume !(0 == ~E_10~0); 1478809#L1219-1 assume !(0 == ~E_11~0); 1478956#L1224-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1477790#L544 assume !(1 == ~m_pc~0); 1477791#L544-2 is_master_triggered_~__retres1~0#1 := 0; 1478701#L555 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1478157#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1477415#L1379 assume !(0 != activate_threads_~tmp~1#1); 1477416#L1379-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1478237#L563 assume !(1 == ~t1_pc~0); 1478023#L563-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1477275#L574 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1477276#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1478368#L1387 assume !(0 != activate_threads_~tmp___0~0#1); 1477271#L1387-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1477272#L582 assume !(1 == ~t2_pc~0); 1478000#L582-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1478373#L593 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1477611#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1477612#L1395 assume !(0 != activate_threads_~tmp___1~0#1); 1477301#L1395-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1477302#L601 assume !(1 == ~t3_pc~0); 1478018#L601-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1478017#L612 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1478515#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1478406#L1403 assume !(0 != activate_threads_~tmp___2~0#1); 1478407#L1403-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1478348#L620 assume !(1 == ~t4_pc~0); 1478349#L620-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1477928#L631 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1477315#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1477316#L1411 assume !(0 != activate_threads_~tmp___3~0#1); 1478247#L1411-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1478447#L639 assume !(1 == ~t5_pc~0); 1478448#L639-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1477578#L650 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1477579#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1478268#L1419 assume !(0 != activate_threads_~tmp___4~0#1); 1478269#L1419-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1478194#L658 assume !(1 == ~t6_pc~0); 1477787#L658-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1477788#L669 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1478987#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1478958#L1427 assume !(0 != activate_threads_~tmp___5~0#1); 1478411#L1427-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1477626#L677 assume !(1 == ~t7_pc~0); 1477522#L677-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1477523#L688 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1478585#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1478747#L1435 assume !(0 != activate_threads_~tmp___6~0#1); 1478748#L1435-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1478831#L696 assume !(1 == ~t8_pc~0); 1477852#L696-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1477853#L707 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1478791#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1478835#L1443 assume !(0 != activate_threads_~tmp___7~0#1); 1478906#L1443-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1478313#L715 assume 1 == ~t9_pc~0; 1478314#L716 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 1477957#L726 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1477664#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1477665#L1451 assume !(0 != activate_threads_~tmp___8~0#1); 1478291#L1451-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1478580#L734 assume !(1 == ~t10_pc~0); 1478581#L734-2 is_transmit10_triggered_~__retres1~10#1 := 0; 1477744#L745 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1477745#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1478517#L1459 assume !(0 != activate_threads_~tmp___9~0#1); 1478518#L1459-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1477826#L753 assume 1 == ~t11_pc~0; 1477827#L754 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 1478420#L764 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1478802#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1478107#L1467 assume !(0 != activate_threads_~tmp___10~0#1); 1478108#L1467-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1478164#L1237 assume 1 == ~M_E~0;~M_E~0 := 2; 1478165#L1237-2 assume !(1 == ~T1_E~0); 1478875#L1242-1 assume !(1 == ~T2_E~0); 1477925#L1247-1 assume !(1 == ~T3_E~0); 1477926#L1252-1 assume !(1 == ~T4_E~0); 1477684#L1257-1 assume !(1 == ~T5_E~0); 1477685#L1262-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1478602#L1267-1 assume !(1 == ~T7_E~0); 1478739#L1272-1 assume !(1 == ~T8_E~0); 1478012#L1277-1 assume !(1 == ~T9_E~0); 1478013#L1282-1 assume !(1 == ~T10_E~0); 1478523#L1287-1 assume !(1 == ~T11_E~0); 1478494#L1292-1 assume !(1 == ~E_M~0); 1478495#L1297-1 assume !(1 == ~E_1~0); 1477817#L1302-1 assume 1 == ~E_2~0;~E_2~0 := 2; 1477818#L1307-1 assume !(1 == ~E_3~0); 1478912#L1312-1 assume !(1 == ~E_4~0); 1478913#L1317-1 assume !(1 == ~E_5~0); 1478304#L1322-1 assume !(1 == ~E_6~0); 1478305#L1327-1 assume !(1 == ~E_7~0); 1478366#L1332-1 assume !(1 == ~E_8~0); 1478367#L1337-1 assume !(1 == ~E_9~0); 1478297#L1342-1 assume 1 == ~E_10~0;~E_10~0 := 2; 1478298#L1347-1 assume !(1 == ~E_11~0); 1478723#L1352-1 assume { :end_inline_reset_delta_events } true; 1478724#L1678-2 [2022-12-13 17:13:50,528 INFO L750 eck$LassoCheckResult]: Loop: 1478724#L1678-2 assume !false; 1600986#L1679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1600982#L1084 assume !false; 1600980#L921 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 1600956#L848 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 1600951#L910 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 1600949#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1600946#L925 assume !(0 != eval_~tmp~0#1); 1600947#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1601594#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1601592#L1109-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1601590#L1109-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1601588#L1114-3 assume !(0 == ~T2_E~0); 1601585#L1119-3 assume !(0 == ~T3_E~0); 1601583#L1124-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1601581#L1129-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1601579#L1134-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1601577#L1139-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1601576#L1144-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1601572#L1149-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 1601570#L1154-3 assume !(0 == ~T10_E~0); 1601568#L1159-3 assume !(0 == ~T11_E~0); 1601563#L1164-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1601562#L1169-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1601561#L1174-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1601560#L1179-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1601559#L1184-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1601558#L1189-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1601557#L1194-3 assume !(0 == ~E_6~0); 1601556#L1199-3 assume !(0 == ~E_7~0); 1601555#L1204-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1601554#L1209-3 assume 0 == ~E_9~0;~E_9~0 := 1; 1601553#L1214-3 assume 0 == ~E_10~0;~E_10~0 := 1; 1601551#L1219-3 assume 0 == ~E_11~0;~E_11~0 := 1; 1601549#L1224-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1601548#L544-39 assume !(1 == ~m_pc~0); 1601547#L544-41 is_master_triggered_~__retres1~0#1 := 0; 1601546#L555-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1601544#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1601543#L1379-39 assume !(0 != activate_threads_~tmp~1#1); 1601542#L1379-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1601541#L563-39 assume 1 == ~t1_pc~0; 1601539#L564-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1601538#L574-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1601537#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1601536#L1387-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1601534#L1387-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1601532#L582-39 assume !(1 == ~t2_pc~0); 1596978#L582-41 is_transmit2_triggered_~__retres1~2#1 := 0; 1601529#L593-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1601527#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1601525#L1395-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1601523#L1395-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1601520#L601-39 assume 1 == ~t3_pc~0; 1601517#L602-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1601515#L612-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1601513#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1601511#L1403-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1601509#L1403-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1601508#L620-39 assume !(1 == ~t4_pc~0); 1601506#L620-41 is_transmit4_triggered_~__retres1~4#1 := 0; 1601504#L631-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1601502#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1601500#L1411-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1601498#L1411-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1601495#L639-39 assume !(1 == ~t5_pc~0); 1601493#L639-41 is_transmit5_triggered_~__retres1~5#1 := 0; 1601491#L650-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1601489#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1601487#L1419-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1601485#L1419-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1601483#L658-39 assume 1 == ~t6_pc~0; 1601481#L659-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1601482#L669-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1601545#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1601472#L1427-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1601470#L1427-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1601468#L677-39 assume !(1 == ~t7_pc~0); 1531170#L677-41 is_transmit7_triggered_~__retres1~7#1 := 0; 1601465#L688-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1601463#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1601461#L1435-39 assume !(0 != activate_threads_~tmp___6~0#1); 1601459#L1435-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1601456#L696-39 assume 1 == ~t8_pc~0; 1601453#L697-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 1601451#L707-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1601448#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1601446#L1443-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1601444#L1443-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1601443#L715-39 assume 1 == ~t9_pc~0; 1601440#L716-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 1601438#L726-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1601436#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1601434#L1451-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1601432#L1451-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1601429#L734-39 assume 1 == ~t10_pc~0; 1601426#L735-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 1601424#L745-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1601422#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1601420#L1459-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1601418#L1459-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1601415#L753-39 assume !(1 == ~t11_pc~0); 1601412#L753-41 is_transmit11_triggered_~__retres1~11#1 := 0; 1601410#L764-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1601408#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1601406#L1467-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 1601404#L1467-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1601401#L1237-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1577662#L1237-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1601398#L1242-3 assume !(1 == ~T2_E~0); 1586241#L1247-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1601395#L1252-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1601393#L1257-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1601390#L1262-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1601388#L1267-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1601386#L1272-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1601384#L1277-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1601382#L1282-3 assume !(1 == ~T10_E~0); 1582893#L1287-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 1601378#L1292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1601376#L1297-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1601374#L1302-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1601369#L1307-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1601368#L1312-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1601367#L1317-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1601366#L1322-3 assume !(1 == ~E_6~0); 1588372#L1327-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1601365#L1332-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1601364#L1337-3 assume 1 == ~E_9~0;~E_9~0 := 2; 1601363#L1342-3 assume 1 == ~E_10~0;~E_10~0 := 2; 1601362#L1347-3 assume 1 == ~E_11~0;~E_11~0 := 2; 1601361#L1352-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 1601346#L848-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 1601342#L910-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 1601340#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 1601165#L1697 assume !(0 == start_simulation_~tmp~3#1); 1601163#L1697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 1601151#L848-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 1601142#L910-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 1601137#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; 1601136#L1652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1601135#L1659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1601133#stop_simulation_returnLabel#1 start_simulation_#t~ret32#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 1601131#L1710 assume !(0 != start_simulation_~tmp___0~1#1); 1478724#L1678-2 [2022-12-13 17:13:50,528 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 17:13:50,528 INFO L85 PathProgramCache]: Analyzing trace with hash 1946581819, now seen corresponding path program 1 times [2022-12-13 17:13:50,528 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 17:13:50,528 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [53874621] [2022-12-13 17:13:50,529 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 17:13:50,529 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 17:13:50,539 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 17:13:50,586 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 17:13:50,586 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 17:13:50,586 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [53874621] [2022-12-13 17:13:50,586 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [53874621] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 17:13:50,586 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 17:13:50,586 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 17:13:50,586 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [709383465] [2022-12-13 17:13:50,587 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 17:13:50,587 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 17:13:50,587 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 17:13:50,587 INFO L85 PathProgramCache]: Analyzing trace with hash -1125307640, now seen corresponding path program 1 times [2022-12-13 17:13:50,588 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 17:13:50,588 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1580828642] [2022-12-13 17:13:50,588 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 17:13:50,588 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 17:13:50,601 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 17:13:50,630 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 17:13:50,630 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 17:13:50,630 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1580828642] [2022-12-13 17:13:50,630 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1580828642] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 17:13:50,630 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 17:13:50,630 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 17:13:50,630 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1930077362] [2022-12-13 17:13:50,630 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 17:13:50,631 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 17:13:50,631 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 17:13:50,631 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 17:13:50,631 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 17:13:50,632 INFO L87 Difference]: Start difference. First operand 277249 states and 393886 transitions. cyclomatic complexity: 116701 Second operand has 4 states, 4 states have (on average 34.75) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 17:13:52,680 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 17:13:52,681 INFO L93 Difference]: Finished difference Result 665168 states and 939227 transitions. [2022-12-13 17:13:52,681 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 665168 states and 939227 transitions. [2022-12-13 17:13:54,961 INFO L131 ngComponentsAnalysis]: Automaton has 96 accepting balls. 651744 [2022-12-13 17:13:56,219 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 665168 states to 665168 states and 939227 transitions. [2022-12-13 17:13:56,220 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 665168 [2022-12-13 17:13:56,459 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 665168 [2022-12-13 17:13:56,459 INFO L73 IsDeterministic]: Start isDeterministic. Operand 665168 states and 939227 transitions. [2022-12-13 17:13:56,784 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 17:13:56,784 INFO L218 hiAutomatonCegarLoop]: Abstraction has 665168 states and 939227 transitions. [2022-12-13 17:13:57,045 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 665168 states and 939227 transitions. [2022-12-13 17:14:00,755 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 665168 to 528944. [2022-12-13 17:14:00,964 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 528944 states, 528944 states have (on average 1.416155585468405) internal successors, (749067), 528943 states have internal predecessors, (749067), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 17:14:01,833 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 528944 states to 528944 states and 749067 transitions. [2022-12-13 17:14:01,833 INFO L240 hiAutomatonCegarLoop]: Abstraction has 528944 states and 749067 transitions. [2022-12-13 17:14:01,833 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 17:14:01,834 INFO L428 stractBuchiCegarLoop]: Abstraction has 528944 states and 749067 transitions. [2022-12-13 17:14:01,834 INFO L335 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2022-12-13 17:14:01,834 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 528944 states and 749067 transitions. [2022-12-13 17:14:02,970 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 527424 [2022-12-13 17:14:02,970 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 17:14:02,970 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 17:14:02,971 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 17:14:02,972 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 17:14:02,972 INFO L748 eck$LassoCheckResult]: Stem: 2419902#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 2419903#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 2420723#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2420724#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2419876#L780 assume 1 == ~m_i~0;~m_st~0 := 0; 2419877#L780-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2421274#L785-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2421228#L790-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2421229#L795-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 2420231#L800-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 2420232#L805-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 2420687#L810-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 2421180#L815-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 2420138#L820-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 2420139#L825-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 2420030#L830-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 2420031#L835-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2421070#L1109 assume !(0 == ~M_E~0); 2421097#L1109-2 assume !(0 == ~T1_E~0); 2420039#L1114-1 assume !(0 == ~T2_E~0); 2420040#L1119-1 assume !(0 == ~T3_E~0); 2421183#L1124-1 assume !(0 == ~T4_E~0); 2419691#L1129-1 assume !(0 == ~T5_E~0); 2419692#L1134-1 assume !(0 == ~T6_E~0); 2420326#L1139-1 assume !(0 == ~T7_E~0); 2421082#L1144-1 assume !(0 == ~T8_E~0); 2420921#L1149-1 assume !(0 == ~T9_E~0); 2419802#L1154-1 assume !(0 == ~T10_E~0); 2419803#L1159-1 assume !(0 == ~T11_E~0); 2420909#L1164-1 assume !(0 == ~E_M~0); 2420191#L1169-1 assume !(0 == ~E_1~0); 2420089#L1174-1 assume !(0 == ~E_2~0); 2419960#L1179-1 assume !(0 == ~E_3~0); 2419882#L1184-1 assume !(0 == ~E_4~0); 2419883#L1189-1 assume !(0 == ~E_5~0); 2419915#L1194-1 assume !(0 == ~E_6~0); 2420001#L1199-1 assume !(0 == ~E_7~0); 2420931#L1204-1 assume !(0 == ~E_8~0); 2420868#L1209-1 assume !(0 == ~E_9~0); 2420869#L1214-1 assume !(0 == ~E_10~0); 2421297#L1219-1 assume !(0 == ~E_11~0); 2421452#L1224-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2420211#L544 assume !(1 == ~m_pc~0); 2420212#L544-2 is_master_triggered_~__retres1~0#1 := 0; 2421159#L555 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2420588#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2419845#L1379 assume !(0 != activate_threads_~tmp~1#1); 2419846#L1379-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2420674#L563 assume !(1 == ~t1_pc~0); 2420446#L563-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2419701#L574 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2419702#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2420809#L1387 assume !(0 != activate_threads_~tmp___0~0#1); 2419697#L1387-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2419698#L582 assume !(1 == ~t2_pc~0); 2420423#L582-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2420814#L593 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2420035#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2420036#L1395 assume !(0 != activate_threads_~tmp___1~0#1); 2419727#L1395-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2419728#L601 assume !(1 == ~t3_pc~0); 2420441#L601-2 is_transmit3_triggered_~__retres1~3#1 := 0; 2420440#L612 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2420954#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2420846#L1403 assume !(0 != activate_threads_~tmp___2~0#1); 2420847#L1403-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2420788#L620 assume !(1 == ~t4_pc~0); 2420789#L620-2 is_transmit4_triggered_~__retres1~4#1 := 0; 2420353#L631 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2419741#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2419742#L1411 assume !(0 != activate_threads_~tmp___3~0#1); 2420684#L1411-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2420887#L639 assume !(1 == ~t5_pc~0); 2420888#L639-2 is_transmit5_triggered_~__retres1~5#1 := 0; 2420004#L650 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2420005#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2420704#L1419 assume !(0 != activate_threads_~tmp___4~0#1); 2420705#L1419-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2420630#L658 assume !(1 == ~t6_pc~0); 2420206#L658-2 is_transmit6_triggered_~__retres1~6#1 := 0; 2420207#L669 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2421487#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 2421456#L1427 assume !(0 != activate_threads_~tmp___5~0#1); 2420851#L1427-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2420052#L677 assume !(1 == ~t7_pc~0); 2419950#L677-2 is_transmit7_triggered_~__retres1~7#1 := 0; 2419951#L688 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2421033#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 2421218#L1435 assume !(0 != activate_threads_~tmp___6~0#1); 2421219#L1435-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2421321#L696 assume !(1 == ~t8_pc~0); 2420276#L696-2 is_transmit8_triggered_~__retres1~8#1 := 0; 2420277#L707 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2421272#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 2421324#L1443 assume !(0 != activate_threads_~tmp___7~0#1); 2421400#L1443-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 2420751#L715 assume !(1 == ~t9_pc~0); 2420752#L715-2 is_transmit9_triggered_~__retres1~9#1 := 0; 2420382#L726 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 2420087#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 2420088#L1451 assume !(0 != activate_threads_~tmp___8~0#1); 2420729#L1451-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 2421030#L734 assume !(1 == ~t10_pc~0); 2421031#L734-2 is_transmit10_triggered_~__retres1~10#1 := 0; 2420163#L745 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 2420164#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 2420956#L1459 assume !(0 != activate_threads_~tmp___9~0#1); 2420957#L1459-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 2420245#L753 assume 1 == ~t11_pc~0; 2420246#L754 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 2420860#L764 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 2421288#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 2420537#L1467 assume !(0 != activate_threads_~tmp___10~0#1); 2420538#L1467-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2420600#L1237 assume 1 == ~M_E~0;~M_E~0 := 2; 2420601#L1237-2 assume !(1 == ~T1_E~0); 2421430#L1242-1 assume !(1 == ~T2_E~0); 2421431#L1247-1 assume !(1 == ~T3_E~0); 2421214#L1252-1 assume !(1 == ~T4_E~0); 2421215#L1257-1 assume !(1 == ~T5_E~0); 2421053#L1262-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 2421054#L1267-1 assume !(1 == ~T7_E~0); 2421206#L1272-1 assume !(1 == ~T8_E~0); 2421207#L1277-1 assume !(1 == ~T9_E~0); 2420964#L1282-1 assume !(1 == ~T10_E~0); 2420897#L1287-1 assume !(1 == ~T11_E~0); 2420898#L1292-1 assume !(1 == ~E_M~0); 2420849#L1297-1 assume !(1 == ~E_1~0); 2420850#L1302-1 assume 1 == ~E_2~0;~E_2~0 := 2; 2421188#L1307-1 assume !(1 == ~E_3~0); 2421189#L1312-1 assume !(1 == ~E_4~0); 2420484#L1317-1 assume !(1 == ~E_5~0); 2420485#L1322-1 assume !(1 == ~E_6~0); 2420745#L1327-1 assume !(1 == ~E_7~0); 2420807#L1332-1 assume !(1 == ~E_8~0); 2420808#L1337-1 assume !(1 == ~E_9~0); 2420735#L1342-1 assume 1 == ~E_10~0;~E_10~0 := 2; 2420736#L1347-1 assume !(1 == ~E_11~0); 2421186#L1352-1 assume { :end_inline_reset_delta_events } true; 2421187#L1678-2 [2022-12-13 17:14:02,972 INFO L750 eck$LassoCheckResult]: Loop: 2421187#L1678-2 assume !false; 2537148#L1679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2537143#L1084 assume !false; 2537141#L921 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 2536920#L848 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 2536916#L910 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 2536914#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 2536911#L925 assume !(0 != eval_~tmp~0#1); 2536912#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2540431#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2540429#L1109-3 assume 0 == ~M_E~0;~M_E~0 := 1; 2540427#L1109-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2540425#L1114-3 assume !(0 == ~T2_E~0); 2540423#L1119-3 assume !(0 == ~T3_E~0); 2540421#L1124-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2540419#L1129-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2540417#L1134-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 2540415#L1139-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 2540413#L1144-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 2540411#L1149-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 2540409#L1154-3 assume !(0 == ~T10_E~0); 2540406#L1159-3 assume !(0 == ~T11_E~0); 2540404#L1164-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2540402#L1169-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2540399#L1174-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2540397#L1179-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2540394#L1184-3 assume 0 == ~E_4~0;~E_4~0 := 1; 2540393#L1189-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2540390#L1194-3 assume !(0 == ~E_6~0); 2540388#L1199-3 assume !(0 == ~E_7~0); 2540386#L1204-3 assume 0 == ~E_8~0;~E_8~0 := 1; 2540384#L1209-3 assume 0 == ~E_9~0;~E_9~0 := 1; 2540382#L1214-3 assume 0 == ~E_10~0;~E_10~0 := 1; 2540380#L1219-3 assume 0 == ~E_11~0;~E_11~0 := 1; 2540377#L1224-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2540375#L544-39 assume !(1 == ~m_pc~0); 2540373#L544-41 is_master_triggered_~__retres1~0#1 := 0; 2540371#L555-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2540369#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2540367#L1379-39 assume !(0 != activate_threads_~tmp~1#1); 2540364#L1379-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2540362#L563-39 assume 1 == ~t1_pc~0; 2540359#L564-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2540357#L574-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2540355#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2540353#L1387-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2540350#L1387-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2540348#L582-39 assume !(1 == ~t2_pc~0); 2538671#L582-41 is_transmit2_triggered_~__retres1~2#1 := 0; 2540345#L593-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2540342#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2540340#L1395-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2540338#L1395-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2540336#L601-39 assume 1 == ~t3_pc~0; 2540334#L602-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 2540333#L612-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2540240#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2539689#L1403-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2539688#L1403-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2539687#L620-39 assume !(1 == ~t4_pc~0); 2538986#L620-41 is_transmit4_triggered_~__retres1~4#1 := 0; 2538984#L631-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2538982#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2538979#L1411-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 2538976#L1411-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2538973#L639-39 assume !(1 == ~t5_pc~0); 2538969#L639-41 is_transmit5_triggered_~__retres1~5#1 := 0; 2538965#L650-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2538961#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2538957#L1419-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 2538953#L1419-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2538950#L658-39 assume !(1 == ~t6_pc~0); 2538948#L658-41 is_transmit6_triggered_~__retres1~6#1 := 0; 2538944#L669-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2538939#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 2538934#L1427-39 assume !(0 != activate_threads_~tmp___5~0#1); 2538930#L1427-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2538928#L677-39 assume !(1 == ~t7_pc~0); 2537714#L677-41 is_transmit7_triggered_~__retres1~7#1 := 0; 2538927#L688-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2538925#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 2538924#L1435-39 assume !(0 != activate_threads_~tmp___6~0#1); 2538923#L1435-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2538922#L696-39 assume 1 == ~t8_pc~0; 2538920#L697-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 2538918#L707-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2538916#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 2538914#L1443-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 2538912#L1443-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 2538910#L715-39 assume !(1 == ~t9_pc~0); 2467937#L715-41 is_transmit9_triggered_~__retres1~9#1 := 0; 2538906#L726-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 2538904#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 2538902#L1451-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 2538900#L1451-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 2538898#L734-39 assume !(1 == ~t10_pc~0); 2538896#L734-41 is_transmit10_triggered_~__retres1~10#1 := 0; 2538893#L745-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 2538891#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 2538889#L1459-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 2538887#L1459-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 2538885#L753-39 assume 1 == ~t11_pc~0; 2538882#L754-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 2538879#L764-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 2538877#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 2538875#L1467-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 2538871#L1467-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2538869#L1237-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2486365#L1237-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2538866#L1242-3 assume !(1 == ~T2_E~0); 2488169#L1247-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2538862#L1252-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2538860#L1257-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2538859#L1262-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 2538857#L1267-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 2538855#L1272-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 2538853#L1277-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 2538851#L1282-3 assume !(1 == ~T10_E~0); 2511550#L1287-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 2538849#L1292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2538846#L1297-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2538844#L1302-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2538842#L1307-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2538840#L1312-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2538838#L1317-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2538836#L1322-3 assume !(1 == ~E_6~0); 2533940#L1327-3 assume 1 == ~E_7~0;~E_7~0 := 2; 2538834#L1332-3 assume 1 == ~E_8~0;~E_8~0 := 2; 2538832#L1337-3 assume 1 == ~E_9~0;~E_9~0 := 2; 2538830#L1342-3 assume 1 == ~E_10~0;~E_10~0 := 2; 2538828#L1347-3 assume 1 == ~E_11~0;~E_11~0 := 2; 2538826#L1352-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 2538748#L848-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 2538742#L910-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 2538738#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 2538734#L1697 assume !(0 == start_simulation_~tmp~3#1); 2538732#L1697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 2538700#L848-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 2538683#L910-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 2538678#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; 2538675#L1652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2538672#L1659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2538668#stop_simulation_returnLabel#1 start_simulation_#t~ret32#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 2537157#L1710 assume !(0 != start_simulation_~tmp___0~1#1); 2421187#L1678-2 [2022-12-13 17:14:02,972 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 17:14:02,972 INFO L85 PathProgramCache]: Analyzing trace with hash -449855172, now seen corresponding path program 1 times [2022-12-13 17:14:02,972 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 17:14:02,972 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [52493383] [2022-12-13 17:14:02,972 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 17:14:02,973 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 17:14:02,982 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 17:14:03,025 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 17:14:03,025 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 17:14:03,026 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [52493383] [2022-12-13 17:14:03,026 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [52493383] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 17:14:03,026 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 17:14:03,026 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 17:14:03,026 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [258164736] [2022-12-13 17:14:03,026 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 17:14:03,026 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 17:14:03,027 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 17:14:03,027 INFO L85 PathProgramCache]: Analyzing trace with hash -1024401396, now seen corresponding path program 1 times [2022-12-13 17:14:03,027 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 17:14:03,027 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1822432741] [2022-12-13 17:14:03,027 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 17:14:03,027 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 17:14:03,234 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 17:14:03,273 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 17:14:03,274 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 17:14:03,274 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1822432741] [2022-12-13 17:14:03,274 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1822432741] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 17:14:03,274 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 17:14:03,274 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-12-13 17:14:03,274 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1196129298] [2022-12-13 17:14:03,274 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 17:14:03,275 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 17:14:03,275 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 17:14:03,275 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 17:14:03,275 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 17:14:03,275 INFO L87 Difference]: Start difference. First operand 528944 states and 749067 transitions. cyclomatic complexity: 220187 Second operand has 4 states, 4 states have (on average 34.75) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 17:14:06,942 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 17:14:06,942 INFO L93 Difference]: Finished difference Result 1260415 states and 1774360 transitions. [2022-12-13 17:14:06,942 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1260415 states and 1774360 transitions. [2022-12-13 17:14:11,522 INFO L131 ngComponentsAnalysis]: Automaton has 96 accepting balls. 1233936 [2022-12-13 17:14:13,832 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1260415 states to 1260415 states and 1774360 transitions. [2022-12-13 17:14:13,832 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1260415 [2022-12-13 17:14:14,270 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1260415 [2022-12-13 17:14:14,270 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1260415 states and 1774360 transitions. [2022-12-13 17:14:14,762 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 17:14:14,762 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1260415 states and 1774360 transitions. [2022-12-13 17:14:15,263 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1260415 states and 1774360 transitions. [2022-12-13 17:14:22,493 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1260415 to 1007535. [2022-12-13 17:14:22,869 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1007535 states, 1007535 states have (on average 1.4120243961748227) internal successors, (1422664), 1007534 states have internal predecessors, (1422664), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 17:14:25,022 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1007535 states to 1007535 states and 1422664 transitions. [2022-12-13 17:14:25,022 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1007535 states and 1422664 transitions. [2022-12-13 17:14:25,022 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 17:14:25,022 INFO L428 stractBuchiCegarLoop]: Abstraction has 1007535 states and 1422664 transitions. [2022-12-13 17:14:25,023 INFO L335 stractBuchiCegarLoop]: ======== Iteration 23 ============ [2022-12-13 17:14:25,023 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1007535 states and 1422664 transitions. [2022-12-13 17:14:27,232 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 1004736 [2022-12-13 17:14:27,233 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 17:14:27,233 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 17:14:27,235 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 17:14:27,235 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 17:14:27,236 INFO L748 eck$LassoCheckResult]: Stem: 4209273#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 4209274#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 4210100#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4210101#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4209246#L780 assume 1 == ~m_i~0;~m_st~0 := 0; 4209247#L780-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4210690#L785-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4210644#L790-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 4210645#L795-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 4209607#L800-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 4209608#L805-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 4210064#L810-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 4210593#L815-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 4209511#L820-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 4209512#L825-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 4209403#L830-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 4209404#L835-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4210477#L1109 assume !(0 == ~M_E~0); 4210514#L1109-2 assume !(0 == ~T1_E~0); 4209412#L1114-1 assume !(0 == ~T2_E~0); 4209413#L1119-1 assume !(0 == ~T3_E~0); 4210596#L1124-1 assume !(0 == ~T4_E~0); 4209063#L1129-1 assume !(0 == ~T5_E~0); 4209064#L1134-1 assume !(0 == ~T6_E~0); 4209700#L1139-1 assume !(0 == ~T7_E~0); 4210493#L1144-1 assume !(0 == ~T8_E~0); 4210316#L1149-1 assume !(0 == ~T9_E~0); 4209171#L1154-1 assume !(0 == ~T10_E~0); 4209172#L1159-1 assume !(0 == ~T11_E~0); 4210305#L1164-1 assume !(0 == ~E_M~0); 4209566#L1169-1 assume !(0 == ~E_1~0); 4209462#L1174-1 assume !(0 == ~E_2~0); 4209326#L1179-1 assume !(0 == ~E_3~0); 4209252#L1184-1 assume !(0 == ~E_4~0); 4209253#L1189-1 assume !(0 == ~E_5~0); 4209286#L1194-1 assume !(0 == ~E_6~0); 4209367#L1199-1 assume !(0 == ~E_7~0); 4210327#L1204-1 assume !(0 == ~E_8~0); 4210252#L1209-1 assume !(0 == ~E_9~0); 4210253#L1214-1 assume !(0 == ~E_10~0); 4210718#L1219-1 assume !(0 == ~E_11~0); 4210893#L1224-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4209585#L544 assume !(1 == ~m_pc~0); 4209586#L544-2 is_master_triggered_~__retres1~0#1 := 0; 4210568#L555 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4209966#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4209214#L1379 assume !(0 != activate_threads_~tmp~1#1); 4209215#L1379-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4210048#L563 assume !(1 == ~t1_pc~0); 4209822#L563-2 is_transmit1_triggered_~__retres1~1#1 := 0; 4209073#L574 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4209074#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4210193#L1387 assume !(0 != activate_threads_~tmp___0~0#1); 4209069#L1387-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4209070#L582 assume !(1 == ~t2_pc~0); 4209799#L582-2 is_transmit2_triggered_~__retres1~2#1 := 0; 4210198#L593 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4209408#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4209409#L1395 assume !(0 != activate_threads_~tmp___1~0#1); 4209099#L1395-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4209100#L601 assume !(1 == ~t3_pc~0); 4209817#L601-2 is_transmit3_triggered_~__retres1~3#1 := 0; 4209816#L612 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4210352#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4210234#L1403 assume !(0 != activate_threads_~tmp___2~0#1); 4210235#L1403-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4210170#L620 assume !(1 == ~t4_pc~0); 4210171#L620-2 is_transmit4_triggered_~__retres1~4#1 := 0; 4209725#L631 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4209113#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4209114#L1411 assume !(0 != activate_threads_~tmp___3~0#1); 4210059#L1411-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4210276#L639 assume !(1 == ~t5_pc~0); 4210277#L639-2 is_transmit5_triggered_~__retres1~5#1 := 0; 4209374#L650 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4209375#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4210084#L1419 assume !(0 != activate_threads_~tmp___4~0#1); 4210085#L1419-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4210001#L658 assume !(1 == ~t6_pc~0); 4209581#L658-2 is_transmit6_triggered_~__retres1~6#1 := 0; 4209582#L669 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4210938#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4210897#L1427 assume !(0 != activate_threads_~tmp___5~0#1); 4210238#L1427-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4209423#L677 assume !(1 == ~t7_pc~0); 4209319#L677-2 is_transmit7_triggered_~__retres1~7#1 := 0; 4209320#L688 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4210435#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 4210634#L1435 assume !(0 != activate_threads_~tmp___6~0#1); 4210635#L1435-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4210751#L696 assume !(1 == ~t8_pc~0); 4209646#L696-2 is_transmit8_triggered_~__retres1~8#1 := 0; 4209647#L707 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4210688#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 4210755#L1443 assume !(0 != activate_threads_~tmp___7~0#1); 4210835#L1443-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4210129#L715 assume !(1 == ~t9_pc~0); 4210130#L715-2 is_transmit9_triggered_~__retres1~9#1 := 0; 4209756#L726 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 4209460#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 4209461#L1451 assume !(0 != activate_threads_~tmp___8~0#1); 4210109#L1451-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 4210432#L734 assume !(1 == ~t10_pc~0); 4210433#L734-2 is_transmit10_triggered_~__retres1~10#1 := 0; 4209538#L745 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 4209539#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 4210354#L1459 assume !(0 != activate_threads_~tmp___9~0#1); 4210355#L1459-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 4209621#L753 assume !(1 == ~t11_pc~0); 4209622#L753-2 is_transmit11_triggered_~__retres1~11#1 := 0; 4210631#L764 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 4210708#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 4209911#L1467 assume !(0 != activate_threads_~tmp___10~0#1); 4209912#L1467-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4209974#L1237 assume 1 == ~M_E~0;~M_E~0 := 2; 4209975#L1237-2 assume !(1 == ~T1_E~0); 4210865#L1242-1 assume !(1 == ~T2_E~0); 4210866#L1247-1 assume !(1 == ~T3_E~0); 4210629#L1252-1 assume !(1 == ~T4_E~0); 4210630#L1257-1 assume !(1 == ~T5_E~0); 4210461#L1262-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 4210462#L1267-1 assume !(1 == ~T7_E~0); 4210621#L1272-1 assume !(1 == ~T8_E~0); 4209811#L1277-1 assume !(1 == ~T9_E~0); 4209812#L1282-1 assume !(1 == ~T10_E~0); 4210363#L1287-1 assume !(1 == ~T11_E~0); 4344442#L1292-1 assume !(1 == ~E_M~0); 4344441#L1297-1 assume !(1 == ~E_1~0); 4344440#L1302-1 assume 1 == ~E_2~0;~E_2~0 := 2; 4344439#L1307-1 assume !(1 == ~E_3~0); 4344438#L1312-1 assume !(1 == ~E_4~0); 4344437#L1317-1 assume !(1 == ~E_5~0); 4344436#L1322-1 assume !(1 == ~E_6~0); 4327692#L1327-1 assume !(1 == ~E_7~0); 4344435#L1332-1 assume !(1 == ~E_8~0); 4344434#L1337-1 assume !(1 == ~E_9~0); 4344433#L1342-1 assume 1 == ~E_10~0;~E_10~0 := 2; 4344432#L1347-1 assume !(1 == ~E_11~0); 4344431#L1352-1 assume { :end_inline_reset_delta_events } true; 4344428#L1678-2 [2022-12-13 17:14:27,236 INFO L750 eck$LassoCheckResult]: Loop: 4344428#L1678-2 assume !false; 4344426#L1679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4320433#L1084 assume !false; 4344422#L921 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 4344400#L848 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 4344396#L910 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 4344394#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 4344391#L925 assume !(0 != eval_~tmp~0#1); 4344392#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4425905#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4425903#L1109-3 assume 0 == ~M_E~0;~M_E~0 := 1; 4425901#L1109-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4425899#L1114-3 assume !(0 == ~T2_E~0); 4425897#L1119-3 assume !(0 == ~T3_E~0); 4425894#L1124-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4425892#L1129-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 4425890#L1134-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 4425888#L1139-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 4425886#L1144-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 4425884#L1149-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 4425883#L1154-3 assume !(0 == ~T10_E~0); 4425881#L1159-3 assume !(0 == ~T11_E~0); 4425879#L1164-3 assume 0 == ~E_M~0;~E_M~0 := 1; 4425877#L1169-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4425875#L1174-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4425874#L1179-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4425873#L1184-3 assume 0 == ~E_4~0;~E_4~0 := 1; 4425869#L1189-3 assume 0 == ~E_5~0;~E_5~0 := 1; 4425867#L1194-3 assume !(0 == ~E_6~0); 4425865#L1199-3 assume !(0 == ~E_7~0); 4425864#L1204-3 assume 0 == ~E_8~0;~E_8~0 := 1; 4425863#L1209-3 assume 0 == ~E_9~0;~E_9~0 := 1; 4425862#L1214-3 assume 0 == ~E_10~0;~E_10~0 := 1; 4425861#L1219-3 assume 0 == ~E_11~0;~E_11~0 := 1; 4425860#L1224-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4425859#L544-39 assume !(1 == ~m_pc~0); 4425858#L544-41 is_master_triggered_~__retres1~0#1 := 0; 4425857#L555-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4425856#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4425855#L1379-39 assume !(0 != activate_threads_~tmp~1#1); 4425854#L1379-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4425853#L563-39 assume 1 == ~t1_pc~0; 4425851#L564-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4425850#L574-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4425849#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4425848#L1387-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4425847#L1387-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4425846#L582-39 assume !(1 == ~t2_pc~0); 4388414#L582-41 is_transmit2_triggered_~__retres1~2#1 := 0; 4425844#L593-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4425843#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4425842#L1395-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4425841#L1395-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4425840#L601-39 assume !(1 == ~t3_pc~0); 4425838#L601-41 is_transmit3_triggered_~__retres1~3#1 := 0; 4425835#L612-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4425833#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4425831#L1403-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4425829#L1403-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4425827#L620-39 assume !(1 == ~t4_pc~0); 4425825#L620-41 is_transmit4_triggered_~__retres1~4#1 := 0; 4425823#L631-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4425821#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4425819#L1411-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 4425817#L1411-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4425815#L639-39 assume !(1 == ~t5_pc~0); 4425813#L639-41 is_transmit5_triggered_~__retres1~5#1 := 0; 4425811#L650-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4425809#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4425807#L1419-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 4425805#L1419-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4425803#L658-39 assume !(1 == ~t6_pc~0); 4425799#L658-41 is_transmit6_triggered_~__retres1~6#1 := 0; 4425797#L669-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4425795#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4425793#L1427-39 assume !(0 != activate_threads_~tmp___5~0#1); 4425790#L1427-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4425788#L677-39 assume !(1 == ~t7_pc~0); 4413359#L677-41 is_transmit7_triggered_~__retres1~7#1 := 0; 4425785#L688-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4425783#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 4425781#L1435-39 assume !(0 != activate_threads_~tmp___6~0#1); 4425779#L1435-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4425777#L696-39 assume !(1 == ~t8_pc~0); 4425775#L696-41 is_transmit8_triggered_~__retres1~8#1 := 0; 4425772#L707-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4425770#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 4425767#L1443-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 4425765#L1443-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4345014#L715-39 assume !(1 == ~t9_pc~0); 4345011#L715-41 is_transmit9_triggered_~__retres1~9#1 := 0; 4345009#L726-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 4345007#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 4345005#L1451-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 4345003#L1451-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 4345001#L734-39 assume !(1 == ~t10_pc~0); 4344998#L734-41 is_transmit10_triggered_~__retres1~10#1 := 0; 4344995#L745-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 4344993#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 4344991#L1459-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 4344989#L1459-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 4344987#L753-39 assume !(1 == ~t11_pc~0); 4297182#L753-41 is_transmit11_triggered_~__retres1~11#1 := 0; 4344983#L764-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 4344981#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 4344979#L1467-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 4344977#L1467-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4344975#L1237-3 assume 1 == ~M_E~0;~M_E~0 := 2; 4327917#L1237-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4344834#L1242-3 assume !(1 == ~T2_E~0); 4344833#L1247-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4344832#L1252-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4344831#L1257-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 4344830#L1262-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 4344829#L1267-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 4344828#L1272-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 4344827#L1277-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 4344727#L1282-3 assume !(1 == ~T10_E~0); 4344723#L1287-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 4344721#L1292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 4344719#L1297-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4344718#L1302-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4344717#L1307-3 assume 1 == ~E_3~0;~E_3~0 := 2; 4344716#L1312-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4344715#L1317-3 assume 1 == ~E_5~0;~E_5~0 := 2; 4344714#L1322-3 assume !(1 == ~E_6~0); 4327883#L1327-3 assume 1 == ~E_7~0;~E_7~0 := 2; 4344713#L1332-3 assume 1 == ~E_8~0;~E_8~0 := 2; 4344712#L1337-3 assume 1 == ~E_9~0;~E_9~0 := 2; 4344711#L1342-3 assume 1 == ~E_10~0;~E_10~0 := 2; 4344710#L1347-3 assume 1 == ~E_11~0;~E_11~0 := 2; 4344709#L1352-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 4344690#L848-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 4344685#L910-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 4344683#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 4344470#L1697 assume !(0 == start_simulation_~tmp~3#1); 4344468#L1697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 4344457#L848-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 4344447#L910-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 4344446#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; 4344445#L1652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4344444#L1659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4344443#stop_simulation_returnLabel#1 start_simulation_#t~ret32#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 4344430#L1710 assume !(0 != start_simulation_~tmp___0~1#1); 4344428#L1678-2 [2022-12-13 17:14:27,236 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 17:14:27,236 INFO L85 PathProgramCache]: Analyzing trace with hash 2073641149, now seen corresponding path program 1 times [2022-12-13 17:14:27,236 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 17:14:27,237 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1316880238] [2022-12-13 17:14:27,237 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 17:14:27,237 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 17:14:27,246 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 17:14:27,274 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 17:14:27,274 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 17:14:27,274 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1316880238] [2022-12-13 17:14:27,274 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1316880238] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 17:14:27,274 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 17:14:27,274 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-12-13 17:14:27,274 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1874147908] [2022-12-13 17:14:27,274 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 17:14:27,274 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 17:14:27,275 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 17:14:27,275 INFO L85 PathProgramCache]: Analyzing trace with hash 741813711, now seen corresponding path program 1 times [2022-12-13 17:14:27,275 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 17:14:27,275 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [610678652] [2022-12-13 17:14:27,275 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 17:14:27,275 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 17:14:27,282 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 17:14:27,309 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 17:14:27,309 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 17:14:27,309 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [610678652] [2022-12-13 17:14:27,309 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [610678652] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 17:14:27,309 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 17:14:27,310 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-12-13 17:14:27,310 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1567223124] [2022-12-13 17:14:27,310 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 17:14:27,310 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 17:14:27,310 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 17:14:27,310 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 17:14:27,310 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 17:14:27,310 INFO L87 Difference]: Start difference. First operand 1007535 states and 1422664 transitions. cyclomatic complexity: 415193 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 2 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 17:14:30,332 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 17:14:30,332 INFO L93 Difference]: Finished difference Result 1137501 states and 1606499 transitions. [2022-12-13 17:14:30,333 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1137501 states and 1606499 transitions. [2022-12-13 17:14:34,315 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 1134400