./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/token_ring.12.cil-1.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 2329fc70 Calling Ultimate with: /usr/lib/jvm/java-11-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c26e6e04-e396-41a9-81e6-bff65d3f5bfe/bin/uautomizer-uyxdKDjOR8/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c26e6e04-e396-41a9-81e6-bff65d3f5bfe/bin/uautomizer-uyxdKDjOR8/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c26e6e04-e396-41a9-81e6-bff65d3f5bfe/bin/uautomizer-uyxdKDjOR8/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c26e6e04-e396-41a9-81e6-bff65d3f5bfe/bin/uautomizer-uyxdKDjOR8/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/token_ring.12.cil-1.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c26e6e04-e396-41a9-81e6-bff65d3f5bfe/bin/uautomizer-uyxdKDjOR8/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c26e6e04-e396-41a9-81e6-bff65d3f5bfe/bin/uautomizer-uyxdKDjOR8 --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 962623ba1d780e7ad35b9b6d7f5839750bc2f361556d46080824a3701cf71595 --- Real Ultimate output --- [0.001s][warning][os,container] Duplicate cpuset controllers detected. Picking /sys/fs/cgroup/cpuset, skipping /sys/fs/cgroup/cpuset. This is Ultimate 0.2.2-dev-2329fc7 [2022-12-13 13:22:02,660 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-12-13 13:22:02,662 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-12-13 13:22:02,674 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-12-13 13:22:02,674 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-12-13 13:22:02,675 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-12-13 13:22:02,675 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-12-13 13:22:02,676 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-12-13 13:22:02,677 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-12-13 13:22:02,678 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-12-13 13:22:02,678 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-12-13 13:22:02,679 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-12-13 13:22:02,679 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-12-13 13:22:02,680 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-12-13 13:22:02,681 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-12-13 13:22:02,681 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-12-13 13:22:02,682 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-12-13 13:22:02,682 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-12-13 13:22:02,683 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-12-13 13:22:02,684 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-12-13 13:22:02,685 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-12-13 13:22:02,686 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-12-13 13:22:02,687 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-12-13 13:22:02,687 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-12-13 13:22:02,689 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-12-13 13:22:02,689 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-12-13 13:22:02,689 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-12-13 13:22:02,690 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-12-13 13:22:02,690 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-12-13 13:22:02,691 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-12-13 13:22:02,691 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-12-13 13:22:02,691 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-12-13 13:22:02,692 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-12-13 13:22:02,692 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-12-13 13:22:02,693 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-12-13 13:22:02,693 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-12-13 13:22:02,693 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-12-13 13:22:02,693 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-12-13 13:22:02,693 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-12-13 13:22:02,694 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-12-13 13:22:02,694 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-12-13 13:22:02,695 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c26e6e04-e396-41a9-81e6-bff65d3f5bfe/bin/uautomizer-uyxdKDjOR8/config/svcomp-Termination-32bit-Automizer_Default.epf [2022-12-13 13:22:02,719 INFO L113 SettingsManager]: Loading preferences was successful [2022-12-13 13:22:02,723 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-12-13 13:22:02,723 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-12-13 13:22:02,724 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-12-13 13:22:02,724 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-12-13 13:22:02,725 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-12-13 13:22:02,725 INFO L138 SettingsManager]: * Use SBE=true [2022-12-13 13:22:02,725 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2022-12-13 13:22:02,725 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2022-12-13 13:22:02,725 INFO L138 SettingsManager]: * Use old map elimination=false [2022-12-13 13:22:02,725 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2022-12-13 13:22:02,725 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2022-12-13 13:22:02,725 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2022-12-13 13:22:02,725 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-12-13 13:22:02,725 INFO L138 SettingsManager]: * sizeof long=4 [2022-12-13 13:22:02,726 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2022-12-13 13:22:02,726 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-12-13 13:22:02,726 INFO L138 SettingsManager]: * sizeof POINTER=4 [2022-12-13 13:22:02,726 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-12-13 13:22:02,726 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2022-12-13 13:22:02,726 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2022-12-13 13:22:02,726 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2022-12-13 13:22:02,726 INFO L138 SettingsManager]: * sizeof long double=12 [2022-12-13 13:22:02,726 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-12-13 13:22:02,726 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2022-12-13 13:22:02,726 INFO L138 SettingsManager]: * Use constant arrays=true [2022-12-13 13:22:02,726 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2022-12-13 13:22:02,727 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-12-13 13:22:02,727 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-12-13 13:22:02,727 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-12-13 13:22:02,727 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-12-13 13:22:02,728 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-12-13 13:22:02,728 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c26e6e04-e396-41a9-81e6-bff65d3f5bfe/bin/uautomizer-uyxdKDjOR8/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c26e6e04-e396-41a9-81e6-bff65d3f5bfe/bin/uautomizer-uyxdKDjOR8 Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 962623ba1d780e7ad35b9b6d7f5839750bc2f361556d46080824a3701cf71595 [2022-12-13 13:22:02,913 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-12-13 13:22:02,933 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-12-13 13:22:02,935 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-12-13 13:22:02,936 INFO L271 PluginConnector]: Initializing CDTParser... [2022-12-13 13:22:02,936 INFO L275 PluginConnector]: CDTParser initialized [2022-12-13 13:22:02,937 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c26e6e04-e396-41a9-81e6-bff65d3f5bfe/bin/uautomizer-uyxdKDjOR8/../../sv-benchmarks/c/systemc/token_ring.12.cil-1.c [2022-12-13 13:22:05,555 INFO L500 CDTParser]: Created temporary CDT project at NULL [2022-12-13 13:22:05,754 INFO L351 CDTParser]: Found 1 translation units. [2022-12-13 13:22:05,754 INFO L172 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c26e6e04-e396-41a9-81e6-bff65d3f5bfe/sv-benchmarks/c/systemc/token_ring.12.cil-1.c [2022-12-13 13:22:05,766 INFO L394 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c26e6e04-e396-41a9-81e6-bff65d3f5bfe/bin/uautomizer-uyxdKDjOR8/data/173b5e3ad/cc78129598944571806172cbac5e87cb/FLAG55e166174 [2022-12-13 13:22:05,778 INFO L402 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c26e6e04-e396-41a9-81e6-bff65d3f5bfe/bin/uautomizer-uyxdKDjOR8/data/173b5e3ad/cc78129598944571806172cbac5e87cb [2022-12-13 13:22:05,781 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-12-13 13:22:05,782 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-12-13 13:22:05,783 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-12-13 13:22:05,783 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-12-13 13:22:05,786 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-12-13 13:22:05,787 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.12 01:22:05" (1/1) ... [2022-12-13 13:22:05,788 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@7512de5b and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 01:22:05, skipping insertion in model container [2022-12-13 13:22:05,788 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.12 01:22:05" (1/1) ... [2022-12-13 13:22:05,793 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-12-13 13:22:05,846 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-12-13 13:22:05,964 WARN L237 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c26e6e04-e396-41a9-81e6-bff65d3f5bfe/sv-benchmarks/c/systemc/token_ring.12.cil-1.c[671,684] [2022-12-13 13:22:06,047 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-12-13 13:22:06,058 INFO L203 MainTranslator]: Completed pre-run [2022-12-13 13:22:06,066 WARN L237 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c26e6e04-e396-41a9-81e6-bff65d3f5bfe/sv-benchmarks/c/systemc/token_ring.12.cil-1.c[671,684] [2022-12-13 13:22:06,110 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-12-13 13:22:06,123 INFO L208 MainTranslator]: Completed translation [2022-12-13 13:22:06,123 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 01:22:06 WrapperNode [2022-12-13 13:22:06,124 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-12-13 13:22:06,124 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-12-13 13:22:06,124 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-12-13 13:22:06,124 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-12-13 13:22:06,130 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 01:22:06" (1/1) ... [2022-12-13 13:22:06,141 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 01:22:06" (1/1) ... [2022-12-13 13:22:06,217 INFO L138 Inliner]: procedures = 52, calls = 68, calls flagged for inlining = 63, calls inlined = 270, statements flattened = 4146 [2022-12-13 13:22:06,218 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-12-13 13:22:06,218 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-12-13 13:22:06,219 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-12-13 13:22:06,219 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-12-13 13:22:06,228 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 01:22:06" (1/1) ... [2022-12-13 13:22:06,228 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 01:22:06" (1/1) ... [2022-12-13 13:22:06,237 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 01:22:06" (1/1) ... [2022-12-13 13:22:06,237 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 01:22:06" (1/1) ... [2022-12-13 13:22:06,268 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 01:22:06" (1/1) ... [2022-12-13 13:22:06,298 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 01:22:06" (1/1) ... [2022-12-13 13:22:06,304 INFO L185 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 01:22:06" (1/1) ... [2022-12-13 13:22:06,311 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 01:22:06" (1/1) ... [2022-12-13 13:22:06,323 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-12-13 13:22:06,324 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-12-13 13:22:06,324 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-12-13 13:22:06,324 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-12-13 13:22:06,325 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 01:22:06" (1/1) ... [2022-12-13 13:22:06,331 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-12-13 13:22:06,341 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c26e6e04-e396-41a9-81e6-bff65d3f5bfe/bin/uautomizer-uyxdKDjOR8/z3 [2022-12-13 13:22:06,352 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c26e6e04-e396-41a9-81e6-bff65d3f5bfe/bin/uautomizer-uyxdKDjOR8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-12-13 13:22:06,354 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c26e6e04-e396-41a9-81e6-bff65d3f5bfe/bin/uautomizer-uyxdKDjOR8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2022-12-13 13:22:06,389 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-12-13 13:22:06,389 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-12-13 13:22:06,389 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-12-13 13:22:06,389 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-12-13 13:22:06,478 INFO L235 CfgBuilder]: Building ICFG [2022-12-13 13:22:06,480 INFO L261 CfgBuilder]: Building CFG for each procedure with an implementation [2022-12-13 13:22:08,005 INFO L276 CfgBuilder]: Performing block encoding [2022-12-13 13:22:08,017 INFO L295 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-12-13 13:22:08,017 INFO L300 CfgBuilder]: Removed 15 assume(true) statements. [2022-12-13 13:22:08,020 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.12 01:22:08 BoogieIcfgContainer [2022-12-13 13:22:08,020 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-12-13 13:22:08,020 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2022-12-13 13:22:08,020 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2022-12-13 13:22:08,023 INFO L275 PluginConnector]: BuchiAutomizer initialized [2022-12-13 13:22:08,023 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-12-13 13:22:08,024 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 13.12 01:22:05" (1/3) ... [2022-12-13 13:22:08,024 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@247a1bd3 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 13.12 01:22:08, skipping insertion in model container [2022-12-13 13:22:08,024 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-12-13 13:22:08,025 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 01:22:06" (2/3) ... [2022-12-13 13:22:08,025 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@247a1bd3 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 13.12 01:22:08, skipping insertion in model container [2022-12-13 13:22:08,025 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-12-13 13:22:08,025 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.12 01:22:08" (3/3) ... [2022-12-13 13:22:08,026 INFO L332 chiAutomizerObserver]: Analyzing ICFG token_ring.12.cil-1.c [2022-12-13 13:22:08,081 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2022-12-13 13:22:08,081 INFO L304 stractBuchiCegarLoop]: Hoare is false [2022-12-13 13:22:08,081 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2022-12-13 13:22:08,081 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2022-12-13 13:22:08,081 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2022-12-13 13:22:08,082 INFO L308 stractBuchiCegarLoop]: Difference is false [2022-12-13 13:22:08,082 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2022-12-13 13:22:08,082 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2022-12-13 13:22:08,090 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1798 states, 1797 states have (on average 1.4997217584863662) internal successors, (2695), 1797 states have internal predecessors, (2695), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 13:22:08,130 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1631 [2022-12-13 13:22:08,130 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 13:22:08,131 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 13:22:08,140 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 13:22:08,140 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 13:22:08,140 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2022-12-13 13:22:08,143 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1798 states, 1797 states have (on average 1.4997217584863662) internal successors, (2695), 1797 states have internal predecessors, (2695), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 13:22:08,153 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1631 [2022-12-13 13:22:08,153 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 13:22:08,153 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 13:22:08,156 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 13:22:08,156 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 13:22:08,162 INFO L748 eck$LassoCheckResult]: Stem: 113#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 1722#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 668#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1720#update_channels_returnLabel#1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1162#L853true assume !(1 == ~m_i~0);~m_st~0 := 2; 964#L853-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 258#L858-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 2#L863-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 745#L868-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 870#L873-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 1647#L878-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 1611#L883-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 1682#L888-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 379#L893-1true assume 1 == ~t9_i~0;~t9_st~0 := 0; 774#L898-1true assume !(1 == ~t10_i~0);~t10_st~0 := 2; 1789#L903-1true assume !(1 == ~t11_i~0);~t11_st~0 := 2; 707#L908-1true assume !(1 == ~t12_i~0);~t12_st~0 := 2; 1391#L913-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 833#L1206true assume !(0 == ~M_E~0); 369#L1206-2true assume 0 == ~T1_E~0;~T1_E~0 := 1; 1154#L1211-1true assume !(0 == ~T2_E~0); 1324#L1216-1true assume !(0 == ~T3_E~0); 246#L1221-1true assume !(0 == ~T4_E~0); 1243#L1226-1true assume !(0 == ~T5_E~0); 83#L1231-1true assume !(0 == ~T6_E~0); 1398#L1236-1true assume !(0 == ~T7_E~0); 1228#L1241-1true assume !(0 == ~T8_E~0); 285#L1246-1true assume 0 == ~T9_E~0;~T9_E~0 := 1; 408#L1251-1true assume !(0 == ~T10_E~0); 910#L1256-1true assume !(0 == ~T11_E~0); 6#L1261-1true assume !(0 == ~T12_E~0); 1622#L1266-1true assume !(0 == ~E_M~0); 1562#L1271-1true assume !(0 == ~E_1~0); 860#L1276-1true assume !(0 == ~E_2~0); 1553#L1281-1true assume !(0 == ~E_3~0); 795#L1286-1true assume 0 == ~E_4~0;~E_4~0 := 1; 197#L1291-1true assume !(0 == ~E_5~0); 1645#L1296-1true assume !(0 == ~E_6~0); 636#L1301-1true assume !(0 == ~E_7~0); 1095#L1306-1true assume !(0 == ~E_8~0); 1057#L1311-1true assume !(0 == ~E_9~0); 179#L1316-1true assume !(0 == ~E_10~0); 1482#L1321-1true assume !(0 == ~E_11~0); 648#L1326-1true assume 0 == ~E_12~0;~E_12~0 := 1; 108#L1331-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1784#L598true assume 1 == ~m_pc~0; 131#L599true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1195#L609true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 560#is_master_triggered_returnLabel#1true activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1419#L1497true assume !(0 != activate_threads_~tmp~1#1); 1683#L1497-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1283#L617true assume !(1 == ~t1_pc~0); 296#L617-2true is_transmit1_triggered_~__retres1~1#1 := 0; 1728#L628true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 937#is_transmit1_triggered_returnLabel#1true activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1468#L1505true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 717#L1505-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1315#L636true assume 1 == ~t2_pc~0; 280#L637true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 544#L647true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 189#is_transmit2_triggered_returnLabel#1true activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1457#L1513true assume !(0 != activate_threads_~tmp___1~0#1); 744#L1513-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 480#L655true assume !(1 == ~t3_pc~0); 1428#L655-2true is_transmit3_triggered_~__retres1~3#1 := 0; 1704#L666true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 927#is_transmit3_triggered_returnLabel#1true activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1791#L1521true assume !(0 != activate_threads_~tmp___2~0#1); 1564#L1521-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1593#L674true assume 1 == ~t4_pc~0; 44#L675true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1656#L685true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 55#is_transmit4_triggered_returnLabel#1true activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 190#L1529true assume !(0 != activate_threads_~tmp___3~0#1); 479#L1529-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1336#L693true assume !(1 == ~t5_pc~0); 599#L693-2true is_transmit5_triggered_~__retres1~5#1 := 0; 370#L704true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1471#is_transmit5_triggered_returnLabel#1true activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1062#L1537true assume !(0 != activate_threads_~tmp___4~0#1); 416#L1537-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 381#L712true assume 1 == ~t6_pc~0; 887#L713true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 671#L723true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 184#is_transmit6_triggered_returnLabel#1true activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1665#L1545true assume !(0 != activate_threads_~tmp___5~0#1); 761#L1545-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 754#L731true assume 1 == ~t7_pc~0; 109#L732true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 212#L742true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1742#is_transmit7_triggered_returnLabel#1true activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1071#L1553true assume !(0 != activate_threads_~tmp___6~0#1); 980#L1553-2true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 163#L750true assume !(1 == ~t8_pc~0); 848#L750-2true is_transmit8_triggered_~__retres1~8#1 := 0; 264#L761true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1405#is_transmit8_triggered_returnLabel#1true activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1082#L1561true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 340#L1561-2true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 715#L769true assume 1 == ~t9_pc~0; 1729#L770true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 92#L780true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 205#is_transmit9_triggered_returnLabel#1true activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 906#L1569true assume !(0 != activate_threads_~tmp___8~0#1); 1352#L1569-2true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1004#L788true assume !(1 == ~t10_pc~0); 611#L788-2true is_transmit10_triggered_~__retres1~10#1 := 0; 1230#L799true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1207#is_transmit10_triggered_returnLabel#1true activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1119#L1577true assume !(0 != activate_threads_~tmp___9~0#1); 161#L1577-2true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1009#L807true assume 1 == ~t11_pc~0; 1208#L808true assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 746#L818true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1321#is_transmit11_triggered_returnLabel#1true activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1798#L1585true assume !(0 != activate_threads_~tmp___10~0#1); 1785#L1585-2true assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 1169#L826true assume !(1 == ~t12_pc~0); 382#L826-2true is_transmit12_triggered_~__retres1~12#1 := 0; 769#L837true is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 34#is_transmit12_triggered_returnLabel#1true activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 1356#L1593true assume !(0 != activate_threads_~tmp___11~0#1); 475#L1593-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 421#L1344true assume !(1 == ~M_E~0); 506#L1344-2true assume !(1 == ~T1_E~0); 1746#L1349-1true assume 1 == ~T2_E~0;~T2_E~0 := 2; 641#L1354-1true assume !(1 == ~T3_E~0); 992#L1359-1true assume !(1 == ~T4_E~0); 1586#L1364-1true assume !(1 == ~T5_E~0); 220#L1369-1true assume !(1 == ~T6_E~0); 967#L1374-1true assume !(1 == ~T7_E~0); 647#L1379-1true assume !(1 == ~T8_E~0); 705#L1384-1true assume !(1 == ~T9_E~0); 1771#L1389-1true assume 1 == ~T10_E~0;~T10_E~0 := 2; 1235#L1394-1true assume !(1 == ~T11_E~0); 1666#L1399-1true assume !(1 == ~T12_E~0); 1458#L1404-1true assume !(1 == ~E_M~0); 287#L1409-1true assume !(1 == ~E_1~0); 1416#L1414-1true assume !(1 == ~E_2~0); 888#L1419-1true assume !(1 == ~E_3~0); 99#L1424-1true assume !(1 == ~E_4~0); 652#L1429-1true assume 1 == ~E_5~0;~E_5~0 := 2; 1260#L1434-1true assume !(1 == ~E_6~0); 1650#L1439-1true assume !(1 == ~E_7~0); 117#L1444-1true assume !(1 == ~E_8~0); 842#L1449-1true assume !(1 == ~E_9~0); 343#L1454-1true assume !(1 == ~E_10~0); 1317#L1459-1true assume !(1 == ~E_11~0); 730#L1464-1true assume !(1 == ~E_12~0); 775#L1469-1true assume { :end_inline_reset_delta_events } true; 1517#L1815-2true [2022-12-13 13:22:08,164 INFO L750 eck$LassoCheckResult]: Loop: 1517#L1815-2true assume !false; 908#L1816true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 675#L1181true assume false; 514#eval_returnLabel#1true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 291#update_channels_returnLabel#2true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1646#L1206-3true assume 0 == ~M_E~0;~M_E~0 := 1; 1663#L1206-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 729#L1211-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 154#L1216-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 489#L1221-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 1014#L1226-3true assume !(0 == ~T5_E~0); 192#L1231-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 366#L1236-3true assume 0 == ~T7_E~0;~T7_E~0 := 1; 1786#L1241-3true assume 0 == ~T8_E~0;~T8_E~0 := 1; 1350#L1246-3true assume 0 == ~T9_E~0;~T9_E~0 := 1; 1139#L1251-3true assume 0 == ~T10_E~0;~T10_E~0 := 1; 820#L1256-3true assume 0 == ~T11_E~0;~T11_E~0 := 1; 166#L1261-3true assume 0 == ~T12_E~0;~T12_E~0 := 1; 530#L1266-3true assume !(0 == ~E_M~0); 191#L1271-3true assume 0 == ~E_1~0;~E_1~0 := 1; 505#L1276-3true assume 0 == ~E_2~0;~E_2~0 := 1; 454#L1281-3true assume 0 == ~E_3~0;~E_3~0 := 1; 1204#L1286-3true assume 0 == ~E_4~0;~E_4~0 := 1; 883#L1291-3true assume 0 == ~E_5~0;~E_5~0 := 1; 1659#L1296-3true assume 0 == ~E_6~0;~E_6~0 := 1; 1580#L1301-3true assume 0 == ~E_7~0;~E_7~0 := 1; 1437#L1306-3true assume !(0 == ~E_8~0); 539#L1311-3true assume 0 == ~E_9~0;~E_9~0 := 1; 125#L1316-3true assume 0 == ~E_10~0;~E_10~0 := 1; 167#L1321-3true assume 0 == ~E_11~0;~E_11~0 := 1; 619#L1326-3true assume 0 == ~E_12~0;~E_12~0 := 1; 1409#L1331-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 894#L598-42true assume 1 == ~m_pc~0; 1334#L599-14true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1180#L609-14true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 383#is_master_triggered_returnLabel#15true activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1438#L1497-42true assume !(0 != activate_threads_~tmp~1#1); 1703#L1497-44true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 658#L617-42true assume 1 == ~t1_pc~0; 485#L618-14true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 406#L628-14true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1661#is_transmit1_triggered_returnLabel#15true activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1429#L1505-42true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 243#L1505-44true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1414#L636-42true assume !(1 == ~t2_pc~0); 513#L636-44true is_transmit2_triggered_~__retres1~2#1 := 0; 1743#L647-14true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 578#is_transmit2_triggered_returnLabel#15true activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1081#L1513-42true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 988#L1513-44true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 844#L655-42true assume !(1 == ~t3_pc~0); 497#L655-44true is_transmit3_triggered_~__retres1~3#1 := 0; 1046#L666-14true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 920#is_transmit3_triggered_returnLabel#15true activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1758#L1521-42true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1202#L1521-44true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1092#L674-42true assume !(1 == ~t4_pc~0); 828#L674-44true is_transmit4_triggered_~__retres1~4#1 := 0; 762#L685-14true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 975#is_transmit4_triggered_returnLabel#15true activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 953#L1529-42true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 598#L1529-44true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1185#L693-42true assume !(1 == ~t5_pc~0); 1510#L693-44true is_transmit5_triggered_~__retres1~5#1 := 0; 866#L704-14true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 638#is_transmit5_triggered_returnLabel#15true activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 862#L1537-42true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1142#L1537-44true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 349#L712-42true assume !(1 == ~t6_pc~0); 1590#L712-44true is_transmit6_triggered_~__retres1~6#1 := 0; 982#L723-14true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 162#is_transmit6_triggered_returnLabel#15true activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1790#L1545-42true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 411#L1545-44true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1367#L731-42true assume !(1 == ~t7_pc~0); 240#L731-44true is_transmit7_triggered_~__retres1~7#1 := 0; 1370#L742-14true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 655#is_transmit7_triggered_returnLabel#15true activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 360#L1553-42true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1043#L1553-44true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 195#L750-42true assume 1 == ~t8_pc~0; 527#L751-14true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 1559#L761-14true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 770#is_transmit8_triggered_returnLabel#15true activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 132#L1561-42true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1693#L1561-44true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 597#L769-42true assume !(1 == ~t9_pc~0); 588#L769-44true is_transmit9_triggered_~__retres1~9#1 := 0; 1098#L780-14true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1675#is_transmit9_triggered_returnLabel#15true activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1595#L1569-42true assume !(0 != activate_threads_~tmp___8~0#1); 244#L1569-44true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 605#L788-42true assume 1 == ~t10_pc~0; 784#L789-14true assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 1696#L799-14true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 759#is_transmit10_triggered_returnLabel#15true activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1669#L1577-42true assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1624#L1577-44true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1538#L807-42true assume 1 == ~t11_pc~0; 902#L808-14true assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 529#L818-14true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1378#is_transmit11_triggered_returnLabel#15true activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 111#L1585-42true assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 1137#L1585-44true assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 242#L826-42true assume !(1 == ~t12_pc~0); 353#L826-44true is_transmit12_triggered_~__retres1~12#1 := 0; 971#L837-14true is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 615#is_transmit12_triggered_returnLabel#15true activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 238#L1593-42true assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 1478#L1593-44true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 825#L1344-3true assume 1 == ~M_E~0;~M_E~0 := 2; 1215#L1344-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 763#L1349-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 325#L1354-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 778#L1359-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 1655#L1364-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 1549#L1369-3true assume !(1 == ~T6_E~0); 1258#L1374-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 199#L1379-3true assume 1 == ~T8_E~0;~T8_E~0 := 2; 1146#L1384-3true assume 1 == ~T9_E~0;~T9_E~0 := 2; 324#L1389-3true assume 1 == ~T10_E~0;~T10_E~0 := 2; 500#L1394-3true assume 1 == ~T11_E~0;~T11_E~0 := 2; 1724#L1399-3true assume 1 == ~T12_E~0;~T12_E~0 := 2; 1280#L1404-3true assume 1 == ~E_M~0;~E_M~0 := 2; 1222#L1409-3true assume !(1 == ~E_1~0); 1349#L1414-3true assume 1 == ~E_2~0;~E_2~0 := 2; 1375#L1419-3true assume 1 == ~E_3~0;~E_3~0 := 2; 960#L1424-3true assume 1 == ~E_4~0;~E_4~0 := 2; 141#L1429-3true assume 1 == ~E_5~0;~E_5~0 := 2; 777#L1434-3true assume 1 == ~E_6~0;~E_6~0 := 2; 943#L1439-3true assume 1 == ~E_7~0;~E_7~0 := 2; 114#L1444-3true assume 1 == ~E_8~0;~E_8~0 := 2; 172#L1449-3true assume !(1 == ~E_9~0); 1436#L1454-3true assume 1 == ~E_10~0;~E_10~0 := 2; 773#L1459-3true assume 1 == ~E_11~0;~E_11~0 := 2; 1777#L1464-3true assume 1 == ~E_12~0;~E_12~0 := 2; 1255#L1469-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 660#L926-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 76#L993-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 157#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 1591#L1834true assume !(0 == start_simulation_~tmp~3#1); 1088#L1834-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 890#L926-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 566#L993-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 24#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 1240#L1789true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1596#L1796true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1234#stop_simulation_returnLabel#1true start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 961#L1847true assume !(0 != start_simulation_~tmp___0~1#1); 1517#L1815-2true [2022-12-13 13:22:08,169 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 13:22:08,169 INFO L85 PathProgramCache]: Analyzing trace with hash -1818030166, now seen corresponding path program 1 times [2022-12-13 13:22:08,176 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 13:22:08,176 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2120575350] [2022-12-13 13:22:08,176 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 13:22:08,177 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 13:22:08,258 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 13:22:08,375 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 13:22:08,375 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 13:22:08,376 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2120575350] [2022-12-13 13:22:08,376 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2120575350] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 13:22:08,376 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 13:22:08,377 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 13:22:08,378 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1993678480] [2022-12-13 13:22:08,379 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 13:22:08,383 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 13:22:08,384 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 13:22:08,384 INFO L85 PathProgramCache]: Analyzing trace with hash 1473574458, now seen corresponding path program 1 times [2022-12-13 13:22:08,384 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 13:22:08,384 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1020169083] [2022-12-13 13:22:08,384 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 13:22:08,385 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 13:22:08,401 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 13:22:08,446 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 13:22:08,447 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 13:22:08,447 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1020169083] [2022-12-13 13:22:08,447 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1020169083] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 13:22:08,457 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 13:22:08,457 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-12-13 13:22:08,457 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [880309476] [2022-12-13 13:22:08,458 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 13:22:08,459 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 13:22:08,460 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 13:22:08,485 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2022-12-13 13:22:08,486 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2022-12-13 13:22:08,490 INFO L87 Difference]: Start difference. First operand has 1798 states, 1797 states have (on average 1.4997217584863662) internal successors, (2695), 1797 states have internal predecessors, (2695), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 2 states, 2 states have (on average 74.5) internal successors, (149), 2 states have internal predecessors, (149), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 13:22:08,546 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 13:22:08,546 INFO L93 Difference]: Finished difference Result 1796 states and 2661 transitions. [2022-12-13 13:22:08,548 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1796 states and 2661 transitions. [2022-12-13 13:22:08,562 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1627 [2022-12-13 13:22:08,576 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1796 states to 1790 states and 2655 transitions. [2022-12-13 13:22:08,577 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1790 [2022-12-13 13:22:08,580 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1790 [2022-12-13 13:22:08,580 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1790 states and 2655 transitions. [2022-12-13 13:22:08,586 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 13:22:08,587 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1790 states and 2655 transitions. [2022-12-13 13:22:08,603 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1790 states and 2655 transitions. [2022-12-13 13:22:08,645 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1790 to 1790. [2022-12-13 13:22:08,649 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1790 states, 1790 states have (on average 1.4832402234636872) internal successors, (2655), 1789 states have internal predecessors, (2655), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 13:22:08,655 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1790 states to 1790 states and 2655 transitions. [2022-12-13 13:22:08,657 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1790 states and 2655 transitions. [2022-12-13 13:22:08,657 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2022-12-13 13:22:08,661 INFO L428 stractBuchiCegarLoop]: Abstraction has 1790 states and 2655 transitions. [2022-12-13 13:22:08,662 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2022-12-13 13:22:08,662 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1790 states and 2655 transitions. [2022-12-13 13:22:08,672 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1627 [2022-12-13 13:22:08,673 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 13:22:08,673 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 13:22:08,675 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 13:22:08,675 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 13:22:08,676 INFO L748 eck$LassoCheckResult]: Stem: 3847#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 3848#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 4763#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4764#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5219#L853 assume !(1 == ~m_i~0);~m_st~0 := 2; 5089#L853-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4128#L858-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 3603#L863-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 3604#L868-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 4859#L873-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 4997#L878-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 5380#L883-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 5381#L888-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 4345#L893-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 4346#L898-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 4887#L903-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 4809#L908-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 4810#L913-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4960#L1206 assume !(0 == ~M_E~0); 4328#L1206-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4329#L1211-1 assume !(0 == ~T2_E~0); 5212#L1216-1 assume !(0 == ~T3_E~0); 4105#L1221-1 assume !(0 == ~T4_E~0); 4106#L1226-1 assume !(0 == ~T5_E~0); 3779#L1231-1 assume !(0 == ~T6_E~0); 3780#L1236-1 assume !(0 == ~T7_E~0); 5253#L1241-1 assume !(0 == ~T8_E~0); 4175#L1246-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 4176#L1251-1 assume !(0 == ~T10_E~0); 4397#L1256-1 assume !(0 == ~T11_E~0); 3613#L1261-1 assume !(0 == ~T12_E~0); 3614#L1266-1 assume !(0 == ~E_M~0); 5366#L1271-1 assume !(0 == ~E_1~0); 4987#L1276-1 assume !(0 == ~E_2~0); 4988#L1281-1 assume !(0 == ~E_3~0); 4916#L1286-1 assume 0 == ~E_4~0;~E_4~0 := 1; 4008#L1291-1 assume !(0 == ~E_5~0); 4009#L1296-1 assume !(0 == ~E_6~0); 4719#L1301-1 assume !(0 == ~E_7~0); 4720#L1306-1 assume !(0 == ~E_8~0); 5152#L1311-1 assume !(0 == ~E_9~0); 3968#L1316-1 assume !(0 == ~E_10~0); 3969#L1321-1 assume !(0 == ~E_11~0); 4734#L1326-1 assume 0 == ~E_12~0;~E_12~0 := 1; 3835#L1331-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3836#L598 assume 1 == ~m_pc~0; 3883#L599 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 3884#L609 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4617#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4618#L1497 assume !(0 != activate_threads_~tmp~1#1); 5329#L1497-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5277#L617 assume !(1 == ~t1_pc~0); 4197#L617-2 is_transmit1_triggered_~__retres1~1#1 := 0; 4198#L628 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5068#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 5069#L1505 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4826#L1505-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4827#L636 assume 1 == ~t2_pc~0; 4166#L637 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4167#L647 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3990#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3991#L1513 assume !(0 != activate_threads_~tmp___1~0#1); 4858#L1513-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4515#L655 assume !(1 == ~t3_pc~0); 4516#L655-2 is_transmit3_triggered_~__retres1~3#1 := 0; 5238#L666 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5057#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 5058#L1521 assume !(0 != activate_threads_~tmp___2~0#1); 5367#L1521-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5368#L674 assume 1 == ~t4_pc~0; 3700#L675 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3701#L685 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3725#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3726#L1529 assume !(0 != activate_threads_~tmp___3~0#1); 3992#L1529-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4514#L693 assume !(1 == ~t5_pc~0); 4669#L693-2 is_transmit5_triggered_~__retres1~5#1 := 0; 4330#L704 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4331#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 5154#L1537 assume !(0 != activate_threads_~tmp___4~0#1); 4410#L1537-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4349#L712 assume 1 == ~t6_pc~0; 4350#L713 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 4768#L723 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3978#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 3979#L1545 assume !(0 != activate_threads_~tmp___5~0#1); 4875#L1545-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4868#L731 assume 1 == ~t7_pc~0; 3837#L732 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 3838#L742 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4034#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 5157#L1553 assume !(0 != activate_threads_~tmp___6~0#1); 5098#L1553-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3941#L750 assume !(1 == ~t8_pc~0); 3634#L750-2 is_transmit8_triggered_~__retres1~8#1 := 0; 3633#L761 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4139#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 5167#L1561 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 4281#L1561-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4282#L769 assume 1 == ~t9_pc~0; 4822#L770 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 3799#L780 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3800#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 4024#L1569 assume !(0 != activate_threads_~tmp___8~0#1); 5034#L1569-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 5117#L788 assume !(1 == ~t10_pc~0); 4685#L788-2 is_transmit10_triggered_~__retres1~10#1 := 0; 4686#L799 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 5239#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 5191#L1577 assume !(0 != activate_threads_~tmp___9~0#1); 3937#L1577-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 3938#L807 assume 1 == ~t11_pc~0; 5123#L808 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 4700#L818 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 4860#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 5297#L1585 assume !(0 != activate_threads_~tmp___10~0#1); 5392#L1585-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 5222#L826 assume !(1 == ~t12_pc~0); 4352#L826-2 is_transmit12_triggered_~__retres1~12#1 := 0; 4353#L837 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 3678#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 3679#L1593 assume !(0 != activate_threads_~tmp___11~0#1); 4508#L1593-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4420#L1344 assume !(1 == ~M_E~0); 4421#L1344-2 assume !(1 == ~T1_E~0); 4551#L1349-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4725#L1354-1 assume !(1 == ~T3_E~0); 4726#L1359-1 assume !(1 == ~T4_E~0); 5109#L1364-1 assume !(1 == ~T5_E~0); 4051#L1369-1 assume !(1 == ~T6_E~0); 4052#L1374-1 assume !(1 == ~T7_E~0); 4732#L1379-1 assume !(1 == ~T8_E~0); 4733#L1384-1 assume !(1 == ~T9_E~0); 4808#L1389-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 5255#L1394-1 assume !(1 == ~T11_E~0); 5256#L1399-1 assume !(1 == ~T12_E~0); 5337#L1404-1 assume !(1 == ~E_M~0); 4178#L1409-1 assume !(1 == ~E_1~0); 4179#L1414-1 assume !(1 == ~E_2~0); 5013#L1419-1 assume !(1 == ~E_3~0); 3812#L1424-1 assume !(1 == ~E_4~0); 3813#L1429-1 assume 1 == ~E_5~0;~E_5~0 := 2; 4741#L1434-1 assume !(1 == ~E_6~0); 5270#L1439-1 assume !(1 == ~E_7~0); 3856#L1444-1 assume !(1 == ~E_8~0); 3857#L1449-1 assume !(1 == ~E_9~0); 4286#L1454-1 assume !(1 == ~E_10~0); 4287#L1459-1 assume !(1 == ~E_11~0); 4838#L1464-1 assume !(1 == ~E_12~0); 4839#L1469-1 assume { :end_inline_reset_delta_events } true; 4888#L1815-2 [2022-12-13 13:22:08,677 INFO L750 eck$LassoCheckResult]: Loop: 4888#L1815-2 assume !false; 5035#L1816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4702#L1181 assume !false; 4772#L1004 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 4723#L926 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 3606#L993 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 4323#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 4867#L1008 assume !(0 != eval_~tmp~0#1); 4563#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4186#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4187#L1206-3 assume 0 == ~M_E~0;~M_E~0 := 1; 5387#L1206-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4837#L1211-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3925#L1216-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3926#L1221-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4530#L1226-3 assume !(0 == ~T5_E~0); 3995#L1231-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 3996#L1236-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 4324#L1241-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 5307#L1246-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 5206#L1251-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 4947#L1256-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 3947#L1261-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 3948#L1266-3 assume !(0 == ~E_M~0); 3993#L1271-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3994#L1276-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4471#L1281-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4472#L1286-3 assume 0 == ~E_4~0;~E_4~0 := 1; 5010#L1291-3 assume 0 == ~E_5~0;~E_5~0 := 1; 5011#L1296-3 assume 0 == ~E_6~0;~E_6~0 := 1; 5373#L1301-3 assume 0 == ~E_7~0;~E_7~0 := 1; 5334#L1306-3 assume !(0 == ~E_8~0); 4591#L1311-3 assume 0 == ~E_9~0;~E_9~0 := 1; 3871#L1316-3 assume 0 == ~E_10~0;~E_10~0 := 1; 3872#L1321-3 assume 0 == ~E_11~0;~E_11~0 := 1; 3949#L1326-3 assume 0 == ~E_12~0;~E_12~0 := 1; 4694#L1331-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5021#L598-42 assume !(1 == ~m_pc~0); 5022#L598-44 is_master_triggered_~__retres1~0#1 := 0; 5138#L609-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4354#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4355#L1497-42 assume !(0 != activate_threads_~tmp~1#1); 5335#L1497-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4748#L617-42 assume 1 == ~t1_pc~0; 4524#L618-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4393#L628-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4394#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 5332#L1505-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4099#L1505-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4100#L636-42 assume 1 == ~t2_pc~0; 5312#L637-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4562#L647-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4639#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4640#L1513-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 5105#L1513-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4970#L655-42 assume !(1 == ~t3_pc~0); 4537#L655-44 is_transmit3_triggered_~__retres1~3#1 := 0; 4538#L666-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5048#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 5049#L1521-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 5237#L1521-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5173#L674-42 assume 1 == ~t4_pc~0; 5174#L675-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 4876#L685-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4877#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 5080#L1529-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 4667#L1529-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4668#L693-42 assume 1 == ~t5_pc~0; 4935#L694-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 4936#L704-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4721#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 4722#L1537-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 4991#L1537-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4296#L712-42 assume !(1 == ~t6_pc~0); 4297#L712-44 is_transmit6_triggered_~__retres1~6#1 := 0; 4609#L723-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3939#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 3940#L1545-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 4402#L1545-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4403#L731-42 assume 1 == ~t7_pc~0; 4266#L732-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 4092#L742-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4744#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 4313#L1553-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 4314#L1553-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4003#L750-42 assume 1 == ~t8_pc~0; 4004#L751-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 4578#L761-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4883#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 3886#L1561-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 3887#L1561-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4666#L769-42 assume !(1 == ~t9_pc~0); 4497#L769-44 is_transmit9_triggered_~__retres1~9#1 := 0; 4496#L780-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 5178#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 5376#L1569-42 assume !(0 != activate_threads_~tmp___8~0#1); 4101#L1569-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 4102#L788-42 assume 1 == ~t10_pc~0; 4674#L789-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 4902#L799-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 4873#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 4874#L1577-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 5385#L1577-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 5360#L807-42 assume 1 == ~t11_pc~0; 5030#L808-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 3722#L818-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 4582#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 3843#L1585-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 3844#L1585-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 4096#L826-42 assume 1 == ~t12_pc~0; 4097#L827-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 4302#L837-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 4690#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 4086#L1593-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 4087#L1593-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4951#L1344-3 assume 1 == ~M_E~0;~M_E~0 := 2; 4952#L1344-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4878#L1349-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4255#L1354-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4256#L1359-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4892#L1364-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 5363#L1369-3 assume !(1 == ~T6_E~0); 5269#L1374-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 4012#L1379-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 4013#L1384-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 4253#L1389-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 4254#L1394-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 4543#L1399-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 5275#L1404-3 assume 1 == ~E_M~0;~E_M~0 := 2; 5244#L1409-3 assume !(1 == ~E_1~0); 5245#L1414-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5306#L1419-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5087#L1424-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3902#L1429-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3903#L1434-3 assume 1 == ~E_6~0;~E_6~0 := 2; 4891#L1439-3 assume 1 == ~E_7~0;~E_7~0 := 2; 3849#L1444-3 assume 1 == ~E_8~0;~E_8~0 := 2; 3850#L1449-3 assume !(1 == ~E_9~0); 3955#L1454-3 assume 1 == ~E_10~0;~E_10~0 := 2; 4885#L1459-3 assume 1 == ~E_11~0;~E_11~0 := 2; 4886#L1464-3 assume 1 == ~E_12~0;~E_12~0 := 2; 5268#L1469-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 4752#L926-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 3767#L993-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 3768#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 3931#L1834 assume !(0 == start_simulation_~tmp~3#1); 4998#L1834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 5015#L926-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 4456#L993-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 3655#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 3656#L1789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5258#L1796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5254#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 5088#L1847 assume !(0 != start_simulation_~tmp___0~1#1); 4888#L1815-2 [2022-12-13 13:22:08,678 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 13:22:08,678 INFO L85 PathProgramCache]: Analyzing trace with hash -1818030166, now seen corresponding path program 2 times [2022-12-13 13:22:08,678 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 13:22:08,678 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1397895414] [2022-12-13 13:22:08,678 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 13:22:08,679 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 13:22:08,698 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 13:22:08,756 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 13:22:08,756 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 13:22:08,757 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1397895414] [2022-12-13 13:22:08,757 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1397895414] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 13:22:08,757 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 13:22:08,757 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 13:22:08,757 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1064067602] [2022-12-13 13:22:08,757 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 13:22:08,758 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 13:22:08,759 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 13:22:08,759 INFO L85 PathProgramCache]: Analyzing trace with hash -1091333421, now seen corresponding path program 1 times [2022-12-13 13:22:08,759 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 13:22:08,759 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1390782857] [2022-12-13 13:22:08,760 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 13:22:08,760 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 13:22:08,790 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 13:22:08,847 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 13:22:08,847 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 13:22:08,848 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1390782857] [2022-12-13 13:22:08,848 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1390782857] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 13:22:08,848 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 13:22:08,848 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 13:22:08,848 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1021160641] [2022-12-13 13:22:08,848 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 13:22:08,849 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 13:22:08,849 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 13:22:08,850 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 13:22:08,850 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 13:22:08,850 INFO L87 Difference]: Start difference. First operand 1790 states and 2655 transitions. cyclomatic complexity: 866 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 13:22:08,901 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 13:22:08,901 INFO L93 Difference]: Finished difference Result 1790 states and 2654 transitions. [2022-12-13 13:22:08,901 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1790 states and 2654 transitions. [2022-12-13 13:22:08,912 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1627 [2022-12-13 13:22:08,917 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1790 states to 1790 states and 2654 transitions. [2022-12-13 13:22:08,917 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1790 [2022-12-13 13:22:08,918 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1790 [2022-12-13 13:22:08,918 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1790 states and 2654 transitions. [2022-12-13 13:22:08,922 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 13:22:08,922 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1790 states and 2654 transitions. [2022-12-13 13:22:08,926 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1790 states and 2654 transitions. [2022-12-13 13:22:08,952 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1790 to 1790. [2022-12-13 13:22:08,955 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1790 states, 1790 states have (on average 1.48268156424581) internal successors, (2654), 1789 states have internal predecessors, (2654), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 13:22:08,977 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1790 states to 1790 states and 2654 transitions. [2022-12-13 13:22:08,978 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1790 states and 2654 transitions. [2022-12-13 13:22:08,978 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 13:22:08,979 INFO L428 stractBuchiCegarLoop]: Abstraction has 1790 states and 2654 transitions. [2022-12-13 13:22:08,979 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2022-12-13 13:22:08,979 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1790 states and 2654 transitions. [2022-12-13 13:22:08,984 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1627 [2022-12-13 13:22:08,984 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 13:22:08,985 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 13:22:08,986 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 13:22:08,986 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 13:22:08,987 INFO L748 eck$LassoCheckResult]: Stem: 7434#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 7435#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 8350#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 8351#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 8806#L853 assume 1 == ~m_i~0;~m_st~0 := 0; 8676#L853-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7715#L858-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 7190#L863-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 7191#L868-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 8446#L873-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 8584#L878-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 8967#L883-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 8968#L888-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 7932#L893-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 7933#L898-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 8474#L903-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 8396#L908-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 8397#L913-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8547#L1206 assume !(0 == ~M_E~0); 7915#L1206-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 7916#L1211-1 assume !(0 == ~T2_E~0); 8799#L1216-1 assume !(0 == ~T3_E~0); 7692#L1221-1 assume !(0 == ~T4_E~0); 7693#L1226-1 assume !(0 == ~T5_E~0); 7366#L1231-1 assume !(0 == ~T6_E~0); 7367#L1236-1 assume !(0 == ~T7_E~0); 8840#L1241-1 assume !(0 == ~T8_E~0); 7762#L1246-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 7763#L1251-1 assume !(0 == ~T10_E~0); 7984#L1256-1 assume !(0 == ~T11_E~0); 7200#L1261-1 assume !(0 == ~T12_E~0); 7201#L1266-1 assume !(0 == ~E_M~0); 8953#L1271-1 assume !(0 == ~E_1~0); 8574#L1276-1 assume !(0 == ~E_2~0); 8575#L1281-1 assume !(0 == ~E_3~0); 8503#L1286-1 assume 0 == ~E_4~0;~E_4~0 := 1; 7595#L1291-1 assume !(0 == ~E_5~0); 7596#L1296-1 assume !(0 == ~E_6~0); 8306#L1301-1 assume !(0 == ~E_7~0); 8307#L1306-1 assume !(0 == ~E_8~0); 8739#L1311-1 assume !(0 == ~E_9~0); 7555#L1316-1 assume !(0 == ~E_10~0); 7556#L1321-1 assume !(0 == ~E_11~0); 8321#L1326-1 assume 0 == ~E_12~0;~E_12~0 := 1; 7422#L1331-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7423#L598 assume 1 == ~m_pc~0; 7470#L599 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 7471#L609 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8204#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8205#L1497 assume !(0 != activate_threads_~tmp~1#1); 8916#L1497-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8864#L617 assume !(1 == ~t1_pc~0); 7784#L617-2 is_transmit1_triggered_~__retres1~1#1 := 0; 7785#L628 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8655#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8656#L1505 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 8413#L1505-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8414#L636 assume 1 == ~t2_pc~0; 7753#L637 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 7754#L647 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7577#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 7578#L1513 assume !(0 != activate_threads_~tmp___1~0#1); 8445#L1513-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8102#L655 assume !(1 == ~t3_pc~0); 8103#L655-2 is_transmit3_triggered_~__retres1~3#1 := 0; 8825#L666 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8644#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 8645#L1521 assume !(0 != activate_threads_~tmp___2~0#1); 8954#L1521-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8955#L674 assume 1 == ~t4_pc~0; 7287#L675 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 7288#L685 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7312#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 7313#L1529 assume !(0 != activate_threads_~tmp___3~0#1); 7579#L1529-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8101#L693 assume !(1 == ~t5_pc~0); 8256#L693-2 is_transmit5_triggered_~__retres1~5#1 := 0; 7917#L704 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7918#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 8741#L1537 assume !(0 != activate_threads_~tmp___4~0#1); 7997#L1537-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7936#L712 assume 1 == ~t6_pc~0; 7937#L713 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 8355#L723 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 7565#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 7566#L1545 assume !(0 != activate_threads_~tmp___5~0#1); 8462#L1545-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8455#L731 assume 1 == ~t7_pc~0; 7424#L732 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 7425#L742 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 7621#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 8744#L1553 assume !(0 != activate_threads_~tmp___6~0#1); 8685#L1553-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 7528#L750 assume !(1 == ~t8_pc~0); 7221#L750-2 is_transmit8_triggered_~__retres1~8#1 := 0; 7220#L761 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 7726#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 8754#L1561 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 7868#L1561-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 7869#L769 assume 1 == ~t9_pc~0; 8409#L770 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 7386#L780 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 7387#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 7611#L1569 assume !(0 != activate_threads_~tmp___8~0#1); 8621#L1569-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 8704#L788 assume !(1 == ~t10_pc~0); 8272#L788-2 is_transmit10_triggered_~__retres1~10#1 := 0; 8273#L799 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 8826#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 8778#L1577 assume !(0 != activate_threads_~tmp___9~0#1); 7524#L1577-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 7525#L807 assume 1 == ~t11_pc~0; 8710#L808 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 8287#L818 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 8447#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 8884#L1585 assume !(0 != activate_threads_~tmp___10~0#1); 8979#L1585-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 8809#L826 assume !(1 == ~t12_pc~0); 7939#L826-2 is_transmit12_triggered_~__retres1~12#1 := 0; 7940#L837 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 7265#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 7266#L1593 assume !(0 != activate_threads_~tmp___11~0#1); 8095#L1593-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8007#L1344 assume !(1 == ~M_E~0); 8008#L1344-2 assume !(1 == ~T1_E~0); 8138#L1349-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 8312#L1354-1 assume !(1 == ~T3_E~0); 8313#L1359-1 assume !(1 == ~T4_E~0); 8696#L1364-1 assume !(1 == ~T5_E~0); 7638#L1369-1 assume !(1 == ~T6_E~0); 7639#L1374-1 assume !(1 == ~T7_E~0); 8319#L1379-1 assume !(1 == ~T8_E~0); 8320#L1384-1 assume !(1 == ~T9_E~0); 8395#L1389-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 8842#L1394-1 assume !(1 == ~T11_E~0); 8843#L1399-1 assume !(1 == ~T12_E~0); 8924#L1404-1 assume !(1 == ~E_M~0); 7765#L1409-1 assume !(1 == ~E_1~0); 7766#L1414-1 assume !(1 == ~E_2~0); 8600#L1419-1 assume !(1 == ~E_3~0); 7399#L1424-1 assume !(1 == ~E_4~0); 7400#L1429-1 assume 1 == ~E_5~0;~E_5~0 := 2; 8328#L1434-1 assume !(1 == ~E_6~0); 8857#L1439-1 assume !(1 == ~E_7~0); 7443#L1444-1 assume !(1 == ~E_8~0); 7444#L1449-1 assume !(1 == ~E_9~0); 7873#L1454-1 assume !(1 == ~E_10~0); 7874#L1459-1 assume !(1 == ~E_11~0); 8425#L1464-1 assume !(1 == ~E_12~0); 8426#L1469-1 assume { :end_inline_reset_delta_events } true; 8475#L1815-2 [2022-12-13 13:22:08,988 INFO L750 eck$LassoCheckResult]: Loop: 8475#L1815-2 assume !false; 8622#L1816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 8289#L1181 assume !false; 8359#L1004 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 8310#L926 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 7193#L993 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 7910#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 8454#L1008 assume !(0 != eval_~tmp~0#1); 8150#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 7773#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 7774#L1206-3 assume 0 == ~M_E~0;~M_E~0 := 1; 8974#L1206-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 8424#L1211-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7512#L1216-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 7513#L1221-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 8117#L1226-3 assume !(0 == ~T5_E~0); 7582#L1231-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 7583#L1236-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 7911#L1241-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 8894#L1246-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 8793#L1251-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 8534#L1256-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 7534#L1261-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 7535#L1266-3 assume !(0 == ~E_M~0); 7580#L1271-3 assume 0 == ~E_1~0;~E_1~0 := 1; 7581#L1276-3 assume 0 == ~E_2~0;~E_2~0 := 1; 8058#L1281-3 assume 0 == ~E_3~0;~E_3~0 := 1; 8059#L1286-3 assume 0 == ~E_4~0;~E_4~0 := 1; 8597#L1291-3 assume 0 == ~E_5~0;~E_5~0 := 1; 8598#L1296-3 assume 0 == ~E_6~0;~E_6~0 := 1; 8960#L1301-3 assume 0 == ~E_7~0;~E_7~0 := 1; 8921#L1306-3 assume !(0 == ~E_8~0); 8178#L1311-3 assume 0 == ~E_9~0;~E_9~0 := 1; 7458#L1316-3 assume 0 == ~E_10~0;~E_10~0 := 1; 7459#L1321-3 assume 0 == ~E_11~0;~E_11~0 := 1; 7536#L1326-3 assume 0 == ~E_12~0;~E_12~0 := 1; 8281#L1331-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8608#L598-42 assume !(1 == ~m_pc~0); 8609#L598-44 is_master_triggered_~__retres1~0#1 := 0; 8725#L609-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7941#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 7942#L1497-42 assume !(0 != activate_threads_~tmp~1#1); 8922#L1497-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8335#L617-42 assume !(1 == ~t1_pc~0); 8112#L617-44 is_transmit1_triggered_~__retres1~1#1 := 0; 7980#L628-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7981#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8919#L1505-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 7686#L1505-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7687#L636-42 assume 1 == ~t2_pc~0; 8899#L637-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 8149#L647-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8226#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 8227#L1513-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 8692#L1513-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8557#L655-42 assume !(1 == ~t3_pc~0); 8124#L655-44 is_transmit3_triggered_~__retres1~3#1 := 0; 8125#L666-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8635#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 8636#L1521-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 8824#L1521-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8760#L674-42 assume 1 == ~t4_pc~0; 8761#L675-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 8463#L685-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8464#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 8667#L1529-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 8254#L1529-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8255#L693-42 assume 1 == ~t5_pc~0; 8522#L694-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 8523#L704-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8308#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 8309#L1537-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 8578#L1537-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7883#L712-42 assume !(1 == ~t6_pc~0); 7884#L712-44 is_transmit6_triggered_~__retres1~6#1 := 0; 8196#L723-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 7526#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 7527#L1545-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 7989#L1545-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 7990#L731-42 assume 1 == ~t7_pc~0; 7853#L732-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 7679#L742-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8331#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 7900#L1553-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 7901#L1553-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 7590#L750-42 assume 1 == ~t8_pc~0; 7591#L751-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 8165#L761-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 8470#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 7473#L1561-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 7474#L1561-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 8253#L769-42 assume 1 == ~t9_pc~0; 8082#L770-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 8083#L780-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 8765#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 8963#L1569-42 assume !(0 != activate_threads_~tmp___8~0#1); 7688#L1569-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 7689#L788-42 assume 1 == ~t10_pc~0; 8261#L789-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 8489#L799-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 8460#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 8461#L1577-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 8972#L1577-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 8947#L807-42 assume 1 == ~t11_pc~0; 8617#L808-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 7309#L818-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 8169#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 7430#L1585-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 7431#L1585-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 7683#L826-42 assume 1 == ~t12_pc~0; 7684#L827-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 7889#L837-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 8277#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 7673#L1593-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 7674#L1593-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8538#L1344-3 assume 1 == ~M_E~0;~M_E~0 := 2; 8539#L1344-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 8465#L1349-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7842#L1354-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 7843#L1359-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8479#L1364-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 8950#L1369-3 assume !(1 == ~T6_E~0); 8856#L1374-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 7599#L1379-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 7600#L1384-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 7840#L1389-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 7841#L1394-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 8130#L1399-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 8862#L1404-3 assume 1 == ~E_M~0;~E_M~0 := 2; 8831#L1409-3 assume !(1 == ~E_1~0); 8832#L1414-3 assume 1 == ~E_2~0;~E_2~0 := 2; 8893#L1419-3 assume 1 == ~E_3~0;~E_3~0 := 2; 8674#L1424-3 assume 1 == ~E_4~0;~E_4~0 := 2; 7489#L1429-3 assume 1 == ~E_5~0;~E_5~0 := 2; 7490#L1434-3 assume 1 == ~E_6~0;~E_6~0 := 2; 8478#L1439-3 assume 1 == ~E_7~0;~E_7~0 := 2; 7436#L1444-3 assume 1 == ~E_8~0;~E_8~0 := 2; 7437#L1449-3 assume !(1 == ~E_9~0); 7542#L1454-3 assume 1 == ~E_10~0;~E_10~0 := 2; 8472#L1459-3 assume 1 == ~E_11~0;~E_11~0 := 2; 8473#L1464-3 assume 1 == ~E_12~0;~E_12~0 := 2; 8855#L1469-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 8339#L926-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 7354#L993-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 7355#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 7518#L1834 assume !(0 == start_simulation_~tmp~3#1); 8585#L1834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 8602#L926-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 8043#L993-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 7242#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 7243#L1789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 8845#L1796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 8841#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 8675#L1847 assume !(0 != start_simulation_~tmp___0~1#1); 8475#L1815-2 [2022-12-13 13:22:08,988 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 13:22:08,989 INFO L85 PathProgramCache]: Analyzing trace with hash -494851220, now seen corresponding path program 1 times [2022-12-13 13:22:08,989 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 13:22:08,989 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1586317330] [2022-12-13 13:22:08,989 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 13:22:08,989 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 13:22:09,007 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 13:22:09,049 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 13:22:09,050 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 13:22:09,050 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1586317330] [2022-12-13 13:22:09,050 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1586317330] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 13:22:09,050 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 13:22:09,050 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 13:22:09,051 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2100164824] [2022-12-13 13:22:09,051 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 13:22:09,051 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 13:22:09,052 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 13:22:09,052 INFO L85 PathProgramCache]: Analyzing trace with hash -943182637, now seen corresponding path program 1 times [2022-12-13 13:22:09,052 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 13:22:09,052 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [209608267] [2022-12-13 13:22:09,052 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 13:22:09,053 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 13:22:09,069 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 13:22:09,112 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 13:22:09,112 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 13:22:09,112 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [209608267] [2022-12-13 13:22:09,113 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [209608267] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 13:22:09,113 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 13:22:09,113 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 13:22:09,113 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [682033188] [2022-12-13 13:22:09,113 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 13:22:09,114 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 13:22:09,114 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 13:22:09,114 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 13:22:09,114 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 13:22:09,115 INFO L87 Difference]: Start difference. First operand 1790 states and 2654 transitions. cyclomatic complexity: 865 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 13:22:09,142 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 13:22:09,142 INFO L93 Difference]: Finished difference Result 1790 states and 2653 transitions. [2022-12-13 13:22:09,143 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1790 states and 2653 transitions. [2022-12-13 13:22:09,149 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1627 [2022-12-13 13:22:09,153 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1790 states to 1790 states and 2653 transitions. [2022-12-13 13:22:09,153 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1790 [2022-12-13 13:22:09,154 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1790 [2022-12-13 13:22:09,154 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1790 states and 2653 transitions. [2022-12-13 13:22:09,156 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 13:22:09,156 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1790 states and 2653 transitions. [2022-12-13 13:22:09,158 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1790 states and 2653 transitions. [2022-12-13 13:22:09,172 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1790 to 1790. [2022-12-13 13:22:09,174 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1790 states, 1790 states have (on average 1.482122905027933) internal successors, (2653), 1789 states have internal predecessors, (2653), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 13:22:09,177 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1790 states to 1790 states and 2653 transitions. [2022-12-13 13:22:09,177 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1790 states and 2653 transitions. [2022-12-13 13:22:09,177 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 13:22:09,178 INFO L428 stractBuchiCegarLoop]: Abstraction has 1790 states and 2653 transitions. [2022-12-13 13:22:09,178 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2022-12-13 13:22:09,178 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1790 states and 2653 transitions. [2022-12-13 13:22:09,183 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1627 [2022-12-13 13:22:09,183 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 13:22:09,183 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 13:22:09,185 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 13:22:09,185 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 13:22:09,185 INFO L748 eck$LassoCheckResult]: Stem: 11021#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 11022#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 11937#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 11938#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 12393#L853 assume 1 == ~m_i~0;~m_st~0 := 0; 12263#L853-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 11302#L858-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 10777#L863-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 10778#L868-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 12033#L873-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 12171#L878-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 12554#L883-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 12555#L888-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 11519#L893-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 11520#L898-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 12061#L903-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 11983#L908-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 11984#L913-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 12134#L1206 assume !(0 == ~M_E~0); 11502#L1206-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 11503#L1211-1 assume !(0 == ~T2_E~0); 12386#L1216-1 assume !(0 == ~T3_E~0); 11279#L1221-1 assume !(0 == ~T4_E~0); 11280#L1226-1 assume !(0 == ~T5_E~0); 10953#L1231-1 assume !(0 == ~T6_E~0); 10954#L1236-1 assume !(0 == ~T7_E~0); 12427#L1241-1 assume !(0 == ~T8_E~0); 11349#L1246-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 11350#L1251-1 assume !(0 == ~T10_E~0); 11571#L1256-1 assume !(0 == ~T11_E~0); 10787#L1261-1 assume !(0 == ~T12_E~0); 10788#L1266-1 assume !(0 == ~E_M~0); 12540#L1271-1 assume !(0 == ~E_1~0); 12161#L1276-1 assume !(0 == ~E_2~0); 12162#L1281-1 assume !(0 == ~E_3~0); 12090#L1286-1 assume 0 == ~E_4~0;~E_4~0 := 1; 11182#L1291-1 assume !(0 == ~E_5~0); 11183#L1296-1 assume !(0 == ~E_6~0); 11893#L1301-1 assume !(0 == ~E_7~0); 11894#L1306-1 assume !(0 == ~E_8~0); 12326#L1311-1 assume !(0 == ~E_9~0); 11142#L1316-1 assume !(0 == ~E_10~0); 11143#L1321-1 assume !(0 == ~E_11~0); 11908#L1326-1 assume 0 == ~E_12~0;~E_12~0 := 1; 11009#L1331-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11010#L598 assume 1 == ~m_pc~0; 11057#L599 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 11058#L609 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11791#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 11792#L1497 assume !(0 != activate_threads_~tmp~1#1); 12503#L1497-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12451#L617 assume !(1 == ~t1_pc~0); 11371#L617-2 is_transmit1_triggered_~__retres1~1#1 := 0; 11372#L628 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12242#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 12243#L1505 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 12000#L1505-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12001#L636 assume 1 == ~t2_pc~0; 11340#L637 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 11341#L647 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11164#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 11165#L1513 assume !(0 != activate_threads_~tmp___1~0#1); 12032#L1513-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11689#L655 assume !(1 == ~t3_pc~0); 11690#L655-2 is_transmit3_triggered_~__retres1~3#1 := 0; 12412#L666 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12231#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 12232#L1521 assume !(0 != activate_threads_~tmp___2~0#1); 12541#L1521-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12542#L674 assume 1 == ~t4_pc~0; 10874#L675 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 10875#L685 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10899#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 10900#L1529 assume !(0 != activate_threads_~tmp___3~0#1); 11166#L1529-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 11688#L693 assume !(1 == ~t5_pc~0); 11843#L693-2 is_transmit5_triggered_~__retres1~5#1 := 0; 11504#L704 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 11505#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 12328#L1537 assume !(0 != activate_threads_~tmp___4~0#1); 11584#L1537-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11523#L712 assume 1 == ~t6_pc~0; 11524#L713 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 11942#L723 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11152#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 11153#L1545 assume !(0 != activate_threads_~tmp___5~0#1); 12049#L1545-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12042#L731 assume 1 == ~t7_pc~0; 11011#L732 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 11012#L742 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 11208#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 12331#L1553 assume !(0 != activate_threads_~tmp___6~0#1); 12272#L1553-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 11115#L750 assume !(1 == ~t8_pc~0); 10808#L750-2 is_transmit8_triggered_~__retres1~8#1 := 0; 10807#L761 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 11313#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 12341#L1561 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 11455#L1561-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 11456#L769 assume 1 == ~t9_pc~0; 11996#L770 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 10973#L780 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 10974#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 11198#L1569 assume !(0 != activate_threads_~tmp___8~0#1); 12208#L1569-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 12291#L788 assume !(1 == ~t10_pc~0); 11859#L788-2 is_transmit10_triggered_~__retres1~10#1 := 0; 11860#L799 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 12413#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 12365#L1577 assume !(0 != activate_threads_~tmp___9~0#1); 11111#L1577-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 11112#L807 assume 1 == ~t11_pc~0; 12297#L808 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 11874#L818 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 12034#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 12471#L1585 assume !(0 != activate_threads_~tmp___10~0#1); 12566#L1585-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 12396#L826 assume !(1 == ~t12_pc~0); 11526#L826-2 is_transmit12_triggered_~__retres1~12#1 := 0; 11527#L837 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 10852#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 10853#L1593 assume !(0 != activate_threads_~tmp___11~0#1); 11682#L1593-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11594#L1344 assume !(1 == ~M_E~0); 11595#L1344-2 assume !(1 == ~T1_E~0); 11725#L1349-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 11899#L1354-1 assume !(1 == ~T3_E~0); 11900#L1359-1 assume !(1 == ~T4_E~0); 12283#L1364-1 assume !(1 == ~T5_E~0); 11225#L1369-1 assume !(1 == ~T6_E~0); 11226#L1374-1 assume !(1 == ~T7_E~0); 11906#L1379-1 assume !(1 == ~T8_E~0); 11907#L1384-1 assume !(1 == ~T9_E~0); 11982#L1389-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 12429#L1394-1 assume !(1 == ~T11_E~0); 12430#L1399-1 assume !(1 == ~T12_E~0); 12511#L1404-1 assume !(1 == ~E_M~0); 11352#L1409-1 assume !(1 == ~E_1~0); 11353#L1414-1 assume !(1 == ~E_2~0); 12187#L1419-1 assume !(1 == ~E_3~0); 10986#L1424-1 assume !(1 == ~E_4~0); 10987#L1429-1 assume 1 == ~E_5~0;~E_5~0 := 2; 11915#L1434-1 assume !(1 == ~E_6~0); 12444#L1439-1 assume !(1 == ~E_7~0); 11030#L1444-1 assume !(1 == ~E_8~0); 11031#L1449-1 assume !(1 == ~E_9~0); 11460#L1454-1 assume !(1 == ~E_10~0); 11461#L1459-1 assume !(1 == ~E_11~0); 12012#L1464-1 assume !(1 == ~E_12~0); 12013#L1469-1 assume { :end_inline_reset_delta_events } true; 12062#L1815-2 [2022-12-13 13:22:09,185 INFO L750 eck$LassoCheckResult]: Loop: 12062#L1815-2 assume !false; 12209#L1816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 11876#L1181 assume !false; 11946#L1004 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 11897#L926 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 10780#L993 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 11497#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 12041#L1008 assume !(0 != eval_~tmp~0#1); 11737#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 11360#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 11361#L1206-3 assume 0 == ~M_E~0;~M_E~0 := 1; 12561#L1206-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 12011#L1211-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 11099#L1216-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 11100#L1221-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 11704#L1226-3 assume !(0 == ~T5_E~0); 11169#L1231-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 11170#L1236-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 11498#L1241-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 12481#L1246-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 12380#L1251-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 12121#L1256-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 11121#L1261-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 11122#L1266-3 assume !(0 == ~E_M~0); 11167#L1271-3 assume 0 == ~E_1~0;~E_1~0 := 1; 11168#L1276-3 assume 0 == ~E_2~0;~E_2~0 := 1; 11645#L1281-3 assume 0 == ~E_3~0;~E_3~0 := 1; 11646#L1286-3 assume 0 == ~E_4~0;~E_4~0 := 1; 12184#L1291-3 assume 0 == ~E_5~0;~E_5~0 := 1; 12185#L1296-3 assume 0 == ~E_6~0;~E_6~0 := 1; 12547#L1301-3 assume 0 == ~E_7~0;~E_7~0 := 1; 12508#L1306-3 assume !(0 == ~E_8~0); 11765#L1311-3 assume 0 == ~E_9~0;~E_9~0 := 1; 11045#L1316-3 assume 0 == ~E_10~0;~E_10~0 := 1; 11046#L1321-3 assume 0 == ~E_11~0;~E_11~0 := 1; 11123#L1326-3 assume 0 == ~E_12~0;~E_12~0 := 1; 11868#L1331-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12195#L598-42 assume !(1 == ~m_pc~0); 12196#L598-44 is_master_triggered_~__retres1~0#1 := 0; 12312#L609-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11528#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 11529#L1497-42 assume !(0 != activate_threads_~tmp~1#1); 12509#L1497-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11922#L617-42 assume 1 == ~t1_pc~0; 11698#L618-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 11567#L628-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11568#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 12506#L1505-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 11273#L1505-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11274#L636-42 assume 1 == ~t2_pc~0; 12486#L637-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 11736#L647-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11813#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 11814#L1513-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 12279#L1513-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12144#L655-42 assume 1 == ~t3_pc~0; 12145#L656-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 11712#L666-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12222#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 12223#L1521-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 12411#L1521-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12347#L674-42 assume !(1 == ~t4_pc~0); 12129#L674-44 is_transmit4_triggered_~__retres1~4#1 := 0; 12050#L685-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12051#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 12254#L1529-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 11841#L1529-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 11842#L693-42 assume 1 == ~t5_pc~0; 12109#L694-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 12110#L704-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 11895#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 11896#L1537-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 12165#L1537-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11470#L712-42 assume 1 == ~t6_pc~0; 11472#L713-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 11783#L723-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11113#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 11114#L1545-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 11576#L1545-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 11577#L731-42 assume 1 == ~t7_pc~0; 11440#L732-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 11266#L742-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 11918#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 11487#L1553-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 11488#L1553-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 11177#L750-42 assume 1 == ~t8_pc~0; 11178#L751-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 11752#L761-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 12057#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 11060#L1561-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 11061#L1561-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 11840#L769-42 assume 1 == ~t9_pc~0; 11669#L770-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 11670#L780-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 12352#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 12550#L1569-42 assume !(0 != activate_threads_~tmp___8~0#1); 11275#L1569-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 11276#L788-42 assume 1 == ~t10_pc~0; 11848#L789-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 12076#L799-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 12047#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 12048#L1577-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 12559#L1577-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 12534#L807-42 assume 1 == ~t11_pc~0; 12204#L808-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 10896#L818-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 11756#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 11017#L1585-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 11018#L1585-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 11270#L826-42 assume 1 == ~t12_pc~0; 11271#L827-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 11476#L837-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 11864#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 11260#L1593-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 11261#L1593-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12125#L1344-3 assume 1 == ~M_E~0;~M_E~0 := 2; 12126#L1344-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 12052#L1349-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 11429#L1354-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 11430#L1359-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 12066#L1364-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 12537#L1369-3 assume !(1 == ~T6_E~0); 12443#L1374-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 11186#L1379-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 11187#L1384-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 11427#L1389-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 11428#L1394-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 11717#L1399-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 12449#L1404-3 assume 1 == ~E_M~0;~E_M~0 := 2; 12418#L1409-3 assume !(1 == ~E_1~0); 12419#L1414-3 assume 1 == ~E_2~0;~E_2~0 := 2; 12480#L1419-3 assume 1 == ~E_3~0;~E_3~0 := 2; 12261#L1424-3 assume 1 == ~E_4~0;~E_4~0 := 2; 11076#L1429-3 assume 1 == ~E_5~0;~E_5~0 := 2; 11077#L1434-3 assume 1 == ~E_6~0;~E_6~0 := 2; 12065#L1439-3 assume 1 == ~E_7~0;~E_7~0 := 2; 11023#L1444-3 assume 1 == ~E_8~0;~E_8~0 := 2; 11024#L1449-3 assume !(1 == ~E_9~0); 11129#L1454-3 assume 1 == ~E_10~0;~E_10~0 := 2; 12059#L1459-3 assume 1 == ~E_11~0;~E_11~0 := 2; 12060#L1464-3 assume 1 == ~E_12~0;~E_12~0 := 2; 12442#L1469-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 11926#L926-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 10941#L993-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 10942#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 11105#L1834 assume !(0 == start_simulation_~tmp~3#1); 12172#L1834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 12189#L926-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 11630#L993-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 10829#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 10830#L1789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 12432#L1796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 12428#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 12262#L1847 assume !(0 != start_simulation_~tmp___0~1#1); 12062#L1815-2 [2022-12-13 13:22:09,186 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 13:22:09,186 INFO L85 PathProgramCache]: Analyzing trace with hash -833138770, now seen corresponding path program 1 times [2022-12-13 13:22:09,186 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 13:22:09,186 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [551219795] [2022-12-13 13:22:09,186 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 13:22:09,187 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 13:22:09,196 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 13:22:09,221 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 13:22:09,221 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 13:22:09,221 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [551219795] [2022-12-13 13:22:09,222 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [551219795] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 13:22:09,222 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 13:22:09,222 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 13:22:09,222 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1116759008] [2022-12-13 13:22:09,222 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 13:22:09,223 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 13:22:09,223 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 13:22:09,223 INFO L85 PathProgramCache]: Analyzing trace with hash 99495633, now seen corresponding path program 1 times [2022-12-13 13:22:09,223 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 13:22:09,224 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1917159845] [2022-12-13 13:22:09,224 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 13:22:09,224 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 13:22:09,240 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 13:22:09,287 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 13:22:09,287 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 13:22:09,288 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1917159845] [2022-12-13 13:22:09,288 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1917159845] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 13:22:09,288 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 13:22:09,288 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 13:22:09,288 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1247766315] [2022-12-13 13:22:09,288 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 13:22:09,289 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 13:22:09,289 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 13:22:09,289 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 13:22:09,289 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 13:22:09,290 INFO L87 Difference]: Start difference. First operand 1790 states and 2653 transitions. cyclomatic complexity: 864 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 13:22:09,315 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 13:22:09,315 INFO L93 Difference]: Finished difference Result 1790 states and 2652 transitions. [2022-12-13 13:22:09,315 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1790 states and 2652 transitions. [2022-12-13 13:22:09,321 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1627 [2022-12-13 13:22:09,326 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1790 states to 1790 states and 2652 transitions. [2022-12-13 13:22:09,326 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1790 [2022-12-13 13:22:09,327 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1790 [2022-12-13 13:22:09,327 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1790 states and 2652 transitions. [2022-12-13 13:22:09,328 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 13:22:09,328 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1790 states and 2652 transitions. [2022-12-13 13:22:09,330 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1790 states and 2652 transitions. [2022-12-13 13:22:09,344 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1790 to 1790. [2022-12-13 13:22:09,346 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1790 states, 1790 states have (on average 1.481564245810056) internal successors, (2652), 1789 states have internal predecessors, (2652), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 13:22:09,349 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1790 states to 1790 states and 2652 transitions. [2022-12-13 13:22:09,349 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1790 states and 2652 transitions. [2022-12-13 13:22:09,349 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 13:22:09,350 INFO L428 stractBuchiCegarLoop]: Abstraction has 1790 states and 2652 transitions. [2022-12-13 13:22:09,350 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2022-12-13 13:22:09,350 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1790 states and 2652 transitions. [2022-12-13 13:22:09,355 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1627 [2022-12-13 13:22:09,355 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 13:22:09,355 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 13:22:09,356 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 13:22:09,356 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 13:22:09,357 INFO L748 eck$LassoCheckResult]: Stem: 14608#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 14609#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 15524#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 15525#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 15980#L853 assume 1 == ~m_i~0;~m_st~0 := 0; 15850#L853-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 14889#L858-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 14364#L863-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 14365#L868-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 15620#L873-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 15758#L878-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 16141#L883-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 16142#L888-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 15106#L893-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 15107#L898-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 15648#L903-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 15570#L908-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 15571#L913-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 15721#L1206 assume !(0 == ~M_E~0); 15089#L1206-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 15090#L1211-1 assume !(0 == ~T2_E~0); 15973#L1216-1 assume !(0 == ~T3_E~0); 14866#L1221-1 assume !(0 == ~T4_E~0); 14867#L1226-1 assume !(0 == ~T5_E~0); 14540#L1231-1 assume !(0 == ~T6_E~0); 14541#L1236-1 assume !(0 == ~T7_E~0); 16014#L1241-1 assume !(0 == ~T8_E~0); 14936#L1246-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 14937#L1251-1 assume !(0 == ~T10_E~0); 15158#L1256-1 assume !(0 == ~T11_E~0); 14374#L1261-1 assume !(0 == ~T12_E~0); 14375#L1266-1 assume !(0 == ~E_M~0); 16127#L1271-1 assume !(0 == ~E_1~0); 15748#L1276-1 assume !(0 == ~E_2~0); 15749#L1281-1 assume !(0 == ~E_3~0); 15677#L1286-1 assume 0 == ~E_4~0;~E_4~0 := 1; 14769#L1291-1 assume !(0 == ~E_5~0); 14770#L1296-1 assume !(0 == ~E_6~0); 15480#L1301-1 assume !(0 == ~E_7~0); 15481#L1306-1 assume !(0 == ~E_8~0); 15913#L1311-1 assume !(0 == ~E_9~0); 14729#L1316-1 assume !(0 == ~E_10~0); 14730#L1321-1 assume !(0 == ~E_11~0); 15495#L1326-1 assume 0 == ~E_12~0;~E_12~0 := 1; 14596#L1331-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 14597#L598 assume 1 == ~m_pc~0; 14644#L599 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 14645#L609 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 15378#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 15379#L1497 assume !(0 != activate_threads_~tmp~1#1); 16090#L1497-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16038#L617 assume !(1 == ~t1_pc~0); 14958#L617-2 is_transmit1_triggered_~__retres1~1#1 := 0; 14959#L628 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 15829#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 15830#L1505 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 15587#L1505-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15588#L636 assume 1 == ~t2_pc~0; 14927#L637 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 14928#L647 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14751#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 14752#L1513 assume !(0 != activate_threads_~tmp___1~0#1); 15619#L1513-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 15276#L655 assume !(1 == ~t3_pc~0); 15277#L655-2 is_transmit3_triggered_~__retres1~3#1 := 0; 15999#L666 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 15818#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 15819#L1521 assume !(0 != activate_threads_~tmp___2~0#1); 16128#L1521-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 16129#L674 assume 1 == ~t4_pc~0; 14461#L675 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 14462#L685 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 14486#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 14487#L1529 assume !(0 != activate_threads_~tmp___3~0#1); 14753#L1529-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 15275#L693 assume !(1 == ~t5_pc~0); 15430#L693-2 is_transmit5_triggered_~__retres1~5#1 := 0; 15091#L704 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 15092#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 15915#L1537 assume !(0 != activate_threads_~tmp___4~0#1); 15171#L1537-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 15110#L712 assume 1 == ~t6_pc~0; 15111#L713 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 15529#L723 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 14739#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 14740#L1545 assume !(0 != activate_threads_~tmp___5~0#1); 15636#L1545-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 15629#L731 assume 1 == ~t7_pc~0; 14598#L732 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 14599#L742 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 14795#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 15918#L1553 assume !(0 != activate_threads_~tmp___6~0#1); 15859#L1553-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 14702#L750 assume !(1 == ~t8_pc~0); 14395#L750-2 is_transmit8_triggered_~__retres1~8#1 := 0; 14394#L761 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 14900#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 15928#L1561 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 15042#L1561-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 15043#L769 assume 1 == ~t9_pc~0; 15583#L770 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 14560#L780 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 14561#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 14785#L1569 assume !(0 != activate_threads_~tmp___8~0#1); 15795#L1569-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 15878#L788 assume !(1 == ~t10_pc~0); 15446#L788-2 is_transmit10_triggered_~__retres1~10#1 := 0; 15447#L799 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 16000#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 15952#L1577 assume !(0 != activate_threads_~tmp___9~0#1); 14698#L1577-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 14699#L807 assume 1 == ~t11_pc~0; 15884#L808 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 15461#L818 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 15621#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 16058#L1585 assume !(0 != activate_threads_~tmp___10~0#1); 16153#L1585-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 15983#L826 assume !(1 == ~t12_pc~0); 15113#L826-2 is_transmit12_triggered_~__retres1~12#1 := 0; 15114#L837 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 14439#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 14440#L1593 assume !(0 != activate_threads_~tmp___11~0#1); 15269#L1593-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 15181#L1344 assume !(1 == ~M_E~0); 15182#L1344-2 assume !(1 == ~T1_E~0); 15312#L1349-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 15486#L1354-1 assume !(1 == ~T3_E~0); 15487#L1359-1 assume !(1 == ~T4_E~0); 15870#L1364-1 assume !(1 == ~T5_E~0); 14812#L1369-1 assume !(1 == ~T6_E~0); 14813#L1374-1 assume !(1 == ~T7_E~0); 15493#L1379-1 assume !(1 == ~T8_E~0); 15494#L1384-1 assume !(1 == ~T9_E~0); 15569#L1389-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 16016#L1394-1 assume !(1 == ~T11_E~0); 16017#L1399-1 assume !(1 == ~T12_E~0); 16098#L1404-1 assume !(1 == ~E_M~0); 14939#L1409-1 assume !(1 == ~E_1~0); 14940#L1414-1 assume !(1 == ~E_2~0); 15774#L1419-1 assume !(1 == ~E_3~0); 14573#L1424-1 assume !(1 == ~E_4~0); 14574#L1429-1 assume 1 == ~E_5~0;~E_5~0 := 2; 15502#L1434-1 assume !(1 == ~E_6~0); 16031#L1439-1 assume !(1 == ~E_7~0); 14617#L1444-1 assume !(1 == ~E_8~0); 14618#L1449-1 assume !(1 == ~E_9~0); 15047#L1454-1 assume !(1 == ~E_10~0); 15048#L1459-1 assume !(1 == ~E_11~0); 15599#L1464-1 assume !(1 == ~E_12~0); 15600#L1469-1 assume { :end_inline_reset_delta_events } true; 15649#L1815-2 [2022-12-13 13:22:09,357 INFO L750 eck$LassoCheckResult]: Loop: 15649#L1815-2 assume !false; 15796#L1816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 15463#L1181 assume !false; 15533#L1004 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 15484#L926 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 14367#L993 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 15084#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 15628#L1008 assume !(0 != eval_~tmp~0#1); 15324#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 14947#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 14948#L1206-3 assume 0 == ~M_E~0;~M_E~0 := 1; 16148#L1206-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 15598#L1211-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 14686#L1216-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 14687#L1221-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 15291#L1226-3 assume !(0 == ~T5_E~0); 14756#L1231-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 14757#L1236-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 15085#L1241-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 16068#L1246-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 15967#L1251-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 15708#L1256-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 14708#L1261-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 14709#L1266-3 assume !(0 == ~E_M~0); 14754#L1271-3 assume 0 == ~E_1~0;~E_1~0 := 1; 14755#L1276-3 assume 0 == ~E_2~0;~E_2~0 := 1; 15232#L1281-3 assume 0 == ~E_3~0;~E_3~0 := 1; 15233#L1286-3 assume 0 == ~E_4~0;~E_4~0 := 1; 15771#L1291-3 assume 0 == ~E_5~0;~E_5~0 := 1; 15772#L1296-3 assume 0 == ~E_6~0;~E_6~0 := 1; 16134#L1301-3 assume 0 == ~E_7~0;~E_7~0 := 1; 16095#L1306-3 assume !(0 == ~E_8~0); 15352#L1311-3 assume 0 == ~E_9~0;~E_9~0 := 1; 14632#L1316-3 assume 0 == ~E_10~0;~E_10~0 := 1; 14633#L1321-3 assume 0 == ~E_11~0;~E_11~0 := 1; 14710#L1326-3 assume 0 == ~E_12~0;~E_12~0 := 1; 15455#L1331-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 15782#L598-42 assume !(1 == ~m_pc~0); 15783#L598-44 is_master_triggered_~__retres1~0#1 := 0; 15899#L609-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 15115#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 15116#L1497-42 assume !(0 != activate_threads_~tmp~1#1); 16096#L1497-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 15509#L617-42 assume 1 == ~t1_pc~0; 15285#L618-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 15154#L628-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 15155#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 16093#L1505-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 14860#L1505-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14861#L636-42 assume 1 == ~t2_pc~0; 16073#L637-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 15323#L647-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 15400#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 15401#L1513-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 15866#L1513-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 15731#L655-42 assume !(1 == ~t3_pc~0); 15298#L655-44 is_transmit3_triggered_~__retres1~3#1 := 0; 15299#L666-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 15809#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 15810#L1521-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 15998#L1521-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 15934#L674-42 assume !(1 == ~t4_pc~0); 15716#L674-44 is_transmit4_triggered_~__retres1~4#1 := 0; 15637#L685-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 15638#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 15841#L1529-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 15428#L1529-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 15429#L693-42 assume 1 == ~t5_pc~0; 15696#L694-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 15697#L704-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 15482#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 15483#L1537-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 15752#L1537-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 15057#L712-42 assume !(1 == ~t6_pc~0); 15058#L712-44 is_transmit6_triggered_~__retres1~6#1 := 0; 15370#L723-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 14700#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 14701#L1545-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 15163#L1545-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 15164#L731-42 assume 1 == ~t7_pc~0; 15027#L732-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 14853#L742-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 15505#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 15074#L1553-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 15075#L1553-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 14764#L750-42 assume 1 == ~t8_pc~0; 14765#L751-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 15339#L761-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 15644#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 14647#L1561-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 14648#L1561-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 15427#L769-42 assume 1 == ~t9_pc~0; 15256#L770-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 15257#L780-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 15939#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 16137#L1569-42 assume !(0 != activate_threads_~tmp___8~0#1); 14862#L1569-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 14863#L788-42 assume 1 == ~t10_pc~0; 15435#L789-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 15663#L799-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 15634#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 15635#L1577-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 16146#L1577-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 16121#L807-42 assume !(1 == ~t11_pc~0); 14482#L807-44 is_transmit11_triggered_~__retres1~11#1 := 0; 14483#L818-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 15343#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 14604#L1585-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 14605#L1585-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 14857#L826-42 assume 1 == ~t12_pc~0; 14858#L827-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 15063#L837-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 15451#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 14847#L1593-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 14848#L1593-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 15712#L1344-3 assume 1 == ~M_E~0;~M_E~0 := 2; 15713#L1344-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 15639#L1349-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 15016#L1354-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 15017#L1359-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 15653#L1364-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 16124#L1369-3 assume !(1 == ~T6_E~0); 16030#L1374-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 14773#L1379-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 14774#L1384-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 15014#L1389-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 15015#L1394-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 15304#L1399-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 16036#L1404-3 assume 1 == ~E_M~0;~E_M~0 := 2; 16005#L1409-3 assume !(1 == ~E_1~0); 16006#L1414-3 assume 1 == ~E_2~0;~E_2~0 := 2; 16067#L1419-3 assume 1 == ~E_3~0;~E_3~0 := 2; 15848#L1424-3 assume 1 == ~E_4~0;~E_4~0 := 2; 14663#L1429-3 assume 1 == ~E_5~0;~E_5~0 := 2; 14664#L1434-3 assume 1 == ~E_6~0;~E_6~0 := 2; 15652#L1439-3 assume 1 == ~E_7~0;~E_7~0 := 2; 14610#L1444-3 assume 1 == ~E_8~0;~E_8~0 := 2; 14611#L1449-3 assume !(1 == ~E_9~0); 14716#L1454-3 assume 1 == ~E_10~0;~E_10~0 := 2; 15646#L1459-3 assume 1 == ~E_11~0;~E_11~0 := 2; 15647#L1464-3 assume 1 == ~E_12~0;~E_12~0 := 2; 16029#L1469-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 15513#L926-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 14528#L993-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 14529#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 14692#L1834 assume !(0 == start_simulation_~tmp~3#1); 15759#L1834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 15776#L926-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 15217#L993-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 14416#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 14417#L1789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 16019#L1796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 16015#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 15849#L1847 assume !(0 != start_simulation_~tmp___0~1#1); 15649#L1815-2 [2022-12-13 13:22:09,357 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 13:22:09,357 INFO L85 PathProgramCache]: Analyzing trace with hash -1259693268, now seen corresponding path program 1 times [2022-12-13 13:22:09,358 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 13:22:09,358 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [776503629] [2022-12-13 13:22:09,358 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 13:22:09,358 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 13:22:09,366 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 13:22:09,388 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 13:22:09,388 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 13:22:09,389 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [776503629] [2022-12-13 13:22:09,389 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [776503629] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 13:22:09,389 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 13:22:09,389 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 13:22:09,389 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [29317888] [2022-12-13 13:22:09,389 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 13:22:09,390 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 13:22:09,390 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 13:22:09,390 INFO L85 PathProgramCache]: Analyzing trace with hash 1643048980, now seen corresponding path program 1 times [2022-12-13 13:22:09,390 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 13:22:09,391 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [643206675] [2022-12-13 13:22:09,391 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 13:22:09,391 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 13:22:09,402 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 13:22:09,432 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 13:22:09,432 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 13:22:09,432 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [643206675] [2022-12-13 13:22:09,433 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [643206675] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 13:22:09,433 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 13:22:09,433 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 13:22:09,433 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [981060311] [2022-12-13 13:22:09,433 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 13:22:09,433 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 13:22:09,434 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 13:22:09,434 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 13:22:09,434 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 13:22:09,434 INFO L87 Difference]: Start difference. First operand 1790 states and 2652 transitions. cyclomatic complexity: 863 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 13:22:09,460 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 13:22:09,460 INFO L93 Difference]: Finished difference Result 1790 states and 2651 transitions. [2022-12-13 13:22:09,460 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1790 states and 2651 transitions. [2022-12-13 13:22:09,466 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1627 [2022-12-13 13:22:09,470 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1790 states to 1790 states and 2651 transitions. [2022-12-13 13:22:09,471 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1790 [2022-12-13 13:22:09,471 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1790 [2022-12-13 13:22:09,472 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1790 states and 2651 transitions. [2022-12-13 13:22:09,473 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 13:22:09,473 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1790 states and 2651 transitions. [2022-12-13 13:22:09,475 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1790 states and 2651 transitions. [2022-12-13 13:22:09,489 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1790 to 1790. [2022-12-13 13:22:09,491 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1790 states, 1790 states have (on average 1.4810055865921787) internal successors, (2651), 1789 states have internal predecessors, (2651), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 13:22:09,494 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1790 states to 1790 states and 2651 transitions. [2022-12-13 13:22:09,494 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1790 states and 2651 transitions. [2022-12-13 13:22:09,494 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 13:22:09,495 INFO L428 stractBuchiCegarLoop]: Abstraction has 1790 states and 2651 transitions. [2022-12-13 13:22:09,495 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2022-12-13 13:22:09,495 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1790 states and 2651 transitions. [2022-12-13 13:22:09,512 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1627 [2022-12-13 13:22:09,512 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 13:22:09,512 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 13:22:09,514 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 13:22:09,514 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 13:22:09,514 INFO L748 eck$LassoCheckResult]: Stem: 18195#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 18196#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 19112#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 19113#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 19567#L853 assume 1 == ~m_i~0;~m_st~0 := 0; 19437#L853-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 18476#L858-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 17951#L863-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 17952#L868-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 19207#L873-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 19345#L878-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 19728#L883-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 19729#L888-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 18695#L893-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 18696#L898-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 19235#L903-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 19157#L908-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 19158#L913-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 19308#L1206 assume !(0 == ~M_E~0); 18676#L1206-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 18677#L1211-1 assume !(0 == ~T2_E~0); 19561#L1216-1 assume !(0 == ~T3_E~0); 18453#L1221-1 assume !(0 == ~T4_E~0); 18454#L1226-1 assume !(0 == ~T5_E~0); 18129#L1231-1 assume !(0 == ~T6_E~0); 18130#L1236-1 assume !(0 == ~T7_E~0); 19601#L1241-1 assume !(0 == ~T8_E~0); 18523#L1246-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 18524#L1251-1 assume !(0 == ~T10_E~0); 18745#L1256-1 assume !(0 == ~T11_E~0); 17961#L1261-1 assume !(0 == ~T12_E~0); 17962#L1266-1 assume !(0 == ~E_M~0); 19714#L1271-1 assume !(0 == ~E_1~0); 19335#L1276-1 assume !(0 == ~E_2~0); 19336#L1281-1 assume !(0 == ~E_3~0); 19266#L1286-1 assume 0 == ~E_4~0;~E_4~0 := 1; 18356#L1291-1 assume !(0 == ~E_5~0); 18357#L1296-1 assume !(0 == ~E_6~0); 19067#L1301-1 assume !(0 == ~E_7~0); 19068#L1306-1 assume !(0 == ~E_8~0); 19500#L1311-1 assume !(0 == ~E_9~0); 18316#L1316-1 assume !(0 == ~E_10~0); 18317#L1321-1 assume !(0 == ~E_11~0); 19082#L1326-1 assume 0 == ~E_12~0;~E_12~0 := 1; 18183#L1331-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 18184#L598 assume 1 == ~m_pc~0; 18231#L599 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 18232#L609 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 18965#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 18966#L1497 assume !(0 != activate_threads_~tmp~1#1); 19677#L1497-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 19625#L617 assume !(1 == ~t1_pc~0); 18545#L617-2 is_transmit1_triggered_~__retres1~1#1 := 0; 18546#L628 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 19416#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 19417#L1505 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 19174#L1505-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 19175#L636 assume 1 == ~t2_pc~0; 18514#L637 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 18515#L647 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 18338#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 18339#L1513 assume !(0 != activate_threads_~tmp___1~0#1); 19206#L1513-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 18864#L655 assume !(1 == ~t3_pc~0); 18865#L655-2 is_transmit3_triggered_~__retres1~3#1 := 0; 19586#L666 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 19405#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 19406#L1521 assume !(0 != activate_threads_~tmp___2~0#1); 19715#L1521-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19716#L674 assume 1 == ~t4_pc~0; 18048#L675 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 18049#L685 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 18073#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 18074#L1529 assume !(0 != activate_threads_~tmp___3~0#1); 18342#L1529-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 18862#L693 assume !(1 == ~t5_pc~0); 19018#L693-2 is_transmit5_triggered_~__retres1~5#1 := 0; 18680#L704 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 18681#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 19502#L1537 assume !(0 != activate_threads_~tmp___4~0#1); 18760#L1537-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 18697#L712 assume 1 == ~t6_pc~0; 18698#L713 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 19116#L723 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 18326#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 18327#L1545 assume !(0 != activate_threads_~tmp___5~0#1); 19223#L1545-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 19216#L731 assume 1 == ~t7_pc~0; 18185#L732 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 18186#L742 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 18382#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 19505#L1553 assume !(0 != activate_threads_~tmp___6~0#1); 19447#L1553-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 18289#L750 assume !(1 == ~t8_pc~0); 17982#L750-2 is_transmit8_triggered_~__retres1~8#1 := 0; 17981#L761 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 18487#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 19515#L1561 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 18629#L1561-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 18630#L769 assume 1 == ~t9_pc~0; 19172#L770 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 18147#L780 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 18148#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 18372#L1569 assume !(0 != activate_threads_~tmp___8~0#1); 19382#L1569-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 19465#L788 assume !(1 == ~t10_pc~0); 19033#L788-2 is_transmit10_triggered_~__retres1~10#1 := 0; 19034#L799 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 19587#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 19540#L1577 assume !(0 != activate_threads_~tmp___9~0#1); 18285#L1577-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 18286#L807 assume 1 == ~t11_pc~0; 19471#L808 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 19048#L818 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 19208#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 19645#L1585 assume !(0 != activate_threads_~tmp___10~0#1); 19740#L1585-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 19570#L826 assume !(1 == ~t12_pc~0); 18700#L826-2 is_transmit12_triggered_~__retres1~12#1 := 0; 18701#L837 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 18026#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 18027#L1593 assume !(0 != activate_threads_~tmp___11~0#1); 18856#L1593-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 18768#L1344 assume !(1 == ~M_E~0); 18769#L1344-2 assume !(1 == ~T1_E~0); 18899#L1349-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 19075#L1354-1 assume !(1 == ~T3_E~0); 19076#L1359-1 assume !(1 == ~T4_E~0); 19457#L1364-1 assume !(1 == ~T5_E~0); 18399#L1369-1 assume !(1 == ~T6_E~0); 18400#L1374-1 assume !(1 == ~T7_E~0); 19080#L1379-1 assume !(1 == ~T8_E~0); 19081#L1384-1 assume !(1 == ~T9_E~0); 19156#L1389-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 19603#L1394-1 assume !(1 == ~T11_E~0); 19604#L1399-1 assume !(1 == ~T12_E~0); 19685#L1404-1 assume !(1 == ~E_M~0); 18526#L1409-1 assume !(1 == ~E_1~0); 18527#L1414-1 assume !(1 == ~E_2~0); 19361#L1419-1 assume !(1 == ~E_3~0); 18160#L1424-1 assume !(1 == ~E_4~0); 18161#L1429-1 assume 1 == ~E_5~0;~E_5~0 := 2; 19091#L1434-1 assume !(1 == ~E_6~0); 19618#L1439-1 assume !(1 == ~E_7~0); 18204#L1444-1 assume !(1 == ~E_8~0); 18205#L1449-1 assume !(1 == ~E_9~0); 18635#L1454-1 assume !(1 == ~E_10~0); 18636#L1459-1 assume !(1 == ~E_11~0); 19186#L1464-1 assume !(1 == ~E_12~0); 19187#L1469-1 assume { :end_inline_reset_delta_events } true; 19236#L1815-2 [2022-12-13 13:22:09,515 INFO L750 eck$LassoCheckResult]: Loop: 19236#L1815-2 assume !false; 19383#L1816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 19050#L1181 assume !false; 19120#L1004 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 19071#L926 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 17954#L993 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 18672#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 19215#L1008 assume !(0 != eval_~tmp~0#1); 18911#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 18536#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 18537#L1206-3 assume 0 == ~M_E~0;~M_E~0 := 1; 19735#L1206-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 19185#L1211-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 18273#L1216-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 18274#L1221-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 18878#L1226-3 assume !(0 == ~T5_E~0); 18343#L1231-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 18344#L1236-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 18671#L1241-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 19655#L1246-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 19554#L1251-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 19295#L1256-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 18295#L1261-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 18296#L1266-3 assume !(0 == ~E_M~0); 18340#L1271-3 assume 0 == ~E_1~0;~E_1~0 := 1; 18341#L1276-3 assume 0 == ~E_2~0;~E_2~0 := 1; 18819#L1281-3 assume 0 == ~E_3~0;~E_3~0 := 1; 18820#L1286-3 assume 0 == ~E_4~0;~E_4~0 := 1; 19358#L1291-3 assume 0 == ~E_5~0;~E_5~0 := 1; 19359#L1296-3 assume 0 == ~E_6~0;~E_6~0 := 1; 19721#L1301-3 assume 0 == ~E_7~0;~E_7~0 := 1; 19682#L1306-3 assume !(0 == ~E_8~0); 18939#L1311-3 assume 0 == ~E_9~0;~E_9~0 := 1; 18219#L1316-3 assume 0 == ~E_10~0;~E_10~0 := 1; 18220#L1321-3 assume 0 == ~E_11~0;~E_11~0 := 1; 18297#L1326-3 assume 0 == ~E_12~0;~E_12~0 := 1; 19041#L1331-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 19369#L598-42 assume !(1 == ~m_pc~0); 19370#L598-44 is_master_triggered_~__retres1~0#1 := 0; 19486#L609-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 18702#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 18703#L1497-42 assume !(0 != activate_threads_~tmp~1#1); 19683#L1497-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 19096#L617-42 assume 1 == ~t1_pc~0; 18872#L618-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 18741#L628-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 18742#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 19680#L1505-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 18447#L1505-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 18448#L636-42 assume 1 == ~t2_pc~0; 19660#L637-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 18910#L647-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 18987#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 18988#L1513-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 19453#L1513-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 19318#L655-42 assume !(1 == ~t3_pc~0); 18885#L655-44 is_transmit3_triggered_~__retres1~3#1 := 0; 18886#L666-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 19396#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 19397#L1521-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 19585#L1521-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19521#L674-42 assume 1 == ~t4_pc~0; 19522#L675-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 19224#L685-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 19225#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 19428#L1529-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 19015#L1529-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 19016#L693-42 assume 1 == ~t5_pc~0; 19283#L694-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 19284#L704-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 19069#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 19070#L1537-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 19339#L1537-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 18644#L712-42 assume !(1 == ~t6_pc~0); 18645#L712-44 is_transmit6_triggered_~__retres1~6#1 := 0; 18957#L723-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 18287#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 18288#L1545-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 18750#L1545-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 18751#L731-42 assume 1 == ~t7_pc~0; 18614#L732-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 18440#L742-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 19092#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 18661#L1553-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 18662#L1553-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 18351#L750-42 assume 1 == ~t8_pc~0; 18352#L751-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 18926#L761-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 19231#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 18234#L1561-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 18235#L1561-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 19014#L769-42 assume 1 == ~t9_pc~0; 18843#L770-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 18844#L780-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 19526#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 19724#L1569-42 assume !(0 != activate_threads_~tmp___8~0#1); 18449#L1569-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 18450#L788-42 assume 1 == ~t10_pc~0; 19022#L789-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 19250#L799-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 19221#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 19222#L1577-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 19733#L1577-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 19708#L807-42 assume 1 == ~t11_pc~0; 19378#L808-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 18070#L818-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 18930#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 18191#L1585-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 18192#L1585-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 18444#L826-42 assume 1 == ~t12_pc~0; 18445#L827-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 18650#L837-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 19038#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 18434#L1593-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 18435#L1593-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19299#L1344-3 assume 1 == ~M_E~0;~M_E~0 := 2; 19300#L1344-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 19226#L1349-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 18603#L1354-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 18604#L1359-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 19240#L1364-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 19711#L1369-3 assume !(1 == ~T6_E~0); 19617#L1374-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 18360#L1379-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 18361#L1384-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 18601#L1389-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 18602#L1394-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 18891#L1399-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 19623#L1404-3 assume 1 == ~E_M~0;~E_M~0 := 2; 19592#L1409-3 assume !(1 == ~E_1~0); 19593#L1414-3 assume 1 == ~E_2~0;~E_2~0 := 2; 19654#L1419-3 assume 1 == ~E_3~0;~E_3~0 := 2; 19435#L1424-3 assume 1 == ~E_4~0;~E_4~0 := 2; 18250#L1429-3 assume 1 == ~E_5~0;~E_5~0 := 2; 18251#L1434-3 assume 1 == ~E_6~0;~E_6~0 := 2; 19239#L1439-3 assume 1 == ~E_7~0;~E_7~0 := 2; 18197#L1444-3 assume 1 == ~E_8~0;~E_8~0 := 2; 18198#L1449-3 assume !(1 == ~E_9~0); 18303#L1454-3 assume 1 == ~E_10~0;~E_10~0 := 2; 19233#L1459-3 assume 1 == ~E_11~0;~E_11~0 := 2; 19234#L1464-3 assume 1 == ~E_12~0;~E_12~0 := 2; 19616#L1469-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 19100#L926-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 18115#L993-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 18116#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 18279#L1834 assume !(0 == start_simulation_~tmp~3#1); 19346#L1834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 19363#L926-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 18804#L993-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 18003#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 18004#L1789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 19606#L1796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 19602#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 19436#L1847 assume !(0 != start_simulation_~tmp___0~1#1); 19236#L1815-2 [2022-12-13 13:22:09,515 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 13:22:09,516 INFO L85 PathProgramCache]: Analyzing trace with hash -719263762, now seen corresponding path program 1 times [2022-12-13 13:22:09,516 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 13:22:09,516 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2044340211] [2022-12-13 13:22:09,516 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 13:22:09,516 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 13:22:09,527 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 13:22:09,554 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 13:22:09,554 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 13:22:09,554 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2044340211] [2022-12-13 13:22:09,555 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2044340211] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 13:22:09,555 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 13:22:09,555 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 13:22:09,555 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1300032396] [2022-12-13 13:22:09,555 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 13:22:09,556 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 13:22:09,556 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 13:22:09,556 INFO L85 PathProgramCache]: Analyzing trace with hash -1668262062, now seen corresponding path program 1 times [2022-12-13 13:22:09,557 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 13:22:09,557 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [927990986] [2022-12-13 13:22:09,557 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 13:22:09,557 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 13:22:09,570 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 13:22:09,606 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 13:22:09,607 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 13:22:09,607 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [927990986] [2022-12-13 13:22:09,607 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [927990986] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 13:22:09,607 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 13:22:09,607 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 13:22:09,607 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1992760164] [2022-12-13 13:22:09,608 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 13:22:09,608 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 13:22:09,608 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 13:22:09,609 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 13:22:09,609 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 13:22:09,609 INFO L87 Difference]: Start difference. First operand 1790 states and 2651 transitions. cyclomatic complexity: 862 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 13:22:09,636 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 13:22:09,636 INFO L93 Difference]: Finished difference Result 1790 states and 2650 transitions. [2022-12-13 13:22:09,637 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1790 states and 2650 transitions. [2022-12-13 13:22:09,641 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1627 [2022-12-13 13:22:09,646 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1790 states to 1790 states and 2650 transitions. [2022-12-13 13:22:09,646 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1790 [2022-12-13 13:22:09,647 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1790 [2022-12-13 13:22:09,647 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1790 states and 2650 transitions. [2022-12-13 13:22:09,648 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 13:22:09,649 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1790 states and 2650 transitions. [2022-12-13 13:22:09,650 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1790 states and 2650 transitions. [2022-12-13 13:22:09,663 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1790 to 1790. [2022-12-13 13:22:09,665 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1790 states, 1790 states have (on average 1.4804469273743017) internal successors, (2650), 1789 states have internal predecessors, (2650), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 13:22:09,668 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1790 states to 1790 states and 2650 transitions. [2022-12-13 13:22:09,668 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1790 states and 2650 transitions. [2022-12-13 13:22:09,668 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 13:22:09,669 INFO L428 stractBuchiCegarLoop]: Abstraction has 1790 states and 2650 transitions. [2022-12-13 13:22:09,669 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2022-12-13 13:22:09,669 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1790 states and 2650 transitions. [2022-12-13 13:22:09,676 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1627 [2022-12-13 13:22:09,676 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 13:22:09,676 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 13:22:09,677 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 13:22:09,678 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 13:22:09,678 INFO L748 eck$LassoCheckResult]: Stem: 21782#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 21783#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 22698#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 22699#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 23154#L853 assume 1 == ~m_i~0;~m_st~0 := 0; 23024#L853-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 22063#L858-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 21538#L863-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 21539#L868-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 22794#L873-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 22932#L878-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 23315#L883-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 23316#L888-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 22282#L893-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 22283#L898-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 22822#L903-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 22744#L908-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 22745#L913-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 22895#L1206 assume !(0 == ~M_E~0); 22263#L1206-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 22264#L1211-1 assume !(0 == ~T2_E~0); 23148#L1216-1 assume !(0 == ~T3_E~0); 22040#L1221-1 assume !(0 == ~T4_E~0); 22041#L1226-1 assume !(0 == ~T5_E~0); 21716#L1231-1 assume !(0 == ~T6_E~0); 21717#L1236-1 assume !(0 == ~T7_E~0); 23188#L1241-1 assume !(0 == ~T8_E~0); 22110#L1246-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 22111#L1251-1 assume !(0 == ~T10_E~0); 22332#L1256-1 assume !(0 == ~T11_E~0); 21548#L1261-1 assume !(0 == ~T12_E~0); 21549#L1266-1 assume !(0 == ~E_M~0); 23301#L1271-1 assume !(0 == ~E_1~0); 22922#L1276-1 assume !(0 == ~E_2~0); 22923#L1281-1 assume !(0 == ~E_3~0); 22853#L1286-1 assume 0 == ~E_4~0;~E_4~0 := 1; 21943#L1291-1 assume !(0 == ~E_5~0); 21944#L1296-1 assume !(0 == ~E_6~0); 22654#L1301-1 assume !(0 == ~E_7~0); 22655#L1306-1 assume !(0 == ~E_8~0); 23087#L1311-1 assume !(0 == ~E_9~0); 21903#L1316-1 assume !(0 == ~E_10~0); 21904#L1321-1 assume !(0 == ~E_11~0); 22669#L1326-1 assume 0 == ~E_12~0;~E_12~0 := 1; 21770#L1331-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 21771#L598 assume 1 == ~m_pc~0; 21818#L599 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 21819#L609 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 22552#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 22553#L1497 assume !(0 != activate_threads_~tmp~1#1); 23264#L1497-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 23212#L617 assume !(1 == ~t1_pc~0); 22132#L617-2 is_transmit1_triggered_~__retres1~1#1 := 0; 22133#L628 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 23003#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 23004#L1505 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 22761#L1505-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 22762#L636 assume 1 == ~t2_pc~0; 22101#L637 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 22102#L647 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 21925#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 21926#L1513 assume !(0 != activate_threads_~tmp___1~0#1); 22793#L1513-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 22450#L655 assume !(1 == ~t3_pc~0); 22451#L655-2 is_transmit3_triggered_~__retres1~3#1 := 0; 23173#L666 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 22992#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 22993#L1521 assume !(0 != activate_threads_~tmp___2~0#1); 23302#L1521-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 23303#L674 assume 1 == ~t4_pc~0; 21635#L675 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 21636#L685 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 21660#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 21661#L1529 assume !(0 != activate_threads_~tmp___3~0#1); 21927#L1529-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 22449#L693 assume !(1 == ~t5_pc~0); 22605#L693-2 is_transmit5_triggered_~__retres1~5#1 := 0; 22267#L704 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 22268#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 23089#L1537 assume !(0 != activate_threads_~tmp___4~0#1); 22347#L1537-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 22284#L712 assume 1 == ~t6_pc~0; 22285#L713 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 22703#L723 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 21913#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 21914#L1545 assume !(0 != activate_threads_~tmp___5~0#1); 22810#L1545-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 22803#L731 assume 1 == ~t7_pc~0; 21772#L732 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 21773#L742 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 21969#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 23092#L1553 assume !(0 != activate_threads_~tmp___6~0#1); 23033#L1553-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 21876#L750 assume !(1 == ~t8_pc~0); 21569#L750-2 is_transmit8_triggered_~__retres1~8#1 := 0; 21568#L761 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 22074#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 23102#L1561 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 22216#L1561-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 22217#L769 assume 1 == ~t9_pc~0; 22759#L770 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 21734#L780 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 21735#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 21959#L1569 assume !(0 != activate_threads_~tmp___8~0#1); 22969#L1569-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 23052#L788 assume !(1 == ~t10_pc~0); 22620#L788-2 is_transmit10_triggered_~__retres1~10#1 := 0; 22621#L799 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 23174#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 23127#L1577 assume !(0 != activate_threads_~tmp___9~0#1); 21872#L1577-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 21873#L807 assume 1 == ~t11_pc~0; 23058#L808 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 22635#L818 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 22795#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 23232#L1585 assume !(0 != activate_threads_~tmp___10~0#1); 23327#L1585-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 23157#L826 assume !(1 == ~t12_pc~0); 22287#L826-2 is_transmit12_triggered_~__retres1~12#1 := 0; 22288#L837 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 21613#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 21614#L1593 assume !(0 != activate_threads_~tmp___11~0#1); 22443#L1593-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 22355#L1344 assume !(1 == ~M_E~0); 22356#L1344-2 assume !(1 == ~T1_E~0); 22486#L1349-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 22662#L1354-1 assume !(1 == ~T3_E~0); 22663#L1359-1 assume !(1 == ~T4_E~0); 23044#L1364-1 assume !(1 == ~T5_E~0); 21986#L1369-1 assume !(1 == ~T6_E~0); 21987#L1374-1 assume !(1 == ~T7_E~0); 22667#L1379-1 assume !(1 == ~T8_E~0); 22668#L1384-1 assume !(1 == ~T9_E~0); 22743#L1389-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 23190#L1394-1 assume !(1 == ~T11_E~0); 23191#L1399-1 assume !(1 == ~T12_E~0); 23272#L1404-1 assume !(1 == ~E_M~0); 22113#L1409-1 assume !(1 == ~E_1~0); 22114#L1414-1 assume !(1 == ~E_2~0); 22948#L1419-1 assume !(1 == ~E_3~0); 21747#L1424-1 assume !(1 == ~E_4~0); 21748#L1429-1 assume 1 == ~E_5~0;~E_5~0 := 2; 22678#L1434-1 assume !(1 == ~E_6~0); 23205#L1439-1 assume !(1 == ~E_7~0); 21791#L1444-1 assume !(1 == ~E_8~0); 21792#L1449-1 assume !(1 == ~E_9~0); 22222#L1454-1 assume !(1 == ~E_10~0); 22223#L1459-1 assume !(1 == ~E_11~0); 22773#L1464-1 assume !(1 == ~E_12~0); 22774#L1469-1 assume { :end_inline_reset_delta_events } true; 22823#L1815-2 [2022-12-13 13:22:09,678 INFO L750 eck$LassoCheckResult]: Loop: 22823#L1815-2 assume !false; 22970#L1816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 22637#L1181 assume !false; 22707#L1004 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 22658#L926 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 21541#L993 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 22258#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 22802#L1008 assume !(0 != eval_~tmp~0#1); 22498#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 22123#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 22124#L1206-3 assume 0 == ~M_E~0;~M_E~0 := 1; 23322#L1206-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 22772#L1211-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 21860#L1216-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 21861#L1221-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 22465#L1226-3 assume !(0 == ~T5_E~0); 21930#L1231-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 21931#L1236-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 22259#L1241-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 23244#L1246-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 23141#L1251-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 22882#L1256-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 21884#L1261-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 21885#L1266-3 assume !(0 == ~E_M~0); 21928#L1271-3 assume 0 == ~E_1~0;~E_1~0 := 1; 21929#L1276-3 assume 0 == ~E_2~0;~E_2~0 := 1; 22406#L1281-3 assume 0 == ~E_3~0;~E_3~0 := 1; 22407#L1286-3 assume 0 == ~E_4~0;~E_4~0 := 1; 22945#L1291-3 assume 0 == ~E_5~0;~E_5~0 := 1; 22946#L1296-3 assume 0 == ~E_6~0;~E_6~0 := 1; 23308#L1301-3 assume 0 == ~E_7~0;~E_7~0 := 1; 23269#L1306-3 assume !(0 == ~E_8~0); 22526#L1311-3 assume 0 == ~E_9~0;~E_9~0 := 1; 21806#L1316-3 assume 0 == ~E_10~0;~E_10~0 := 1; 21807#L1321-3 assume 0 == ~E_11~0;~E_11~0 := 1; 21886#L1326-3 assume 0 == ~E_12~0;~E_12~0 := 1; 22629#L1331-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 22957#L598-42 assume !(1 == ~m_pc~0); 22958#L598-44 is_master_triggered_~__retres1~0#1 := 0; 23073#L609-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 22289#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 22290#L1497-42 assume !(0 != activate_threads_~tmp~1#1); 23270#L1497-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 22683#L617-42 assume 1 == ~t1_pc~0; 22460#L618-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 22328#L628-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 22329#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 23267#L1505-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 22034#L1505-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 22035#L636-42 assume !(1 == ~t2_pc~0); 22495#L636-44 is_transmit2_triggered_~__retres1~2#1 := 0; 22496#L647-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 22574#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 22575#L1513-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 23040#L1513-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 22902#L655-42 assume 1 == ~t3_pc~0; 22903#L656-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 22472#L666-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 22981#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 22982#L1521-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 23172#L1521-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 23108#L674-42 assume 1 == ~t4_pc~0; 23109#L675-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 22811#L685-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 22812#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 23015#L1529-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 22602#L1529-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 22603#L693-42 assume 1 == ~t5_pc~0; 22870#L694-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 22871#L704-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 22656#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 22657#L1537-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 22926#L1537-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 22231#L712-42 assume !(1 == ~t6_pc~0); 22232#L712-44 is_transmit6_triggered_~__retres1~6#1 := 0; 22544#L723-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 21874#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 21875#L1545-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 22337#L1545-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 22338#L731-42 assume 1 == ~t7_pc~0; 22199#L732-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 22027#L742-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 22679#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 22247#L1553-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 22248#L1553-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 21938#L750-42 assume 1 == ~t8_pc~0; 21939#L751-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 22513#L761-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 22818#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 21821#L1561-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 21822#L1561-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 22601#L769-42 assume 1 == ~t9_pc~0; 22429#L770-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 22430#L780-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 23113#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 23311#L1569-42 assume !(0 != activate_threads_~tmp___8~0#1); 22036#L1569-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 22037#L788-42 assume 1 == ~t10_pc~0; 22609#L789-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 22837#L799-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 22808#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 22809#L1577-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 23320#L1577-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 23294#L807-42 assume 1 == ~t11_pc~0; 22965#L808-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 21657#L818-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 22517#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 21778#L1585-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 21779#L1585-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 22031#L826-42 assume 1 == ~t12_pc~0; 22032#L827-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 22237#L837-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 22622#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 22021#L1593-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 22022#L1593-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 22886#L1344-3 assume 1 == ~M_E~0;~M_E~0 := 2; 22887#L1344-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 22813#L1349-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 22190#L1354-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 22191#L1359-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 22827#L1364-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 23298#L1369-3 assume !(1 == ~T6_E~0); 23204#L1374-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 21945#L1379-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 21946#L1384-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 22188#L1389-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 22189#L1394-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 22478#L1399-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 23210#L1404-3 assume 1 == ~E_M~0;~E_M~0 := 2; 23179#L1409-3 assume !(1 == ~E_1~0); 23180#L1414-3 assume 1 == ~E_2~0;~E_2~0 := 2; 23241#L1419-3 assume 1 == ~E_3~0;~E_3~0 := 2; 23022#L1424-3 assume 1 == ~E_4~0;~E_4~0 := 2; 21837#L1429-3 assume 1 == ~E_5~0;~E_5~0 := 2; 21838#L1434-3 assume 1 == ~E_6~0;~E_6~0 := 2; 22826#L1439-3 assume 1 == ~E_7~0;~E_7~0 := 2; 21784#L1444-3 assume 1 == ~E_8~0;~E_8~0 := 2; 21785#L1449-3 assume !(1 == ~E_9~0); 21890#L1454-3 assume 1 == ~E_10~0;~E_10~0 := 2; 22820#L1459-3 assume 1 == ~E_11~0;~E_11~0 := 2; 22821#L1464-3 assume 1 == ~E_12~0;~E_12~0 := 2; 23203#L1469-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 22687#L926-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 21702#L993-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 21703#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 21866#L1834 assume !(0 == start_simulation_~tmp~3#1); 22933#L1834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 22950#L926-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 22391#L993-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 21590#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 21591#L1789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 23193#L1796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 23189#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 23023#L1847 assume !(0 != start_simulation_~tmp___0~1#1); 22823#L1815-2 [2022-12-13 13:22:09,678 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 13:22:09,678 INFO L85 PathProgramCache]: Analyzing trace with hash -563283220, now seen corresponding path program 1 times [2022-12-13 13:22:09,679 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 13:22:09,679 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1376054878] [2022-12-13 13:22:09,679 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 13:22:09,679 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 13:22:09,687 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 13:22:09,708 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 13:22:09,708 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 13:22:09,708 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1376054878] [2022-12-13 13:22:09,708 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1376054878] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 13:22:09,709 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 13:22:09,709 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 13:22:09,709 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1349329017] [2022-12-13 13:22:09,709 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 13:22:09,709 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 13:22:09,710 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 13:22:09,710 INFO L85 PathProgramCache]: Analyzing trace with hash 729764498, now seen corresponding path program 1 times [2022-12-13 13:22:09,710 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 13:22:09,710 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [286128470] [2022-12-13 13:22:09,710 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 13:22:09,710 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 13:22:09,720 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 13:22:09,749 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 13:22:09,749 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 13:22:09,749 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [286128470] [2022-12-13 13:22:09,749 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [286128470] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 13:22:09,749 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 13:22:09,750 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 13:22:09,750 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1560706816] [2022-12-13 13:22:09,750 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 13:22:09,750 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 13:22:09,750 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 13:22:09,751 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 13:22:09,751 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 13:22:09,751 INFO L87 Difference]: Start difference. First operand 1790 states and 2650 transitions. cyclomatic complexity: 861 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 13:22:09,774 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 13:22:09,774 INFO L93 Difference]: Finished difference Result 1790 states and 2649 transitions. [2022-12-13 13:22:09,774 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1790 states and 2649 transitions. [2022-12-13 13:22:09,779 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1627 [2022-12-13 13:22:09,784 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1790 states to 1790 states and 2649 transitions. [2022-12-13 13:22:09,784 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1790 [2022-12-13 13:22:09,785 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1790 [2022-12-13 13:22:09,785 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1790 states and 2649 transitions. [2022-12-13 13:22:09,787 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 13:22:09,787 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1790 states and 2649 transitions. [2022-12-13 13:22:09,789 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1790 states and 2649 transitions. [2022-12-13 13:22:09,801 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1790 to 1790. [2022-12-13 13:22:09,803 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1790 states, 1790 states have (on average 1.4798882681564245) internal successors, (2649), 1789 states have internal predecessors, (2649), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 13:22:09,806 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1790 states to 1790 states and 2649 transitions. [2022-12-13 13:22:09,806 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1790 states and 2649 transitions. [2022-12-13 13:22:09,806 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 13:22:09,807 INFO L428 stractBuchiCegarLoop]: Abstraction has 1790 states and 2649 transitions. [2022-12-13 13:22:09,807 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2022-12-13 13:22:09,807 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1790 states and 2649 transitions. [2022-12-13 13:22:09,813 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1627 [2022-12-13 13:22:09,813 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 13:22:09,814 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 13:22:09,815 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 13:22:09,815 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 13:22:09,816 INFO L748 eck$LassoCheckResult]: Stem: 25369#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 25370#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 26285#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 26286#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 26741#L853 assume 1 == ~m_i~0;~m_st~0 := 0; 26611#L853-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 25650#L858-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 25125#L863-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 25126#L868-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 26381#L873-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 26519#L878-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 26902#L883-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 26903#L888-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 25869#L893-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 25870#L898-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 26409#L903-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 26331#L908-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 26332#L913-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 26482#L1206 assume !(0 == ~M_E~0); 25850#L1206-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 25851#L1211-1 assume !(0 == ~T2_E~0); 26735#L1216-1 assume !(0 == ~T3_E~0); 25627#L1221-1 assume !(0 == ~T4_E~0); 25628#L1226-1 assume !(0 == ~T5_E~0); 25301#L1231-1 assume !(0 == ~T6_E~0); 25302#L1236-1 assume !(0 == ~T7_E~0); 26775#L1241-1 assume !(0 == ~T8_E~0); 25697#L1246-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 25698#L1251-1 assume !(0 == ~T10_E~0); 25919#L1256-1 assume !(0 == ~T11_E~0); 25135#L1261-1 assume !(0 == ~T12_E~0); 25136#L1266-1 assume !(0 == ~E_M~0); 26888#L1271-1 assume !(0 == ~E_1~0); 26509#L1276-1 assume !(0 == ~E_2~0); 26510#L1281-1 assume !(0 == ~E_3~0); 26438#L1286-1 assume 0 == ~E_4~0;~E_4~0 := 1; 25530#L1291-1 assume !(0 == ~E_5~0); 25531#L1296-1 assume !(0 == ~E_6~0); 26241#L1301-1 assume !(0 == ~E_7~0); 26242#L1306-1 assume !(0 == ~E_8~0); 26674#L1311-1 assume !(0 == ~E_9~0); 25490#L1316-1 assume !(0 == ~E_10~0); 25491#L1321-1 assume !(0 == ~E_11~0); 26256#L1326-1 assume 0 == ~E_12~0;~E_12~0 := 1; 25357#L1331-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 25358#L598 assume 1 == ~m_pc~0; 25405#L599 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 25406#L609 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 26139#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 26140#L1497 assume !(0 != activate_threads_~tmp~1#1); 26851#L1497-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 26799#L617 assume !(1 == ~t1_pc~0); 25719#L617-2 is_transmit1_triggered_~__retres1~1#1 := 0; 25720#L628 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 26590#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 26591#L1505 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 26348#L1505-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 26349#L636 assume 1 == ~t2_pc~0; 25688#L637 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 25689#L647 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 25512#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 25513#L1513 assume !(0 != activate_threads_~tmp___1~0#1); 26380#L1513-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 26037#L655 assume !(1 == ~t3_pc~0); 26038#L655-2 is_transmit3_triggered_~__retres1~3#1 := 0; 26760#L666 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 26579#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 26580#L1521 assume !(0 != activate_threads_~tmp___2~0#1); 26889#L1521-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 26890#L674 assume 1 == ~t4_pc~0; 25222#L675 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 25223#L685 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 25247#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 25248#L1529 assume !(0 != activate_threads_~tmp___3~0#1); 25514#L1529-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 26036#L693 assume !(1 == ~t5_pc~0); 26192#L693-2 is_transmit5_triggered_~__retres1~5#1 := 0; 25853#L704 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 25854#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 26676#L1537 assume !(0 != activate_threads_~tmp___4~0#1); 25934#L1537-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 25871#L712 assume 1 == ~t6_pc~0; 25872#L713 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 26290#L723 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 25500#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 25501#L1545 assume !(0 != activate_threads_~tmp___5~0#1); 26397#L1545-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 26390#L731 assume 1 == ~t7_pc~0; 25359#L732 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 25360#L742 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 25556#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 26679#L1553 assume !(0 != activate_threads_~tmp___6~0#1); 26620#L1553-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 25463#L750 assume !(1 == ~t8_pc~0); 25156#L750-2 is_transmit8_triggered_~__retres1~8#1 := 0; 25155#L761 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 25661#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 26689#L1561 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 25803#L1561-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 25804#L769 assume 1 == ~t9_pc~0; 26346#L770 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 25321#L780 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 25322#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 25546#L1569 assume !(0 != activate_threads_~tmp___8~0#1); 26556#L1569-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 26639#L788 assume !(1 == ~t10_pc~0); 26207#L788-2 is_transmit10_triggered_~__retres1~10#1 := 0; 26208#L799 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 26761#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 26713#L1577 assume !(0 != activate_threads_~tmp___9~0#1); 25459#L1577-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 25460#L807 assume 1 == ~t11_pc~0; 26645#L808 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 26222#L818 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 26382#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 26819#L1585 assume !(0 != activate_threads_~tmp___10~0#1); 26914#L1585-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 26744#L826 assume !(1 == ~t12_pc~0); 25874#L826-2 is_transmit12_triggered_~__retres1~12#1 := 0; 25875#L837 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 25200#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 25201#L1593 assume !(0 != activate_threads_~tmp___11~0#1); 26030#L1593-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 25942#L1344 assume !(1 == ~M_E~0); 25943#L1344-2 assume !(1 == ~T1_E~0); 26073#L1349-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 26249#L1354-1 assume !(1 == ~T3_E~0); 26250#L1359-1 assume !(1 == ~T4_E~0); 26631#L1364-1 assume !(1 == ~T5_E~0); 25573#L1369-1 assume !(1 == ~T6_E~0); 25574#L1374-1 assume !(1 == ~T7_E~0); 26254#L1379-1 assume !(1 == ~T8_E~0); 26255#L1384-1 assume !(1 == ~T9_E~0); 26330#L1389-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 26777#L1394-1 assume !(1 == ~T11_E~0); 26778#L1399-1 assume !(1 == ~T12_E~0); 26859#L1404-1 assume !(1 == ~E_M~0); 25700#L1409-1 assume !(1 == ~E_1~0); 25701#L1414-1 assume !(1 == ~E_2~0); 26535#L1419-1 assume !(1 == ~E_3~0); 25334#L1424-1 assume !(1 == ~E_4~0); 25335#L1429-1 assume 1 == ~E_5~0;~E_5~0 := 2; 26263#L1434-1 assume !(1 == ~E_6~0); 26792#L1439-1 assume !(1 == ~E_7~0); 25378#L1444-1 assume !(1 == ~E_8~0); 25379#L1449-1 assume !(1 == ~E_9~0); 25809#L1454-1 assume !(1 == ~E_10~0); 25810#L1459-1 assume !(1 == ~E_11~0); 26360#L1464-1 assume !(1 == ~E_12~0); 26361#L1469-1 assume { :end_inline_reset_delta_events } true; 26410#L1815-2 [2022-12-13 13:22:09,816 INFO L750 eck$LassoCheckResult]: Loop: 26410#L1815-2 assume !false; 26557#L1816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 26224#L1181 assume !false; 26294#L1004 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 26245#L926 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 25128#L993 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 25845#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 26389#L1008 assume !(0 != eval_~tmp~0#1); 26085#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 25710#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 25711#L1206-3 assume 0 == ~M_E~0;~M_E~0 := 1; 26909#L1206-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 26359#L1211-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 25447#L1216-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 25448#L1221-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 26052#L1226-3 assume !(0 == ~T5_E~0); 25517#L1231-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 25518#L1236-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 25846#L1241-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 26831#L1246-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 26728#L1251-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 26469#L1256-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 25469#L1261-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 25470#L1266-3 assume !(0 == ~E_M~0); 25515#L1271-3 assume 0 == ~E_1~0;~E_1~0 := 1; 25516#L1276-3 assume 0 == ~E_2~0;~E_2~0 := 1; 25993#L1281-3 assume 0 == ~E_3~0;~E_3~0 := 1; 25994#L1286-3 assume 0 == ~E_4~0;~E_4~0 := 1; 26532#L1291-3 assume 0 == ~E_5~0;~E_5~0 := 1; 26533#L1296-3 assume 0 == ~E_6~0;~E_6~0 := 1; 26895#L1301-3 assume 0 == ~E_7~0;~E_7~0 := 1; 26856#L1306-3 assume !(0 == ~E_8~0); 26113#L1311-3 assume 0 == ~E_9~0;~E_9~0 := 1; 25393#L1316-3 assume 0 == ~E_10~0;~E_10~0 := 1; 25394#L1321-3 assume 0 == ~E_11~0;~E_11~0 := 1; 25471#L1326-3 assume 0 == ~E_12~0;~E_12~0 := 1; 26216#L1331-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 26544#L598-42 assume !(1 == ~m_pc~0); 26545#L598-44 is_master_triggered_~__retres1~0#1 := 0; 26660#L609-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 25876#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 25877#L1497-42 assume !(0 != activate_threads_~tmp~1#1); 26857#L1497-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 26270#L617-42 assume !(1 == ~t1_pc~0); 26048#L617-44 is_transmit1_triggered_~__retres1~1#1 := 0; 25915#L628-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 25916#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 26854#L1505-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 25621#L1505-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 25622#L636-42 assume 1 == ~t2_pc~0; 26834#L637-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 26084#L647-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 26164#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 26165#L1513-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 26627#L1513-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 26492#L655-42 assume 1 == ~t3_pc~0; 26493#L656-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 26062#L666-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 26570#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 26571#L1521-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 26759#L1521-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 26695#L674-42 assume 1 == ~t4_pc~0; 26696#L675-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 26398#L685-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 26399#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 26602#L1529-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 26189#L1529-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 26190#L693-42 assume 1 == ~t5_pc~0; 26460#L694-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 26461#L704-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 26243#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 26244#L1537-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 26513#L1537-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 25818#L712-42 assume !(1 == ~t6_pc~0); 25819#L712-44 is_transmit6_triggered_~__retres1~6#1 := 0; 26132#L723-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 25461#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 25462#L1545-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 25924#L1545-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 25925#L731-42 assume 1 == ~t7_pc~0; 25786#L732-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 25611#L742-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 26266#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 25834#L1553-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 25835#L1553-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 25522#L750-42 assume 1 == ~t8_pc~0; 25523#L751-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 26100#L761-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 26405#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 25408#L1561-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 25409#L1561-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 26188#L769-42 assume !(1 == ~t9_pc~0); 26017#L769-44 is_transmit9_triggered_~__retres1~9#1 := 0; 26016#L780-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 26700#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 26898#L1569-42 assume !(0 != activate_threads_~tmp___8~0#1); 25623#L1569-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 25624#L788-42 assume 1 == ~t10_pc~0; 26196#L789-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 26421#L799-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 26395#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 26396#L1577-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 26907#L1577-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 26880#L807-42 assume 1 == ~t11_pc~0; 26552#L808-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 25244#L818-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 26104#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 25365#L1585-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 25366#L1585-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 25618#L826-42 assume 1 == ~t12_pc~0; 25619#L827-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 25824#L837-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 26209#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 25608#L1593-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 25609#L1593-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 26473#L1344-3 assume 1 == ~M_E~0;~M_E~0 := 2; 26474#L1344-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 26400#L1349-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 25777#L1354-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 25778#L1359-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 26414#L1364-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 26885#L1369-3 assume !(1 == ~T6_E~0); 26791#L1374-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 25532#L1379-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 25533#L1384-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 25775#L1389-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 25776#L1394-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 26065#L1399-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 26797#L1404-3 assume 1 == ~E_M~0;~E_M~0 := 2; 26766#L1409-3 assume !(1 == ~E_1~0); 26767#L1414-3 assume 1 == ~E_2~0;~E_2~0 := 2; 26828#L1419-3 assume 1 == ~E_3~0;~E_3~0 := 2; 26609#L1424-3 assume 1 == ~E_4~0;~E_4~0 := 2; 25424#L1429-3 assume 1 == ~E_5~0;~E_5~0 := 2; 25425#L1434-3 assume 1 == ~E_6~0;~E_6~0 := 2; 26413#L1439-3 assume 1 == ~E_7~0;~E_7~0 := 2; 25371#L1444-3 assume 1 == ~E_8~0;~E_8~0 := 2; 25372#L1449-3 assume !(1 == ~E_9~0); 25477#L1454-3 assume 1 == ~E_10~0;~E_10~0 := 2; 26407#L1459-3 assume 1 == ~E_11~0;~E_11~0 := 2; 26408#L1464-3 assume 1 == ~E_12~0;~E_12~0 := 2; 26790#L1469-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 26274#L926-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 25289#L993-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 25290#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 25453#L1834 assume !(0 == start_simulation_~tmp~3#1); 26520#L1834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 26537#L926-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 25978#L993-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 25177#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 25178#L1789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 26780#L1796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 26776#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 26610#L1847 assume !(0 != start_simulation_~tmp___0~1#1); 26410#L1815-2 [2022-12-13 13:22:09,816 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 13:22:09,816 INFO L85 PathProgramCache]: Analyzing trace with hash -973893586, now seen corresponding path program 1 times [2022-12-13 13:22:09,817 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 13:22:09,817 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2051705868] [2022-12-13 13:22:09,817 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 13:22:09,817 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 13:22:09,826 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 13:22:09,846 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 13:22:09,847 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 13:22:09,847 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2051705868] [2022-12-13 13:22:09,847 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2051705868] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 13:22:09,847 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 13:22:09,847 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 13:22:09,847 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1162497655] [2022-12-13 13:22:09,848 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 13:22:09,848 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 13:22:09,848 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 13:22:09,848 INFO L85 PathProgramCache]: Analyzing trace with hash 1744312659, now seen corresponding path program 1 times [2022-12-13 13:22:09,848 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 13:22:09,849 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [177997633] [2022-12-13 13:22:09,849 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 13:22:09,849 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 13:22:09,873 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 13:22:09,914 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 13:22:09,915 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 13:22:09,915 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [177997633] [2022-12-13 13:22:09,915 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [177997633] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 13:22:09,915 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 13:22:09,915 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 13:22:09,915 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [825199124] [2022-12-13 13:22:09,916 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 13:22:09,916 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 13:22:09,916 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 13:22:09,916 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 13:22:09,917 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 13:22:09,917 INFO L87 Difference]: Start difference. First operand 1790 states and 2649 transitions. cyclomatic complexity: 860 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 13:22:09,940 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 13:22:09,940 INFO L93 Difference]: Finished difference Result 1790 states and 2648 transitions. [2022-12-13 13:22:09,941 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1790 states and 2648 transitions. [2022-12-13 13:22:09,946 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1627 [2022-12-13 13:22:09,950 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1790 states to 1790 states and 2648 transitions. [2022-12-13 13:22:09,950 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1790 [2022-12-13 13:22:09,951 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1790 [2022-12-13 13:22:09,951 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1790 states and 2648 transitions. [2022-12-13 13:22:09,953 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 13:22:09,953 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1790 states and 2648 transitions. [2022-12-13 13:22:09,955 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1790 states and 2648 transitions. [2022-12-13 13:22:09,973 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1790 to 1790. [2022-12-13 13:22:09,977 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1790 states, 1790 states have (on average 1.4793296089385475) internal successors, (2648), 1789 states have internal predecessors, (2648), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 13:22:09,983 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1790 states to 1790 states and 2648 transitions. [2022-12-13 13:22:09,983 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1790 states and 2648 transitions. [2022-12-13 13:22:09,983 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 13:22:09,984 INFO L428 stractBuchiCegarLoop]: Abstraction has 1790 states and 2648 transitions. [2022-12-13 13:22:09,984 INFO L335 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2022-12-13 13:22:09,984 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1790 states and 2648 transitions. [2022-12-13 13:22:09,991 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1627 [2022-12-13 13:22:09,991 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 13:22:09,991 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 13:22:09,994 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 13:22:09,994 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 13:22:09,994 INFO L748 eck$LassoCheckResult]: Stem: 28956#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 28957#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 29872#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 29873#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 30328#L853 assume 1 == ~m_i~0;~m_st~0 := 0; 30198#L853-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 29237#L858-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 28712#L863-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 28713#L868-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 29968#L873-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 30106#L878-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 30489#L883-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 30490#L888-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 29454#L893-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 29455#L898-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 29996#L903-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 29918#L908-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 29919#L913-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 30069#L1206 assume !(0 == ~M_E~0); 29437#L1206-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 29438#L1211-1 assume !(0 == ~T2_E~0); 30321#L1216-1 assume !(0 == ~T3_E~0); 29214#L1221-1 assume !(0 == ~T4_E~0); 29215#L1226-1 assume !(0 == ~T5_E~0); 28888#L1231-1 assume !(0 == ~T6_E~0); 28889#L1236-1 assume !(0 == ~T7_E~0); 30362#L1241-1 assume !(0 == ~T8_E~0); 29284#L1246-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 29285#L1251-1 assume !(0 == ~T10_E~0); 29506#L1256-1 assume !(0 == ~T11_E~0); 28722#L1261-1 assume !(0 == ~T12_E~0); 28723#L1266-1 assume !(0 == ~E_M~0); 30475#L1271-1 assume !(0 == ~E_1~0); 30096#L1276-1 assume !(0 == ~E_2~0); 30097#L1281-1 assume !(0 == ~E_3~0); 30025#L1286-1 assume 0 == ~E_4~0;~E_4~0 := 1; 29117#L1291-1 assume !(0 == ~E_5~0); 29118#L1296-1 assume !(0 == ~E_6~0); 29828#L1301-1 assume !(0 == ~E_7~0); 29829#L1306-1 assume !(0 == ~E_8~0); 30261#L1311-1 assume !(0 == ~E_9~0); 29077#L1316-1 assume !(0 == ~E_10~0); 29078#L1321-1 assume !(0 == ~E_11~0); 29843#L1326-1 assume 0 == ~E_12~0;~E_12~0 := 1; 28944#L1331-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 28945#L598 assume 1 == ~m_pc~0; 28992#L599 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 28993#L609 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 29726#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 29727#L1497 assume !(0 != activate_threads_~tmp~1#1); 30438#L1497-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 30386#L617 assume !(1 == ~t1_pc~0); 29306#L617-2 is_transmit1_triggered_~__retres1~1#1 := 0; 29307#L628 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 30177#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 30178#L1505 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 29935#L1505-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 29936#L636 assume 1 == ~t2_pc~0; 29275#L637 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 29276#L647 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 29099#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 29100#L1513 assume !(0 != activate_threads_~tmp___1~0#1); 29967#L1513-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 29624#L655 assume !(1 == ~t3_pc~0); 29625#L655-2 is_transmit3_triggered_~__retres1~3#1 := 0; 30347#L666 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 30166#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 30167#L1521 assume !(0 != activate_threads_~tmp___2~0#1); 30476#L1521-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 30477#L674 assume 1 == ~t4_pc~0; 28809#L675 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 28810#L685 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 28834#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 28835#L1529 assume !(0 != activate_threads_~tmp___3~0#1); 29101#L1529-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 29623#L693 assume !(1 == ~t5_pc~0); 29778#L693-2 is_transmit5_triggered_~__retres1~5#1 := 0; 29439#L704 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 29440#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 30263#L1537 assume !(0 != activate_threads_~tmp___4~0#1); 29519#L1537-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 29458#L712 assume 1 == ~t6_pc~0; 29459#L713 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 29877#L723 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 29087#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 29088#L1545 assume !(0 != activate_threads_~tmp___5~0#1); 29984#L1545-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 29977#L731 assume 1 == ~t7_pc~0; 28946#L732 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 28947#L742 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 29143#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 30266#L1553 assume !(0 != activate_threads_~tmp___6~0#1); 30207#L1553-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 29050#L750 assume !(1 == ~t8_pc~0); 28743#L750-2 is_transmit8_triggered_~__retres1~8#1 := 0; 28742#L761 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 29248#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 30276#L1561 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 29390#L1561-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 29391#L769 assume 1 == ~t9_pc~0; 29933#L770 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 28908#L780 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 28909#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 29133#L1569 assume !(0 != activate_threads_~tmp___8~0#1); 30143#L1569-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 30226#L788 assume !(1 == ~t10_pc~0); 29794#L788-2 is_transmit10_triggered_~__retres1~10#1 := 0; 29795#L799 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 30348#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 30300#L1577 assume !(0 != activate_threads_~tmp___9~0#1); 29046#L1577-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 29047#L807 assume 1 == ~t11_pc~0; 30232#L808 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 29809#L818 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 29969#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 30406#L1585 assume !(0 != activate_threads_~tmp___10~0#1); 30501#L1585-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 30331#L826 assume !(1 == ~t12_pc~0); 29461#L826-2 is_transmit12_triggered_~__retres1~12#1 := 0; 29462#L837 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 28787#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 28788#L1593 assume !(0 != activate_threads_~tmp___11~0#1); 29617#L1593-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 29529#L1344 assume !(1 == ~M_E~0); 29530#L1344-2 assume !(1 == ~T1_E~0); 29660#L1349-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 29834#L1354-1 assume !(1 == ~T3_E~0); 29835#L1359-1 assume !(1 == ~T4_E~0); 30218#L1364-1 assume !(1 == ~T5_E~0); 29160#L1369-1 assume !(1 == ~T6_E~0); 29161#L1374-1 assume !(1 == ~T7_E~0); 29841#L1379-1 assume !(1 == ~T8_E~0); 29842#L1384-1 assume !(1 == ~T9_E~0); 29917#L1389-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 30364#L1394-1 assume !(1 == ~T11_E~0); 30365#L1399-1 assume !(1 == ~T12_E~0); 30446#L1404-1 assume !(1 == ~E_M~0); 29287#L1409-1 assume !(1 == ~E_1~0); 29288#L1414-1 assume !(1 == ~E_2~0); 30122#L1419-1 assume !(1 == ~E_3~0); 28921#L1424-1 assume !(1 == ~E_4~0); 28922#L1429-1 assume 1 == ~E_5~0;~E_5~0 := 2; 29850#L1434-1 assume !(1 == ~E_6~0); 30379#L1439-1 assume !(1 == ~E_7~0); 28965#L1444-1 assume !(1 == ~E_8~0); 28966#L1449-1 assume !(1 == ~E_9~0); 29395#L1454-1 assume !(1 == ~E_10~0); 29396#L1459-1 assume !(1 == ~E_11~0); 29947#L1464-1 assume !(1 == ~E_12~0); 29948#L1469-1 assume { :end_inline_reset_delta_events } true; 29997#L1815-2 [2022-12-13 13:22:09,994 INFO L750 eck$LassoCheckResult]: Loop: 29997#L1815-2 assume !false; 30144#L1816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 29811#L1181 assume !false; 29881#L1004 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 29832#L926 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 28715#L993 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 29432#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 29976#L1008 assume !(0 != eval_~tmp~0#1); 29672#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 29295#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 29296#L1206-3 assume 0 == ~M_E~0;~M_E~0 := 1; 30496#L1206-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 29946#L1211-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 29034#L1216-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 29035#L1221-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 29639#L1226-3 assume !(0 == ~T5_E~0); 29104#L1231-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 29105#L1236-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 29433#L1241-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 30416#L1246-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 30315#L1251-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 30056#L1256-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 29056#L1261-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 29057#L1266-3 assume !(0 == ~E_M~0); 29102#L1271-3 assume 0 == ~E_1~0;~E_1~0 := 1; 29103#L1276-3 assume 0 == ~E_2~0;~E_2~0 := 1; 29580#L1281-3 assume 0 == ~E_3~0;~E_3~0 := 1; 29581#L1286-3 assume 0 == ~E_4~0;~E_4~0 := 1; 30119#L1291-3 assume 0 == ~E_5~0;~E_5~0 := 1; 30120#L1296-3 assume 0 == ~E_6~0;~E_6~0 := 1; 30482#L1301-3 assume 0 == ~E_7~0;~E_7~0 := 1; 30443#L1306-3 assume !(0 == ~E_8~0); 29700#L1311-3 assume 0 == ~E_9~0;~E_9~0 := 1; 28980#L1316-3 assume 0 == ~E_10~0;~E_10~0 := 1; 28981#L1321-3 assume 0 == ~E_11~0;~E_11~0 := 1; 29058#L1326-3 assume 0 == ~E_12~0;~E_12~0 := 1; 29803#L1331-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 30130#L598-42 assume !(1 == ~m_pc~0); 30131#L598-44 is_master_triggered_~__retres1~0#1 := 0; 30247#L609-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 29463#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 29464#L1497-42 assume !(0 != activate_threads_~tmp~1#1); 30444#L1497-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 29857#L617-42 assume 1 == ~t1_pc~0; 29633#L618-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 29502#L628-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 29503#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 30441#L1505-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 29208#L1505-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 29209#L636-42 assume 1 == ~t2_pc~0; 30421#L637-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 29671#L647-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 29748#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 29749#L1513-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 30214#L1513-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 30079#L655-42 assume 1 == ~t3_pc~0; 30080#L656-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 29647#L666-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 30157#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 30158#L1521-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 30346#L1521-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 30282#L674-42 assume !(1 == ~t4_pc~0); 30064#L674-44 is_transmit4_triggered_~__retres1~4#1 := 0; 29985#L685-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 29986#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 30189#L1529-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 29776#L1529-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 29777#L693-42 assume 1 == ~t5_pc~0; 30044#L694-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 30045#L704-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 29830#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 29831#L1537-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 30100#L1537-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 29405#L712-42 assume !(1 == ~t6_pc~0); 29406#L712-44 is_transmit6_triggered_~__retres1~6#1 := 0; 29718#L723-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 29048#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 29049#L1545-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 29511#L1545-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 29512#L731-42 assume !(1 == ~t7_pc~0); 29200#L731-44 is_transmit7_triggered_~__retres1~7#1 := 0; 29201#L742-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 29853#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 29422#L1553-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 29423#L1553-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 29112#L750-42 assume 1 == ~t8_pc~0; 29113#L751-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 29687#L761-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 29992#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 28995#L1561-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 28996#L1561-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 29775#L769-42 assume 1 == ~t9_pc~0; 29604#L770-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 29605#L780-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 30287#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 30485#L1569-42 assume !(0 != activate_threads_~tmp___8~0#1); 29210#L1569-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 29211#L788-42 assume 1 == ~t10_pc~0; 29783#L789-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 30011#L799-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 29982#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 29983#L1577-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 30494#L1577-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 30469#L807-42 assume 1 == ~t11_pc~0; 30139#L808-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 28831#L818-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 29691#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 28952#L1585-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 28953#L1585-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 29205#L826-42 assume 1 == ~t12_pc~0; 29206#L827-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 29411#L837-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 29799#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 29195#L1593-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 29196#L1593-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 30060#L1344-3 assume 1 == ~M_E~0;~M_E~0 := 2; 30061#L1344-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 29987#L1349-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 29364#L1354-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 29365#L1359-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 30001#L1364-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 30472#L1369-3 assume !(1 == ~T6_E~0); 30378#L1374-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 29121#L1379-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 29122#L1384-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 29362#L1389-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 29363#L1394-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 29652#L1399-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 30384#L1404-3 assume 1 == ~E_M~0;~E_M~0 := 2; 30353#L1409-3 assume !(1 == ~E_1~0); 30354#L1414-3 assume 1 == ~E_2~0;~E_2~0 := 2; 30415#L1419-3 assume 1 == ~E_3~0;~E_3~0 := 2; 30196#L1424-3 assume 1 == ~E_4~0;~E_4~0 := 2; 29011#L1429-3 assume 1 == ~E_5~0;~E_5~0 := 2; 29012#L1434-3 assume 1 == ~E_6~0;~E_6~0 := 2; 30000#L1439-3 assume 1 == ~E_7~0;~E_7~0 := 2; 28958#L1444-3 assume 1 == ~E_8~0;~E_8~0 := 2; 28959#L1449-3 assume !(1 == ~E_9~0); 29064#L1454-3 assume 1 == ~E_10~0;~E_10~0 := 2; 29994#L1459-3 assume 1 == ~E_11~0;~E_11~0 := 2; 29995#L1464-3 assume 1 == ~E_12~0;~E_12~0 := 2; 30377#L1469-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 29861#L926-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 28876#L993-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 28877#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 29040#L1834 assume !(0 == start_simulation_~tmp~3#1); 30107#L1834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 30124#L926-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 29565#L993-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 28764#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 28765#L1789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 30367#L1796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 30363#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 30197#L1847 assume !(0 != start_simulation_~tmp___0~1#1); 29997#L1815-2 [2022-12-13 13:22:09,995 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 13:22:09,995 INFO L85 PathProgramCache]: Analyzing trace with hash 813976236, now seen corresponding path program 1 times [2022-12-13 13:22:09,995 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 13:22:09,995 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1650668623] [2022-12-13 13:22:09,995 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 13:22:09,995 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 13:22:10,006 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 13:22:10,033 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 13:22:10,034 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 13:22:10,034 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1650668623] [2022-12-13 13:22:10,034 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1650668623] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 13:22:10,034 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 13:22:10,034 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 13:22:10,034 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [969064831] [2022-12-13 13:22:10,035 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 13:22:10,035 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 13:22:10,035 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 13:22:10,035 INFO L85 PathProgramCache]: Analyzing trace with hash 1700589075, now seen corresponding path program 1 times [2022-12-13 13:22:10,035 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 13:22:10,036 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [427753591] [2022-12-13 13:22:10,036 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 13:22:10,036 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 13:22:10,048 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 13:22:10,090 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 13:22:10,090 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 13:22:10,091 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [427753591] [2022-12-13 13:22:10,091 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [427753591] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 13:22:10,091 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 13:22:10,091 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 13:22:10,091 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1906252270] [2022-12-13 13:22:10,091 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 13:22:10,092 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 13:22:10,092 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 13:22:10,092 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 13:22:10,092 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 13:22:10,092 INFO L87 Difference]: Start difference. First operand 1790 states and 2648 transitions. cyclomatic complexity: 859 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 13:22:10,122 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 13:22:10,122 INFO L93 Difference]: Finished difference Result 1790 states and 2647 transitions. [2022-12-13 13:22:10,122 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1790 states and 2647 transitions. [2022-12-13 13:22:10,130 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1627 [2022-12-13 13:22:10,138 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1790 states to 1790 states and 2647 transitions. [2022-12-13 13:22:10,138 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1790 [2022-12-13 13:22:10,139 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1790 [2022-12-13 13:22:10,140 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1790 states and 2647 transitions. [2022-12-13 13:22:10,142 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 13:22:10,142 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1790 states and 2647 transitions. [2022-12-13 13:22:10,146 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1790 states and 2647 transitions. [2022-12-13 13:22:10,160 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1790 to 1790. [2022-12-13 13:22:10,162 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1790 states, 1790 states have (on average 1.4787709497206705) internal successors, (2647), 1789 states have internal predecessors, (2647), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 13:22:10,164 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1790 states to 1790 states and 2647 transitions. [2022-12-13 13:22:10,164 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1790 states and 2647 transitions. [2022-12-13 13:22:10,165 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 13:22:10,165 INFO L428 stractBuchiCegarLoop]: Abstraction has 1790 states and 2647 transitions. [2022-12-13 13:22:10,165 INFO L335 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2022-12-13 13:22:10,165 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1790 states and 2647 transitions. [2022-12-13 13:22:10,169 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1627 [2022-12-13 13:22:10,169 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 13:22:10,169 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 13:22:10,171 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 13:22:10,171 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 13:22:10,171 INFO L748 eck$LassoCheckResult]: Stem: 32543#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 32544#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 33459#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 33460#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 33915#L853 assume 1 == ~m_i~0;~m_st~0 := 0; 33785#L853-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 32824#L858-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 32299#L863-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 32300#L868-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 33555#L873-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 33693#L878-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 34076#L883-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 34077#L888-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 33041#L893-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 33042#L898-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 33583#L903-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 33505#L908-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 33506#L913-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 33656#L1206 assume !(0 == ~M_E~0); 33024#L1206-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 33025#L1211-1 assume !(0 == ~T2_E~0); 33908#L1216-1 assume !(0 == ~T3_E~0); 32801#L1221-1 assume !(0 == ~T4_E~0); 32802#L1226-1 assume !(0 == ~T5_E~0); 32475#L1231-1 assume !(0 == ~T6_E~0); 32476#L1236-1 assume !(0 == ~T7_E~0); 33949#L1241-1 assume !(0 == ~T8_E~0); 32871#L1246-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 32872#L1251-1 assume !(0 == ~T10_E~0); 33093#L1256-1 assume !(0 == ~T11_E~0); 32309#L1261-1 assume !(0 == ~T12_E~0); 32310#L1266-1 assume !(0 == ~E_M~0); 34062#L1271-1 assume !(0 == ~E_1~0); 33683#L1276-1 assume !(0 == ~E_2~0); 33684#L1281-1 assume !(0 == ~E_3~0); 33612#L1286-1 assume 0 == ~E_4~0;~E_4~0 := 1; 32704#L1291-1 assume !(0 == ~E_5~0); 32705#L1296-1 assume !(0 == ~E_6~0); 33415#L1301-1 assume !(0 == ~E_7~0); 33416#L1306-1 assume !(0 == ~E_8~0); 33848#L1311-1 assume !(0 == ~E_9~0); 32664#L1316-1 assume !(0 == ~E_10~0); 32665#L1321-1 assume !(0 == ~E_11~0); 33430#L1326-1 assume 0 == ~E_12~0;~E_12~0 := 1; 32531#L1331-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 32532#L598 assume 1 == ~m_pc~0; 32579#L599 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 32580#L609 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 33313#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 33314#L1497 assume !(0 != activate_threads_~tmp~1#1); 34025#L1497-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 33973#L617 assume !(1 == ~t1_pc~0); 32893#L617-2 is_transmit1_triggered_~__retres1~1#1 := 0; 32894#L628 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 33764#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 33765#L1505 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 33522#L1505-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 33523#L636 assume 1 == ~t2_pc~0; 32862#L637 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 32863#L647 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 32686#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 32687#L1513 assume !(0 != activate_threads_~tmp___1~0#1); 33554#L1513-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 33211#L655 assume !(1 == ~t3_pc~0); 33212#L655-2 is_transmit3_triggered_~__retres1~3#1 := 0; 33934#L666 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 33753#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 33754#L1521 assume !(0 != activate_threads_~tmp___2~0#1); 34063#L1521-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 34064#L674 assume 1 == ~t4_pc~0; 32396#L675 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 32397#L685 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 32421#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 32422#L1529 assume !(0 != activate_threads_~tmp___3~0#1); 32688#L1529-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 33210#L693 assume !(1 == ~t5_pc~0); 33365#L693-2 is_transmit5_triggered_~__retres1~5#1 := 0; 33026#L704 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 33027#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 33850#L1537 assume !(0 != activate_threads_~tmp___4~0#1); 33106#L1537-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 33045#L712 assume 1 == ~t6_pc~0; 33046#L713 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 33464#L723 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 32674#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 32675#L1545 assume !(0 != activate_threads_~tmp___5~0#1); 33571#L1545-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 33564#L731 assume 1 == ~t7_pc~0; 32533#L732 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 32534#L742 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 32730#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 33853#L1553 assume !(0 != activate_threads_~tmp___6~0#1); 33794#L1553-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 32637#L750 assume !(1 == ~t8_pc~0); 32330#L750-2 is_transmit8_triggered_~__retres1~8#1 := 0; 32329#L761 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 32835#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 33863#L1561 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 32977#L1561-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 32978#L769 assume 1 == ~t9_pc~0; 33518#L770 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 32495#L780 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 32496#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 32720#L1569 assume !(0 != activate_threads_~tmp___8~0#1); 33730#L1569-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 33813#L788 assume !(1 == ~t10_pc~0); 33381#L788-2 is_transmit10_triggered_~__retres1~10#1 := 0; 33382#L799 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 33935#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 33887#L1577 assume !(0 != activate_threads_~tmp___9~0#1); 32633#L1577-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 32634#L807 assume 1 == ~t11_pc~0; 33819#L808 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 33396#L818 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 33556#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 33993#L1585 assume !(0 != activate_threads_~tmp___10~0#1); 34088#L1585-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 33918#L826 assume !(1 == ~t12_pc~0); 33048#L826-2 is_transmit12_triggered_~__retres1~12#1 := 0; 33049#L837 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 32374#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 32375#L1593 assume !(0 != activate_threads_~tmp___11~0#1); 33204#L1593-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 33116#L1344 assume !(1 == ~M_E~0); 33117#L1344-2 assume !(1 == ~T1_E~0); 33247#L1349-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 33421#L1354-1 assume !(1 == ~T3_E~0); 33422#L1359-1 assume !(1 == ~T4_E~0); 33805#L1364-1 assume !(1 == ~T5_E~0); 32747#L1369-1 assume !(1 == ~T6_E~0); 32748#L1374-1 assume !(1 == ~T7_E~0); 33428#L1379-1 assume !(1 == ~T8_E~0); 33429#L1384-1 assume !(1 == ~T9_E~0); 33504#L1389-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 33951#L1394-1 assume !(1 == ~T11_E~0); 33952#L1399-1 assume !(1 == ~T12_E~0); 34033#L1404-1 assume !(1 == ~E_M~0); 32874#L1409-1 assume !(1 == ~E_1~0); 32875#L1414-1 assume !(1 == ~E_2~0); 33709#L1419-1 assume !(1 == ~E_3~0); 32508#L1424-1 assume !(1 == ~E_4~0); 32509#L1429-1 assume 1 == ~E_5~0;~E_5~0 := 2; 33437#L1434-1 assume !(1 == ~E_6~0); 33966#L1439-1 assume !(1 == ~E_7~0); 32552#L1444-1 assume !(1 == ~E_8~0); 32553#L1449-1 assume !(1 == ~E_9~0); 32982#L1454-1 assume !(1 == ~E_10~0); 32983#L1459-1 assume !(1 == ~E_11~0); 33534#L1464-1 assume !(1 == ~E_12~0); 33535#L1469-1 assume { :end_inline_reset_delta_events } true; 33584#L1815-2 [2022-12-13 13:22:10,171 INFO L750 eck$LassoCheckResult]: Loop: 33584#L1815-2 assume !false; 33731#L1816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 33398#L1181 assume !false; 33468#L1004 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 33419#L926 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 32302#L993 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 33019#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 33563#L1008 assume !(0 != eval_~tmp~0#1); 33259#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 32882#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 32883#L1206-3 assume 0 == ~M_E~0;~M_E~0 := 1; 34083#L1206-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 33533#L1211-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 32621#L1216-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 32622#L1221-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 33226#L1226-3 assume !(0 == ~T5_E~0); 32691#L1231-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 32692#L1236-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 33020#L1241-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 34003#L1246-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 33902#L1251-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 33643#L1256-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 32643#L1261-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 32644#L1266-3 assume !(0 == ~E_M~0); 32689#L1271-3 assume 0 == ~E_1~0;~E_1~0 := 1; 32690#L1276-3 assume 0 == ~E_2~0;~E_2~0 := 1; 33167#L1281-3 assume 0 == ~E_3~0;~E_3~0 := 1; 33168#L1286-3 assume 0 == ~E_4~0;~E_4~0 := 1; 33706#L1291-3 assume 0 == ~E_5~0;~E_5~0 := 1; 33707#L1296-3 assume 0 == ~E_6~0;~E_6~0 := 1; 34069#L1301-3 assume 0 == ~E_7~0;~E_7~0 := 1; 34030#L1306-3 assume !(0 == ~E_8~0); 33287#L1311-3 assume 0 == ~E_9~0;~E_9~0 := 1; 32567#L1316-3 assume 0 == ~E_10~0;~E_10~0 := 1; 32568#L1321-3 assume 0 == ~E_11~0;~E_11~0 := 1; 32645#L1326-3 assume 0 == ~E_12~0;~E_12~0 := 1; 33390#L1331-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 33717#L598-42 assume !(1 == ~m_pc~0); 33718#L598-44 is_master_triggered_~__retres1~0#1 := 0; 33834#L609-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 33050#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 33051#L1497-42 assume !(0 != activate_threads_~tmp~1#1); 34031#L1497-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 33444#L617-42 assume 1 == ~t1_pc~0; 33220#L618-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 33089#L628-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 33090#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 34028#L1505-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 32795#L1505-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 32796#L636-42 assume 1 == ~t2_pc~0; 34008#L637-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 33258#L647-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 33335#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 33336#L1513-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 33801#L1513-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 33666#L655-42 assume !(1 == ~t3_pc~0); 33233#L655-44 is_transmit3_triggered_~__retres1~3#1 := 0; 33234#L666-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 33744#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 33745#L1521-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 33933#L1521-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 33869#L674-42 assume !(1 == ~t4_pc~0); 33651#L674-44 is_transmit4_triggered_~__retres1~4#1 := 0; 33572#L685-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 33573#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 33776#L1529-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 33363#L1529-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 33364#L693-42 assume !(1 == ~t5_pc~0); 33633#L693-44 is_transmit5_triggered_~__retres1~5#1 := 0; 33632#L704-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 33417#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 33418#L1537-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 33687#L1537-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 32992#L712-42 assume !(1 == ~t6_pc~0); 32993#L712-44 is_transmit6_triggered_~__retres1~6#1 := 0; 33305#L723-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 32635#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 32636#L1545-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 33098#L1545-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 33099#L731-42 assume 1 == ~t7_pc~0; 32962#L732-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 32788#L742-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 33440#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 33009#L1553-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 33010#L1553-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 32699#L750-42 assume 1 == ~t8_pc~0; 32700#L751-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 33274#L761-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 33579#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 32582#L1561-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 32583#L1561-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 33362#L769-42 assume 1 == ~t9_pc~0; 33191#L770-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 33192#L780-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 33874#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 34072#L1569-42 assume !(0 != activate_threads_~tmp___8~0#1); 32797#L1569-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 32798#L788-42 assume 1 == ~t10_pc~0; 33370#L789-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 33598#L799-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 33569#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 33570#L1577-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 34081#L1577-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 34056#L807-42 assume !(1 == ~t11_pc~0); 32417#L807-44 is_transmit11_triggered_~__retres1~11#1 := 0; 32418#L818-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 33278#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 32539#L1585-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 32540#L1585-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 32792#L826-42 assume 1 == ~t12_pc~0; 32793#L827-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 32998#L837-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 33386#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 32782#L1593-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 32783#L1593-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 33647#L1344-3 assume 1 == ~M_E~0;~M_E~0 := 2; 33648#L1344-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 33574#L1349-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 32951#L1354-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 32952#L1359-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 33588#L1364-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 34059#L1369-3 assume !(1 == ~T6_E~0); 33965#L1374-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 32708#L1379-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 32709#L1384-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 32949#L1389-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 32950#L1394-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 33239#L1399-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 33971#L1404-3 assume 1 == ~E_M~0;~E_M~0 := 2; 33940#L1409-3 assume !(1 == ~E_1~0); 33941#L1414-3 assume 1 == ~E_2~0;~E_2~0 := 2; 34002#L1419-3 assume 1 == ~E_3~0;~E_3~0 := 2; 33783#L1424-3 assume 1 == ~E_4~0;~E_4~0 := 2; 32598#L1429-3 assume 1 == ~E_5~0;~E_5~0 := 2; 32599#L1434-3 assume 1 == ~E_6~0;~E_6~0 := 2; 33587#L1439-3 assume 1 == ~E_7~0;~E_7~0 := 2; 32545#L1444-3 assume 1 == ~E_8~0;~E_8~0 := 2; 32546#L1449-3 assume !(1 == ~E_9~0); 32651#L1454-3 assume 1 == ~E_10~0;~E_10~0 := 2; 33581#L1459-3 assume 1 == ~E_11~0;~E_11~0 := 2; 33582#L1464-3 assume 1 == ~E_12~0;~E_12~0 := 2; 33964#L1469-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 33448#L926-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 32463#L993-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 32464#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 32627#L1834 assume !(0 == start_simulation_~tmp~3#1); 33694#L1834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 33711#L926-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 33152#L993-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 32351#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 32352#L1789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 33954#L1796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 33950#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 33784#L1847 assume !(0 != start_simulation_~tmp___0~1#1); 33584#L1815-2 [2022-12-13 13:22:10,171 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 13:22:10,172 INFO L85 PathProgramCache]: Analyzing trace with hash -1345107858, now seen corresponding path program 1 times [2022-12-13 13:22:10,172 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 13:22:10,172 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2084182015] [2022-12-13 13:22:10,172 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 13:22:10,172 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 13:22:10,179 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 13:22:10,197 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 13:22:10,198 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 13:22:10,198 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2084182015] [2022-12-13 13:22:10,198 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2084182015] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 13:22:10,198 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 13:22:10,198 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 13:22:10,198 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [517602169] [2022-12-13 13:22:10,198 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 13:22:10,198 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 13:22:10,198 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 13:22:10,199 INFO L85 PathProgramCache]: Analyzing trace with hash 157808789, now seen corresponding path program 1 times [2022-12-13 13:22:10,199 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 13:22:10,199 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2128343180] [2022-12-13 13:22:10,199 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 13:22:10,199 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 13:22:10,207 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 13:22:10,231 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 13:22:10,231 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 13:22:10,231 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2128343180] [2022-12-13 13:22:10,231 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2128343180] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 13:22:10,231 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 13:22:10,231 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 13:22:10,231 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1557481445] [2022-12-13 13:22:10,231 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 13:22:10,231 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 13:22:10,232 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 13:22:10,232 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 13:22:10,232 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 13:22:10,232 INFO L87 Difference]: Start difference. First operand 1790 states and 2647 transitions. cyclomatic complexity: 858 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 13:22:10,261 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 13:22:10,261 INFO L93 Difference]: Finished difference Result 1790 states and 2646 transitions. [2022-12-13 13:22:10,261 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1790 states and 2646 transitions. [2022-12-13 13:22:10,266 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1627 [2022-12-13 13:22:10,270 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1790 states to 1790 states and 2646 transitions. [2022-12-13 13:22:10,270 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1790 [2022-12-13 13:22:10,271 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1790 [2022-12-13 13:22:10,271 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1790 states and 2646 transitions. [2022-12-13 13:22:10,273 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 13:22:10,273 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1790 states and 2646 transitions. [2022-12-13 13:22:10,275 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1790 states and 2646 transitions. [2022-12-13 13:22:10,287 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1790 to 1790. [2022-12-13 13:22:10,290 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1790 states, 1790 states have (on average 1.4782122905027932) internal successors, (2646), 1789 states have internal predecessors, (2646), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 13:22:10,292 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1790 states to 1790 states and 2646 transitions. [2022-12-13 13:22:10,292 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1790 states and 2646 transitions. [2022-12-13 13:22:10,293 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 13:22:10,293 INFO L428 stractBuchiCegarLoop]: Abstraction has 1790 states and 2646 transitions. [2022-12-13 13:22:10,293 INFO L335 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2022-12-13 13:22:10,293 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1790 states and 2646 transitions. [2022-12-13 13:22:10,297 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1627 [2022-12-13 13:22:10,298 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 13:22:10,298 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 13:22:10,299 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 13:22:10,299 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 13:22:10,299 INFO L748 eck$LassoCheckResult]: Stem: 36130#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 36131#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 37046#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 37047#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 37502#L853 assume 1 == ~m_i~0;~m_st~0 := 0; 37372#L853-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 36411#L858-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 35886#L863-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 35887#L868-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 37142#L873-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 37280#L878-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 37663#L883-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 37664#L888-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 36628#L893-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 36629#L898-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 37170#L903-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 37092#L908-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 37093#L913-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 37243#L1206 assume !(0 == ~M_E~0); 36611#L1206-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 36612#L1211-1 assume !(0 == ~T2_E~0); 37495#L1216-1 assume !(0 == ~T3_E~0); 36388#L1221-1 assume !(0 == ~T4_E~0); 36389#L1226-1 assume !(0 == ~T5_E~0); 36062#L1231-1 assume !(0 == ~T6_E~0); 36063#L1236-1 assume !(0 == ~T7_E~0); 37536#L1241-1 assume !(0 == ~T8_E~0); 36458#L1246-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 36459#L1251-1 assume !(0 == ~T10_E~0); 36680#L1256-1 assume !(0 == ~T11_E~0); 35896#L1261-1 assume !(0 == ~T12_E~0); 35897#L1266-1 assume !(0 == ~E_M~0); 37649#L1271-1 assume !(0 == ~E_1~0); 37270#L1276-1 assume !(0 == ~E_2~0); 37271#L1281-1 assume !(0 == ~E_3~0); 37199#L1286-1 assume 0 == ~E_4~0;~E_4~0 := 1; 36291#L1291-1 assume !(0 == ~E_5~0); 36292#L1296-1 assume !(0 == ~E_6~0); 37002#L1301-1 assume !(0 == ~E_7~0); 37003#L1306-1 assume !(0 == ~E_8~0); 37435#L1311-1 assume !(0 == ~E_9~0); 36251#L1316-1 assume !(0 == ~E_10~0); 36252#L1321-1 assume !(0 == ~E_11~0); 37017#L1326-1 assume 0 == ~E_12~0;~E_12~0 := 1; 36118#L1331-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 36119#L598 assume 1 == ~m_pc~0; 36166#L599 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 36167#L609 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 36900#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 36901#L1497 assume !(0 != activate_threads_~tmp~1#1); 37612#L1497-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 37560#L617 assume !(1 == ~t1_pc~0); 36480#L617-2 is_transmit1_triggered_~__retres1~1#1 := 0; 36481#L628 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 37351#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 37352#L1505 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 37109#L1505-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 37110#L636 assume 1 == ~t2_pc~0; 36449#L637 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 36450#L647 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 36273#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 36274#L1513 assume !(0 != activate_threads_~tmp___1~0#1); 37141#L1513-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 36798#L655 assume !(1 == ~t3_pc~0); 36799#L655-2 is_transmit3_triggered_~__retres1~3#1 := 0; 37521#L666 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 37340#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 37341#L1521 assume !(0 != activate_threads_~tmp___2~0#1); 37650#L1521-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 37651#L674 assume 1 == ~t4_pc~0; 35983#L675 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 35984#L685 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 36008#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 36009#L1529 assume !(0 != activate_threads_~tmp___3~0#1); 36275#L1529-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 36797#L693 assume !(1 == ~t5_pc~0); 36952#L693-2 is_transmit5_triggered_~__retres1~5#1 := 0; 36613#L704 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 36614#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 37437#L1537 assume !(0 != activate_threads_~tmp___4~0#1); 36693#L1537-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 36632#L712 assume 1 == ~t6_pc~0; 36633#L713 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 37051#L723 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 36261#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 36262#L1545 assume !(0 != activate_threads_~tmp___5~0#1); 37158#L1545-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 37151#L731 assume 1 == ~t7_pc~0; 36120#L732 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 36121#L742 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 36317#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 37440#L1553 assume !(0 != activate_threads_~tmp___6~0#1); 37381#L1553-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 36224#L750 assume !(1 == ~t8_pc~0); 35917#L750-2 is_transmit8_triggered_~__retres1~8#1 := 0; 35916#L761 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 36422#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 37450#L1561 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 36564#L1561-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 36565#L769 assume 1 == ~t9_pc~0; 37105#L770 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 36082#L780 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 36083#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 36307#L1569 assume !(0 != activate_threads_~tmp___8~0#1); 37317#L1569-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 37400#L788 assume !(1 == ~t10_pc~0); 36968#L788-2 is_transmit10_triggered_~__retres1~10#1 := 0; 36969#L799 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 37522#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 37474#L1577 assume !(0 != activate_threads_~tmp___9~0#1); 36220#L1577-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 36221#L807 assume 1 == ~t11_pc~0; 37406#L808 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 36983#L818 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 37143#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 37580#L1585 assume !(0 != activate_threads_~tmp___10~0#1); 37675#L1585-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 37505#L826 assume !(1 == ~t12_pc~0); 36635#L826-2 is_transmit12_triggered_~__retres1~12#1 := 0; 36636#L837 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 35961#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 35962#L1593 assume !(0 != activate_threads_~tmp___11~0#1); 36791#L1593-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 36703#L1344 assume !(1 == ~M_E~0); 36704#L1344-2 assume !(1 == ~T1_E~0); 36834#L1349-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 37008#L1354-1 assume !(1 == ~T3_E~0); 37009#L1359-1 assume !(1 == ~T4_E~0); 37392#L1364-1 assume !(1 == ~T5_E~0); 36334#L1369-1 assume !(1 == ~T6_E~0); 36335#L1374-1 assume !(1 == ~T7_E~0); 37015#L1379-1 assume !(1 == ~T8_E~0); 37016#L1384-1 assume !(1 == ~T9_E~0); 37091#L1389-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 37538#L1394-1 assume !(1 == ~T11_E~0); 37539#L1399-1 assume !(1 == ~T12_E~0); 37620#L1404-1 assume !(1 == ~E_M~0); 36461#L1409-1 assume !(1 == ~E_1~0); 36462#L1414-1 assume !(1 == ~E_2~0); 37296#L1419-1 assume !(1 == ~E_3~0); 36095#L1424-1 assume !(1 == ~E_4~0); 36096#L1429-1 assume 1 == ~E_5~0;~E_5~0 := 2; 37024#L1434-1 assume !(1 == ~E_6~0); 37553#L1439-1 assume !(1 == ~E_7~0); 36139#L1444-1 assume !(1 == ~E_8~0); 36140#L1449-1 assume !(1 == ~E_9~0); 36569#L1454-1 assume !(1 == ~E_10~0); 36570#L1459-1 assume !(1 == ~E_11~0); 37121#L1464-1 assume !(1 == ~E_12~0); 37122#L1469-1 assume { :end_inline_reset_delta_events } true; 37171#L1815-2 [2022-12-13 13:22:10,299 INFO L750 eck$LassoCheckResult]: Loop: 37171#L1815-2 assume !false; 37318#L1816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 36985#L1181 assume !false; 37055#L1004 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 37006#L926 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 35889#L993 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 36606#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 37150#L1008 assume !(0 != eval_~tmp~0#1); 36846#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 36469#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 36470#L1206-3 assume 0 == ~M_E~0;~M_E~0 := 1; 37670#L1206-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 37120#L1211-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 36208#L1216-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 36209#L1221-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 36813#L1226-3 assume !(0 == ~T5_E~0); 36278#L1231-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 36279#L1236-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 36607#L1241-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 37590#L1246-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 37489#L1251-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 37230#L1256-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 36230#L1261-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 36231#L1266-3 assume !(0 == ~E_M~0); 36276#L1271-3 assume 0 == ~E_1~0;~E_1~0 := 1; 36277#L1276-3 assume 0 == ~E_2~0;~E_2~0 := 1; 36754#L1281-3 assume 0 == ~E_3~0;~E_3~0 := 1; 36755#L1286-3 assume 0 == ~E_4~0;~E_4~0 := 1; 37293#L1291-3 assume 0 == ~E_5~0;~E_5~0 := 1; 37294#L1296-3 assume 0 == ~E_6~0;~E_6~0 := 1; 37656#L1301-3 assume 0 == ~E_7~0;~E_7~0 := 1; 37617#L1306-3 assume !(0 == ~E_8~0); 36874#L1311-3 assume 0 == ~E_9~0;~E_9~0 := 1; 36154#L1316-3 assume 0 == ~E_10~0;~E_10~0 := 1; 36155#L1321-3 assume 0 == ~E_11~0;~E_11~0 := 1; 36232#L1326-3 assume 0 == ~E_12~0;~E_12~0 := 1; 36977#L1331-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 37304#L598-42 assume !(1 == ~m_pc~0); 37305#L598-44 is_master_triggered_~__retres1~0#1 := 0; 37421#L609-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 36637#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 36638#L1497-42 assume !(0 != activate_threads_~tmp~1#1); 37618#L1497-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 37031#L617-42 assume 1 == ~t1_pc~0; 36807#L618-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 36676#L628-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 36677#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 37615#L1505-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 36382#L1505-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 36383#L636-42 assume 1 == ~t2_pc~0; 37595#L637-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 36845#L647-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 36922#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 36923#L1513-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 37388#L1513-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 37253#L655-42 assume !(1 == ~t3_pc~0); 36820#L655-44 is_transmit3_triggered_~__retres1~3#1 := 0; 36821#L666-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 37331#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 37332#L1521-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 37520#L1521-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 37456#L674-42 assume 1 == ~t4_pc~0; 37457#L675-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 37159#L685-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 37160#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 37363#L1529-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 36950#L1529-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 36951#L693-42 assume 1 == ~t5_pc~0; 37218#L694-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 37219#L704-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 37004#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 37005#L1537-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 37274#L1537-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 36579#L712-42 assume !(1 == ~t6_pc~0); 36580#L712-44 is_transmit6_triggered_~__retres1~6#1 := 0; 36892#L723-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 36222#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 36223#L1545-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 36685#L1545-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 36686#L731-42 assume 1 == ~t7_pc~0; 36549#L732-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 36375#L742-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 37027#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 36596#L1553-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 36597#L1553-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 36286#L750-42 assume !(1 == ~t8_pc~0); 36288#L750-44 is_transmit8_triggered_~__retres1~8#1 := 0; 36861#L761-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 37166#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 36169#L1561-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 36170#L1561-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 36949#L769-42 assume 1 == ~t9_pc~0; 36778#L770-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 36779#L780-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 37461#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 37659#L1569-42 assume !(0 != activate_threads_~tmp___8~0#1); 36384#L1569-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 36385#L788-42 assume 1 == ~t10_pc~0; 36957#L789-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 37185#L799-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 37156#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 37157#L1577-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 37668#L1577-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 37643#L807-42 assume 1 == ~t11_pc~0; 37313#L808-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 36005#L818-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 36865#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 36126#L1585-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 36127#L1585-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 36379#L826-42 assume 1 == ~t12_pc~0; 36380#L827-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 36585#L837-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 36973#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 36369#L1593-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 36370#L1593-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 37234#L1344-3 assume 1 == ~M_E~0;~M_E~0 := 2; 37235#L1344-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 37161#L1349-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 36538#L1354-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 36539#L1359-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 37175#L1364-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 37646#L1369-3 assume !(1 == ~T6_E~0); 37552#L1374-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 36295#L1379-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 36296#L1384-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 36536#L1389-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 36537#L1394-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 36826#L1399-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 37558#L1404-3 assume 1 == ~E_M~0;~E_M~0 := 2; 37527#L1409-3 assume !(1 == ~E_1~0); 37528#L1414-3 assume 1 == ~E_2~0;~E_2~0 := 2; 37589#L1419-3 assume 1 == ~E_3~0;~E_3~0 := 2; 37370#L1424-3 assume 1 == ~E_4~0;~E_4~0 := 2; 36185#L1429-3 assume 1 == ~E_5~0;~E_5~0 := 2; 36186#L1434-3 assume 1 == ~E_6~0;~E_6~0 := 2; 37174#L1439-3 assume 1 == ~E_7~0;~E_7~0 := 2; 36132#L1444-3 assume 1 == ~E_8~0;~E_8~0 := 2; 36133#L1449-3 assume !(1 == ~E_9~0); 36238#L1454-3 assume 1 == ~E_10~0;~E_10~0 := 2; 37168#L1459-3 assume 1 == ~E_11~0;~E_11~0 := 2; 37169#L1464-3 assume 1 == ~E_12~0;~E_12~0 := 2; 37551#L1469-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 37035#L926-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 36050#L993-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 36051#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 36214#L1834 assume !(0 == start_simulation_~tmp~3#1); 37281#L1834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 37298#L926-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 36739#L993-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 35938#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 35939#L1789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 37541#L1796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 37537#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 37371#L1847 assume !(0 != start_simulation_~tmp___0~1#1); 37171#L1815-2 [2022-12-13 13:22:10,300 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 13:22:10,300 INFO L85 PathProgramCache]: Analyzing trace with hash -1762996560, now seen corresponding path program 1 times [2022-12-13 13:22:10,300 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 13:22:10,300 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [67308270] [2022-12-13 13:22:10,300 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 13:22:10,300 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 13:22:10,307 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 13:22:10,325 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 13:22:10,325 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 13:22:10,325 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [67308270] [2022-12-13 13:22:10,325 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [67308270] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 13:22:10,325 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 13:22:10,325 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 13:22:10,325 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1822334304] [2022-12-13 13:22:10,325 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 13:22:10,326 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 13:22:10,326 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 13:22:10,326 INFO L85 PathProgramCache]: Analyzing trace with hash -530633197, now seen corresponding path program 1 times [2022-12-13 13:22:10,326 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 13:22:10,326 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [706756548] [2022-12-13 13:22:10,326 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 13:22:10,326 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 13:22:10,334 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 13:22:10,358 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 13:22:10,358 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 13:22:10,358 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [706756548] [2022-12-13 13:22:10,359 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [706756548] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 13:22:10,359 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 13:22:10,359 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 13:22:10,359 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [479722364] [2022-12-13 13:22:10,359 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 13:22:10,359 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 13:22:10,359 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 13:22:10,359 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 13:22:10,359 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 13:22:10,360 INFO L87 Difference]: Start difference. First operand 1790 states and 2646 transitions. cyclomatic complexity: 857 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 13:22:10,379 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 13:22:10,379 INFO L93 Difference]: Finished difference Result 1790 states and 2645 transitions. [2022-12-13 13:22:10,379 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1790 states and 2645 transitions. [2022-12-13 13:22:10,384 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1627 [2022-12-13 13:22:10,389 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1790 states to 1790 states and 2645 transitions. [2022-12-13 13:22:10,389 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1790 [2022-12-13 13:22:10,390 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1790 [2022-12-13 13:22:10,390 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1790 states and 2645 transitions. [2022-12-13 13:22:10,392 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 13:22:10,392 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1790 states and 2645 transitions. [2022-12-13 13:22:10,393 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1790 states and 2645 transitions. [2022-12-13 13:22:10,406 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1790 to 1790. [2022-12-13 13:22:10,408 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1790 states, 1790 states have (on average 1.4776536312849162) internal successors, (2645), 1789 states have internal predecessors, (2645), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 13:22:10,411 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1790 states to 1790 states and 2645 transitions. [2022-12-13 13:22:10,411 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1790 states and 2645 transitions. [2022-12-13 13:22:10,411 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 13:22:10,412 INFO L428 stractBuchiCegarLoop]: Abstraction has 1790 states and 2645 transitions. [2022-12-13 13:22:10,412 INFO L335 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2022-12-13 13:22:10,412 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1790 states and 2645 transitions. [2022-12-13 13:22:10,418 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1627 [2022-12-13 13:22:10,418 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 13:22:10,418 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 13:22:10,421 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 13:22:10,421 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 13:22:10,421 INFO L748 eck$LassoCheckResult]: Stem: 39717#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 39718#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 40633#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 40634#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 41089#L853 assume 1 == ~m_i~0;~m_st~0 := 0; 40959#L853-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 39998#L858-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 39473#L863-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 39474#L868-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 40729#L873-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 40867#L878-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 41250#L883-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 41251#L888-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 40215#L893-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 40216#L898-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 40757#L903-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 40679#L908-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 40680#L913-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 40830#L1206 assume !(0 == ~M_E~0); 40198#L1206-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 40199#L1211-1 assume !(0 == ~T2_E~0); 41082#L1216-1 assume !(0 == ~T3_E~0); 39975#L1221-1 assume !(0 == ~T4_E~0); 39976#L1226-1 assume !(0 == ~T5_E~0); 39649#L1231-1 assume !(0 == ~T6_E~0); 39650#L1236-1 assume !(0 == ~T7_E~0); 41123#L1241-1 assume !(0 == ~T8_E~0); 40045#L1246-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 40046#L1251-1 assume !(0 == ~T10_E~0); 40267#L1256-1 assume !(0 == ~T11_E~0); 39483#L1261-1 assume !(0 == ~T12_E~0); 39484#L1266-1 assume !(0 == ~E_M~0); 41236#L1271-1 assume !(0 == ~E_1~0); 40857#L1276-1 assume !(0 == ~E_2~0); 40858#L1281-1 assume !(0 == ~E_3~0); 40786#L1286-1 assume 0 == ~E_4~0;~E_4~0 := 1; 39878#L1291-1 assume !(0 == ~E_5~0); 39879#L1296-1 assume !(0 == ~E_6~0); 40589#L1301-1 assume !(0 == ~E_7~0); 40590#L1306-1 assume !(0 == ~E_8~0); 41022#L1311-1 assume !(0 == ~E_9~0); 39838#L1316-1 assume !(0 == ~E_10~0); 39839#L1321-1 assume !(0 == ~E_11~0); 40604#L1326-1 assume 0 == ~E_12~0;~E_12~0 := 1; 39705#L1331-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 39706#L598 assume 1 == ~m_pc~0; 39753#L599 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 39754#L609 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 40487#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 40488#L1497 assume !(0 != activate_threads_~tmp~1#1); 41199#L1497-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 41147#L617 assume !(1 == ~t1_pc~0); 40067#L617-2 is_transmit1_triggered_~__retres1~1#1 := 0; 40068#L628 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 40938#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 40939#L1505 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 40696#L1505-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 40697#L636 assume 1 == ~t2_pc~0; 40036#L637 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 40037#L647 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 39860#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 39861#L1513 assume !(0 != activate_threads_~tmp___1~0#1); 40728#L1513-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 40385#L655 assume !(1 == ~t3_pc~0); 40386#L655-2 is_transmit3_triggered_~__retres1~3#1 := 0; 41108#L666 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 40927#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 40928#L1521 assume !(0 != activate_threads_~tmp___2~0#1); 41237#L1521-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 41238#L674 assume 1 == ~t4_pc~0; 39570#L675 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 39571#L685 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 39595#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 39596#L1529 assume !(0 != activate_threads_~tmp___3~0#1); 39862#L1529-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 40384#L693 assume !(1 == ~t5_pc~0); 40539#L693-2 is_transmit5_triggered_~__retres1~5#1 := 0; 40200#L704 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 40201#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 41024#L1537 assume !(0 != activate_threads_~tmp___4~0#1); 40280#L1537-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 40219#L712 assume 1 == ~t6_pc~0; 40220#L713 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 40638#L723 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 39848#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 39849#L1545 assume !(0 != activate_threads_~tmp___5~0#1); 40745#L1545-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 40738#L731 assume 1 == ~t7_pc~0; 39707#L732 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 39708#L742 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 39904#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 41027#L1553 assume !(0 != activate_threads_~tmp___6~0#1); 40968#L1553-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 39811#L750 assume !(1 == ~t8_pc~0); 39504#L750-2 is_transmit8_triggered_~__retres1~8#1 := 0; 39503#L761 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 40009#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 41037#L1561 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 40151#L1561-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 40152#L769 assume 1 == ~t9_pc~0; 40692#L770 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 39669#L780 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 39670#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 39894#L1569 assume !(0 != activate_threads_~tmp___8~0#1); 40904#L1569-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 40987#L788 assume !(1 == ~t10_pc~0); 40555#L788-2 is_transmit10_triggered_~__retres1~10#1 := 0; 40556#L799 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 41109#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 41061#L1577 assume !(0 != activate_threads_~tmp___9~0#1); 39807#L1577-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 39808#L807 assume 1 == ~t11_pc~0; 40993#L808 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 40570#L818 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 40730#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 41167#L1585 assume !(0 != activate_threads_~tmp___10~0#1); 41262#L1585-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 41092#L826 assume !(1 == ~t12_pc~0); 40222#L826-2 is_transmit12_triggered_~__retres1~12#1 := 0; 40223#L837 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 39548#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 39549#L1593 assume !(0 != activate_threads_~tmp___11~0#1); 40378#L1593-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 40290#L1344 assume !(1 == ~M_E~0); 40291#L1344-2 assume !(1 == ~T1_E~0); 40421#L1349-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 40595#L1354-1 assume !(1 == ~T3_E~0); 40596#L1359-1 assume !(1 == ~T4_E~0); 40979#L1364-1 assume !(1 == ~T5_E~0); 39921#L1369-1 assume !(1 == ~T6_E~0); 39922#L1374-1 assume !(1 == ~T7_E~0); 40602#L1379-1 assume !(1 == ~T8_E~0); 40603#L1384-1 assume !(1 == ~T9_E~0); 40678#L1389-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 41125#L1394-1 assume !(1 == ~T11_E~0); 41126#L1399-1 assume !(1 == ~T12_E~0); 41207#L1404-1 assume !(1 == ~E_M~0); 40048#L1409-1 assume !(1 == ~E_1~0); 40049#L1414-1 assume !(1 == ~E_2~0); 40883#L1419-1 assume !(1 == ~E_3~0); 39682#L1424-1 assume !(1 == ~E_4~0); 39683#L1429-1 assume 1 == ~E_5~0;~E_5~0 := 2; 40611#L1434-1 assume !(1 == ~E_6~0); 41140#L1439-1 assume !(1 == ~E_7~0); 39726#L1444-1 assume !(1 == ~E_8~0); 39727#L1449-1 assume !(1 == ~E_9~0); 40156#L1454-1 assume !(1 == ~E_10~0); 40157#L1459-1 assume !(1 == ~E_11~0); 40708#L1464-1 assume !(1 == ~E_12~0); 40709#L1469-1 assume { :end_inline_reset_delta_events } true; 40758#L1815-2 [2022-12-13 13:22:10,421 INFO L750 eck$LassoCheckResult]: Loop: 40758#L1815-2 assume !false; 40905#L1816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 40572#L1181 assume !false; 40642#L1004 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 40593#L926 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 39476#L993 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 40193#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 40737#L1008 assume !(0 != eval_~tmp~0#1); 40433#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 40056#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 40057#L1206-3 assume 0 == ~M_E~0;~M_E~0 := 1; 41257#L1206-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 40707#L1211-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 39795#L1216-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 39796#L1221-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 40400#L1226-3 assume !(0 == ~T5_E~0); 39865#L1231-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 39866#L1236-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 40194#L1241-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 41177#L1246-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 41076#L1251-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 40817#L1256-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 39817#L1261-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 39818#L1266-3 assume !(0 == ~E_M~0); 39863#L1271-3 assume 0 == ~E_1~0;~E_1~0 := 1; 39864#L1276-3 assume 0 == ~E_2~0;~E_2~0 := 1; 40341#L1281-3 assume 0 == ~E_3~0;~E_3~0 := 1; 40342#L1286-3 assume 0 == ~E_4~0;~E_4~0 := 1; 40880#L1291-3 assume 0 == ~E_5~0;~E_5~0 := 1; 40881#L1296-3 assume 0 == ~E_6~0;~E_6~0 := 1; 41243#L1301-3 assume 0 == ~E_7~0;~E_7~0 := 1; 41204#L1306-3 assume !(0 == ~E_8~0); 40461#L1311-3 assume 0 == ~E_9~0;~E_9~0 := 1; 39741#L1316-3 assume 0 == ~E_10~0;~E_10~0 := 1; 39742#L1321-3 assume 0 == ~E_11~0;~E_11~0 := 1; 39819#L1326-3 assume 0 == ~E_12~0;~E_12~0 := 1; 40564#L1331-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 40891#L598-42 assume !(1 == ~m_pc~0); 40892#L598-44 is_master_triggered_~__retres1~0#1 := 0; 41008#L609-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 40224#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 40225#L1497-42 assume !(0 != activate_threads_~tmp~1#1); 41205#L1497-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 40618#L617-42 assume 1 == ~t1_pc~0; 40394#L618-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 40263#L628-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 40264#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 41202#L1505-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 39969#L1505-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 39970#L636-42 assume 1 == ~t2_pc~0; 41182#L637-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 40432#L647-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 40509#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 40510#L1513-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 40975#L1513-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 40840#L655-42 assume !(1 == ~t3_pc~0); 40407#L655-44 is_transmit3_triggered_~__retres1~3#1 := 0; 40408#L666-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 40918#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 40919#L1521-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 41107#L1521-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 41043#L674-42 assume 1 == ~t4_pc~0; 41044#L675-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 40746#L685-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 40747#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 40950#L1529-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 40537#L1529-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 40538#L693-42 assume 1 == ~t5_pc~0; 40805#L694-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 40806#L704-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 40591#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 40592#L1537-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 40861#L1537-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 40166#L712-42 assume !(1 == ~t6_pc~0); 40167#L712-44 is_transmit6_triggered_~__retres1~6#1 := 0; 40479#L723-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 39809#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 39810#L1545-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 40272#L1545-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 40273#L731-42 assume 1 == ~t7_pc~0; 40136#L732-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 39962#L742-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 40614#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 40183#L1553-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 40184#L1553-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 39873#L750-42 assume 1 == ~t8_pc~0; 39874#L751-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 40448#L761-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 40753#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 39756#L1561-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 39757#L1561-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 40536#L769-42 assume 1 == ~t9_pc~0; 40365#L770-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 40366#L780-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 41048#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 41246#L1569-42 assume !(0 != activate_threads_~tmp___8~0#1); 39971#L1569-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 39972#L788-42 assume 1 == ~t10_pc~0; 40544#L789-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 40772#L799-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 40743#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 40744#L1577-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 41255#L1577-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 41230#L807-42 assume 1 == ~t11_pc~0; 40900#L808-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 39592#L818-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 40452#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 39713#L1585-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 39714#L1585-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 39966#L826-42 assume !(1 == ~t12_pc~0); 39968#L826-44 is_transmit12_triggered_~__retres1~12#1 := 0; 40172#L837-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 40560#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 39956#L1593-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 39957#L1593-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 40821#L1344-3 assume 1 == ~M_E~0;~M_E~0 := 2; 40822#L1344-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 40748#L1349-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 40125#L1354-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 40126#L1359-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 40762#L1364-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 41233#L1369-3 assume !(1 == ~T6_E~0); 41139#L1374-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 39882#L1379-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 39883#L1384-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 40123#L1389-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 40124#L1394-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 40413#L1399-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 41145#L1404-3 assume 1 == ~E_M~0;~E_M~0 := 2; 41114#L1409-3 assume !(1 == ~E_1~0); 41115#L1414-3 assume 1 == ~E_2~0;~E_2~0 := 2; 41176#L1419-3 assume 1 == ~E_3~0;~E_3~0 := 2; 40957#L1424-3 assume 1 == ~E_4~0;~E_4~0 := 2; 39772#L1429-3 assume 1 == ~E_5~0;~E_5~0 := 2; 39773#L1434-3 assume 1 == ~E_6~0;~E_6~0 := 2; 40761#L1439-3 assume 1 == ~E_7~0;~E_7~0 := 2; 39719#L1444-3 assume 1 == ~E_8~0;~E_8~0 := 2; 39720#L1449-3 assume !(1 == ~E_9~0); 39825#L1454-3 assume 1 == ~E_10~0;~E_10~0 := 2; 40755#L1459-3 assume 1 == ~E_11~0;~E_11~0 := 2; 40756#L1464-3 assume 1 == ~E_12~0;~E_12~0 := 2; 41138#L1469-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 40622#L926-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 39637#L993-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 39638#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 39801#L1834 assume !(0 == start_simulation_~tmp~3#1); 40868#L1834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 40885#L926-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 40326#L993-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 39525#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 39526#L1789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 41128#L1796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 41124#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 40958#L1847 assume !(0 != start_simulation_~tmp___0~1#1); 40758#L1815-2 [2022-12-13 13:22:10,422 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 13:22:10,422 INFO L85 PathProgramCache]: Analyzing trace with hash 1133017134, now seen corresponding path program 1 times [2022-12-13 13:22:10,422 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 13:22:10,422 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1847999253] [2022-12-13 13:22:10,422 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 13:22:10,422 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 13:22:10,433 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 13:22:10,459 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 13:22:10,459 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 13:22:10,459 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1847999253] [2022-12-13 13:22:10,460 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1847999253] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 13:22:10,460 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 13:22:10,460 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 13:22:10,460 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1851722227] [2022-12-13 13:22:10,460 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 13:22:10,460 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 13:22:10,461 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 13:22:10,461 INFO L85 PathProgramCache]: Analyzing trace with hash 1753227539, now seen corresponding path program 1 times [2022-12-13 13:22:10,461 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 13:22:10,461 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1906528155] [2022-12-13 13:22:10,461 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 13:22:10,461 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 13:22:10,472 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 13:22:10,507 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 13:22:10,508 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 13:22:10,508 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1906528155] [2022-12-13 13:22:10,508 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1906528155] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 13:22:10,508 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 13:22:10,508 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 13:22:10,508 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1462864524] [2022-12-13 13:22:10,508 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 13:22:10,509 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 13:22:10,509 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 13:22:10,509 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 13:22:10,509 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 13:22:10,509 INFO L87 Difference]: Start difference. First operand 1790 states and 2645 transitions. cyclomatic complexity: 856 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 13:22:10,539 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 13:22:10,539 INFO L93 Difference]: Finished difference Result 1790 states and 2644 transitions. [2022-12-13 13:22:10,539 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1790 states and 2644 transitions. [2022-12-13 13:22:10,546 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1627 [2022-12-13 13:22:10,552 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1790 states to 1790 states and 2644 transitions. [2022-12-13 13:22:10,552 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1790 [2022-12-13 13:22:10,553 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1790 [2022-12-13 13:22:10,553 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1790 states and 2644 transitions. [2022-12-13 13:22:10,556 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 13:22:10,556 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1790 states and 2644 transitions. [2022-12-13 13:22:10,559 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1790 states and 2644 transitions. [2022-12-13 13:22:10,590 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1790 to 1790. [2022-12-13 13:22:10,593 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1790 states, 1790 states have (on average 1.4770949720670392) internal successors, (2644), 1789 states have internal predecessors, (2644), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 13:22:10,597 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1790 states to 1790 states and 2644 transitions. [2022-12-13 13:22:10,597 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1790 states and 2644 transitions. [2022-12-13 13:22:10,598 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 13:22:10,598 INFO L428 stractBuchiCegarLoop]: Abstraction has 1790 states and 2644 transitions. [2022-12-13 13:22:10,598 INFO L335 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2022-12-13 13:22:10,599 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1790 states and 2644 transitions. [2022-12-13 13:22:10,604 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1627 [2022-12-13 13:22:10,604 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 13:22:10,604 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 13:22:10,606 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 13:22:10,607 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 13:22:10,607 INFO L748 eck$LassoCheckResult]: Stem: 43304#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 43305#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 44220#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 44221#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 44676#L853 assume 1 == ~m_i~0;~m_st~0 := 0; 44546#L853-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 43585#L858-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 43060#L863-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 43061#L868-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 44316#L873-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 44454#L878-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 44837#L883-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 44838#L888-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 43802#L893-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 43803#L898-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 44344#L903-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 44266#L908-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 44267#L913-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 44417#L1206 assume !(0 == ~M_E~0); 43785#L1206-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 43786#L1211-1 assume !(0 == ~T2_E~0); 44669#L1216-1 assume !(0 == ~T3_E~0); 43562#L1221-1 assume !(0 == ~T4_E~0); 43563#L1226-1 assume !(0 == ~T5_E~0); 43236#L1231-1 assume !(0 == ~T6_E~0); 43237#L1236-1 assume !(0 == ~T7_E~0); 44710#L1241-1 assume !(0 == ~T8_E~0); 43632#L1246-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 43633#L1251-1 assume !(0 == ~T10_E~0); 43854#L1256-1 assume !(0 == ~T11_E~0); 43070#L1261-1 assume !(0 == ~T12_E~0); 43071#L1266-1 assume !(0 == ~E_M~0); 44823#L1271-1 assume !(0 == ~E_1~0); 44444#L1276-1 assume !(0 == ~E_2~0); 44445#L1281-1 assume !(0 == ~E_3~0); 44373#L1286-1 assume 0 == ~E_4~0;~E_4~0 := 1; 43465#L1291-1 assume !(0 == ~E_5~0); 43466#L1296-1 assume !(0 == ~E_6~0); 44176#L1301-1 assume !(0 == ~E_7~0); 44177#L1306-1 assume !(0 == ~E_8~0); 44609#L1311-1 assume !(0 == ~E_9~0); 43425#L1316-1 assume !(0 == ~E_10~0); 43426#L1321-1 assume !(0 == ~E_11~0); 44191#L1326-1 assume 0 == ~E_12~0;~E_12~0 := 1; 43292#L1331-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 43293#L598 assume 1 == ~m_pc~0; 43340#L599 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 43341#L609 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 44074#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 44075#L1497 assume !(0 != activate_threads_~tmp~1#1); 44786#L1497-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 44734#L617 assume !(1 == ~t1_pc~0); 43654#L617-2 is_transmit1_triggered_~__retres1~1#1 := 0; 43655#L628 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 44525#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 44526#L1505 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 44283#L1505-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 44284#L636 assume 1 == ~t2_pc~0; 43623#L637 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 43624#L647 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 43447#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 43448#L1513 assume !(0 != activate_threads_~tmp___1~0#1); 44315#L1513-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 43972#L655 assume !(1 == ~t3_pc~0); 43973#L655-2 is_transmit3_triggered_~__retres1~3#1 := 0; 44695#L666 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 44514#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 44515#L1521 assume !(0 != activate_threads_~tmp___2~0#1); 44824#L1521-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 44825#L674 assume 1 == ~t4_pc~0; 43157#L675 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 43158#L685 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 43182#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 43183#L1529 assume !(0 != activate_threads_~tmp___3~0#1); 43449#L1529-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 43971#L693 assume !(1 == ~t5_pc~0); 44126#L693-2 is_transmit5_triggered_~__retres1~5#1 := 0; 43787#L704 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 43788#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 44611#L1537 assume !(0 != activate_threads_~tmp___4~0#1); 43867#L1537-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 43806#L712 assume 1 == ~t6_pc~0; 43807#L713 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 44225#L723 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 43435#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 43436#L1545 assume !(0 != activate_threads_~tmp___5~0#1); 44332#L1545-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 44325#L731 assume 1 == ~t7_pc~0; 43294#L732 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 43295#L742 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 43491#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 44614#L1553 assume !(0 != activate_threads_~tmp___6~0#1); 44555#L1553-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 43398#L750 assume !(1 == ~t8_pc~0); 43091#L750-2 is_transmit8_triggered_~__retres1~8#1 := 0; 43090#L761 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 43596#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 44624#L1561 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 43738#L1561-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 43739#L769 assume 1 == ~t9_pc~0; 44279#L770 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 43256#L780 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 43257#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 43481#L1569 assume !(0 != activate_threads_~tmp___8~0#1); 44491#L1569-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 44574#L788 assume !(1 == ~t10_pc~0); 44142#L788-2 is_transmit10_triggered_~__retres1~10#1 := 0; 44143#L799 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 44696#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 44648#L1577 assume !(0 != activate_threads_~tmp___9~0#1); 43394#L1577-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 43395#L807 assume 1 == ~t11_pc~0; 44580#L808 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 44157#L818 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 44317#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 44754#L1585 assume !(0 != activate_threads_~tmp___10~0#1); 44849#L1585-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 44679#L826 assume !(1 == ~t12_pc~0); 43809#L826-2 is_transmit12_triggered_~__retres1~12#1 := 0; 43810#L837 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 43135#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 43136#L1593 assume !(0 != activate_threads_~tmp___11~0#1); 43965#L1593-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 43877#L1344 assume !(1 == ~M_E~0); 43878#L1344-2 assume !(1 == ~T1_E~0); 44008#L1349-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 44182#L1354-1 assume !(1 == ~T3_E~0); 44183#L1359-1 assume !(1 == ~T4_E~0); 44566#L1364-1 assume !(1 == ~T5_E~0); 43508#L1369-1 assume !(1 == ~T6_E~0); 43509#L1374-1 assume !(1 == ~T7_E~0); 44189#L1379-1 assume !(1 == ~T8_E~0); 44190#L1384-1 assume !(1 == ~T9_E~0); 44265#L1389-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 44712#L1394-1 assume !(1 == ~T11_E~0); 44713#L1399-1 assume !(1 == ~T12_E~0); 44794#L1404-1 assume !(1 == ~E_M~0); 43635#L1409-1 assume !(1 == ~E_1~0); 43636#L1414-1 assume !(1 == ~E_2~0); 44470#L1419-1 assume !(1 == ~E_3~0); 43269#L1424-1 assume !(1 == ~E_4~0); 43270#L1429-1 assume 1 == ~E_5~0;~E_5~0 := 2; 44198#L1434-1 assume !(1 == ~E_6~0); 44727#L1439-1 assume !(1 == ~E_7~0); 43313#L1444-1 assume !(1 == ~E_8~0); 43314#L1449-1 assume !(1 == ~E_9~0); 43743#L1454-1 assume !(1 == ~E_10~0); 43744#L1459-1 assume !(1 == ~E_11~0); 44295#L1464-1 assume !(1 == ~E_12~0); 44296#L1469-1 assume { :end_inline_reset_delta_events } true; 44345#L1815-2 [2022-12-13 13:22:10,607 INFO L750 eck$LassoCheckResult]: Loop: 44345#L1815-2 assume !false; 44492#L1816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 44159#L1181 assume !false; 44229#L1004 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 44180#L926 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 43063#L993 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 43780#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 44324#L1008 assume !(0 != eval_~tmp~0#1); 44020#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 43643#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 43644#L1206-3 assume 0 == ~M_E~0;~M_E~0 := 1; 44844#L1206-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 44294#L1211-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 43382#L1216-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 43383#L1221-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 43987#L1226-3 assume !(0 == ~T5_E~0); 43452#L1231-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 43453#L1236-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 43781#L1241-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 44764#L1246-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 44663#L1251-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 44404#L1256-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 43404#L1261-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 43405#L1266-3 assume !(0 == ~E_M~0); 43450#L1271-3 assume 0 == ~E_1~0;~E_1~0 := 1; 43451#L1276-3 assume 0 == ~E_2~0;~E_2~0 := 1; 43928#L1281-3 assume 0 == ~E_3~0;~E_3~0 := 1; 43929#L1286-3 assume 0 == ~E_4~0;~E_4~0 := 1; 44467#L1291-3 assume 0 == ~E_5~0;~E_5~0 := 1; 44468#L1296-3 assume 0 == ~E_6~0;~E_6~0 := 1; 44830#L1301-3 assume 0 == ~E_7~0;~E_7~0 := 1; 44791#L1306-3 assume !(0 == ~E_8~0); 44048#L1311-3 assume 0 == ~E_9~0;~E_9~0 := 1; 43328#L1316-3 assume 0 == ~E_10~0;~E_10~0 := 1; 43329#L1321-3 assume 0 == ~E_11~0;~E_11~0 := 1; 43406#L1326-3 assume 0 == ~E_12~0;~E_12~0 := 1; 44151#L1331-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 44478#L598-42 assume 1 == ~m_pc~0; 44480#L599-14 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 44595#L609-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 43811#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 43812#L1497-42 assume !(0 != activate_threads_~tmp~1#1); 44792#L1497-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 44205#L617-42 assume 1 == ~t1_pc~0; 43981#L618-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 43850#L628-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 43851#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 44789#L1505-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 43556#L1505-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 43557#L636-42 assume 1 == ~t2_pc~0; 44769#L637-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 44019#L647-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 44096#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 44097#L1513-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 44562#L1513-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 44427#L655-42 assume !(1 == ~t3_pc~0); 43994#L655-44 is_transmit3_triggered_~__retres1~3#1 := 0; 43995#L666-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 44505#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 44506#L1521-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 44694#L1521-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 44630#L674-42 assume 1 == ~t4_pc~0; 44631#L675-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 44333#L685-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 44334#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 44537#L1529-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 44124#L1529-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 44125#L693-42 assume 1 == ~t5_pc~0; 44392#L694-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 44393#L704-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 44178#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 44179#L1537-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 44448#L1537-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 43753#L712-42 assume !(1 == ~t6_pc~0); 43754#L712-44 is_transmit6_triggered_~__retres1~6#1 := 0; 44066#L723-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 43396#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 43397#L1545-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 43859#L1545-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 43860#L731-42 assume 1 == ~t7_pc~0; 43723#L732-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 43549#L742-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 44201#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 43770#L1553-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 43771#L1553-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 43460#L750-42 assume 1 == ~t8_pc~0; 43461#L751-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 44035#L761-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 44340#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 43343#L1561-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 43344#L1561-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 44123#L769-42 assume 1 == ~t9_pc~0; 43952#L770-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 43953#L780-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 44635#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 44833#L1569-42 assume !(0 != activate_threads_~tmp___8~0#1); 43558#L1569-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 43559#L788-42 assume 1 == ~t10_pc~0; 44131#L789-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 44359#L799-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 44330#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 44331#L1577-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 44842#L1577-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 44817#L807-42 assume 1 == ~t11_pc~0; 44487#L808-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 43179#L818-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 44039#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 43300#L1585-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 43301#L1585-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 43553#L826-42 assume 1 == ~t12_pc~0; 43554#L827-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 43759#L837-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 44147#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 43543#L1593-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 43544#L1593-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 44408#L1344-3 assume 1 == ~M_E~0;~M_E~0 := 2; 44409#L1344-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 44335#L1349-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 43712#L1354-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 43713#L1359-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 44349#L1364-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 44820#L1369-3 assume !(1 == ~T6_E~0); 44726#L1374-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 43469#L1379-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 43470#L1384-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 43710#L1389-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 43711#L1394-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 44000#L1399-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 44732#L1404-3 assume 1 == ~E_M~0;~E_M~0 := 2; 44701#L1409-3 assume !(1 == ~E_1~0); 44702#L1414-3 assume 1 == ~E_2~0;~E_2~0 := 2; 44763#L1419-3 assume 1 == ~E_3~0;~E_3~0 := 2; 44544#L1424-3 assume 1 == ~E_4~0;~E_4~0 := 2; 43359#L1429-3 assume 1 == ~E_5~0;~E_5~0 := 2; 43360#L1434-3 assume 1 == ~E_6~0;~E_6~0 := 2; 44348#L1439-3 assume 1 == ~E_7~0;~E_7~0 := 2; 43306#L1444-3 assume 1 == ~E_8~0;~E_8~0 := 2; 43307#L1449-3 assume !(1 == ~E_9~0); 43412#L1454-3 assume 1 == ~E_10~0;~E_10~0 := 2; 44342#L1459-3 assume 1 == ~E_11~0;~E_11~0 := 2; 44343#L1464-3 assume 1 == ~E_12~0;~E_12~0 := 2; 44725#L1469-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 44209#L926-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 43224#L993-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 43225#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 43388#L1834 assume !(0 == start_simulation_~tmp~3#1); 44455#L1834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 44472#L926-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 43913#L993-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 43112#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 43113#L1789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 44715#L1796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 44711#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 44545#L1847 assume !(0 != start_simulation_~tmp___0~1#1); 44345#L1815-2 [2022-12-13 13:22:10,608 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 13:22:10,608 INFO L85 PathProgramCache]: Analyzing trace with hash -1544509712, now seen corresponding path program 1 times [2022-12-13 13:22:10,608 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 13:22:10,608 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1767229769] [2022-12-13 13:22:10,608 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 13:22:10,608 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 13:22:10,622 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 13:22:10,661 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 13:22:10,661 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 13:22:10,661 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1767229769] [2022-12-13 13:22:10,661 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1767229769] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 13:22:10,661 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 13:22:10,662 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-12-13 13:22:10,662 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [735893833] [2022-12-13 13:22:10,662 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 13:22:10,662 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 13:22:10,663 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 13:22:10,663 INFO L85 PathProgramCache]: Analyzing trace with hash -1085774191, now seen corresponding path program 1 times [2022-12-13 13:22:10,663 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 13:22:10,663 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [684536401] [2022-12-13 13:22:10,663 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 13:22:10,663 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 13:22:10,677 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 13:22:10,715 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 13:22:10,715 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 13:22:10,715 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [684536401] [2022-12-13 13:22:10,716 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [684536401] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 13:22:10,716 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 13:22:10,716 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 13:22:10,716 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [245573368] [2022-12-13 13:22:10,716 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 13:22:10,717 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 13:22:10,717 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 13:22:10,717 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 13:22:10,717 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 13:22:10,718 INFO L87 Difference]: Start difference. First operand 1790 states and 2644 transitions. cyclomatic complexity: 855 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 2 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 13:22:10,754 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 13:22:10,754 INFO L93 Difference]: Finished difference Result 1790 states and 2639 transitions. [2022-12-13 13:22:10,754 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1790 states and 2639 transitions. [2022-12-13 13:22:10,762 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1627 [2022-12-13 13:22:10,771 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1790 states to 1790 states and 2639 transitions. [2022-12-13 13:22:10,771 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1790 [2022-12-13 13:22:10,773 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1790 [2022-12-13 13:22:10,773 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1790 states and 2639 transitions. [2022-12-13 13:22:10,777 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 13:22:10,777 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1790 states and 2639 transitions. [2022-12-13 13:22:10,781 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1790 states and 2639 transitions. [2022-12-13 13:22:10,803 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1790 to 1790. [2022-12-13 13:22:10,806 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1790 states, 1790 states have (on average 1.4743016759776537) internal successors, (2639), 1789 states have internal predecessors, (2639), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 13:22:10,810 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1790 states to 1790 states and 2639 transitions. [2022-12-13 13:22:10,811 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1790 states and 2639 transitions. [2022-12-13 13:22:10,811 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 13:22:10,811 INFO L428 stractBuchiCegarLoop]: Abstraction has 1790 states and 2639 transitions. [2022-12-13 13:22:10,812 INFO L335 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2022-12-13 13:22:10,812 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1790 states and 2639 transitions. [2022-12-13 13:22:10,818 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1627 [2022-12-13 13:22:10,818 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 13:22:10,818 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 13:22:10,820 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 13:22:10,821 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 13:22:10,821 INFO L748 eck$LassoCheckResult]: Stem: 46891#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 46892#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 47808#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 47809#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 48263#L853 assume 1 == ~m_i~0;~m_st~0 := 0; 48133#L853-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 47172#L858-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 46647#L863-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 46648#L868-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 47903#L873-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 48041#L878-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 48424#L883-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 48425#L888-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 47391#L893-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 47392#L898-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 47931#L903-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 47853#L908-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 47854#L913-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 48004#L1206 assume !(0 == ~M_E~0); 47372#L1206-2 assume !(0 == ~T1_E~0); 47373#L1211-1 assume !(0 == ~T2_E~0); 48257#L1216-1 assume !(0 == ~T3_E~0); 47149#L1221-1 assume !(0 == ~T4_E~0); 47150#L1226-1 assume !(0 == ~T5_E~0); 46825#L1231-1 assume !(0 == ~T6_E~0); 46826#L1236-1 assume !(0 == ~T7_E~0); 48297#L1241-1 assume !(0 == ~T8_E~0); 47219#L1246-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 47220#L1251-1 assume !(0 == ~T10_E~0); 47441#L1256-1 assume !(0 == ~T11_E~0); 46657#L1261-1 assume !(0 == ~T12_E~0); 46658#L1266-1 assume !(0 == ~E_M~0); 48410#L1271-1 assume !(0 == ~E_1~0); 48031#L1276-1 assume !(0 == ~E_2~0); 48032#L1281-1 assume !(0 == ~E_3~0); 47962#L1286-1 assume 0 == ~E_4~0;~E_4~0 := 1; 47052#L1291-1 assume !(0 == ~E_5~0); 47053#L1296-1 assume !(0 == ~E_6~0); 47763#L1301-1 assume !(0 == ~E_7~0); 47764#L1306-1 assume !(0 == ~E_8~0); 48196#L1311-1 assume !(0 == ~E_9~0); 47012#L1316-1 assume !(0 == ~E_10~0); 47013#L1321-1 assume !(0 == ~E_11~0); 47778#L1326-1 assume 0 == ~E_12~0;~E_12~0 := 1; 46879#L1331-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 46880#L598 assume 1 == ~m_pc~0; 46927#L599 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 46928#L609 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 47661#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 47662#L1497 assume !(0 != activate_threads_~tmp~1#1); 48373#L1497-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 48321#L617 assume !(1 == ~t1_pc~0); 47241#L617-2 is_transmit1_triggered_~__retres1~1#1 := 0; 47242#L628 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 48112#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 48113#L1505 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 47870#L1505-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 47871#L636 assume 1 == ~t2_pc~0; 47210#L637 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 47211#L647 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 47034#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 47035#L1513 assume !(0 != activate_threads_~tmp___1~0#1); 47902#L1513-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 47560#L655 assume !(1 == ~t3_pc~0); 47561#L655-2 is_transmit3_triggered_~__retres1~3#1 := 0; 48282#L666 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 48101#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 48102#L1521 assume !(0 != activate_threads_~tmp___2~0#1); 48411#L1521-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 48412#L674 assume 1 == ~t4_pc~0; 46744#L675 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 46745#L685 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 46769#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 46770#L1529 assume !(0 != activate_threads_~tmp___3~0#1); 47038#L1529-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 47558#L693 assume !(1 == ~t5_pc~0); 47714#L693-2 is_transmit5_triggered_~__retres1~5#1 := 0; 47376#L704 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 47377#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 48198#L1537 assume !(0 != activate_threads_~tmp___4~0#1); 47456#L1537-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 47393#L712 assume 1 == ~t6_pc~0; 47394#L713 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 47812#L723 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 47022#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 47023#L1545 assume !(0 != activate_threads_~tmp___5~0#1); 47919#L1545-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 47912#L731 assume 1 == ~t7_pc~0; 46881#L732 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 46882#L742 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 47078#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 48201#L1553 assume !(0 != activate_threads_~tmp___6~0#1); 48143#L1553-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 46985#L750 assume !(1 == ~t8_pc~0); 46678#L750-2 is_transmit8_triggered_~__retres1~8#1 := 0; 46677#L761 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 47183#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 48211#L1561 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 47325#L1561-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 47326#L769 assume 1 == ~t9_pc~0; 47868#L770 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 46843#L780 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 46844#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 47068#L1569 assume !(0 != activate_threads_~tmp___8~0#1); 48078#L1569-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 48161#L788 assume !(1 == ~t10_pc~0); 47729#L788-2 is_transmit10_triggered_~__retres1~10#1 := 0; 47730#L799 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 48283#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 48236#L1577 assume !(0 != activate_threads_~tmp___9~0#1); 46981#L1577-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 46982#L807 assume 1 == ~t11_pc~0; 48167#L808 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 47744#L818 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 47904#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 48341#L1585 assume !(0 != activate_threads_~tmp___10~0#1); 48436#L1585-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 48266#L826 assume !(1 == ~t12_pc~0); 47396#L826-2 is_transmit12_triggered_~__retres1~12#1 := 0; 47397#L837 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 46722#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 46723#L1593 assume !(0 != activate_threads_~tmp___11~0#1); 47552#L1593-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 47464#L1344 assume !(1 == ~M_E~0); 47465#L1344-2 assume !(1 == ~T1_E~0); 47595#L1349-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 47771#L1354-1 assume !(1 == ~T3_E~0); 47772#L1359-1 assume !(1 == ~T4_E~0); 48153#L1364-1 assume !(1 == ~T5_E~0); 47095#L1369-1 assume !(1 == ~T6_E~0); 47096#L1374-1 assume !(1 == ~T7_E~0); 47776#L1379-1 assume !(1 == ~T8_E~0); 47777#L1384-1 assume !(1 == ~T9_E~0); 47852#L1389-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 48299#L1394-1 assume !(1 == ~T11_E~0); 48300#L1399-1 assume !(1 == ~T12_E~0); 48381#L1404-1 assume !(1 == ~E_M~0); 47222#L1409-1 assume !(1 == ~E_1~0); 47223#L1414-1 assume !(1 == ~E_2~0); 48057#L1419-1 assume !(1 == ~E_3~0); 46856#L1424-1 assume !(1 == ~E_4~0); 46857#L1429-1 assume 1 == ~E_5~0;~E_5~0 := 2; 47787#L1434-1 assume !(1 == ~E_6~0); 48314#L1439-1 assume !(1 == ~E_7~0); 46900#L1444-1 assume !(1 == ~E_8~0); 46901#L1449-1 assume !(1 == ~E_9~0); 47331#L1454-1 assume !(1 == ~E_10~0); 47332#L1459-1 assume !(1 == ~E_11~0); 47882#L1464-1 assume !(1 == ~E_12~0); 47883#L1469-1 assume { :end_inline_reset_delta_events } true; 47932#L1815-2 [2022-12-13 13:22:10,821 INFO L750 eck$LassoCheckResult]: Loop: 47932#L1815-2 assume !false; 48079#L1816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 47746#L1181 assume !false; 47816#L1004 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 47767#L926 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 46650#L993 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 47368#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 47911#L1008 assume !(0 != eval_~tmp~0#1); 47607#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 47232#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 47233#L1206-3 assume 0 == ~M_E~0;~M_E~0 := 1; 48431#L1206-5 assume !(0 == ~T1_E~0); 47881#L1211-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 46969#L1216-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 46970#L1221-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 47574#L1226-3 assume !(0 == ~T5_E~0); 47039#L1231-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 47040#L1236-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 47367#L1241-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 48351#L1246-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 48250#L1251-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 47991#L1256-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 46991#L1261-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 46992#L1266-3 assume !(0 == ~E_M~0); 47036#L1271-3 assume 0 == ~E_1~0;~E_1~0 := 1; 47037#L1276-3 assume 0 == ~E_2~0;~E_2~0 := 1; 47515#L1281-3 assume 0 == ~E_3~0;~E_3~0 := 1; 47516#L1286-3 assume 0 == ~E_4~0;~E_4~0 := 1; 48054#L1291-3 assume 0 == ~E_5~0;~E_5~0 := 1; 48055#L1296-3 assume 0 == ~E_6~0;~E_6~0 := 1; 48417#L1301-3 assume 0 == ~E_7~0;~E_7~0 := 1; 48378#L1306-3 assume !(0 == ~E_8~0); 47635#L1311-3 assume 0 == ~E_9~0;~E_9~0 := 1; 46915#L1316-3 assume 0 == ~E_10~0;~E_10~0 := 1; 46916#L1321-3 assume 0 == ~E_11~0;~E_11~0 := 1; 46993#L1326-3 assume 0 == ~E_12~0;~E_12~0 := 1; 47737#L1331-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 48065#L598-42 assume !(1 == ~m_pc~0); 48066#L598-44 is_master_triggered_~__retres1~0#1 := 0; 48182#L609-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 47398#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 47399#L1497-42 assume !(0 != activate_threads_~tmp~1#1); 48379#L1497-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 47792#L617-42 assume 1 == ~t1_pc~0; 47568#L618-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 47437#L628-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 47438#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 48376#L1505-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 47143#L1505-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 47144#L636-42 assume 1 == ~t2_pc~0; 48356#L637-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 47606#L647-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 47683#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 47684#L1513-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 48149#L1513-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 48014#L655-42 assume !(1 == ~t3_pc~0); 47581#L655-44 is_transmit3_triggered_~__retres1~3#1 := 0; 47582#L666-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 48092#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 48093#L1521-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 48281#L1521-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 48217#L674-42 assume 1 == ~t4_pc~0; 48218#L675-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 47920#L685-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 47921#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 48124#L1529-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 47711#L1529-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 47712#L693-42 assume 1 == ~t5_pc~0; 47979#L694-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 47980#L704-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 47765#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 47766#L1537-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 48035#L1537-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 47340#L712-42 assume !(1 == ~t6_pc~0); 47341#L712-44 is_transmit6_triggered_~__retres1~6#1 := 0; 47653#L723-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 46983#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 46984#L1545-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 47446#L1545-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 47447#L731-42 assume 1 == ~t7_pc~0; 47310#L732-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 47136#L742-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 47788#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 47357#L1553-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 47358#L1553-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 47047#L750-42 assume 1 == ~t8_pc~0; 47048#L751-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 47622#L761-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 47927#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 46930#L1561-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 46931#L1561-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 47710#L769-42 assume 1 == ~t9_pc~0; 47539#L770-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 47540#L780-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 48222#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 48420#L1569-42 assume !(0 != activate_threads_~tmp___8~0#1); 47145#L1569-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 47146#L788-42 assume 1 == ~t10_pc~0; 47718#L789-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 47946#L799-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 47917#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 47918#L1577-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 48429#L1577-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 48404#L807-42 assume 1 == ~t11_pc~0; 48074#L808-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 46766#L818-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 47626#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 46887#L1585-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 46888#L1585-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 47140#L826-42 assume 1 == ~t12_pc~0; 47141#L827-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 47346#L837-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 47734#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 47130#L1593-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 47131#L1593-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 47995#L1344-3 assume 1 == ~M_E~0;~M_E~0 := 2; 47996#L1344-5 assume !(1 == ~T1_E~0); 47922#L1349-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 47299#L1354-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 47300#L1359-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 47936#L1364-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 48407#L1369-3 assume !(1 == ~T6_E~0); 48313#L1374-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 47056#L1379-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 47057#L1384-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 47297#L1389-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 47298#L1394-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 47587#L1399-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 48319#L1404-3 assume 1 == ~E_M~0;~E_M~0 := 2; 48288#L1409-3 assume !(1 == ~E_1~0); 48289#L1414-3 assume 1 == ~E_2~0;~E_2~0 := 2; 48350#L1419-3 assume 1 == ~E_3~0;~E_3~0 := 2; 48131#L1424-3 assume 1 == ~E_4~0;~E_4~0 := 2; 46946#L1429-3 assume 1 == ~E_5~0;~E_5~0 := 2; 46947#L1434-3 assume 1 == ~E_6~0;~E_6~0 := 2; 47935#L1439-3 assume 1 == ~E_7~0;~E_7~0 := 2; 46893#L1444-3 assume 1 == ~E_8~0;~E_8~0 := 2; 46894#L1449-3 assume !(1 == ~E_9~0); 46999#L1454-3 assume 1 == ~E_10~0;~E_10~0 := 2; 47929#L1459-3 assume 1 == ~E_11~0;~E_11~0 := 2; 47930#L1464-3 assume 1 == ~E_12~0;~E_12~0 := 2; 48312#L1469-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 47796#L926-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 46811#L993-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 46812#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 46975#L1834 assume !(0 == start_simulation_~tmp~3#1); 48042#L1834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 48059#L926-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 47500#L993-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 46699#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 46700#L1789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 48302#L1796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 48298#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 48132#L1847 assume !(0 != start_simulation_~tmp___0~1#1); 47932#L1815-2 [2022-12-13 13:22:10,822 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 13:22:10,822 INFO L85 PathProgramCache]: Analyzing trace with hash -2089382286, now seen corresponding path program 1 times [2022-12-13 13:22:10,822 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 13:22:10,822 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1648887126] [2022-12-13 13:22:10,822 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 13:22:10,822 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 13:22:10,835 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 13:22:10,900 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 13:22:10,900 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 13:22:10,901 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1648887126] [2022-12-13 13:22:10,901 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1648887126] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 13:22:10,901 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 13:22:10,901 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 13:22:10,901 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [569323458] [2022-12-13 13:22:10,901 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 13:22:10,902 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 13:22:10,902 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 13:22:10,902 INFO L85 PathProgramCache]: Analyzing trace with hash 2023900434, now seen corresponding path program 1 times [2022-12-13 13:22:10,902 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 13:22:10,902 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1554986937] [2022-12-13 13:22:10,902 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 13:22:10,903 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 13:22:10,916 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 13:22:10,955 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 13:22:10,955 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 13:22:10,955 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1554986937] [2022-12-13 13:22:10,955 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1554986937] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 13:22:10,955 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 13:22:10,955 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 13:22:10,955 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1190285850] [2022-12-13 13:22:10,955 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 13:22:10,956 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 13:22:10,956 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 13:22:10,956 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 13:22:10,957 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 13:22:10,957 INFO L87 Difference]: Start difference. First operand 1790 states and 2639 transitions. cyclomatic complexity: 850 Second operand has 4 states, 4 states have (on average 37.5) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 13:22:11,102 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 13:22:11,102 INFO L93 Difference]: Finished difference Result 3324 states and 4886 transitions. [2022-12-13 13:22:11,103 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3324 states and 4886 transitions. [2022-12-13 13:22:11,116 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 3135 [2022-12-13 13:22:11,125 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3324 states to 3324 states and 4886 transitions. [2022-12-13 13:22:11,125 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3324 [2022-12-13 13:22:11,127 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3324 [2022-12-13 13:22:11,127 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3324 states and 4886 transitions. [2022-12-13 13:22:11,129 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 13:22:11,130 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3324 states and 4886 transitions. [2022-12-13 13:22:11,133 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3324 states and 4886 transitions. [2022-12-13 13:22:11,175 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3324 to 3324. [2022-12-13 13:22:11,179 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3324 states, 3324 states have (on average 1.4699157641395908) internal successors, (4886), 3323 states have internal predecessors, (4886), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 13:22:11,186 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3324 states to 3324 states and 4886 transitions. [2022-12-13 13:22:11,186 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3324 states and 4886 transitions. [2022-12-13 13:22:11,186 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 13:22:11,186 INFO L428 stractBuchiCegarLoop]: Abstraction has 3324 states and 4886 transitions. [2022-12-13 13:22:11,186 INFO L335 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2022-12-13 13:22:11,187 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3324 states and 4886 transitions. [2022-12-13 13:22:11,195 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 3135 [2022-12-13 13:22:11,195 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 13:22:11,196 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 13:22:11,197 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 13:22:11,197 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 13:22:11,198 INFO L748 eck$LassoCheckResult]: Stem: 52016#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 52017#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 52943#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 52944#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 53439#L853 assume 1 == ~m_i~0;~m_st~0 := 0; 53290#L853-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 52297#L858-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 51771#L863-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 51772#L868-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 53045#L873-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 53194#L878-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 53650#L883-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 53651#L888-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 52518#L893-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 52519#L898-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 53075#L903-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 52992#L908-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 52993#L913-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 53151#L1206 assume !(0 == ~M_E~0); 52499#L1206-2 assume !(0 == ~T1_E~0); 52500#L1211-1 assume !(0 == ~T2_E~0); 53433#L1216-1 assume !(0 == ~T3_E~0); 52274#L1221-1 assume !(0 == ~T4_E~0); 52275#L1226-1 assume !(0 == ~T5_E~0); 51949#L1231-1 assume !(0 == ~T6_E~0); 51950#L1236-1 assume !(0 == ~T7_E~0); 53478#L1241-1 assume !(0 == ~T8_E~0); 52344#L1246-1 assume !(0 == ~T9_E~0); 52345#L1251-1 assume !(0 == ~T10_E~0); 52569#L1256-1 assume !(0 == ~T11_E~0); 51781#L1261-1 assume !(0 == ~T12_E~0); 51782#L1266-1 assume !(0 == ~E_M~0); 53633#L1271-1 assume !(0 == ~E_1~0); 53182#L1276-1 assume !(0 == ~E_2~0); 53183#L1281-1 assume !(0 == ~E_3~0); 53108#L1286-1 assume 0 == ~E_4~0;~E_4~0 := 1; 52177#L1291-1 assume !(0 == ~E_5~0); 52178#L1296-1 assume !(0 == ~E_6~0); 52898#L1301-1 assume !(0 == ~E_7~0); 52899#L1306-1 assume !(0 == ~E_8~0); 53364#L1311-1 assume !(0 == ~E_9~0); 52137#L1316-1 assume !(0 == ~E_10~0); 52138#L1321-1 assume !(0 == ~E_11~0); 52913#L1326-1 assume 0 == ~E_12~0;~E_12~0 := 1; 52004#L1331-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 52005#L598 assume 1 == ~m_pc~0; 52052#L599 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 52053#L609 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 52791#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 52792#L1497 assume !(0 != activate_threads_~tmp~1#1); 53584#L1497-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 53518#L617 assume !(1 == ~t1_pc~0); 52367#L617-2 is_transmit1_triggered_~__retres1~1#1 := 0; 52368#L628 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 53267#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 53268#L1505 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 53010#L1505-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 53011#L636 assume 1 == ~t2_pc~0; 52335#L637 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 52336#L647 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 52159#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 52160#L1513 assume !(0 != activate_threads_~tmp___1~0#1); 53044#L1513-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 52688#L655 assume !(1 == ~t3_pc~0); 52689#L655-2 is_transmit3_triggered_~__retres1~3#1 := 0; 53462#L666 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 53255#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 53256#L1521 assume !(0 != activate_threads_~tmp___2~0#1); 53634#L1521-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 53635#L674 assume 1 == ~t4_pc~0; 51868#L675 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 51869#L685 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 51893#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 51894#L1529 assume !(0 != activate_threads_~tmp___3~0#1); 52161#L1529-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 52687#L693 assume !(1 == ~t5_pc~0); 52849#L693-2 is_transmit5_triggered_~__retres1~5#1 := 0; 52503#L704 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 52504#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 53366#L1537 assume !(0 != activate_threads_~tmp___4~0#1); 52584#L1537-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 52520#L712 assume 1 == ~t6_pc~0; 52521#L713 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 52947#L723 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 52147#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 52148#L1545 assume !(0 != activate_threads_~tmp___5~0#1); 53063#L1545-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 53056#L731 assume 1 == ~t7_pc~0; 52006#L732 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 52007#L742 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 52203#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 53369#L1553 assume !(0 != activate_threads_~tmp___6~0#1); 53301#L1553-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 52110#L750 assume !(1 == ~t8_pc~0); 51802#L750-2 is_transmit8_triggered_~__retres1~8#1 := 0; 51801#L761 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 52308#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 53380#L1561 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 52451#L1561-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 52452#L769 assume 1 == ~t9_pc~0; 53008#L770 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 51968#L780 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 51969#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 52193#L1569 assume !(0 != activate_threads_~tmp___8~0#1); 53231#L1569-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 53324#L788 assume !(1 == ~t10_pc~0); 52864#L788-2 is_transmit10_triggered_~__retres1~10#1 := 0; 52865#L799 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 53464#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 53408#L1577 assume !(0 != activate_threads_~tmp___9~0#1); 52106#L1577-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 52107#L807 assume 1 == ~t11_pc~0; 53332#L808 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 52879#L818 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 53046#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 53545#L1585 assume !(0 != activate_threads_~tmp___10~0#1); 53674#L1585-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 53442#L826 assume !(1 == ~t12_pc~0); 52523#L826-2 is_transmit12_triggered_~__retres1~12#1 := 0; 52524#L837 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 51846#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 51847#L1593 assume !(0 != activate_threads_~tmp___11~0#1); 52681#L1593-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 52592#L1344 assume 1 == ~M_E~0;~M_E~0 := 2; 52593#L1344-2 assume !(1 == ~T1_E~0); 52724#L1349-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 52906#L1354-1 assume !(1 == ~T3_E~0); 52907#L1359-1 assume !(1 == ~T4_E~0); 53314#L1364-1 assume !(1 == ~T5_E~0); 52220#L1369-1 assume !(1 == ~T6_E~0); 52221#L1374-1 assume !(1 == ~T7_E~0); 52911#L1379-1 assume !(1 == ~T8_E~0); 52912#L1384-1 assume !(1 == ~T9_E~0); 52989#L1389-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 53483#L1394-1 assume !(1 == ~T11_E~0); 53484#L1399-1 assume !(1 == ~T12_E~0); 53593#L1404-1 assume !(1 == ~E_M~0); 52347#L1409-1 assume !(1 == ~E_1~0); 52348#L1414-1 assume !(1 == ~E_2~0); 53210#L1419-1 assume !(1 == ~E_3~0); 51981#L1424-1 assume !(1 == ~E_4~0); 51982#L1429-1 assume 1 == ~E_5~0;~E_5~0 := 2; 52922#L1434-1 assume !(1 == ~E_6~0); 53511#L1439-1 assume !(1 == ~E_7~0); 52025#L1444-1 assume !(1 == ~E_8~0); 52026#L1449-1 assume !(1 == ~E_9~0); 53165#L1454-1 assume !(1 == ~E_10~0); 53710#L1459-1 assume !(1 == ~E_11~0); 53708#L1464-1 assume !(1 == ~E_12~0); 53076#L1469-1 assume { :end_inline_reset_delta_events } true; 53077#L1815-2 [2022-12-13 13:22:11,198 INFO L750 eck$LassoCheckResult]: Loop: 53077#L1815-2 assume !false; 53232#L1816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 52881#L1181 assume !false; 53481#L1004 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 53482#L926 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 52493#L993 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 52494#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 53054#L1008 assume !(0 != eval_~tmp~0#1); 53055#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 52358#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 52359#L1206-3 assume 0 == ~M_E~0;~M_E~0 := 1; 53662#L1206-5 assume !(0 == ~T1_E~0); 53023#L1211-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 52094#L1216-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 52095#L1221-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 52703#L1226-3 assume !(0 == ~T5_E~0); 52164#L1231-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 52165#L1236-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 52495#L1241-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 53559#L1246-3 assume !(0 == ~T9_E~0); 53425#L1251-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 53138#L1256-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 52119#L1261-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 52120#L1266-3 assume !(0 == ~E_M~0); 52162#L1271-3 assume 0 == ~E_1~0;~E_1~0 := 1; 52163#L1276-3 assume 0 == ~E_2~0;~E_2~0 := 1; 52644#L1281-3 assume 0 == ~E_3~0;~E_3~0 := 1; 52645#L1286-3 assume 0 == ~E_4~0;~E_4~0 := 1; 53207#L1291-3 assume 0 == ~E_5~0;~E_5~0 := 1; 53208#L1296-3 assume 0 == ~E_6~0;~E_6~0 := 1; 53641#L1301-3 assume 0 == ~E_7~0;~E_7~0 := 1; 53589#L1306-3 assume !(0 == ~E_8~0); 52765#L1311-3 assume 0 == ~E_9~0;~E_9~0 := 1; 52040#L1316-3 assume 0 == ~E_10~0;~E_10~0 := 1; 52041#L1321-3 assume 0 == ~E_11~0;~E_11~0 := 1; 52116#L1326-3 assume 0 == ~E_12~0;~E_12~0 := 1; 52872#L1331-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 53217#L598-42 assume !(1 == ~m_pc~0); 53218#L598-44 is_master_triggered_~__retres1~0#1 := 0; 53348#L609-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 52525#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 52526#L1497-42 assume !(0 != activate_threads_~tmp~1#1); 53590#L1497-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 52927#L617-42 assume 1 == ~t1_pc~0; 52697#L618-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 52565#L628-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 52566#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 53587#L1505-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 52268#L1505-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 52269#L636-42 assume 1 == ~t2_pc~0; 53562#L637-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 52735#L647-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 52816#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 52817#L1513-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 53309#L1513-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 53163#L655-42 assume !(1 == ~t3_pc~0); 52710#L655-44 is_transmit3_triggered_~__retres1~3#1 := 0; 52711#L666-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 53243#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 53244#L1521-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 53461#L1521-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 53387#L674-42 assume !(1 == ~t4_pc~0); 53146#L674-44 is_transmit4_triggered_~__retres1~4#1 := 0; 53064#L685-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 53065#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 53281#L1529-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 52846#L1529-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 52847#L693-42 assume 1 == ~t5_pc~0; 53125#L694-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 53126#L704-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 52900#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 52901#L1537-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 53186#L1537-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 52466#L712-42 assume !(1 == ~t6_pc~0); 52467#L712-44 is_transmit6_triggered_~__retres1~6#1 := 0; 52783#L723-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 52108#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 52109#L1545-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 52574#L1545-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 52575#L731-42 assume 1 == ~t7_pc~0; 52436#L732-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 52261#L742-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 52923#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 52483#L1553-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 52484#L1553-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 52172#L750-42 assume 1 == ~t8_pc~0; 52173#L751-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 52752#L761-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 53071#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 52055#L1561-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 52056#L1561-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 52845#L769-42 assume 1 == ~t9_pc~0; 52668#L770-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 52669#L780-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 53392#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 53645#L1569-42 assume !(0 != activate_threads_~tmp___8~0#1); 52270#L1569-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 52271#L788-42 assume 1 == ~t10_pc~0; 52853#L789-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 53091#L799-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 53061#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 53062#L1577-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 53655#L1577-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 53623#L807-42 assume !(1 == ~t11_pc~0); 51889#L807-44 is_transmit11_triggered_~__retres1~11#1 := 0; 51890#L818-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 52756#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 52012#L1585-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 52013#L1585-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 52265#L826-42 assume 1 == ~t12_pc~0; 52266#L827-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 52472#L837-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 52866#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 52255#L1593-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 52256#L1593-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 53142#L1344-3 assume 1 == ~M_E~0;~M_E~0 := 2; 53143#L1344-5 assume !(1 == ~T1_E~0); 53066#L1349-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 52425#L1354-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 52426#L1359-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 53081#L1364-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 53628#L1369-3 assume !(1 == ~T6_E~0); 53510#L1374-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 52179#L1379-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 52180#L1384-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 52423#L1389-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 52424#L1394-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 52716#L1399-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 53516#L1404-3 assume 1 == ~E_M~0;~E_M~0 := 2; 53469#L1409-3 assume !(1 == ~E_1~0); 53470#L1414-3 assume 1 == ~E_2~0;~E_2~0 := 2; 53556#L1419-3 assume 1 == ~E_3~0;~E_3~0 := 2; 53288#L1424-3 assume 1 == ~E_4~0;~E_4~0 := 2; 52071#L1429-3 assume 1 == ~E_5~0;~E_5~0 := 2; 52072#L1434-3 assume 1 == ~E_6~0;~E_6~0 := 2; 53080#L1439-3 assume 1 == ~E_7~0;~E_7~0 := 2; 52018#L1444-3 assume 1 == ~E_8~0;~E_8~0 := 2; 52019#L1449-3 assume !(1 == ~E_9~0); 52124#L1454-3 assume 1 == ~E_10~0;~E_10~0 := 2; 53073#L1459-3 assume 1 == ~E_11~0;~E_11~0 := 2; 53074#L1464-3 assume 1 == ~E_12~0;~E_12~0 := 2; 53506#L1469-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 53507#L926-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 54713#L993-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 54712#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 54711#L1834 assume !(0 == start_simulation_~tmp~3#1); 53195#L1834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 53814#L926-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 53805#L993-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 51823#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 51824#L1789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 53700#L1796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 53698#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 53289#L1847 assume !(0 != start_simulation_~tmp___0~1#1); 53077#L1815-2 [2022-12-13 13:22:11,199 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 13:22:11,199 INFO L85 PathProgramCache]: Analyzing trace with hash 1144190578, now seen corresponding path program 1 times [2022-12-13 13:22:11,199 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 13:22:11,199 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [365243894] [2022-12-13 13:22:11,199 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 13:22:11,199 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 13:22:11,208 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 13:22:11,244 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 13:22:11,245 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 13:22:11,245 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [365243894] [2022-12-13 13:22:11,245 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [365243894] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 13:22:11,245 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 13:22:11,245 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 13:22:11,245 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1231322656] [2022-12-13 13:22:11,245 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 13:22:11,246 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 13:22:11,246 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 13:22:11,246 INFO L85 PathProgramCache]: Analyzing trace with hash -1855769514, now seen corresponding path program 1 times [2022-12-13 13:22:11,246 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 13:22:11,246 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1263151915] [2022-12-13 13:22:11,247 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 13:22:11,247 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 13:22:11,257 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 13:22:11,281 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 13:22:11,281 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 13:22:11,281 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1263151915] [2022-12-13 13:22:11,281 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1263151915] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 13:22:11,281 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 13:22:11,281 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 13:22:11,282 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1721016861] [2022-12-13 13:22:11,282 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 13:22:11,282 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 13:22:11,282 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 13:22:11,283 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 13:22:11,283 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 13:22:11,283 INFO L87 Difference]: Start difference. First operand 3324 states and 4886 transitions. cyclomatic complexity: 1564 Second operand has 4 states, 4 states have (on average 37.5) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 13:22:11,461 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 13:22:11,461 INFO L93 Difference]: Finished difference Result 6182 states and 9069 transitions. [2022-12-13 13:22:11,461 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6182 states and 9069 transitions. [2022-12-13 13:22:11,481 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 5965 [2022-12-13 13:22:11,493 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6182 states to 6182 states and 9069 transitions. [2022-12-13 13:22:11,494 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6182 [2022-12-13 13:22:11,497 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6182 [2022-12-13 13:22:11,497 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6182 states and 9069 transitions. [2022-12-13 13:22:11,501 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 13:22:11,501 INFO L218 hiAutomatonCegarLoop]: Abstraction has 6182 states and 9069 transitions. [2022-12-13 13:22:11,506 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6182 states and 9069 transitions. [2022-12-13 13:22:11,576 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6182 to 6180. [2022-12-13 13:22:11,581 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6180 states, 6180 states have (on average 1.4671521035598705) internal successors, (9067), 6179 states have internal predecessors, (9067), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 13:22:11,590 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6180 states to 6180 states and 9067 transitions. [2022-12-13 13:22:11,590 INFO L240 hiAutomatonCegarLoop]: Abstraction has 6180 states and 9067 transitions. [2022-12-13 13:22:11,590 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 13:22:11,591 INFO L428 stractBuchiCegarLoop]: Abstraction has 6180 states and 9067 transitions. [2022-12-13 13:22:11,591 INFO L335 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2022-12-13 13:22:11,591 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6180 states and 9067 transitions. [2022-12-13 13:22:11,604 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 5965 [2022-12-13 13:22:11,604 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 13:22:11,604 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 13:22:11,606 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 13:22:11,606 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 13:22:11,606 INFO L748 eck$LassoCheckResult]: Stem: 61533#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 61534#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 62464#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 62465#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 62954#L853 assume 1 == ~m_i~0;~m_st~0 := 0; 62804#L853-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 61816#L858-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 61287#L863-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 61288#L868-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 62563#L873-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 62707#L878-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 63146#L883-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 63147#L888-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 62035#L893-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 62036#L898-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 62592#L903-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 62512#L908-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 62513#L913-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 62669#L1206 assume !(0 == ~M_E~0); 62018#L1206-2 assume !(0 == ~T1_E~0); 62019#L1211-1 assume !(0 == ~T2_E~0); 62947#L1216-1 assume !(0 == ~T3_E~0); 61793#L1221-1 assume !(0 == ~T4_E~0); 61794#L1226-1 assume !(0 == ~T5_E~0); 61464#L1231-1 assume !(0 == ~T6_E~0); 61465#L1236-1 assume !(0 == ~T7_E~0); 62991#L1241-1 assume !(0 == ~T8_E~0); 61864#L1246-1 assume !(0 == ~T9_E~0); 61865#L1251-1 assume !(0 == ~T10_E~0); 62090#L1256-1 assume !(0 == ~T11_E~0); 61297#L1261-1 assume !(0 == ~T12_E~0); 61298#L1266-1 assume !(0 == ~E_M~0); 63125#L1271-1 assume !(0 == ~E_1~0); 62697#L1276-1 assume !(0 == ~E_2~0); 62698#L1281-1 assume !(0 == ~E_3~0); 62622#L1286-1 assume !(0 == ~E_4~0); 61695#L1291-1 assume !(0 == ~E_5~0); 61696#L1296-1 assume !(0 == ~E_6~0); 62418#L1301-1 assume !(0 == ~E_7~0); 62419#L1306-1 assume !(0 == ~E_8~0); 62872#L1311-1 assume !(0 == ~E_9~0); 61655#L1316-1 assume !(0 == ~E_10~0); 61656#L1321-1 assume !(0 == ~E_11~0); 62433#L1326-1 assume 0 == ~E_12~0;~E_12~0 := 1; 61521#L1331-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 61522#L598 assume 1 == ~m_pc~0; 61570#L599 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 61571#L609 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 62314#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 62315#L1497 assume !(0 != activate_threads_~tmp~1#1); 63081#L1497-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 63019#L617 assume !(1 == ~t1_pc~0); 61886#L617-2 is_transmit1_triggered_~__retres1~1#1 := 0; 61887#L628 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 62781#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 62782#L1505 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 62529#L1505-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 62530#L636 assume 1 == ~t2_pc~0; 61855#L637 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 61856#L647 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 61677#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 61678#L1513 assume !(0 != activate_threads_~tmp___1~0#1); 62562#L1513-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 62210#L655 assume !(1 == ~t3_pc~0); 62211#L655-2 is_transmit3_triggered_~__retres1~3#1 := 0; 62975#L666 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 62770#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 62771#L1521 assume !(0 != activate_threads_~tmp___2~0#1); 63126#L1521-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 63127#L674 assume 1 == ~t4_pc~0; 61384#L675 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 61385#L685 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 61409#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 61410#L1529 assume !(0 != activate_threads_~tmp___3~0#1); 61679#L1529-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 62209#L693 assume !(1 == ~t5_pc~0); 62367#L693-2 is_transmit5_triggered_~__retres1~5#1 := 0; 62020#L704 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 62021#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 62874#L1537 assume !(0 != activate_threads_~tmp___4~0#1); 62103#L1537-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 62039#L712 assume 1 == ~t6_pc~0; 62040#L713 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 62469#L723 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 61665#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 61666#L1545 assume !(0 != activate_threads_~tmp___5~0#1); 62579#L1545-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 62572#L731 assume 1 == ~t7_pc~0; 61523#L732 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 61524#L742 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 61721#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 62878#L1553 assume !(0 != activate_threads_~tmp___6~0#1); 62814#L1553-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 61628#L750 assume !(1 == ~t8_pc~0); 61318#L750-2 is_transmit8_triggered_~__retres1~8#1 := 0; 61317#L761 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 61827#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 62890#L1561 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 61971#L1561-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 61972#L769 assume 1 == ~t9_pc~0; 62525#L770 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 61484#L780 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 61485#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 61711#L1569 assume !(0 != activate_threads_~tmp___8~0#1); 62746#L1569-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 62835#L788 assume !(1 == ~t10_pc~0); 62384#L788-2 is_transmit10_triggered_~__retres1~10#1 := 0; 62385#L799 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 62976#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 62916#L1577 assume !(0 != activate_threads_~tmp___9~0#1); 61624#L1577-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 61625#L807 assume 1 == ~t11_pc~0; 62841#L808 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 62399#L818 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 62564#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 63040#L1585 assume !(0 != activate_threads_~tmp___10~0#1); 63174#L1585-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 62957#L826 assume !(1 == ~t12_pc~0); 62042#L826-2 is_transmit12_triggered_~__retres1~12#1 := 0; 62043#L837 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 61362#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 61363#L1593 assume !(0 != activate_threads_~tmp___11~0#1); 62203#L1593-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 62113#L1344 assume 1 == ~M_E~0;~M_E~0 := 2; 62114#L1344-2 assume !(1 == ~T1_E~0); 62246#L1349-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 62424#L1354-1 assume !(1 == ~T3_E~0); 62425#L1359-1 assume !(1 == ~T4_E~0); 62827#L1364-1 assume !(1 == ~T5_E~0); 61738#L1369-1 assume !(1 == ~T6_E~0); 61739#L1374-1 assume !(1 == ~T7_E~0); 62431#L1379-1 assume !(1 == ~T8_E~0); 62432#L1384-1 assume !(1 == ~T9_E~0); 62511#L1389-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 63473#L1394-1 assume !(1 == ~T11_E~0); 63160#L1399-1 assume !(1 == ~T12_E~0); 63161#L1404-1 assume !(1 == ~E_M~0); 63410#L1409-1 assume !(1 == ~E_1~0); 63408#L1414-1 assume !(1 == ~E_2~0); 62723#L1419-1 assume !(1 == ~E_3~0); 62724#L1424-1 assume !(1 == ~E_4~0); 63354#L1429-1 assume 1 == ~E_5~0;~E_5~0 := 2; 63352#L1434-1 assume !(1 == ~E_6~0); 63335#L1439-1 assume !(1 == ~E_7~0); 63331#L1444-1 assume !(1 == ~E_8~0); 63329#L1449-1 assume !(1 == ~E_9~0); 63327#L1454-1 assume !(1 == ~E_10~0); 63312#L1459-1 assume !(1 == ~E_11~0); 63231#L1464-1 assume !(1 == ~E_12~0); 63217#L1469-1 assume { :end_inline_reset_delta_events } true; 63209#L1815-2 [2022-12-13 13:22:11,606 INFO L750 eck$LassoCheckResult]: Loop: 63209#L1815-2 assume !false; 63203#L1816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 63198#L1181 assume !false; 63197#L1004 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 63194#L926 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 63183#L993 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 63182#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 63180#L1008 assume !(0 != eval_~tmp~0#1); 63179#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 63178#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 63176#L1206-3 assume 0 == ~M_E~0;~M_E~0 := 1; 63177#L1206-5 assume !(0 == ~T1_E~0); 64522#L1211-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 64521#L1216-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 64520#L1221-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 64519#L1226-3 assume !(0 == ~T5_E~0); 64518#L1231-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 64517#L1236-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 64516#L1241-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 64515#L1246-3 assume !(0 == ~T9_E~0); 64514#L1251-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 64513#L1256-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 64512#L1261-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 64511#L1266-3 assume !(0 == ~E_M~0); 64510#L1271-3 assume 0 == ~E_1~0;~E_1~0 := 1; 64508#L1276-3 assume 0 == ~E_2~0;~E_2~0 := 1; 64509#L1281-3 assume 0 == ~E_3~0;~E_3~0 := 1; 64737#L1286-3 assume !(0 == ~E_4~0); 64718#L1291-3 assume 0 == ~E_5~0;~E_5~0 := 1; 64703#L1296-3 assume 0 == ~E_6~0;~E_6~0 := 1; 64690#L1301-3 assume 0 == ~E_7~0;~E_7~0 := 1; 64687#L1306-3 assume !(0 == ~E_8~0); 64685#L1311-3 assume 0 == ~E_9~0;~E_9~0 := 1; 64666#L1316-3 assume 0 == ~E_10~0;~E_10~0 := 1; 64648#L1321-3 assume 0 == ~E_11~0;~E_11~0 := 1; 64643#L1326-3 assume 0 == ~E_12~0;~E_12~0 := 1; 64486#L1331-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 64487#L598-42 assume 1 == ~m_pc~0; 64630#L599-14 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 64628#L609-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 64627#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 64625#L1497-42 assume !(0 != activate_threads_~tmp~1#1); 64623#L1497-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 64621#L617-42 assume 1 == ~t1_pc~0; 64618#L618-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 64617#L628-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 64616#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 64597#L1505-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 64595#L1505-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 64592#L636-42 assume 1 == ~t2_pc~0; 64589#L637-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 64588#L647-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 64585#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 64549#L1513-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 64419#L1513-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 64417#L655-42 assume 1 == ~t3_pc~0; 64414#L656-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 64382#L666-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 64358#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 64331#L1521-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 64329#L1521-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 64327#L674-42 assume !(1 == ~t4_pc~0); 64323#L674-44 is_transmit4_triggered_~__retres1~4#1 := 0; 64320#L685-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 64318#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 64315#L1529-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 64313#L1529-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 64277#L693-42 assume 1 == ~t5_pc~0; 64264#L694-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 64262#L704-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 64259#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 64227#L1537-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 64224#L1537-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 64222#L712-42 assume !(1 == ~t6_pc~0); 64188#L712-44 is_transmit6_triggered_~__retres1~6#1 := 0; 64186#L723-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 64159#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 64157#L1545-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 64155#L1545-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 64154#L731-42 assume 1 == ~t7_pc~0; 64123#L732-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 64097#L742-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 64067#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 64033#L1553-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 64031#L1553-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 64030#L750-42 assume !(1 == ~t8_pc~0); 64026#L750-44 is_transmit8_triggered_~__retres1~8#1 := 0; 64023#L761-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 64021#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 64019#L1561-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 63978#L1561-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 62364#L769-42 assume !(1 == ~t9_pc~0); 62192#L769-44 is_transmit9_triggered_~__retres1~9#1 := 0; 62191#L780-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 62903#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 63138#L1569-42 assume !(0 != activate_threads_~tmp___8~0#1); 61789#L1569-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 61790#L788-42 assume 1 == ~t10_pc~0; 62372#L789-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 62607#L799-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 62577#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 62578#L1577-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 63152#L1577-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 63118#L807-42 assume 1 == ~t11_pc~0; 62742#L808-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 61406#L818-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 62279#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 61529#L1585-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 61530#L1585-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 63681#L826-42 assume 1 == ~t12_pc~0; 63580#L827-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 63578#L837-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 63576#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 63574#L1593-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 63098#L1593-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 62658#L1344-3 assume 1 == ~M_E~0;~M_E~0 := 2; 62659#L1344-5 assume !(1 == ~T1_E~0); 62582#L1349-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 62583#L1354-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 63504#L1359-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 63502#L1364-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 63500#L1369-3 assume !(1 == ~T6_E~0); 63458#L1374-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 63427#L1379-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 63425#L1384-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 62939#L1389-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 63368#L1394-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 63366#L1399-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 63348#L1404-3 assume 1 == ~E_M~0;~E_M~0 := 2; 63346#L1409-3 assume !(1 == ~E_1~0); 63344#L1414-3 assume 1 == ~E_2~0;~E_2~0 := 2; 63324#L1419-3 assume 1 == ~E_3~0;~E_3~0 := 2; 63308#L1424-3 assume 1 == ~E_4~0;~E_4~0 := 2; 63305#L1429-3 assume 1 == ~E_5~0;~E_5~0 := 2; 63303#L1434-3 assume 1 == ~E_6~0;~E_6~0 := 2; 63301#L1439-3 assume 1 == ~E_7~0;~E_7~0 := 2; 63299#L1444-3 assume 1 == ~E_8~0;~E_8~0 := 2; 63297#L1449-3 assume !(1 == ~E_9~0); 63294#L1454-3 assume 1 == ~E_10~0;~E_10~0 := 2; 63292#L1459-3 assume 1 == ~E_11~0;~E_11~0 := 2; 63290#L1464-3 assume 1 == ~E_12~0;~E_12~0 := 2; 63288#L1469-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 63285#L926-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 63272#L993-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 63269#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 63267#L1834 assume !(0 == start_simulation_~tmp~3#1); 62708#L1834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 63261#L926-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 63251#L993-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 63249#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 63246#L1789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 63244#L1796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 63227#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 63216#L1847 assume !(0 != start_simulation_~tmp___0~1#1); 63209#L1815-2 [2022-12-13 13:22:11,606 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 13:22:11,607 INFO L85 PathProgramCache]: Analyzing trace with hash -1221844492, now seen corresponding path program 1 times [2022-12-13 13:22:11,607 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 13:22:11,607 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [481592656] [2022-12-13 13:22:11,607 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 13:22:11,607 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 13:22:11,614 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 13:22:11,651 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 13:22:11,651 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 13:22:11,652 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [481592656] [2022-12-13 13:22:11,652 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [481592656] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 13:22:11,652 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 13:22:11,652 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 13:22:11,652 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2077267944] [2022-12-13 13:22:11,652 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 13:22:11,653 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 13:22:11,653 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 13:22:11,653 INFO L85 PathProgramCache]: Analyzing trace with hash -76789161, now seen corresponding path program 1 times [2022-12-13 13:22:11,653 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 13:22:11,653 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1273348971] [2022-12-13 13:22:11,653 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 13:22:11,654 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 13:22:11,665 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 13:22:11,703 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 13:22:11,703 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 13:22:11,703 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1273348971] [2022-12-13 13:22:11,703 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1273348971] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 13:22:11,703 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 13:22:11,703 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 13:22:11,704 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1547530503] [2022-12-13 13:22:11,704 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 13:22:11,704 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 13:22:11,704 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 13:22:11,704 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 13:22:11,705 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 13:22:11,705 INFO L87 Difference]: Start difference. First operand 6180 states and 9067 transitions. cyclomatic complexity: 2891 Second operand has 4 states, 4 states have (on average 37.5) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 13:22:11,855 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 13:22:11,855 INFO L93 Difference]: Finished difference Result 11670 states and 17086 transitions. [2022-12-13 13:22:11,855 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 11670 states and 17086 transitions. [2022-12-13 13:22:11,890 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 11439 [2022-12-13 13:22:11,915 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 11670 states to 11670 states and 17086 transitions. [2022-12-13 13:22:11,915 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 11670 [2022-12-13 13:22:11,922 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11670 [2022-12-13 13:22:11,922 INFO L73 IsDeterministic]: Start isDeterministic. Operand 11670 states and 17086 transitions. [2022-12-13 13:22:11,929 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 13:22:11,929 INFO L218 hiAutomatonCegarLoop]: Abstraction has 11670 states and 17086 transitions. [2022-12-13 13:22:11,938 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11670 states and 17086 transitions. [2022-12-13 13:22:12,041 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11670 to 11666. [2022-12-13 13:22:12,052 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 11666 states, 11666 states have (on average 1.4642551002914452) internal successors, (17082), 11665 states have internal predecessors, (17082), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 13:22:12,066 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11666 states to 11666 states and 17082 transitions. [2022-12-13 13:22:12,067 INFO L240 hiAutomatonCegarLoop]: Abstraction has 11666 states and 17082 transitions. [2022-12-13 13:22:12,067 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 13:22:12,068 INFO L428 stractBuchiCegarLoop]: Abstraction has 11666 states and 17082 transitions. [2022-12-13 13:22:12,068 INFO L335 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2022-12-13 13:22:12,068 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 11666 states and 17082 transitions. [2022-12-13 13:22:12,091 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 11439 [2022-12-13 13:22:12,091 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 13:22:12,091 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 13:22:12,092 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 13:22:12,092 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 13:22:12,092 INFO L748 eck$LassoCheckResult]: Stem: 79392#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 79393#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 80327#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 80328#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 80797#L853 assume 1 == ~m_i~0;~m_st~0 := 0; 80659#L853-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 79675#L858-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 79147#L863-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 79148#L868-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 80426#L873-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 80567#L878-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 80972#L883-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 80973#L888-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 79898#L893-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 79899#L898-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 80455#L903-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 80374#L908-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 80375#L913-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 80530#L1206 assume !(0 == ~M_E~0); 79881#L1206-2 assume !(0 == ~T1_E~0); 79882#L1211-1 assume !(0 == ~T2_E~0); 80790#L1216-1 assume !(0 == ~T3_E~0); 79651#L1221-1 assume !(0 == ~T4_E~0); 79652#L1226-1 assume !(0 == ~T5_E~0); 79323#L1231-1 assume !(0 == ~T6_E~0); 79324#L1236-1 assume !(0 == ~T7_E~0); 80835#L1241-1 assume !(0 == ~T8_E~0); 79723#L1246-1 assume !(0 == ~T9_E~0); 79724#L1251-1 assume !(0 == ~T10_E~0); 79950#L1256-1 assume !(0 == ~T11_E~0); 79157#L1261-1 assume !(0 == ~T12_E~0); 79158#L1266-1 assume !(0 == ~E_M~0); 80958#L1271-1 assume !(0 == ~E_1~0); 80557#L1276-1 assume !(0 == ~E_2~0); 80558#L1281-1 assume !(0 == ~E_3~0); 80484#L1286-1 assume !(0 == ~E_4~0); 79554#L1291-1 assume !(0 == ~E_5~0); 79555#L1296-1 assume !(0 == ~E_6~0); 80283#L1301-1 assume !(0 == ~E_7~0); 80284#L1306-1 assume !(0 == ~E_8~0); 80725#L1311-1 assume !(0 == ~E_9~0); 79514#L1316-1 assume !(0 == ~E_10~0); 79515#L1321-1 assume !(0 == ~E_11~0); 80298#L1326-1 assume !(0 == ~E_12~0); 79380#L1331-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 79381#L598 assume 1 == ~m_pc~0; 79429#L599 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 79430#L609 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 80179#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 80180#L1497 assume !(0 != activate_threads_~tmp~1#1); 80917#L1497-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 80862#L617 assume !(1 == ~t1_pc~0); 79745#L617-2 is_transmit1_triggered_~__retres1~1#1 := 0; 79746#L628 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 80638#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 80639#L1505 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 80391#L1505-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 80392#L636 assume 1 == ~t2_pc~0; 79713#L637 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 79714#L647 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 79536#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 79537#L1513 assume !(0 != activate_threads_~tmp___1~0#1); 80425#L1513-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 80070#L655 assume !(1 == ~t3_pc~0); 80071#L655-2 is_transmit3_triggered_~__retres1~3#1 := 0; 80818#L666 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 80627#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 80628#L1521 assume !(0 != activate_threads_~tmp___2~0#1); 80959#L1521-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 80960#L674 assume 1 == ~t4_pc~0; 79244#L675 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 79245#L685 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 79269#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 79270#L1529 assume !(0 != activate_threads_~tmp___3~0#1); 79538#L1529-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 80069#L693 assume !(1 == ~t5_pc~0); 80233#L693-2 is_transmit5_triggered_~__retres1~5#1 := 0; 79883#L704 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 79884#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 80728#L1537 assume !(0 != activate_threads_~tmp___4~0#1); 79963#L1537-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 79902#L712 assume 1 == ~t6_pc~0; 79903#L713 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 80332#L723 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 79524#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 79525#L1545 assume !(0 != activate_threads_~tmp___5~0#1); 80442#L1545-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 80435#L731 assume 1 == ~t7_pc~0; 79382#L732 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 79383#L742 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 79580#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 80731#L1553 assume !(0 != activate_threads_~tmp___6~0#1); 80669#L1553-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 79487#L750 assume !(1 == ~t8_pc~0); 79178#L750-2 is_transmit8_triggered_~__retres1~8#1 := 0; 79177#L761 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 79686#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 80741#L1561 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 79833#L1561-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 79834#L769 assume 1 == ~t9_pc~0; 80387#L770 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 79343#L780 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 79344#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 79570#L1569 assume !(0 != activate_threads_~tmp___8~0#1); 80604#L1569-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 80690#L788 assume !(1 == ~t10_pc~0); 80249#L788-2 is_transmit10_triggered_~__retres1~10#1 := 0; 80250#L799 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 80819#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 80766#L1577 assume !(0 != activate_threads_~tmp___9~0#1); 79483#L1577-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 79484#L807 assume 1 == ~t11_pc~0; 80696#L808 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 80264#L818 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 80427#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 80883#L1585 assume !(0 != activate_threads_~tmp___10~0#1); 80995#L1585-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 80800#L826 assume !(1 == ~t12_pc~0); 79905#L826-2 is_transmit12_triggered_~__retres1~12#1 := 0; 79906#L837 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 79222#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 79223#L1593 assume !(0 != activate_threads_~tmp___11~0#1); 80063#L1593-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 79973#L1344 assume 1 == ~M_E~0;~M_E~0 := 2; 79974#L1344-2 assume !(1 == ~T1_E~0); 81927#L1349-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 81926#L1354-1 assume !(1 == ~T3_E~0); 81925#L1359-1 assume !(1 == ~T4_E~0); 81924#L1364-1 assume !(1 == ~T5_E~0); 81923#L1369-1 assume !(1 == ~T6_E~0); 81922#L1374-1 assume !(1 == ~T7_E~0); 81919#L1379-1 assume !(1 == ~T8_E~0); 80372#L1384-1 assume !(1 == ~T9_E~0); 80373#L1389-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 81160#L1394-1 assume !(1 == ~T11_E~0); 81158#L1399-1 assume !(1 == ~T12_E~0); 81156#L1404-1 assume !(1 == ~E_M~0); 81154#L1409-1 assume !(1 == ~E_1~0); 81151#L1414-1 assume !(1 == ~E_2~0); 81149#L1419-1 assume !(1 == ~E_3~0); 81147#L1424-1 assume !(1 == ~E_4~0); 81145#L1429-1 assume 1 == ~E_5~0;~E_5~0 := 2; 81143#L1434-1 assume !(1 == ~E_6~0); 81142#L1439-1 assume !(1 == ~E_7~0); 81109#L1444-1 assume !(1 == ~E_8~0); 81095#L1449-1 assume !(1 == ~E_9~0); 81093#L1454-1 assume !(1 == ~E_10~0); 81070#L1459-1 assume !(1 == ~E_11~0); 81050#L1464-1 assume !(1 == ~E_12~0); 81036#L1469-1 assume { :end_inline_reset_delta_events } true; 81028#L1815-2 [2022-12-13 13:22:12,093 INFO L750 eck$LassoCheckResult]: Loop: 81028#L1815-2 assume !false; 81022#L1816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 81017#L1181 assume !false; 81016#L1004 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 81013#L926 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 81002#L993 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 81001#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 80999#L1008 assume !(0 != eval_~tmp~0#1); 80998#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 80997#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 80996#L1206-3 assume 0 == ~M_E~0;~M_E~0 := 1; 80983#L1206-5 assume !(0 == ~T1_E~0); 80402#L1211-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 80403#L1216-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 80087#L1221-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 80088#L1226-3 assume !(0 == ~T5_E~0); 79541#L1231-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 79542#L1236-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 79877#L1241-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 80893#L1246-3 assume !(0 == ~T9_E~0); 80781#L1251-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 80517#L1256-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 79493#L1261-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 79494#L1266-3 assume !(0 == ~E_M~0); 79539#L1271-3 assume 0 == ~E_1~0;~E_1~0 := 1; 79540#L1276-3 assume 0 == ~E_2~0;~E_2~0 := 1; 80026#L1281-3 assume 0 == ~E_3~0;~E_3~0 := 1; 80027#L1286-3 assume !(0 == ~E_4~0); 80580#L1291-3 assume 0 == ~E_5~0;~E_5~0 := 1; 80581#L1296-3 assume 0 == ~E_6~0;~E_6~0 := 1; 80965#L1301-3 assume 0 == ~E_7~0;~E_7~0 := 1; 80922#L1306-3 assume !(0 == ~E_8~0); 80153#L1311-3 assume 0 == ~E_9~0;~E_9~0 := 1; 79417#L1316-3 assume 0 == ~E_10~0;~E_10~0 := 1; 79418#L1321-3 assume 0 == ~E_11~0;~E_11~0 := 1; 79495#L1326-3 assume !(0 == ~E_12~0); 80258#L1331-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 80591#L598-42 assume 1 == ~m_pc~0; 80593#L599-14 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 80711#L609-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 79907#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 79908#L1497-42 assume !(0 != activate_threads_~tmp~1#1); 80923#L1497-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 80312#L617-42 assume 1 == ~t1_pc~0; 80081#L618-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 79946#L628-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 79947#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 80920#L1505-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 79645#L1505-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 79646#L636-42 assume 1 == ~t2_pc~0; 80898#L637-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 80121#L647-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 80201#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 80202#L1513-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 80677#L1513-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 80540#L655-42 assume !(1 == ~t3_pc~0); 80096#L655-44 is_transmit3_triggered_~__retres1~3#1 := 0; 80097#L666-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 80618#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 80619#L1521-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 80817#L1521-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 80748#L674-42 assume !(1 == ~t4_pc~0); 80525#L674-44 is_transmit4_triggered_~__retres1~4#1 := 0; 80443#L685-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 80444#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 80650#L1529-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 80231#L1529-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 80232#L693-42 assume 1 == ~t5_pc~0; 80505#L694-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 80506#L704-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 80285#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 80286#L1537-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 80561#L1537-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 79849#L712-42 assume 1 == ~t6_pc~0; 79851#L713-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 80171#L723-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 79485#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 79486#L1545-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 79955#L1545-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 79956#L731-42 assume !(1 == ~t7_pc~0); 79637#L731-44 is_transmit7_triggered_~__retres1~7#1 := 0; 79638#L742-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 80308#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 79866#L1553-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 79867#L1553-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 79549#L750-42 assume !(1 == ~t8_pc~0); 79551#L750-44 is_transmit8_triggered_~__retres1~8#1 := 0; 80140#L761-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 80451#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 79432#L1561-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 79433#L1561-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 80230#L769-42 assume 1 == ~t9_pc~0; 80050#L770-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 80051#L780-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 80753#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 80968#L1569-42 assume !(0 != activate_threads_~tmp___8~0#1); 79647#L1569-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 79648#L788-42 assume !(1 == ~t10_pc~0); 80239#L788-44 is_transmit10_triggered_~__retres1~10#1 := 0; 80470#L799-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 80440#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 80441#L1577-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 80977#L1577-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 80950#L807-42 assume !(1 == ~t11_pc~0); 79265#L807-44 is_transmit11_triggered_~__retres1~11#1 := 0; 79266#L818-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 80144#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 79388#L1585-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 79389#L1585-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 79642#L826-42 assume 1 == ~t12_pc~0; 79643#L827-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 79855#L837-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 80254#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 79632#L1593-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 79633#L1593-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 80521#L1344-3 assume 1 == ~M_E~0;~M_E~0 := 2; 80522#L1344-5 assume !(1 == ~T1_E~0); 80445#L1349-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 80446#L1354-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 82540#L1359-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 82533#L1364-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 82526#L1369-3 assume !(1 == ~T6_E~0); 82519#L1374-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 82512#L1379-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 82505#L1384-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 80787#L1389-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 82493#L1394-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 82489#L1399-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 82485#L1404-3 assume 1 == ~E_M~0;~E_M~0 := 2; 82481#L1409-3 assume !(1 == ~E_1~0); 82477#L1414-3 assume 1 == ~E_2~0;~E_2~0 := 2; 82473#L1419-3 assume 1 == ~E_3~0;~E_3~0 := 2; 82469#L1424-3 assume 1 == ~E_4~0;~E_4~0 := 2; 82463#L1429-3 assume 1 == ~E_5~0;~E_5~0 := 2; 82461#L1434-3 assume 1 == ~E_6~0;~E_6~0 := 2; 82459#L1439-3 assume 1 == ~E_7~0;~E_7~0 := 2; 82457#L1444-3 assume 1 == ~E_8~0;~E_8~0 := 2; 82455#L1449-3 assume !(1 == ~E_9~0); 82452#L1454-3 assume 1 == ~E_10~0;~E_10~0 := 2; 82448#L1459-3 assume 1 == ~E_11~0;~E_11~0 := 2; 82445#L1464-3 assume 1 == ~E_12~0;~E_12~0 := 2; 82442#L1469-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 82439#L926-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 82426#L993-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 82424#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 81141#L1834 assume !(0 == start_simulation_~tmp~3#1); 80568#L1834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 81104#L926-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 81094#L993-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 81092#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 81090#L1789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 81068#L1796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 81047#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 81035#L1847 assume !(0 != start_simulation_~tmp___0~1#1); 81028#L1815-2 [2022-12-13 13:22:12,093 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 13:22:12,093 INFO L85 PathProgramCache]: Analyzing trace with hash 931262326, now seen corresponding path program 1 times [2022-12-13 13:22:12,093 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 13:22:12,093 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1470284823] [2022-12-13 13:22:12,093 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 13:22:12,093 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 13:22:12,101 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 13:22:12,133 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 13:22:12,133 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 13:22:12,134 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1470284823] [2022-12-13 13:22:12,134 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1470284823] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 13:22:12,134 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 13:22:12,134 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-12-13 13:22:12,134 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [591442343] [2022-12-13 13:22:12,134 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 13:22:12,135 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 13:22:12,135 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 13:22:12,135 INFO L85 PathProgramCache]: Analyzing trace with hash 1364009563, now seen corresponding path program 1 times [2022-12-13 13:22:12,135 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 13:22:12,135 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1819617384] [2022-12-13 13:22:12,135 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 13:22:12,136 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 13:22:12,147 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 13:22:12,186 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 13:22:12,186 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 13:22:12,186 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1819617384] [2022-12-13 13:22:12,186 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1819617384] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 13:22:12,186 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 13:22:12,186 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 13:22:12,187 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1795026366] [2022-12-13 13:22:12,187 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 13:22:12,187 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 13:22:12,187 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 13:22:12,187 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 13:22:12,188 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 13:22:12,188 INFO L87 Difference]: Start difference. First operand 11666 states and 17082 transitions. cyclomatic complexity: 5424 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 2 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 13:22:12,408 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 13:22:12,408 INFO L93 Difference]: Finished difference Result 22935 states and 33364 transitions. [2022-12-13 13:22:12,408 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 22935 states and 33364 transitions. [2022-12-13 13:22:12,489 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 22701 [2022-12-13 13:22:12,533 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 22935 states to 22935 states and 33364 transitions. [2022-12-13 13:22:12,533 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 22935 [2022-12-13 13:22:12,543 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 22935 [2022-12-13 13:22:12,543 INFO L73 IsDeterministic]: Start isDeterministic. Operand 22935 states and 33364 transitions. [2022-12-13 13:22:12,553 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 13:22:12,553 INFO L218 hiAutomatonCegarLoop]: Abstraction has 22935 states and 33364 transitions. [2022-12-13 13:22:12,600 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 22935 states and 33364 transitions. [2022-12-13 13:22:12,881 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 22935 to 22215. [2022-12-13 13:22:12,905 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 22215 states, 22215 states have (on average 1.456133243304074) internal successors, (32348), 22214 states have internal predecessors, (32348), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 13:22:12,954 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22215 states to 22215 states and 32348 transitions. [2022-12-13 13:22:12,954 INFO L240 hiAutomatonCegarLoop]: Abstraction has 22215 states and 32348 transitions. [2022-12-13 13:22:12,954 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 13:22:12,955 INFO L428 stractBuchiCegarLoop]: Abstraction has 22215 states and 32348 transitions. [2022-12-13 13:22:12,955 INFO L335 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2022-12-13 13:22:12,955 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 22215 states and 32348 transitions. [2022-12-13 13:22:13,029 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 21981 [2022-12-13 13:22:13,029 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 13:22:13,029 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 13:22:13,031 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 13:22:13,031 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 13:22:13,031 INFO L748 eck$LassoCheckResult]: Stem: 114001#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 114002#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 114958#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 114959#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 115529#L853 assume 1 == ~m_i~0;~m_st~0 := 0; 115350#L853-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 114282#L858-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 113755#L863-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 113756#L868-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 115072#L873-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 115235#L878-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 115805#L883-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 115806#L888-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 114509#L893-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 114510#L898-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 115106#L903-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 115013#L908-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 115014#L913-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 115194#L1206 assume !(0 == ~M_E~0); 114488#L1206-2 assume !(0 == ~T1_E~0); 114489#L1211-1 assume !(0 == ~T2_E~0); 115523#L1216-1 assume !(0 == ~T3_E~0); 114259#L1221-1 assume !(0 == ~T4_E~0); 114260#L1226-1 assume !(0 == ~T5_E~0); 113934#L1231-1 assume !(0 == ~T6_E~0); 113935#L1236-1 assume !(0 == ~T7_E~0); 115573#L1241-1 assume !(0 == ~T8_E~0); 114330#L1246-1 assume !(0 == ~T9_E~0); 114331#L1251-1 assume !(0 == ~T10_E~0); 114560#L1256-1 assume !(0 == ~T11_E~0); 113765#L1261-1 assume !(0 == ~T12_E~0); 113766#L1266-1 assume !(0 == ~E_M~0); 115780#L1271-1 assume !(0 == ~E_1~0); 115225#L1276-1 assume !(0 == ~E_2~0); 115226#L1281-1 assume !(0 == ~E_3~0); 115144#L1286-1 assume !(0 == ~E_4~0); 114161#L1291-1 assume !(0 == ~E_5~0); 114162#L1296-1 assume !(0 == ~E_6~0); 114909#L1301-1 assume !(0 == ~E_7~0); 114910#L1306-1 assume !(0 == ~E_8~0); 115443#L1311-1 assume !(0 == ~E_9~0); 114122#L1316-1 assume !(0 == ~E_10~0); 114123#L1321-1 assume !(0 == ~E_11~0); 114926#L1326-1 assume !(0 == ~E_12~0); 113989#L1331-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 113990#L598 assume !(1 == ~m_pc~0); 114710#L598-2 is_master_triggered_~__retres1~0#1 := 0; 114711#L609 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 114797#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 114798#L1497 assume !(0 != activate_threads_~tmp~1#1); 115704#L1497-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 115611#L617 assume !(1 == ~t1_pc~0); 114353#L617-2 is_transmit1_triggered_~__retres1~1#1 := 0; 114354#L628 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 115321#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 115322#L1505 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 115031#L1505-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 115032#L636 assume 1 == ~t2_pc~0; 114321#L637 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 114322#L647 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 114143#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 114144#L1513 assume !(0 != activate_threads_~tmp___1~0#1); 115071#L1513-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 114687#L655 assume !(1 == ~t3_pc~0); 114688#L655-2 is_transmit3_triggered_~__retres1~3#1 := 0; 115557#L666 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 115306#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 115307#L1521 assume !(0 != activate_threads_~tmp___2~0#1); 115782#L1521-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 115783#L674 assume 1 == ~t4_pc~0; 113851#L675 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 113852#L685 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 113876#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 113877#L1529 assume !(0 != activate_threads_~tmp___3~0#1); 114147#L1529-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 114683#L693 assume !(1 == ~t5_pc~0); 114856#L693-2 is_transmit5_triggered_~__retres1~5#1 := 0; 114493#L704 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 114494#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 115447#L1537 assume !(0 != activate_threads_~tmp___4~0#1); 114575#L1537-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 114511#L712 assume 1 == ~t6_pc~0; 114512#L713 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 114962#L723 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 114132#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 114133#L1545 assume !(0 != activate_threads_~tmp___5~0#1); 115093#L1545-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 115084#L731 assume 1 == ~t7_pc~0; 113991#L732 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 113992#L742 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 114187#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 115451#L1553 assume !(0 != activate_threads_~tmp___6~0#1); 115367#L1553-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 114095#L750 assume !(1 == ~t8_pc~0); 113786#L750-2 is_transmit8_triggered_~__retres1~8#1 := 0; 113785#L761 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 114294#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 115461#L1561 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 114438#L1561-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 114439#L769 assume 1 == ~t9_pc~0; 115029#L770 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 113952#L780 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 113953#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 114177#L1569 assume !(0 != activate_threads_~tmp___8~0#1); 115281#L1569-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 115390#L788 assume !(1 == ~t10_pc~0); 114873#L788-2 is_transmit10_triggered_~__retres1~10#1 := 0; 114874#L799 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 115558#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 115495#L1577 assume !(0 != activate_threads_~tmp___9~0#1); 114091#L1577-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 114092#L807 assume 1 == ~t11_pc~0; 115396#L808 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 114889#L818 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 115073#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 115642#L1585 assume !(0 != activate_threads_~tmp___10~0#1); 115883#L1585-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 115536#L826 assume !(1 == ~t12_pc~0); 114514#L826-2 is_transmit12_triggered_~__retres1~12#1 := 0; 114515#L837 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 113829#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 113830#L1593 assume !(0 != activate_threads_~tmp___11~0#1); 114677#L1593-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 114583#L1344 assume 1 == ~M_E~0;~M_E~0 := 2; 114584#L1344-2 assume !(1 == ~T1_E~0); 114727#L1349-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 114919#L1354-1 assume !(1 == ~T3_E~0); 114920#L1359-1 assume !(1 == ~T4_E~0); 115792#L1364-1 assume !(1 == ~T5_E~0); 115793#L1369-1 assume !(1 == ~T6_E~0); 115354#L1374-1 assume !(1 == ~T7_E~0); 115355#L1379-1 assume !(1 == ~T8_E~0); 115011#L1384-1 assume !(1 == ~T9_E~0); 115012#L1389-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 115579#L1394-1 assume !(1 == ~T11_E~0); 115580#L1399-1 assume !(1 == ~T12_E~0); 115722#L1404-1 assume !(1 == ~E_M~0); 115723#L1409-1 assume !(1 == ~E_1~0); 128949#L1414-1 assume !(1 == ~E_2~0); 128947#L1419-1 assume !(1 == ~E_3~0); 128945#L1424-1 assume !(1 == ~E_4~0); 128943#L1429-1 assume 1 == ~E_5~0;~E_5~0 := 2; 128941#L1434-1 assume !(1 == ~E_6~0); 128939#L1439-1 assume !(1 == ~E_7~0); 128937#L1444-1 assume !(1 == ~E_8~0); 128935#L1449-1 assume !(1 == ~E_9~0); 128933#L1454-1 assume !(1 == ~E_10~0); 128931#L1459-1 assume !(1 == ~E_11~0); 128929#L1464-1 assume !(1 == ~E_12~0); 128926#L1469-1 assume { :end_inline_reset_delta_events } true; 128923#L1815-2 [2022-12-13 13:22:13,032 INFO L750 eck$LassoCheckResult]: Loop: 128923#L1815-2 assume !false; 128921#L1816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 128915#L1181 assume !false; 128913#L1004 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 128906#L926 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 128894#L993 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 128892#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 128889#L1008 assume !(0 != eval_~tmp~0#1); 128890#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 129300#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 129298#L1206-3 assume 0 == ~M_E~0;~M_E~0 := 1; 129296#L1206-5 assume !(0 == ~T1_E~0); 129294#L1211-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 129292#L1216-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 129290#L1221-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 129288#L1226-3 assume !(0 == ~T5_E~0); 129286#L1231-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 129284#L1236-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 129282#L1241-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 129280#L1246-3 assume !(0 == ~T9_E~0); 129278#L1251-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 129276#L1256-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 129274#L1261-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 129272#L1266-3 assume !(0 == ~E_M~0); 129270#L1271-3 assume 0 == ~E_1~0;~E_1~0 := 1; 129268#L1276-3 assume 0 == ~E_2~0;~E_2~0 := 1; 129266#L1281-3 assume 0 == ~E_3~0;~E_3~0 := 1; 129264#L1286-3 assume !(0 == ~E_4~0); 129262#L1291-3 assume 0 == ~E_5~0;~E_5~0 := 1; 129260#L1296-3 assume 0 == ~E_6~0;~E_6~0 := 1; 129258#L1301-3 assume 0 == ~E_7~0;~E_7~0 := 1; 129256#L1306-3 assume !(0 == ~E_8~0); 129254#L1311-3 assume 0 == ~E_9~0;~E_9~0 := 1; 129252#L1316-3 assume 0 == ~E_10~0;~E_10~0 := 1; 129250#L1321-3 assume 0 == ~E_11~0;~E_11~0 := 1; 129248#L1326-3 assume !(0 == ~E_12~0); 129246#L1331-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 129244#L598-42 assume !(1 == ~m_pc~0); 129242#L598-44 is_master_triggered_~__retres1~0#1 := 0; 129240#L609-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 129238#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 129236#L1497-42 assume !(0 != activate_threads_~tmp~1#1); 129234#L1497-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 129232#L617-42 assume 1 == ~t1_pc~0; 129229#L618-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 129228#L628-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 129225#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 129223#L1505-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 129221#L1505-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 129219#L636-42 assume !(1 == ~t2_pc~0); 129217#L636-44 is_transmit2_triggered_~__retres1~2#1 := 0; 129214#L647-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 129211#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 129209#L1513-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 129207#L1513-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 129205#L655-42 assume !(1 == ~t3_pc~0); 129203#L655-44 is_transmit3_triggered_~__retres1~3#1 := 0; 129200#L666-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 129197#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 129195#L1521-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 129193#L1521-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 129191#L674-42 assume !(1 == ~t4_pc~0); 129187#L674-44 is_transmit4_triggered_~__retres1~4#1 := 0; 129184#L685-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 129182#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 129180#L1529-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 129178#L1529-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 129176#L693-42 assume 1 == ~t5_pc~0; 129173#L694-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 129170#L704-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 129168#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 129166#L1537-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 129164#L1537-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 129162#L712-42 assume !(1 == ~t6_pc~0); 129159#L712-44 is_transmit6_triggered_~__retres1~6#1 := 0; 129158#L723-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 129155#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 129153#L1545-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 129151#L1545-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 129149#L731-42 assume !(1 == ~t7_pc~0); 129147#L731-44 is_transmit7_triggered_~__retres1~7#1 := 0; 129144#L742-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 129141#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 129139#L1553-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 129137#L1553-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 129135#L750-42 assume 1 == ~t8_pc~0; 129133#L751-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 129130#L761-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 129127#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 129125#L1561-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 129123#L1561-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 129121#L769-42 assume !(1 == ~t9_pc~0); 129119#L769-44 is_transmit9_triggered_~__retres1~9#1 := 0; 129116#L780-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 129113#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 129111#L1569-42 assume !(0 != activate_threads_~tmp___8~0#1); 129109#L1569-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 129107#L788-42 assume 1 == ~t10_pc~0; 129101#L789-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 129099#L799-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 129097#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 129095#L1577-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 129093#L1577-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 129091#L807-42 assume 1 == ~t11_pc~0; 129088#L808-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 129085#L818-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 129083#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 129081#L1585-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 129079#L1585-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 129077#L826-42 assume 1 == ~t12_pc~0; 129073#L827-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 129071#L837-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 129069#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 129067#L1593-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 129065#L1593-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 129063#L1344-3 assume 1 == ~M_E~0;~M_E~0 := 2; 115183#L1344-5 assume !(1 == ~T1_E~0); 129060#L1349-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 129058#L1354-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 129056#L1359-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 129054#L1364-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 129052#L1369-3 assume !(1 == ~T6_E~0); 129050#L1374-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 129048#L1379-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 129046#L1384-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 127361#L1389-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 129044#L1394-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 129042#L1399-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 129040#L1404-3 assume 1 == ~E_M~0;~E_M~0 := 2; 129038#L1409-3 assume !(1 == ~E_1~0); 129036#L1414-3 assume 1 == ~E_2~0;~E_2~0 := 2; 129034#L1419-3 assume 1 == ~E_3~0;~E_3~0 := 2; 129032#L1424-3 assume 1 == ~E_4~0;~E_4~0 := 2; 129029#L1429-3 assume 1 == ~E_5~0;~E_5~0 := 2; 129027#L1434-3 assume 1 == ~E_6~0;~E_6~0 := 2; 129025#L1439-3 assume 1 == ~E_7~0;~E_7~0 := 2; 129023#L1444-3 assume 1 == ~E_8~0;~E_8~0 := 2; 129021#L1449-3 assume !(1 == ~E_9~0); 129019#L1454-3 assume 1 == ~E_10~0;~E_10~0 := 2; 129017#L1459-3 assume 1 == ~E_11~0;~E_11~0 := 2; 129016#L1464-3 assume 1 == ~E_12~0;~E_12~0 := 2; 129013#L1469-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 129011#L926-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 128999#L993-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 128998#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 128997#L1834 assume !(0 == start_simulation_~tmp~3#1); 116637#L1834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 128992#L926-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 128981#L993-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 128979#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 128977#L1789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 128976#L1796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 128971#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 128925#L1847 assume !(0 != start_simulation_~tmp___0~1#1); 128923#L1815-2 [2022-12-13 13:22:13,032 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 13:22:13,032 INFO L85 PathProgramCache]: Analyzing trace with hash 1218722231, now seen corresponding path program 1 times [2022-12-13 13:22:13,032 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 13:22:13,032 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [765239570] [2022-12-13 13:22:13,032 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 13:22:13,033 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 13:22:13,042 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 13:22:13,080 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 13:22:13,080 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 13:22:13,080 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [765239570] [2022-12-13 13:22:13,081 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [765239570] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 13:22:13,081 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 13:22:13,081 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-12-13 13:22:13,081 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1961657053] [2022-12-13 13:22:13,081 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 13:22:13,081 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 13:22:13,082 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 13:22:13,082 INFO L85 PathProgramCache]: Analyzing trace with hash -466118116, now seen corresponding path program 1 times [2022-12-13 13:22:13,082 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 13:22:13,082 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1477308488] [2022-12-13 13:22:13,082 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 13:22:13,082 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 13:22:13,094 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 13:22:13,122 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 13:22:13,122 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 13:22:13,123 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1477308488] [2022-12-13 13:22:13,123 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1477308488] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 13:22:13,123 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 13:22:13,123 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 13:22:13,123 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2024391327] [2022-12-13 13:22:13,123 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 13:22:13,123 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 13:22:13,124 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 13:22:13,124 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-12-13 13:22:13,124 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-12-13 13:22:13,124 INFO L87 Difference]: Start difference. First operand 22215 states and 32348 transitions. cyclomatic complexity: 10149 Second operand has 5 states, 5 states have (on average 30.0) internal successors, (150), 5 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 13:22:13,479 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 13:22:13,479 INFO L93 Difference]: Finished difference Result 63391 states and 92112 transitions. [2022-12-13 13:22:13,479 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 63391 states and 92112 transitions. [2022-12-13 13:22:13,690 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 62800 [2022-12-13 13:22:13,859 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 63391 states to 63391 states and 92112 transitions. [2022-12-13 13:22:13,859 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 63391 [2022-12-13 13:22:13,890 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 63391 [2022-12-13 13:22:13,890 INFO L73 IsDeterministic]: Start isDeterministic. Operand 63391 states and 92112 transitions. [2022-12-13 13:22:13,919 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 13:22:13,919 INFO L218 hiAutomatonCegarLoop]: Abstraction has 63391 states and 92112 transitions. [2022-12-13 13:22:13,940 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 63391 states and 92112 transitions. [2022-12-13 13:22:14,192 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 63391 to 22824. [2022-12-13 13:22:14,207 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 22824 states, 22824 states have (on average 1.443962495618647) internal successors, (32957), 22823 states have internal predecessors, (32957), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 13:22:14,230 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22824 states to 22824 states and 32957 transitions. [2022-12-13 13:22:14,231 INFO L240 hiAutomatonCegarLoop]: Abstraction has 22824 states and 32957 transitions. [2022-12-13 13:22:14,231 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-12-13 13:22:14,231 INFO L428 stractBuchiCegarLoop]: Abstraction has 22824 states and 32957 transitions. [2022-12-13 13:22:14,231 INFO L335 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2022-12-13 13:22:14,232 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 22824 states and 32957 transitions. [2022-12-13 13:22:14,275 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 22587 [2022-12-13 13:22:14,276 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 13:22:14,276 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 13:22:14,277 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 13:22:14,277 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 13:22:14,277 INFO L748 eck$LassoCheckResult]: Stem: 199619#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 199620#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 200579#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 200580#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 201122#L853 assume 1 == ~m_i~0;~m_st~0 := 0; 200945#L853-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 199901#L858-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 199374#L863-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 199375#L868-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 200686#L873-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 200843#L878-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 201378#L883-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 201379#L888-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 200127#L893-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 200128#L898-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 200716#L903-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 200634#L908-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 200635#L913-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 200802#L1206 assume !(0 == ~M_E~0); 200109#L1206-2 assume !(0 == ~T1_E~0); 200110#L1211-1 assume !(0 == ~T2_E~0); 201115#L1216-1 assume !(0 == ~T3_E~0); 199878#L1221-1 assume !(0 == ~T4_E~0); 199879#L1226-1 assume !(0 == ~T5_E~0); 199550#L1231-1 assume !(0 == ~T6_E~0); 199551#L1236-1 assume !(0 == ~T7_E~0); 201174#L1241-1 assume !(0 == ~T8_E~0); 199950#L1246-1 assume !(0 == ~T9_E~0); 199951#L1251-1 assume !(0 == ~T10_E~0); 200180#L1256-1 assume !(0 == ~T11_E~0); 199384#L1261-1 assume !(0 == ~T12_E~0); 199385#L1266-1 assume !(0 == ~E_M~0); 201350#L1271-1 assume !(0 == ~E_1~0); 200831#L1276-1 assume !(0 == ~E_2~0); 200832#L1281-1 assume !(0 == ~E_3~0); 200746#L1286-1 assume !(0 == ~E_4~0); 199780#L1291-1 assume !(0 == ~E_5~0); 199781#L1296-1 assume !(0 == ~E_6~0); 200531#L1301-1 assume !(0 == ~E_7~0); 200532#L1306-1 assume !(0 == ~E_8~0); 201027#L1311-1 assume !(0 == ~E_9~0); 199739#L1316-1 assume !(0 == ~E_10~0); 199740#L1321-1 assume !(0 == ~E_11~0); 200546#L1326-1 assume !(0 == ~E_12~0); 199607#L1331-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 199608#L598 assume !(1 == ~m_pc~0); 200334#L598-2 is_master_triggered_~__retres1~0#1 := 0; 200335#L609 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 200420#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 200421#L1497 assume !(0 != activate_threads_~tmp~1#1); 201288#L1497-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 201207#L617 assume !(1 == ~t1_pc~0); 199974#L617-2 is_transmit1_triggered_~__retres1~1#1 := 0; 199975#L628 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 201410#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 201308#L1505 assume !(0 != activate_threads_~tmp___0~0#1); 200651#L1505-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 200652#L636 assume 1 == ~t2_pc~0; 199941#L637 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 199942#L647 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 199762#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 199763#L1513 assume !(0 != activate_threads_~tmp___1~0#1); 200685#L1513-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 200308#L655 assume !(1 == ~t3_pc~0); 200309#L655-2 is_transmit3_triggered_~__retres1~3#1 := 0; 201154#L666 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 200906#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 200907#L1521 assume !(0 != activate_threads_~tmp___2~0#1); 201352#L1521-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 201353#L674 assume 1 == ~t4_pc~0; 199470#L675 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 199471#L685 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 199495#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 199496#L1529 assume !(0 != activate_threads_~tmp___3~0#1); 199764#L1529-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 200307#L693 assume !(1 == ~t5_pc~0); 200478#L693-2 is_transmit5_triggered_~__retres1~5#1 := 0; 200111#L704 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 200112#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 201032#L1537 assume !(0 != activate_threads_~tmp___4~0#1); 200193#L1537-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 200131#L712 assume 1 == ~t6_pc~0; 200132#L713 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 200585#L723 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 199751#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 199752#L1545 assume !(0 != activate_threads_~tmp___5~0#1); 200704#L1545-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 200697#L731 assume 1 == ~t7_pc~0; 199609#L732 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 199610#L742 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 199806#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 201035#L1553 assume !(0 != activate_threads_~tmp___6~0#1); 200958#L1553-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 199712#L750 assume !(1 == ~t8_pc~0); 199405#L750-2 is_transmit8_triggered_~__retres1~8#1 := 0; 199404#L761 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 199912#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 201045#L1561 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 200059#L1561-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 200060#L769 assume 1 == ~t9_pc~0; 200647#L770 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 199570#L780 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 199571#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 199796#L1569 assume !(0 != activate_threads_~tmp___8~0#1); 200881#L1569-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 200979#L788 assume !(1 == ~t10_pc~0); 200495#L788-2 is_transmit10_triggered_~__retres1~10#1 := 0; 200496#L799 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 201156#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 201079#L1577 assume !(0 != activate_threads_~tmp___9~0#1); 199708#L1577-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 199709#L807 assume 1 == ~t11_pc~0; 200987#L808 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 200512#L818 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 200687#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 201230#L1585 assume !(0 != activate_threads_~tmp___10~0#1); 201419#L1585-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 201129#L826 assume !(1 == ~t12_pc~0); 200134#L826-2 is_transmit12_triggered_~__retres1~12#1 := 0; 200135#L837 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 199448#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 199449#L1593 assume !(0 != activate_threads_~tmp___11~0#1); 200300#L1593-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 200203#L1344 assume 1 == ~M_E~0;~M_E~0 := 2; 200204#L1344-2 assume !(1 == ~T1_E~0); 200351#L1349-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 200537#L1354-1 assume !(1 == ~T3_E~0); 200538#L1359-1 assume !(1 == ~T4_E~0); 200970#L1364-1 assume !(1 == ~T5_E~0); 199823#L1369-1 assume !(1 == ~T6_E~0); 199824#L1374-1 assume !(1 == ~T7_E~0); 200544#L1379-1 assume !(1 == ~T8_E~0); 200545#L1384-1 assume !(1 == ~T9_E~0); 200631#L1389-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 201954#L1394-1 assume !(1 == ~T11_E~0); 201396#L1399-1 assume !(1 == ~T12_E~0); 201304#L1404-1 assume !(1 == ~E_M~0); 199953#L1409-1 assume !(1 == ~E_1~0); 199954#L1414-1 assume !(1 == ~E_2~0); 200859#L1419-1 assume !(1 == ~E_3~0); 200860#L1424-1 assume !(1 == ~E_4~0); 201774#L1429-1 assume 1 == ~E_5~0;~E_5~0 := 2; 201771#L1434-1 assume !(1 == ~E_6~0); 201769#L1439-1 assume !(1 == ~E_7~0); 201722#L1444-1 assume !(1 == ~E_8~0); 201720#L1449-1 assume !(1 == ~E_9~0); 201716#L1454-1 assume !(1 == ~E_10~0); 201714#L1459-1 assume !(1 == ~E_11~0); 201697#L1464-1 assume !(1 == ~E_12~0); 201684#L1469-1 assume { :end_inline_reset_delta_events } true; 201676#L1815-2 [2022-12-13 13:22:14,277 INFO L750 eck$LassoCheckResult]: Loop: 201676#L1815-2 assume !false; 201670#L1816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 201665#L1181 assume !false; 201664#L1004 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 201661#L926 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 201650#L993 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 201649#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 201647#L1008 assume !(0 != eval_~tmp~0#1); 201646#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 201645#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 201642#L1206-3 assume 0 == ~M_E~0;~M_E~0 := 1; 201641#L1206-5 assume !(0 == ~T1_E~0); 201639#L1211-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 201637#L1216-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 201634#L1221-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 201632#L1226-3 assume !(0 == ~T5_E~0); 201630#L1231-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 201628#L1236-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 201626#L1241-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 201625#L1246-3 assume !(0 == ~T9_E~0); 201624#L1251-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 201608#L1256-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 201594#L1261-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 201519#L1266-3 assume !(0 == ~E_M~0); 201518#L1271-3 assume 0 == ~E_1~0;~E_1~0 := 1; 201516#L1276-3 assume 0 == ~E_2~0;~E_2~0 := 1; 201505#L1281-3 assume 0 == ~E_3~0;~E_3~0 := 1; 201504#L1286-3 assume !(0 == ~E_4~0); 201490#L1291-3 assume 0 == ~E_5~0;~E_5~0 := 1; 201488#L1296-3 assume 0 == ~E_6~0;~E_6~0 := 1; 201486#L1301-3 assume 0 == ~E_7~0;~E_7~0 := 1; 201484#L1306-3 assume !(0 == ~E_8~0); 201482#L1311-3 assume 0 == ~E_9~0;~E_9~0 := 1; 201480#L1316-3 assume 0 == ~E_10~0;~E_10~0 := 1; 201477#L1321-3 assume 0 == ~E_11~0;~E_11~0 := 1; 201476#L1326-3 assume !(0 == ~E_12~0); 201281#L1331-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 200867#L598-42 assume !(1 == ~m_pc~0); 200868#L598-44 is_master_triggered_~__retres1~0#1 := 0; 210543#L609-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 210542#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 210541#L1497-42 assume !(0 != activate_threads_~tmp~1#1); 210540#L1497-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 210539#L617-42 assume !(1 == ~t1_pc~0); 210538#L617-44 is_transmit1_triggered_~__retres1~1#1 := 0; 210536#L628-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 210534#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 210532#L1505-42 assume !(0 != activate_threads_~tmp___0~0#1); 210529#L1505-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 210527#L636-42 assume 1 == ~t2_pc~0; 210523#L637-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 210521#L647-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 210227#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 206789#L1513-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 206540#L1513-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 206539#L655-42 assume !(1 == ~t3_pc~0); 206538#L655-44 is_transmit3_triggered_~__retres1~3#1 := 0; 206536#L666-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 206535#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 206534#L1521-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 206533#L1521-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 206532#L674-42 assume 1 == ~t4_pc~0; 206531#L675-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 206529#L685-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 206528#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 206527#L1529-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 206526#L1529-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 206525#L693-42 assume 1 == ~t5_pc~0; 206523#L694-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 206522#L704-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 206521#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 206520#L1537-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 206519#L1537-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 206518#L712-42 assume 1 == ~t6_pc~0; 206517#L713-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 206515#L723-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 206514#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 206513#L1545-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 206512#L1545-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 206511#L731-42 assume !(1 == ~t7_pc~0); 206510#L731-44 is_transmit7_triggered_~__retres1~7#1 := 0; 206508#L742-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 206507#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 206506#L1553-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 206505#L1553-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 206504#L750-42 assume 1 == ~t8_pc~0; 206503#L751-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 206501#L761-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 206500#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 205396#L1561-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 205395#L1561-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 205394#L769-42 assume !(1 == ~t9_pc~0); 205393#L769-44 is_transmit9_triggered_~__retres1~9#1 := 0; 203914#L780-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 203912#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 203910#L1569-42 assume !(0 != activate_threads_~tmp___8~0#1); 203907#L1569-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 203905#L788-42 assume !(1 == ~t10_pc~0); 203903#L788-44 is_transmit10_triggered_~__retres1~10#1 := 0; 203900#L799-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 203898#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 203896#L1577-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 203895#L1577-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 203892#L807-42 assume 1 == ~t11_pc~0; 203890#L808-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 203887#L818-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 203885#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 203883#L1585-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 203531#L1585-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 203528#L826-42 assume !(1 == ~t12_pc~0); 203526#L826-44 is_transmit12_triggered_~__retres1~12#1 := 0; 203523#L837-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 203521#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 203519#L1593-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 203517#L1593-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 203514#L1344-3 assume 1 == ~M_E~0;~M_E~0 := 2; 202221#L1344-5 assume !(1 == ~T1_E~0); 203511#L1349-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 203509#L1354-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 203507#L1359-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 203505#L1364-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 203504#L1369-3 assume !(1 == ~T6_E~0); 203501#L1374-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 203499#L1379-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 202202#L1384-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 202196#L1389-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 202194#L1394-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 202192#L1399-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 202190#L1404-3 assume 1 == ~E_M~0;~E_M~0 := 2; 202188#L1409-3 assume !(1 == ~E_1~0); 202161#L1414-3 assume 1 == ~E_2~0;~E_2~0 := 2; 202152#L1419-3 assume 1 == ~E_3~0;~E_3~0 := 2; 202143#L1424-3 assume 1 == ~E_4~0;~E_4~0 := 2; 202131#L1429-3 assume 1 == ~E_5~0;~E_5~0 := 2; 202124#L1434-3 assume 1 == ~E_6~0;~E_6~0 := 2; 202116#L1439-3 assume 1 == ~E_7~0;~E_7~0 := 2; 202106#L1444-3 assume 1 == ~E_8~0;~E_8~0 := 2; 202099#L1449-3 assume !(1 == ~E_9~0); 202092#L1454-3 assume 1 == ~E_10~0;~E_10~0 := 2; 202084#L1459-3 assume 1 == ~E_11~0;~E_11~0 := 2; 202078#L1464-3 assume 1 == ~E_12~0;~E_12~0 := 2; 202073#L1469-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 201995#L926-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 201980#L993-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 201979#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 201849#L1834 assume !(0 == start_simulation_~tmp~3#1); 201847#L1834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 201761#L926-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 201712#L993-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 201710#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 201708#L1789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 201707#L1796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 201694#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 201683#L1847 assume !(0 != start_simulation_~tmp___0~1#1); 201676#L1815-2 [2022-12-13 13:22:14,278 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 13:22:14,278 INFO L85 PathProgramCache]: Analyzing trace with hash -1724859847, now seen corresponding path program 1 times [2022-12-13 13:22:14,278 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 13:22:14,278 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1091041155] [2022-12-13 13:22:14,278 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 13:22:14,278 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 13:22:14,286 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 13:22:14,320 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 13:22:14,321 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 13:22:14,321 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1091041155] [2022-12-13 13:22:14,321 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1091041155] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 13:22:14,321 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 13:22:14,321 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 13:22:14,321 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2128469566] [2022-12-13 13:22:14,321 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 13:22:14,322 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 13:22:14,322 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 13:22:14,322 INFO L85 PathProgramCache]: Analyzing trace with hash -1085781026, now seen corresponding path program 1 times [2022-12-13 13:22:14,322 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 13:22:14,322 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1290361696] [2022-12-13 13:22:14,322 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 13:22:14,322 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 13:22:14,329 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 13:22:14,351 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 13:22:14,352 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 13:22:14,352 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1290361696] [2022-12-13 13:22:14,352 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1290361696] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 13:22:14,352 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 13:22:14,352 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 13:22:14,352 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [111303679] [2022-12-13 13:22:14,352 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 13:22:14,353 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 13:22:14,353 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 13:22:14,353 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 13:22:14,353 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 13:22:14,353 INFO L87 Difference]: Start difference. First operand 22824 states and 32957 transitions. cyclomatic complexity: 10149 Second operand has 4 states, 4 states have (on average 37.5) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 13:22:14,690 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 13:22:14,690 INFO L93 Difference]: Finished difference Result 55624 states and 79764 transitions. [2022-12-13 13:22:14,690 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 55624 states and 79764 transitions. [2022-12-13 13:22:14,876 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 54580 [2022-12-13 13:22:14,966 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 55624 states to 55624 states and 79764 transitions. [2022-12-13 13:22:14,967 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 55624 [2022-12-13 13:22:14,987 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 55624 [2022-12-13 13:22:14,987 INFO L73 IsDeterministic]: Start isDeterministic. Operand 55624 states and 79764 transitions. [2022-12-13 13:22:15,014 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 13:22:15,014 INFO L218 hiAutomatonCegarLoop]: Abstraction has 55624 states and 79764 transitions. [2022-12-13 13:22:15,037 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 55624 states and 79764 transitions. [2022-12-13 13:22:15,431 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 55624 to 43656. [2022-12-13 13:22:15,462 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 43656 states, 43656 states have (on average 1.438129924867143) internal successors, (62783), 43655 states have internal predecessors, (62783), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 13:22:15,529 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 43656 states to 43656 states and 62783 transitions. [2022-12-13 13:22:15,529 INFO L240 hiAutomatonCegarLoop]: Abstraction has 43656 states and 62783 transitions. [2022-12-13 13:22:15,529 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 13:22:15,530 INFO L428 stractBuchiCegarLoop]: Abstraction has 43656 states and 62783 transitions. [2022-12-13 13:22:15,530 INFO L335 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2022-12-13 13:22:15,530 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 43656 states and 62783 transitions. [2022-12-13 13:22:15,636 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 43412 [2022-12-13 13:22:15,637 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 13:22:15,637 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 13:22:15,638 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 13:22:15,639 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 13:22:15,639 INFO L748 eck$LassoCheckResult]: Stem: 278075#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 278076#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 279020#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 279021#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 279525#L853 assume 1 == ~m_i~0;~m_st~0 := 0; 279365#L853-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 278355#L858-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 277832#L863-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 277833#L868-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 279124#L873-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 279269#L878-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 279729#L883-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 279730#L888-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 278574#L893-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 278575#L898-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 279157#L903-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 279071#L908-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 279072#L913-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 279231#L1206 assume !(0 == ~M_E~0); 278555#L1206-2 assume !(0 == ~T1_E~0); 278556#L1211-1 assume !(0 == ~T2_E~0); 279519#L1216-1 assume !(0 == ~T3_E~0); 278332#L1221-1 assume !(0 == ~T4_E~0); 278333#L1226-1 assume !(0 == ~T5_E~0); 278008#L1231-1 assume !(0 == ~T6_E~0); 278009#L1236-1 assume !(0 == ~T7_E~0); 279568#L1241-1 assume !(0 == ~T8_E~0); 278399#L1246-1 assume !(0 == ~T9_E~0); 278400#L1251-1 assume !(0 == ~T10_E~0); 278624#L1256-1 assume !(0 == ~T11_E~0); 277842#L1261-1 assume !(0 == ~T12_E~0); 277843#L1266-1 assume !(0 == ~E_M~0); 279714#L1271-1 assume !(0 == ~E_1~0); 279259#L1276-1 assume !(0 == ~E_2~0); 279260#L1281-1 assume !(0 == ~E_3~0); 279188#L1286-1 assume !(0 == ~E_4~0); 278233#L1291-1 assume !(0 == ~E_5~0); 278234#L1296-1 assume !(0 == ~E_6~0); 278972#L1301-1 assume !(0 == ~E_7~0); 278973#L1306-1 assume !(0 == ~E_8~0); 279442#L1311-1 assume !(0 == ~E_9~0); 278194#L1316-1 assume !(0 == ~E_10~0); 278195#L1321-1 assume !(0 == ~E_11~0); 278987#L1326-1 assume !(0 == ~E_12~0); 278063#L1331-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 278064#L598 assume !(1 == ~m_pc~0); 278772#L598-2 is_master_triggered_~__retres1~0#1 := 0; 278773#L609 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 278861#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 278862#L1497 assume !(0 != activate_threads_~tmp~1#1); 279669#L1497-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 279596#L617 assume !(1 == ~t1_pc~0); 278422#L617-2 is_transmit1_triggered_~__retres1~1#1 := 0; 278423#L628 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 279767#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 279679#L1505 assume !(0 != activate_threads_~tmp___0~0#1); 279088#L1505-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 279089#L636 assume !(1 == ~t2_pc~0); 279616#L636-2 is_transmit2_triggered_~__retres1~2#1 := 0; 278841#L647 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 278215#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 278216#L1513 assume !(0 != activate_threads_~tmp___1~0#1); 279123#L1513-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 278747#L655 assume !(1 == ~t3_pc~0); 278748#L655-2 is_transmit3_triggered_~__retres1~3#1 := 0; 279549#L666 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 279329#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 279330#L1521 assume !(0 != activate_threads_~tmp___2~0#1); 279715#L1521-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 279716#L674 assume 1 == ~t4_pc~0; 277927#L675 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 277928#L685 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 277952#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 277953#L1529 assume !(0 != activate_threads_~tmp___3~0#1); 278217#L1529-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 278746#L693 assume !(1 == ~t5_pc~0); 278920#L693-2 is_transmit5_triggered_~__retres1~5#1 := 0; 278559#L704 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 278560#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 279445#L1537 assume !(0 != activate_threads_~tmp___4~0#1); 278639#L1537-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 278576#L712 assume 1 == ~t6_pc~0; 278577#L713 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 279025#L723 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 278204#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 278205#L1545 assume !(0 != activate_threads_~tmp___5~0#1); 279143#L1545-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 279135#L731 assume 1 == ~t7_pc~0; 278065#L732 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 278066#L742 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 278259#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 279449#L1553 assume !(0 != activate_threads_~tmp___6~0#1); 279377#L1553-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 278167#L750 assume !(1 == ~t8_pc~0); 277863#L750-2 is_transmit8_triggered_~__retres1~8#1 := 0; 277862#L761 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 278366#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 279459#L1561 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 278506#L1561-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 278507#L769 assume 1 == ~t9_pc~0; 279086#L770 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 278026#L780 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 278027#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 278249#L1569 assume !(0 != activate_threads_~tmp___8~0#1); 279305#L1569-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 279400#L788 assume !(1 == ~t10_pc~0); 278936#L788-2 is_transmit10_triggered_~__retres1~10#1 := 0; 278937#L799 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 279551#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 279492#L1577 assume !(0 != activate_threads_~tmp___9~0#1); 278163#L1577-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 278164#L807 assume 1 == ~t11_pc~0; 279406#L808 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 278952#L818 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 279125#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 279620#L1585 assume !(0 != activate_threads_~tmp___10~0#1); 279763#L1585-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 279530#L826 assume !(1 == ~t12_pc~0); 278579#L826-2 is_transmit12_triggered_~__retres1~12#1 := 0; 278580#L837 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 277905#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 277906#L1593 assume !(0 != activate_threads_~tmp___11~0#1); 278740#L1593-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 278648#L1344 assume 1 == ~M_E~0;~M_E~0 := 2; 278649#L1344-2 assume !(1 == ~T1_E~0); 318859#L1349-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 318858#L1354-1 assume !(1 == ~T3_E~0); 318857#L1359-1 assume !(1 == ~T4_E~0); 318856#L1364-1 assume !(1 == ~T5_E~0); 318855#L1369-1 assume !(1 == ~T6_E~0); 279369#L1374-1 assume !(1 == ~T7_E~0); 278985#L1379-1 assume !(1 == ~T8_E~0); 278986#L1384-1 assume !(1 == ~T9_E~0); 318848#L1389-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 319764#L1394-1 assume !(1 == ~T11_E~0); 319763#L1399-1 assume !(1 == ~T12_E~0); 319762#L1404-1 assume !(1 == ~E_M~0); 319761#L1409-1 assume !(1 == ~E_1~0); 319760#L1414-1 assume !(1 == ~E_2~0); 319759#L1419-1 assume !(1 == ~E_3~0); 319758#L1424-1 assume !(1 == ~E_4~0); 317257#L1429-1 assume 1 == ~E_5~0;~E_5~0 := 2; 317255#L1434-1 assume !(1 == ~E_6~0); 317253#L1439-1 assume !(1 == ~E_7~0); 317251#L1444-1 assume !(1 == ~E_8~0); 317249#L1449-1 assume !(1 == ~E_9~0); 317247#L1454-1 assume !(1 == ~E_10~0); 279617#L1459-1 assume !(1 == ~E_11~0); 279618#L1464-1 assume !(1 == ~E_12~0); 313743#L1469-1 assume { :end_inline_reset_delta_events } true; 313732#L1815-2 [2022-12-13 13:22:15,639 INFO L750 eck$LassoCheckResult]: Loop: 313732#L1815-2 assume !false; 313722#L1816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 313711#L1181 assume !false; 313708#L1004 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 313647#L926 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 313633#L993 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 313630#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 313535#L1008 assume !(0 != eval_~tmp~0#1); 313536#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 316026#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 316024#L1206-3 assume 0 == ~M_E~0;~M_E~0 := 1; 316022#L1206-5 assume !(0 == ~T1_E~0); 316020#L1211-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 316018#L1216-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 316016#L1221-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 316014#L1226-3 assume !(0 == ~T5_E~0); 316012#L1231-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 316010#L1236-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 316008#L1241-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 316006#L1246-3 assume !(0 == ~T9_E~0); 316004#L1251-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 316002#L1256-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 316000#L1261-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 315998#L1266-3 assume !(0 == ~E_M~0); 315996#L1271-3 assume 0 == ~E_1~0;~E_1~0 := 1; 315994#L1276-3 assume 0 == ~E_2~0;~E_2~0 := 1; 315992#L1281-3 assume 0 == ~E_3~0;~E_3~0 := 1; 315990#L1286-3 assume !(0 == ~E_4~0); 315988#L1291-3 assume 0 == ~E_5~0;~E_5~0 := 1; 315986#L1296-3 assume 0 == ~E_6~0;~E_6~0 := 1; 315984#L1301-3 assume 0 == ~E_7~0;~E_7~0 := 1; 315982#L1306-3 assume !(0 == ~E_8~0); 315980#L1311-3 assume 0 == ~E_9~0;~E_9~0 := 1; 315978#L1316-3 assume 0 == ~E_10~0;~E_10~0 := 1; 315976#L1321-3 assume 0 == ~E_11~0;~E_11~0 := 1; 315974#L1326-3 assume !(0 == ~E_12~0); 315972#L1331-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 315970#L598-42 assume !(1 == ~m_pc~0); 315968#L598-44 is_master_triggered_~__retres1~0#1 := 0; 315966#L609-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 315964#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 315962#L1497-42 assume !(0 != activate_threads_~tmp~1#1); 315960#L1497-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 315956#L617-42 assume !(1 == ~t1_pc~0); 315952#L617-44 is_transmit1_triggered_~__retres1~1#1 := 0; 315950#L628-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 315948#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 315945#L1505-42 assume !(0 != activate_threads_~tmp___0~0#1); 315942#L1505-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 315940#L636-42 assume !(1 == ~t2_pc~0); 288346#L636-44 is_transmit2_triggered_~__retres1~2#1 := 0; 315938#L647-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 315936#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 315934#L1513-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 315932#L1513-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 315930#L655-42 assume 1 == ~t3_pc~0; 315926#L656-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 315924#L666-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 315922#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 315920#L1521-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 315918#L1521-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 315916#L674-42 assume !(1 == ~t4_pc~0); 315912#L674-44 is_transmit4_triggered_~__retres1~4#1 := 0; 315910#L685-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 315908#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 315906#L1529-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 315904#L1529-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 315902#L693-42 assume 1 == ~t5_pc~0; 315898#L694-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 315896#L704-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 315894#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 315892#L1537-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 315890#L1537-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 315888#L712-42 assume !(1 == ~t6_pc~0); 315884#L712-44 is_transmit6_triggered_~__retres1~6#1 := 0; 315882#L723-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 315880#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 315878#L1545-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 315876#L1545-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 315874#L731-42 assume 1 == ~t7_pc~0; 315870#L732-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 315868#L742-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 315866#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 315864#L1553-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 315862#L1553-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 315860#L750-42 assume !(1 == ~t8_pc~0); 315856#L750-44 is_transmit8_triggered_~__retres1~8#1 := 0; 315854#L761-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 315852#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 315850#L1561-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 315848#L1561-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 315846#L769-42 assume 1 == ~t9_pc~0; 315842#L770-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 315840#L780-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 315838#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 315836#L1569-42 assume !(0 != activate_threads_~tmp___8~0#1); 315834#L1569-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 315832#L788-42 assume 1 == ~t10_pc~0; 315828#L789-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 315826#L799-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 315824#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 315822#L1577-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 315820#L1577-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 315818#L807-42 assume !(1 == ~t11_pc~0); 315814#L807-44 is_transmit11_triggered_~__retres1~11#1 := 0; 315812#L818-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 315810#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 315808#L1585-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 315806#L1585-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 315804#L826-42 assume 1 == ~t12_pc~0; 315800#L827-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 315798#L837-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 315796#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 315794#L1593-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 315792#L1593-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 315790#L1344-3 assume 1 == ~M_E~0;~M_E~0 := 2; 279222#L1344-5 assume !(1 == ~T1_E~0); 315787#L1349-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 315785#L1354-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 315783#L1359-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 315781#L1364-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 315779#L1369-3 assume !(1 == ~T6_E~0); 315777#L1374-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 315775#L1379-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 315774#L1384-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 315772#L1389-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 315770#L1394-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 315768#L1399-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 315766#L1404-3 assume 1 == ~E_M~0;~E_M~0 := 2; 315764#L1409-3 assume !(1 == ~E_1~0); 315762#L1414-3 assume 1 == ~E_2~0;~E_2~0 := 2; 315760#L1419-3 assume 1 == ~E_3~0;~E_3~0 := 2; 315758#L1424-3 assume 1 == ~E_4~0;~E_4~0 := 2; 308424#L1429-3 assume 1 == ~E_5~0;~E_5~0 := 2; 315756#L1434-3 assume 1 == ~E_6~0;~E_6~0 := 2; 315754#L1439-3 assume 1 == ~E_7~0;~E_7~0 := 2; 315752#L1444-3 assume 1 == ~E_8~0;~E_8~0 := 2; 315750#L1449-3 assume !(1 == ~E_9~0); 315748#L1454-3 assume 1 == ~E_10~0;~E_10~0 := 2; 315746#L1459-3 assume 1 == ~E_11~0;~E_11~0 := 2; 315745#L1464-3 assume 1 == ~E_12~0;~E_12~0 := 2; 315743#L1469-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 315741#L926-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 315729#L993-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 315728#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 315727#L1834 assume !(0 == start_simulation_~tmp~3#1); 279270#L1834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 313945#L926-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 313935#L993-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 313933#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 313931#L1789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 313929#L1796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 313927#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 313742#L1847 assume !(0 != start_simulation_~tmp___0~1#1); 313732#L1815-2 [2022-12-13 13:22:15,640 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 13:22:15,640 INFO L85 PathProgramCache]: Analyzing trace with hash -607674886, now seen corresponding path program 1 times [2022-12-13 13:22:15,640 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 13:22:15,640 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [657275014] [2022-12-13 13:22:15,640 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 13:22:15,640 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 13:22:15,652 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 13:22:15,687 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 13:22:15,687 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 13:22:15,687 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [657275014] [2022-12-13 13:22:15,687 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [657275014] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 13:22:15,687 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 13:22:15,687 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-12-13 13:22:15,688 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1575052426] [2022-12-13 13:22:15,688 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 13:22:15,688 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 13:22:15,688 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 13:22:15,689 INFO L85 PathProgramCache]: Analyzing trace with hash -1453573026, now seen corresponding path program 1 times [2022-12-13 13:22:15,689 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 13:22:15,689 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1457152799] [2022-12-13 13:22:15,689 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 13:22:15,689 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 13:22:15,700 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 13:22:15,730 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 13:22:15,730 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 13:22:15,730 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1457152799] [2022-12-13 13:22:15,730 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1457152799] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 13:22:15,730 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 13:22:15,730 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 13:22:15,731 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1930859960] [2022-12-13 13:22:15,731 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 13:22:15,731 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 13:22:15,731 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 13:22:15,732 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 13:22:15,732 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 13:22:15,732 INFO L87 Difference]: Start difference. First operand 43656 states and 62783 transitions. cyclomatic complexity: 19143 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 2 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 13:22:16,062 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 13:22:16,063 INFO L93 Difference]: Finished difference Result 83655 states and 119840 transitions. [2022-12-13 13:22:16,063 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 83655 states and 119840 transitions. [2022-12-13 13:22:16,291 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 83332 [2022-12-13 13:22:16,503 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 83655 states to 83655 states and 119840 transitions. [2022-12-13 13:22:16,503 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 83655 [2022-12-13 13:22:16,529 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 83655 [2022-12-13 13:22:16,530 INFO L73 IsDeterministic]: Start isDeterministic. Operand 83655 states and 119840 transitions. [2022-12-13 13:22:16,554 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 13:22:16,554 INFO L218 hiAutomatonCegarLoop]: Abstraction has 83655 states and 119840 transitions. [2022-12-13 13:22:16,582 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 83655 states and 119840 transitions. [2022-12-13 13:22:17,007 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 83655 to 83591. [2022-12-13 13:22:17,055 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 83591 states, 83591 states have (on average 1.4328815303082867) internal successors, (119776), 83590 states have internal predecessors, (119776), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 13:22:17,155 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 83591 states to 83591 states and 119776 transitions. [2022-12-13 13:22:17,155 INFO L240 hiAutomatonCegarLoop]: Abstraction has 83591 states and 119776 transitions. [2022-12-13 13:22:17,156 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 13:22:17,156 INFO L428 stractBuchiCegarLoop]: Abstraction has 83591 states and 119776 transitions. [2022-12-13 13:22:17,156 INFO L335 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2022-12-13 13:22:17,156 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 83591 states and 119776 transitions. [2022-12-13 13:22:17,433 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 83268 [2022-12-13 13:22:17,433 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 13:22:17,434 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 13:22:17,435 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 13:22:17,435 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 13:22:17,436 INFO L748 eck$LassoCheckResult]: Stem: 405389#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 405390#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 406357#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 406358#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 406904#L853 assume 1 == ~m_i~0;~m_st~0 := 0; 406740#L853-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 405672#L858-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 405150#L863-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 405151#L868-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 406471#L873-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 406626#L878-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 407178#L883-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 407179#L888-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 405892#L893-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 405893#L898-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 406507#L903-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 406411#L908-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 406412#L913-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 406584#L1206 assume !(0 == ~M_E~0); 405873#L1206-2 assume !(0 == ~T1_E~0); 405874#L1211-1 assume !(0 == ~T2_E~0); 406898#L1216-1 assume !(0 == ~T3_E~0); 405649#L1221-1 assume !(0 == ~T4_E~0); 405650#L1226-1 assume !(0 == ~T5_E~0); 405322#L1231-1 assume !(0 == ~T6_E~0); 405323#L1236-1 assume !(0 == ~T7_E~0); 406951#L1241-1 assume !(0 == ~T8_E~0); 405718#L1246-1 assume !(0 == ~T9_E~0); 405719#L1251-1 assume !(0 == ~T10_E~0); 405942#L1256-1 assume !(0 == ~T11_E~0); 405160#L1261-1 assume !(0 == ~T12_E~0); 405161#L1266-1 assume !(0 == ~E_M~0); 407150#L1271-1 assume !(0 == ~E_1~0); 406613#L1276-1 assume !(0 == ~E_2~0); 406614#L1281-1 assume !(0 == ~E_3~0); 406538#L1286-1 assume !(0 == ~E_4~0); 405551#L1291-1 assume !(0 == ~E_5~0); 405552#L1296-1 assume !(0 == ~E_6~0); 406308#L1301-1 assume !(0 == ~E_7~0); 406309#L1306-1 assume !(0 == ~E_8~0); 406816#L1311-1 assume !(0 == ~E_9~0); 405511#L1316-1 assume !(0 == ~E_10~0); 405512#L1321-1 assume !(0 == ~E_11~0); 406324#L1326-1 assume !(0 == ~E_12~0); 405377#L1331-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 405378#L598 assume !(1 == ~m_pc~0); 406094#L598-2 is_master_triggered_~__retres1~0#1 := 0; 406095#L609 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 406185#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 406186#L1497 assume !(0 != activate_threads_~tmp~1#1); 407071#L1497-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 406983#L617 assume !(1 == ~t1_pc~0); 405740#L617-2 is_transmit1_triggered_~__retres1~1#1 := 0; 405741#L628 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 407257#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 407097#L1505 assume !(0 != activate_threads_~tmp___0~0#1); 406429#L1505-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 406430#L636 assume !(1 == ~t2_pc~0); 407004#L636-2 is_transmit2_triggered_~__retres1~2#1 := 0; 406163#L647 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 405533#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 405534#L1513 assume !(0 != activate_threads_~tmp___1~0#1); 406470#L1513-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 406068#L655 assume !(1 == ~t3_pc~0); 406069#L655-2 is_transmit3_triggered_~__retres1~3#1 := 0; 406935#L666 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 406696#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 406697#L1521 assume !(0 != activate_threads_~tmp___2~0#1); 407152#L1521-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 407153#L674 assume !(1 == ~t4_pc~0); 406909#L674-2 is_transmit4_triggered_~__retres1~4#1 := 0; 406910#L685 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 405267#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 405268#L1529 assume !(0 != activate_threads_~tmp___3~0#1); 405535#L1529-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 406067#L693 assume !(1 == ~t5_pc~0); 406248#L693-2 is_transmit5_triggered_~__retres1~5#1 := 0; 405877#L704 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 405878#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 406820#L1537 assume !(0 != activate_threads_~tmp___4~0#1); 405955#L1537-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 405894#L712 assume 1 == ~t6_pc~0; 405895#L713 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 406362#L723 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 405521#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 405522#L1545 assume !(0 != activate_threads_~tmp___5~0#1); 406492#L1545-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 406482#L731 assume 1 == ~t7_pc~0; 405379#L732 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 405380#L742 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 405578#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 406824#L1553 assume !(0 != activate_threads_~tmp___6~0#1); 406753#L1553-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 405484#L750 assume !(1 == ~t8_pc~0); 405181#L750-2 is_transmit8_triggered_~__retres1~8#1 := 0; 405180#L761 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 405685#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 406834#L1561 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 405824#L1561-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 405825#L769 assume 1 == ~t9_pc~0; 406427#L770 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 405341#L780 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 405342#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 405568#L1569 assume !(0 != activate_threads_~tmp___8~0#1); 406670#L1569-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 406775#L788 assume !(1 == ~t10_pc~0); 406268#L788-2 is_transmit10_triggered_~__retres1~10#1 := 0; 406269#L799 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 406936#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 406864#L1577 assume !(0 != activate_threads_~tmp___9~0#1); 405480#L1577-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 405481#L807 assume 1 == ~t11_pc~0; 406781#L808 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 406288#L818 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 406472#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 407008#L1585 assume !(0 != activate_threads_~tmp___10~0#1); 407251#L1585-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 406908#L826 assume !(1 == ~t12_pc~0); 405897#L826-2 is_transmit12_triggered_~__retres1~12#1 := 0; 405898#L837 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 405223#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 405224#L1593 assume !(0 != activate_threads_~tmp___11~0#1); 406061#L1593-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 405965#L1344 assume 1 == ~M_E~0;~M_E~0 := 2; 405966#L1344-2 assume !(1 == ~T1_E~0); 406111#L1349-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 406316#L1354-1 assume !(1 == ~T3_E~0); 406317#L1359-1 assume !(1 == ~T4_E~0); 406764#L1364-1 assume !(1 == ~T5_E~0); 405595#L1369-1 assume !(1 == ~T6_E~0); 405596#L1374-1 assume !(1 == ~T7_E~0); 406322#L1379-1 assume !(1 == ~T8_E~0); 406323#L1384-1 assume !(1 == ~T9_E~0); 406410#L1389-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 406954#L1394-1 assume !(1 == ~T11_E~0); 406955#L1399-1 assume !(1 == ~T12_E~0); 407090#L1404-1 assume !(1 == ~E_M~0); 405721#L1409-1 assume !(1 == ~E_1~0); 405722#L1414-1 assume !(1 == ~E_2~0); 406644#L1419-1 assume !(1 == ~E_3~0); 405354#L1424-1 assume !(1 == ~E_4~0); 405355#L1429-1 assume 1 == ~E_5~0;~E_5~0 := 2; 406331#L1434-1 assume !(1 == ~E_6~0); 406976#L1439-1 assume !(1 == ~E_7~0); 405398#L1444-1 assume !(1 == ~E_8~0); 405399#L1449-1 assume !(1 == ~E_9~0); 405830#L1454-1 assume !(1 == ~E_10~0); 405831#L1459-1 assume !(1 == ~E_11~0); 406445#L1464-1 assume !(1 == ~E_12~0); 406446#L1469-1 assume { :end_inline_reset_delta_events } true; 430071#L1815-2 [2022-12-13 13:22:17,436 INFO L750 eck$LassoCheckResult]: Loop: 430071#L1815-2 assume !false; 430068#L1816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 430062#L1181 assume !false; 430060#L1004 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 430051#L926 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 430039#L993 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 430037#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 430034#L1008 assume !(0 != eval_~tmp~0#1); 430035#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 443953#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 443951#L1206-3 assume 0 == ~M_E~0;~M_E~0 := 1; 443949#L1206-5 assume !(0 == ~T1_E~0); 443947#L1211-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 443945#L1216-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 443943#L1221-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 443941#L1226-3 assume !(0 == ~T5_E~0); 443939#L1231-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 443937#L1236-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 443935#L1241-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 443933#L1246-3 assume !(0 == ~T9_E~0); 443931#L1251-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 443929#L1256-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 443927#L1261-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 443925#L1266-3 assume !(0 == ~E_M~0); 443923#L1271-3 assume 0 == ~E_1~0;~E_1~0 := 1; 443921#L1276-3 assume 0 == ~E_2~0;~E_2~0 := 1; 443919#L1281-3 assume 0 == ~E_3~0;~E_3~0 := 1; 443917#L1286-3 assume !(0 == ~E_4~0); 443915#L1291-3 assume 0 == ~E_5~0;~E_5~0 := 1; 443913#L1296-3 assume 0 == ~E_6~0;~E_6~0 := 1; 443911#L1301-3 assume 0 == ~E_7~0;~E_7~0 := 1; 443909#L1306-3 assume !(0 == ~E_8~0); 443907#L1311-3 assume 0 == ~E_9~0;~E_9~0 := 1; 443905#L1316-3 assume 0 == ~E_10~0;~E_10~0 := 1; 443882#L1321-3 assume 0 == ~E_11~0;~E_11~0 := 1; 443870#L1326-3 assume !(0 == ~E_12~0); 443862#L1331-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 443858#L598-42 assume !(1 == ~m_pc~0); 443856#L598-44 is_master_triggered_~__retres1~0#1 := 0; 443854#L609-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 443852#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 443849#L1497-42 assume !(0 != activate_threads_~tmp~1#1); 443847#L1497-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 443846#L617-42 assume !(1 == ~t1_pc~0); 443844#L617-44 is_transmit1_triggered_~__retres1~1#1 := 0; 443842#L628-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 443840#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 443833#L1505-42 assume !(0 != activate_threads_~tmp___0~0#1); 443830#L1505-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 443828#L636-42 assume !(1 == ~t2_pc~0); 441981#L636-44 is_transmit2_triggered_~__retres1~2#1 := 0; 441974#L647-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 441967#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 441961#L1513-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 441953#L1513-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 441945#L655-42 assume !(1 == ~t3_pc~0); 441936#L655-44 is_transmit3_triggered_~__retres1~3#1 := 0; 441925#L666-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 441916#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 441907#L1521-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 440904#L1521-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 440900#L674-42 assume !(1 == ~t4_pc~0); 440898#L674-44 is_transmit4_triggered_~__retres1~4#1 := 0; 440896#L685-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 440894#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 440891#L1529-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 440889#L1529-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 440885#L693-42 assume 1 == ~t5_pc~0; 440882#L694-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 440880#L704-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 440878#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 440875#L1537-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 440873#L1537-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 440797#L712-42 assume 1 == ~t6_pc~0; 440794#L713-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 440791#L723-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 440789#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 440787#L1545-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 440785#L1545-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 440783#L731-42 assume 1 == ~t7_pc~0; 440778#L732-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 440776#L742-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 440774#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 440772#L1553-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 440770#L1553-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 440767#L750-42 assume !(1 == ~t8_pc~0); 440764#L750-44 is_transmit8_triggered_~__retres1~8#1 := 0; 440762#L761-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 440760#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 440758#L1561-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 440756#L1561-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 440755#L769-42 assume !(1 == ~t9_pc~0); 440754#L769-44 is_transmit9_triggered_~__retres1~9#1 := 0; 437513#L780-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 437510#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 437508#L1569-42 assume !(0 != activate_threads_~tmp___8~0#1); 437506#L1569-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 437504#L788-42 assume !(1 == ~t10_pc~0); 437502#L788-44 is_transmit10_triggered_~__retres1~10#1 := 0; 437499#L799-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 437496#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 437494#L1577-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 437492#L1577-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 437490#L807-42 assume 1 == ~t11_pc~0; 437488#L808-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 437485#L818-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 437482#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 437480#L1585-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 437478#L1585-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 437476#L826-42 assume !(1 == ~t12_pc~0); 437474#L826-44 is_transmit12_triggered_~__retres1~12#1 := 0; 437471#L837-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 437470#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 437469#L1593-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 437468#L1593-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 437466#L1344-3 assume 1 == ~M_E~0;~M_E~0 := 2; 407600#L1344-5 assume !(1 == ~T1_E~0); 437463#L1349-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 437461#L1354-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 430230#L1359-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 430228#L1364-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 430226#L1369-3 assume !(1 == ~T6_E~0); 430224#L1374-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 430222#L1379-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 430211#L1384-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 407551#L1389-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 430196#L1394-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 430191#L1399-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 430186#L1404-3 assume 1 == ~E_M~0;~E_M~0 := 2; 430181#L1409-3 assume !(1 == ~E_1~0); 430176#L1414-3 assume 1 == ~E_2~0;~E_2~0 := 2; 430170#L1419-3 assume 1 == ~E_3~0;~E_3~0 := 2; 430165#L1424-3 assume 1 == ~E_4~0;~E_4~0 := 2; 430158#L1429-3 assume 1 == ~E_5~0;~E_5~0 := 2; 430155#L1434-3 assume 1 == ~E_6~0;~E_6~0 := 2; 430152#L1439-3 assume 1 == ~E_7~0;~E_7~0 := 2; 430149#L1444-3 assume 1 == ~E_8~0;~E_8~0 := 2; 430145#L1449-3 assume !(1 == ~E_9~0); 430142#L1454-3 assume 1 == ~E_10~0;~E_10~0 := 2; 430139#L1459-3 assume 1 == ~E_11~0;~E_11~0 := 2; 430136#L1464-3 assume 1 == ~E_12~0;~E_12~0 := 2; 430132#L1469-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 430129#L926-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 430115#L993-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 430113#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 430111#L1834 assume !(0 == start_simulation_~tmp~3#1); 430108#L1834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 430095#L926-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 430085#L993-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 430082#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 430080#L1789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 430078#L1796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 430076#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 430073#L1847 assume !(0 != start_simulation_~tmp___0~1#1); 430071#L1815-2 [2022-12-13 13:22:17,436 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 13:22:17,436 INFO L85 PathProgramCache]: Analyzing trace with hash 852319035, now seen corresponding path program 1 times [2022-12-13 13:22:17,436 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 13:22:17,437 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2117805040] [2022-12-13 13:22:17,437 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 13:22:17,437 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 13:22:17,448 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 13:22:17,495 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 13:22:17,495 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 13:22:17,495 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2117805040] [2022-12-13 13:22:17,495 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2117805040] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 13:22:17,496 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 13:22:17,496 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 13:22:17,496 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [193844839] [2022-12-13 13:22:17,496 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 13:22:17,496 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 13:22:17,497 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 13:22:17,497 INFO L85 PathProgramCache]: Analyzing trace with hash 1315393184, now seen corresponding path program 1 times [2022-12-13 13:22:17,497 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 13:22:17,497 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1696450767] [2022-12-13 13:22:17,497 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 13:22:17,498 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 13:22:17,511 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 13:22:17,543 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 13:22:17,544 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 13:22:17,544 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1696450767] [2022-12-13 13:22:17,544 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1696450767] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 13:22:17,544 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 13:22:17,544 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 13:22:17,544 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [916231451] [2022-12-13 13:22:17,544 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 13:22:17,545 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 13:22:17,545 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 13:22:17,545 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 13:22:17,545 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 13:22:17,546 INFO L87 Difference]: Start difference. First operand 83591 states and 119776 transitions. cyclomatic complexity: 36217 Second operand has 4 states, 4 states have (on average 37.5) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 13:22:18,458 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 13:22:18,458 INFO L93 Difference]: Finished difference Result 202670 states and 288625 transitions. [2022-12-13 13:22:18,458 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 202670 states and 288625 transitions. [2022-12-13 13:22:19,053 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 199052 [2022-12-13 13:22:19,503 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 202670 states to 202670 states and 288625 transitions. [2022-12-13 13:22:19,503 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 202670 [2022-12-13 13:22:19,574 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 202670 [2022-12-13 13:22:19,574 INFO L73 IsDeterministic]: Start isDeterministic. Operand 202670 states and 288625 transitions. [2022-12-13 13:22:19,632 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 13:22:19,632 INFO L218 hiAutomatonCegarLoop]: Abstraction has 202670 states and 288625 transitions. [2022-12-13 13:22:19,711 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 202670 states and 288625 transitions. [2022-12-13 13:22:20,784 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 202670 to 160034. [2022-12-13 13:22:20,853 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 160034 states, 160034 states have (on average 1.4280527887823837) internal successors, (228537), 160033 states have internal predecessors, (228537), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 13:22:21,160 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 160034 states to 160034 states and 228537 transitions. [2022-12-13 13:22:21,160 INFO L240 hiAutomatonCegarLoop]: Abstraction has 160034 states and 228537 transitions. [2022-12-13 13:22:21,161 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 13:22:21,161 INFO L428 stractBuchiCegarLoop]: Abstraction has 160034 states and 228537 transitions. [2022-12-13 13:22:21,161 INFO L335 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2022-12-13 13:22:21,161 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 160034 states and 228537 transitions. [2022-12-13 13:22:21,630 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 159616 [2022-12-13 13:22:21,631 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 13:22:21,631 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 13:22:21,632 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 13:22:21,632 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 13:22:21,632 INFO L748 eck$LassoCheckResult]: Stem: 691661#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 691662#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 692615#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 692616#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 693169#L853 assume 1 == ~m_i~0;~m_st~0 := 0; 692995#L853-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 691948#L858-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 691421#L863-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 691422#L868-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 692731#L873-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 692885#L878-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 693461#L883-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 693462#L888-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 692167#L893-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 692168#L898-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 692763#L903-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 692669#L908-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 692670#L913-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 692841#L1206 assume !(0 == ~M_E~0); 692148#L1206-2 assume !(0 == ~T1_E~0); 692149#L1211-1 assume !(0 == ~T2_E~0); 693160#L1216-1 assume !(0 == ~T3_E~0); 691925#L1221-1 assume !(0 == ~T4_E~0); 691926#L1226-1 assume !(0 == ~T5_E~0); 691594#L1231-1 assume !(0 == ~T6_E~0); 691595#L1236-1 assume !(0 == ~T7_E~0); 693226#L1241-1 assume !(0 == ~T8_E~0); 691993#L1246-1 assume !(0 == ~T9_E~0); 691994#L1251-1 assume !(0 == ~T10_E~0); 692218#L1256-1 assume !(0 == ~T11_E~0); 691431#L1261-1 assume !(0 == ~T12_E~0); 691432#L1266-1 assume !(0 == ~E_M~0); 693430#L1271-1 assume !(0 == ~E_1~0); 692873#L1276-1 assume !(0 == ~E_2~0); 692874#L1281-1 assume !(0 == ~E_3~0); 692795#L1286-1 assume !(0 == ~E_4~0); 691827#L1291-1 assume !(0 == ~E_5~0); 691828#L1296-1 assume !(0 == ~E_6~0); 692567#L1301-1 assume !(0 == ~E_7~0); 692568#L1306-1 assume !(0 == ~E_8~0); 693079#L1311-1 assume !(0 == ~E_9~0); 691787#L1316-1 assume !(0 == ~E_10~0); 691788#L1321-1 assume !(0 == ~E_11~0); 692582#L1326-1 assume !(0 == ~E_12~0); 691649#L1331-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 691650#L598 assume !(1 == ~m_pc~0); 692362#L598-2 is_master_triggered_~__retres1~0#1 := 0; 692363#L609 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 692454#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 692455#L1497 assume !(0 != activate_threads_~tmp~1#1); 693357#L1497-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 693267#L617 assume !(1 == ~t1_pc~0); 692015#L617-2 is_transmit1_triggered_~__retres1~1#1 := 0; 692016#L628 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 693524#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 693383#L1505 assume !(0 != activate_threads_~tmp___0~0#1); 692686#L1505-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 692687#L636 assume !(1 == ~t2_pc~0); 693295#L636-2 is_transmit2_triggered_~__retres1~2#1 := 0; 692431#L647 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 691809#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 691810#L1513 assume !(0 != activate_threads_~tmp___1~0#1); 692730#L1513-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 692341#L655 assume !(1 == ~t3_pc~0); 692342#L655-2 is_transmit3_triggered_~__retres1~3#1 := 0; 693200#L666 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 692954#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 692955#L1521 assume !(0 != activate_threads_~tmp___2~0#1); 693431#L1521-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 693432#L674 assume !(1 == ~t4_pc~0); 693174#L674-2 is_transmit4_triggered_~__retres1~4#1 := 0; 693175#L685 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 691538#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 691539#L1529 assume !(0 != activate_threads_~tmp___3~0#1); 691813#L1529-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 692339#L693 assume !(1 == ~t5_pc~0); 692513#L693-2 is_transmit5_triggered_~__retres1~5#1 := 0; 692152#L704 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 692153#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 693081#L1537 assume !(0 != activate_threads_~tmp___4~0#1); 692233#L1537-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 692169#L712 assume !(1 == ~t6_pc~0); 692170#L712-2 is_transmit6_triggered_~__retres1~6#1 := 0; 692619#L723 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 691797#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 691798#L1545 assume !(0 != activate_threads_~tmp___5~0#1); 692751#L1545-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 692742#L731 assume 1 == ~t7_pc~0; 691651#L732 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 691652#L742 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 691853#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 693085#L1553 assume !(0 != activate_threads_~tmp___6~0#1); 693013#L1553-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 691759#L750 assume !(1 == ~t8_pc~0); 691452#L750-2 is_transmit8_triggered_~__retres1~8#1 := 0; 691451#L761 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 691959#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 693097#L1561 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 692100#L1561-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 692101#L769 assume 1 == ~t9_pc~0; 692684#L770 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 691611#L780 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 691612#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 691842#L1569 assume !(0 != activate_threads_~tmp___8~0#1); 692927#L1569-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 693036#L788 assume !(1 == ~t10_pc~0); 692529#L788-2 is_transmit10_triggered_~__retres1~10#1 := 0; 692530#L799 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 693204#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 693129#L1577 assume !(0 != activate_threads_~tmp___9~0#1); 691755#L1577-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 691756#L807 assume 1 == ~t11_pc~0; 693043#L808 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 692547#L818 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 692732#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 693299#L1585 assume !(0 != activate_threads_~tmp___10~0#1); 693522#L1585-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 693173#L826 assume !(1 == ~t12_pc~0); 692171#L826-2 is_transmit12_triggered_~__retres1~12#1 := 0; 692172#L837 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 691494#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 691495#L1593 assume !(0 != activate_threads_~tmp___11~0#1); 692333#L1593-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 692242#L1344 assume 1 == ~M_E~0;~M_E~0 := 2; 692243#L1344-2 assume !(1 == ~T1_E~0); 692380#L1349-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 692575#L1354-1 assume !(1 == ~T3_E~0); 692576#L1359-1 assume !(1 == ~T4_E~0); 693440#L1364-1 assume !(1 == ~T5_E~0); 693441#L1369-1 assume !(1 == ~T6_E~0); 692999#L1374-1 assume !(1 == ~T7_E~0); 693000#L1379-1 assume !(1 == ~T8_E~0); 692667#L1384-1 assume !(1 == ~T9_E~0); 692668#L1389-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 693231#L1394-1 assume !(1 == ~T11_E~0); 693232#L1399-1 assume !(1 == ~T12_E~0); 693377#L1404-1 assume !(1 == ~E_M~0); 693378#L1409-1 assume !(1 == ~E_1~0); 693353#L1414-1 assume !(1 == ~E_2~0); 693354#L1419-1 assume !(1 == ~E_3~0); 691626#L1424-1 assume !(1 == ~E_4~0); 691627#L1429-1 assume 1 == ~E_5~0;~E_5~0 := 2; 692590#L1434-1 assume !(1 == ~E_6~0); 693477#L1439-1 assume !(1 == ~E_7~0); 693478#L1444-1 assume !(1 == ~E_8~0); 692853#L1449-1 assume !(1 == ~E_9~0); 692854#L1454-1 assume !(1 == ~E_10~0); 693296#L1459-1 assume !(1 == ~E_11~0); 693297#L1464-1 assume !(1 == ~E_12~0); 692708#L1469-1 assume { :end_inline_reset_delta_events } true; 692764#L1815-2 [2022-12-13 13:22:21,633 INFO L750 eck$LassoCheckResult]: Loop: 692764#L1815-2 assume !false; 728716#L1816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 712174#L1181 assume !false; 711336#L1004 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 697052#L926 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 697040#L993 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 697037#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 697034#L1008 assume !(0 != eval_~tmp~0#1); 697035#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 730801#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 730800#L1206-3 assume 0 == ~M_E~0;~M_E~0 := 1; 730799#L1206-5 assume !(0 == ~T1_E~0); 730798#L1211-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 730797#L1216-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 730796#L1221-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 730795#L1226-3 assume !(0 == ~T5_E~0); 730794#L1231-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 730793#L1236-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 730792#L1241-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 730791#L1246-3 assume !(0 == ~T9_E~0); 730790#L1251-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 730789#L1256-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 730788#L1261-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 730787#L1266-3 assume !(0 == ~E_M~0); 730786#L1271-3 assume 0 == ~E_1~0;~E_1~0 := 1; 730785#L1276-3 assume 0 == ~E_2~0;~E_2~0 := 1; 730784#L1281-3 assume 0 == ~E_3~0;~E_3~0 := 1; 730783#L1286-3 assume !(0 == ~E_4~0); 730782#L1291-3 assume 0 == ~E_5~0;~E_5~0 := 1; 730781#L1296-3 assume 0 == ~E_6~0;~E_6~0 := 1; 730780#L1301-3 assume 0 == ~E_7~0;~E_7~0 := 1; 730779#L1306-3 assume !(0 == ~E_8~0); 730778#L1311-3 assume 0 == ~E_9~0;~E_9~0 := 1; 730777#L1316-3 assume 0 == ~E_10~0;~E_10~0 := 1; 730776#L1321-3 assume 0 == ~E_11~0;~E_11~0 := 1; 730775#L1326-3 assume !(0 == ~E_12~0); 730774#L1331-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 730773#L598-42 assume !(1 == ~m_pc~0); 730772#L598-44 is_master_triggered_~__retres1~0#1 := 0; 730771#L609-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 730770#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 730769#L1497-42 assume !(0 != activate_threads_~tmp~1#1); 730768#L1497-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 730767#L617-42 assume !(1 == ~t1_pc~0); 730766#L617-44 is_transmit1_triggered_~__retres1~1#1 := 0; 730764#L628-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 730762#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 730760#L1505-42 assume !(0 != activate_threads_~tmp___0~0#1); 730758#L1505-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 730757#L636-42 assume !(1 == ~t2_pc~0); 724577#L636-44 is_transmit2_triggered_~__retres1~2#1 := 0; 730756#L647-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 730755#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 730754#L1513-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 730753#L1513-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 730752#L655-42 assume !(1 == ~t3_pc~0); 730751#L655-44 is_transmit3_triggered_~__retres1~3#1 := 0; 730749#L666-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 730748#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 730747#L1521-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 730746#L1521-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 730745#L674-42 assume !(1 == ~t4_pc~0); 730744#L674-44 is_transmit4_triggered_~__retres1~4#1 := 0; 730743#L685-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 730742#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 730741#L1529-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 730740#L1529-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 730739#L693-42 assume !(1 == ~t5_pc~0); 730738#L693-44 is_transmit5_triggered_~__retres1~5#1 := 0; 730736#L704-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 730735#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 730734#L1537-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 730733#L1537-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 730732#L712-42 assume !(1 == ~t6_pc~0); 696632#L712-44 is_transmit6_triggered_~__retres1~6#1 := 0; 730731#L723-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 730730#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 730729#L1545-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 730728#L1545-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 730727#L731-42 assume !(1 == ~t7_pc~0); 730726#L731-44 is_transmit7_triggered_~__retres1~7#1 := 0; 730724#L742-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 730723#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 730722#L1553-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 730721#L1553-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 730720#L750-42 assume 1 == ~t8_pc~0; 730719#L751-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 730717#L761-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 730716#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 730715#L1561-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 730714#L1561-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 730713#L769-42 assume !(1 == ~t9_pc~0); 730712#L769-44 is_transmit9_triggered_~__retres1~9#1 := 0; 730710#L780-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 730709#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 730708#L1569-42 assume !(0 != activate_threads_~tmp___8~0#1); 730707#L1569-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 730706#L788-42 assume !(1 == ~t10_pc~0); 730705#L788-44 is_transmit10_triggered_~__retres1~10#1 := 0; 730703#L799-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 730702#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 730701#L1577-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 730700#L1577-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 730699#L807-42 assume 1 == ~t11_pc~0; 730698#L808-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 730696#L818-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 730695#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 730694#L1585-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 730693#L1585-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 730692#L826-42 assume !(1 == ~t12_pc~0); 730691#L826-44 is_transmit12_triggered_~__retres1~12#1 := 0; 730689#L837-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 730688#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 730687#L1593-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 730686#L1593-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 730685#L1344-3 assume 1 == ~M_E~0;~M_E~0 := 2; 713262#L1344-5 assume !(1 == ~T1_E~0); 730684#L1349-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 730683#L1354-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 730682#L1359-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 730681#L1364-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 730680#L1369-3 assume !(1 == ~T6_E~0); 730679#L1374-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 730678#L1379-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 730677#L1384-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 718143#L1389-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 730676#L1394-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 730675#L1399-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 730674#L1404-3 assume 1 == ~E_M~0;~E_M~0 := 2; 730673#L1409-3 assume !(1 == ~E_1~0); 730672#L1414-3 assume 1 == ~E_2~0;~E_2~0 := 2; 730671#L1419-3 assume 1 == ~E_3~0;~E_3~0 := 2; 730670#L1424-3 assume 1 == ~E_4~0;~E_4~0 := 2; 725787#L1429-3 assume 1 == ~E_5~0;~E_5~0 := 2; 730669#L1434-3 assume 1 == ~E_6~0;~E_6~0 := 2; 730668#L1439-3 assume 1 == ~E_7~0;~E_7~0 := 2; 730667#L1444-3 assume 1 == ~E_8~0;~E_8~0 := 2; 730666#L1449-3 assume !(1 == ~E_9~0); 730665#L1454-3 assume 1 == ~E_10~0;~E_10~0 := 2; 730664#L1459-3 assume 1 == ~E_11~0;~E_11~0 := 2; 730663#L1464-3 assume 1 == ~E_12~0;~E_12~0 := 2; 728225#L1469-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 730652#L926-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 730638#L993-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 730637#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 693447#L1834 assume !(0 == start_simulation_~tmp~3#1); 693448#L1834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 729003#L926-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 728993#L993-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 728990#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 728989#L1789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 728979#L1796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 728972#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 728787#L1847 assume !(0 != start_simulation_~tmp___0~1#1); 692764#L1815-2 [2022-12-13 13:22:21,633 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 13:22:21,633 INFO L85 PathProgramCache]: Analyzing trace with hash 1989947900, now seen corresponding path program 1 times [2022-12-13 13:22:21,633 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 13:22:21,633 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [667125132] [2022-12-13 13:22:21,633 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 13:22:21,633 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 13:22:21,641 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 13:22:21,682 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 13:22:21,683 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 13:22:21,683 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [667125132] [2022-12-13 13:22:21,683 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [667125132] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 13:22:21,683 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 13:22:21,683 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 13:22:21,683 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2066976638] [2022-12-13 13:22:21,683 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 13:22:21,684 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 13:22:21,684 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 13:22:21,684 INFO L85 PathProgramCache]: Analyzing trace with hash 293617570, now seen corresponding path program 1 times [2022-12-13 13:22:21,684 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 13:22:21,684 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1799392305] [2022-12-13 13:22:21,684 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 13:22:21,685 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 13:22:21,694 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 13:22:21,715 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 13:22:21,715 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 13:22:21,715 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1799392305] [2022-12-13 13:22:21,715 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1799392305] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 13:22:21,715 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 13:22:21,715 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 13:22:21,716 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1683462736] [2022-12-13 13:22:21,716 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 13:22:21,716 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 13:22:21,716 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 13:22:21,716 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 13:22:21,717 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 13:22:21,717 INFO L87 Difference]: Start difference. First operand 160034 states and 228537 transitions. cyclomatic complexity: 68535 Second operand has 4 states, 4 states have (on average 37.5) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 13:22:22,932 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 13:22:22,932 INFO L93 Difference]: Finished difference Result 387109 states and 549562 transitions. [2022-12-13 13:22:22,933 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 387109 states and 549562 transitions. [2022-12-13 13:22:24,262 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 380132 [2022-12-13 13:22:24,978 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 387109 states to 387109 states and 549562 transitions. [2022-12-13 13:22:24,979 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 387109 [2022-12-13 13:22:25,132 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 387109 [2022-12-13 13:22:25,132 INFO L73 IsDeterministic]: Start isDeterministic. Operand 387109 states and 549562 transitions. [2022-12-13 13:22:25,380 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 13:22:25,380 INFO L218 hiAutomatonCegarLoop]: Abstraction has 387109 states and 549562 transitions. [2022-12-13 13:22:25,510 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 387109 states and 549562 transitions. [2022-12-13 13:22:27,256 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 387109 to 306129. [2022-12-13 13:22:27,433 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 306129 states, 306129 states have (on average 1.423576335466421) internal successors, (435798), 306128 states have internal predecessors, (435798), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 13:22:28,253 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 306129 states to 306129 states and 435798 transitions. [2022-12-13 13:22:28,253 INFO L240 hiAutomatonCegarLoop]: Abstraction has 306129 states and 435798 transitions. [2022-12-13 13:22:28,254 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 13:22:28,254 INFO L428 stractBuchiCegarLoop]: Abstraction has 306129 states and 435798 transitions. [2022-12-13 13:22:28,254 INFO L335 stractBuchiCegarLoop]: ======== Iteration 23 ============ [2022-12-13 13:22:28,254 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 306129 states and 435798 transitions. [2022-12-13 13:22:29,124 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 305520 [2022-12-13 13:22:29,124 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 13:22:29,124 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 13:22:29,126 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 13:22:29,127 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 13:22:29,127 INFO L748 eck$LassoCheckResult]: Stem: 1238810#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 1238811#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 1239787#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1239788#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1240354#L853 assume 1 == ~m_i~0;~m_st~0 := 0; 1240164#L853-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1239096#L858-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1238574#L863-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1238575#L868-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1239897#L873-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1240058#L878-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1240646#L883-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1240647#L888-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1239318#L893-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1239319#L898-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 1239930#L903-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 1239838#L908-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 1239839#L913-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1240013#L1206 assume !(0 == ~M_E~0); 1239299#L1206-2 assume !(0 == ~T1_E~0); 1239300#L1211-1 assume !(0 == ~T2_E~0); 1240345#L1216-1 assume !(0 == ~T3_E~0); 1239072#L1221-1 assume !(0 == ~T4_E~0); 1239073#L1226-1 assume !(0 == ~T5_E~0); 1238747#L1231-1 assume !(0 == ~T6_E~0); 1238748#L1236-1 assume !(0 == ~T7_E~0); 1240408#L1241-1 assume !(0 == ~T8_E~0); 1239142#L1246-1 assume !(0 == ~T9_E~0); 1239143#L1251-1 assume !(0 == ~T10_E~0); 1239369#L1256-1 assume !(0 == ~T11_E~0); 1238584#L1261-1 assume !(0 == ~T12_E~0); 1238585#L1266-1 assume !(0 == ~E_M~0); 1240612#L1271-1 assume !(0 == ~E_1~0); 1240047#L1276-1 assume !(0 == ~E_2~0); 1240048#L1281-1 assume !(0 == ~E_3~0); 1239962#L1286-1 assume !(0 == ~E_4~0); 1238973#L1291-1 assume !(0 == ~E_5~0); 1238974#L1296-1 assume !(0 == ~E_6~0); 1239736#L1301-1 assume !(0 == ~E_7~0); 1239737#L1306-1 assume !(0 == ~E_8~0); 1240255#L1311-1 assume !(0 == ~E_9~0); 1238933#L1316-1 assume !(0 == ~E_10~0); 1238934#L1321-1 assume !(0 == ~E_11~0); 1239753#L1326-1 assume !(0 == ~E_12~0); 1238802#L1331-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1238803#L598 assume !(1 == ~m_pc~0); 1239526#L598-2 is_master_triggered_~__retres1~0#1 := 0; 1239527#L609 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1239620#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1239621#L1497 assume !(0 != activate_threads_~tmp~1#1); 1240543#L1497-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1240445#L617 assume !(1 == ~t1_pc~0); 1239164#L617-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1239165#L628 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1240697#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1240563#L1505 assume !(0 != activate_threads_~tmp___0~0#1); 1239855#L1505-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1239856#L636 assume !(1 == ~t2_pc~0); 1240473#L636-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1239597#L647 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1238955#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1238956#L1513 assume !(0 != activate_threads_~tmp___1~0#1); 1239896#L1513-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1239500#L655 assume !(1 == ~t3_pc~0); 1239501#L655-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1240389#L666 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1240125#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1240126#L1521 assume !(0 != activate_threads_~tmp___2~0#1); 1240613#L1521-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1240614#L674 assume !(1 == ~t4_pc~0); 1240360#L674-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1240361#L685 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1238691#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1238692#L1529 assume !(0 != activate_threads_~tmp___3~0#1); 1238959#L1529-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1239498#L693 assume !(1 == ~t5_pc~0); 1239681#L693-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1239303#L704 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1239304#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1240260#L1537 assume !(0 != activate_threads_~tmp___4~0#1); 1239386#L1537-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1239320#L712 assume !(1 == ~t6_pc~0); 1239321#L712-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1239791#L723 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1238943#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1238944#L1545 assume !(0 != activate_threads_~tmp___5~0#1); 1239917#L1545-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1239908#L731 assume !(1 == ~t7_pc~0); 1239909#L731-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1238999#L742 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1239000#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1240267#L1553 assume !(0 != activate_threads_~tmp___6~0#1); 1240180#L1553-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1238906#L750 assume !(1 == ~t8_pc~0); 1238605#L750-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1238604#L761 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1239107#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1240279#L1561 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1239252#L1561-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1239253#L769 assume 1 == ~t9_pc~0; 1239853#L770 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 1238764#L780 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1238765#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1238989#L1569 assume !(0 != activate_threads_~tmp___8~0#1); 1240100#L1569-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1240205#L788 assume !(1 == ~t10_pc~0); 1239700#L788-2 is_transmit10_triggered_~__retres1~10#1 := 0; 1239701#L799 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1240391#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1240313#L1577 assume !(0 != activate_threads_~tmp___9~0#1); 1238902#L1577-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1238903#L807 assume 1 == ~t11_pc~0; 1240212#L808 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 1239717#L818 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1239898#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1240477#L1585 assume !(0 != activate_threads_~tmp___10~0#1); 1240695#L1585-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 1240359#L826 assume !(1 == ~t12_pc~0); 1239322#L826-2 is_transmit12_triggered_~__retres1~12#1 := 0; 1239323#L837 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1238647#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 1238648#L1593 assume !(0 != activate_threads_~tmp___11~0#1); 1239491#L1593-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1239395#L1344 assume 1 == ~M_E~0;~M_E~0 := 2; 1239396#L1344-2 assume !(1 == ~T1_E~0); 1240677#L1349-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1240678#L1354-1 assume !(1 == ~T3_E~0); 1240192#L1359-1 assume !(1 == ~T4_E~0); 1240193#L1364-1 assume !(1 == ~T5_E~0); 1239017#L1369-1 assume !(1 == ~T6_E~0); 1239018#L1374-1 assume !(1 == ~T7_E~0); 1239751#L1379-1 assume !(1 == ~T8_E~0); 1239752#L1384-1 assume !(1 == ~T9_E~0); 1341198#L1389-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 1341193#L1394-1 assume !(1 == ~T11_E~0); 1341194#L1399-1 assume !(1 == ~T12_E~0); 1341186#L1404-1 assume !(1 == ~E_M~0); 1341187#L1409-1 assume !(1 == ~E_1~0); 1341183#L1414-1 assume !(1 == ~E_2~0); 1341184#L1419-1 assume !(1 == ~E_3~0); 1238779#L1424-1 assume !(1 == ~E_4~0); 1238780#L1429-1 assume 1 == ~E_5~0;~E_5~0 := 2; 1240434#L1434-1 assume !(1 == ~E_6~0); 1240435#L1439-1 assume !(1 == ~E_7~0); 1238819#L1444-1 assume !(1 == ~E_8~0); 1238820#L1449-1 assume !(1 == ~E_9~0); 1239258#L1454-1 assume !(1 == ~E_10~0); 1239259#L1459-1 assume !(1 == ~E_11~0); 1239873#L1464-1 assume !(1 == ~E_12~0); 1239874#L1469-1 assume { :end_inline_reset_delta_events } true; 1379506#L1815-2 [2022-12-13 13:22:29,127 INFO L750 eck$LassoCheckResult]: Loop: 1379506#L1815-2 assume !false; 1379504#L1816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1379499#L1181 assume !false; 1379498#L1004 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 1379432#L926 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 1379420#L993 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 1379418#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1379336#L1008 assume !(0 != eval_~tmp~0#1); 1379337#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1383818#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1383816#L1206-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1383814#L1206-5 assume !(0 == ~T1_E~0); 1383805#L1211-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1383801#L1216-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1383799#L1221-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1383797#L1226-3 assume !(0 == ~T5_E~0); 1383795#L1231-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1383792#L1236-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1383790#L1241-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1383788#L1246-3 assume !(0 == ~T9_E~0); 1383787#L1251-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 1383785#L1256-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 1382162#L1261-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 1382157#L1266-3 assume !(0 == ~E_M~0); 1382151#L1271-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1382143#L1276-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1382135#L1281-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1382127#L1286-3 assume !(0 == ~E_4~0); 1382120#L1291-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1381791#L1296-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1381789#L1301-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1381785#L1306-3 assume !(0 == ~E_8~0); 1381780#L1311-3 assume 0 == ~E_9~0;~E_9~0 := 1; 1381775#L1316-3 assume 0 == ~E_10~0;~E_10~0 := 1; 1381770#L1321-3 assume 0 == ~E_11~0;~E_11~0 := 1; 1381765#L1326-3 assume !(0 == ~E_12~0); 1381760#L1331-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1381754#L598-42 assume !(1 == ~m_pc~0); 1381748#L598-44 is_master_triggered_~__retres1~0#1 := 0; 1381743#L609-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1381738#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1381733#L1497-42 assume !(0 != activate_threads_~tmp~1#1); 1381728#L1497-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1381722#L617-42 assume !(1 == ~t1_pc~0); 1381717#L617-44 is_transmit1_triggered_~__retres1~1#1 := 0; 1381711#L628-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1381705#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1381699#L1505-42 assume !(0 != activate_threads_~tmp___0~0#1); 1381693#L1505-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1381687#L636-42 assume !(1 == ~t2_pc~0); 1376244#L636-44 is_transmit2_triggered_~__retres1~2#1 := 0; 1381677#L647-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1381672#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1381667#L1513-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1381662#L1513-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1381656#L655-42 assume !(1 == ~t3_pc~0); 1381652#L655-44 is_transmit3_triggered_~__retres1~3#1 := 0; 1381646#L666-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1381641#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1381636#L1521-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1381631#L1521-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1381626#L674-42 assume !(1 == ~t4_pc~0); 1381621#L674-44 is_transmit4_triggered_~__retres1~4#1 := 0; 1381615#L685-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1381609#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1381603#L1529-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1381311#L1529-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1381308#L693-42 assume 1 == ~t5_pc~0; 1381305#L694-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1381303#L704-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1381301#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1381300#L1537-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1381299#L1537-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1381297#L712-42 assume !(1 == ~t6_pc~0); 1379623#L712-44 is_transmit6_triggered_~__retres1~6#1 := 0; 1381294#L723-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1381292#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1381290#L1545-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1381288#L1545-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1381281#L731-42 assume !(1 == ~t7_pc~0); 1288791#L731-44 is_transmit7_triggered_~__retres1~7#1 := 0; 1381267#L742-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1381266#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1381265#L1553-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1381264#L1553-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1381263#L750-42 assume !(1 == ~t8_pc~0); 1381261#L750-44 is_transmit8_triggered_~__retres1~8#1 := 0; 1381259#L761-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1381257#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1381255#L1561-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1381253#L1561-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1381251#L769-42 assume !(1 == ~t9_pc~0); 1381249#L769-44 is_transmit9_triggered_~__retres1~9#1 := 0; 1381246#L780-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1381244#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1381242#L1569-42 assume !(0 != activate_threads_~tmp___8~0#1); 1381240#L1569-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1381238#L788-42 assume !(1 == ~t10_pc~0); 1381236#L788-44 is_transmit10_triggered_~__retres1~10#1 := 0; 1381233#L799-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1381231#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1381229#L1577-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1381227#L1577-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1381225#L807-42 assume 1 == ~t11_pc~0; 1381223#L808-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 1381214#L818-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1381204#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1381203#L1585-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 1381202#L1585-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 1381201#L826-42 assume !(1 == ~t12_pc~0); 1381200#L826-44 is_transmit12_triggered_~__retres1~12#1 := 0; 1381198#L837-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1381197#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 1381196#L1593-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 1381195#L1593-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1381194#L1344-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1341760#L1344-5 assume !(1 == ~T1_E~0); 1381193#L1349-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1381192#L1354-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1381190#L1359-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1381188#L1364-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1381186#L1369-3 assume !(1 == ~T6_E~0); 1381184#L1374-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1381182#L1379-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1381180#L1384-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1371575#L1389-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 1381177#L1394-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 1381175#L1399-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 1381173#L1404-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1381171#L1409-3 assume !(1 == ~E_1~0); 1381169#L1414-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1381167#L1419-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1381165#L1424-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1352094#L1429-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1381162#L1434-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1381160#L1439-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1381158#L1444-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1381156#L1449-3 assume !(1 == ~E_9~0); 1381154#L1454-3 assume 1 == ~E_10~0;~E_10~0 := 2; 1381152#L1459-3 assume 1 == ~E_11~0;~E_11~0 := 2; 1381150#L1464-3 assume 1 == ~E_12~0;~E_12~0 := 2; 1341712#L1469-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 1381144#L926-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 1380464#L993-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 1380461#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 1380457#L1834 assume !(0 == start_simulation_~tmp~3#1); 1380453#L1834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 1379534#L926-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 1379523#L993-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 1379521#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 1379519#L1789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1379518#L1796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1379513#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 1379512#L1847 assume !(0 != start_simulation_~tmp___0~1#1); 1379506#L1815-2 [2022-12-13 13:22:29,127 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 13:22:29,128 INFO L85 PathProgramCache]: Analyzing trace with hash -1728090755, now seen corresponding path program 1 times [2022-12-13 13:22:29,128 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 13:22:29,128 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [144312389] [2022-12-13 13:22:29,128 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 13:22:29,128 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 13:22:29,136 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 13:22:29,174 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 13:22:29,174 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 13:22:29,174 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [144312389] [2022-12-13 13:22:29,174 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [144312389] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 13:22:29,174 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 13:22:29,174 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-12-13 13:22:29,174 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [845371905] [2022-12-13 13:22:29,175 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 13:22:29,175 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 13:22:29,175 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 13:22:29,175 INFO L85 PathProgramCache]: Analyzing trace with hash -1378480670, now seen corresponding path program 1 times [2022-12-13 13:22:29,175 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 13:22:29,176 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1423804561] [2022-12-13 13:22:29,176 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 13:22:29,176 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 13:22:29,187 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 13:22:29,218 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 13:22:29,218 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 13:22:29,218 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1423804561] [2022-12-13 13:22:29,219 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1423804561] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 13:22:29,219 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 13:22:29,219 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 13:22:29,219 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [572189042] [2022-12-13 13:22:29,219 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 13:22:29,219 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 13:22:29,219 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 13:22:29,219 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-12-13 13:22:29,220 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-12-13 13:22:29,220 INFO L87 Difference]: Start difference. First operand 306129 states and 435798 transitions. cyclomatic complexity: 129701 Second operand has 5 states, 5 states have (on average 30.0) internal successors, (150), 5 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 13:22:31,005 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 13:22:31,005 INFO L93 Difference]: Finished difference Result 739572 states and 1059859 transitions. [2022-12-13 13:22:31,005 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 739572 states and 1059859 transitions. [2022-12-13 13:22:33,715 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 737952 [2022-12-13 13:22:34,904 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 739572 states to 739572 states and 1059859 transitions. [2022-12-13 13:22:34,904 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 739572 [2022-12-13 13:22:35,093 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 739572 [2022-12-13 13:22:35,093 INFO L73 IsDeterministic]: Start isDeterministic. Operand 739572 states and 1059859 transitions. [2022-12-13 13:22:35,304 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 13:22:35,305 INFO L218 hiAutomatonCegarLoop]: Abstraction has 739572 states and 1059859 transitions. [2022-12-13 13:22:35,567 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 739572 states and 1059859 transitions. [2022-12-13 13:22:38,499 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 739572 to 314292. [2022-12-13 13:22:38,651 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 314292 states, 314292 states have (on average 1.4125749303195754) internal successors, (443961), 314291 states have internal predecessors, (443961), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 13:22:39,317 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 314292 states to 314292 states and 443961 transitions. [2022-12-13 13:22:39,317 INFO L240 hiAutomatonCegarLoop]: Abstraction has 314292 states and 443961 transitions. [2022-12-13 13:22:39,317 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-12-13 13:22:39,317 INFO L428 stractBuchiCegarLoop]: Abstraction has 314292 states and 443961 transitions. [2022-12-13 13:22:39,318 INFO L335 stractBuchiCegarLoop]: ======== Iteration 24 ============ [2022-12-13 13:22:39,318 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 314292 states and 443961 transitions. [2022-12-13 13:22:39,831 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 313680 [2022-12-13 13:22:39,832 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 13:22:39,832 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 13:22:39,834 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 13:22:39,834 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 13:22:39,834 INFO L748 eck$LassoCheckResult]: Stem: 2284523#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 2284524#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 2285502#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2285503#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2286050#L853 assume 1 == ~m_i~0;~m_st~0 := 0; 2285873#L853-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2284808#L858-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2284288#L863-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2284289#L868-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 2285610#L873-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 2285765#L878-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 2286328#L883-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 2286329#L888-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 2285036#L893-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 2285037#L898-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 2285642#L903-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 2285555#L908-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 2285556#L913-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2285722#L1206 assume !(0 == ~M_E~0); 2285014#L1206-2 assume !(0 == ~T1_E~0); 2285015#L1211-1 assume !(0 == ~T2_E~0); 2286042#L1216-1 assume !(0 == ~T3_E~0); 2284785#L1221-1 assume !(0 == ~T4_E~0); 2284786#L1226-1 assume !(0 == ~T5_E~0); 2284460#L1231-1 assume !(0 == ~T6_E~0); 2284461#L1236-1 assume !(0 == ~T7_E~0); 2286101#L1241-1 assume !(0 == ~T8_E~0); 2284857#L1246-1 assume !(0 == ~T9_E~0); 2284858#L1251-1 assume !(0 == ~T10_E~0); 2285085#L1256-1 assume !(0 == ~T11_E~0); 2284298#L1261-1 assume !(0 == ~T12_E~0); 2284299#L1266-1 assume !(0 == ~E_M~0); 2286306#L1271-1 assume !(0 == ~E_1~0); 2285753#L1276-1 assume !(0 == ~E_2~0); 2285754#L1281-1 assume !(0 == ~E_3~0); 2285673#L1286-1 assume !(0 == ~E_4~0); 2284684#L1291-1 assume !(0 == ~E_5~0); 2284685#L1296-1 assume !(0 == ~E_6~0); 2285451#L1301-1 assume !(0 == ~E_7~0); 2285452#L1306-1 assume !(0 == ~E_8~0); 2285963#L1311-1 assume !(0 == ~E_9~0); 2284644#L1316-1 assume !(0 == ~E_10~0); 2284645#L1321-1 assume !(0 == ~E_11~0); 2285466#L1326-1 assume !(0 == ~E_12~0); 2284515#L1331-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2284516#L598 assume !(1 == ~m_pc~0); 2285241#L598-2 is_master_triggered_~__retres1~0#1 := 0; 2285242#L609 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2285337#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2285338#L1497 assume !(0 != activate_threads_~tmp~1#1); 2286240#L1497-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2286145#L617 assume !(1 == ~t1_pc~0); 2284879#L617-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2284880#L628 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2286389#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2286259#L1505 assume !(0 != activate_threads_~tmp___0~0#1); 2285572#L1505-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2285573#L636 assume !(1 == ~t2_pc~0); 2286168#L636-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2285313#L647 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2284666#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2284667#L1513 assume !(0 != activate_threads_~tmp___1~0#1); 2285609#L1513-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2285213#L655 assume !(1 == ~t3_pc~0); 2285214#L655-2 is_transmit3_triggered_~__retres1~3#1 := 0; 2286081#L666 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2285832#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2285833#L1521 assume !(0 != activate_threads_~tmp___2~0#1); 2286307#L1521-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2286308#L674 assume !(1 == ~t4_pc~0); 2286057#L674-2 is_transmit4_triggered_~__retres1~4#1 := 0; 2286058#L685 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2284404#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 2284405#L1529 assume !(0 != activate_threads_~tmp___3~0#1); 2284668#L1529-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2285212#L693 assume !(1 == ~t5_pc~0); 2285398#L693-2 is_transmit5_triggered_~__retres1~5#1 := 0; 2285019#L704 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2285020#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 2285965#L1537 assume !(0 != activate_threads_~tmp___4~0#1); 2285101#L1537-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2285038#L712 assume !(1 == ~t6_pc~0); 2285039#L712-2 is_transmit6_triggered_~__retres1~6#1 := 0; 2285507#L723 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2284654#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 2284655#L1545 assume !(0 != activate_threads_~tmp___5~0#1); 2285629#L1545-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2285620#L731 assume !(1 == ~t7_pc~0); 2285621#L731-2 is_transmit7_triggered_~__retres1~7#1 := 0; 2284711#L742 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2284712#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 2285969#L1553 assume !(0 != activate_threads_~tmp___6~0#1); 2285887#L1553-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2284616#L750 assume !(1 == ~t8_pc~0); 2284319#L750-2 is_transmit8_triggered_~__retres1~8#1 := 0; 2284819#L761 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2284820#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 2285980#L1561 assume !(0 != activate_threads_~tmp___7~0#1); 2284965#L1561-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 2284966#L769 assume 1 == ~t9_pc~0; 2285570#L770 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 2284478#L780 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 2284479#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 2284700#L1569 assume !(0 != activate_threads_~tmp___8~0#1); 2285803#L1569-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 2285917#L788 assume !(1 == ~t10_pc~0); 2285414#L788-2 is_transmit10_triggered_~__retres1~10#1 := 0; 2285415#L799 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 2286083#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 2286014#L1577 assume !(0 != activate_threads_~tmp___9~0#1); 2284612#L1577-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 2284613#L807 assume 1 == ~t11_pc~0; 2285924#L808 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 2285431#L818 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 2285611#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 2286170#L1585 assume !(0 != activate_threads_~tmp___10~0#1); 2286384#L1585-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 2286056#L826 assume !(1 == ~t12_pc~0); 2285040#L826-2 is_transmit12_triggered_~__retres1~12#1 := 0; 2285041#L837 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 2284360#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 2284361#L1593 assume !(0 != activate_threads_~tmp___11~0#1); 2285206#L1593-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2285109#L1344 assume 1 == ~M_E~0;~M_E~0 := 2; 2285110#L1344-2 assume !(1 == ~T1_E~0); 2285259#L1349-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2285458#L1354-1 assume !(1 == ~T3_E~0); 2285459#L1359-1 assume !(1 == ~T4_E~0); 2307851#L1364-1 assume !(1 == ~T5_E~0); 2307849#L1369-1 assume !(1 == ~T6_E~0); 2307847#L1374-1 assume !(1 == ~T7_E~0); 2285464#L1379-1 assume !(1 == ~T8_E~0); 2285465#L1384-1 assume !(1 == ~T9_E~0); 2285554#L1389-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 2309104#L1394-1 assume !(1 == ~T11_E~0); 2309095#L1399-1 assume !(1 == ~T12_E~0); 2286252#L1404-1 assume !(1 == ~E_M~0); 2286253#L1409-1 assume !(1 == ~E_1~0); 2309079#L1414-1 assume !(1 == ~E_2~0); 2285783#L1419-1 assume !(1 == ~E_3~0); 2284492#L1424-1 assume !(1 == ~E_4~0); 2284493#L1429-1 assume 1 == ~E_5~0;~E_5~0 := 2; 2314253#L1434-1 assume !(1 == ~E_6~0); 2314239#L1439-1 assume !(1 == ~E_7~0); 2314237#L1444-1 assume !(1 == ~E_8~0); 2314235#L1449-1 assume !(1 == ~E_9~0); 2314233#L1454-1 assume !(1 == ~E_10~0); 2314231#L1459-1 assume !(1 == ~E_11~0); 2314229#L1464-1 assume !(1 == ~E_12~0); 2314227#L1469-1 assume { :end_inline_reset_delta_events } true; 2313638#L1815-2 [2022-12-13 13:22:39,834 INFO L750 eck$LassoCheckResult]: Loop: 2313638#L1815-2 assume !false; 2313525#L1816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2313519#L1181 assume !false; 2313517#L1004 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 2312205#L926 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 2312193#L993 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 2312192#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 2312187#L1008 assume !(0 != eval_~tmp~0#1); 2312188#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2358756#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2358754#L1206-3 assume 0 == ~M_E~0;~M_E~0 := 1; 2358752#L1206-5 assume !(0 == ~T1_E~0); 2358750#L1211-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2358748#L1216-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2358746#L1221-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2358744#L1226-3 assume !(0 == ~T5_E~0); 2358742#L1231-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 2358740#L1236-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 2358738#L1241-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 2358736#L1246-3 assume !(0 == ~T9_E~0); 2358734#L1251-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 2358732#L1256-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 2358730#L1261-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 2358728#L1266-3 assume !(0 == ~E_M~0); 2358726#L1271-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2358724#L1276-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2358722#L1281-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2358720#L1286-3 assume !(0 == ~E_4~0); 2358718#L1291-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2358716#L1296-3 assume 0 == ~E_6~0;~E_6~0 := 1; 2358714#L1301-3 assume 0 == ~E_7~0;~E_7~0 := 1; 2358712#L1306-3 assume !(0 == ~E_8~0); 2358710#L1311-3 assume 0 == ~E_9~0;~E_9~0 := 1; 2358708#L1316-3 assume 0 == ~E_10~0;~E_10~0 := 1; 2358706#L1321-3 assume 0 == ~E_11~0;~E_11~0 := 1; 2358704#L1326-3 assume !(0 == ~E_12~0); 2358702#L1331-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2358700#L598-42 assume !(1 == ~m_pc~0); 2358698#L598-44 is_master_triggered_~__retres1~0#1 := 0; 2358696#L609-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2358694#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2358692#L1497-42 assume !(0 != activate_threads_~tmp~1#1); 2358690#L1497-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2358688#L617-42 assume !(1 == ~t1_pc~0); 2358685#L617-44 is_transmit1_triggered_~__retres1~1#1 := 0; 2358681#L628-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2358677#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2358673#L1505-42 assume !(0 != activate_threads_~tmp___0~0#1); 2358670#L1505-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2358668#L636-42 assume !(1 == ~t2_pc~0); 2354834#L636-44 is_transmit2_triggered_~__retres1~2#1 := 0; 2358577#L647-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2358578#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2358454#L1513-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2358455#L1513-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2358444#L655-42 assume !(1 == ~t3_pc~0); 2358446#L655-44 is_transmit3_triggered_~__retres1~3#1 := 0; 2358434#L666-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2358435#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2358426#L1521-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2358427#L1521-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2358418#L674-42 assume !(1 == ~t4_pc~0); 2358419#L674-44 is_transmit4_triggered_~__retres1~4#1 := 0; 2358406#L685-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2358407#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 2358323#L1529-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 2358324#L1529-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2358313#L693-42 assume !(1 == ~t5_pc~0); 2358315#L693-44 is_transmit5_triggered_~__retres1~5#1 := 0; 2357416#L704-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2357417#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 2357412#L1537-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 2357413#L1537-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2316102#L712-42 assume !(1 == ~t6_pc~0); 2316101#L712-44 is_transmit6_triggered_~__retres1~6#1 := 0; 2316100#L723-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2316099#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 2316098#L1545-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 2316097#L1545-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2316096#L731-42 assume !(1 == ~t7_pc~0); 2315587#L731-44 is_transmit7_triggered_~__retres1~7#1 := 0; 2316095#L742-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2316094#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 2316093#L1553-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 2316092#L1553-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2316091#L750-42 assume !(1 == ~t8_pc~0); 2316090#L750-44 is_transmit8_triggered_~__retres1~8#1 := 0; 2316088#L761-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2316086#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 2316084#L1561-42 assume !(0 != activate_threads_~tmp___7~0#1); 2316079#L1561-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 2316077#L769-42 assume !(1 == ~t9_pc~0); 2316075#L769-44 is_transmit9_triggered_~__retres1~9#1 := 0; 2316071#L780-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 2316069#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 2316067#L1569-42 assume !(0 != activate_threads_~tmp___8~0#1); 2316065#L1569-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 2316063#L788-42 assume !(1 == ~t10_pc~0); 2316061#L788-44 is_transmit10_triggered_~__retres1~10#1 := 0; 2316057#L799-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 2316055#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 2316053#L1577-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 2316051#L1577-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 2316049#L807-42 assume 1 == ~t11_pc~0; 2316045#L808-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 2316042#L818-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 2316039#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 2316037#L1585-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 2316035#L1585-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 2316033#L826-42 assume !(1 == ~t12_pc~0); 2316031#L826-44 is_transmit12_triggered_~__retres1~12#1 := 0; 2316028#L837-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 2316027#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 2316024#L1593-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 2316022#L1593-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2316020#L1344-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2308128#L1344-5 assume !(1 == ~T1_E~0); 2316015#L1349-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2316013#L1354-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2316010#L1359-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2316008#L1364-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2316006#L1369-3 assume !(1 == ~T6_E~0); 2316004#L1374-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 2316002#L1379-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 2315402#L1384-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 2315398#L1389-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 2315396#L1394-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 2315393#L1399-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 2315391#L1404-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2315389#L1409-3 assume !(1 == ~E_1~0); 2315387#L1414-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2315385#L1419-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2315383#L1424-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2315378#L1429-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2315376#L1434-3 assume 1 == ~E_6~0;~E_6~0 := 2; 2315374#L1439-3 assume 1 == ~E_7~0;~E_7~0 := 2; 2315372#L1444-3 assume 1 == ~E_8~0;~E_8~0 := 2; 2315370#L1449-3 assume !(1 == ~E_9~0); 2315368#L1454-3 assume 1 == ~E_10~0;~E_10~0 := 2; 2315365#L1459-3 assume 1 == ~E_11~0;~E_11~0 := 2; 2315363#L1464-3 assume 1 == ~E_12~0;~E_12~0 := 2; 2315359#L1469-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 2315352#L926-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 2315339#L993-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 2315337#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 2315335#L1834 assume !(0 == start_simulation_~tmp~3#1); 2315332#L1834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 2314248#L926-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 2314238#L993-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 2314236#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 2314234#L1789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2314232#L1796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2314230#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 2314226#L1847 assume !(0 != start_simulation_~tmp___0~1#1); 2313638#L1815-2 [2022-12-13 13:22:39,835 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 13:22:39,835 INFO L85 PathProgramCache]: Analyzing trace with hash -1284190081, now seen corresponding path program 1 times [2022-12-13 13:22:39,835 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 13:22:39,835 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [448718572] [2022-12-13 13:22:39,835 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 13:22:39,835 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 13:22:39,843 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 13:22:39,878 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 13:22:39,878 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 13:22:39,878 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [448718572] [2022-12-13 13:22:39,878 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [448718572] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 13:22:39,878 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 13:22:39,878 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 13:22:39,878 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1805373745] [2022-12-13 13:22:39,878 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 13:22:39,879 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 13:22:39,879 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 13:22:39,879 INFO L85 PathProgramCache]: Analyzing trace with hash -254933403, now seen corresponding path program 1 times [2022-12-13 13:22:39,879 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 13:22:39,879 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [558349729] [2022-12-13 13:22:39,880 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 13:22:39,880 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 13:22:39,889 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 13:22:39,909 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 13:22:39,909 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 13:22:39,909 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [558349729] [2022-12-13 13:22:39,909 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [558349729] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 13:22:39,910 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 13:22:39,910 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 13:22:39,910 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [56392465] [2022-12-13 13:22:39,910 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 13:22:39,910 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 13:22:39,910 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 13:22:39,911 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 13:22:39,911 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 13:22:39,911 INFO L87 Difference]: Start difference. First operand 314292 states and 443961 transitions. cyclomatic complexity: 129701 Second operand has 4 states, 4 states have (on average 37.5) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 13:22:42,340 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 13:22:42,340 INFO L93 Difference]: Finished difference Result 755955 states and 1061958 transitions. [2022-12-13 13:22:42,340 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 755955 states and 1061958 transitions. [2022-12-13 13:22:44,819 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 741904 [2022-12-13 13:22:46,095 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 755955 states to 755955 states and 1061958 transitions. [2022-12-13 13:22:46,095 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 755955 [2022-12-13 13:22:46,377 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 755955 [2022-12-13 13:22:46,377 INFO L73 IsDeterministic]: Start isDeterministic. Operand 755955 states and 1061958 transitions. [2022-12-13 13:22:46,751 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 13:22:46,751 INFO L218 hiAutomatonCegarLoop]: Abstraction has 755955 states and 1061958 transitions. [2022-12-13 13:22:47,091 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 755955 states and 1061958 transitions. [2022-12-13 13:22:51,400 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 755955 to 600419. [2022-12-13 13:22:51,630 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 600419 states, 600419 states have (on average 1.4085730131791299) internal successors, (845734), 600418 states have internal predecessors, (845734), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 13:22:52,947 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 600419 states to 600419 states and 845734 transitions. [2022-12-13 13:22:52,947 INFO L240 hiAutomatonCegarLoop]: Abstraction has 600419 states and 845734 transitions. [2022-12-13 13:22:52,948 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 13:22:52,948 INFO L428 stractBuchiCegarLoop]: Abstraction has 600419 states and 845734 transitions. [2022-12-13 13:22:52,948 INFO L335 stractBuchiCegarLoop]: ======== Iteration 25 ============ [2022-12-13 13:22:52,948 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 600419 states and 845734 transitions. [2022-12-13 13:22:54,196 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 599424 [2022-12-13 13:22:54,196 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 13:22:54,196 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 13:22:54,199 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 13:22:54,199 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 13:22:54,200 INFO L748 eck$LassoCheckResult]: Stem: 3354779#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 3354780#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 3355759#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3355760#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3356336#L853 assume 1 == ~m_i~0;~m_st~0 := 0; 3356145#L853-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3355062#L858-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3354545#L863-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3354546#L868-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 3355869#L873-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 3356029#L878-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 3356662#L883-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 3356663#L888-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 3355291#L893-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 3355292#L898-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 3355903#L903-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 3355814#L908-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 3355815#L913-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3355984#L1206 assume !(0 == ~M_E~0); 3355270#L1206-2 assume !(0 == ~T1_E~0); 3355271#L1211-1 assume !(0 == ~T2_E~0); 3356330#L1216-1 assume !(0 == ~T3_E~0); 3355039#L1221-1 assume !(0 == ~T4_E~0); 3355040#L1226-1 assume !(0 == ~T5_E~0); 3354718#L1231-1 assume !(0 == ~T6_E~0); 3354719#L1236-1 assume !(0 == ~T7_E~0); 3356391#L1241-1 assume !(0 == ~T8_E~0); 3355112#L1246-1 assume !(0 == ~T9_E~0); 3355113#L1251-1 assume !(0 == ~T10_E~0); 3355344#L1256-1 assume !(0 == ~T11_E~0); 3354555#L1261-1 assume !(0 == ~T12_E~0); 3354556#L1266-1 assume !(0 == ~E_M~0); 3356633#L1271-1 assume !(0 == ~E_1~0); 3356017#L1276-1 assume !(0 == ~E_2~0); 3356018#L1281-1 assume !(0 == ~E_3~0); 3355937#L1286-1 assume !(0 == ~E_4~0); 3354940#L1291-1 assume !(0 == ~E_5~0); 3354941#L1296-1 assume !(0 == ~E_6~0); 3355712#L1301-1 assume !(0 == ~E_7~0); 3355713#L1306-1 assume !(0 == ~E_8~0); 3356241#L1311-1 assume !(0 == ~E_9~0); 3354900#L1316-1 assume !(0 == ~E_10~0); 3354901#L1321-1 assume !(0 == ~E_11~0); 3355727#L1326-1 assume !(0 == ~E_12~0); 3354771#L1331-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3354772#L598 assume !(1 == ~m_pc~0); 3355494#L598-2 is_master_triggered_~__retres1~0#1 := 0; 3355495#L609 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3355590#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3355591#L1497 assume !(0 != activate_threads_~tmp~1#1); 3356553#L1497-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3356442#L617 assume !(1 == ~t1_pc~0); 3355134#L617-2 is_transmit1_triggered_~__retres1~1#1 := 0; 3355135#L628 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3356741#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3356573#L1505 assume !(0 != activate_threads_~tmp___0~0#1); 3355829#L1505-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3355830#L636 assume !(1 == ~t2_pc~0); 3356472#L636-2 is_transmit2_triggered_~__retres1~2#1 := 0; 3355567#L647 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3354922#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3354923#L1513 assume !(0 != activate_threads_~tmp___1~0#1); 3355868#L1513-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3355471#L655 assume !(1 == ~t3_pc~0); 3355472#L655-2 is_transmit3_triggered_~__retres1~3#1 := 0; 3356371#L666 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3356100#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3356101#L1521 assume !(0 != activate_threads_~tmp___2~0#1); 3356635#L1521-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3356636#L674 assume !(1 == ~t4_pc~0); 3356344#L674-2 is_transmit4_triggered_~__retres1~4#1 := 0; 3356345#L685 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3354662#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3354663#L1529 assume !(0 != activate_threads_~tmp___3~0#1); 3354924#L1529-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3355470#L693 assume !(1 == ~t5_pc~0); 3355655#L693-2 is_transmit5_triggered_~__retres1~5#1 := 0; 3355276#L704 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3355277#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 3356243#L1537 assume !(0 != activate_threads_~tmp___4~0#1); 3355360#L1537-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3355293#L712 assume !(1 == ~t6_pc~0); 3355294#L712-2 is_transmit6_triggered_~__retres1~6#1 := 0; 3355764#L723 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3354910#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 3354911#L1545 assume !(0 != activate_threads_~tmp___5~0#1); 3355890#L1545-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3355881#L731 assume !(1 == ~t7_pc~0); 3355882#L731-2 is_transmit7_triggered_~__retres1~7#1 := 0; 3354966#L742 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3354967#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 3356252#L1553 assume !(0 != activate_threads_~tmp___6~0#1); 3356158#L1553-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3354872#L750 assume !(1 == ~t8_pc~0); 3354576#L750-2 is_transmit8_triggered_~__retres1~8#1 := 0; 3355073#L761 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3355074#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 3356264#L1561 assume !(0 != activate_threads_~tmp___7~0#1); 3355221#L1561-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3355222#L769 assume !(1 == ~t9_pc~0); 3355828#L769-2 is_transmit9_triggered_~__retres1~9#1 := 0; 3354736#L780 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3354737#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 3354956#L1569 assume !(0 != activate_threads_~tmp___8~0#1); 3356072#L1569-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 3356183#L788 assume !(1 == ~t10_pc~0); 3355671#L788-2 is_transmit10_triggered_~__retres1~10#1 := 0; 3355672#L799 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 3356374#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 3356294#L1577 assume !(0 != activate_threads_~tmp___9~0#1); 3354868#L1577-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 3354869#L807 assume 1 == ~t11_pc~0; 3356190#L808 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 3355693#L818 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 3355870#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 3356476#L1585 assume !(0 != activate_threads_~tmp___10~0#1); 3356736#L1585-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 3356343#L826 assume !(1 == ~t12_pc~0); 3355295#L826-2 is_transmit12_triggered_~__retres1~12#1 := 0; 3355296#L837 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 3354618#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 3354619#L1593 assume !(0 != activate_threads_~tmp___11~0#1); 3355464#L1593-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3355369#L1344 assume 1 == ~M_E~0;~M_E~0 := 2; 3355370#L1344-2 assume !(1 == ~T1_E~0); 3355513#L1349-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3355719#L1354-1 assume !(1 == ~T3_E~0); 3355720#L1359-1 assume !(1 == ~T4_E~0); 3356645#L1364-1 assume !(1 == ~T5_E~0); 3356646#L1369-1 assume !(1 == ~T6_E~0); 3356149#L1374-1 assume !(1 == ~T7_E~0); 3356150#L1379-1 assume !(1 == ~T8_E~0); 3355812#L1384-1 assume !(1 == ~T9_E~0); 3355813#L1389-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 3356394#L1394-1 assume !(1 == ~T11_E~0); 3356395#L1399-1 assume !(1 == ~T12_E~0); 3356567#L1404-1 assume !(1 == ~E_M~0); 3356568#L1409-1 assume !(1 == ~E_1~0); 3356550#L1414-1 assume !(1 == ~E_2~0); 3356551#L1419-1 assume !(1 == ~E_3~0); 3354749#L1424-1 assume !(1 == ~E_4~0); 3354750#L1429-1 assume 1 == ~E_5~0;~E_5~0 := 2; 3356421#L1434-1 assume !(1 == ~E_6~0); 3356422#L1439-1 assume !(1 == ~E_7~0); 3572740#L1444-1 assume !(1 == ~E_8~0); 3355998#L1449-1 assume !(1 == ~E_9~0); 3355999#L1454-1 assume !(1 == ~E_10~0); 3356473#L1459-1 assume !(1 == ~E_11~0); 3356474#L1464-1 assume !(1 == ~E_12~0); 3570557#L1469-1 assume { :end_inline_reset_delta_events } true; 3572730#L1815-2 [2022-12-13 13:22:54,200 INFO L750 eck$LassoCheckResult]: Loop: 3572730#L1815-2 assume !false; 3572722#L1816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3572715#L1181 assume !false; 3572712#L1004 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 3572643#L926 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 3572628#L993 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 3572620#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 3572613#L1008 assume !(0 != eval_~tmp~0#1); 3572614#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3641121#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3641119#L1206-3 assume 0 == ~M_E~0;~M_E~0 := 1; 3641117#L1206-5 assume !(0 == ~T1_E~0); 3641115#L1211-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3641113#L1216-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3641111#L1221-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3641109#L1226-3 assume !(0 == ~T5_E~0); 3641107#L1231-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 3641105#L1236-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 3641103#L1241-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 3641101#L1246-3 assume !(0 == ~T9_E~0); 3641099#L1251-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 3641097#L1256-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 3641094#L1261-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 3641090#L1266-3 assume !(0 == ~E_M~0); 3641086#L1271-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3641082#L1276-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3641079#L1281-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3641076#L1286-3 assume !(0 == ~E_4~0); 3641074#L1291-3 assume 0 == ~E_5~0;~E_5~0 := 1; 3641071#L1296-3 assume 0 == ~E_6~0;~E_6~0 := 1; 3641067#L1301-3 assume 0 == ~E_7~0;~E_7~0 := 1; 3641063#L1306-3 assume !(0 == ~E_8~0); 3641059#L1311-3 assume 0 == ~E_9~0;~E_9~0 := 1; 3641055#L1316-3 assume 0 == ~E_10~0;~E_10~0 := 1; 3641051#L1321-3 assume 0 == ~E_11~0;~E_11~0 := 1; 3641048#L1326-3 assume !(0 == ~E_12~0); 3641046#L1331-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3641043#L598-42 assume !(1 == ~m_pc~0); 3641039#L598-44 is_master_triggered_~__retres1~0#1 := 0; 3641035#L609-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3640614#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3640328#L1497-42 assume !(0 != activate_threads_~tmp~1#1); 3640324#L1497-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3640322#L617-42 assume 1 == ~t1_pc~0; 3640319#L618-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3640314#L628-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3640309#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3640304#L1505-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3640300#L1505-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3640296#L636-42 assume !(1 == ~t2_pc~0); 3623321#L636-44 is_transmit2_triggered_~__retres1~2#1 := 0; 3640288#L647-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3640282#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3640276#L1513-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3640270#L1513-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3640265#L655-42 assume 1 == ~t3_pc~0; 3640263#L656-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3640262#L666-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3640242#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3640239#L1521-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3640236#L1521-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3640233#L674-42 assume !(1 == ~t4_pc~0); 3640229#L674-44 is_transmit4_triggered_~__retres1~4#1 := 0; 3640225#L685-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3640224#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3640222#L1529-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 3640221#L1529-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3640219#L693-42 assume !(1 == ~t5_pc~0); 3640217#L693-44 is_transmit5_triggered_~__retres1~5#1 := 0; 3640214#L704-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3640212#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 3640210#L1537-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 3636873#L1537-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3613426#L712-42 assume !(1 == ~t6_pc~0); 3613419#L712-44 is_transmit6_triggered_~__retres1~6#1 := 0; 3613413#L723-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3613407#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 3613401#L1545-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 3613397#L1545-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3573069#L731-42 assume !(1 == ~t7_pc~0); 3573067#L731-44 is_transmit7_triggered_~__retres1~7#1 := 0; 3573063#L742-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3573061#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 3573059#L1553-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 3573057#L1553-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3573054#L750-42 assume !(1 == ~t8_pc~0); 3573052#L750-44 is_transmit8_triggered_~__retres1~8#1 := 0; 3573357#L761-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3573355#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 3573045#L1561-42 assume !(0 != activate_threads_~tmp___7~0#1); 3573042#L1561-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3573040#L769-42 assume !(1 == ~t9_pc~0); 3493224#L769-44 is_transmit9_triggered_~__retres1~9#1 := 0; 3573036#L780-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3573034#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 3573032#L1569-42 assume !(0 != activate_threads_~tmp___8~0#1); 3573030#L1569-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 3573028#L788-42 assume !(1 == ~t10_pc~0); 3573026#L788-44 is_transmit10_triggered_~__retres1~10#1 := 0; 3573022#L799-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 3573020#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 3573018#L1577-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 3573016#L1577-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 3573014#L807-42 assume 1 == ~t11_pc~0; 3573012#L808-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 3573008#L818-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 3573006#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 3573004#L1585-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 3573002#L1585-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 3573000#L826-42 assume !(1 == ~t12_pc~0); 3572998#L826-44 is_transmit12_triggered_~__retres1~12#1 := 0; 3572995#L837-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 3572993#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 3572991#L1593-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 3572989#L1593-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3572987#L1344-3 assume 1 == ~M_E~0;~M_E~0 := 2; 3517810#L1344-5 assume !(1 == ~T1_E~0); 3572982#L1349-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3572980#L1354-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3572978#L1359-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3572976#L1364-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3572974#L1369-3 assume !(1 == ~T6_E~0); 3572972#L1374-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 3572970#L1379-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 3572968#L1384-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 3565575#L1389-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 3572965#L1394-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 3572963#L1399-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 3572961#L1404-3 assume 1 == ~E_M~0;~E_M~0 := 2; 3572959#L1409-3 assume !(1 == ~E_1~0); 3572957#L1414-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3572955#L1419-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3572953#L1424-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3572950#L1429-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3572949#L1434-3 assume 1 == ~E_6~0;~E_6~0 := 2; 3572948#L1439-3 assume 1 == ~E_7~0;~E_7~0 := 2; 3572947#L1444-3 assume 1 == ~E_8~0;~E_8~0 := 2; 3572946#L1449-3 assume !(1 == ~E_9~0); 3572944#L1454-3 assume 1 == ~E_10~0;~E_10~0 := 2; 3572942#L1459-3 assume 1 == ~E_11~0;~E_11~0 := 2; 3572940#L1464-3 assume 1 == ~E_12~0;~E_12~0 := 2; 3570625#L1469-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 3572934#L926-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 3572919#L993-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 3572915#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 3572911#L1834 assume !(0 == start_simulation_~tmp~3#1); 3572907#L1834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 3572789#L926-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 3572775#L993-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 3572769#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 3572761#L1789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3572755#L1796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3572748#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 3572739#L1847 assume !(0 != start_simulation_~tmp___0~1#1); 3572730#L1815-2 [2022-12-13 13:22:54,200 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 13:22:54,201 INFO L85 PathProgramCache]: Analyzing trace with hash 909936000, now seen corresponding path program 1 times [2022-12-13 13:22:54,201 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 13:22:54,201 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [195064181] [2022-12-13 13:22:54,201 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 13:22:54,201 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 13:22:54,210 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 13:22:54,245 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 13:22:54,245 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 13:22:54,246 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [195064181] [2022-12-13 13:22:54,246 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [195064181] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 13:22:54,246 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 13:22:54,246 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 13:22:54,246 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [689379698] [2022-12-13 13:22:54,246 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 13:22:54,246 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 13:22:54,247 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 13:22:54,247 INFO L85 PathProgramCache]: Analyzing trace with hash -1022552991, now seen corresponding path program 1 times [2022-12-13 13:22:54,247 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 13:22:54,247 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1473137510] [2022-12-13 13:22:54,247 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 13:22:54,247 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 13:22:54,254 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 13:22:54,276 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 13:22:54,276 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 13:22:54,276 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1473137510] [2022-12-13 13:22:54,276 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1473137510] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 13:22:54,276 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 13:22:54,277 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 13:22:54,277 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1425950231] [2022-12-13 13:22:54,277 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 13:22:54,277 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 13:22:54,277 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 13:22:54,277 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 13:22:54,278 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 13:22:54,278 INFO L87 Difference]: Start difference. First operand 600419 states and 845734 transitions. cyclomatic complexity: 245347 Second operand has 4 states, 4 states have (on average 37.5) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 13:22:58,291 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 13:22:58,291 INFO L93 Difference]: Finished difference Result 1468018 states and 2054387 transitions. [2022-12-13 13:22:58,291 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1468018 states and 2054387 transitions. [2022-12-13 13:23:03,467 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 1440272 [2022-12-13 13:23:06,370 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1468018 states to 1468018 states and 2054387 transitions. [2022-12-13 13:23:06,370 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1468018 [2022-12-13 13:23:06,945 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1468018 [2022-12-13 13:23:06,946 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1468018 states and 2054387 transitions. [2022-12-13 13:23:07,561 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 13:23:07,561 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1468018 states and 2054387 transitions. [2022-12-13 13:23:08,222 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1468018 states and 2054387 transitions. [2022-12-13 13:23:16,227 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1468018 to 1169570. [2022-12-13 13:23:16,722 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1169570 states, 1169570 states have (on average 1.403294373145686) internal successors, (1641251), 1169569 states have internal predecessors, (1641251), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 13:23:19,647 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1169570 states to 1169570 states and 1641251 transitions. [2022-12-13 13:23:19,648 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1169570 states and 1641251 transitions. [2022-12-13 13:23:19,648 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 13:23:19,648 INFO L428 stractBuchiCegarLoop]: Abstraction has 1169570 states and 1641251 transitions. [2022-12-13 13:23:19,648 INFO L335 stractBuchiCegarLoop]: ======== Iteration 26 ============ [2022-12-13 13:23:19,648 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1169570 states and 1641251 transitions.