./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/transmitter.04.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 2329fc70 Calling Ultimate with: /usr/lib/jvm/java-1.11.0-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d951f68a-5c6f-42d8-aa18-e8b3628bcfb9/bin/uautomizer-uyxdKDjOR8/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d951f68a-5c6f-42d8-aa18-e8b3628bcfb9/bin/uautomizer-uyxdKDjOR8/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d951f68a-5c6f-42d8-aa18-e8b3628bcfb9/bin/uautomizer-uyxdKDjOR8/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d951f68a-5c6f-42d8-aa18-e8b3628bcfb9/bin/uautomizer-uyxdKDjOR8/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/transmitter.04.cil.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d951f68a-5c6f-42d8-aa18-e8b3628bcfb9/bin/uautomizer-uyxdKDjOR8/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d951f68a-5c6f-42d8-aa18-e8b3628bcfb9/bin/uautomizer-uyxdKDjOR8 --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 1de07d37d630bd073064bf436fb9512b72ab982b0eaf3fcb1582f689c57482fa --- Real Ultimate output --- [0.001s][warning][os,container] Duplicate cpuset controllers detected. Picking /sys/fs/cgroup/cpuset, skipping /sys/fs/cgroup/cpuset. This is Ultimate 0.2.2-dev-2329fc7 [2022-12-13 21:03:27,869 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-12-13 21:03:27,871 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-12-13 21:03:27,890 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-12-13 21:03:27,890 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-12-13 21:03:27,891 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-12-13 21:03:27,892 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-12-13 21:03:27,894 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-12-13 21:03:27,895 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-12-13 21:03:27,896 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-12-13 21:03:27,897 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-12-13 21:03:27,898 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-12-13 21:03:27,898 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-12-13 21:03:27,899 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-12-13 21:03:27,900 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-12-13 21:03:27,901 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-12-13 21:03:27,902 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-12-13 21:03:27,903 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-12-13 21:03:27,905 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-12-13 21:03:27,906 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-12-13 21:03:27,908 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-12-13 21:03:27,909 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-12-13 21:03:27,910 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-12-13 21:03:27,911 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-12-13 21:03:27,915 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-12-13 21:03:27,915 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-12-13 21:03:27,915 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-12-13 21:03:27,916 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-12-13 21:03:27,917 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-12-13 21:03:27,918 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-12-13 21:03:27,918 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-12-13 21:03:27,919 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-12-13 21:03:27,919 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-12-13 21:03:27,920 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-12-13 21:03:27,921 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-12-13 21:03:27,921 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-12-13 21:03:27,922 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-12-13 21:03:27,922 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-12-13 21:03:27,922 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-12-13 21:03:27,923 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-12-13 21:03:27,924 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-12-13 21:03:27,925 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d951f68a-5c6f-42d8-aa18-e8b3628bcfb9/bin/uautomizer-uyxdKDjOR8/config/svcomp-Termination-32bit-Automizer_Default.epf [2022-12-13 21:03:27,946 INFO L113 SettingsManager]: Loading preferences was successful [2022-12-13 21:03:27,946 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-12-13 21:03:27,946 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-12-13 21:03:27,947 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-12-13 21:03:27,948 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-12-13 21:03:27,948 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-12-13 21:03:27,948 INFO L138 SettingsManager]: * Use SBE=true [2022-12-13 21:03:27,948 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2022-12-13 21:03:27,949 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2022-12-13 21:03:27,949 INFO L138 SettingsManager]: * Use old map elimination=false [2022-12-13 21:03:27,949 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2022-12-13 21:03:27,949 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2022-12-13 21:03:27,949 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2022-12-13 21:03:27,949 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-12-13 21:03:27,950 INFO L138 SettingsManager]: * sizeof long=4 [2022-12-13 21:03:27,950 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2022-12-13 21:03:27,950 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-12-13 21:03:27,950 INFO L138 SettingsManager]: * sizeof POINTER=4 [2022-12-13 21:03:27,950 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-12-13 21:03:27,951 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2022-12-13 21:03:27,951 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2022-12-13 21:03:27,951 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2022-12-13 21:03:27,951 INFO L138 SettingsManager]: * sizeof long double=12 [2022-12-13 21:03:27,951 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-12-13 21:03:27,951 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2022-12-13 21:03:27,952 INFO L138 SettingsManager]: * Use constant arrays=true [2022-12-13 21:03:27,952 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2022-12-13 21:03:27,952 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-12-13 21:03:27,952 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-12-13 21:03:27,953 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-12-13 21:03:27,953 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-12-13 21:03:27,954 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-12-13 21:03:27,954 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d951f68a-5c6f-42d8-aa18-e8b3628bcfb9/bin/uautomizer-uyxdKDjOR8/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d951f68a-5c6f-42d8-aa18-e8b3628bcfb9/bin/uautomizer-uyxdKDjOR8 Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 1de07d37d630bd073064bf436fb9512b72ab982b0eaf3fcb1582f689c57482fa [2022-12-13 21:03:28,152 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-12-13 21:03:28,170 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-12-13 21:03:28,172 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-12-13 21:03:28,173 INFO L271 PluginConnector]: Initializing CDTParser... [2022-12-13 21:03:28,173 INFO L275 PluginConnector]: CDTParser initialized [2022-12-13 21:03:28,174 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d951f68a-5c6f-42d8-aa18-e8b3628bcfb9/bin/uautomizer-uyxdKDjOR8/../../sv-benchmarks/c/systemc/transmitter.04.cil.c [2022-12-13 21:03:30,659 INFO L500 CDTParser]: Created temporary CDT project at NULL [2022-12-13 21:03:30,822 INFO L351 CDTParser]: Found 1 translation units. [2022-12-13 21:03:30,823 INFO L172 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d951f68a-5c6f-42d8-aa18-e8b3628bcfb9/sv-benchmarks/c/systemc/transmitter.04.cil.c [2022-12-13 21:03:30,830 INFO L394 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d951f68a-5c6f-42d8-aa18-e8b3628bcfb9/bin/uautomizer-uyxdKDjOR8/data/ff3e7772d/b705ac1e39704928a6518e48cc742b0f/FLAG05e3631ac [2022-12-13 21:03:31,234 INFO L402 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d951f68a-5c6f-42d8-aa18-e8b3628bcfb9/bin/uautomizer-uyxdKDjOR8/data/ff3e7772d/b705ac1e39704928a6518e48cc742b0f [2022-12-13 21:03:31,236 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-12-13 21:03:31,237 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-12-13 21:03:31,238 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-12-13 21:03:31,238 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-12-13 21:03:31,241 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-12-13 21:03:31,242 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.12 09:03:31" (1/1) ... [2022-12-13 21:03:31,243 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@29c43c95 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 09:03:31, skipping insertion in model container [2022-12-13 21:03:31,243 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.12 09:03:31" (1/1) ... [2022-12-13 21:03:31,249 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-12-13 21:03:31,274 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-12-13 21:03:31,378 WARN L237 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d951f68a-5c6f-42d8-aa18-e8b3628bcfb9/sv-benchmarks/c/systemc/transmitter.04.cil.c[706,719] [2022-12-13 21:03:31,427 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-12-13 21:03:31,437 INFO L203 MainTranslator]: Completed pre-run [2022-12-13 21:03:31,445 WARN L237 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d951f68a-5c6f-42d8-aa18-e8b3628bcfb9/sv-benchmarks/c/systemc/transmitter.04.cil.c[706,719] [2022-12-13 21:03:31,469 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-12-13 21:03:31,480 INFO L208 MainTranslator]: Completed translation [2022-12-13 21:03:31,481 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 09:03:31 WrapperNode [2022-12-13 21:03:31,481 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-12-13 21:03:31,482 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-12-13 21:03:31,482 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-12-13 21:03:31,482 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-12-13 21:03:31,487 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 09:03:31" (1/1) ... [2022-12-13 21:03:31,494 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 09:03:31" (1/1) ... [2022-12-13 21:03:31,533 INFO L138 Inliner]: procedures = 36, calls = 42, calls flagged for inlining = 37, calls inlined = 70, statements flattened = 966 [2022-12-13 21:03:31,534 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-12-13 21:03:31,534 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-12-13 21:03:31,534 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-12-13 21:03:31,535 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-12-13 21:03:31,545 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 09:03:31" (1/1) ... [2022-12-13 21:03:31,545 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 09:03:31" (1/1) ... [2022-12-13 21:03:31,548 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 09:03:31" (1/1) ... [2022-12-13 21:03:31,549 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 09:03:31" (1/1) ... [2022-12-13 21:03:31,560 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 09:03:31" (1/1) ... [2022-12-13 21:03:31,570 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 09:03:31" (1/1) ... [2022-12-13 21:03:31,572 INFO L185 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 09:03:31" (1/1) ... [2022-12-13 21:03:31,575 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 09:03:31" (1/1) ... [2022-12-13 21:03:31,579 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-12-13 21:03:31,580 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-12-13 21:03:31,580 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-12-13 21:03:31,580 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-12-13 21:03:31,581 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 09:03:31" (1/1) ... [2022-12-13 21:03:31,587 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-12-13 21:03:31,599 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d951f68a-5c6f-42d8-aa18-e8b3628bcfb9/bin/uautomizer-uyxdKDjOR8/z3 [2022-12-13 21:03:31,610 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d951f68a-5c6f-42d8-aa18-e8b3628bcfb9/bin/uautomizer-uyxdKDjOR8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-12-13 21:03:31,612 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d951f68a-5c6f-42d8-aa18-e8b3628bcfb9/bin/uautomizer-uyxdKDjOR8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2022-12-13 21:03:31,642 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-12-13 21:03:31,642 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-12-13 21:03:31,643 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-12-13 21:03:31,643 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-12-13 21:03:31,705 INFO L235 CfgBuilder]: Building ICFG [2022-12-13 21:03:31,707 INFO L261 CfgBuilder]: Building CFG for each procedure with an implementation [2022-12-13 21:03:32,322 INFO L276 CfgBuilder]: Performing block encoding [2022-12-13 21:03:32,332 INFO L295 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-12-13 21:03:32,332 INFO L300 CfgBuilder]: Removed 8 assume(true) statements. [2022-12-13 21:03:32,334 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.12 09:03:32 BoogieIcfgContainer [2022-12-13 21:03:32,335 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-12-13 21:03:32,335 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2022-12-13 21:03:32,336 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2022-12-13 21:03:32,338 INFO L275 PluginConnector]: BuchiAutomizer initialized [2022-12-13 21:03:32,339 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-12-13 21:03:32,339 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 13.12 09:03:31" (1/3) ... [2022-12-13 21:03:32,339 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@61254fc and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 13.12 09:03:32, skipping insertion in model container [2022-12-13 21:03:32,340 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-12-13 21:03:32,340 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 09:03:31" (2/3) ... [2022-12-13 21:03:32,340 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@61254fc and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 13.12 09:03:32, skipping insertion in model container [2022-12-13 21:03:32,340 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-12-13 21:03:32,340 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.12 09:03:32" (3/3) ... [2022-12-13 21:03:32,341 INFO L332 chiAutomizerObserver]: Analyzing ICFG transmitter.04.cil.c [2022-12-13 21:03:32,391 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2022-12-13 21:03:32,391 INFO L304 stractBuchiCegarLoop]: Hoare is false [2022-12-13 21:03:32,391 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2022-12-13 21:03:32,391 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2022-12-13 21:03:32,391 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2022-12-13 21:03:32,391 INFO L308 stractBuchiCegarLoop]: Difference is false [2022-12-13 21:03:32,391 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2022-12-13 21:03:32,391 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2022-12-13 21:03:32,396 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 391 states, 390 states have (on average 1.5384615384615385) internal successors, (600), 390 states have internal predecessors, (600), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 21:03:32,429 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 322 [2022-12-13 21:03:32,430 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 21:03:32,430 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 21:03:32,438 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 21:03:32,439 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 21:03:32,439 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2022-12-13 21:03:32,440 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 391 states, 390 states have (on average 1.5384615384615385) internal successors, (600), 390 states have internal predecessors, (600), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 21:03:32,446 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 322 [2022-12-13 21:03:32,446 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 21:03:32,446 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 21:03:32,448 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 21:03:32,448 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 21:03:32,454 INFO L748 eck$LassoCheckResult]: Stem: 121#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 326#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 183#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 322#update_channels_returnLabel#1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 57#L341true assume !(1 == ~m_i~0);~m_st~0 := 2; 363#L341-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 212#L346-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 118#L351-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 22#L356-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 109#L361-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 32#L502true assume !(0 == ~M_E~0); 86#L502-2true assume 0 == ~T1_E~0;~T1_E~0 := 1; 16#L507-1true assume !(0 == ~T2_E~0); 58#L512-1true assume !(0 == ~T3_E~0); 312#L517-1true assume !(0 == ~T4_E~0); 10#L522-1true assume !(0 == ~E_1~0); 278#L527-1true assume !(0 == ~E_2~0); 123#L532-1true assume !(0 == ~E_3~0); 356#L537-1true assume !(0 == ~E_4~0); 136#L542-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 117#L238true assume 1 == ~m_pc~0; 317#L239true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 191#L249true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 103#is_master_triggered_returnLabel#1true activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 102#L615true assume !(0 != activate_threads_~tmp~1#1); 198#L615-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 92#L257true assume 1 == ~t1_pc~0; 318#L258true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 114#L268true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 31#is_transmit1_triggered_returnLabel#1true activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 188#L623true assume !(0 != activate_threads_~tmp___0~0#1); 23#L623-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 187#L276true assume !(1 == ~t2_pc~0); 280#L276-2true is_transmit2_triggered_~__retres1~2#1 := 0; 337#L287true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 186#is_transmit2_triggered_returnLabel#1true activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 341#L631true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 354#L631-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 101#L295true assume 1 == ~t3_pc~0; 37#L296true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 94#L306true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8#is_transmit3_triggered_returnLabel#1true activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 320#L639true assume !(0 != activate_threads_~tmp___2~0#1); 315#L639-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 372#L314true assume !(1 == ~t4_pc~0); 345#L314-2true is_transmit4_triggered_~__retres1~4#1 := 0; 143#L325true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 52#is_transmit4_triggered_returnLabel#1true activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 91#L647true assume !(0 != activate_threads_~tmp___3~0#1); 274#L647-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 386#L555true assume !(1 == ~M_E~0); 39#L555-2true assume !(1 == ~T1_E~0); 365#L560-1true assume !(1 == ~T2_E~0); 11#L565-1true assume !(1 == ~T3_E~0); 96#L570-1true assume !(1 == ~T4_E~0); 219#L575-1true assume !(1 == ~E_1~0); 292#L580-1true assume !(1 == ~E_2~0); 131#L585-1true assume 1 == ~E_3~0;~E_3~0 := 2; 29#L590-1true assume !(1 == ~E_4~0); 26#L595-1true assume { :end_inline_reset_delta_events } true; 175#L776-2true [2022-12-13 21:03:32,455 INFO L750 eck$LassoCheckResult]: Loop: 175#L776-2true assume !false; 18#L777true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 119#L477true assume !true; 55#eval_returnLabel#1true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 286#update_channels_returnLabel#2true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 79#L502-3true assume !(0 == ~M_E~0); 299#L502-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 310#L507-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 56#L512-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 391#L517-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 49#L522-3true assume 0 == ~E_1~0;~E_1~0 := 1; 93#L527-3true assume 0 == ~E_2~0;~E_2~0 := 1; 142#L532-3true assume 0 == ~E_3~0;~E_3~0 := 1; 266#L537-3true assume !(0 == ~E_4~0); 61#L542-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 87#L238-15true assume !(1 == ~m_pc~0); 115#L238-17true is_master_triggered_~__retres1~0#1 := 0; 307#L249-5true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 51#is_master_triggered_returnLabel#6true activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 227#L615-15true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 155#L615-17true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 210#L257-15true assume !(1 == ~t1_pc~0); 75#L257-17true is_transmit1_triggered_~__retres1~1#1 := 0; 334#L268-5true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 246#is_transmit1_triggered_returnLabel#6true activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 303#L623-15true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 311#L623-17true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 366#L276-15true assume !(1 == ~t2_pc~0); 376#L276-17true is_transmit2_triggered_~__retres1~2#1 := 0; 248#L287-5true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 362#is_transmit2_triggered_returnLabel#6true activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 179#L631-15true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 287#L631-17true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 24#L295-15true assume !(1 == ~t3_pc~0); 172#L295-17true is_transmit3_triggered_~__retres1~3#1 := 0; 331#L306-5true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 339#is_transmit3_triggered_returnLabel#6true activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 162#L639-15true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 124#L639-17true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 161#L314-15true assume 1 == ~t4_pc~0; 282#L315-5true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 181#L325-5true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 304#is_transmit4_triggered_returnLabel#6true activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 314#L647-15true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 122#L647-17true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 85#L555-3true assume 1 == ~M_E~0;~M_E~0 := 2; 194#L555-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 42#L560-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 305#L565-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 346#L570-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 288#L575-3true assume 1 == ~E_1~0;~E_1~0 := 2; 190#L580-3true assume !(1 == ~E_2~0); 389#L585-3true assume 1 == ~E_3~0;~E_3~0 := 2; 234#L590-3true assume 1 == ~E_4~0;~E_4~0 := 2; 273#L595-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 163#L374-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 74#L401-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 160#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 100#L795true assume !(0 == start_simulation_~tmp~3#1); 316#L795-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 111#L374-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 270#L401-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 30#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 168#L750true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 40#L757true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 295#stop_simulation_returnLabel#1true start_simulation_#t~ret17#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 277#L808true assume !(0 != start_simulation_~tmp___0~1#1); 175#L776-2true [2022-12-13 21:03:32,459 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 21:03:32,460 INFO L85 PathProgramCache]: Analyzing trace with hash 1110077256, now seen corresponding path program 1 times [2022-12-13 21:03:32,466 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 21:03:32,467 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [241444791] [2022-12-13 21:03:32,467 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 21:03:32,468 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 21:03:32,535 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 21:03:32,609 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 21:03:32,609 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 21:03:32,610 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [241444791] [2022-12-13 21:03:32,610 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [241444791] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 21:03:32,610 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 21:03:32,610 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 21:03:32,611 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [879114229] [2022-12-13 21:03:32,612 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 21:03:32,615 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 21:03:32,616 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 21:03:32,616 INFO L85 PathProgramCache]: Analyzing trace with hash -37682228, now seen corresponding path program 1 times [2022-12-13 21:03:32,616 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 21:03:32,616 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [846874809] [2022-12-13 21:03:32,616 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 21:03:32,616 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 21:03:32,625 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 21:03:32,642 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 21:03:32,642 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 21:03:32,642 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [846874809] [2022-12-13 21:03:32,642 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [846874809] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 21:03:32,642 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 21:03:32,643 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-12-13 21:03:32,643 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [609122132] [2022-12-13 21:03:32,643 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 21:03:32,644 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 21:03:32,645 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 21:03:32,670 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 21:03:32,670 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 21:03:32,673 INFO L87 Difference]: Start difference. First operand has 391 states, 390 states have (on average 1.5384615384615385) internal successors, (600), 390 states have internal predecessors, (600), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 20.0) internal successors, (60), 3 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 21:03:32,707 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 21:03:32,707 INFO L93 Difference]: Finished difference Result 390 states and 581 transitions. [2022-12-13 21:03:32,708 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 390 states and 581 transitions. [2022-12-13 21:03:32,711 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 319 [2022-12-13 21:03:32,715 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 390 states to 384 states and 575 transitions. [2022-12-13 21:03:32,716 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 384 [2022-12-13 21:03:32,717 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 384 [2022-12-13 21:03:32,717 INFO L73 IsDeterministic]: Start isDeterministic. Operand 384 states and 575 transitions. [2022-12-13 21:03:32,719 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 21:03:32,719 INFO L218 hiAutomatonCegarLoop]: Abstraction has 384 states and 575 transitions. [2022-12-13 21:03:32,732 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 384 states and 575 transitions. [2022-12-13 21:03:32,746 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 384 to 384. [2022-12-13 21:03:32,748 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 384 states, 384 states have (on average 1.4973958333333333) internal successors, (575), 383 states have internal predecessors, (575), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 21:03:32,749 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 384 states to 384 states and 575 transitions. [2022-12-13 21:03:32,750 INFO L240 hiAutomatonCegarLoop]: Abstraction has 384 states and 575 transitions. [2022-12-13 21:03:32,751 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 21:03:32,753 INFO L428 stractBuchiCegarLoop]: Abstraction has 384 states and 575 transitions. [2022-12-13 21:03:32,754 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2022-12-13 21:03:32,754 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 384 states and 575 transitions. [2022-12-13 21:03:32,755 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 319 [2022-12-13 21:03:32,755 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 21:03:32,755 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 21:03:32,756 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 21:03:32,757 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 21:03:32,757 INFO L748 eck$LassoCheckResult]: Stem: 1133#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 1134#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 1143#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1141#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1038#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 1039#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 877#L346-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 878#L351-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 888#L356-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 889#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 934#L502 assume !(0 == ~M_E~0); 935#L502-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 865#L507-1 assume !(0 == ~T2_E~0); 866#L512-1 assume !(0 == ~T3_E~0); 1040#L517-1 assume !(0 == ~T4_E~0); 848#L522-1 assume !(0 == ~E_1~0); 849#L527-1 assume !(0 == ~E_2~0); 1054#L532-1 assume !(0 == ~E_3~0); 1137#L537-1 assume !(0 == ~E_4~0); 1149#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1127#L238 assume 1 == ~m_pc~0; 1128#L239 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 807#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 808#is_master_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 1106#L615 assume !(0 != activate_threads_~tmp~1#1); 830#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 831#L257 assume 1 == ~t1_pc~0; 1091#L258 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 943#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 923#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 795#L623 assume !(0 != activate_threads_~tmp___0~0#1); 796#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 790#L276 assume !(1 == ~t2_pc~0); 791#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1064#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1155#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1161#L631 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1162#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1105#L295 assume 1 == ~t3_pc~0; 958#L296 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 905#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 832#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 833#L639 assume !(0 != activate_threads_~tmp___2~0#1); 1130#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1131#L314 assume !(1 == ~t4_pc~0); 948#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 947#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1021#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1022#L647 assume !(0 != activate_threads_~tmp___3~0#1); 1046#L647-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1047#L555 assume !(1 == ~M_E~0); 964#L555-2 assume !(1 == ~T1_E~0); 965#L560-1 assume !(1 == ~T2_E~0); 850#L565-1 assume !(1 == ~T3_E~0); 851#L570-1 assume !(1 == ~T4_E~0); 918#L575-1 assume !(1 == ~E_1~0); 919#L580-1 assume !(1 == ~E_2~0); 1090#L585-1 assume 1 == ~E_3~0;~E_3~0 := 2; 920#L590-1 assume !(1 == ~E_4~0); 906#L595-1 assume { :end_inline_reset_delta_events } true; 907#L776-2 [2022-12-13 21:03:32,757 INFO L750 eck$LassoCheckResult]: Loop: 907#L776-2 assume !false; 879#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 880#L477 assume !false; 974#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 975#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 815#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 816#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 834#L416 assume !(0 != eval_~tmp~0#1); 855#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1026#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1078#L502-3 assume !(0 == ~M_E~0); 1079#L502-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1096#L507-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1027#L512-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1028#L517-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1008#L522-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1009#L527-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1092#L532-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1034#L537-3 assume !(0 == ~E_4~0); 1035#L542-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1042#L238-15 assume 1 == ~m_pc~0; 835#L239-5 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 836#L249-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1018#is_master_triggered_returnLabel#6 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 940#L615-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 941#L615-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 872#L257-15 assume !(1 == ~t1_pc~0); 873#L257-17 is_transmit1_triggered_~__retres1~1#1 := 0; 1074#L268-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 986#is_transmit1_triggered_returnLabel#6 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 987#L623-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1107#L623-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1121#L276-15 assume 1 == ~t2_pc~0; 1005#L277-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 993#L287-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 994#is_transmit2_triggered_returnLabel#6 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1170#L631-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1085#L631-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 901#L295-15 assume !(1 == ~t3_pc~0); 902#L295-17 is_transmit3_triggered_~__retres1~3#1 := 0; 1104#L306-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1148#is_transmit3_triggered_returnLabel#6 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1156#L639-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1139#L639-17 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1140#L314-15 assume !(1 == ~t4_pc~0); 1072#L314-17 is_transmit4_triggered_~__retres1~4#1 := 0; 1071#L325-5 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1109#is_transmit4_triggered_returnLabel#6 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1110#L647-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1126#L647-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1084#L555-3 assume 1 == ~M_E~0;~M_E~0 := 2; 809#L555-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 810#L560-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 981#L565-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1111#L570-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1086#L575-3 assume 1 == ~E_1~0;~E_1~0 := 2; 799#L580-3 assume !(1 == ~E_2~0); 800#L585-3 assume 1 == ~E_3~0;~E_3~0 := 2; 961#L590-3 assume 1 == ~E_4~0;~E_4~0 := 2; 962#L595-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 1045#L374-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 884#L401-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 1073#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 1101#L795 assume !(0 == start_simulation_~tmp~3#1); 1102#L795-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 1122#L374-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 845#L401-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 916#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 917#L750 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 970#L757 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 971#stop_simulation_returnLabel#1 start_simulation_#t~ret17#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 1052#L808 assume !(0 != start_simulation_~tmp___0~1#1); 907#L776-2 [2022-12-13 21:03:32,757 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 21:03:32,758 INFO L85 PathProgramCache]: Analyzing trace with hash 1069402506, now seen corresponding path program 1 times [2022-12-13 21:03:32,758 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 21:03:32,758 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1265000442] [2022-12-13 21:03:32,758 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 21:03:32,758 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 21:03:32,772 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 21:03:32,819 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 21:03:32,819 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 21:03:32,820 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1265000442] [2022-12-13 21:03:32,820 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1265000442] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 21:03:32,820 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 21:03:32,820 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 21:03:32,820 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1840850657] [2022-12-13 21:03:32,820 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 21:03:32,821 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 21:03:32,821 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 21:03:32,822 INFO L85 PathProgramCache]: Analyzing trace with hash -2012547652, now seen corresponding path program 1 times [2022-12-13 21:03:32,822 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 21:03:32,822 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1790817798] [2022-12-13 21:03:32,822 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 21:03:32,822 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 21:03:32,840 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 21:03:32,893 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 21:03:32,893 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 21:03:32,893 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1790817798] [2022-12-13 21:03:32,893 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1790817798] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 21:03:32,894 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 21:03:32,894 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 21:03:32,894 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1194409342] [2022-12-13 21:03:32,894 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 21:03:32,894 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 21:03:32,895 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 21:03:32,895 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 21:03:32,895 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 21:03:32,895 INFO L87 Difference]: Start difference. First operand 384 states and 575 transitions. cyclomatic complexity: 192 Second operand has 3 states, 3 states have (on average 20.0) internal successors, (60), 3 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 21:03:32,917 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 21:03:32,917 INFO L93 Difference]: Finished difference Result 384 states and 574 transitions. [2022-12-13 21:03:32,917 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 384 states and 574 transitions. [2022-12-13 21:03:32,921 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 319 [2022-12-13 21:03:32,926 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 384 states to 384 states and 574 transitions. [2022-12-13 21:03:32,926 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 384 [2022-12-13 21:03:32,927 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 384 [2022-12-13 21:03:32,927 INFO L73 IsDeterministic]: Start isDeterministic. Operand 384 states and 574 transitions. [2022-12-13 21:03:32,929 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 21:03:32,930 INFO L218 hiAutomatonCegarLoop]: Abstraction has 384 states and 574 transitions. [2022-12-13 21:03:32,931 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 384 states and 574 transitions. [2022-12-13 21:03:32,944 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 384 to 384. [2022-12-13 21:03:32,944 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 384 states, 384 states have (on average 1.4947916666666667) internal successors, (574), 383 states have internal predecessors, (574), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 21:03:32,945 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 384 states to 384 states and 574 transitions. [2022-12-13 21:03:32,945 INFO L240 hiAutomatonCegarLoop]: Abstraction has 384 states and 574 transitions. [2022-12-13 21:03:32,945 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 21:03:32,946 INFO L428 stractBuchiCegarLoop]: Abstraction has 384 states and 574 transitions. [2022-12-13 21:03:32,946 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2022-12-13 21:03:32,946 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 384 states and 574 transitions. [2022-12-13 21:03:32,949 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 319 [2022-12-13 21:03:32,949 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 21:03:32,949 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 21:03:32,950 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 21:03:32,950 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 21:03:32,951 INFO L748 eck$LassoCheckResult]: Stem: 1908#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 1909#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 1917#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1916#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1811#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 1812#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1652#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1653#L351-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1663#L356-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1664#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1709#L502 assume !(0 == ~M_E~0); 1710#L502-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1640#L507-1 assume !(0 == ~T2_E~0); 1641#L512-1 assume !(0 == ~T3_E~0); 1815#L517-1 assume !(0 == ~T4_E~0); 1616#L522-1 assume !(0 == ~E_1~0); 1617#L527-1 assume !(0 == ~E_2~0); 1829#L532-1 assume !(0 == ~E_3~0); 1912#L537-1 assume !(0 == ~E_4~0); 1924#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1902#L238 assume 1 == ~m_pc~0; 1903#L239 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 1578#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1579#is_master_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 1881#L615 assume !(0 != activate_threads_~tmp~1#1); 1601#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1602#L257 assume 1 == ~t1_pc~0; 1866#L258 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1718#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1698#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1570#L623 assume !(0 != activate_threads_~tmp___0~0#1); 1571#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1565#L276 assume !(1 == ~t2_pc~0); 1566#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1838#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1930#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1935#L631 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1936#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1878#L295 assume 1 == ~t3_pc~0; 1733#L296 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1680#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1603#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1604#L639 assume !(0 != activate_threads_~tmp___2~0#1); 1905#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1906#L314 assume !(1 == ~t4_pc~0); 1723#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1722#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1796#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1797#L647 assume !(0 != activate_threads_~tmp___3~0#1); 1821#L647-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1822#L555 assume !(1 == ~M_E~0); 1739#L555-2 assume !(1 == ~T1_E~0); 1740#L560-1 assume !(1 == ~T2_E~0); 1618#L565-1 assume !(1 == ~T3_E~0); 1619#L570-1 assume !(1 == ~T4_E~0); 1691#L575-1 assume !(1 == ~E_1~0); 1692#L580-1 assume !(1 == ~E_2~0); 1865#L585-1 assume 1 == ~E_3~0;~E_3~0 := 2; 1693#L590-1 assume !(1 == ~E_4~0); 1681#L595-1 assume { :end_inline_reset_delta_events } true; 1682#L776-2 [2022-12-13 21:03:32,951 INFO L750 eck$LassoCheckResult]: Loop: 1682#L776-2 assume !false; 1654#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1655#L477 assume !false; 1749#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 1750#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 1590#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 1591#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1605#L416 assume !(0 != eval_~tmp~0#1); 1630#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1801#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1853#L502-3 assume !(0 == ~M_E~0); 1854#L502-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1870#L507-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1802#L512-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1803#L517-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1783#L522-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1784#L527-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1867#L532-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1809#L537-3 assume !(0 == ~E_4~0); 1810#L542-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1817#L238-15 assume 1 == ~m_pc~0; 1610#L239-5 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 1611#L249-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1793#is_master_triggered_returnLabel#6 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 1715#L615-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1716#L615-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1647#L257-15 assume !(1 == ~t1_pc~0); 1648#L257-17 is_transmit1_triggered_~__retres1~1#1 := 0; 1849#L268-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1761#is_transmit1_triggered_returnLabel#6 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1762#L623-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1882#L623-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1896#L276-15 assume 1 == ~t2_pc~0; 1780#L277-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1768#L287-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1769#is_transmit2_triggered_returnLabel#6 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1945#L631-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1860#L631-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1676#L295-15 assume !(1 == ~t3_pc~0); 1677#L295-17 is_transmit3_triggered_~__retres1~3#1 := 0; 1880#L306-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1923#is_transmit3_triggered_returnLabel#6 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1931#L639-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1914#L639-17 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1915#L314-15 assume 1 == ~t4_pc~0; 1845#L315-5 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1846#L325-5 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1884#is_transmit4_triggered_returnLabel#6 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1885#L647-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1901#L647-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1859#L555-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1584#L555-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1585#L560-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1756#L565-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1886#L570-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1861#L575-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1574#L580-3 assume !(1 == ~E_2~0); 1575#L585-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1736#L590-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1737#L595-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 1820#L374-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 1659#L401-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 1848#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 1876#L795 assume !(0 == start_simulation_~tmp~3#1); 1877#L795-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 1897#L374-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 1624#L401-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 1694#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 1695#L750 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1747#L757 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1748#stop_simulation_returnLabel#1 start_simulation_#t~ret17#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 1827#L808 assume !(0 != start_simulation_~tmp___0~1#1); 1682#L776-2 [2022-12-13 21:03:32,952 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 21:03:32,952 INFO L85 PathProgramCache]: Analyzing trace with hash 193383500, now seen corresponding path program 1 times [2022-12-13 21:03:32,952 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 21:03:32,952 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1072729941] [2022-12-13 21:03:32,952 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 21:03:32,952 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 21:03:32,962 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 21:03:32,984 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 21:03:32,984 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 21:03:32,984 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1072729941] [2022-12-13 21:03:32,984 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1072729941] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 21:03:32,985 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 21:03:32,985 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 21:03:32,985 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1988470050] [2022-12-13 21:03:32,985 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 21:03:32,985 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 21:03:32,986 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 21:03:32,986 INFO L85 PathProgramCache]: Analyzing trace with hash -1704108643, now seen corresponding path program 1 times [2022-12-13 21:03:32,986 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 21:03:32,986 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1108205874] [2022-12-13 21:03:32,986 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 21:03:32,987 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 21:03:32,999 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 21:03:33,036 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 21:03:33,036 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 21:03:33,037 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1108205874] [2022-12-13 21:03:33,037 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1108205874] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 21:03:33,037 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 21:03:33,037 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 21:03:33,037 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [956464566] [2022-12-13 21:03:33,037 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 21:03:33,038 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 21:03:33,038 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 21:03:33,038 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 21:03:33,038 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 21:03:33,039 INFO L87 Difference]: Start difference. First operand 384 states and 574 transitions. cyclomatic complexity: 191 Second operand has 3 states, 3 states have (on average 20.0) internal successors, (60), 3 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 21:03:33,050 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 21:03:33,051 INFO L93 Difference]: Finished difference Result 384 states and 573 transitions. [2022-12-13 21:03:33,051 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 384 states and 573 transitions. [2022-12-13 21:03:33,054 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 319 [2022-12-13 21:03:33,056 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 384 states to 384 states and 573 transitions. [2022-12-13 21:03:33,056 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 384 [2022-12-13 21:03:33,057 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 384 [2022-12-13 21:03:33,057 INFO L73 IsDeterministic]: Start isDeterministic. Operand 384 states and 573 transitions. [2022-12-13 21:03:33,058 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 21:03:33,058 INFO L218 hiAutomatonCegarLoop]: Abstraction has 384 states and 573 transitions. [2022-12-13 21:03:33,058 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 384 states and 573 transitions. [2022-12-13 21:03:33,064 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 384 to 384. [2022-12-13 21:03:33,065 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 384 states, 384 states have (on average 1.4921875) internal successors, (573), 383 states have internal predecessors, (573), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 21:03:33,066 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 384 states to 384 states and 573 transitions. [2022-12-13 21:03:33,066 INFO L240 hiAutomatonCegarLoop]: Abstraction has 384 states and 573 transitions. [2022-12-13 21:03:33,066 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 21:03:33,067 INFO L428 stractBuchiCegarLoop]: Abstraction has 384 states and 573 transitions. [2022-12-13 21:03:33,067 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2022-12-13 21:03:33,067 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 384 states and 573 transitions. [2022-12-13 21:03:33,069 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 319 [2022-12-13 21:03:33,070 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 21:03:33,070 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 21:03:33,071 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 21:03:33,071 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 21:03:33,071 INFO L748 eck$LassoCheckResult]: Stem: 2683#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 2684#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 2693#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2691#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2588#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 2589#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2427#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2428#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2438#L356-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2439#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2484#L502 assume !(0 == ~M_E~0); 2485#L502-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2418#L507-1 assume !(0 == ~T2_E~0); 2419#L512-1 assume !(0 == ~T3_E~0); 2590#L517-1 assume !(0 == ~T4_E~0); 2398#L522-1 assume !(0 == ~E_1~0); 2399#L527-1 assume !(0 == ~E_2~0); 2604#L532-1 assume !(0 == ~E_3~0); 2687#L537-1 assume !(0 == ~E_4~0); 2699#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2677#L238 assume 1 == ~m_pc~0; 2678#L239 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 2357#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2358#is_master_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 2656#L615 assume !(0 != activate_threads_~tmp~1#1); 2380#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2381#L257 assume 1 == ~t1_pc~0; 2641#L258 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2493#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2473#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 2345#L623 assume !(0 != activate_threads_~tmp___0~0#1); 2346#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2340#L276 assume !(1 == ~t2_pc~0); 2341#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2616#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2705#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 2711#L631 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2712#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2655#L295 assume 1 == ~t3_pc~0; 2508#L296 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 2455#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2382#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2383#L639 assume !(0 != activate_threads_~tmp___2~0#1); 2680#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2681#L314 assume !(1 == ~t4_pc~0); 2498#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 2497#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2571#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2572#L647 assume !(0 != activate_threads_~tmp___3~0#1); 2596#L647-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2597#L555 assume !(1 == ~M_E~0); 2514#L555-2 assume !(1 == ~T1_E~0); 2515#L560-1 assume !(1 == ~T2_E~0); 2400#L565-1 assume !(1 == ~T3_E~0); 2401#L570-1 assume !(1 == ~T4_E~0); 2468#L575-1 assume !(1 == ~E_1~0); 2469#L580-1 assume !(1 == ~E_2~0); 2640#L585-1 assume 1 == ~E_3~0;~E_3~0 := 2; 2470#L590-1 assume !(1 == ~E_4~0); 2456#L595-1 assume { :end_inline_reset_delta_events } true; 2457#L776-2 [2022-12-13 21:03:33,072 INFO L750 eck$LassoCheckResult]: Loop: 2457#L776-2 assume !false; 2429#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2430#L477 assume !false; 2524#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 2525#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 2365#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 2366#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 2384#L416 assume !(0 != eval_~tmp~0#1); 2405#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2576#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2628#L502-3 assume !(0 == ~M_E~0); 2629#L502-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2646#L507-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2577#L512-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2578#L517-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2558#L522-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2559#L527-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2642#L532-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2584#L537-3 assume !(0 == ~E_4~0); 2585#L542-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2592#L238-15 assume 1 == ~m_pc~0; 2385#L239-5 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 2386#L249-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2568#is_master_triggered_returnLabel#6 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 2490#L615-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2491#L615-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2422#L257-15 assume !(1 == ~t1_pc~0); 2423#L257-17 is_transmit1_triggered_~__retres1~1#1 := 0; 2624#L268-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2536#is_transmit1_triggered_returnLabel#6 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 2537#L623-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2657#L623-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2671#L276-15 assume 1 == ~t2_pc~0; 2555#L277-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2543#L287-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2544#is_transmit2_triggered_returnLabel#6 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 2720#L631-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2635#L631-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2451#L295-15 assume !(1 == ~t3_pc~0); 2452#L295-17 is_transmit3_triggered_~__retres1~3#1 := 0; 2654#L306-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2698#is_transmit3_triggered_returnLabel#6 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2706#L639-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2689#L639-17 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2690#L314-15 assume 1 == ~t4_pc~0; 2620#L315-5 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2621#L325-5 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2659#is_transmit4_triggered_returnLabel#6 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2660#L647-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 2676#L647-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2634#L555-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2359#L555-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2360#L560-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2531#L565-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2661#L570-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2636#L575-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2349#L580-3 assume !(1 == ~E_2~0); 2350#L585-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2511#L590-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2512#L595-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 2595#L374-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 2434#L401-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 2623#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 2651#L795 assume !(0 == start_simulation_~tmp~3#1); 2652#L795-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 2672#L374-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 2395#L401-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 2466#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 2467#L750 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2520#L757 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2521#stop_simulation_returnLabel#1 start_simulation_#t~ret17#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 2602#L808 assume !(0 != start_simulation_~tmp___0~1#1); 2457#L776-2 [2022-12-13 21:03:33,072 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 21:03:33,073 INFO L85 PathProgramCache]: Analyzing trace with hash -250517174, now seen corresponding path program 1 times [2022-12-13 21:03:33,073 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 21:03:33,073 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1776205077] [2022-12-13 21:03:33,073 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 21:03:33,073 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 21:03:33,082 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 21:03:33,102 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 21:03:33,103 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 21:03:33,103 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1776205077] [2022-12-13 21:03:33,103 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1776205077] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 21:03:33,103 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 21:03:33,103 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 21:03:33,103 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [625067318] [2022-12-13 21:03:33,104 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 21:03:33,104 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 21:03:33,104 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 21:03:33,104 INFO L85 PathProgramCache]: Analyzing trace with hash -1704108643, now seen corresponding path program 2 times [2022-12-13 21:03:33,105 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 21:03:33,105 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1469348430] [2022-12-13 21:03:33,105 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 21:03:33,105 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 21:03:33,115 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 21:03:33,143 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 21:03:33,143 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 21:03:33,144 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1469348430] [2022-12-13 21:03:33,144 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1469348430] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 21:03:33,144 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 21:03:33,144 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 21:03:33,144 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2060115837] [2022-12-13 21:03:33,144 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 21:03:33,145 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 21:03:33,145 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 21:03:33,145 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 21:03:33,145 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 21:03:33,145 INFO L87 Difference]: Start difference. First operand 384 states and 573 transitions. cyclomatic complexity: 190 Second operand has 3 states, 3 states have (on average 20.0) internal successors, (60), 3 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 21:03:33,154 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 21:03:33,154 INFO L93 Difference]: Finished difference Result 384 states and 572 transitions. [2022-12-13 21:03:33,154 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 384 states and 572 transitions. [2022-12-13 21:03:33,168 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 319 [2022-12-13 21:03:33,170 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 384 states to 384 states and 572 transitions. [2022-12-13 21:03:33,170 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 384 [2022-12-13 21:03:33,171 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 384 [2022-12-13 21:03:33,171 INFO L73 IsDeterministic]: Start isDeterministic. Operand 384 states and 572 transitions. [2022-12-13 21:03:33,171 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 21:03:33,171 INFO L218 hiAutomatonCegarLoop]: Abstraction has 384 states and 572 transitions. [2022-12-13 21:03:33,172 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 384 states and 572 transitions. [2022-12-13 21:03:33,176 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 384 to 384. [2022-12-13 21:03:33,177 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 384 states, 384 states have (on average 1.4895833333333333) internal successors, (572), 383 states have internal predecessors, (572), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 21:03:33,179 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 384 states to 384 states and 572 transitions. [2022-12-13 21:03:33,179 INFO L240 hiAutomatonCegarLoop]: Abstraction has 384 states and 572 transitions. [2022-12-13 21:03:33,179 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 21:03:33,180 INFO L428 stractBuchiCegarLoop]: Abstraction has 384 states and 572 transitions. [2022-12-13 21:03:33,180 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2022-12-13 21:03:33,180 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 384 states and 572 transitions. [2022-12-13 21:03:33,182 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 319 [2022-12-13 21:03:33,182 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 21:03:33,182 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 21:03:33,184 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 21:03:33,184 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 21:03:33,184 INFO L748 eck$LassoCheckResult]: Stem: 3458#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 3459#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 3467#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3466#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3363#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 3364#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3202#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3203#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3213#L356-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 3214#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3259#L502 assume !(0 == ~M_E~0); 3260#L502-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3190#L507-1 assume !(0 == ~T2_E~0); 3191#L512-1 assume !(0 == ~T3_E~0); 3365#L517-1 assume !(0 == ~T4_E~0); 3168#L522-1 assume !(0 == ~E_1~0); 3169#L527-1 assume !(0 == ~E_2~0); 3379#L532-1 assume !(0 == ~E_3~0); 3462#L537-1 assume !(0 == ~E_4~0); 3474#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3452#L238 assume 1 == ~m_pc~0; 3453#L239 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 3128#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3129#is_master_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 3431#L615 assume !(0 != activate_threads_~tmp~1#1); 3151#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3152#L257 assume 1 == ~t1_pc~0; 3416#L258 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3268#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3248#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 3120#L623 assume !(0 != activate_threads_~tmp___0~0#1); 3121#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3115#L276 assume !(1 == ~t2_pc~0); 3116#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 3388#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3480#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 3485#L631 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3486#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3428#L295 assume 1 == ~t3_pc~0; 3283#L296 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3230#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3153#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3154#L639 assume !(0 != activate_threads_~tmp___2~0#1); 3455#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3456#L314 assume !(1 == ~t4_pc~0); 3273#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 3272#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3346#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 3347#L647 assume !(0 != activate_threads_~tmp___3~0#1); 3371#L647-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3372#L555 assume !(1 == ~M_E~0); 3289#L555-2 assume !(1 == ~T1_E~0); 3290#L560-1 assume !(1 == ~T2_E~0); 3170#L565-1 assume !(1 == ~T3_E~0); 3171#L570-1 assume !(1 == ~T4_E~0); 3241#L575-1 assume !(1 == ~E_1~0); 3242#L580-1 assume !(1 == ~E_2~0); 3415#L585-1 assume 1 == ~E_3~0;~E_3~0 := 2; 3243#L590-1 assume !(1 == ~E_4~0); 3231#L595-1 assume { :end_inline_reset_delta_events } true; 3232#L776-2 [2022-12-13 21:03:33,184 INFO L750 eck$LassoCheckResult]: Loop: 3232#L776-2 assume !false; 3204#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3205#L477 assume !false; 3299#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 3300#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 3140#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 3141#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 3155#L416 assume !(0 != eval_~tmp~0#1); 3180#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3351#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3403#L502-3 assume !(0 == ~M_E~0); 3404#L502-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3420#L507-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3352#L512-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3353#L517-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3333#L522-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3334#L527-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3417#L532-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3359#L537-3 assume !(0 == ~E_4~0); 3360#L542-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3367#L238-15 assume 1 == ~m_pc~0; 3160#L239-5 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 3161#L249-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3343#is_master_triggered_returnLabel#6 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 3265#L615-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3266#L615-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3197#L257-15 assume !(1 == ~t1_pc~0); 3198#L257-17 is_transmit1_triggered_~__retres1~1#1 := 0; 3399#L268-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3311#is_transmit1_triggered_returnLabel#6 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 3312#L623-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3432#L623-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3446#L276-15 assume 1 == ~t2_pc~0; 3330#L277-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3318#L287-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3319#is_transmit2_triggered_returnLabel#6 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 3495#L631-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3410#L631-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3226#L295-15 assume !(1 == ~t3_pc~0); 3227#L295-17 is_transmit3_triggered_~__retres1~3#1 := 0; 3430#L306-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3473#is_transmit3_triggered_returnLabel#6 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3481#L639-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3464#L639-17 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3465#L314-15 assume 1 == ~t4_pc~0; 3395#L315-5 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3396#L325-5 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3434#is_transmit4_triggered_returnLabel#6 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 3435#L647-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 3451#L647-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3409#L555-3 assume 1 == ~M_E~0;~M_E~0 := 2; 3134#L555-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3135#L560-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3306#L565-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3436#L570-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3411#L575-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3124#L580-3 assume !(1 == ~E_2~0); 3125#L585-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3286#L590-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3287#L595-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 3370#L374-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 3209#L401-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 3398#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 3426#L795 assume !(0 == start_simulation_~tmp~3#1); 3427#L795-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 3447#L374-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 3176#L401-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 3244#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 3245#L750 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3295#L757 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3296#stop_simulation_returnLabel#1 start_simulation_#t~ret17#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 3377#L808 assume !(0 != start_simulation_~tmp___0~1#1); 3232#L776-2 [2022-12-13 21:03:33,185 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 21:03:33,185 INFO L85 PathProgramCache]: Analyzing trace with hash -1788857204, now seen corresponding path program 1 times [2022-12-13 21:03:33,185 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 21:03:33,185 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [284268318] [2022-12-13 21:03:33,185 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 21:03:33,186 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 21:03:33,195 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 21:03:33,225 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 21:03:33,226 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 21:03:33,226 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [284268318] [2022-12-13 21:03:33,226 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [284268318] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 21:03:33,226 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 21:03:33,226 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-12-13 21:03:33,227 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [145129845] [2022-12-13 21:03:33,227 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 21:03:33,227 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 21:03:33,227 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 21:03:33,227 INFO L85 PathProgramCache]: Analyzing trace with hash -1704108643, now seen corresponding path program 3 times [2022-12-13 21:03:33,228 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 21:03:33,228 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1014725235] [2022-12-13 21:03:33,228 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 21:03:33,228 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 21:03:33,237 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 21:03:33,264 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 21:03:33,264 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 21:03:33,264 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1014725235] [2022-12-13 21:03:33,264 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1014725235] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 21:03:33,264 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 21:03:33,264 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 21:03:33,264 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1034732067] [2022-12-13 21:03:33,264 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 21:03:33,264 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 21:03:33,265 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 21:03:33,265 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 21:03:33,265 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 21:03:33,265 INFO L87 Difference]: Start difference. First operand 384 states and 572 transitions. cyclomatic complexity: 189 Second operand has 3 states, 3 states have (on average 20.0) internal successors, (60), 2 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 21:03:33,281 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 21:03:33,282 INFO L93 Difference]: Finished difference Result 384 states and 567 transitions. [2022-12-13 21:03:33,282 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 384 states and 567 transitions. [2022-12-13 21:03:33,284 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 319 [2022-12-13 21:03:33,285 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 384 states to 384 states and 567 transitions. [2022-12-13 21:03:33,285 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 384 [2022-12-13 21:03:33,286 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 384 [2022-12-13 21:03:33,286 INFO L73 IsDeterministic]: Start isDeterministic. Operand 384 states and 567 transitions. [2022-12-13 21:03:33,286 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 21:03:33,286 INFO L218 hiAutomatonCegarLoop]: Abstraction has 384 states and 567 transitions. [2022-12-13 21:03:33,287 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 384 states and 567 transitions. [2022-12-13 21:03:33,289 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 384 to 384. [2022-12-13 21:03:33,290 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 384 states, 384 states have (on average 1.4765625) internal successors, (567), 383 states have internal predecessors, (567), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 21:03:33,291 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 384 states to 384 states and 567 transitions. [2022-12-13 21:03:33,291 INFO L240 hiAutomatonCegarLoop]: Abstraction has 384 states and 567 transitions. [2022-12-13 21:03:33,291 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 21:03:33,292 INFO L428 stractBuchiCegarLoop]: Abstraction has 384 states and 567 transitions. [2022-12-13 21:03:33,292 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2022-12-13 21:03:33,292 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 384 states and 567 transitions. [2022-12-13 21:03:33,294 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 319 [2022-12-13 21:03:33,294 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 21:03:33,294 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 21:03:33,295 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 21:03:33,295 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 21:03:33,296 INFO L748 eck$LassoCheckResult]: Stem: 4233#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 4234#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 4243#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4241#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4138#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 4139#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3977#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3978#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3988#L356-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 3989#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4034#L502 assume !(0 == ~M_E~0); 4035#L502-2 assume !(0 == ~T1_E~0); 3968#L507-1 assume !(0 == ~T2_E~0); 3969#L512-1 assume !(0 == ~T3_E~0); 4140#L517-1 assume !(0 == ~T4_E~0); 3948#L522-1 assume !(0 == ~E_1~0); 3949#L527-1 assume !(0 == ~E_2~0); 4154#L532-1 assume !(0 == ~E_3~0); 4237#L537-1 assume !(0 == ~E_4~0); 4249#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4227#L238 assume 1 == ~m_pc~0; 4228#L239 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 3907#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3908#is_master_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 4206#L615 assume !(0 != activate_threads_~tmp~1#1); 3930#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3931#L257 assume 1 == ~t1_pc~0; 4191#L258 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4043#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4023#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 3895#L623 assume !(0 != activate_threads_~tmp___0~0#1); 3896#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3890#L276 assume !(1 == ~t2_pc~0); 3891#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 4166#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4255#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 4261#L631 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4262#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4205#L295 assume 1 == ~t3_pc~0; 4058#L296 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 4005#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3932#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3933#L639 assume !(0 != activate_threads_~tmp___2~0#1); 4230#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4231#L314 assume !(1 == ~t4_pc~0); 4048#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 4047#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4121#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4122#L647 assume !(0 != activate_threads_~tmp___3~0#1); 4146#L647-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4147#L555 assume !(1 == ~M_E~0); 4064#L555-2 assume !(1 == ~T1_E~0); 4065#L560-1 assume !(1 == ~T2_E~0); 3950#L565-1 assume !(1 == ~T3_E~0); 3951#L570-1 assume !(1 == ~T4_E~0); 4018#L575-1 assume !(1 == ~E_1~0); 4019#L580-1 assume !(1 == ~E_2~0); 4190#L585-1 assume 1 == ~E_3~0;~E_3~0 := 2; 4020#L590-1 assume !(1 == ~E_4~0); 4006#L595-1 assume { :end_inline_reset_delta_events } true; 4007#L776-2 [2022-12-13 21:03:33,296 INFO L750 eck$LassoCheckResult]: Loop: 4007#L776-2 assume !false; 3979#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3980#L477 assume !false; 4074#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 4075#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 3915#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 3916#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 3934#L416 assume !(0 != eval_~tmp~0#1); 3955#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4126#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4178#L502-3 assume !(0 == ~M_E~0); 4179#L502-5 assume !(0 == ~T1_E~0); 4195#L507-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4127#L512-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4128#L517-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4108#L522-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4109#L527-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4192#L532-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4134#L537-3 assume !(0 == ~E_4~0); 4135#L542-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4142#L238-15 assume !(1 == ~m_pc~0); 3937#L238-17 is_master_triggered_~__retres1~0#1 := 0; 3936#L249-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4118#is_master_triggered_returnLabel#6 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 4040#L615-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4041#L615-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3972#L257-15 assume !(1 == ~t1_pc~0); 3973#L257-17 is_transmit1_triggered_~__retres1~1#1 := 0; 4174#L268-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4086#is_transmit1_triggered_returnLabel#6 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 4087#L623-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4207#L623-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4221#L276-15 assume 1 == ~t2_pc~0; 4105#L277-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4093#L287-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4094#is_transmit2_triggered_returnLabel#6 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 4270#L631-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4185#L631-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4001#L295-15 assume !(1 == ~t3_pc~0); 4002#L295-17 is_transmit3_triggered_~__retres1~3#1 := 0; 4204#L306-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4248#is_transmit3_triggered_returnLabel#6 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 4256#L639-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4239#L639-17 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4240#L314-15 assume 1 == ~t4_pc~0; 4170#L315-5 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 4171#L325-5 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4209#is_transmit4_triggered_returnLabel#6 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4210#L647-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 4226#L647-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4184#L555-3 assume 1 == ~M_E~0;~M_E~0 := 2; 3909#L555-5 assume !(1 == ~T1_E~0); 3910#L560-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4081#L565-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4211#L570-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4186#L575-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3899#L580-3 assume !(1 == ~E_2~0); 3900#L585-3 assume 1 == ~E_3~0;~E_3~0 := 2; 4061#L590-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4062#L595-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 4145#L374-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 3984#L401-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 4173#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 4201#L795 assume !(0 == start_simulation_~tmp~3#1); 4202#L795-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 4222#L374-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 3945#L401-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 4016#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 4017#L750 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4070#L757 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4071#stop_simulation_returnLabel#1 start_simulation_#t~ret17#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 4152#L808 assume !(0 != start_simulation_~tmp___0~1#1); 4007#L776-2 [2022-12-13 21:03:33,296 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 21:03:33,297 INFO L85 PathProgramCache]: Analyzing trace with hash -1804375922, now seen corresponding path program 1 times [2022-12-13 21:03:33,297 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 21:03:33,297 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [60075147] [2022-12-13 21:03:33,297 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 21:03:33,297 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 21:03:33,307 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 21:03:33,340 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 21:03:33,340 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 21:03:33,341 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [60075147] [2022-12-13 21:03:33,341 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [60075147] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 21:03:33,341 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 21:03:33,341 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-12-13 21:03:33,341 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1550740973] [2022-12-13 21:03:33,341 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 21:03:33,342 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 21:03:33,342 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 21:03:33,342 INFO L85 PathProgramCache]: Analyzing trace with hash -21400384, now seen corresponding path program 1 times [2022-12-13 21:03:33,342 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 21:03:33,342 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [298588540] [2022-12-13 21:03:33,343 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 21:03:33,343 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 21:03:33,351 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 21:03:33,373 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 21:03:33,373 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 21:03:33,373 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [298588540] [2022-12-13 21:03:33,374 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [298588540] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 21:03:33,374 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 21:03:33,374 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 21:03:33,374 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1484805516] [2022-12-13 21:03:33,374 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 21:03:33,374 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 21:03:33,375 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 21:03:33,375 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 21:03:33,375 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 21:03:33,375 INFO L87 Difference]: Start difference. First operand 384 states and 567 transitions. cyclomatic complexity: 184 Second operand has 3 states, 3 states have (on average 20.0) internal successors, (60), 2 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 21:03:33,419 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 21:03:33,419 INFO L93 Difference]: Finished difference Result 694 states and 1012 transitions. [2022-12-13 21:03:33,419 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 694 states and 1012 transitions. [2022-12-13 21:03:33,424 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 629 [2022-12-13 21:03:33,426 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 694 states to 694 states and 1012 transitions. [2022-12-13 21:03:33,426 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 694 [2022-12-13 21:03:33,427 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 694 [2022-12-13 21:03:33,427 INFO L73 IsDeterministic]: Start isDeterministic. Operand 694 states and 1012 transitions. [2022-12-13 21:03:33,427 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 21:03:33,427 INFO L218 hiAutomatonCegarLoop]: Abstraction has 694 states and 1012 transitions. [2022-12-13 21:03:33,428 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 694 states and 1012 transitions. [2022-12-13 21:03:33,434 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 694 to 658. [2022-12-13 21:03:33,435 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 658 states, 658 states have (on average 1.4635258358662615) internal successors, (963), 657 states have internal predecessors, (963), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 21:03:33,436 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 658 states to 658 states and 963 transitions. [2022-12-13 21:03:33,436 INFO L240 hiAutomatonCegarLoop]: Abstraction has 658 states and 963 transitions. [2022-12-13 21:03:33,436 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 21:03:33,437 INFO L428 stractBuchiCegarLoop]: Abstraction has 658 states and 963 transitions. [2022-12-13 21:03:33,437 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2022-12-13 21:03:33,437 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 658 states and 963 transitions. [2022-12-13 21:03:33,439 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 593 [2022-12-13 21:03:33,439 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 21:03:33,439 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 21:03:33,439 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 21:03:33,440 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 21:03:33,440 INFO L748 eck$LassoCheckResult]: Stem: 5332#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 5333#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 5344#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5340#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5226#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 5227#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5062#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5063#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 5073#L356-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 5074#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5119#L502 assume !(0 == ~M_E~0); 5120#L502-2 assume !(0 == ~T1_E~0); 5050#L507-1 assume !(0 == ~T2_E~0); 5051#L512-1 assume !(0 == ~T3_E~0); 5230#L517-1 assume !(0 == ~T4_E~0); 5026#L522-1 assume !(0 == ~E_1~0); 5027#L527-1 assume !(0 == ~E_2~0); 5245#L532-1 assume !(0 == ~E_3~0); 5336#L537-1 assume !(0 == ~E_4~0); 5352#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5326#L238 assume !(1 == ~m_pc~0); 5327#L238-2 is_master_triggered_~__retres1~0#1 := 0; 4986#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4987#is_master_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 5304#L615 assume !(0 != activate_threads_~tmp~1#1); 5011#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5012#L257 assume 1 == ~t1_pc~0; 5286#L258 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 5128#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5108#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 4978#L623 assume !(0 != activate_threads_~tmp___0~0#1); 4979#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4975#L276 assume !(1 == ~t2_pc~0); 4976#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 5253#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5359#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 5365#L631 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 5366#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5301#L295 assume 1 == ~t3_pc~0; 5143#L296 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 5090#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5013#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 5014#L639 assume !(0 != activate_threads_~tmp___2~0#1); 5328#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5329#L314 assume !(1 == ~t4_pc~0); 5133#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 5132#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5208#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 5209#L647 assume !(0 != activate_threads_~tmp___3~0#1); 5236#L647-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5237#L555 assume !(1 == ~M_E~0); 5149#L555-2 assume !(1 == ~T1_E~0); 5150#L560-1 assume !(1 == ~T2_E~0); 5028#L565-1 assume !(1 == ~T3_E~0); 5029#L570-1 assume !(1 == ~T4_E~0); 5101#L575-1 assume !(1 == ~E_1~0); 5102#L580-1 assume !(1 == ~E_2~0); 5285#L585-1 assume 1 == ~E_3~0;~E_3~0 := 2; 5103#L590-1 assume !(1 == ~E_4~0); 5091#L595-1 assume { :end_inline_reset_delta_events } true; 5092#L776-2 [2022-12-13 21:03:33,440 INFO L750 eck$LassoCheckResult]: Loop: 5092#L776-2 assume !false; 5064#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5065#L477 assume !false; 5159#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 5160#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 4998#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 4999#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 5015#L416 assume !(0 != eval_~tmp~0#1); 5040#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5215#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5272#L502-3 assume !(0 == ~M_E~0); 5293#L502-5 assume !(0 == ~T1_E~0); 5294#L507-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 5216#L512-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5217#L517-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5197#L522-3 assume 0 == ~E_1~0;~E_1~0 := 1; 5198#L527-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5287#L532-3 assume 0 == ~E_3~0;~E_3~0 := 1; 5224#L537-3 assume !(0 == ~E_4~0); 5225#L542-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5232#L238-15 assume !(1 == ~m_pc~0); 5281#L238-17 is_master_triggered_~__retres1~0#1 := 0; 5314#L249-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5206#is_master_triggered_returnLabel#6 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 5125#L615-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 5126#L615-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5057#L257-15 assume !(1 == ~t1_pc~0); 5058#L257-17 is_transmit1_triggered_~__retres1~1#1 := 0; 5265#L268-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5174#is_transmit1_triggered_returnLabel#6 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 5175#L623-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 5305#L623-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5319#L276-15 assume 1 == ~t2_pc~0; 5194#L277-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5182#L287-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5183#is_transmit2_triggered_returnLabel#6 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 5379#L631-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 5278#L631-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5086#L295-15 assume 1 == ~t3_pc~0; 5088#L296-5 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 5303#L306-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5351#is_transmit3_triggered_returnLabel#6 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 5361#L639-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 5338#L639-17 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5339#L314-15 assume 1 == ~t4_pc~0; 5261#L315-5 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5262#L325-5 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5307#is_transmit4_triggered_returnLabel#6 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 5308#L647-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 5325#L647-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5276#L555-3 assume 1 == ~M_E~0;~M_E~0 := 2; 5277#L555-5 assume !(1 == ~T1_E~0); 5166#L560-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5167#L565-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 5309#L570-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5279#L575-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5280#L580-3 assume !(1 == ~E_2~0); 5519#L585-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5485#L590-3 assume 1 == ~E_4~0;~E_4~0 := 2; 5484#L595-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 5481#L374-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 5478#L401-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 5477#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 5476#L795 assume !(0 == start_simulation_~tmp~3#1); 5330#L795-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 5320#L374-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 5034#L401-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 5104#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 5105#L750 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5155#L757 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5156#stop_simulation_returnLabel#1 start_simulation_#t~ret17#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 5242#L808 assume !(0 != start_simulation_~tmp___0~1#1); 5092#L776-2 [2022-12-13 21:03:33,440 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 21:03:33,440 INFO L85 PathProgramCache]: Analyzing trace with hash -1404384723, now seen corresponding path program 1 times [2022-12-13 21:03:33,440 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 21:03:33,441 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1959822331] [2022-12-13 21:03:33,441 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 21:03:33,441 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 21:03:33,445 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 21:03:33,471 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 21:03:33,471 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 21:03:33,471 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1959822331] [2022-12-13 21:03:33,472 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1959822331] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 21:03:33,472 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 21:03:33,472 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 21:03:33,472 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [670209636] [2022-12-13 21:03:33,472 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 21:03:33,472 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 21:03:33,473 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 21:03:33,473 INFO L85 PathProgramCache]: Analyzing trace with hash 1607249889, now seen corresponding path program 1 times [2022-12-13 21:03:33,473 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 21:03:33,473 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [606899348] [2022-12-13 21:03:33,473 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 21:03:33,473 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 21:03:33,481 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 21:03:33,501 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 21:03:33,501 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 21:03:33,501 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [606899348] [2022-12-13 21:03:33,502 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [606899348] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 21:03:33,502 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 21:03:33,502 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 21:03:33,502 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2106222021] [2022-12-13 21:03:33,502 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 21:03:33,502 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 21:03:33,503 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 21:03:33,503 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 21:03:33,503 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 21:03:33,511 INFO L87 Difference]: Start difference. First operand 658 states and 963 transitions. cyclomatic complexity: 307 Second operand has 4 states, 4 states have (on average 15.0) internal successors, (60), 3 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 21:03:33,623 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 21:03:33,623 INFO L93 Difference]: Finished difference Result 1490 states and 2153 transitions. [2022-12-13 21:03:33,624 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1490 states and 2153 transitions. [2022-12-13 21:03:33,631 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 1382 [2022-12-13 21:03:33,635 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1490 states to 1490 states and 2153 transitions. [2022-12-13 21:03:33,635 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1490 [2022-12-13 21:03:33,636 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1490 [2022-12-13 21:03:33,636 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1490 states and 2153 transitions. [2022-12-13 21:03:33,637 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 21:03:33,637 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1490 states and 2153 transitions. [2022-12-13 21:03:33,638 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1490 states and 2153 transitions. [2022-12-13 21:03:33,649 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1490 to 1163. [2022-12-13 21:03:33,650 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1163 states, 1163 states have (on average 1.4557179707652623) internal successors, (1693), 1162 states have internal predecessors, (1693), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 21:03:33,652 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1163 states to 1163 states and 1693 transitions. [2022-12-13 21:03:33,652 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1163 states and 1693 transitions. [2022-12-13 21:03:33,652 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 21:03:33,653 INFO L428 stractBuchiCegarLoop]: Abstraction has 1163 states and 1693 transitions. [2022-12-13 21:03:33,653 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2022-12-13 21:03:33,653 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1163 states and 1693 transitions. [2022-12-13 21:03:33,656 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1098 [2022-12-13 21:03:33,657 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 21:03:33,657 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 21:03:33,657 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 21:03:33,657 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 21:03:33,658 INFO L748 eck$LassoCheckResult]: Stem: 7490#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 7491#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 7503#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 7498#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7391#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 7392#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7220#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 7221#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 7231#L356-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 7232#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7277#L502 assume !(0 == ~M_E~0); 7278#L502-2 assume !(0 == ~T1_E~0); 7212#L507-1 assume !(0 == ~T2_E~0); 7213#L512-1 assume !(0 == ~T3_E~0); 7393#L517-1 assume !(0 == ~T4_E~0); 7192#L522-1 assume !(0 == ~E_1~0); 7193#L527-1 assume !(0 == ~E_2~0); 7408#L532-1 assume !(0 == ~E_3~0); 7494#L537-1 assume !(0 == ~E_4~0); 7510#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7485#L238 assume !(1 == ~m_pc~0); 7486#L238-2 is_master_triggered_~__retres1~0#1 := 0; 7150#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7151#is_master_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 7461#L615 assume !(0 != activate_threads_~tmp~1#1); 7174#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7175#L257 assume !(1 == ~t1_pc~0); 7285#L257-2 is_transmit1_triggered_~__retres1~1#1 := 0; 7286#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7266#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 7138#L623 assume !(0 != activate_threads_~tmp___0~0#1); 7139#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7133#L276 assume !(1 == ~t2_pc~0); 7134#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 7419#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7516#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 7524#L631 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 7525#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7459#L295 assume 1 == ~t3_pc~0; 7301#L296 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 7248#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7176#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 7177#L639 assume !(0 != activate_threads_~tmp___2~0#1); 7487#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7488#L314 assume !(1 == ~t4_pc~0); 7291#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 7290#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7372#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 7373#L647 assume !(0 != activate_threads_~tmp___3~0#1); 7399#L647-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7400#L555 assume !(1 == ~M_E~0); 7308#L555-2 assume !(1 == ~T1_E~0); 7309#L560-1 assume !(1 == ~T2_E~0); 7194#L565-1 assume !(1 == ~T3_E~0); 7195#L570-1 assume !(1 == ~T4_E~0); 7261#L575-1 assume !(1 == ~E_1~0); 7262#L580-1 assume !(1 == ~E_2~0); 7444#L585-1 assume 1 == ~E_3~0;~E_3~0 := 2; 7263#L590-1 assume !(1 == ~E_4~0); 7249#L595-1 assume { :end_inline_reset_delta_events } true; 7250#L776-2 [2022-12-13 21:03:33,658 INFO L750 eck$LassoCheckResult]: Loop: 7250#L776-2 assume !false; 7222#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 7223#L477 assume !false; 7318#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 7319#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 7156#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 7157#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 7169#L416 assume !(0 != eval_~tmp~0#1); 7199#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 8260#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 8259#L502-3 assume !(0 == ~M_E~0); 8258#L502-5 assume !(0 == ~T1_E~0); 8257#L507-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 8256#L512-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 8255#L517-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 8254#L522-3 assume 0 == ~E_1~0;~E_1~0 := 1; 8253#L527-3 assume 0 == ~E_2~0;~E_2~0 := 1; 8252#L532-3 assume 0 == ~E_3~0;~E_3~0 := 1; 8251#L537-3 assume !(0 == ~E_4~0); 8250#L542-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8249#L238-15 assume !(1 == ~m_pc~0); 8248#L238-17 is_master_triggered_~__retres1~0#1 := 0; 7471#L249-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7367#is_master_triggered_returnLabel#6 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 7283#L615-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 7284#L615-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7216#L257-15 assume !(1 == ~t1_pc~0); 7217#L257-17 is_transmit1_triggered_~__retres1~1#1 := 0; 7427#L268-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7331#is_transmit1_triggered_returnLabel#6 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 7332#L623-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 7462#L623-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7475#L276-15 assume 1 == ~t2_pc~0; 7355#L277-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 7336#L287-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7337#is_transmit2_triggered_returnLabel#6 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 7538#L631-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 7439#L631-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7244#L295-15 assume !(1 == ~t3_pc~0); 7245#L295-17 is_transmit3_triggered_~__retres1~3#1 := 0; 7458#L306-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7508#is_transmit3_triggered_returnLabel#6 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 7517#L639-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 7496#L639-17 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7497#L314-15 assume !(1 == ~t4_pc~0); 7425#L314-17 is_transmit4_triggered_~__retres1~4#1 := 0; 7424#L325-5 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7464#is_transmit4_triggered_returnLabel#6 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 7465#L647-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 8155#L647-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8154#L555-3 assume 1 == ~M_E~0;~M_E~0 := 2; 8153#L555-5 assume !(1 == ~T1_E~0); 7323#L560-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7324#L565-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 7466#L570-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 7440#L575-3 assume 1 == ~E_1~0;~E_1~0 := 2; 7142#L580-3 assume !(1 == ~E_2~0); 7143#L585-3 assume 1 == ~E_3~0;~E_3~0 := 2; 7304#L590-3 assume 1 == ~E_4~0;~E_4~0 := 2; 7305#L595-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 7398#L374-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 7227#L401-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 7426#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 7456#L795 assume !(0 == start_simulation_~tmp~3#1); 7457#L795-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 7477#L374-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 7186#L401-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 7259#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 7260#L750 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 7314#L757 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 7315#stop_simulation_returnLabel#1 start_simulation_#t~ret17#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 7405#L808 assume !(0 != start_simulation_~tmp___0~1#1); 7250#L776-2 [2022-12-13 21:03:33,658 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 21:03:33,658 INFO L85 PathProgramCache]: Analyzing trace with hash 1261932300, now seen corresponding path program 1 times [2022-12-13 21:03:33,658 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 21:03:33,658 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [947043674] [2022-12-13 21:03:33,658 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 21:03:33,659 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 21:03:33,664 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 21:03:33,689 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 21:03:33,690 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 21:03:33,690 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [947043674] [2022-12-13 21:03:33,690 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [947043674] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 21:03:33,690 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 21:03:33,690 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-12-13 21:03:33,690 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1772051251] [2022-12-13 21:03:33,690 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 21:03:33,691 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 21:03:33,691 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 21:03:33,691 INFO L85 PathProgramCache]: Analyzing trace with hash -329839393, now seen corresponding path program 1 times [2022-12-13 21:03:33,691 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 21:03:33,691 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1017517943] [2022-12-13 21:03:33,691 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 21:03:33,692 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 21:03:33,699 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 21:03:33,719 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 21:03:33,720 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 21:03:33,720 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1017517943] [2022-12-13 21:03:33,720 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1017517943] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 21:03:33,720 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 21:03:33,720 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 21:03:33,720 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1987612151] [2022-12-13 21:03:33,720 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 21:03:33,721 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 21:03:33,721 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 21:03:33,721 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-12-13 21:03:33,721 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-12-13 21:03:33,721 INFO L87 Difference]: Start difference. First operand 1163 states and 1693 transitions. cyclomatic complexity: 532 Second operand has 5 states, 5 states have (on average 12.0) internal successors, (60), 5 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 21:03:33,848 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 21:03:33,848 INFO L93 Difference]: Finished difference Result 2972 states and 4330 transitions. [2022-12-13 21:03:33,848 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2972 states and 4330 transitions. [2022-12-13 21:03:33,859 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2850 [2022-12-13 21:03:33,867 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2972 states to 2972 states and 4330 transitions. [2022-12-13 21:03:33,867 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2972 [2022-12-13 21:03:33,869 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2972 [2022-12-13 21:03:33,869 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2972 states and 4330 transitions. [2022-12-13 21:03:33,872 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 21:03:33,872 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2972 states and 4330 transitions. [2022-12-13 21:03:33,874 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2972 states and 4330 transitions. [2022-12-13 21:03:33,888 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2972 to 1226. [2022-12-13 21:03:33,889 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1226 states, 1226 states have (on average 1.432300163132137) internal successors, (1756), 1225 states have internal predecessors, (1756), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 21:03:33,891 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1226 states to 1226 states and 1756 transitions. [2022-12-13 21:03:33,891 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1226 states and 1756 transitions. [2022-12-13 21:03:33,892 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-12-13 21:03:33,892 INFO L428 stractBuchiCegarLoop]: Abstraction has 1226 states and 1756 transitions. [2022-12-13 21:03:33,892 INFO L335 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2022-12-13 21:03:33,892 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1226 states and 1756 transitions. [2022-12-13 21:03:33,895 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1158 [2022-12-13 21:03:33,896 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 21:03:33,896 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 21:03:33,896 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 21:03:33,896 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 21:03:33,896 INFO L748 eck$LassoCheckResult]: Stem: 11643#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 11644#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 11655#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 11651#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 11534#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 11535#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 11367#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 11368#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 11378#L356-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 11379#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 11424#L502 assume !(0 == ~M_E~0); 11425#L502-2 assume !(0 == ~T1_E~0); 11356#L507-1 assume !(0 == ~T2_E~0); 11357#L512-1 assume !(0 == ~T3_E~0); 11538#L517-1 assume !(0 == ~T4_E~0); 11332#L522-1 assume !(0 == ~E_1~0); 11333#L527-1 assume !(0 == ~E_2~0); 11556#L532-1 assume !(0 == ~E_3~0); 11647#L537-1 assume !(0 == ~E_4~0); 11667#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11638#L238 assume !(1 == ~m_pc~0); 11639#L238-2 is_master_triggered_~__retres1~0#1 := 0; 11292#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11293#is_master_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 11615#L615 assume !(0 != activate_threads_~tmp~1#1); 11317#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11318#L257 assume !(1 == ~t1_pc~0); 11432#L257-2 is_transmit1_triggered_~__retres1~1#1 := 0; 11433#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11413#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 11284#L623 assume !(0 != activate_threads_~tmp___0~0#1); 11285#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11281#L276 assume !(1 == ~t2_pc~0); 11282#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 11565#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11674#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 11681#L631 assume !(0 != activate_threads_~tmp___1~0#1); 11682#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11612#L295 assume 1 == ~t3_pc~0; 11448#L296 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 11395#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11319#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 11320#L639 assume !(0 != activate_threads_~tmp___2~0#1); 11640#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 11641#L314 assume !(1 == ~t4_pc~0); 11438#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 11437#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 11515#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 11516#L647 assume !(0 != activate_threads_~tmp___3~0#1); 11545#L647-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11546#L555 assume !(1 == ~M_E~0); 11454#L555-2 assume !(1 == ~T1_E~0); 11455#L560-1 assume !(1 == ~T2_E~0); 11334#L565-1 assume !(1 == ~T3_E~0); 11335#L570-1 assume !(1 == ~T4_E~0); 11406#L575-1 assume !(1 == ~E_1~0); 11407#L580-1 assume !(1 == ~E_2~0); 11596#L585-1 assume 1 == ~E_3~0;~E_3~0 := 2; 11408#L590-1 assume !(1 == ~E_4~0); 11396#L595-1 assume { :end_inline_reset_delta_events } true; 11397#L776-2 [2022-12-13 21:03:33,897 INFO L750 eck$LassoCheckResult]: Loop: 11397#L776-2 assume !false; 11369#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 11370#L477 assume !false; 11464#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 11465#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 11304#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 11305#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 11321#L416 assume !(0 != eval_~tmp~0#1); 11346#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 12502#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 12501#L502-3 assume !(0 == ~M_E~0); 12500#L502-5 assume !(0 == ~T1_E~0); 12499#L507-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 12498#L512-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 11721#L517-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 11504#L522-3 assume 0 == ~E_1~0;~E_1~0 := 1; 11505#L527-3 assume 0 == ~E_2~0;~E_2~0 := 1; 11597#L532-3 assume 0 == ~E_3~0;~E_3~0 := 1; 11532#L537-3 assume !(0 == ~E_4~0); 11533#L542-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12485#L238-15 assume !(1 == ~m_pc~0); 12484#L238-17 is_master_triggered_~__retres1~0#1 := 0; 12483#L249-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12481#is_master_triggered_returnLabel#6 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 12479#L615-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 12477#L615-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11363#L257-15 assume !(1 == ~t1_pc~0); 11364#L257-17 is_transmit1_triggered_~__retres1~1#1 := 0; 12482#L268-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12480#is_transmit1_triggered_returnLabel#6 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 12478#L623-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 12476#L623-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11699#L276-15 assume 1 == ~t2_pc~0; 11501#L277-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 11486#L287-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11487#is_transmit2_triggered_returnLabel#6 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 11697#L631-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 11589#L631-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11391#L295-15 assume !(1 == ~t3_pc~0); 11392#L295-17 is_transmit3_triggered_~__retres1~3#1 := 0; 11614#L306-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11676#is_transmit3_triggered_returnLabel#6 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 11677#L639-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 11648#L639-17 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 11649#L314-15 assume 1 == ~t4_pc~0; 11570#L315-5 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 11571#L325-5 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 11618#is_transmit4_triggered_returnLabel#6 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 11619#L647-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 11637#L647-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11588#L555-3 assume 1 == ~M_E~0;~M_E~0 := 2; 11300#L555-5 assume !(1 == ~T1_E~0); 11301#L560-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 11471#L565-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 11620#L570-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 11590#L575-3 assume 1 == ~E_1~0;~E_1~0 := 2; 11290#L580-3 assume !(1 == ~E_2~0); 11291#L585-3 assume 1 == ~E_3~0;~E_3~0 := 2; 11451#L590-3 assume 1 == ~E_4~0;~E_4~0 := 2; 11452#L595-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 11544#L374-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 11374#L401-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 11575#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 11610#L795 assume !(0 == start_simulation_~tmp~3#1); 11611#L795-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 11633#L374-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 11340#L401-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 11409#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 11410#L750 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 11460#L757 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 11461#stop_simulation_returnLabel#1 start_simulation_#t~ret17#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 11553#L808 assume !(0 != start_simulation_~tmp___0~1#1); 11397#L776-2 [2022-12-13 21:03:33,897 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 21:03:33,897 INFO L85 PathProgramCache]: Analyzing trace with hash 1127918794, now seen corresponding path program 1 times [2022-12-13 21:03:33,897 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 21:03:33,897 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [804306064] [2022-12-13 21:03:33,897 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 21:03:33,897 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 21:03:33,910 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 21:03:33,940 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 21:03:33,940 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 21:03:33,940 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [804306064] [2022-12-13 21:03:33,940 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [804306064] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 21:03:33,940 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 21:03:33,940 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 21:03:33,940 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [934023129] [2022-12-13 21:03:33,940 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 21:03:33,941 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 21:03:33,941 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 21:03:33,941 INFO L85 PathProgramCache]: Analyzing trace with hash -21400384, now seen corresponding path program 2 times [2022-12-13 21:03:33,941 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 21:03:33,941 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1011837642] [2022-12-13 21:03:33,941 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 21:03:33,941 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 21:03:33,948 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 21:03:33,966 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 21:03:33,966 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 21:03:33,966 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1011837642] [2022-12-13 21:03:33,967 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1011837642] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 21:03:33,967 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 21:03:33,967 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 21:03:33,967 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1322300019] [2022-12-13 21:03:33,967 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 21:03:33,967 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 21:03:33,967 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 21:03:33,968 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 21:03:33,968 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 21:03:33,968 INFO L87 Difference]: Start difference. First operand 1226 states and 1756 transitions. cyclomatic complexity: 532 Second operand has 4 states, 4 states have (on average 15.0) internal successors, (60), 3 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 21:03:34,065 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 21:03:34,065 INFO L93 Difference]: Finished difference Result 2784 states and 3948 transitions. [2022-12-13 21:03:34,066 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2784 states and 3948 transitions. [2022-12-13 21:03:34,088 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 2624 [2022-12-13 21:03:34,111 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2784 states to 2784 states and 3948 transitions. [2022-12-13 21:03:34,111 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2784 [2022-12-13 21:03:34,114 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2784 [2022-12-13 21:03:34,114 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2784 states and 3948 transitions. [2022-12-13 21:03:34,119 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 21:03:34,119 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2784 states and 3948 transitions. [2022-12-13 21:03:34,123 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2784 states and 3948 transitions. [2022-12-13 21:03:34,156 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2784 to 2201. [2022-12-13 21:03:34,161 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2201 states, 2201 states have (on average 1.4279872785097683) internal successors, (3143), 2200 states have internal predecessors, (3143), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 21:03:34,169 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2201 states to 2201 states and 3143 transitions. [2022-12-13 21:03:34,169 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2201 states and 3143 transitions. [2022-12-13 21:03:34,169 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 21:03:34,170 INFO L428 stractBuchiCegarLoop]: Abstraction has 2201 states and 3143 transitions. [2022-12-13 21:03:34,170 INFO L335 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2022-12-13 21:03:34,170 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2201 states and 3143 transitions. [2022-12-13 21:03:34,183 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2132 [2022-12-13 21:03:34,183 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 21:03:34,183 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 21:03:34,185 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 21:03:34,185 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 21:03:34,185 INFO L748 eck$LassoCheckResult]: Stem: 15665#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 15666#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 15676#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 15673#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 15554#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 15555#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 15387#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 15388#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 15398#L356-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 15399#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 15443#L502 assume !(0 == ~M_E~0); 15444#L502-2 assume !(0 == ~T1_E~0); 15376#L507-1 assume !(0 == ~T2_E~0); 15377#L512-1 assume !(0 == ~T3_E~0); 15558#L517-1 assume !(0 == ~T4_E~0); 15352#L522-1 assume !(0 == ~E_1~0); 15353#L527-1 assume !(0 == ~E_2~0); 15575#L532-1 assume !(0 == ~E_3~0); 15669#L537-1 assume !(0 == ~E_4~0); 15689#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 15660#L238 assume !(1 == ~m_pc~0); 15661#L238-2 is_master_triggered_~__retres1~0#1 := 0; 15312#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 15313#is_master_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 15639#L615 assume !(0 != activate_threads_~tmp~1#1); 15337#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 15338#L257 assume !(1 == ~t1_pc~0); 15451#L257-2 is_transmit1_triggered_~__retres1~1#1 := 0; 15452#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 15432#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 15304#L623 assume !(0 != activate_threads_~tmp___0~0#1); 15305#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15301#L276 assume !(1 == ~t2_pc~0); 15302#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 15583#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 15738#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 15705#L631 assume !(0 != activate_threads_~tmp___1~0#1); 15706#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 15635#L295 assume !(1 == ~t3_pc~0); 15413#L295-2 is_transmit3_triggered_~__retres1~3#1 := 0; 15414#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 15339#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 15340#L639 assume !(0 != activate_threads_~tmp___2~0#1); 15662#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 15663#L314 assume !(1 == ~t4_pc~0); 15458#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 15457#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 15535#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 15536#L647 assume !(0 != activate_threads_~tmp___3~0#1); 15565#L647-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 15566#L555 assume !(1 == ~M_E~0); 15473#L555-2 assume !(1 == ~T1_E~0); 15474#L560-1 assume !(1 == ~T2_E~0); 15354#L565-1 assume !(1 == ~T3_E~0); 15355#L570-1 assume !(1 == ~T4_E~0); 15425#L575-1 assume !(1 == ~E_1~0); 15426#L580-1 assume !(1 == ~E_2~0); 15617#L585-1 assume 1 == ~E_3~0;~E_3~0 := 2; 15427#L590-1 assume !(1 == ~E_4~0); 15415#L595-1 assume { :end_inline_reset_delta_events } true; 15416#L776-2 [2022-12-13 21:03:34,185 INFO L750 eck$LassoCheckResult]: Loop: 15416#L776-2 assume !false; 15389#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 15390#L477 assume !false; 15483#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 15484#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 15324#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 15325#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 15341#L416 assume !(0 != eval_~tmp~0#1); 15366#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 15544#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 15601#L502-3 assume !(0 == ~M_E~0); 15602#L502-5 assume !(0 == ~T1_E~0); 15626#L507-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 15545#L512-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 15546#L517-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 15522#L522-3 assume 0 == ~E_1~0;~E_1~0 := 1; 15523#L527-3 assume 0 == ~E_2~0;~E_2~0 := 1; 15618#L532-3 assume 0 == ~E_3~0;~E_3~0 := 1; 15552#L537-3 assume !(0 == ~E_4~0); 15553#L542-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 15561#L238-15 assume !(1 == ~m_pc~0); 15611#L238-17 is_master_triggered_~__retres1~0#1 := 0; 15649#L249-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 15530#is_master_triggered_returnLabel#6 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 15449#L615-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 15450#L615-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 15383#L257-15 assume !(1 == ~t1_pc~0); 15384#L257-17 is_transmit1_triggered_~__retres1~1#1 := 0; 17453#L268-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 17451#is_transmit1_triggered_returnLabel#6 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 17450#L623-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 17449#L623-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 17448#L276-15 assume !(1 == ~t2_pc~0); 17444#L276-17 is_transmit2_triggered_~__retres1~2#1 := 0; 17442#L287-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17440#is_transmit2_triggered_returnLabel#6 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 17438#L631-15 assume !(0 != activate_threads_~tmp___1~0#1); 17435#L631-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 17433#L295-15 assume !(1 == ~t3_pc~0); 16495#L295-17 is_transmit3_triggered_~__retres1~3#1 := 0; 17430#L306-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 17429#is_transmit3_triggered_returnLabel#6 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 17426#L639-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 17424#L639-17 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 17422#L314-15 assume 1 == ~t4_pc~0; 17420#L315-5 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 17418#L325-5 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 17416#is_transmit4_triggered_returnLabel#6 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 17414#L647-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 17412#L647-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 17410#L555-3 assume 1 == ~M_E~0;~M_E~0 := 2; 17407#L555-5 assume !(1 == ~T1_E~0); 17405#L560-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 17403#L565-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 17401#L570-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 17399#L575-3 assume 1 == ~E_1~0;~E_1~0 := 2; 17397#L580-3 assume !(1 == ~E_2~0); 17395#L585-3 assume 1 == ~E_3~0;~E_3~0 := 2; 17393#L590-3 assume 1 == ~E_4~0;~E_4~0 := 2; 17391#L595-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 17365#L374-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 17360#L401-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 17354#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 17347#L795 assume !(0 == start_simulation_~tmp~3#1); 17348#L795-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 17376#L374-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 17372#L401-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 17370#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 15721#L750 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 15479#L757 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 15480#stop_simulation_returnLabel#1 start_simulation_#t~ret17#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 15572#L808 assume !(0 != start_simulation_~tmp___0~1#1); 15416#L776-2 [2022-12-13 21:03:34,186 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 21:03:34,186 INFO L85 PathProgramCache]: Analyzing trace with hash 1014532137, now seen corresponding path program 1 times [2022-12-13 21:03:34,186 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 21:03:34,186 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [574136658] [2022-12-13 21:03:34,186 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 21:03:34,186 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 21:03:34,194 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 21:03:34,230 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 21:03:34,230 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 21:03:34,230 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [574136658] [2022-12-13 21:03:34,230 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [574136658] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 21:03:34,230 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 21:03:34,230 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 21:03:34,230 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [838777752] [2022-12-13 21:03:34,230 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 21:03:34,231 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 21:03:34,231 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 21:03:34,231 INFO L85 PathProgramCache]: Analyzing trace with hash -15775971, now seen corresponding path program 1 times [2022-12-13 21:03:34,231 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 21:03:34,231 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1187777636] [2022-12-13 21:03:34,231 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 21:03:34,232 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 21:03:34,239 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 21:03:34,259 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 21:03:34,260 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 21:03:34,260 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1187777636] [2022-12-13 21:03:34,260 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1187777636] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 21:03:34,260 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 21:03:34,260 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 21:03:34,260 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2112274259] [2022-12-13 21:03:34,260 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 21:03:34,261 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 21:03:34,261 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 21:03:34,261 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 21:03:34,261 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 21:03:34,261 INFO L87 Difference]: Start difference. First operand 2201 states and 3143 transitions. cyclomatic complexity: 944 Second operand has 4 states, 4 states have (on average 15.0) internal successors, (60), 3 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 21:03:34,354 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 21:03:34,354 INFO L93 Difference]: Finished difference Result 4550 states and 6445 transitions. [2022-12-13 21:03:34,354 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4550 states and 6445 transitions. [2022-12-13 21:03:34,399 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4372 [2022-12-13 21:03:34,410 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4550 states to 4550 states and 6445 transitions. [2022-12-13 21:03:34,410 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4550 [2022-12-13 21:03:34,413 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4550 [2022-12-13 21:03:34,413 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4550 states and 6445 transitions. [2022-12-13 21:03:34,416 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 21:03:34,416 INFO L218 hiAutomatonCegarLoop]: Abstraction has 4550 states and 6445 transitions. [2022-12-13 21:03:34,419 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4550 states and 6445 transitions. [2022-12-13 21:03:34,453 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4550 to 4494. [2022-12-13 21:03:34,458 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4494 states, 4494 states have (on average 1.4181130396083668) internal successors, (6373), 4493 states have internal predecessors, (6373), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 21:03:34,465 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4494 states to 4494 states and 6373 transitions. [2022-12-13 21:03:34,465 INFO L240 hiAutomatonCegarLoop]: Abstraction has 4494 states and 6373 transitions. [2022-12-13 21:03:34,466 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 21:03:34,466 INFO L428 stractBuchiCegarLoop]: Abstraction has 4494 states and 6373 transitions. [2022-12-13 21:03:34,466 INFO L335 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2022-12-13 21:03:34,467 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4494 states and 6373 transitions. [2022-12-13 21:03:34,484 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4324 [2022-12-13 21:03:34,484 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 21:03:34,484 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 21:03:34,485 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 21:03:34,485 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 21:03:34,486 INFO L748 eck$LassoCheckResult]: Stem: 22451#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 22452#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 22465#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 22461#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 22319#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 22320#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 22150#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 22151#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 22161#L356-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 22162#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 22208#L502 assume !(0 == ~M_E~0); 22209#L502-2 assume !(0 == ~T1_E~0); 22138#L507-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 22139#L512-1 assume !(0 == ~T3_E~0); 22441#L517-1 assume !(0 == ~T4_E~0); 22442#L522-1 assume !(0 == ~E_1~0); 22341#L527-1 assume !(0 == ~E_2~0); 22342#L532-1 assume 0 == ~E_3~0;~E_3~0 := 1; 22456#L537-1 assume !(0 == ~E_4~0); 22598#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 22597#L238 assume !(1 == ~m_pc~0); 22596#L238-2 is_master_triggered_~__retres1~0#1 := 0; 22595#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 22594#is_master_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 22593#L615 assume !(0 != activate_threads_~tmp~1#1); 22592#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 22591#L257 assume !(1 == ~t1_pc~0); 22590#L257-2 is_transmit1_triggered_~__retres1~1#1 := 0; 22589#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 22588#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 22587#L623 assume !(0 != activate_threads_~tmp___0~0#1); 22586#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 22585#L276 assume !(1 == ~t2_pc~0); 22584#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 22582#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 22580#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 22577#L631 assume !(0 != activate_threads_~tmp___1~0#1); 22576#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 22575#L295 assume !(1 == ~t3_pc~0); 22574#L295-2 is_transmit3_triggered_~__retres1~3#1 := 0; 22573#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 22572#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 22571#L639 assume !(0 != activate_threads_~tmp___2~0#1); 22570#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 22569#L314 assume !(1 == ~t4_pc~0); 22568#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 22566#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 22565#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 22564#L647 assume !(0 != activate_threads_~tmp___3~0#1); 22563#L647-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 22562#L555 assume !(1 == ~M_E~0); 22561#L555-2 assume !(1 == ~T1_E~0); 22560#L560-1 assume !(1 == ~T2_E~0); 22559#L565-1 assume !(1 == ~T3_E~0); 22558#L570-1 assume !(1 == ~T4_E~0); 22557#L575-1 assume !(1 == ~E_1~0); 22556#L580-1 assume !(1 == ~E_2~0); 22554#L585-1 assume 1 == ~E_3~0;~E_3~0 := 2; 22555#L590-1 assume !(1 == ~E_4~0); 24374#L595-1 assume { :end_inline_reset_delta_events } true; 24372#L776-2 [2022-12-13 21:03:34,486 INFO L750 eck$LassoCheckResult]: Loop: 24372#L776-2 assume !false; 24369#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 24366#L477 assume !false; 24365#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 24359#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 24355#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 24353#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 24349#L416 assume !(0 != eval_~tmp~0#1); 24350#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 25807#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 25805#L502-3 assume !(0 == ~M_E~0); 25803#L502-5 assume !(0 == ~T1_E~0); 25802#L507-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 25794#L512-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 25792#L517-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 25790#L522-3 assume 0 == ~E_1~0;~E_1~0 := 1; 25786#L527-3 assume 0 == ~E_2~0;~E_2~0 := 1; 25784#L532-3 assume !(0 == ~E_3~0); 25783#L537-3 assume !(0 == ~E_4~0); 25782#L542-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 25781#L238-15 assume !(1 == ~m_pc~0); 25775#L238-17 is_master_triggered_~__retres1~0#1 := 0; 25773#L249-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 25771#is_master_triggered_returnLabel#6 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 25769#L615-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 25767#L615-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 24474#L257-15 assume !(1 == ~t1_pc~0); 24473#L257-17 is_transmit1_triggered_~__retres1~1#1 := 0; 24472#L268-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 24471#is_transmit1_triggered_returnLabel#6 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 24469#L623-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 24468#L623-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 24467#L276-15 assume !(1 == ~t2_pc~0); 24464#L276-17 is_transmit2_triggered_~__retres1~2#1 := 0; 24462#L287-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 24460#is_transmit2_triggered_returnLabel#6 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 24458#L631-15 assume !(0 != activate_threads_~tmp___1~0#1); 24455#L631-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 24453#L295-15 assume !(1 == ~t3_pc~0); 24210#L295-17 is_transmit3_triggered_~__retres1~3#1 := 0; 24448#L306-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 24446#is_transmit3_triggered_returnLabel#6 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 24444#L639-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 24441#L639-17 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 24439#L314-15 assume 1 == ~t4_pc~0; 24436#L315-5 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 24435#L325-5 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 24433#is_transmit4_triggered_returnLabel#6 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 24431#L647-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 24429#L647-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 24427#L555-3 assume 1 == ~M_E~0;~M_E~0 := 2; 24425#L555-5 assume !(1 == ~T1_E~0); 24422#L560-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 24420#L565-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 24418#L570-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 24416#L575-3 assume 1 == ~E_1~0;~E_1~0 := 2; 24414#L580-3 assume !(1 == ~E_2~0); 24412#L585-3 assume !(1 == ~E_3~0); 24409#L590-3 assume 1 == ~E_4~0;~E_4~0 := 2; 24407#L595-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 24400#L374-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 24396#L401-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 24394#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 24393#L795 assume !(0 == start_simulation_~tmp~3#1); 24391#L795-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 24386#L374-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 24382#L401-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 24380#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 24379#L750 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 24378#L757 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 24377#stop_simulation_returnLabel#1 start_simulation_#t~ret17#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 24375#L808 assume !(0 != start_simulation_~tmp___0~1#1); 24372#L776-2 [2022-12-13 21:03:34,486 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 21:03:34,486 INFO L85 PathProgramCache]: Analyzing trace with hash -27236631, now seen corresponding path program 1 times [2022-12-13 21:03:34,486 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 21:03:34,487 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1673070322] [2022-12-13 21:03:34,487 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 21:03:34,487 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 21:03:34,493 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 21:03:34,517 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 21:03:34,517 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 21:03:34,517 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1673070322] [2022-12-13 21:03:34,517 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1673070322] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 21:03:34,517 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 21:03:34,517 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-12-13 21:03:34,517 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [867831763] [2022-12-13 21:03:34,518 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 21:03:34,518 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 21:03:34,518 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 21:03:34,518 INFO L85 PathProgramCache]: Analyzing trace with hash 91145761, now seen corresponding path program 1 times [2022-12-13 21:03:34,518 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 21:03:34,518 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [348953796] [2022-12-13 21:03:34,519 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 21:03:34,519 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 21:03:34,526 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 21:03:34,546 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 21:03:34,546 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 21:03:34,546 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [348953796] [2022-12-13 21:03:34,546 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [348953796] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 21:03:34,547 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 21:03:34,547 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 21:03:34,547 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [436156695] [2022-12-13 21:03:34,547 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 21:03:34,547 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 21:03:34,547 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 21:03:34,548 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 21:03:34,548 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 21:03:34,548 INFO L87 Difference]: Start difference. First operand 4494 states and 6373 transitions. cyclomatic complexity: 1883 Second operand has 3 states, 3 states have (on average 20.0) internal successors, (60), 2 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 21:03:34,578 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 21:03:34,578 INFO L93 Difference]: Finished difference Result 4444 states and 6260 transitions. [2022-12-13 21:03:34,578 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4444 states and 6260 transitions. [2022-12-13 21:03:34,599 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4324 [2022-12-13 21:03:34,617 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4444 states to 4444 states and 6260 transitions. [2022-12-13 21:03:34,617 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4444 [2022-12-13 21:03:34,621 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4444 [2022-12-13 21:03:34,622 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4444 states and 6260 transitions. [2022-12-13 21:03:34,628 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 21:03:34,628 INFO L218 hiAutomatonCegarLoop]: Abstraction has 4444 states and 6260 transitions. [2022-12-13 21:03:34,632 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4444 states and 6260 transitions. [2022-12-13 21:03:34,673 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4444 to 2614. [2022-12-13 21:03:34,678 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2614 states, 2614 states have (on average 1.4020657995409334) internal successors, (3665), 2613 states have internal predecessors, (3665), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 21:03:34,683 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2614 states to 2614 states and 3665 transitions. [2022-12-13 21:03:34,684 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2614 states and 3665 transitions. [2022-12-13 21:03:34,684 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 21:03:34,684 INFO L428 stractBuchiCegarLoop]: Abstraction has 2614 states and 3665 transitions. [2022-12-13 21:03:34,684 INFO L335 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2022-12-13 21:03:34,685 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2614 states and 3665 transitions. [2022-12-13 21:03:34,693 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2500 [2022-12-13 21:03:34,693 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 21:03:34,693 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 21:03:34,695 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 21:03:34,695 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 21:03:34,695 INFO L748 eck$LassoCheckResult]: Stem: 31397#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 31398#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 31413#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 31407#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 31265#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 31266#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 31094#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 31095#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 31105#L356-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 31106#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 31152#L502 assume !(0 == ~M_E~0); 31153#L502-2 assume !(0 == ~T1_E~0); 31083#L507-1 assume !(0 == ~T2_E~0); 31084#L512-1 assume !(0 == ~T3_E~0); 31269#L517-1 assume !(0 == ~T4_E~0); 31059#L522-1 assume !(0 == ~E_1~0); 31060#L527-1 assume !(0 == ~E_2~0); 31287#L532-1 assume 0 == ~E_3~0;~E_3~0 := 1; 31401#L537-1 assume !(0 == ~E_4~0); 31431#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 31432#L238 assume !(1 == ~m_pc~0); 31475#L238-2 is_master_triggered_~__retres1~0#1 := 0; 31476#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 31367#is_master_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 31368#L615 assume !(0 != activate_threads_~tmp~1#1); 31043#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 31044#L257 assume !(1 == ~t1_pc~0); 31160#L257-2 is_transmit1_triggered_~__retres1~1#1 := 0; 31161#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 31141#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 31142#L623 assume !(0 != activate_threads_~tmp___0~0#1); 31112#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 31113#L276 assume !(1 == ~t2_pc~0); 31297#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 31298#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 31508#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 31509#L631 assume !(0 != activate_threads_~tmp___1~0#1); 31466#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 31467#L295 assume !(1 == ~t3_pc~0); 31122#L295-2 is_transmit3_triggered_~__retres1~3#1 := 0; 31123#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 31045#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 31046#L639 assume !(0 != activate_threads_~tmp___2~0#1); 31403#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 31485#L314 assume !(1 == ~t4_pc~0); 31486#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 31445#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 31446#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 31332#L647 assume !(0 != activate_threads_~tmp___3~0#1); 31333#L647-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 31502#L555 assume !(1 == ~M_E~0); 31503#L555-2 assume !(1 == ~T1_E~0); 31479#L560-1 assume !(1 == ~T2_E~0); 31480#L565-1 assume !(1 == ~T3_E~0); 31347#L570-1 assume !(1 == ~T4_E~0); 31348#L575-1 assume !(1 == ~E_1~0); 31334#L580-1 assume !(1 == ~E_2~0); 31335#L585-1 assume 1 == ~E_3~0;~E_3~0 := 2; 31136#L590-1 assume !(1 == ~E_4~0); 31124#L595-1 assume { :end_inline_reset_delta_events } true; 31125#L776-2 [2022-12-13 21:03:34,695 INFO L750 eck$LassoCheckResult]: Loop: 31125#L776-2 assume !false; 33139#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 33133#L477 assume !false; 33132#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 31349#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 31030#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 31031#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 31047#L416 assume !(0 != eval_~tmp~0#1); 31073#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 33449#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 33445#L502-3 assume !(0 == ~M_E~0); 33441#L502-5 assume !(0 == ~T1_E~0); 33435#L507-3 assume !(0 == ~T2_E~0); 33431#L512-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 33426#L517-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 33420#L522-3 assume 0 == ~E_1~0;~E_1~0 := 1; 33414#L527-3 assume 0 == ~E_2~0;~E_2~0 := 1; 33410#L532-3 assume 0 == ~E_3~0;~E_3~0 := 1; 33266#L537-3 assume !(0 == ~E_4~0); 33267#L542-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 33262#L238-15 assume !(1 == ~m_pc~0); 33263#L238-17 is_master_triggered_~__retres1~0#1 := 0; 33252#L249-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 33253#is_master_triggered_returnLabel#6 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 33244#L615-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 33245#L615-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 33240#L257-15 assume !(1 == ~t1_pc~0); 31992#L257-17 is_transmit1_triggered_~__retres1~1#1 := 0; 33237#L268-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 33238#is_transmit1_triggered_returnLabel#6 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 33227#L623-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 33228#L623-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 33220#L276-15 assume 1 == ~t2_pc~0; 33221#L277-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 33328#L287-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 33329#is_transmit2_triggered_returnLabel#6 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 33205#L631-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 33206#L631-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 33202#L295-15 assume !(1 == ~t3_pc~0); 33201#L295-17 is_transmit3_triggered_~__retres1~3#1 := 0; 33200#L306-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 33199#is_transmit3_triggered_returnLabel#6 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 33198#L639-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 33197#L639-17 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 33196#L314-15 assume 1 == ~t4_pc~0; 33194#L315-5 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 33193#L325-5 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 33192#is_transmit4_triggered_returnLabel#6 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 33191#L647-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 33190#L647-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 33189#L555-3 assume 1 == ~M_E~0;~M_E~0 := 2; 33188#L555-5 assume !(1 == ~T1_E~0); 33187#L560-3 assume !(1 == ~T2_E~0); 33186#L565-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 33185#L570-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 33184#L575-3 assume 1 == ~E_1~0;~E_1~0 := 2; 33183#L580-3 assume !(1 == ~E_2~0); 33181#L585-3 assume 1 == ~E_3~0;~E_3~0 := 2; 33180#L590-3 assume 1 == ~E_4~0;~E_4~0 := 2; 33179#L595-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 33175#L374-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 33171#L401-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 33169#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 33167#L795 assume !(0 == start_simulation_~tmp~3#1); 33161#L795-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 33154#L374-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 33150#L401-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 33149#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 33148#L750 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 33146#L757 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 33144#stop_simulation_returnLabel#1 start_simulation_#t~ret17#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 33142#L808 assume !(0 != start_simulation_~tmp___0~1#1); 31125#L776-2 [2022-12-13 21:03:34,695 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 21:03:34,696 INFO L85 PathProgramCache]: Analyzing trace with hash 1911925415, now seen corresponding path program 1 times [2022-12-13 21:03:34,696 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 21:03:34,696 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [522475299] [2022-12-13 21:03:34,696 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 21:03:34,696 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 21:03:34,720 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 21:03:34,750 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 21:03:34,750 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 21:03:34,750 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [522475299] [2022-12-13 21:03:34,750 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [522475299] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 21:03:34,750 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 21:03:34,750 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 21:03:34,751 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1587213222] [2022-12-13 21:03:34,751 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 21:03:34,751 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 21:03:34,751 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 21:03:34,751 INFO L85 PathProgramCache]: Analyzing trace with hash -637224900, now seen corresponding path program 1 times [2022-12-13 21:03:34,751 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 21:03:34,752 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [502148380] [2022-12-13 21:03:34,752 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 21:03:34,752 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 21:03:34,759 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 21:03:34,778 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 21:03:34,778 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 21:03:34,778 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [502148380] [2022-12-13 21:03:34,778 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [502148380] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 21:03:34,778 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 21:03:34,778 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 21:03:34,778 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1728523437] [2022-12-13 21:03:34,779 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 21:03:34,779 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 21:03:34,779 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 21:03:34,779 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 21:03:34,779 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 21:03:34,780 INFO L87 Difference]: Start difference. First operand 2614 states and 3665 transitions. cyclomatic complexity: 1053 Second operand has 4 states, 4 states have (on average 15.0) internal successors, (60), 3 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 21:03:34,845 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 21:03:34,845 INFO L93 Difference]: Finished difference Result 4037 states and 5667 transitions. [2022-12-13 21:03:34,845 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4037 states and 5667 transitions. [2022-12-13 21:03:34,863 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3956 [2022-12-13 21:03:34,876 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4037 states to 4037 states and 5667 transitions. [2022-12-13 21:03:34,876 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4037 [2022-12-13 21:03:34,878 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4037 [2022-12-13 21:03:34,878 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4037 states and 5667 transitions. [2022-12-13 21:03:34,882 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 21:03:34,882 INFO L218 hiAutomatonCegarLoop]: Abstraction has 4037 states and 5667 transitions. [2022-12-13 21:03:34,884 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4037 states and 5667 transitions. [2022-12-13 21:03:34,906 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4037 to 2201. [2022-12-13 21:03:34,908 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2201 states, 2201 states have (on average 1.39709223080418) internal successors, (3075), 2200 states have internal predecessors, (3075), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 21:03:34,912 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2201 states to 2201 states and 3075 transitions. [2022-12-13 21:03:34,912 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2201 states and 3075 transitions. [2022-12-13 21:03:34,912 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 21:03:34,912 INFO L428 stractBuchiCegarLoop]: Abstraction has 2201 states and 3075 transitions. [2022-12-13 21:03:34,912 INFO L335 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2022-12-13 21:03:34,912 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2201 states and 3075 transitions. [2022-12-13 21:03:34,917 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2132 [2022-12-13 21:03:34,917 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 21:03:34,917 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 21:03:34,917 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 21:03:34,917 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 21:03:34,918 INFO L748 eck$LassoCheckResult]: Stem: 38041#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 38042#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 38052#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 38049#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 37924#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 37925#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 37756#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 37757#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 37767#L356-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 37768#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 37811#L502 assume !(0 == ~M_E~0); 37812#L502-2 assume !(0 == ~T1_E~0); 37745#L507-1 assume !(0 == ~T2_E~0); 37746#L512-1 assume !(0 == ~T3_E~0); 37928#L517-1 assume !(0 == ~T4_E~0); 37719#L522-1 assume !(0 == ~E_1~0); 37720#L527-1 assume !(0 == ~E_2~0); 37946#L532-1 assume !(0 == ~E_3~0); 38045#L537-1 assume !(0 == ~E_4~0); 38069#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 38036#L238 assume !(1 == ~m_pc~0); 38037#L238-2 is_master_triggered_~__retres1~0#1 := 0; 37679#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 37680#is_master_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 38012#L615 assume !(0 != activate_threads_~tmp~1#1); 37704#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 37705#L257 assume !(1 == ~t1_pc~0); 37819#L257-2 is_transmit1_triggered_~__retres1~1#1 := 0; 37820#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 37801#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 37671#L623 assume !(0 != activate_threads_~tmp___0~0#1); 37672#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 37668#L276 assume !(1 == ~t2_pc~0); 37669#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 37954#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 38117#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 38084#L631 assume !(0 != activate_threads_~tmp___1~0#1); 38085#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 38009#L295 assume !(1 == ~t3_pc~0); 37782#L295-2 is_transmit3_triggered_~__retres1~3#1 := 0; 37783#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 37706#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 37707#L639 assume !(0 != activate_threads_~tmp___2~0#1); 38038#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 38039#L314 assume !(1 == ~t4_pc~0); 37826#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 37825#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 37905#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 37906#L647 assume !(0 != activate_threads_~tmp___3~0#1); 37935#L647-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 37936#L555 assume !(1 == ~M_E~0); 37841#L555-2 assume !(1 == ~T1_E~0); 37842#L560-1 assume !(1 == ~T2_E~0); 37721#L565-1 assume !(1 == ~T3_E~0); 37722#L570-1 assume !(1 == ~T4_E~0); 37794#L575-1 assume !(1 == ~E_1~0); 37795#L580-1 assume !(1 == ~E_2~0); 37990#L585-1 assume !(1 == ~E_3~0); 37796#L590-1 assume !(1 == ~E_4~0); 37784#L595-1 assume { :end_inline_reset_delta_events } true; 37785#L776-2 [2022-12-13 21:03:34,918 INFO L750 eck$LassoCheckResult]: Loop: 37785#L776-2 assume !false; 39471#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 39468#L477 assume !false; 39466#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 39463#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 39460#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 39459#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 37733#L416 assume !(0 != eval_~tmp~0#1); 37735#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 37976#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 37973#L502-3 assume !(0 == ~M_E~0); 37974#L502-5 assume !(0 == ~T1_E~0); 38000#L507-3 assume !(0 == ~T2_E~0); 37915#L512-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 37916#L517-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 37893#L522-3 assume 0 == ~E_1~0;~E_1~0 := 1; 37894#L527-3 assume 0 == ~E_2~0;~E_2~0 := 1; 37991#L532-3 assume !(0 == ~E_3~0); 38077#L537-3 assume !(0 == ~E_4~0); 39860#L542-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 39859#L238-15 assume !(1 == ~m_pc~0); 39858#L238-17 is_master_triggered_~__retres1~0#1 := 0; 39857#L249-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 39856#is_master_triggered_returnLabel#6 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 39855#L615-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 39854#L615-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 37752#L257-15 assume !(1 == ~t1_pc~0); 37753#L257-17 is_transmit1_triggered_~__retres1~1#1 := 0; 39729#L268-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 39727#is_transmit1_triggered_returnLabel#6 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 39725#L623-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 39586#L623-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 39585#L276-15 assume 1 == ~t2_pc~0; 39584#L277-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 39582#L287-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 39580#is_transmit2_triggered_returnLabel#6 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 39577#L631-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 39576#L631-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 39568#L295-15 assume !(1 == ~t3_pc~0); 39362#L295-17 is_transmit3_triggered_~__retres1~3#1 := 0; 39563#L306-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 39561#is_transmit3_triggered_returnLabel#6 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 39559#L639-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 39556#L639-17 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 39554#L314-15 assume !(1 == ~t4_pc~0); 39552#L314-17 is_transmit4_triggered_~__retres1~4#1 := 0; 39550#L325-5 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 39548#is_transmit4_triggered_returnLabel#6 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 39546#L647-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 39544#L647-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 39542#L555-3 assume 1 == ~M_E~0;~M_E~0 := 2; 39540#L555-5 assume !(1 == ~T1_E~0); 39537#L560-3 assume !(1 == ~T2_E~0); 39535#L565-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 39533#L570-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 39531#L575-3 assume 1 == ~E_1~0;~E_1~0 := 2; 39529#L580-3 assume !(1 == ~E_2~0); 39527#L585-3 assume !(1 == ~E_3~0); 39525#L590-3 assume 1 == ~E_4~0;~E_4~0 := 2; 39523#L595-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 39516#L374-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 39512#L401-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 39510#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 39508#L795 assume !(0 == start_simulation_~tmp~3#1); 39505#L795-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 39497#L374-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 39493#L401-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 39491#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 39490#L750 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 39488#L757 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 39486#stop_simulation_returnLabel#1 start_simulation_#t~ret17#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 39484#L808 assume !(0 != start_simulation_~tmp___0~1#1); 37785#L776-2 [2022-12-13 21:03:34,918 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 21:03:34,918 INFO L85 PathProgramCache]: Analyzing trace with hash 1014534059, now seen corresponding path program 1 times [2022-12-13 21:03:34,918 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 21:03:34,918 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2118618132] [2022-12-13 21:03:34,918 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 21:03:34,918 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 21:03:34,927 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 21:03:34,927 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 21:03:34,933 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 21:03:34,967 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 21:03:34,967 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 21:03:34,967 INFO L85 PathProgramCache]: Analyzing trace with hash -838742177, now seen corresponding path program 1 times [2022-12-13 21:03:34,968 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 21:03:34,968 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [571151133] [2022-12-13 21:03:34,968 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 21:03:34,968 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 21:03:34,973 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 21:03:34,987 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 21:03:34,988 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 21:03:34,988 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [571151133] [2022-12-13 21:03:34,988 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [571151133] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 21:03:34,988 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 21:03:34,988 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 21:03:34,988 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1281778536] [2022-12-13 21:03:34,988 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 21:03:34,988 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 21:03:34,989 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 21:03:34,989 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 21:03:34,989 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 21:03:34,989 INFO L87 Difference]: Start difference. First operand 2201 states and 3075 transitions. cyclomatic complexity: 876 Second operand has 3 states, 3 states have (on average 24.0) internal successors, (72), 3 states have internal predecessors, (72), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 21:03:35,043 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 21:03:35,043 INFO L93 Difference]: Finished difference Result 3747 states and 5191 transitions. [2022-12-13 21:03:35,043 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3747 states and 5191 transitions. [2022-12-13 21:03:35,057 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 3632 [2022-12-13 21:03:35,065 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3747 states to 3747 states and 5191 transitions. [2022-12-13 21:03:35,065 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3747 [2022-12-13 21:03:35,067 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3747 [2022-12-13 21:03:35,067 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3747 states and 5191 transitions. [2022-12-13 21:03:35,072 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 21:03:35,072 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3747 states and 5191 transitions. [2022-12-13 21:03:35,075 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3747 states and 5191 transitions. [2022-12-13 21:03:35,110 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3747 to 3743. [2022-12-13 21:03:35,114 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3743 states, 3743 states have (on average 1.385786802030457) internal successors, (5187), 3742 states have internal predecessors, (5187), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 21:03:35,119 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3743 states to 3743 states and 5187 transitions. [2022-12-13 21:03:35,119 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3743 states and 5187 transitions. [2022-12-13 21:03:35,120 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 21:03:35,120 INFO L428 stractBuchiCegarLoop]: Abstraction has 3743 states and 5187 transitions. [2022-12-13 21:03:35,120 INFO L335 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2022-12-13 21:03:35,120 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3743 states and 5187 transitions. [2022-12-13 21:03:35,128 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 3628 [2022-12-13 21:03:35,128 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 21:03:35,128 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 21:03:35,129 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 21:03:35,129 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 21:03:35,129 INFO L748 eck$LassoCheckResult]: Stem: 43999#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 44000#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 44017#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 44010#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 43873#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 43874#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 43708#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 43709#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 43719#L356-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 43720#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 43762#L502 assume !(0 == ~M_E~0); 43763#L502-2 assume !(0 == ~T1_E~0); 43700#L507-1 assume !(0 == ~T2_E~0); 43701#L512-1 assume !(0 == ~T3_E~0); 43876#L517-1 assume !(0 == ~T4_E~0); 43680#L522-1 assume !(0 == ~E_1~0); 43681#L527-1 assume 0 == ~E_2~0;~E_2~0 := 1; 43894#L532-1 assume !(0 == ~E_3~0); 44005#L537-1 assume !(0 == ~E_4~0); 44033#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 43991#L238 assume !(1 == ~m_pc~0); 43992#L238-2 is_master_triggered_~__retres1~0#1 := 0; 43639#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 43640#is_master_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 43964#L615 assume !(0 != activate_threads_~tmp~1#1); 43663#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 43664#L257 assume !(1 == ~t1_pc~0); 43943#L257-2 is_transmit1_triggered_~__retres1~1#1 := 0; 44146#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 43752#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 43627#L623 assume !(0 != activate_threads_~tmp___0~0#1); 43628#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 43622#L276 assume !(1 == ~t2_pc~0); 43623#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 44044#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 44045#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 44119#L631 assume !(0 != activate_threads_~tmp___1~0#1); 44076#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 43962#L295 assume !(1 == ~t3_pc~0); 43733#L295-2 is_transmit3_triggered_~__retres1~3#1 := 0; 43734#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 43665#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 43666#L639 assume !(0 != activate_threads_~tmp___2~0#1); 43994#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 43995#L314 assume !(1 == ~t4_pc~0); 43777#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 43776#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 44132#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 44131#L647 assume !(0 != activate_threads_~tmp___3~0#1); 43883#L647-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 43884#L555 assume !(1 == ~M_E~0); 43794#L555-2 assume !(1 == ~T1_E~0); 43795#L560-1 assume !(1 == ~T2_E~0); 43682#L565-1 assume !(1 == ~T3_E~0); 43683#L570-1 assume !(1 == ~T4_E~0); 43747#L575-1 assume !(1 == ~E_1~0); 43748#L580-1 assume 1 == ~E_2~0;~E_2~0 := 2; 43942#L585-1 assume !(1 == ~E_3~0); 43749#L590-1 assume !(1 == ~E_4~0); 43735#L595-1 assume { :end_inline_reset_delta_events } true; 43736#L776-2 [2022-12-13 21:03:35,129 INFO L750 eck$LassoCheckResult]: Loop: 43736#L776-2 assume !false; 45499#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 45495#L477 assume !false; 45493#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 45484#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 45480#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 45479#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 45472#L416 assume !(0 != eval_~tmp~0#1); 45473#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 47278#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 47277#L502-3 assume !(0 == ~M_E~0); 47276#L502-5 assume !(0 == ~T1_E~0); 47275#L507-3 assume !(0 == ~T2_E~0); 47274#L512-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 47272#L517-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 47269#L522-3 assume 0 == ~E_1~0;~E_1~0 := 1; 47267#L527-3 assume !(0 == ~E_2~0); 47265#L532-3 assume !(0 == ~E_3~0); 47263#L537-3 assume !(0 == ~E_4~0); 47261#L542-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 47260#L238-15 assume !(1 == ~m_pc~0); 47259#L238-17 is_master_triggered_~__retres1~0#1 := 0; 47257#L249-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 47255#is_master_triggered_returnLabel#6 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 47254#L615-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 47253#L615-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 46078#L257-15 assume !(1 == ~t1_pc~0); 46076#L257-17 is_transmit1_triggered_~__retres1~1#1 := 0; 46074#L268-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 46058#is_transmit1_triggered_returnLabel#6 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 46054#L623-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 46052#L623-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 46014#L276-15 assume 1 == ~t2_pc~0; 46013#L277-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 45952#L287-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 45950#is_transmit2_triggered_returnLabel#6 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 45940#L631-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 45936#L631-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 45632#L295-15 assume !(1 == ~t3_pc~0); 45630#L295-17 is_transmit3_triggered_~__retres1~3#1 := 0; 45628#L306-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 45625#is_transmit3_triggered_returnLabel#6 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 45623#L639-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 45621#L639-17 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 45619#L314-15 assume 1 == ~t4_pc~0; 45616#L315-5 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 45614#L325-5 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 45612#is_transmit4_triggered_returnLabel#6 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 45610#L647-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 45608#L647-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 45606#L555-3 assume 1 == ~M_E~0;~M_E~0 := 2; 45604#L555-5 assume !(1 == ~T1_E~0); 45603#L560-3 assume !(1 == ~T2_E~0); 45601#L565-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 45599#L570-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 45597#L575-3 assume 1 == ~E_1~0;~E_1~0 := 2; 45595#L580-3 assume 1 == ~E_2~0;~E_2~0 := 2; 45592#L585-3 assume !(1 == ~E_3~0); 45590#L590-3 assume 1 == ~E_4~0;~E_4~0 := 2; 45588#L595-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 45534#L374-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 45530#L401-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 45528#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 45526#L795 assume !(0 == start_simulation_~tmp~3#1); 45524#L795-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 45521#L374-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 45518#L401-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 45516#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 45514#L750 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 45512#L757 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 45511#stop_simulation_returnLabel#1 start_simulation_#t~ret17#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 45510#L808 assume !(0 != start_simulation_~tmp___0~1#1); 43736#L776-2 [2022-12-13 21:03:35,130 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 21:03:35,130 INFO L85 PathProgramCache]: Analyzing trace with hash -1231104977, now seen corresponding path program 1 times [2022-12-13 21:03:35,130 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 21:03:35,130 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [169358943] [2022-12-13 21:03:35,130 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 21:03:35,130 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 21:03:35,135 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 21:03:35,150 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 21:03:35,151 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 21:03:35,151 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [169358943] [2022-12-13 21:03:35,151 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [169358943] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 21:03:35,151 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 21:03:35,151 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-12-13 21:03:35,151 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1216124847] [2022-12-13 21:03:35,151 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 21:03:35,152 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 21:03:35,152 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 21:03:35,152 INFO L85 PathProgramCache]: Analyzing trace with hash 531439936, now seen corresponding path program 1 times [2022-12-13 21:03:35,152 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 21:03:35,152 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1616662750] [2022-12-13 21:03:35,152 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 21:03:35,152 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 21:03:35,160 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 21:03:35,187 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 21:03:35,187 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 21:03:35,187 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1616662750] [2022-12-13 21:03:35,187 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1616662750] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 21:03:35,187 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 21:03:35,187 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-12-13 21:03:35,188 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [293294171] [2022-12-13 21:03:35,188 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 21:03:35,188 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 21:03:35,188 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 21:03:35,188 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 21:03:35,188 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 21:03:35,189 INFO L87 Difference]: Start difference. First operand 3743 states and 5187 transitions. cyclomatic complexity: 1446 Second operand has 3 states, 3 states have (on average 20.0) internal successors, (60), 2 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 21:03:35,220 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 21:03:35,220 INFO L93 Difference]: Finished difference Result 2102 states and 2880 transitions. [2022-12-13 21:03:35,221 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2102 states and 2880 transitions. [2022-12-13 21:03:35,228 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2036 [2022-12-13 21:03:35,232 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2102 states to 2102 states and 2880 transitions. [2022-12-13 21:03:35,232 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2102 [2022-12-13 21:03:35,233 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2102 [2022-12-13 21:03:35,233 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2102 states and 2880 transitions. [2022-12-13 21:03:35,235 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 21:03:35,235 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2102 states and 2880 transitions. [2022-12-13 21:03:35,236 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2102 states and 2880 transitions. [2022-12-13 21:03:35,250 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2102 to 2102. [2022-12-13 21:03:35,252 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2102 states, 2102 states have (on average 1.3701236917221693) internal successors, (2880), 2101 states have internal predecessors, (2880), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 21:03:35,255 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2102 states to 2102 states and 2880 transitions. [2022-12-13 21:03:35,255 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2102 states and 2880 transitions. [2022-12-13 21:03:35,256 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 21:03:35,256 INFO L428 stractBuchiCegarLoop]: Abstraction has 2102 states and 2880 transitions. [2022-12-13 21:03:35,256 INFO L335 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2022-12-13 21:03:35,256 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2102 states and 2880 transitions. [2022-12-13 21:03:35,260 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2036 [2022-12-13 21:03:35,260 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 21:03:35,260 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 21:03:35,261 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 21:03:35,261 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 21:03:35,261 INFO L748 eck$LassoCheckResult]: Stem: 49830#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 49831#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 49844#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 49838#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 49725#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 49726#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 49562#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 49563#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 49573#L356-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 49574#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 49616#L502 assume !(0 == ~M_E~0); 49617#L502-2 assume !(0 == ~T1_E~0); 49551#L507-1 assume !(0 == ~T2_E~0); 49552#L512-1 assume !(0 == ~T3_E~0); 49727#L517-1 assume !(0 == ~T4_E~0); 49532#L522-1 assume !(0 == ~E_1~0); 49533#L527-1 assume !(0 == ~E_2~0); 49742#L532-1 assume !(0 == ~E_3~0); 49834#L537-1 assume !(0 == ~E_4~0); 49856#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 49824#L238 assume !(1 == ~m_pc~0); 49825#L238-2 is_master_triggered_~__retres1~0#1 := 0; 49489#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 49490#is_master_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 49804#L615 assume !(0 != activate_threads_~tmp~1#1); 49512#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 49513#L257 assume !(1 == ~t1_pc~0); 49624#L257-2 is_transmit1_triggered_~__retres1~1#1 := 0; 49625#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 49606#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 49481#L623 assume !(0 != activate_threads_~tmp___0~0#1); 49482#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 49476#L276 assume !(1 == ~t2_pc~0); 49477#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 49750#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 49863#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 49870#L631 assume !(0 != activate_threads_~tmp___1~0#1); 49871#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 49801#L295 assume !(1 == ~t3_pc~0); 49587#L295-2 is_transmit3_triggered_~__retres1~3#1 := 0; 49588#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 49514#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 49515#L639 assume !(0 != activate_threads_~tmp___2~0#1); 49826#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 49827#L314 assume !(1 == ~t4_pc~0); 49631#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 49630#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 49706#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 49707#L647 assume !(0 != activate_threads_~tmp___3~0#1); 49733#L647-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 49734#L555 assume !(1 == ~M_E~0); 49646#L555-2 assume !(1 == ~T1_E~0); 49647#L560-1 assume !(1 == ~T2_E~0); 49534#L565-1 assume !(1 == ~T3_E~0); 49535#L570-1 assume !(1 == ~T4_E~0); 49601#L575-1 assume !(1 == ~E_1~0); 49602#L580-1 assume !(1 == ~E_2~0); 49782#L585-1 assume !(1 == ~E_3~0); 49603#L590-1 assume !(1 == ~E_4~0); 49589#L595-1 assume { :end_inline_reset_delta_events } true; 49590#L776-2 [2022-12-13 21:03:35,261 INFO L750 eck$LassoCheckResult]: Loop: 49590#L776-2 assume !false; 49564#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 49565#L477 assume !false; 49656#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 49657#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 49501#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 49502#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 49516#L416 assume !(0 != eval_~tmp~0#1); 49541#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 51547#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 51545#L502-3 assume !(0 == ~M_E~0); 51543#L502-5 assume !(0 == ~T1_E~0); 51541#L507-3 assume !(0 == ~T2_E~0); 51539#L512-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 51537#L517-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 51535#L522-3 assume 0 == ~E_1~0;~E_1~0 := 1; 51534#L527-3 assume !(0 == ~E_2~0); 51533#L532-3 assume !(0 == ~E_3~0); 51532#L537-3 assume !(0 == ~E_4~0); 51531#L542-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 51530#L238-15 assume !(1 == ~m_pc~0); 51529#L238-17 is_master_triggered_~__retres1~0#1 := 0; 51528#L249-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 51527#is_master_triggered_returnLabel#6 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 51526#L615-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 51525#L615-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 51524#L257-15 assume !(1 == ~t1_pc~0); 51441#L257-17 is_transmit1_triggered_~__retres1~1#1 := 0; 51523#L268-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 51522#is_transmit1_triggered_returnLabel#6 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 51521#L623-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 51520#L623-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 51519#L276-15 assume !(1 == ~t2_pc~0); 51517#L276-17 is_transmit2_triggered_~__retres1~2#1 := 0; 51516#L287-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 51515#is_transmit2_triggered_returnLabel#6 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 51514#L631-15 assume !(0 != activate_threads_~tmp___1~0#1); 51512#L631-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 49585#L295-15 assume !(1 == ~t3_pc~0); 49586#L295-17 is_transmit3_triggered_~__retres1~3#1 := 0; 49854#L306-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 49855#is_transmit3_triggered_returnLabel#6 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 49864#L639-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 49835#L639-17 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 49836#L314-15 assume 1 == ~t4_pc~0; 49756#L315-5 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 49757#L325-5 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 49807#is_transmit4_triggered_returnLabel#6 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 49808#L647-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 49823#L647-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 49774#L555-3 assume 1 == ~M_E~0;~M_E~0 := 2; 49495#L555-5 assume !(1 == ~T1_E~0); 49496#L560-3 assume !(1 == ~T2_E~0); 49661#L565-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 49809#L570-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 49777#L575-3 assume 1 == ~E_1~0;~E_1~0 := 2; 49485#L580-3 assume !(1 == ~E_2~0); 49486#L585-3 assume !(1 == ~E_3~0); 49643#L590-3 assume 1 == ~E_4~0;~E_4~0 := 2; 49644#L595-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 49732#L374-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 49569#L401-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 49761#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 49798#L795 assume !(0 == start_simulation_~tmp~3#1); 49800#L795-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 49817#L374-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 49529#L401-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 49599#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 49600#L750 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 49654#L757 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 49655#stop_simulation_returnLabel#1 start_simulation_#t~ret17#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 49739#L808 assume !(0 != start_simulation_~tmp___0~1#1); 49590#L776-2 [2022-12-13 21:03:35,261 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 21:03:35,261 INFO L85 PathProgramCache]: Analyzing trace with hash 1014534059, now seen corresponding path program 2 times [2022-12-13 21:03:35,262 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 21:03:35,262 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1253807778] [2022-12-13 21:03:35,262 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 21:03:35,262 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 21:03:35,267 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 21:03:35,267 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 21:03:35,270 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 21:03:35,276 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 21:03:35,277 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 21:03:35,277 INFO L85 PathProgramCache]: Analyzing trace with hash -484004005, now seen corresponding path program 1 times [2022-12-13 21:03:35,277 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 21:03:35,277 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [581281270] [2022-12-13 21:03:35,277 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 21:03:35,277 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 21:03:35,282 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 21:03:35,307 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 21:03:35,307 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 21:03:35,307 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [581281270] [2022-12-13 21:03:35,307 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [581281270] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 21:03:35,308 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 21:03:35,308 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-12-13 21:03:35,308 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [374649268] [2022-12-13 21:03:35,308 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 21:03:35,308 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 21:03:35,308 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 21:03:35,309 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-12-13 21:03:35,309 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-12-13 21:03:35,309 INFO L87 Difference]: Start difference. First operand 2102 states and 2880 transitions. cyclomatic complexity: 780 Second operand has 5 states, 5 states have (on average 14.4) internal successors, (72), 5 states have internal predecessors, (72), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 21:03:35,400 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 21:03:35,400 INFO L93 Difference]: Finished difference Result 3666 states and 4960 transitions. [2022-12-13 21:03:35,400 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3666 states and 4960 transitions. [2022-12-13 21:03:35,417 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 3596 [2022-12-13 21:03:35,430 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3666 states to 3666 states and 4960 transitions. [2022-12-13 21:03:35,430 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3666 [2022-12-13 21:03:35,433 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3666 [2022-12-13 21:03:35,433 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3666 states and 4960 transitions. [2022-12-13 21:03:35,437 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 21:03:35,438 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3666 states and 4960 transitions. [2022-12-13 21:03:35,441 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3666 states and 4960 transitions. [2022-12-13 21:03:35,479 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3666 to 2126. [2022-12-13 21:03:35,483 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2126 states, 2126 states have (on average 1.3659454374412041) internal successors, (2904), 2125 states have internal predecessors, (2904), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 21:03:35,489 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2126 states to 2126 states and 2904 transitions. [2022-12-13 21:03:35,489 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2126 states and 2904 transitions. [2022-12-13 21:03:35,490 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2022-12-13 21:03:35,490 INFO L428 stractBuchiCegarLoop]: Abstraction has 2126 states and 2904 transitions. [2022-12-13 21:03:35,490 INFO L335 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2022-12-13 21:03:35,490 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2126 states and 2904 transitions. [2022-12-13 21:03:35,498 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2060 [2022-12-13 21:03:35,498 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 21:03:35,498 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 21:03:35,499 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 21:03:35,499 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 21:03:35,500 INFO L748 eck$LassoCheckResult]: Stem: 55620#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 55621#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 55632#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 55628#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 55512#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 55513#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 55345#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 55346#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 55356#L356-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 55357#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 55400#L502 assume !(0 == ~M_E~0); 55401#L502-2 assume !(0 == ~T1_E~0); 55334#L507-1 assume !(0 == ~T2_E~0); 55335#L512-1 assume !(0 == ~T3_E~0); 55516#L517-1 assume !(0 == ~T4_E~0); 55311#L522-1 assume !(0 == ~E_1~0); 55312#L527-1 assume !(0 == ~E_2~0); 55534#L532-1 assume !(0 == ~E_3~0); 55624#L537-1 assume !(0 == ~E_4~0); 55642#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 55612#L238 assume !(1 == ~m_pc~0); 55613#L238-2 is_master_triggered_~__retres1~0#1 := 0; 55271#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 55272#is_master_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 55590#L615 assume !(0 != activate_threads_~tmp~1#1); 55296#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 55297#L257 assume !(1 == ~t1_pc~0); 55408#L257-2 is_transmit1_triggered_~__retres1~1#1 := 0; 55409#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 55389#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 55263#L623 assume !(0 != activate_threads_~tmp___0~0#1); 55264#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 55260#L276 assume !(1 == ~t2_pc~0); 55261#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 55542#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 55650#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 55659#L631 assume !(0 != activate_threads_~tmp___1~0#1); 55660#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 55587#L295 assume !(1 == ~t3_pc~0); 55370#L295-2 is_transmit3_triggered_~__retres1~3#1 := 0; 55371#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 55298#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 55299#L639 assume !(0 != activate_threads_~tmp___2~0#1); 55614#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 55615#L314 assume !(1 == ~t4_pc~0); 55415#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 55414#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 55493#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 55494#L647 assume !(0 != activate_threads_~tmp___3~0#1); 55522#L647-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 55523#L555 assume !(1 == ~M_E~0); 55430#L555-2 assume !(1 == ~T1_E~0); 55431#L560-1 assume !(1 == ~T2_E~0); 55313#L565-1 assume !(1 == ~T3_E~0); 55314#L570-1 assume !(1 == ~T4_E~0); 55382#L575-1 assume !(1 == ~E_1~0); 55383#L580-1 assume !(1 == ~E_2~0); 55574#L585-1 assume !(1 == ~E_3~0); 55384#L590-1 assume !(1 == ~E_4~0); 55372#L595-1 assume { :end_inline_reset_delta_events } true; 55373#L776-2 [2022-12-13 21:03:35,500 INFO L750 eck$LassoCheckResult]: Loop: 55373#L776-2 assume !false; 57356#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 55617#L477 assume !false; 55618#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 56889#L374 assume !(0 == ~m_st~0); 56890#L378 assume !(0 == ~t1_st~0); 56892#L382 assume !(0 == ~t2_st~0); 56887#L386 assume !(0 == ~t3_st~0); 56888#L390 assume !(0 == ~t4_st~0);exists_runnable_thread_~__retres1~5#1 := 0; 56891#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 56360#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 56361#L416 assume !(0 != eval_~tmp~0#1); 56879#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 56878#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 56877#L502-3 assume !(0 == ~M_E~0); 56876#L502-5 assume !(0 == ~T1_E~0); 56875#L507-3 assume !(0 == ~T2_E~0); 56874#L512-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 55704#L517-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 55479#L522-3 assume 0 == ~E_1~0;~E_1~0 := 1; 55480#L527-3 assume !(0 == ~E_2~0); 55575#L532-3 assume !(0 == ~E_3~0); 55510#L537-3 assume !(0 == ~E_4~0); 55511#L542-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 55518#L238-15 assume !(1 == ~m_pc~0); 55569#L238-17 is_master_triggered_~__retres1~0#1 := 0; 57081#L249-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 55487#is_master_triggered_returnLabel#6 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 55488#L615-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 57080#L615-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 55341#L257-15 assume !(1 == ~t1_pc~0); 55342#L257-17 is_transmit1_triggered_~__retres1~1#1 := 0; 55555#L268-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 57079#is_transmit1_triggered_returnLabel#6 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 57078#L623-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 55604#L623-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 55605#L276-15 assume !(1 == ~t2_pc~0); 55691#L276-17 is_transmit2_triggered_~__retres1~2#1 := 0; 55461#L287-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 55462#is_transmit2_triggered_returnLabel#6 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 55697#L631-15 assume !(0 != activate_threads_~tmp___1~0#1); 55567#L631-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 55368#L295-15 assume !(1 == ~t3_pc~0); 55369#L295-17 is_transmit3_triggered_~__retres1~3#1 := 0; 57259#L306-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 57258#is_transmit3_triggered_returnLabel#6 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 57257#L639-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 57256#L639-17 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 57255#L314-15 assume 1 == ~t4_pc~0; 57253#L315-5 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 57252#L325-5 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 57251#is_transmit4_triggered_returnLabel#6 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 57250#L647-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 57249#L647-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 57248#L555-3 assume 1 == ~M_E~0;~M_E~0 := 2; 57247#L555-5 assume !(1 == ~T1_E~0); 57246#L560-3 assume !(1 == ~T2_E~0); 57245#L565-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 57244#L570-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 57243#L575-3 assume 1 == ~E_1~0;~E_1~0 := 2; 57242#L580-3 assume !(1 == ~E_2~0); 57241#L585-3 assume !(1 == ~E_3~0); 57240#L590-3 assume 1 == ~E_4~0;~E_4~0 := 2; 57239#L595-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 55682#L374-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 55352#L401-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 55554#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 55585#L795 assume !(0 == start_simulation_~tmp~3#1); 55586#L795-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 55616#L374-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 57366#L401-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 57365#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 57364#L750 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 57363#L757 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 57362#stop_simulation_returnLabel#1 start_simulation_#t~ret17#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 57360#L808 assume !(0 != start_simulation_~tmp___0~1#1); 55373#L776-2 [2022-12-13 21:03:35,500 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 21:03:35,501 INFO L85 PathProgramCache]: Analyzing trace with hash 1014534059, now seen corresponding path program 3 times [2022-12-13 21:03:35,501 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 21:03:35,501 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [744590094] [2022-12-13 21:03:35,501 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 21:03:35,501 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 21:03:35,510 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 21:03:35,511 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 21:03:35,516 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 21:03:35,527 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 21:03:35,527 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 21:03:35,528 INFO L85 PathProgramCache]: Analyzing trace with hash 1567438159, now seen corresponding path program 1 times [2022-12-13 21:03:35,528 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 21:03:35,528 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [37587358] [2022-12-13 21:03:35,528 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 21:03:35,528 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 21:03:35,538 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 21:03:35,601 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 21:03:35,601 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 21:03:35,601 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [37587358] [2022-12-13 21:03:35,601 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [37587358] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 21:03:35,601 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 21:03:35,601 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-12-13 21:03:35,601 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1504279983] [2022-12-13 21:03:35,601 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 21:03:35,602 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 21:03:35,602 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 21:03:35,602 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-12-13 21:03:35,602 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-12-13 21:03:35,603 INFO L87 Difference]: Start difference. First operand 2126 states and 2904 transitions. cyclomatic complexity: 780 Second operand has 5 states, 5 states have (on average 15.2) internal successors, (76), 5 states have internal predecessors, (76), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 21:03:35,720 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 21:03:35,720 INFO L93 Difference]: Finished difference Result 4194 states and 5677 transitions. [2022-12-13 21:03:35,720 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4194 states and 5677 transitions. [2022-12-13 21:03:35,734 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4128 [2022-12-13 21:03:35,746 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4194 states to 4194 states and 5677 transitions. [2022-12-13 21:03:35,746 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4194 [2022-12-13 21:03:35,750 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4194 [2022-12-13 21:03:35,750 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4194 states and 5677 transitions. [2022-12-13 21:03:35,753 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 21:03:35,754 INFO L218 hiAutomatonCegarLoop]: Abstraction has 4194 states and 5677 transitions. [2022-12-13 21:03:35,758 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4194 states and 5677 transitions. [2022-12-13 21:03:35,786 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4194 to 2186. [2022-12-13 21:03:35,790 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2186 states, 2186 states have (on average 1.348124428179323) internal successors, (2947), 2185 states have internal predecessors, (2947), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 21:03:35,795 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2186 states to 2186 states and 2947 transitions. [2022-12-13 21:03:35,795 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2186 states and 2947 transitions. [2022-12-13 21:03:35,796 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-12-13 21:03:35,796 INFO L428 stractBuchiCegarLoop]: Abstraction has 2186 states and 2947 transitions. [2022-12-13 21:03:35,796 INFO L335 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2022-12-13 21:03:35,796 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2186 states and 2947 transitions. [2022-12-13 21:03:35,801 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2120 [2022-12-13 21:03:35,801 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 21:03:35,802 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 21:03:35,803 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 21:03:35,803 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 21:03:35,803 INFO L748 eck$LassoCheckResult]: Stem: 61959#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 61960#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 61973#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 61967#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 61848#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 61849#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 61681#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 61682#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 61692#L356-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 61693#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 61735#L502 assume !(0 == ~M_E~0); 61736#L502-2 assume !(0 == ~T1_E~0); 61670#L507-1 assume !(0 == ~T2_E~0); 61671#L512-1 assume !(0 == ~T3_E~0); 61852#L517-1 assume !(0 == ~T4_E~0); 61645#L522-1 assume !(0 == ~E_1~0); 61646#L527-1 assume !(0 == ~E_2~0); 61871#L532-1 assume !(0 == ~E_3~0); 61963#L537-1 assume !(0 == ~E_4~0); 61989#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 61954#L238 assume !(1 == ~m_pc~0); 61955#L238-2 is_master_triggered_~__retres1~0#1 := 0; 61604#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 61605#is_master_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 61931#L615 assume !(0 != activate_threads_~tmp~1#1); 61629#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 61630#L257 assume !(1 == ~t1_pc~0); 61743#L257-2 is_transmit1_triggered_~__retres1~1#1 := 0; 61744#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 61725#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 61596#L623 assume !(0 != activate_threads_~tmp___0~0#1); 61597#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 61593#L276 assume !(1 == ~t2_pc~0); 61594#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 61879#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 61995#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 62004#L631 assume !(0 != activate_threads_~tmp___1~0#1); 62005#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 61928#L295 assume !(1 == ~t3_pc~0); 61706#L295-2 is_transmit3_triggered_~__retres1~3#1 := 0; 61707#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 61631#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 61632#L639 assume !(0 != activate_threads_~tmp___2~0#1); 61956#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 61957#L314 assume !(1 == ~t4_pc~0); 61750#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 61749#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 61830#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 61831#L647 assume !(0 != activate_threads_~tmp___3~0#1); 61861#L647-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 61862#L555 assume !(1 == ~M_E~0); 61766#L555-2 assume !(1 == ~T1_E~0); 61767#L560-1 assume !(1 == ~T2_E~0); 61647#L565-1 assume !(1 == ~T3_E~0); 61648#L570-1 assume !(1 == ~T4_E~0); 61718#L575-1 assume !(1 == ~E_1~0); 61719#L580-1 assume !(1 == ~E_2~0); 61912#L585-1 assume !(1 == ~E_3~0); 61720#L590-1 assume !(1 == ~E_4~0); 61708#L595-1 assume { :end_inline_reset_delta_events } true; 61709#L776-2 [2022-12-13 21:03:35,803 INFO L750 eck$LassoCheckResult]: Loop: 61709#L776-2 assume !false; 62358#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 62355#L477 assume !false; 62354#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 62350#L374 assume !(0 == ~m_st~0); 62351#L378 assume !(0 == ~t1_st~0); 62353#L382 assume !(0 == ~t2_st~0); 62348#L386 assume !(0 == ~t3_st~0); 62349#L390 assume !(0 == ~t4_st~0);exists_runnable_thread_~__retres1~5#1 := 0; 62352#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 62328#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 62329#L416 assume !(0 != eval_~tmp~0#1); 63198#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 63197#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 63196#L502-3 assume !(0 == ~M_E~0); 63195#L502-5 assume !(0 == ~T1_E~0); 63194#L507-3 assume !(0 == ~T2_E~0); 63193#L512-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 63192#L517-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 63191#L522-3 assume 0 == ~E_1~0;~E_1~0 := 1; 63190#L527-3 assume !(0 == ~E_2~0); 63189#L532-3 assume !(0 == ~E_3~0); 63188#L537-3 assume !(0 == ~E_4~0); 61856#L542-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 61857#L238-15 assume !(1 == ~m_pc~0); 61908#L238-17 is_master_triggered_~__retres1~0#1 := 0; 62552#L249-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 62553#is_master_triggered_returnLabel#6 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 62476#L615-15 assume !(0 != activate_threads_~tmp~1#1); 62477#L615-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 62453#L257-15 assume !(1 == ~t1_pc~0); 62452#L257-17 is_transmit1_triggered_~__retres1~1#1 := 0; 62451#L268-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 62450#is_transmit1_triggered_returnLabel#6 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 62449#L623-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 62447#L623-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 62445#L276-15 assume !(1 == ~t2_pc~0); 62442#L276-17 is_transmit2_triggered_~__retres1~2#1 := 0; 62440#L287-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 62438#is_transmit2_triggered_returnLabel#6 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 62436#L631-15 assume !(0 != activate_threads_~tmp___1~0#1); 62433#L631-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 62431#L295-15 assume !(1 == ~t3_pc~0); 62313#L295-17 is_transmit3_triggered_~__retres1~3#1 := 0; 62428#L306-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 62426#is_transmit3_triggered_returnLabel#6 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 62424#L639-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 62422#L639-17 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 62421#L314-15 assume 1 == ~t4_pc~0; 62418#L315-5 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 62416#L325-5 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 62414#is_transmit4_triggered_returnLabel#6 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 62412#L647-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 62410#L647-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 62407#L555-3 assume 1 == ~M_E~0;~M_E~0 := 2; 62405#L555-5 assume !(1 == ~T1_E~0); 62403#L560-3 assume !(1 == ~T2_E~0); 62401#L565-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 62399#L570-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 62397#L575-3 assume 1 == ~E_1~0;~E_1~0 := 2; 62395#L580-3 assume !(1 == ~E_2~0); 62393#L585-3 assume !(1 == ~E_3~0); 62391#L590-3 assume 1 == ~E_4~0;~E_4~0 := 2; 62389#L595-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 62385#L374-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 62381#L401-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 62379#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 62376#L795 assume !(0 == start_simulation_~tmp~3#1); 62374#L795-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 62371#L374-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 62368#L401-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 62367#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 62366#L750 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 62365#L757 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 62363#stop_simulation_returnLabel#1 start_simulation_#t~ret17#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 62361#L808 assume !(0 != start_simulation_~tmp___0~1#1); 61709#L776-2 [2022-12-13 21:03:35,803 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 21:03:35,804 INFO L85 PathProgramCache]: Analyzing trace with hash 1014534059, now seen corresponding path program 4 times [2022-12-13 21:03:35,804 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 21:03:35,804 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [740036295] [2022-12-13 21:03:35,804 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 21:03:35,804 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 21:03:35,812 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 21:03:35,812 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 21:03:35,817 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 21:03:35,825 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 21:03:35,826 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 21:03:35,826 INFO L85 PathProgramCache]: Analyzing trace with hash -788367091, now seen corresponding path program 1 times [2022-12-13 21:03:35,826 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 21:03:35,826 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [28606886] [2022-12-13 21:03:35,826 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 21:03:35,826 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 21:03:35,840 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 21:03:35,860 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 21:03:35,860 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 21:03:35,860 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [28606886] [2022-12-13 21:03:35,860 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [28606886] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 21:03:35,860 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 21:03:35,861 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 21:03:35,861 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1343051672] [2022-12-13 21:03:35,861 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 21:03:35,861 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 21:03:35,861 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 21:03:35,861 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 21:03:35,861 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 21:03:35,862 INFO L87 Difference]: Start difference. First operand 2186 states and 2947 transitions. cyclomatic complexity: 763 Second operand has 3 states, 3 states have (on average 25.333333333333332) internal successors, (76), 3 states have internal predecessors, (76), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 21:03:35,899 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 21:03:35,899 INFO L93 Difference]: Finished difference Result 3576 states and 4749 transitions. [2022-12-13 21:03:35,899 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3576 states and 4749 transitions. [2022-12-13 21:03:35,911 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 3508 [2022-12-13 21:03:35,920 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3576 states to 3576 states and 4749 transitions. [2022-12-13 21:03:35,921 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3576 [2022-12-13 21:03:35,923 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3576 [2022-12-13 21:03:35,923 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3576 states and 4749 transitions. [2022-12-13 21:03:35,926 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 21:03:35,926 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3576 states and 4749 transitions. [2022-12-13 21:03:35,929 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3576 states and 4749 transitions. [2022-12-13 21:03:35,960 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3576 to 3452. [2022-12-13 21:03:35,965 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3452 states, 3452 states have (on average 1.3311123986095017) internal successors, (4595), 3451 states have internal predecessors, (4595), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 21:03:35,972 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3452 states to 3452 states and 4595 transitions. [2022-12-13 21:03:35,972 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3452 states and 4595 transitions. [2022-12-13 21:03:35,973 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 21:03:35,973 INFO L428 stractBuchiCegarLoop]: Abstraction has 3452 states and 4595 transitions. [2022-12-13 21:03:35,973 INFO L335 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2022-12-13 21:03:35,973 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3452 states and 4595 transitions. [2022-12-13 21:03:35,982 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 3384 [2022-12-13 21:03:35,982 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 21:03:35,982 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 21:03:35,982 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 21:03:35,983 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 21:03:35,983 INFO L748 eck$LassoCheckResult]: Stem: 67728#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 67729#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 67742#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 67736#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 67615#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 67616#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 67448#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 67449#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 67459#L356-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 67460#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 67502#L502 assume !(0 == ~M_E~0); 67503#L502-2 assume !(0 == ~T1_E~0); 67440#L507-1 assume !(0 == ~T2_E~0); 67441#L512-1 assume !(0 == ~T3_E~0); 67617#L517-1 assume !(0 == ~T4_E~0); 67420#L522-1 assume !(0 == ~E_1~0); 67421#L527-1 assume !(0 == ~E_2~0); 67636#L532-1 assume !(0 == ~E_3~0); 67732#L537-1 assume !(0 == ~E_4~0); 67756#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 67721#L238 assume !(1 == ~m_pc~0); 67722#L238-2 is_master_triggered_~__retres1~0#1 := 0; 67378#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 67379#is_master_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 67697#L615 assume !(0 != activate_threads_~tmp~1#1); 67402#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 67403#L257 assume !(1 == ~t1_pc~0); 67510#L257-2 is_transmit1_triggered_~__retres1~1#1 := 0; 67511#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 67492#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 67366#L623 assume !(0 != activate_threads_~tmp___0~0#1); 67367#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 67361#L276 assume !(1 == ~t2_pc~0); 67362#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 67647#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 67763#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 67772#L631 assume !(0 != activate_threads_~tmp___1~0#1); 67773#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 67696#L295 assume !(1 == ~t3_pc~0); 67473#L295-2 is_transmit3_triggered_~__retres1~3#1 := 0; 67474#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 67404#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 67405#L639 assume !(0 != activate_threads_~tmp___2~0#1); 67724#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 67725#L314 assume !(1 == ~t4_pc~0); 67517#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 67516#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 67596#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 67597#L647 assume !(0 != activate_threads_~tmp___3~0#1); 67624#L647-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 67625#L555 assume !(1 == ~M_E~0); 67532#L555-2 assume !(1 == ~T1_E~0); 67533#L560-1 assume !(1 == ~T2_E~0); 67422#L565-1 assume !(1 == ~T3_E~0); 67423#L570-1 assume !(1 == ~T4_E~0); 67487#L575-1 assume !(1 == ~E_1~0); 67488#L580-1 assume !(1 == ~E_2~0); 67677#L585-1 assume !(1 == ~E_3~0); 67489#L590-1 assume !(1 == ~E_4~0); 67475#L595-1 assume { :end_inline_reset_delta_events } true; 67476#L776-2 assume !false; 67906#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 67907#L477 [2022-12-13 21:03:35,983 INFO L750 eck$LassoCheckResult]: Loop: 67907#L477 assume !false; 69888#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 69886#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 69885#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 69884#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 69883#L416 assume 0 != eval_~tmp~0#1; 67872#L416-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 67865#L424 assume !(0 != eval_~tmp_ndt_1~0#1); 67867#L421 assume !(0 == ~t1_st~0); 69775#L435 assume !(0 == ~t2_st~0); 69765#L449 assume !(0 == ~t3_st~0); 69346#L463 assume !(0 == ~t4_st~0); 67907#L477 [2022-12-13 21:03:35,984 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 21:03:35,984 INFO L85 PathProgramCache]: Analyzing trace with hash 9663309, now seen corresponding path program 1 times [2022-12-13 21:03:35,984 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 21:03:35,984 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1573794612] [2022-12-13 21:03:35,984 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 21:03:35,984 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 21:03:35,992 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 21:03:35,993 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 21:03:35,998 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 21:03:36,007 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 21:03:36,007 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 21:03:36,007 INFO L85 PathProgramCache]: Analyzing trace with hash 839567500, now seen corresponding path program 1 times [2022-12-13 21:03:36,008 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 21:03:36,008 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [814011659] [2022-12-13 21:03:36,008 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 21:03:36,008 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 21:03:36,011 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 21:03:36,011 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 21:03:36,013 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 21:03:36,014 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 21:03:36,014 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 21:03:36,015 INFO L85 PathProgramCache]: Analyzing trace with hash -1729123880, now seen corresponding path program 1 times [2022-12-13 21:03:36,015 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 21:03:36,015 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [997665144] [2022-12-13 21:03:36,015 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 21:03:36,015 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 21:03:36,023 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 21:03:36,045 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 21:03:36,046 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 21:03:36,046 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [997665144] [2022-12-13 21:03:36,046 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [997665144] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 21:03:36,046 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 21:03:36,046 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 21:03:36,046 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [40816257] [2022-12-13 21:03:36,046 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 21:03:36,105 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 21:03:36,105 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 21:03:36,105 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 21:03:36,105 INFO L87 Difference]: Start difference. First operand 3452 states and 4595 transitions. cyclomatic complexity: 1146 Second operand has 3 states, 3 states have (on average 24.666666666666668) internal successors, (74), 3 states have internal predecessors, (74), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 21:03:36,156 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 21:03:36,156 INFO L93 Difference]: Finished difference Result 6396 states and 8409 transitions. [2022-12-13 21:03:36,156 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6396 states and 8409 transitions. [2022-12-13 21:03:36,180 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 6266 [2022-12-13 21:03:36,199 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6396 states to 6396 states and 8409 transitions. [2022-12-13 21:03:36,200 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6396 [2022-12-13 21:03:36,204 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6396 [2022-12-13 21:03:36,204 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6396 states and 8409 transitions. [2022-12-13 21:03:36,208 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 21:03:36,208 INFO L218 hiAutomatonCegarLoop]: Abstraction has 6396 states and 8409 transitions. [2022-12-13 21:03:36,212 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6396 states and 8409 transitions. [2022-12-13 21:03:36,257 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6396 to 6176. [2022-12-13 21:03:36,262 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6176 states, 6176 states have (on average 1.3175194300518134) internal successors, (8137), 6175 states have internal predecessors, (8137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 21:03:36,289 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6176 states to 6176 states and 8137 transitions. [2022-12-13 21:03:36,289 INFO L240 hiAutomatonCegarLoop]: Abstraction has 6176 states and 8137 transitions. [2022-12-13 21:03:36,290 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 21:03:36,290 INFO L428 stractBuchiCegarLoop]: Abstraction has 6176 states and 8137 transitions. [2022-12-13 21:03:36,290 INFO L335 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2022-12-13 21:03:36,290 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6176 states and 8137 transitions. [2022-12-13 21:03:36,305 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 6046 [2022-12-13 21:03:36,305 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 21:03:36,305 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 21:03:36,306 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 21:03:36,306 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 21:03:36,306 INFO L748 eck$LassoCheckResult]: Stem: 77609#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 77610#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 77623#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 77619#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 77471#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 77472#L341-2 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 77679#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 77605#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 77606#L356-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 77587#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 77588#L502 assume !(0 == ~M_E~0); 77539#L502-2 assume !(0 == ~T1_E~0); 77540#L507-1 assume !(0 == ~T2_E~0); 77475#L512-1 assume !(0 == ~T3_E~0); 77476#L517-1 assume !(0 == ~T4_E~0); 77269#L522-1 assume !(0 == ~E_1~0); 77270#L527-1 assume !(0 == ~E_2~0); 77613#L532-1 assume !(0 == ~E_3~0); 77614#L537-1 assume !(0 == ~E_4~0); 77638#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 77639#L238 assume !(1 == ~m_pc~0); 77677#L238-2 is_master_triggered_~__retres1~0#1 := 0; 77678#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 77571#is_master_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 77572#L615 assume !(0 != activate_threads_~tmp~1#1); 77253#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 77254#L257 assume !(1 == ~t1_pc~0); 77369#L257-2 is_transmit1_triggered_~__retres1~1#1 := 0; 77370#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 77350#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 77351#L623 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 77221#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 77217#L276 assume !(1 == ~t2_pc~0); 77218#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 77507#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 77644#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 77652#L631 assume !(0 != activate_threads_~tmp___1~0#1); 77653#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 77565#L295 assume !(1 == ~t3_pc~0); 77330#L295-2 is_transmit3_triggered_~__retres1~3#1 := 0; 77331#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 77255#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 77256#L639 assume !(0 != activate_threads_~tmp___2~0#1); 77603#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 77604#L314 assume !(1 == ~t4_pc~0); 77376#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 77375#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 77453#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 77454#L647 assume !(0 != activate_threads_~tmp___3~0#1); 77484#L647-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 77485#L555 assume !(1 == ~M_E~0); 77391#L555-2 assume !(1 == ~T1_E~0); 77392#L560-1 assume !(1 == ~T2_E~0); 77271#L565-1 assume !(1 == ~T3_E~0); 77272#L570-1 assume !(1 == ~T4_E~0); 77342#L575-1 assume !(1 == ~E_1~0); 77343#L580-1 assume !(1 == ~E_2~0); 80299#L585-1 assume !(1 == ~E_3~0); 77344#L590-1 assume !(1 == ~E_4~0); 77345#L595-1 assume { :end_inline_reset_delta_events } true; 78477#L776-2 assume !false; 78478#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 78451#L477 [2022-12-13 21:03:36,307 INFO L750 eck$LassoCheckResult]: Loop: 78451#L477 assume !false; 78452#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 78444#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 78445#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 78438#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 78439#L416 assume 0 != eval_~tmp~0#1; 78432#L416-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 78433#L424 assume !(0 != eval_~tmp_ndt_1~0#1); 78427#L421 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 78424#L438 assume !(0 != eval_~tmp_ndt_2~0#1); 78425#L435 assume !(0 == ~t2_st~0); 80276#L449 assume !(0 == ~t3_st~0); 80271#L463 assume !(0 == ~t4_st~0); 78451#L477 [2022-12-13 21:03:36,307 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 21:03:36,307 INFO L85 PathProgramCache]: Analyzing trace with hash 995820945, now seen corresponding path program 1 times [2022-12-13 21:03:36,307 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 21:03:36,307 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1146093485] [2022-12-13 21:03:36,307 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 21:03:36,307 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 21:03:36,314 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 21:03:36,327 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 21:03:36,327 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 21:03:36,328 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1146093485] [2022-12-13 21:03:36,328 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1146093485] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 21:03:36,328 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 21:03:36,328 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 21:03:36,328 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1507197027] [2022-12-13 21:03:36,328 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 21:03:36,328 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 21:03:36,329 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 21:03:36,329 INFO L85 PathProgramCache]: Analyzing trace with hash 109617948, now seen corresponding path program 1 times [2022-12-13 21:03:36,329 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 21:03:36,329 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [912618391] [2022-12-13 21:03:36,329 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 21:03:36,329 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 21:03:36,332 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 21:03:36,332 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 21:03:36,334 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 21:03:36,335 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 21:03:36,407 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 21:03:36,407 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 21:03:36,407 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 21:03:36,408 INFO L87 Difference]: Start difference. First operand 6176 states and 8137 transitions. cyclomatic complexity: 1964 Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 21:03:36,432 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 21:03:36,432 INFO L93 Difference]: Finished difference Result 6118 states and 8062 transitions. [2022-12-13 21:03:36,432 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6118 states and 8062 transitions. [2022-12-13 21:03:36,452 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 6046 [2022-12-13 21:03:36,469 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6118 states to 6118 states and 8062 transitions. [2022-12-13 21:03:36,469 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6118 [2022-12-13 21:03:36,472 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6118 [2022-12-13 21:03:36,473 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6118 states and 8062 transitions. [2022-12-13 21:03:36,476 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 21:03:36,476 INFO L218 hiAutomatonCegarLoop]: Abstraction has 6118 states and 8062 transitions. [2022-12-13 21:03:36,480 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6118 states and 8062 transitions. [2022-12-13 21:03:36,524 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6118 to 6118. [2022-12-13 21:03:36,531 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6118 states, 6118 states have (on average 1.317750898986597) internal successors, (8062), 6117 states have internal predecessors, (8062), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 21:03:36,542 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6118 states to 6118 states and 8062 transitions. [2022-12-13 21:03:36,542 INFO L240 hiAutomatonCegarLoop]: Abstraction has 6118 states and 8062 transitions. [2022-12-13 21:03:36,542 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 21:03:36,543 INFO L428 stractBuchiCegarLoop]: Abstraction has 6118 states and 8062 transitions. [2022-12-13 21:03:36,543 INFO L335 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2022-12-13 21:03:36,543 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6118 states and 8062 transitions. [2022-12-13 21:03:36,558 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 6046 [2022-12-13 21:03:36,558 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 21:03:36,558 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 21:03:36,559 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 21:03:36,559 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 21:03:36,559 INFO L748 eck$LassoCheckResult]: Stem: 89886#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 89887#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 89898#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 89894#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 89769#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 89770#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 89604#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 89605#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 89615#L356-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 89616#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 89657#L502 assume !(0 == ~M_E~0); 89658#L502-2 assume !(0 == ~T1_E~0); 89593#L507-1 assume !(0 == ~T2_E~0); 89594#L512-1 assume !(0 == ~T3_E~0); 89773#L517-1 assume !(0 == ~T4_E~0); 89569#L522-1 assume !(0 == ~E_1~0); 89570#L527-1 assume !(0 == ~E_2~0); 89791#L532-1 assume !(0 == ~E_3~0); 89890#L537-1 assume !(0 == ~E_4~0); 89912#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 89879#L238 assume !(1 == ~m_pc~0); 89880#L238-2 is_master_triggered_~__retres1~0#1 := 0; 89528#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 89529#is_master_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 89855#L615 assume !(0 != activate_threads_~tmp~1#1); 89553#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 89554#L257 assume !(1 == ~t1_pc~0); 89665#L257-2 is_transmit1_triggered_~__retres1~1#1 := 0; 89666#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 89647#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 89520#L623 assume !(0 != activate_threads_~tmp___0~0#1); 89521#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 89517#L276 assume !(1 == ~t2_pc~0); 89518#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 89799#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 89921#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 89930#L631 assume !(0 != activate_threads_~tmp___1~0#1); 89931#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 89852#L295 assume !(1 == ~t3_pc~0); 89628#L295-2 is_transmit3_triggered_~__retres1~3#1 := 0; 89629#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 89555#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 89556#L639 assume !(0 != activate_threads_~tmp___2~0#1); 89881#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 89882#L314 assume !(1 == ~t4_pc~0); 89672#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 89671#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 89750#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 89751#L647 assume !(0 != activate_threads_~tmp___3~0#1); 89781#L647-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 89782#L555 assume !(1 == ~M_E~0); 89687#L555-2 assume !(1 == ~T1_E~0); 89688#L560-1 assume !(1 == ~T2_E~0); 89571#L565-1 assume !(1 == ~T3_E~0); 89572#L570-1 assume !(1 == ~T4_E~0); 89640#L575-1 assume !(1 == ~E_1~0); 89641#L580-1 assume !(1 == ~E_2~0); 89835#L585-1 assume !(1 == ~E_3~0); 89642#L590-1 assume !(1 == ~E_4~0); 89630#L595-1 assume { :end_inline_reset_delta_events } true; 89631#L776-2 assume !false; 93136#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 93131#L477 [2022-12-13 21:03:36,559 INFO L750 eck$LassoCheckResult]: Loop: 93131#L477 assume !false; 93105#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 93096#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 93091#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 93085#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 93079#L416 assume 0 != eval_~tmp~0#1; 93078#L416-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 93074#L424 assume !(0 != eval_~tmp_ndt_1~0#1); 93072#L421 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 92782#L438 assume !(0 != eval_~tmp_ndt_2~0#1); 93063#L435 assume !(0 == ~t2_st~0); 93165#L449 assume !(0 == ~t3_st~0); 93135#L463 assume !(0 == ~t4_st~0); 93131#L477 [2022-12-13 21:03:36,560 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 21:03:36,584 INFO L85 PathProgramCache]: Analyzing trace with hash 9663309, now seen corresponding path program 2 times [2022-12-13 21:03:36,584 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 21:03:36,584 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [304047142] [2022-12-13 21:03:36,584 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 21:03:36,584 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 21:03:36,592 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 21:03:36,592 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 21:03:36,597 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 21:03:36,605 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 21:03:36,606 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 21:03:36,606 INFO L85 PathProgramCache]: Analyzing trace with hash 109617948, now seen corresponding path program 2 times [2022-12-13 21:03:36,606 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 21:03:36,606 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [164425458] [2022-12-13 21:03:36,606 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 21:03:36,606 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 21:03:36,609 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 21:03:36,609 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 21:03:36,611 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 21:03:36,612 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 21:03:36,613 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 21:03:36,613 INFO L85 PathProgramCache]: Analyzing trace with hash 2084563792, now seen corresponding path program 1 times [2022-12-13 21:03:36,613 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 21:03:36,613 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [838157033] [2022-12-13 21:03:36,613 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 21:03:36,613 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 21:03:36,621 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 21:03:36,642 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 21:03:36,642 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 21:03:36,643 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [838157033] [2022-12-13 21:03:36,643 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [838157033] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 21:03:36,643 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 21:03:36,643 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 21:03:36,643 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [807793205] [2022-12-13 21:03:36,643 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 21:03:36,711 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 21:03:36,711 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 21:03:36,712 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 21:03:36,712 INFO L87 Difference]: Start difference. First operand 6118 states and 8062 transitions. cyclomatic complexity: 1947 Second operand has 3 states, 3 states have (on average 25.0) internal successors, (75), 3 states have internal predecessors, (75), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 21:03:36,761 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 21:03:36,761 INFO L93 Difference]: Finished difference Result 9420 states and 12360 transitions. [2022-12-13 21:03:36,761 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 9420 states and 12360 transitions. [2022-12-13 21:03:36,794 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 9340 [2022-12-13 21:03:36,820 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 9420 states to 9420 states and 12360 transitions. [2022-12-13 21:03:36,820 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9420 [2022-12-13 21:03:36,826 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9420 [2022-12-13 21:03:36,826 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9420 states and 12360 transitions. [2022-12-13 21:03:36,832 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 21:03:36,832 INFO L218 hiAutomatonCegarLoop]: Abstraction has 9420 states and 12360 transitions. [2022-12-13 21:03:36,838 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9420 states and 12360 transitions. [2022-12-13 21:03:36,928 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9420 to 9420. [2022-12-13 21:03:36,938 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 9420 states, 9420 states have (on average 1.3121019108280254) internal successors, (12360), 9419 states have internal predecessors, (12360), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 21:03:36,957 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9420 states to 9420 states and 12360 transitions. [2022-12-13 21:03:36,958 INFO L240 hiAutomatonCegarLoop]: Abstraction has 9420 states and 12360 transitions. [2022-12-13 21:03:36,958 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 21:03:36,958 INFO L428 stractBuchiCegarLoop]: Abstraction has 9420 states and 12360 transitions. [2022-12-13 21:03:36,959 INFO L335 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2022-12-13 21:03:36,959 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 9420 states and 12360 transitions. [2022-12-13 21:03:36,989 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 9340 [2022-12-13 21:03:36,989 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 21:03:36,989 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 21:03:36,990 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 21:03:36,990 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 21:03:36,990 INFO L748 eck$LassoCheckResult]: Stem: 105434#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 105435#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 105451#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 105442#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 105319#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 105320#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 105148#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 105149#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 105159#L356-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 105160#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 105201#L502 assume !(0 == ~M_E~0); 105202#L502-2 assume !(0 == ~T1_E~0); 105140#L507-1 assume !(0 == ~T2_E~0); 105141#L512-1 assume !(0 == ~T3_E~0); 105321#L517-1 assume !(0 == ~T4_E~0); 105121#L522-1 assume !(0 == ~E_1~0); 105122#L527-1 assume !(0 == ~E_2~0); 105339#L532-1 assume !(0 == ~E_3~0); 105438#L537-1 assume !(0 == ~E_4~0); 105463#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 105426#L238 assume !(1 == ~m_pc~0); 105427#L238-2 is_master_triggered_~__retres1~0#1 := 0; 105080#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 105081#is_master_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 105403#L615 assume !(0 != activate_threads_~tmp~1#1); 105105#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 105106#L257 assume !(1 == ~t1_pc~0); 105209#L257-2 is_transmit1_triggered_~__retres1~1#1 := 0; 105210#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 105191#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 105068#L623 assume !(0 != activate_threads_~tmp___0~0#1); 105069#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 105063#L276 assume !(1 == ~t2_pc~0); 105064#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 105353#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 105472#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 105481#L631 assume !(0 != activate_threads_~tmp___1~0#1); 105482#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 105401#L295 assume !(1 == ~t3_pc~0); 105172#L295-2 is_transmit3_triggered_~__retres1~3#1 := 0; 105173#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 105107#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 105108#L639 assume !(0 != activate_threads_~tmp___2~0#1); 105430#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 105431#L314 assume !(1 == ~t4_pc~0); 105217#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 105216#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 105299#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 105300#L647 assume !(0 != activate_threads_~tmp___3~0#1); 105329#L647-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 105330#L555 assume !(1 == ~M_E~0); 105232#L555-2 assume !(1 == ~T1_E~0); 105233#L560-1 assume !(1 == ~T2_E~0); 105123#L565-1 assume !(1 == ~T3_E~0); 105124#L570-1 assume !(1 == ~T4_E~0); 105186#L575-1 assume !(1 == ~E_1~0); 105187#L580-1 assume !(1 == ~E_2~0); 105382#L585-1 assume !(1 == ~E_3~0); 105188#L590-1 assume !(1 == ~E_4~0); 105174#L595-1 assume { :end_inline_reset_delta_events } true; 105175#L776-2 assume !false; 112776#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 112773#L477 [2022-12-13 21:03:36,990 INFO L750 eck$LassoCheckResult]: Loop: 112773#L477 assume !false; 112772#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 112681#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 112682#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 113873#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 113872#L416 assume 0 != eval_~tmp~0#1; 113871#L416-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 105510#L424 assume !(0 != eval_~tmp_ndt_1~0#1); 105511#L421 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 108575#L438 assume !(0 != eval_~tmp_ndt_2~0#1); 108576#L435 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 109313#L452 assume !(0 != eval_~tmp_ndt_3~0#1); 109441#L449 assume !(0 == ~t3_st~0); 109443#L463 assume !(0 == ~t4_st~0); 112773#L477 [2022-12-13 21:03:36,991 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 21:03:36,991 INFO L85 PathProgramCache]: Analyzing trace with hash 9663309, now seen corresponding path program 3 times [2022-12-13 21:03:36,991 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 21:03:36,991 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1390377480] [2022-12-13 21:03:36,991 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 21:03:36,991 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 21:03:37,001 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 21:03:37,001 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 21:03:37,007 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 21:03:37,016 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 21:03:37,017 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 21:03:37,017 INFO L85 PathProgramCache]: Analyzing trace with hash -901553796, now seen corresponding path program 1 times [2022-12-13 21:03:37,017 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 21:03:37,017 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1175792954] [2022-12-13 21:03:37,017 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 21:03:37,017 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 21:03:37,021 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 21:03:37,021 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 21:03:37,023 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 21:03:37,025 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 21:03:37,025 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 21:03:37,025 INFO L85 PathProgramCache]: Analyzing trace with hash 192225224, now seen corresponding path program 1 times [2022-12-13 21:03:37,025 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 21:03:37,025 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1354001436] [2022-12-13 21:03:37,026 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 21:03:37,026 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 21:03:37,035 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 21:03:37,062 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 21:03:37,062 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 21:03:37,063 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1354001436] [2022-12-13 21:03:37,063 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1354001436] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 21:03:37,063 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 21:03:37,063 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 21:03:37,063 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2102128257] [2022-12-13 21:03:37,063 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 21:03:37,154 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 21:03:37,154 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 21:03:37,154 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 21:03:37,154 INFO L87 Difference]: Start difference. First operand 9420 states and 12360 transitions. cyclomatic complexity: 2943 Second operand has 3 states, 3 states have (on average 25.333333333333332) internal successors, (76), 3 states have internal predecessors, (76), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 21:03:37,215 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 21:03:37,216 INFO L93 Difference]: Finished difference Result 17038 states and 22278 transitions. [2022-12-13 21:03:37,216 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 17038 states and 22278 transitions. [2022-12-13 21:03:37,292 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 16942 [2022-12-13 21:03:37,333 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 17038 states to 17038 states and 22278 transitions. [2022-12-13 21:03:37,333 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 17038 [2022-12-13 21:03:37,340 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 17038 [2022-12-13 21:03:37,340 INFO L73 IsDeterministic]: Start isDeterministic. Operand 17038 states and 22278 transitions. [2022-12-13 21:03:37,346 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 21:03:37,346 INFO L218 hiAutomatonCegarLoop]: Abstraction has 17038 states and 22278 transitions. [2022-12-13 21:03:37,353 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17038 states and 22278 transitions. [2022-12-13 21:03:37,475 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17038 to 16686. [2022-12-13 21:03:37,485 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 16686 states, 16686 states have (on average 1.3082823924247873) internal successors, (21830), 16685 states have internal predecessors, (21830), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 21:03:37,503 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16686 states to 16686 states and 21830 transitions. [2022-12-13 21:03:37,503 INFO L240 hiAutomatonCegarLoop]: Abstraction has 16686 states and 21830 transitions. [2022-12-13 21:03:37,504 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 21:03:37,504 INFO L428 stractBuchiCegarLoop]: Abstraction has 16686 states and 21830 transitions. [2022-12-13 21:03:37,504 INFO L335 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2022-12-13 21:03:37,504 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 16686 states and 21830 transitions. [2022-12-13 21:03:37,538 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 16590 [2022-12-13 21:03:37,538 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 21:03:37,538 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 21:03:37,538 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 21:03:37,538 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 21:03:37,539 INFO L748 eck$LassoCheckResult]: Stem: 131909#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 131910#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 131921#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 131917#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 131783#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 131784#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 131615#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 131616#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 131626#L356-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 131627#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 131668#L502 assume !(0 == ~M_E~0); 131669#L502-2 assume !(0 == ~T1_E~0); 131604#L507-1 assume !(0 == ~T2_E~0); 131605#L512-1 assume !(0 == ~T3_E~0); 131787#L517-1 assume !(0 == ~T4_E~0); 131581#L522-1 assume !(0 == ~E_1~0); 131582#L527-1 assume !(0 == ~E_2~0); 131808#L532-1 assume !(0 == ~E_3~0); 131913#L537-1 assume !(0 == ~E_4~0); 131937#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 131902#L238 assume !(1 == ~m_pc~0); 131903#L238-2 is_master_triggered_~__retres1~0#1 := 0; 131540#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 131541#is_master_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 131877#L615 assume !(0 != activate_threads_~tmp~1#1); 131565#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 131566#L257 assume !(1 == ~t1_pc~0); 131676#L257-2 is_transmit1_triggered_~__retres1~1#1 := 0; 131677#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 131658#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 131532#L623 assume !(0 != activate_threads_~tmp___0~0#1); 131533#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 131529#L276 assume !(1 == ~t2_pc~0); 131530#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 131816#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 131947#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 131955#L631 assume !(0 != activate_threads_~tmp___1~0#1); 131956#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 131873#L295 assume !(1 == ~t3_pc~0); 131639#L295-2 is_transmit3_triggered_~__retres1~3#1 := 0; 131640#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 131567#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 131568#L639 assume !(0 != activate_threads_~tmp___2~0#1); 131906#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 131907#L314 assume !(1 == ~t4_pc~0); 131683#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 131682#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 131764#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 131765#L647 assume !(0 != activate_threads_~tmp___3~0#1); 131797#L647-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 131798#L555 assume !(1 == ~M_E~0); 131698#L555-2 assume !(1 == ~T1_E~0); 131699#L560-1 assume !(1 == ~T2_E~0); 131583#L565-1 assume !(1 == ~T3_E~0); 131584#L570-1 assume !(1 == ~T4_E~0); 131653#L575-1 assume !(1 == ~E_1~0); 131654#L580-1 assume !(1 == ~E_2~0); 131854#L585-1 assume !(1 == ~E_3~0); 131655#L590-1 assume !(1 == ~E_4~0); 131641#L595-1 assume { :end_inline_reset_delta_events } true; 131642#L776-2 assume !false; 147701#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 147698#L477 [2022-12-13 21:03:37,539 INFO L750 eck$LassoCheckResult]: Loop: 147698#L477 assume !false; 147697#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 147696#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 147695#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 147694#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 143873#L416 assume 0 != eval_~tmp~0#1; 143871#L416-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 143869#L424 assume !(0 != eval_~tmp_ndt_1~0#1); 143868#L421 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 143355#L438 assume !(0 != eval_~tmp_ndt_2~0#1); 143867#L435 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 143837#L452 assume !(0 != eval_~tmp_ndt_3~0#1); 142052#L449 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 142048#L466 assume !(0 != eval_~tmp_ndt_4~0#1); 142049#L463 assume !(0 == ~t4_st~0); 147698#L477 [2022-12-13 21:03:37,539 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 21:03:37,539 INFO L85 PathProgramCache]: Analyzing trace with hash 9663309, now seen corresponding path program 4 times [2022-12-13 21:03:37,539 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 21:03:37,539 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1460700156] [2022-12-13 21:03:37,539 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 21:03:37,539 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 21:03:37,544 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 21:03:37,544 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 21:03:37,547 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 21:03:37,552 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 21:03:37,552 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 21:03:37,552 INFO L85 PathProgramCache]: Analyzing trace with hash 2116454956, now seen corresponding path program 1 times [2022-12-13 21:03:37,552 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 21:03:37,552 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [462431577] [2022-12-13 21:03:37,552 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 21:03:37,552 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 21:03:37,554 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 21:03:37,555 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 21:03:37,556 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 21:03:37,557 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 21:03:37,557 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 21:03:37,557 INFO L85 PathProgramCache]: Analyzing trace with hash 1663866208, now seen corresponding path program 1 times [2022-12-13 21:03:37,557 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 21:03:37,557 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1048775890] [2022-12-13 21:03:37,557 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 21:03:37,557 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 21:03:37,563 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 21:03:37,577 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 21:03:37,577 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 21:03:37,577 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1048775890] [2022-12-13 21:03:37,577 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1048775890] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 21:03:37,577 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 21:03:37,577 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-12-13 21:03:37,577 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1271368704] [2022-12-13 21:03:37,578 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 21:03:37,683 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 21:03:37,683 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 21:03:37,683 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 21:03:37,683 INFO L87 Difference]: Start difference. First operand 16686 states and 21830 transitions. cyclomatic complexity: 5147 Second operand has 3 states, 2 states have (on average 38.5) internal successors, (77), 3 states have internal predecessors, (77), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 21:03:37,801 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 21:03:37,801 INFO L93 Difference]: Finished difference Result 31602 states and 41178 transitions. [2022-12-13 21:03:37,801 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 31602 states and 41178 transitions. [2022-12-13 21:03:37,901 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 31474 [2022-12-13 21:03:37,965 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 31602 states to 31602 states and 41178 transitions. [2022-12-13 21:03:37,966 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 31602 [2022-12-13 21:03:37,978 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 31602 [2022-12-13 21:03:37,978 INFO L73 IsDeterministic]: Start isDeterministic. Operand 31602 states and 41178 transitions. [2022-12-13 21:03:37,997 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 21:03:37,997 INFO L218 hiAutomatonCegarLoop]: Abstraction has 31602 states and 41178 transitions. [2022-12-13 21:03:38,010 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 31602 states and 41178 transitions. [2022-12-13 21:03:38,246 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 31602 to 31602. [2022-12-13 21:03:38,262 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 31602 states, 31602 states have (on average 1.3030187962787165) internal successors, (41178), 31601 states have internal predecessors, (41178), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 21:03:38,313 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 31602 states to 31602 states and 41178 transitions. [2022-12-13 21:03:38,313 INFO L240 hiAutomatonCegarLoop]: Abstraction has 31602 states and 41178 transitions. [2022-12-13 21:03:38,313 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 21:03:38,314 INFO L428 stractBuchiCegarLoop]: Abstraction has 31602 states and 41178 transitions. [2022-12-13 21:03:38,314 INFO L335 stractBuchiCegarLoop]: ======== Iteration 23 ============ [2022-12-13 21:03:38,314 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 31602 states and 41178 transitions. [2022-12-13 21:03:38,382 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 31474 [2022-12-13 21:03:38,382 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 21:03:38,382 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 21:03:38,382 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 21:03:38,382 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 21:03:38,382 INFO L748 eck$LassoCheckResult]: Stem: 180213#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 180214#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 180227#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 180222#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 180077#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 180078#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 179909#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 179910#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 179920#L356-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 179921#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 179962#L502 assume !(0 == ~M_E~0); 179963#L502-2 assume !(0 == ~T1_E~0); 179898#L507-1 assume !(0 == ~T2_E~0); 179899#L512-1 assume !(0 == ~T3_E~0); 180081#L517-1 assume !(0 == ~T4_E~0); 179876#L522-1 assume !(0 == ~E_1~0); 179877#L527-1 assume !(0 == ~E_2~0); 180102#L532-1 assume !(0 == ~E_3~0); 180218#L537-1 assume !(0 == ~E_4~0); 180246#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 180205#L238 assume !(1 == ~m_pc~0); 180206#L238-2 is_master_triggered_~__retres1~0#1 := 0; 179836#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 179837#is_master_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 180176#L615 assume !(0 != activate_threads_~tmp~1#1); 179861#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 179862#L257 assume !(1 == ~t1_pc~0); 179970#L257-2 is_transmit1_triggered_~__retres1~1#1 := 0; 179971#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 179952#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 179828#L623 assume !(0 != activate_threads_~tmp___0~0#1); 179829#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 179825#L276 assume !(1 == ~t2_pc~0); 179826#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 180112#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 180254#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 180263#L631 assume !(0 != activate_threads_~tmp___1~0#1); 180264#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 180172#L295 assume !(1 == ~t3_pc~0); 179933#L295-2 is_transmit3_triggered_~__retres1~3#1 := 0; 179934#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 179863#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 179864#L639 assume !(0 != activate_threads_~tmp___2~0#1); 180207#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 180208#L314 assume !(1 == ~t4_pc~0); 179977#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 179976#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 180058#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 180059#L647 assume !(0 != activate_threads_~tmp___3~0#1); 180091#L647-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 180092#L555 assume !(1 == ~M_E~0); 179994#L555-2 assume !(1 == ~T1_E~0); 179995#L560-1 assume !(1 == ~T2_E~0); 179878#L565-1 assume !(1 == ~T3_E~0); 179879#L570-1 assume !(1 == ~T4_E~0); 179946#L575-1 assume !(1 == ~E_1~0); 179947#L580-1 assume !(1 == ~E_2~0); 180154#L585-1 assume !(1 == ~E_3~0); 179945#L590-1 assume !(1 == ~E_4~0); 179935#L595-1 assume { :end_inline_reset_delta_events } true; 179936#L776-2 assume !false; 192434#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 192435#L477 [2022-12-13 21:03:38,383 INFO L750 eck$LassoCheckResult]: Loop: 192435#L477 assume !false; 192427#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 192424#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 192421#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 192422#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 196974#L416 assume 0 != eval_~tmp~0#1; 196971#L416-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 192409#L424 assume !(0 != eval_~tmp_ndt_1~0#1); 188889#L421 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 188372#L438 assume !(0 != eval_~tmp_ndt_2~0#1); 188373#L435 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 196258#L452 assume !(0 != eval_~tmp_ndt_3~0#1); 196256#L449 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 189830#L466 assume !(0 != eval_~tmp_ndt_4~0#1); 195866#L463 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0#1;eval_~tmp_ndt_5~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 200052#L480 assume !(0 != eval_~tmp_ndt_5~0#1); 192435#L477 [2022-12-13 21:03:38,383 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 21:03:38,383 INFO L85 PathProgramCache]: Analyzing trace with hash 9663309, now seen corresponding path program 5 times [2022-12-13 21:03:38,383 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 21:03:38,383 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [196881458] [2022-12-13 21:03:38,383 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 21:03:38,383 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 21:03:38,388 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 21:03:38,388 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 21:03:38,391 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 21:03:38,395 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 21:03:38,396 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 21:03:38,396 INFO L85 PathProgramCache]: Analyzing trace with hash 1185593964, now seen corresponding path program 1 times [2022-12-13 21:03:38,396 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 21:03:38,396 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1225632796] [2022-12-13 21:03:38,396 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 21:03:38,396 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 21:03:38,398 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 21:03:38,398 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 21:03:38,399 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 21:03:38,400 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 21:03:38,401 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 21:03:38,401 INFO L85 PathProgramCache]: Analyzing trace with hash 40244664, now seen corresponding path program 1 times [2022-12-13 21:03:38,401 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 21:03:38,401 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1719001858] [2022-12-13 21:03:38,401 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 21:03:38,401 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 21:03:38,406 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 21:03:38,406 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 21:03:38,439 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 21:03:38,448 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 21:03:39,483 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 21:03:39,483 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 21:03:39,499 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 21:03:39,625 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 13.12 09:03:39 BoogieIcfgContainer [2022-12-13 21:03:39,625 INFO L132 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2022-12-13 21:03:39,625 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2022-12-13 21:03:39,625 INFO L271 PluginConnector]: Initializing Witness Printer... [2022-12-13 21:03:39,625 INFO L275 PluginConnector]: Witness Printer initialized [2022-12-13 21:03:39,626 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.12 09:03:32" (3/4) ... [2022-12-13 21:03:39,628 INFO L134 WitnessPrinter]: Generating witness for non-termination counterexample [2022-12-13 21:03:39,692 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d951f68a-5c6f-42d8-aa18-e8b3628bcfb9/bin/uautomizer-uyxdKDjOR8/witness.graphml [2022-12-13 21:03:39,693 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2022-12-13 21:03:39,693 INFO L158 Benchmark]: Toolchain (without parser) took 8456.36ms. Allocated memory was 113.2MB in the beginning and 1.0GB in the end (delta: 931.1MB). Free memory was 78.8MB in the beginning and 655.0MB in the end (delta: -576.2MB). Peak memory consumption was 357.1MB. Max. memory is 16.1GB. [2022-12-13 21:03:39,693 INFO L158 Benchmark]: CDTParser took 0.14ms. Allocated memory is still 113.2MB. Free memory is still 89.1MB. There was no memory consumed. Max. memory is 16.1GB. [2022-12-13 21:03:39,694 INFO L158 Benchmark]: CACSL2BoogieTranslator took 243.36ms. Allocated memory is still 113.2MB. Free memory was 78.5MB in the beginning and 63.6MB in the end (delta: 14.9MB). Peak memory consumption was 14.7MB. Max. memory is 16.1GB. [2022-12-13 21:03:39,694 INFO L158 Benchmark]: Boogie Procedure Inliner took 52.17ms. Allocated memory is still 113.2MB. Free memory was 63.6MB in the beginning and 59.4MB in the end (delta: 4.2MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2022-12-13 21:03:39,694 INFO L158 Benchmark]: Boogie Preprocessor took 45.11ms. Allocated memory is still 113.2MB. Free memory was 59.4MB in the beginning and 55.8MB in the end (delta: 3.5MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2022-12-13 21:03:39,695 INFO L158 Benchmark]: RCFGBuilder took 754.62ms. Allocated memory was 113.2MB in the beginning and 163.6MB in the end (delta: 50.3MB). Free memory was 55.8MB in the beginning and 101.5MB in the end (delta: -45.7MB). Peak memory consumption was 22.8MB. Max. memory is 16.1GB. [2022-12-13 21:03:39,695 INFO L158 Benchmark]: BuchiAutomizer took 7289.30ms. Allocated memory was 163.6MB in the beginning and 1.0GB in the end (delta: 880.8MB). Free memory was 101.5MB in the beginning and 663.4MB in the end (delta: -561.8MB). Peak memory consumption was 319.6MB. Max. memory is 16.1GB. [2022-12-13 21:03:39,695 INFO L158 Benchmark]: Witness Printer took 67.37ms. Allocated memory is still 1.0GB. Free memory was 662.3MB in the beginning and 655.0MB in the end (delta: 7.3MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. [2022-12-13 21:03:39,698 INFO L339 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.14ms. Allocated memory is still 113.2MB. Free memory is still 89.1MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 243.36ms. Allocated memory is still 113.2MB. Free memory was 78.5MB in the beginning and 63.6MB in the end (delta: 14.9MB). Peak memory consumption was 14.7MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 52.17ms. Allocated memory is still 113.2MB. Free memory was 63.6MB in the beginning and 59.4MB in the end (delta: 4.2MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * Boogie Preprocessor took 45.11ms. Allocated memory is still 113.2MB. Free memory was 59.4MB in the beginning and 55.8MB in the end (delta: 3.5MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * RCFGBuilder took 754.62ms. Allocated memory was 113.2MB in the beginning and 163.6MB in the end (delta: 50.3MB). Free memory was 55.8MB in the beginning and 101.5MB in the end (delta: -45.7MB). Peak memory consumption was 22.8MB. Max. memory is 16.1GB. * BuchiAutomizer took 7289.30ms. Allocated memory was 163.6MB in the beginning and 1.0GB in the end (delta: 880.8MB). Free memory was 101.5MB in the beginning and 663.4MB in the end (delta: -561.8MB). Peak memory consumption was 319.6MB. Max. memory is 16.1GB. * Witness Printer took 67.37ms. Allocated memory is still 1.0GB. Free memory was 662.3MB in the beginning and 655.0MB in the end (delta: 7.3MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 22 terminating modules (22 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.22 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 31602 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 7.1s and 23 iterations. TraceHistogramMax:1. Analysis of lassos took 3.2s. Construction of modules took 0.4s. Büchi inclusion checks took 3.0s. Highest rank in rank-based complementation 0. Minimization of det autom 22. Minimization of nondet autom 0. Automata minimization 1.2s AutomataMinimizationTime, 22 MinimizatonAttempts, 10662 StatesRemovedByMinimization, 13 NontrivialMinimizations. Non-live state removal took 0.7s Buchi closure took 0.0s. Biggest automaton had -1 states and ocurred in iteration -1. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 16146 SdHoareTripleChecker+Valid, 0.6s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 16146 mSDsluCounter, 25479 SdHoareTripleChecker+Invalid, 0.5s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 12262 mSDsCounter, 261 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 619 IncrementalHoareTripleChecker+Invalid, 880 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 261 mSolverCounterUnsat, 13217 mSDtfsCounter, 619 mSolverCounterSat, 0.1s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI4 SFLT0 conc4 concLT0 SILN1 SILU0 SILI13 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s InitialAbstractionConstructionTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - LassoShapedNonTerminationArgument [Line: 411]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite program execution. Stem: [L25] int m_pc = 0; [L26] int t1_pc = 0; [L27] int t2_pc = 0; [L28] int t3_pc = 0; [L29] int t4_pc = 0; [L30] int m_st ; [L31] int t1_st ; [L32] int t2_st ; [L33] int t3_st ; [L34] int t4_st ; [L35] int m_i ; [L36] int t1_i ; [L37] int t2_i ; [L38] int t3_i ; [L39] int t4_i ; [L40] int M_E = 2; [L41] int T1_E = 2; [L42] int T2_E = 2; [L43] int T3_E = 2; [L44] int T4_E = 2; [L45] int E_1 = 2; [L46] int E_2 = 2; [L47] int E_3 = 2; [L48] int E_4 = 2; VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=0, m_pc=0, m_st=0, T1_E=2, t1_i=0, t1_pc=0, t1_st=0, T2_E=2, t2_i=0, t2_pc=0, t2_st=0, T3_E=2, t3_i=0, t3_pc=0, t3_st=0, T4_E=2, t4_i=0, t4_pc=0, t4_st=0] [L821] int __retres1 ; [L825] CALL init_model() [L733] m_i = 1 [L734] t1_i = 1 [L735] t2_i = 1 [L736] t3_i = 1 [L737] t4_i = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L825] RET init_model() [L826] CALL start_simulation() [L762] int kernel_st ; [L763] int tmp ; [L764] int tmp___0 ; [L768] kernel_st = 0 [L769] FCALL update_channels() [L770] CALL init_threads() [L341] COND TRUE m_i == 1 [L342] m_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L346] COND TRUE t1_i == 1 [L347] t1_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L351] COND TRUE t2_i == 1 [L352] t2_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L356] COND TRUE t3_i == 1 [L357] t3_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L361] COND TRUE t4_i == 1 [L362] t4_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L770] RET init_threads() [L771] CALL fire_delta_events() [L502] COND FALSE !(M_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L507] COND FALSE !(T1_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L512] COND FALSE !(T2_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L517] COND FALSE !(T3_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L522] COND FALSE !(T4_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L527] COND FALSE !(E_1 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L532] COND FALSE !(E_2 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L537] COND FALSE !(E_3 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L542] COND FALSE !(E_4 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L771] RET fire_delta_events() [L772] CALL activate_threads() [L605] int tmp ; [L606] int tmp___0 ; [L607] int tmp___1 ; [L608] int tmp___2 ; [L609] int tmp___3 ; [L613] CALL, EXPR is_master_triggered() [L235] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L238] COND FALSE !(m_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L248] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L250] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L613] RET, EXPR is_master_triggered() [L613] tmp = is_master_triggered() [L615] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, tmp=0] [L621] CALL, EXPR is_transmit1_triggered() [L254] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L257] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L267] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L269] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L621] RET, EXPR is_transmit1_triggered() [L621] tmp___0 = is_transmit1_triggered() [L623] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, tmp=0, tmp___0=0] [L629] CALL, EXPR is_transmit2_triggered() [L273] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L276] COND FALSE !(t2_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L286] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L288] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L629] RET, EXPR is_transmit2_triggered() [L629] tmp___1 = is_transmit2_triggered() [L631] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, tmp=0, tmp___0=0, tmp___1=0] [L637] CALL, EXPR is_transmit3_triggered() [L292] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L295] COND FALSE !(t3_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L305] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L307] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L637] RET, EXPR is_transmit3_triggered() [L637] tmp___2 = is_transmit3_triggered() [L639] COND FALSE !(\read(tmp___2)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0] [L645] CALL, EXPR is_transmit4_triggered() [L311] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L314] COND FALSE !(t4_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L324] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L326] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L645] RET, EXPR is_transmit4_triggered() [L645] tmp___3 = is_transmit4_triggered() [L647] COND FALSE !(\read(tmp___3)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0] [L772] RET activate_threads() [L773] CALL reset_delta_events() [L555] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L560] COND FALSE !(T1_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L565] COND FALSE !(T2_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L570] COND FALSE !(T3_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L575] COND FALSE !(T4_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L580] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L585] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L590] COND FALSE !(E_3 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L595] COND FALSE !(E_4 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L773] RET reset_delta_events() [L776] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L779] kernel_st = 1 [L780] CALL eval() [L407] int tmp ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] Loop: [L411] COND TRUE 1 [L414] CALL, EXPR exists_runnable_thread() [L371] int __retres1 ; [L374] COND TRUE m_st == 0 [L375] __retres1 = 1 [L402] return (__retres1); [L414] RET, EXPR exists_runnable_thread() [L414] tmp = exists_runnable_thread() [L416] COND TRUE \read(tmp) [L421] COND TRUE m_st == 0 [L422] int tmp_ndt_1; [L423] tmp_ndt_1 = __VERIFIER_nondet_int() [L424] COND FALSE !(\read(tmp_ndt_1)) [L435] COND TRUE t1_st == 0 [L436] int tmp_ndt_2; [L437] tmp_ndt_2 = __VERIFIER_nondet_int() [L438] COND FALSE !(\read(tmp_ndt_2)) [L449] COND TRUE t2_st == 0 [L450] int tmp_ndt_3; [L451] tmp_ndt_3 = __VERIFIER_nondet_int() [L452] COND FALSE !(\read(tmp_ndt_3)) [L463] COND TRUE t3_st == 0 [L464] int tmp_ndt_4; [L465] tmp_ndt_4 = __VERIFIER_nondet_int() [L466] COND FALSE !(\read(tmp_ndt_4)) [L477] COND TRUE t4_st == 0 [L478] int tmp_ndt_5; [L479] tmp_ndt_5 = __VERIFIER_nondet_int() [L480] COND FALSE !(\read(tmp_ndt_5)) End of lasso representation. - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 411]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L25] int m_pc = 0; [L26] int t1_pc = 0; [L27] int t2_pc = 0; [L28] int t3_pc = 0; [L29] int t4_pc = 0; [L30] int m_st ; [L31] int t1_st ; [L32] int t2_st ; [L33] int t3_st ; [L34] int t4_st ; [L35] int m_i ; [L36] int t1_i ; [L37] int t2_i ; [L38] int t3_i ; [L39] int t4_i ; [L40] int M_E = 2; [L41] int T1_E = 2; [L42] int T2_E = 2; [L43] int T3_E = 2; [L44] int T4_E = 2; [L45] int E_1 = 2; [L46] int E_2 = 2; [L47] int E_3 = 2; [L48] int E_4 = 2; VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=0, m_pc=0, m_st=0, T1_E=2, t1_i=0, t1_pc=0, t1_st=0, T2_E=2, t2_i=0, t2_pc=0, t2_st=0, T3_E=2, t3_i=0, t3_pc=0, t3_st=0, T4_E=2, t4_i=0, t4_pc=0, t4_st=0] [L821] int __retres1 ; [L825] CALL init_model() [L733] m_i = 1 [L734] t1_i = 1 [L735] t2_i = 1 [L736] t3_i = 1 [L737] t4_i = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L825] RET init_model() [L826] CALL start_simulation() [L762] int kernel_st ; [L763] int tmp ; [L764] int tmp___0 ; [L768] kernel_st = 0 [L769] FCALL update_channels() [L770] CALL init_threads() [L341] COND TRUE m_i == 1 [L342] m_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L346] COND TRUE t1_i == 1 [L347] t1_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L351] COND TRUE t2_i == 1 [L352] t2_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L356] COND TRUE t3_i == 1 [L357] t3_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L361] COND TRUE t4_i == 1 [L362] t4_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L770] RET init_threads() [L771] CALL fire_delta_events() [L502] COND FALSE !(M_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L507] COND FALSE !(T1_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L512] COND FALSE !(T2_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L517] COND FALSE !(T3_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L522] COND FALSE !(T4_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L527] COND FALSE !(E_1 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L532] COND FALSE !(E_2 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L537] COND FALSE !(E_3 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L542] COND FALSE !(E_4 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L771] RET fire_delta_events() [L772] CALL activate_threads() [L605] int tmp ; [L606] int tmp___0 ; [L607] int tmp___1 ; [L608] int tmp___2 ; [L609] int tmp___3 ; [L613] CALL, EXPR is_master_triggered() [L235] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L238] COND FALSE !(m_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L248] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L250] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L613] RET, EXPR is_master_triggered() [L613] tmp = is_master_triggered() [L615] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, tmp=0] [L621] CALL, EXPR is_transmit1_triggered() [L254] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L257] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L267] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L269] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L621] RET, EXPR is_transmit1_triggered() [L621] tmp___0 = is_transmit1_triggered() [L623] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, tmp=0, tmp___0=0] [L629] CALL, EXPR is_transmit2_triggered() [L273] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L276] COND FALSE !(t2_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L286] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L288] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L629] RET, EXPR is_transmit2_triggered() [L629] tmp___1 = is_transmit2_triggered() [L631] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, tmp=0, tmp___0=0, tmp___1=0] [L637] CALL, EXPR is_transmit3_triggered() [L292] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L295] COND FALSE !(t3_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L305] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L307] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L637] RET, EXPR is_transmit3_triggered() [L637] tmp___2 = is_transmit3_triggered() [L639] COND FALSE !(\read(tmp___2)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0] [L645] CALL, EXPR is_transmit4_triggered() [L311] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L314] COND FALSE !(t4_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L324] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L326] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L645] RET, EXPR is_transmit4_triggered() [L645] tmp___3 = is_transmit4_triggered() [L647] COND FALSE !(\read(tmp___3)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0] [L772] RET activate_threads() [L773] CALL reset_delta_events() [L555] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L560] COND FALSE !(T1_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L565] COND FALSE !(T2_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L570] COND FALSE !(T3_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L575] COND FALSE !(T4_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L580] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L585] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L590] COND FALSE !(E_3 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L595] COND FALSE !(E_4 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L773] RET reset_delta_events() [L776] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L779] kernel_st = 1 [L780] CALL eval() [L407] int tmp ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] Loop: [L411] COND TRUE 1 [L414] CALL, EXPR exists_runnable_thread() [L371] int __retres1 ; [L374] COND TRUE m_st == 0 [L375] __retres1 = 1 [L402] return (__retres1); [L414] RET, EXPR exists_runnable_thread() [L414] tmp = exists_runnable_thread() [L416] COND TRUE \read(tmp) [L421] COND TRUE m_st == 0 [L422] int tmp_ndt_1; [L423] tmp_ndt_1 = __VERIFIER_nondet_int() [L424] COND FALSE !(\read(tmp_ndt_1)) [L435] COND TRUE t1_st == 0 [L436] int tmp_ndt_2; [L437] tmp_ndt_2 = __VERIFIER_nondet_int() [L438] COND FALSE !(\read(tmp_ndt_2)) [L449] COND TRUE t2_st == 0 [L450] int tmp_ndt_3; [L451] tmp_ndt_3 = __VERIFIER_nondet_int() [L452] COND FALSE !(\read(tmp_ndt_3)) [L463] COND TRUE t3_st == 0 [L464] int tmp_ndt_4; [L465] tmp_ndt_4 = __VERIFIER_nondet_int() [L466] COND FALSE !(\read(tmp_ndt_4)) [L477] COND TRUE t4_st == 0 [L478] int tmp_ndt_5; [L479] tmp_ndt_5 = __VERIFIER_nondet_int() [L480] COND FALSE !(\read(tmp_ndt_5)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2022-12-13 21:03:39,768 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d951f68a-5c6f-42d8-aa18-e8b3628bcfb9/bin/uautomizer-uyxdKDjOR8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Forceful destruction successful, exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)