./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/transmitter.05.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 2329fc70 Calling Ultimate with: /usr/lib/jvm/java-11-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f5200838-b26d-417b-8c3a-fd86d82f1b34/bin/uautomizer-uyxdKDjOR8/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f5200838-b26d-417b-8c3a-fd86d82f1b34/bin/uautomizer-uyxdKDjOR8/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f5200838-b26d-417b-8c3a-fd86d82f1b34/bin/uautomizer-uyxdKDjOR8/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f5200838-b26d-417b-8c3a-fd86d82f1b34/bin/uautomizer-uyxdKDjOR8/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/transmitter.05.cil.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f5200838-b26d-417b-8c3a-fd86d82f1b34/bin/uautomizer-uyxdKDjOR8/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f5200838-b26d-417b-8c3a-fd86d82f1b34/bin/uautomizer-uyxdKDjOR8 --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash d8722862ca37b1ee13dec8b9e420cd40ba7901837b8f3b6258499da6e8a2ca6f --- Real Ultimate output --- [0.001s][warning][os,container] Duplicate cpuset controllers detected. Picking /sys/fs/cgroup/cpuset, skipping /sys/fs/cgroup/cpuset. This is Ultimate 0.2.2-dev-2329fc7 [2022-12-13 19:30:58,956 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-12-13 19:30:58,958 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-12-13 19:30:58,976 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-12-13 19:30:58,976 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-12-13 19:30:58,977 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-12-13 19:30:58,978 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-12-13 19:30:58,980 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-12-13 19:30:58,981 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-12-13 19:30:58,982 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-12-13 19:30:58,983 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-12-13 19:30:58,984 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-12-13 19:30:58,984 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-12-13 19:30:58,985 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-12-13 19:30:58,986 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-12-13 19:30:58,987 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-12-13 19:30:58,988 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-12-13 19:30:58,989 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-12-13 19:30:58,991 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-12-13 19:30:58,992 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-12-13 19:30:58,994 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-12-13 19:30:58,995 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-12-13 19:30:58,996 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-12-13 19:30:58,997 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-12-13 19:30:59,000 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-12-13 19:30:59,000 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-12-13 19:30:59,001 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-12-13 19:30:59,002 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-12-13 19:30:59,002 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-12-13 19:30:59,003 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-12-13 19:30:59,003 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-12-13 19:30:59,004 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-12-13 19:30:59,004 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-12-13 19:30:59,005 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-12-13 19:30:59,006 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-12-13 19:30:59,006 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-12-13 19:30:59,007 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-12-13 19:30:59,007 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-12-13 19:30:59,007 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-12-13 19:30:59,008 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-12-13 19:30:59,009 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-12-13 19:30:59,009 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f5200838-b26d-417b-8c3a-fd86d82f1b34/bin/uautomizer-uyxdKDjOR8/config/svcomp-Termination-32bit-Automizer_Default.epf [2022-12-13 19:30:59,029 INFO L113 SettingsManager]: Loading preferences was successful [2022-12-13 19:30:59,030 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-12-13 19:30:59,030 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-12-13 19:30:59,035 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-12-13 19:30:59,036 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-12-13 19:30:59,036 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-12-13 19:30:59,036 INFO L138 SettingsManager]: * Use SBE=true [2022-12-13 19:30:59,036 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2022-12-13 19:30:59,036 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2022-12-13 19:30:59,036 INFO L138 SettingsManager]: * Use old map elimination=false [2022-12-13 19:30:59,036 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2022-12-13 19:30:59,037 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2022-12-13 19:30:59,037 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2022-12-13 19:30:59,037 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-12-13 19:30:59,037 INFO L138 SettingsManager]: * sizeof long=4 [2022-12-13 19:30:59,037 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2022-12-13 19:30:59,037 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-12-13 19:30:59,037 INFO L138 SettingsManager]: * sizeof POINTER=4 [2022-12-13 19:30:59,037 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-12-13 19:30:59,038 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2022-12-13 19:30:59,038 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2022-12-13 19:30:59,038 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2022-12-13 19:30:59,038 INFO L138 SettingsManager]: * sizeof long double=12 [2022-12-13 19:30:59,038 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-12-13 19:30:59,038 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2022-12-13 19:30:59,038 INFO L138 SettingsManager]: * Use constant arrays=true [2022-12-13 19:30:59,038 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2022-12-13 19:30:59,039 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-12-13 19:30:59,039 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-12-13 19:30:59,039 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-12-13 19:30:59,039 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-12-13 19:30:59,040 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-12-13 19:30:59,040 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f5200838-b26d-417b-8c3a-fd86d82f1b34/bin/uautomizer-uyxdKDjOR8/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f5200838-b26d-417b-8c3a-fd86d82f1b34/bin/uautomizer-uyxdKDjOR8 Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> d8722862ca37b1ee13dec8b9e420cd40ba7901837b8f3b6258499da6e8a2ca6f [2022-12-13 19:30:59,203 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-12-13 19:30:59,223 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-12-13 19:30:59,226 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-12-13 19:30:59,227 INFO L271 PluginConnector]: Initializing CDTParser... [2022-12-13 19:30:59,228 INFO L275 PluginConnector]: CDTParser initialized [2022-12-13 19:30:59,229 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f5200838-b26d-417b-8c3a-fd86d82f1b34/bin/uautomizer-uyxdKDjOR8/../../sv-benchmarks/c/systemc/transmitter.05.cil.c [2022-12-13 19:31:01,860 INFO L500 CDTParser]: Created temporary CDT project at NULL [2022-12-13 19:31:02,033 INFO L351 CDTParser]: Found 1 translation units. [2022-12-13 19:31:02,033 INFO L172 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f5200838-b26d-417b-8c3a-fd86d82f1b34/sv-benchmarks/c/systemc/transmitter.05.cil.c [2022-12-13 19:31:02,043 INFO L394 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f5200838-b26d-417b-8c3a-fd86d82f1b34/bin/uautomizer-uyxdKDjOR8/data/93aa70ecf/71808ef9c08949f0b4c2f51999a4ca64/FLAG59233f792 [2022-12-13 19:31:02,053 INFO L402 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f5200838-b26d-417b-8c3a-fd86d82f1b34/bin/uautomizer-uyxdKDjOR8/data/93aa70ecf/71808ef9c08949f0b4c2f51999a4ca64 [2022-12-13 19:31:02,055 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-12-13 19:31:02,056 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-12-13 19:31:02,057 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-12-13 19:31:02,057 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-12-13 19:31:02,060 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-12-13 19:31:02,060 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.12 07:31:02" (1/1) ... [2022-12-13 19:31:02,061 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@3b94cc51 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 07:31:02, skipping insertion in model container [2022-12-13 19:31:02,061 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.12 07:31:02" (1/1) ... [2022-12-13 19:31:02,067 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-12-13 19:31:02,091 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-12-13 19:31:02,198 WARN L237 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f5200838-b26d-417b-8c3a-fd86d82f1b34/sv-benchmarks/c/systemc/transmitter.05.cil.c[706,719] [2022-12-13 19:31:02,245 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-12-13 19:31:02,255 INFO L203 MainTranslator]: Completed pre-run [2022-12-13 19:31:02,264 WARN L237 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f5200838-b26d-417b-8c3a-fd86d82f1b34/sv-benchmarks/c/systemc/transmitter.05.cil.c[706,719] [2022-12-13 19:31:02,290 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-12-13 19:31:02,302 INFO L208 MainTranslator]: Completed translation [2022-12-13 19:31:02,303 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 07:31:02 WrapperNode [2022-12-13 19:31:02,303 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-12-13 19:31:02,304 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-12-13 19:31:02,304 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-12-13 19:31:02,304 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-12-13 19:31:02,309 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 07:31:02" (1/1) ... [2022-12-13 19:31:02,317 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 07:31:02" (1/1) ... [2022-12-13 19:31:02,358 INFO L138 Inliner]: procedures = 38, calls = 45, calls flagged for inlining = 40, calls inlined = 86, statements flattened = 1229 [2022-12-13 19:31:02,358 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-12-13 19:31:02,359 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-12-13 19:31:02,359 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-12-13 19:31:02,359 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-12-13 19:31:02,369 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 07:31:02" (1/1) ... [2022-12-13 19:31:02,369 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 07:31:02" (1/1) ... [2022-12-13 19:31:02,373 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 07:31:02" (1/1) ... [2022-12-13 19:31:02,374 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 07:31:02" (1/1) ... [2022-12-13 19:31:02,388 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 07:31:02" (1/1) ... [2022-12-13 19:31:02,401 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 07:31:02" (1/1) ... [2022-12-13 19:31:02,403 INFO L185 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 07:31:02" (1/1) ... [2022-12-13 19:31:02,407 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 07:31:02" (1/1) ... [2022-12-13 19:31:02,414 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-12-13 19:31:02,415 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-12-13 19:31:02,415 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-12-13 19:31:02,415 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-12-13 19:31:02,416 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 07:31:02" (1/1) ... [2022-12-13 19:31:02,423 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-12-13 19:31:02,434 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f5200838-b26d-417b-8c3a-fd86d82f1b34/bin/uautomizer-uyxdKDjOR8/z3 [2022-12-13 19:31:02,446 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f5200838-b26d-417b-8c3a-fd86d82f1b34/bin/uautomizer-uyxdKDjOR8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-12-13 19:31:02,448 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f5200838-b26d-417b-8c3a-fd86d82f1b34/bin/uautomizer-uyxdKDjOR8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2022-12-13 19:31:02,492 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-12-13 19:31:02,492 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-12-13 19:31:02,492 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-12-13 19:31:02,492 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-12-13 19:31:02,567 INFO L235 CfgBuilder]: Building ICFG [2022-12-13 19:31:02,569 INFO L261 CfgBuilder]: Building CFG for each procedure with an implementation [2022-12-13 19:31:03,224 INFO L276 CfgBuilder]: Performing block encoding [2022-12-13 19:31:03,233 INFO L295 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-12-13 19:31:03,233 INFO L300 CfgBuilder]: Removed 9 assume(true) statements. [2022-12-13 19:31:03,235 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.12 07:31:03 BoogieIcfgContainer [2022-12-13 19:31:03,235 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-12-13 19:31:03,235 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2022-12-13 19:31:03,236 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2022-12-13 19:31:03,238 INFO L275 PluginConnector]: BuchiAutomizer initialized [2022-12-13 19:31:03,239 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-12-13 19:31:03,239 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 13.12 07:31:02" (1/3) ... [2022-12-13 19:31:03,239 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@43663095 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 13.12 07:31:03, skipping insertion in model container [2022-12-13 19:31:03,240 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-12-13 19:31:03,240 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 07:31:02" (2/3) ... [2022-12-13 19:31:03,240 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@43663095 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 13.12 07:31:03, skipping insertion in model container [2022-12-13 19:31:03,240 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-12-13 19:31:03,240 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.12 07:31:03" (3/3) ... [2022-12-13 19:31:03,241 INFO L332 chiAutomizerObserver]: Analyzing ICFG transmitter.05.cil.c [2022-12-13 19:31:03,298 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2022-12-13 19:31:03,298 INFO L304 stractBuchiCegarLoop]: Hoare is false [2022-12-13 19:31:03,298 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2022-12-13 19:31:03,298 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2022-12-13 19:31:03,298 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2022-12-13 19:31:03,298 INFO L308 stractBuchiCegarLoop]: Difference is false [2022-12-13 19:31:03,298 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2022-12-13 19:31:03,299 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2022-12-13 19:31:03,302 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 505 states, 504 states have (on average 1.5337301587301588) internal successors, (773), 504 states have internal predecessors, (773), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:31:03,327 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 424 [2022-12-13 19:31:03,327 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 19:31:03,327 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 19:31:03,334 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:31:03,334 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:31:03,334 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2022-12-13 19:31:03,336 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 505 states, 504 states have (on average 1.5337301587301588) internal successors, (773), 504 states have internal predecessors, (773), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:31:03,347 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 424 [2022-12-13 19:31:03,347 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 19:31:03,347 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 19:31:03,350 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:31:03,350 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:31:03,357 INFO L748 eck$LassoCheckResult]: Stem: 149#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 409#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 239#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 406#update_channels_returnLabel#1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 254#L401true assume !(1 == ~m_i~0);~m_st~0 := 2; 345#L401-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 113#L406-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 398#L411-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 385#L416-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 461#L421-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 327#L426-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 92#L586true assume 0 == ~M_E~0;~M_E~0 := 1; 125#L586-2true assume !(0 == ~T1_E~0); 228#L591-1true assume !(0 == ~T2_E~0); 206#L596-1true assume !(0 == ~T3_E~0); 270#L601-1true assume !(0 == ~T4_E~0); 245#L606-1true assume !(0 == ~T5_E~0); 464#L611-1true assume !(0 == ~E_1~0); 344#L616-1true assume !(0 == ~E_2~0); 350#L621-1true assume 0 == ~E_3~0;~E_3~0 := 1; 48#L626-1true assume !(0 == ~E_4~0); 301#L631-1true assume !(0 == ~E_5~0); 145#L636-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 46#L279true assume 1 == ~m_pc~0; 213#L280true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 368#L290true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 131#is_master_triggered_returnLabel#1true activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 269#L720true assume !(0 != activate_threads_~tmp~1#1); 486#L720-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 150#L298true assume !(1 == ~t1_pc~0); 21#L298-2true is_transmit1_triggered_~__retres1~1#1 := 0; 451#L309true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 33#is_transmit1_triggered_returnLabel#1true activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 52#L728true assume !(0 != activate_threads_~tmp___0~0#1); 261#L728-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 128#L317true assume 1 == ~t2_pc~0; 236#L318true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 468#L328true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 242#is_transmit2_triggered_returnLabel#1true activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 156#L736true assume !(0 != activate_threads_~tmp___1~0#1); 420#L736-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 323#L336true assume 1 == ~t3_pc~0; 187#L337true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 487#L347true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9#is_transmit3_triggered_returnLabel#1true activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 278#L744true assume !(0 != activate_threads_~tmp___2~0#1); 334#L744-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 400#L355true assume !(1 == ~t4_pc~0); 332#L355-2true is_transmit4_triggered_~__retres1~4#1 := 0; 105#L366true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 70#is_transmit4_triggered_returnLabel#1true activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 315#L752true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 60#L752-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 371#L374true assume 1 == ~t5_pc~0; 383#L375true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 386#L385true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 135#is_transmit5_triggered_returnLabel#1true activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 425#L760true assume !(0 != activate_threads_~tmp___4~0#1); 230#L760-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 433#L649true assume 1 == ~M_E~0;~M_E~0 := 2; 492#L649-2true assume !(1 == ~T1_E~0); 39#L654-1true assume !(1 == ~T2_E~0); 266#L659-1true assume !(1 == ~T3_E~0); 155#L664-1true assume !(1 == ~T4_E~0); 35#L669-1true assume !(1 == ~T5_E~0); 317#L674-1true assume !(1 == ~E_1~0); 330#L679-1true assume !(1 == ~E_2~0); 95#L684-1true assume 1 == ~E_3~0;~E_3~0 := 2; 201#L689-1true assume !(1 == ~E_4~0); 483#L694-1true assume !(1 == ~E_5~0); 200#L699-1true assume { :end_inline_reset_delta_events } true; 473#L900-2true [2022-12-13 19:31:03,359 INFO L750 eck$LassoCheckResult]: Loop: 473#L900-2true assume !false; 501#L901true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 58#L561true assume false; 74#eval_returnLabel#1true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 360#update_channels_returnLabel#2true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 421#L586-3true assume 0 == ~M_E~0;~M_E~0 := 1; 316#L586-5true assume !(0 == ~T1_E~0); 215#L591-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 108#L596-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 226#L601-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 373#L606-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 258#L611-3true assume 0 == ~E_1~0;~E_1~0 := 1; 262#L616-3true assume 0 == ~E_2~0;~E_2~0 := 1; 42#L621-3true assume 0 == ~E_3~0;~E_3~0 := 1; 20#L626-3true assume !(0 == ~E_4~0); 502#L631-3true assume 0 == ~E_5~0;~E_5~0 := 1; 23#L636-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 430#L279-18true assume 1 == ~m_pc~0; 80#L280-6true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 219#L290-6true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 160#is_master_triggered_returnLabel#7true activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 391#L720-18true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 346#L720-20true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 229#L298-18true assume !(1 == ~t1_pc~0); 8#L298-20true is_transmit1_triggered_~__retres1~1#1 := 0; 112#L309-6true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 418#is_transmit1_triggered_returnLabel#7true activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 123#L728-18true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 444#L728-20true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 207#L317-18true assume !(1 == ~t2_pc~0); 225#L317-20true is_transmit2_triggered_~__retres1~2#1 := 0; 238#L328-6true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 234#is_transmit2_triggered_returnLabel#7true activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 114#L736-18true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 353#L736-20true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 349#L336-18true assume !(1 == ~t3_pc~0); 489#L336-20true is_transmit3_triggered_~__retres1~3#1 := 0; 394#L347-6true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 260#is_transmit3_triggered_returnLabel#7true activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 176#L744-18true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 77#L744-20true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 288#L355-18true assume 1 == ~t4_pc~0; 411#L356-6true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 417#L366-6true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 179#is_transmit4_triggered_returnLabel#7true activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 211#L752-18true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 132#L752-20true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 333#L374-18true assume 1 == ~t5_pc~0; 458#L375-6true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 172#L385-6true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 133#is_transmit5_triggered_returnLabel#7true activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 446#L760-18true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 272#L760-20true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 456#L649-3true assume 1 == ~M_E~0;~M_E~0 := 2; 186#L649-5true assume !(1 == ~T1_E~0); 169#L654-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 82#L659-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 450#L664-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 24#L669-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 477#L674-3true assume 1 == ~E_1~0;~E_1~0 := 2; 19#L679-3true assume 1 == ~E_2~0;~E_2~0 := 2; 182#L684-3true assume 1 == ~E_3~0;~E_3~0 := 2; 2#L689-3true assume !(1 == ~E_4~0); 137#L694-3true assume 1 == ~E_5~0;~E_5~0 := 2; 17#L699-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 415#L439-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 476#L471-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 214#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 199#L919true assume !(0 == start_simulation_~tmp~3#1); 485#L919-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 298#L439-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 376#L471-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 31#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 192#L874true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 352#L881true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 369#stop_simulation_returnLabel#1true start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 329#L932true assume !(0 != start_simulation_~tmp___0~1#1); 473#L900-2true [2022-12-13 19:31:03,363 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:31:03,363 INFO L85 PathProgramCache]: Analyzing trace with hash -777385748, now seen corresponding path program 1 times [2022-12-13 19:31:03,372 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:31:03,373 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1086133481] [2022-12-13 19:31:03,373 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:31:03,373 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:31:03,458 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:31:03,568 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:31:03,568 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:31:03,568 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1086133481] [2022-12-13 19:31:03,569 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1086133481] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:31:03,569 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:31:03,569 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:31:03,571 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [173190196] [2022-12-13 19:31:03,571 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:31:03,575 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 19:31:03,576 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:31:03,576 INFO L85 PathProgramCache]: Analyzing trace with hash 1202787219, now seen corresponding path program 1 times [2022-12-13 19:31:03,577 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:31:03,577 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [145106684] [2022-12-13 19:31:03,577 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:31:03,577 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:31:03,588 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:31:03,607 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:31:03,607 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:31:03,608 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [145106684] [2022-12-13 19:31:03,608 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [145106684] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:31:03,608 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:31:03,608 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-12-13 19:31:03,608 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1274448638] [2022-12-13 19:31:03,609 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:31:03,610 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 19:31:03,610 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 19:31:03,635 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 19:31:03,635 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 19:31:03,638 INFO L87 Difference]: Start difference. First operand has 505 states, 504 states have (on average 1.5337301587301588) internal successors, (773), 504 states have internal predecessors, (773), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 23.666666666666668) internal successors, (71), 3 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:31:03,677 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 19:31:03,677 INFO L93 Difference]: Finished difference Result 504 states and 752 transitions. [2022-12-13 19:31:03,678 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 504 states and 752 transitions. [2022-12-13 19:31:03,682 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 421 [2022-12-13 19:31:03,688 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 504 states to 498 states and 746 transitions. [2022-12-13 19:31:03,689 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 498 [2022-12-13 19:31:03,691 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 498 [2022-12-13 19:31:03,691 INFO L73 IsDeterministic]: Start isDeterministic. Operand 498 states and 746 transitions. [2022-12-13 19:31:03,693 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 19:31:03,693 INFO L218 hiAutomatonCegarLoop]: Abstraction has 498 states and 746 transitions. [2022-12-13 19:31:03,706 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 498 states and 746 transitions. [2022-12-13 19:31:03,724 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 498 to 498. [2022-12-13 19:31:03,725 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 498 states, 498 states have (on average 1.497991967871486) internal successors, (746), 497 states have internal predecessors, (746), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:31:03,727 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 498 states to 498 states and 746 transitions. [2022-12-13 19:31:03,728 INFO L240 hiAutomatonCegarLoop]: Abstraction has 498 states and 746 transitions. [2022-12-13 19:31:03,729 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 19:31:03,732 INFO L428 stractBuchiCegarLoop]: Abstraction has 498 states and 746 transitions. [2022-12-13 19:31:03,733 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2022-12-13 19:31:03,733 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 498 states and 746 transitions. [2022-12-13 19:31:03,736 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 421 [2022-12-13 19:31:03,736 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 19:31:03,736 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 19:31:03,738 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:31:03,738 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:31:03,739 INFO L748 eck$LassoCheckResult]: Stem: 1285#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 1286#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 1391#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1392#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1409#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 1410#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1221#L406-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 1222#L411-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1496#L416-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1497#L421-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 1465#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1190#L586 assume 0 == ~M_E~0;~M_E~0 := 1; 1191#L586-2 assume !(0 == ~T1_E~0); 1244#L591-1 assume !(0 == ~T2_E~0); 1355#L596-1 assume !(0 == ~T3_E~0); 1356#L601-1 assume !(0 == ~T4_E~0); 1397#L606-1 assume !(0 == ~T5_E~0); 1398#L611-1 assume !(0 == ~E_1~0); 1473#L616-1 assume !(0 == ~E_2~0); 1474#L621-1 assume 0 == ~E_3~0;~E_3~0 := 1; 1118#L626-1 assume !(0 == ~E_4~0); 1119#L631-1 assume !(0 == ~E_5~0); 1280#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1113#L279 assume 1 == ~m_pc~0; 1114#L280 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 1361#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1258#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1259#L720 assume !(0 != activate_threads_~tmp~1#1); 1420#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1287#L298 assume !(1 == ~t1_pc~0); 1062#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1063#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1088#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1089#L728 assume !(0 != activate_threads_~tmp___0~0#1); 1125#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1250#L317 assume 1 == ~t2_pc~0; 1251#L318 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1389#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1396#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1296#L736 assume !(0 != activate_threads_~tmp___1~0#1); 1297#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1462#L336 assume 1 == ~t3_pc~0; 1333#L337 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1334#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1035#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1036#L744 assume !(0 != activate_threads_~tmp___2~0#1); 1428#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1469#L355 assume !(1 == ~t4_pc~0); 1352#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1208#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1156#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1157#L752 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1136#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1137#L374 assume 1 == ~t5_pc~0; 1489#L375 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1271#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1264#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1265#L760 assume !(0 != activate_threads_~tmp___4~0#1); 1380#L760-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1381#L649 assume 1 == ~M_E~0;~M_E~0 := 2; 1508#L649-2 assume !(1 == ~T1_E~0); 1101#L654-1 assume !(1 == ~T2_E~0); 1102#L659-1 assume !(1 == ~T3_E~0); 1295#L664-1 assume !(1 == ~T4_E~0); 1093#L669-1 assume !(1 == ~T5_E~0); 1094#L674-1 assume !(1 == ~E_1~0); 1454#L679-1 assume !(1 == ~E_2~0); 1195#L684-1 assume 1 == ~E_3~0;~E_3~0 := 2; 1196#L689-1 assume !(1 == ~E_4~0); 1348#L694-1 assume !(1 == ~E_5~0); 1346#L699-1 assume { :end_inline_reset_delta_events } true; 1347#L900-2 [2022-12-13 19:31:03,739 INFO L750 eck$LassoCheckResult]: Loop: 1347#L900-2 assume !false; 1514#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1043#L561 assume !false; 1134#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 1314#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 1064#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 1065#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1184#L486 assume !(0 != eval_~tmp~0#1); 1163#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1164#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1485#L586-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1453#L586-5 assume !(0 == ~T1_E~0); 1363#L591-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1212#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1213#L601-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1376#L606-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1412#L611-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1413#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1107#L621-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1060#L626-3 assume !(0 == ~E_4~0); 1061#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1066#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1067#L279-18 assume 1 == ~m_pc~0; 1171#L280-6 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 1172#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1300#is_master_triggered_returnLabel#7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1301#L720-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1475#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1379#L298-18 assume 1 == ~t1_pc~0; 1040#L299-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1034#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1220#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1240#L728-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1241#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1357#L317-18 assume 1 == ~t2_pc~0; 1272#L318-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1274#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1387#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1223#L736-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1224#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1478#L336-18 assume 1 == ~t3_pc~0; 1458#L337-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1459#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1414#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1322#L744-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1165#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1166#L355-18 assume !(1 == ~t4_pc~0); 1426#L355-20 is_transmit4_triggered_~__retres1~4#1 := 0; 1427#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1327#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1328#L752-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1260#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1261#L374-18 assume !(1 == ~t5_pc~0); 1440#L374-20 is_transmit5_triggered_~__retres1~5#1 := 0; 1319#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1262#is_transmit5_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1263#L760-18 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1421#L760-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1422#L649-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1332#L649-5 assume !(1 == ~T1_E~0); 1313#L654-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1175#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1176#L664-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1068#L669-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1069#L674-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1058#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1059#L684-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1018#L689-3 assume !(1 == ~E_4~0); 1019#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1053#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 1054#L439-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 1056#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 1362#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 1345#L919 assume !(0 == start_simulation_~tmp~3#1); 1071#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 1444#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 1047#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 1085#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 1086#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1340#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1479#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 1467#L932 assume !(0 != start_simulation_~tmp___0~1#1); 1347#L900-2 [2022-12-13 19:31:03,740 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:31:03,740 INFO L85 PathProgramCache]: Analyzing trace with hash 438767978, now seen corresponding path program 1 times [2022-12-13 19:31:03,741 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:31:03,741 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1228095820] [2022-12-13 19:31:03,741 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:31:03,741 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:31:03,755 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:31:03,798 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:31:03,798 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:31:03,798 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1228095820] [2022-12-13 19:31:03,798 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1228095820] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:31:03,799 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:31:03,799 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:31:03,799 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2095898143] [2022-12-13 19:31:03,799 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:31:03,799 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 19:31:03,800 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:31:03,800 INFO L85 PathProgramCache]: Analyzing trace with hash 996767661, now seen corresponding path program 1 times [2022-12-13 19:31:03,800 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:31:03,808 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [25399351] [2022-12-13 19:31:03,808 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:31:03,809 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:31:03,833 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:31:03,903 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:31:03,903 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:31:03,903 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [25399351] [2022-12-13 19:31:03,904 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [25399351] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:31:03,904 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:31:03,904 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-12-13 19:31:03,904 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [325970446] [2022-12-13 19:31:03,904 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:31:03,905 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 19:31:03,905 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 19:31:03,905 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 19:31:03,905 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 19:31:03,905 INFO L87 Difference]: Start difference. First operand 498 states and 746 transitions. cyclomatic complexity: 249 Second operand has 3 states, 3 states have (on average 23.666666666666668) internal successors, (71), 3 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:31:03,918 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 19:31:03,918 INFO L93 Difference]: Finished difference Result 498 states and 745 transitions. [2022-12-13 19:31:03,918 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 498 states and 745 transitions. [2022-12-13 19:31:03,920 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 421 [2022-12-13 19:31:03,922 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 498 states to 498 states and 745 transitions. [2022-12-13 19:31:03,922 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 498 [2022-12-13 19:31:03,922 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 498 [2022-12-13 19:31:03,923 INFO L73 IsDeterministic]: Start isDeterministic. Operand 498 states and 745 transitions. [2022-12-13 19:31:03,924 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 19:31:03,924 INFO L218 hiAutomatonCegarLoop]: Abstraction has 498 states and 745 transitions. [2022-12-13 19:31:03,924 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 498 states and 745 transitions. [2022-12-13 19:31:03,930 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 498 to 498. [2022-12-13 19:31:03,931 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 498 states, 498 states have (on average 1.4959839357429718) internal successors, (745), 497 states have internal predecessors, (745), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:31:03,932 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 498 states to 498 states and 745 transitions. [2022-12-13 19:31:03,932 INFO L240 hiAutomatonCegarLoop]: Abstraction has 498 states and 745 transitions. [2022-12-13 19:31:03,933 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 19:31:03,933 INFO L428 stractBuchiCegarLoop]: Abstraction has 498 states and 745 transitions. [2022-12-13 19:31:03,934 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2022-12-13 19:31:03,934 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 498 states and 745 transitions. [2022-12-13 19:31:03,936 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 421 [2022-12-13 19:31:03,937 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 19:31:03,937 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 19:31:03,938 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:31:03,938 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:31:03,939 INFO L748 eck$LassoCheckResult]: Stem: 2290#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 2291#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 2396#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2397#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2414#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 2415#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2226#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2227#L411-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 2501#L416-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2502#L421-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 2470#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2195#L586 assume 0 == ~M_E~0;~M_E~0 := 1; 2196#L586-2 assume !(0 == ~T1_E~0); 2249#L591-1 assume !(0 == ~T2_E~0); 2360#L596-1 assume !(0 == ~T3_E~0); 2361#L601-1 assume !(0 == ~T4_E~0); 2402#L606-1 assume !(0 == ~T5_E~0); 2403#L611-1 assume !(0 == ~E_1~0); 2478#L616-1 assume !(0 == ~E_2~0); 2479#L621-1 assume 0 == ~E_3~0;~E_3~0 := 1; 2123#L626-1 assume !(0 == ~E_4~0); 2124#L631-1 assume !(0 == ~E_5~0); 2285#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2118#L279 assume 1 == ~m_pc~0; 2119#L280 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 2366#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2263#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 2264#L720 assume !(0 != activate_threads_~tmp~1#1); 2425#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2292#L298 assume !(1 == ~t1_pc~0); 2067#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2068#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2093#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 2094#L728 assume !(0 != activate_threads_~tmp___0~0#1); 2130#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2255#L317 assume 1 == ~t2_pc~0; 2256#L318 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2394#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2401#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2301#L736 assume !(0 != activate_threads_~tmp___1~0#1); 2302#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2467#L336 assume 1 == ~t3_pc~0; 2338#L337 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 2339#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2040#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2041#L744 assume !(0 != activate_threads_~tmp___2~0#1); 2433#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2474#L355 assume !(1 == ~t4_pc~0); 2357#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 2213#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2161#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2162#L752 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 2141#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2142#L374 assume 1 == ~t5_pc~0; 2494#L375 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 2276#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2269#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2270#L760 assume !(0 != activate_threads_~tmp___4~0#1); 2385#L760-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2386#L649 assume 1 == ~M_E~0;~M_E~0 := 2; 2513#L649-2 assume !(1 == ~T1_E~0); 2106#L654-1 assume !(1 == ~T2_E~0); 2107#L659-1 assume !(1 == ~T3_E~0); 2300#L664-1 assume !(1 == ~T4_E~0); 2098#L669-1 assume !(1 == ~T5_E~0); 2099#L674-1 assume !(1 == ~E_1~0); 2459#L679-1 assume !(1 == ~E_2~0); 2200#L684-1 assume 1 == ~E_3~0;~E_3~0 := 2; 2201#L689-1 assume !(1 == ~E_4~0); 2353#L694-1 assume !(1 == ~E_5~0); 2351#L699-1 assume { :end_inline_reset_delta_events } true; 2352#L900-2 [2022-12-13 19:31:03,939 INFO L750 eck$LassoCheckResult]: Loop: 2352#L900-2 assume !false; 2519#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2048#L561 assume !false; 2139#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 2319#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 2069#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 2070#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 2189#L486 assume !(0 != eval_~tmp~0#1); 2168#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2169#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2490#L586-3 assume 0 == ~M_E~0;~M_E~0 := 1; 2458#L586-5 assume !(0 == ~T1_E~0); 2368#L591-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2217#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2218#L601-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2381#L606-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2417#L611-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2418#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2112#L621-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2065#L626-3 assume !(0 == ~E_4~0); 2066#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2071#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2072#L279-18 assume 1 == ~m_pc~0; 2176#L280-6 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 2177#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2305#is_master_triggered_returnLabel#7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 2306#L720-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2480#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2384#L298-18 assume !(1 == ~t1_pc~0); 2038#L298-20 is_transmit1_triggered_~__retres1~1#1 := 0; 2039#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2225#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 2245#L728-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2246#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2362#L317-18 assume 1 == ~t2_pc~0; 2277#L318-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2279#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2392#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2228#L736-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2229#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2483#L336-18 assume !(1 == ~t3_pc~0); 2465#L336-20 is_transmit3_triggered_~__retres1~3#1 := 0; 2464#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2419#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2327#L744-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2170#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2171#L355-18 assume 1 == ~t4_pc~0; 2443#L356-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2432#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2332#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2333#L752-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 2265#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2266#L374-18 assume 1 == ~t5_pc~0; 2473#L375-6 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 2324#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2267#is_transmit5_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2268#L760-18 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 2426#L760-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2427#L649-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2337#L649-5 assume !(1 == ~T1_E~0); 2318#L654-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2180#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2181#L664-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2073#L669-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2074#L674-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2063#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2064#L684-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2023#L689-3 assume !(1 == ~E_4~0); 2024#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2058#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 2059#L439-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 2061#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 2367#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 2350#L919 assume !(0 == start_simulation_~tmp~3#1); 2076#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 2449#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 2052#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 2090#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 2091#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2345#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2484#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 2472#L932 assume !(0 != start_simulation_~tmp___0~1#1); 2352#L900-2 [2022-12-13 19:31:03,940 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:31:03,940 INFO L85 PathProgramCache]: Analyzing trace with hash 2124947816, now seen corresponding path program 1 times [2022-12-13 19:31:03,940 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:31:03,940 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1472443805] [2022-12-13 19:31:03,940 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:31:03,940 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:31:03,952 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:31:03,981 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:31:03,981 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:31:03,982 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1472443805] [2022-12-13 19:31:03,982 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1472443805] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:31:03,982 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:31:03,982 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:31:03,982 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1855623986] [2022-12-13 19:31:03,982 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:31:03,983 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 19:31:03,983 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:31:03,983 INFO L85 PathProgramCache]: Analyzing trace with hash 766015341, now seen corresponding path program 1 times [2022-12-13 19:31:03,984 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:31:03,984 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1918789697] [2022-12-13 19:31:03,984 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:31:03,984 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:31:03,998 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:31:04,029 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:31:04,029 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:31:04,029 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1918789697] [2022-12-13 19:31:04,029 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1918789697] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:31:04,030 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:31:04,030 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:31:04,030 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [691630381] [2022-12-13 19:31:04,030 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:31:04,030 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 19:31:04,030 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 19:31:04,031 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 19:31:04,031 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 19:31:04,031 INFO L87 Difference]: Start difference. First operand 498 states and 745 transitions. cyclomatic complexity: 248 Second operand has 3 states, 3 states have (on average 23.666666666666668) internal successors, (71), 3 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:31:04,041 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 19:31:04,041 INFO L93 Difference]: Finished difference Result 498 states and 744 transitions. [2022-12-13 19:31:04,041 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 498 states and 744 transitions. [2022-12-13 19:31:04,043 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 421 [2022-12-13 19:31:04,045 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 498 states to 498 states and 744 transitions. [2022-12-13 19:31:04,045 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 498 [2022-12-13 19:31:04,045 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 498 [2022-12-13 19:31:04,046 INFO L73 IsDeterministic]: Start isDeterministic. Operand 498 states and 744 transitions. [2022-12-13 19:31:04,046 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 19:31:04,046 INFO L218 hiAutomatonCegarLoop]: Abstraction has 498 states and 744 transitions. [2022-12-13 19:31:04,047 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 498 states and 744 transitions. [2022-12-13 19:31:04,052 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 498 to 498. [2022-12-13 19:31:04,052 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 498 states, 498 states have (on average 1.4939759036144578) internal successors, (744), 497 states have internal predecessors, (744), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:31:04,053 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 498 states to 498 states and 744 transitions. [2022-12-13 19:31:04,054 INFO L240 hiAutomatonCegarLoop]: Abstraction has 498 states and 744 transitions. [2022-12-13 19:31:04,054 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 19:31:04,055 INFO L428 stractBuchiCegarLoop]: Abstraction has 498 states and 744 transitions. [2022-12-13 19:31:04,055 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2022-12-13 19:31:04,055 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 498 states and 744 transitions. [2022-12-13 19:31:04,057 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 421 [2022-12-13 19:31:04,058 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 19:31:04,058 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 19:31:04,059 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:31:04,059 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:31:04,060 INFO L748 eck$LassoCheckResult]: Stem: 3293#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 3294#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 3399#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3400#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3417#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 3418#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3229#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3230#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3504#L416-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 3505#L421-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 3473#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3198#L586 assume 0 == ~M_E~0;~M_E~0 := 1; 3199#L586-2 assume !(0 == ~T1_E~0); 3252#L591-1 assume !(0 == ~T2_E~0); 3363#L596-1 assume !(0 == ~T3_E~0); 3364#L601-1 assume !(0 == ~T4_E~0); 3405#L606-1 assume !(0 == ~T5_E~0); 3406#L611-1 assume !(0 == ~E_1~0); 3481#L616-1 assume !(0 == ~E_2~0); 3482#L621-1 assume 0 == ~E_3~0;~E_3~0 := 1; 3126#L626-1 assume !(0 == ~E_4~0); 3127#L631-1 assume !(0 == ~E_5~0); 3288#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3121#L279 assume 1 == ~m_pc~0; 3122#L280 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 3369#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3266#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 3267#L720 assume !(0 != activate_threads_~tmp~1#1); 3428#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3295#L298 assume !(1 == ~t1_pc~0); 3070#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 3071#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3096#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 3097#L728 assume !(0 != activate_threads_~tmp___0~0#1); 3133#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3258#L317 assume 1 == ~t2_pc~0; 3259#L318 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3397#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3404#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3304#L736 assume !(0 != activate_threads_~tmp___1~0#1); 3305#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3470#L336 assume 1 == ~t3_pc~0; 3341#L337 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3342#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3043#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 3044#L744 assume !(0 != activate_threads_~tmp___2~0#1); 3436#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3477#L355 assume !(1 == ~t4_pc~0); 3360#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 3216#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3164#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3165#L752 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 3144#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3145#L374 assume 1 == ~t5_pc~0; 3497#L375 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 3279#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3272#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3273#L760 assume !(0 != activate_threads_~tmp___4~0#1); 3388#L760-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3389#L649 assume 1 == ~M_E~0;~M_E~0 := 2; 3516#L649-2 assume !(1 == ~T1_E~0); 3109#L654-1 assume !(1 == ~T2_E~0); 3110#L659-1 assume !(1 == ~T3_E~0); 3303#L664-1 assume !(1 == ~T4_E~0); 3101#L669-1 assume !(1 == ~T5_E~0); 3102#L674-1 assume !(1 == ~E_1~0); 3462#L679-1 assume !(1 == ~E_2~0); 3203#L684-1 assume 1 == ~E_3~0;~E_3~0 := 2; 3204#L689-1 assume !(1 == ~E_4~0); 3356#L694-1 assume !(1 == ~E_5~0); 3354#L699-1 assume { :end_inline_reset_delta_events } true; 3355#L900-2 [2022-12-13 19:31:04,060 INFO L750 eck$LassoCheckResult]: Loop: 3355#L900-2 assume !false; 3522#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3051#L561 assume !false; 3142#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 3322#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 3072#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 3073#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 3192#L486 assume !(0 != eval_~tmp~0#1); 3171#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3172#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3493#L586-3 assume 0 == ~M_E~0;~M_E~0 := 1; 3461#L586-5 assume !(0 == ~T1_E~0); 3371#L591-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3220#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3221#L601-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3384#L606-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 3420#L611-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3421#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3115#L621-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3068#L626-3 assume !(0 == ~E_4~0); 3069#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 3074#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3075#L279-18 assume 1 == ~m_pc~0; 3179#L280-6 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 3180#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3308#is_master_triggered_returnLabel#7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 3309#L720-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3483#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3387#L298-18 assume !(1 == ~t1_pc~0); 3041#L298-20 is_transmit1_triggered_~__retres1~1#1 := 0; 3042#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3228#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 3248#L728-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3249#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3365#L317-18 assume 1 == ~t2_pc~0; 3280#L318-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3282#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3395#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3231#L736-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3232#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3486#L336-18 assume 1 == ~t3_pc~0; 3466#L337-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3467#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3422#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 3330#L744-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3173#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3174#L355-18 assume 1 == ~t4_pc~0; 3446#L356-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3435#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3335#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3336#L752-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 3268#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3269#L374-18 assume 1 == ~t5_pc~0; 3476#L375-6 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 3327#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3270#is_transmit5_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3271#L760-18 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 3429#L760-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3430#L649-3 assume 1 == ~M_E~0;~M_E~0 := 2; 3340#L649-5 assume !(1 == ~T1_E~0); 3321#L654-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3183#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3184#L664-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3076#L669-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3077#L674-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3066#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3067#L684-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3026#L689-3 assume !(1 == ~E_4~0); 3027#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3061#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 3062#L439-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 3064#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 3370#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 3353#L919 assume !(0 == start_simulation_~tmp~3#1); 3079#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 3452#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 3055#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 3093#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 3094#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3348#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3487#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 3475#L932 assume !(0 != start_simulation_~tmp___0~1#1); 3355#L900-2 [2022-12-13 19:31:04,060 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:31:04,060 INFO L85 PathProgramCache]: Analyzing trace with hash -2115626582, now seen corresponding path program 1 times [2022-12-13 19:31:04,061 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:31:04,061 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1268760323] [2022-12-13 19:31:04,061 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:31:04,061 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:31:04,077 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:31:04,095 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:31:04,095 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:31:04,095 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1268760323] [2022-12-13 19:31:04,096 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1268760323] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:31:04,096 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:31:04,096 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:31:04,096 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [884162966] [2022-12-13 19:31:04,096 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:31:04,096 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 19:31:04,097 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:31:04,097 INFO L85 PathProgramCache]: Analyzing trace with hash -1373437554, now seen corresponding path program 1 times [2022-12-13 19:31:04,097 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:31:04,097 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [65836528] [2022-12-13 19:31:04,097 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:31:04,098 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:31:04,106 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:31:04,125 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:31:04,125 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:31:04,125 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [65836528] [2022-12-13 19:31:04,125 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [65836528] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:31:04,126 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:31:04,126 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:31:04,126 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1947984036] [2022-12-13 19:31:04,126 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:31:04,126 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 19:31:04,126 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 19:31:04,127 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 19:31:04,127 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 19:31:04,127 INFO L87 Difference]: Start difference. First operand 498 states and 744 transitions. cyclomatic complexity: 247 Second operand has 3 states, 3 states have (on average 23.666666666666668) internal successors, (71), 3 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:31:04,140 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 19:31:04,140 INFO L93 Difference]: Finished difference Result 498 states and 743 transitions. [2022-12-13 19:31:04,140 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 498 states and 743 transitions. [2022-12-13 19:31:04,143 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 421 [2022-12-13 19:31:04,146 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 498 states to 498 states and 743 transitions. [2022-12-13 19:31:04,146 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 498 [2022-12-13 19:31:04,146 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 498 [2022-12-13 19:31:04,147 INFO L73 IsDeterministic]: Start isDeterministic. Operand 498 states and 743 transitions. [2022-12-13 19:31:04,147 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 19:31:04,147 INFO L218 hiAutomatonCegarLoop]: Abstraction has 498 states and 743 transitions. [2022-12-13 19:31:04,148 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 498 states and 743 transitions. [2022-12-13 19:31:04,154 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 498 to 498. [2022-12-13 19:31:04,155 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 498 states, 498 states have (on average 1.4919678714859437) internal successors, (743), 497 states have internal predecessors, (743), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:31:04,156 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 498 states to 498 states and 743 transitions. [2022-12-13 19:31:04,157 INFO L240 hiAutomatonCegarLoop]: Abstraction has 498 states and 743 transitions. [2022-12-13 19:31:04,157 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 19:31:04,158 INFO L428 stractBuchiCegarLoop]: Abstraction has 498 states and 743 transitions. [2022-12-13 19:31:04,158 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2022-12-13 19:31:04,158 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 498 states and 743 transitions. [2022-12-13 19:31:04,159 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 421 [2022-12-13 19:31:04,159 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 19:31:04,159 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 19:31:04,160 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:31:04,160 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:31:04,161 INFO L748 eck$LassoCheckResult]: Stem: 4296#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 4297#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 4402#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4403#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4420#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 4421#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4232#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4233#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 4507#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 4508#L421-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 4476#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4201#L586 assume 0 == ~M_E~0;~M_E~0 := 1; 4202#L586-2 assume !(0 == ~T1_E~0); 4255#L591-1 assume !(0 == ~T2_E~0); 4366#L596-1 assume !(0 == ~T3_E~0); 4367#L601-1 assume !(0 == ~T4_E~0); 4408#L606-1 assume !(0 == ~T5_E~0); 4409#L611-1 assume !(0 == ~E_1~0); 4484#L616-1 assume !(0 == ~E_2~0); 4485#L621-1 assume 0 == ~E_3~0;~E_3~0 := 1; 4129#L626-1 assume !(0 == ~E_4~0); 4130#L631-1 assume !(0 == ~E_5~0); 4291#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4124#L279 assume 1 == ~m_pc~0; 4125#L280 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 4372#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4269#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 4270#L720 assume !(0 != activate_threads_~tmp~1#1); 4431#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4298#L298 assume !(1 == ~t1_pc~0); 4073#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 4074#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4099#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 4100#L728 assume !(0 != activate_threads_~tmp___0~0#1); 4136#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4261#L317 assume 1 == ~t2_pc~0; 4262#L318 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4400#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4407#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 4307#L736 assume !(0 != activate_threads_~tmp___1~0#1); 4308#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4473#L336 assume 1 == ~t3_pc~0; 4344#L337 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 4345#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4046#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4047#L744 assume !(0 != activate_threads_~tmp___2~0#1); 4439#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4480#L355 assume !(1 == ~t4_pc~0); 4363#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 4219#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4167#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4168#L752 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 4147#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4148#L374 assume 1 == ~t5_pc~0; 4500#L375 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 4282#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4275#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4276#L760 assume !(0 != activate_threads_~tmp___4~0#1); 4391#L760-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4392#L649 assume 1 == ~M_E~0;~M_E~0 := 2; 4519#L649-2 assume !(1 == ~T1_E~0); 4112#L654-1 assume !(1 == ~T2_E~0); 4113#L659-1 assume !(1 == ~T3_E~0); 4306#L664-1 assume !(1 == ~T4_E~0); 4104#L669-1 assume !(1 == ~T5_E~0); 4105#L674-1 assume !(1 == ~E_1~0); 4465#L679-1 assume !(1 == ~E_2~0); 4206#L684-1 assume 1 == ~E_3~0;~E_3~0 := 2; 4207#L689-1 assume !(1 == ~E_4~0); 4359#L694-1 assume !(1 == ~E_5~0); 4357#L699-1 assume { :end_inline_reset_delta_events } true; 4358#L900-2 [2022-12-13 19:31:04,161 INFO L750 eck$LassoCheckResult]: Loop: 4358#L900-2 assume !false; 4525#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4054#L561 assume !false; 4145#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 4325#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 4075#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 4076#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 4195#L486 assume !(0 != eval_~tmp~0#1); 4174#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4175#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4496#L586-3 assume 0 == ~M_E~0;~M_E~0 := 1; 4464#L586-5 assume !(0 == ~T1_E~0); 4374#L591-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4223#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4224#L601-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4387#L606-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 4423#L611-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4424#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4118#L621-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4071#L626-3 assume !(0 == ~E_4~0); 4072#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 4077#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4078#L279-18 assume 1 == ~m_pc~0; 4182#L280-6 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 4183#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4311#is_master_triggered_returnLabel#7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 4312#L720-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4486#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4390#L298-18 assume 1 == ~t1_pc~0; 4051#L299-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4045#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4231#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 4251#L728-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4252#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4368#L317-18 assume 1 == ~t2_pc~0; 4283#L318-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4285#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4398#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 4234#L736-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4235#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4489#L336-18 assume 1 == ~t3_pc~0; 4469#L337-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 4470#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4425#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4333#L744-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4176#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4177#L355-18 assume 1 == ~t4_pc~0; 4449#L356-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 4438#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4338#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4339#L752-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 4271#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4272#L374-18 assume !(1 == ~t5_pc~0); 4451#L374-20 is_transmit5_triggered_~__retres1~5#1 := 0; 4330#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4273#is_transmit5_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4274#L760-18 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 4432#L760-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4433#L649-3 assume 1 == ~M_E~0;~M_E~0 := 2; 4343#L649-5 assume !(1 == ~T1_E~0); 4324#L654-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4186#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4187#L664-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4079#L669-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 4080#L674-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4069#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4070#L684-3 assume 1 == ~E_3~0;~E_3~0 := 2; 4029#L689-3 assume !(1 == ~E_4~0); 4030#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 4064#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 4065#L439-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 4067#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 4373#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 4356#L919 assume !(0 == start_simulation_~tmp~3#1); 4082#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 4455#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 4058#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 4096#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 4097#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4351#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4490#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 4478#L932 assume !(0 != start_simulation_~tmp___0~1#1); 4358#L900-2 [2022-12-13 19:31:04,161 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:31:04,161 INFO L85 PathProgramCache]: Analyzing trace with hash -1698229976, now seen corresponding path program 1 times [2022-12-13 19:31:04,161 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:31:04,162 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [471816254] [2022-12-13 19:31:04,162 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:31:04,162 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:31:04,168 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:31:04,183 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:31:04,183 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:31:04,184 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [471816254] [2022-12-13 19:31:04,184 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [471816254] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:31:04,184 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:31:04,184 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:31:04,184 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1749287269] [2022-12-13 19:31:04,184 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:31:04,185 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 19:31:04,185 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:31:04,185 INFO L85 PathProgramCache]: Analyzing trace with hash -1533383026, now seen corresponding path program 1 times [2022-12-13 19:31:04,185 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:31:04,185 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1707937648] [2022-12-13 19:31:04,186 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:31:04,186 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:31:04,193 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:31:04,212 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:31:04,213 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:31:04,213 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1707937648] [2022-12-13 19:31:04,213 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1707937648] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:31:04,213 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:31:04,213 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:31:04,213 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1134494873] [2022-12-13 19:31:04,213 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:31:04,214 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 19:31:04,214 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 19:31:04,214 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 19:31:04,214 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 19:31:04,214 INFO L87 Difference]: Start difference. First operand 498 states and 743 transitions. cyclomatic complexity: 246 Second operand has 3 states, 3 states have (on average 23.666666666666668) internal successors, (71), 3 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:31:04,227 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 19:31:04,228 INFO L93 Difference]: Finished difference Result 498 states and 742 transitions. [2022-12-13 19:31:04,228 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 498 states and 742 transitions. [2022-12-13 19:31:04,231 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 421 [2022-12-13 19:31:04,233 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 498 states to 498 states and 742 transitions. [2022-12-13 19:31:04,233 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 498 [2022-12-13 19:31:04,233 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 498 [2022-12-13 19:31:04,234 INFO L73 IsDeterministic]: Start isDeterministic. Operand 498 states and 742 transitions. [2022-12-13 19:31:04,234 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 19:31:04,234 INFO L218 hiAutomatonCegarLoop]: Abstraction has 498 states and 742 transitions. [2022-12-13 19:31:04,235 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 498 states and 742 transitions. [2022-12-13 19:31:04,241 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 498 to 498. [2022-12-13 19:31:04,242 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 498 states, 498 states have (on average 1.4899598393574298) internal successors, (742), 497 states have internal predecessors, (742), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:31:04,243 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 498 states to 498 states and 742 transitions. [2022-12-13 19:31:04,243 INFO L240 hiAutomatonCegarLoop]: Abstraction has 498 states and 742 transitions. [2022-12-13 19:31:04,244 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 19:31:04,244 INFO L428 stractBuchiCegarLoop]: Abstraction has 498 states and 742 transitions. [2022-12-13 19:31:04,244 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2022-12-13 19:31:04,244 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 498 states and 742 transitions. [2022-12-13 19:31:04,246 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 421 [2022-12-13 19:31:04,247 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 19:31:04,247 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 19:31:04,247 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:31:04,247 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:31:04,248 INFO L748 eck$LassoCheckResult]: Stem: 5299#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 5300#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 5405#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5406#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5423#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 5424#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5235#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5236#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 5510#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 5511#L421-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 5479#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5204#L586 assume 0 == ~M_E~0;~M_E~0 := 1; 5205#L586-2 assume !(0 == ~T1_E~0); 5258#L591-1 assume !(0 == ~T2_E~0); 5369#L596-1 assume !(0 == ~T3_E~0); 5370#L601-1 assume !(0 == ~T4_E~0); 5411#L606-1 assume !(0 == ~T5_E~0); 5412#L611-1 assume !(0 == ~E_1~0); 5487#L616-1 assume !(0 == ~E_2~0); 5488#L621-1 assume 0 == ~E_3~0;~E_3~0 := 1; 5132#L626-1 assume !(0 == ~E_4~0); 5133#L631-1 assume !(0 == ~E_5~0); 5294#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5127#L279 assume 1 == ~m_pc~0; 5128#L280 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 5375#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5272#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 5273#L720 assume !(0 != activate_threads_~tmp~1#1); 5434#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5301#L298 assume !(1 == ~t1_pc~0); 5076#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 5077#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5102#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 5103#L728 assume !(0 != activate_threads_~tmp___0~0#1); 5139#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5264#L317 assume 1 == ~t2_pc~0; 5265#L318 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5403#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5410#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 5310#L736 assume !(0 != activate_threads_~tmp___1~0#1); 5311#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5476#L336 assume 1 == ~t3_pc~0; 5347#L337 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 5348#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5049#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 5050#L744 assume !(0 != activate_threads_~tmp___2~0#1); 5442#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5483#L355 assume !(1 == ~t4_pc~0); 5366#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 5222#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5170#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 5171#L752 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 5150#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5151#L374 assume 1 == ~t5_pc~0; 5503#L375 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 5285#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5278#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5279#L760 assume !(0 != activate_threads_~tmp___4~0#1); 5394#L760-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5395#L649 assume 1 == ~M_E~0;~M_E~0 := 2; 5522#L649-2 assume !(1 == ~T1_E~0); 5115#L654-1 assume !(1 == ~T2_E~0); 5116#L659-1 assume !(1 == ~T3_E~0); 5309#L664-1 assume !(1 == ~T4_E~0); 5107#L669-1 assume !(1 == ~T5_E~0); 5108#L674-1 assume !(1 == ~E_1~0); 5468#L679-1 assume !(1 == ~E_2~0); 5209#L684-1 assume 1 == ~E_3~0;~E_3~0 := 2; 5210#L689-1 assume !(1 == ~E_4~0); 5362#L694-1 assume !(1 == ~E_5~0); 5360#L699-1 assume { :end_inline_reset_delta_events } true; 5361#L900-2 [2022-12-13 19:31:04,248 INFO L750 eck$LassoCheckResult]: Loop: 5361#L900-2 assume !false; 5528#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5057#L561 assume !false; 5148#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 5328#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 5078#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 5079#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 5198#L486 assume !(0 != eval_~tmp~0#1); 5177#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5178#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5499#L586-3 assume 0 == ~M_E~0;~M_E~0 := 1; 5467#L586-5 assume !(0 == ~T1_E~0); 5377#L591-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 5226#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5227#L601-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5390#L606-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 5426#L611-3 assume 0 == ~E_1~0;~E_1~0 := 1; 5427#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5121#L621-3 assume 0 == ~E_3~0;~E_3~0 := 1; 5074#L626-3 assume !(0 == ~E_4~0); 5075#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 5080#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5081#L279-18 assume 1 == ~m_pc~0; 5185#L280-6 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 5186#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5314#is_master_triggered_returnLabel#7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 5315#L720-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 5489#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5393#L298-18 assume !(1 == ~t1_pc~0); 5047#L298-20 is_transmit1_triggered_~__retres1~1#1 := 0; 5048#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5234#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 5254#L728-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 5255#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5371#L317-18 assume 1 == ~t2_pc~0; 5286#L318-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5288#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5401#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 5237#L736-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 5238#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5492#L336-18 assume 1 == ~t3_pc~0; 5472#L337-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 5473#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5428#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 5336#L744-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 5179#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5180#L355-18 assume !(1 == ~t4_pc~0); 5440#L355-20 is_transmit4_triggered_~__retres1~4#1 := 0; 5441#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5341#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 5342#L752-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 5274#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5275#L374-18 assume 1 == ~t5_pc~0; 5482#L375-6 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 5333#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5276#is_transmit5_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5277#L760-18 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 5435#L760-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5436#L649-3 assume 1 == ~M_E~0;~M_E~0 := 2; 5346#L649-5 assume !(1 == ~T1_E~0); 5327#L654-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5189#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 5190#L664-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5082#L669-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 5083#L674-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5072#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5073#L684-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5032#L689-3 assume !(1 == ~E_4~0); 5033#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 5067#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 5068#L439-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 5070#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 5376#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 5359#L919 assume !(0 == start_simulation_~tmp~3#1); 5085#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 5458#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 5061#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 5099#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 5100#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5354#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5493#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 5481#L932 assume !(0 != start_simulation_~tmp___0~1#1); 5361#L900-2 [2022-12-13 19:31:04,248 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:31:04,248 INFO L85 PathProgramCache]: Analyzing trace with hash 1917465066, now seen corresponding path program 1 times [2022-12-13 19:31:04,249 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:31:04,249 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [126428711] [2022-12-13 19:31:04,249 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:31:04,249 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:31:04,259 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:31:04,279 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:31:04,280 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:31:04,280 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [126428711] [2022-12-13 19:31:04,280 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [126428711] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:31:04,280 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:31:04,280 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-12-13 19:31:04,280 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [500460161] [2022-12-13 19:31:04,280 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:31:04,281 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 19:31:04,281 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:31:04,281 INFO L85 PathProgramCache]: Analyzing trace with hash 1156713133, now seen corresponding path program 1 times [2022-12-13 19:31:04,281 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:31:04,282 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1366452683] [2022-12-13 19:31:04,282 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:31:04,282 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:31:04,289 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:31:04,322 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:31:04,322 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:31:04,322 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1366452683] [2022-12-13 19:31:04,322 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1366452683] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:31:04,322 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:31:04,322 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-12-13 19:31:04,323 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1497626495] [2022-12-13 19:31:04,323 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:31:04,323 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 19:31:04,323 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 19:31:04,323 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 19:31:04,324 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 19:31:04,324 INFO L87 Difference]: Start difference. First operand 498 states and 742 transitions. cyclomatic complexity: 245 Second operand has 3 states, 3 states have (on average 23.666666666666668) internal successors, (71), 2 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:31:04,386 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 19:31:04,386 INFO L93 Difference]: Finished difference Result 875 states and 1292 transitions. [2022-12-13 19:31:04,386 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 875 states and 1292 transitions. [2022-12-13 19:31:04,392 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 798 [2022-12-13 19:31:04,396 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 875 states to 875 states and 1292 transitions. [2022-12-13 19:31:04,396 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 875 [2022-12-13 19:31:04,397 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 875 [2022-12-13 19:31:04,397 INFO L73 IsDeterministic]: Start isDeterministic. Operand 875 states and 1292 transitions. [2022-12-13 19:31:04,398 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 19:31:04,398 INFO L218 hiAutomatonCegarLoop]: Abstraction has 875 states and 1292 transitions. [2022-12-13 19:31:04,399 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 875 states and 1292 transitions. [2022-12-13 19:31:04,411 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 875 to 875. [2022-12-13 19:31:04,413 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 875 states, 875 states have (on average 1.4765714285714286) internal successors, (1292), 874 states have internal predecessors, (1292), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:31:04,416 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 875 states to 875 states and 1292 transitions. [2022-12-13 19:31:04,416 INFO L240 hiAutomatonCegarLoop]: Abstraction has 875 states and 1292 transitions. [2022-12-13 19:31:04,416 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 19:31:04,417 INFO L428 stractBuchiCegarLoop]: Abstraction has 875 states and 1292 transitions. [2022-12-13 19:31:04,417 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2022-12-13 19:31:04,417 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 875 states and 1292 transitions. [2022-12-13 19:31:04,421 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 798 [2022-12-13 19:31:04,421 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 19:31:04,422 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 19:31:04,423 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:31:04,423 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:31:04,423 INFO L748 eck$LassoCheckResult]: Stem: 6681#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 6682#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 6787#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 6788#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6805#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 6806#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 6617#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 6618#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 6898#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 6899#L421-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 6863#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 6589#L586 assume !(0 == ~M_E~0); 6590#L586-2 assume !(0 == ~T1_E~0); 6640#L591-1 assume !(0 == ~T2_E~0); 6752#L596-1 assume !(0 == ~T3_E~0); 6753#L601-1 assume !(0 == ~T4_E~0); 6793#L606-1 assume !(0 == ~T5_E~0); 6794#L611-1 assume !(0 == ~E_1~0); 6871#L616-1 assume !(0 == ~E_2~0); 6872#L621-1 assume 0 == ~E_3~0;~E_3~0 := 1; 6513#L626-1 assume !(0 == ~E_4~0); 6514#L631-1 assume !(0 == ~E_5~0); 6676#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6508#L279 assume !(1 == ~m_pc~0); 6510#L279-2 is_master_triggered_~__retres1~0#1 := 0; 6817#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6654#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 6655#L720 assume !(0 != activate_threads_~tmp~1#1); 6816#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6683#L298 assume !(1 == ~t1_pc~0); 6458#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 6459#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6484#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 6485#L728 assume !(0 != activate_threads_~tmp___0~0#1); 6520#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6646#L317 assume 1 == ~t2_pc~0; 6647#L318 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 6785#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6792#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 6693#L736 assume !(0 != activate_threads_~tmp___1~0#1); 6694#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6860#L336 assume 1 == ~t3_pc~0; 6729#L337 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 6730#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6431#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 6432#L744 assume !(0 != activate_threads_~tmp___2~0#1); 6825#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6868#L355 assume !(1 == ~t4_pc~0); 6751#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 6606#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6551#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 6552#L752 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 6534#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6535#L374 assume 1 == ~t5_pc~0; 6890#L375 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 6670#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6660#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 6661#L760 assume !(0 != activate_threads_~tmp___4~0#1); 6776#L760-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6777#L649 assume !(1 == ~M_E~0); 6912#L649-2 assume !(1 == ~T1_E~0); 6496#L654-1 assume !(1 == ~T2_E~0); 6497#L659-1 assume !(1 == ~T3_E~0); 6691#L664-1 assume !(1 == ~T4_E~0); 6488#L669-1 assume !(1 == ~T5_E~0); 6489#L674-1 assume !(1 == ~E_1~0); 6851#L679-1 assume !(1 == ~E_2~0); 6591#L684-1 assume 1 == ~E_3~0;~E_3~0 := 2; 6592#L689-1 assume !(1 == ~E_4~0); 6746#L694-1 assume !(1 == ~E_5~0); 6743#L699-1 assume { :end_inline_reset_delta_events } true; 6744#L900-2 [2022-12-13 19:31:04,424 INFO L750 eck$LassoCheckResult]: Loop: 6744#L900-2 assume !false; 6918#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 6439#L561 assume !false; 6529#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 6711#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 6460#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 6461#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 6580#L486 assume !(0 != eval_~tmp~0#1); 6558#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 6559#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 6884#L586-3 assume !(0 == ~M_E~0); 6850#L586-5 assume !(0 == ~T1_E~0); 6759#L591-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 6608#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 6609#L601-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 6774#L606-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 6808#L611-3 assume 0 == ~E_1~0;~E_1~0 := 1; 6809#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 6502#L621-3 assume 0 == ~E_3~0;~E_3~0 := 1; 6456#L626-3 assume !(0 == ~E_4~0); 6457#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 6462#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6463#L279-18 assume !(1 == ~m_pc~0); 6567#L279-20 is_master_triggered_~__retres1~0#1 := 0; 6700#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6696#is_master_triggered_returnLabel#7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 6697#L720-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 6873#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6775#L298-18 assume 1 == ~t1_pc~0; 6436#L299-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 6430#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6616#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 6636#L728-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 6637#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6754#L317-18 assume 1 == ~t2_pc~0; 6666#L318-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 6668#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6783#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 6619#L736-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 6620#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6876#L336-18 assume 1 == ~t3_pc~0; 6855#L337-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 6856#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6810#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 6719#L744-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 6560#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6561#L355-18 assume 1 == ~t4_pc~0; 6835#L356-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 6824#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6723#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 6724#L752-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 6656#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6657#L374-18 assume 1 == ~t5_pc~0; 6866#L375-6 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 6716#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6658#is_transmit5_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 6659#L760-18 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 6818#L760-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6819#L649-3 assume !(1 == ~M_E~0); 6728#L649-5 assume !(1 == ~T1_E~0); 6710#L654-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 6569#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 6570#L664-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 6464#L669-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 6465#L674-3 assume 1 == ~E_1~0;~E_1~0 := 2; 6454#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 6455#L684-3 assume 1 == ~E_3~0;~E_3~0 := 2; 6414#L689-3 assume !(1 == ~E_4~0); 6415#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 6449#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 6450#L439-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 6452#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 6758#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 6741#L919 assume !(0 == start_simulation_~tmp~3#1); 6467#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 6841#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 6443#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 6985#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 6736#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 6737#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 6877#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 6953#L932 assume !(0 != start_simulation_~tmp___0~1#1); 6744#L900-2 [2022-12-13 19:31:04,424 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:31:04,424 INFO L85 PathProgramCache]: Analyzing trace with hash -484678139, now seen corresponding path program 1 times [2022-12-13 19:31:04,424 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:31:04,424 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1630318953] [2022-12-13 19:31:04,425 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:31:04,425 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:31:04,436 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:31:04,481 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:31:04,481 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:31:04,481 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1630318953] [2022-12-13 19:31:04,481 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1630318953] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:31:04,481 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:31:04,481 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:31:04,481 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1089432590] [2022-12-13 19:31:04,482 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:31:04,482 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 19:31:04,482 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:31:04,482 INFO L85 PathProgramCache]: Analyzing trace with hash 855131594, now seen corresponding path program 1 times [2022-12-13 19:31:04,482 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:31:04,482 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1891647012] [2022-12-13 19:31:04,483 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:31:04,483 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:31:04,492 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:31:04,520 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:31:04,520 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:31:04,520 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1891647012] [2022-12-13 19:31:04,520 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1891647012] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:31:04,520 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:31:04,520 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:31:04,521 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [277757345] [2022-12-13 19:31:04,521 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:31:04,521 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 19:31:04,521 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 19:31:04,521 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 19:31:04,522 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 19:31:04,522 INFO L87 Difference]: Start difference. First operand 875 states and 1292 transitions. cyclomatic complexity: 418 Second operand has 4 states, 4 states have (on average 17.75) internal successors, (71), 3 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:31:04,623 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 19:31:04,623 INFO L93 Difference]: Finished difference Result 1596 states and 2357 transitions. [2022-12-13 19:31:04,623 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1596 states and 2357 transitions. [2022-12-13 19:31:04,632 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1508 [2022-12-13 19:31:04,640 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1596 states to 1596 states and 2357 transitions. [2022-12-13 19:31:04,640 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1596 [2022-12-13 19:31:04,641 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1596 [2022-12-13 19:31:04,641 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1596 states and 2357 transitions. [2022-12-13 19:31:04,643 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 19:31:04,644 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1596 states and 2357 transitions. [2022-12-13 19:31:04,645 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1596 states and 2357 transitions. [2022-12-13 19:31:04,671 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1596 to 1594. [2022-12-13 19:31:04,673 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1594 states, 1594 states have (on average 1.4774153074027603) internal successors, (2355), 1593 states have internal predecessors, (2355), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:31:04,678 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1594 states to 1594 states and 2355 transitions. [2022-12-13 19:31:04,679 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1594 states and 2355 transitions. [2022-12-13 19:31:04,679 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 19:31:04,680 INFO L428 stractBuchiCegarLoop]: Abstraction has 1594 states and 2355 transitions. [2022-12-13 19:31:04,680 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2022-12-13 19:31:04,680 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1594 states and 2355 transitions. [2022-12-13 19:31:04,687 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1508 [2022-12-13 19:31:04,687 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 19:31:04,687 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 19:31:04,688 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:31:04,688 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:31:04,689 INFO L748 eck$LassoCheckResult]: Stem: 9174#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 9175#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 9296#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 9297#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 9316#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 9317#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 9104#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 9105#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 9426#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 9427#L421-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 9388#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 9073#L586 assume !(0 == ~M_E~0); 9074#L586-2 assume !(0 == ~T1_E~0); 9129#L591-1 assume !(0 == ~T2_E~0); 9256#L596-1 assume !(0 == ~T3_E~0); 9257#L601-1 assume !(0 == ~T4_E~0); 9302#L606-1 assume !(0 == ~T5_E~0); 9303#L611-1 assume !(0 == ~E_1~0); 9399#L616-1 assume !(0 == ~E_2~0); 9400#L621-1 assume !(0 == ~E_3~0); 8995#L626-1 assume !(0 == ~E_4~0); 8996#L631-1 assume !(0 == ~E_5~0); 9167#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8990#L279 assume !(1 == ~m_pc~0); 8992#L279-2 is_master_triggered_~__retres1~0#1 := 0; 9331#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9144#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 9145#L720 assume !(0 != activate_threads_~tmp~1#1); 9330#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9176#L298 assume !(1 == ~t1_pc~0); 8941#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 8942#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8967#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 8968#L728 assume !(0 != activate_threads_~tmp___0~0#1); 9002#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9136#L317 assume 1 == ~t2_pc~0; 9137#L318 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 9295#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9301#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 9187#L736 assume !(0 != activate_threads_~tmp___1~0#1); 9188#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9383#L336 assume 1 == ~t3_pc~0; 9229#L337 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 9230#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8912#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 8913#L744 assume !(0 != activate_threads_~tmp___2~0#1); 9340#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9393#L355 assume !(1 == ~t4_pc~0); 9255#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 9093#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9035#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 9036#L752 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 9017#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9018#L374 assume 1 == ~t5_pc~0; 9419#L375 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 9161#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9150#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 9151#L760 assume !(0 != activate_threads_~tmp___4~0#1); 9284#L760-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9285#L649 assume !(1 == ~M_E~0); 9449#L649-2 assume !(1 == ~T1_E~0); 8977#L654-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 8978#L659-1 assume !(1 == ~T3_E~0); 9185#L664-1 assume !(1 == ~T4_E~0); 8969#L669-1 assume !(1 == ~T5_E~0); 8970#L674-1 assume !(1 == ~E_1~0); 9371#L679-1 assume !(1 == ~E_2~0); 9075#L684-1 assume 1 == ~E_3~0;~E_3~0 := 2; 9076#L689-1 assume !(1 == ~E_4~0); 9249#L694-1 assume !(1 == ~E_5~0); 9246#L699-1 assume { :end_inline_reset_delta_events } true; 9247#L900-2 [2022-12-13 19:31:04,689 INFO L750 eck$LassoCheckResult]: Loop: 9247#L900-2 assume !false; 9602#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 9600#L561 assume !false; 9599#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 9512#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 9505#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 9500#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 9501#L486 assume !(0 != eval_~tmp~0#1); 10231#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 10230#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 10229#L586-3 assume !(0 == ~M_E~0); 10228#L586-5 assume !(0 == ~T1_E~0); 10227#L591-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 10226#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 9279#L601-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 9280#L606-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 9321#L611-3 assume 0 == ~E_1~0;~E_1~0 := 1; 9322#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 8984#L621-3 assume !(0 == ~E_3~0); 8937#L626-3 assume !(0 == ~E_4~0); 8938#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 8943#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8944#L279-18 assume !(1 == ~m_pc~0); 9051#L279-20 is_master_triggered_~__retres1~0#1 := 0; 9197#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9190#is_master_triggered_returnLabel#7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 9191#L720-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 9401#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9283#L298-18 assume 1 == ~t1_pc~0; 8917#L299-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 8911#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9103#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 9125#L728-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 9126#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9258#L317-18 assume 1 == ~t2_pc~0; 9157#L318-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 9159#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9291#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 9106#L736-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 9107#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9404#L336-18 assume 1 == ~t3_pc~0; 9376#L337-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 9377#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9323#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 9217#L744-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 9044#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9045#L355-18 assume 1 == ~t4_pc~0; 9351#L356-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 9339#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9221#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 9222#L752-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 9146#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9147#L374-18 assume !(1 == ~t5_pc~0); 9353#L374-20 is_transmit5_triggered_~__retres1~5#1 := 0; 9211#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9212#is_transmit5_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 10069#L760-18 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 9332#L760-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9333#L649-3 assume !(1 == ~M_E~0); 9459#L649-5 assume !(1 == ~T1_E~0); 9778#L654-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 9777#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 9776#L664-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 9775#L669-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 9774#L674-3 assume 1 == ~E_1~0;~E_1~0 := 2; 9772#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 9770#L684-3 assume 1 == ~E_3~0;~E_3~0 := 2; 9768#L689-3 assume !(1 == ~E_4~0); 9766#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 9763#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 9764#L439-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 10000#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 9999#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 9998#L919 assume !(0 == start_simulation_~tmp~3#1); 9747#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 9641#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 9635#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 9634#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 9630#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 9628#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 9626#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 9612#L932 assume !(0 != start_simulation_~tmp___0~1#1); 9247#L900-2 [2022-12-13 19:31:04,689 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:31:04,689 INFO L85 PathProgramCache]: Analyzing trace with hash 1446688901, now seen corresponding path program 1 times [2022-12-13 19:31:04,689 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:31:04,690 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1816420307] [2022-12-13 19:31:04,690 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:31:04,690 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:31:04,699 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:31:04,739 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:31:04,739 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:31:04,739 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1816420307] [2022-12-13 19:31:04,739 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1816420307] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:31:04,739 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:31:04,739 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:31:04,739 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [186771624] [2022-12-13 19:31:04,740 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:31:04,740 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 19:31:04,740 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:31:04,740 INFO L85 PathProgramCache]: Analyzing trace with hash 743594471, now seen corresponding path program 1 times [2022-12-13 19:31:04,740 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:31:04,741 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [347520943] [2022-12-13 19:31:04,741 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:31:04,741 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:31:04,750 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:31:04,778 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:31:04,778 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:31:04,778 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [347520943] [2022-12-13 19:31:04,778 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [347520943] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:31:04,778 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:31:04,778 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:31:04,778 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [116135127] [2022-12-13 19:31:04,778 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:31:04,779 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 19:31:04,779 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 19:31:04,779 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 19:31:04,779 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 19:31:04,779 INFO L87 Difference]: Start difference. First operand 1594 states and 2355 transitions. cyclomatic complexity: 763 Second operand has 4 states, 4 states have (on average 17.75) internal successors, (71), 3 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:31:04,913 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 19:31:04,913 INFO L93 Difference]: Finished difference Result 4404 states and 6412 transitions. [2022-12-13 19:31:04,913 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4404 states and 6412 transitions. [2022-12-13 19:31:04,938 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4116 [2022-12-13 19:31:04,953 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4404 states to 4404 states and 6412 transitions. [2022-12-13 19:31:04,953 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4404 [2022-12-13 19:31:04,955 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4404 [2022-12-13 19:31:04,956 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4404 states and 6412 transitions. [2022-12-13 19:31:04,959 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 19:31:04,959 INFO L218 hiAutomatonCegarLoop]: Abstraction has 4404 states and 6412 transitions. [2022-12-13 19:31:04,962 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4404 states and 6412 transitions. [2022-12-13 19:31:04,999 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4404 to 4162. [2022-12-13 19:31:05,021 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4162 states, 4162 states have (on average 1.4632388274867851) internal successors, (6090), 4161 states have internal predecessors, (6090), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:31:05,029 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4162 states to 4162 states and 6090 transitions. [2022-12-13 19:31:05,029 INFO L240 hiAutomatonCegarLoop]: Abstraction has 4162 states and 6090 transitions. [2022-12-13 19:31:05,029 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 19:31:05,030 INFO L428 stractBuchiCegarLoop]: Abstraction has 4162 states and 6090 transitions. [2022-12-13 19:31:05,030 INFO L335 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2022-12-13 19:31:05,030 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4162 states and 6090 transitions. [2022-12-13 19:31:05,041 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4058 [2022-12-13 19:31:05,041 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 19:31:05,041 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 19:31:05,042 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:31:05,042 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:31:05,042 INFO L748 eck$LassoCheckResult]: Stem: 15176#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 15177#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 15292#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 15293#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 15310#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 15311#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 15111#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 15112#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 15420#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 15421#L421-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 15383#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 15078#L586 assume !(0 == ~M_E~0); 15079#L586-2 assume !(0 == ~T1_E~0); 15136#L591-1 assume !(0 == ~T2_E~0); 15253#L596-1 assume !(0 == ~T3_E~0); 15254#L601-1 assume !(0 == ~T4_E~0); 15298#L606-1 assume !(0 == ~T5_E~0); 15299#L611-1 assume !(0 == ~E_1~0); 15393#L616-1 assume !(0 == ~E_2~0); 15394#L621-1 assume !(0 == ~E_3~0); 15004#L626-1 assume !(0 == ~E_4~0); 15005#L631-1 assume !(0 == ~E_5~0); 15171#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 15000#L279 assume !(1 == ~m_pc~0); 15001#L279-2 is_master_triggered_~__retres1~0#1 := 0; 15325#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 15149#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 15150#L720 assume !(0 != activate_threads_~tmp~1#1); 15324#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 15178#L298 assume !(1 == ~t1_pc~0); 14947#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 14948#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14974#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 14975#L728 assume !(0 != activate_threads_~tmp___0~0#1); 15011#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15142#L317 assume !(1 == ~t2_pc~0); 15143#L317-2 is_transmit2_triggered_~__retres1~2#1 := 0; 15345#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 15297#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 15187#L736 assume !(0 != activate_threads_~tmp___1~0#1); 15188#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 15380#L336 assume 1 == ~t3_pc~0; 15227#L337 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 15228#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14920#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 14921#L744 assume !(0 != activate_threads_~tmp___2~0#1); 15333#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 15388#L355 assume !(1 == ~t4_pc~0); 15250#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 15098#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 15043#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 15044#L752 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 15022#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 15023#L374 assume 1 == ~t5_pc~0; 15412#L375 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 15162#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 15155#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 15156#L760 assume !(0 != activate_threads_~tmp___4~0#1); 15282#L760-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 15283#L649 assume !(1 == ~M_E~0); 15438#L649-2 assume !(1 == ~T1_E~0); 14987#L654-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 14988#L659-1 assume !(1 == ~T3_E~0); 15186#L664-1 assume !(1 == ~T4_E~0); 14979#L669-1 assume !(1 == ~T5_E~0); 14980#L674-1 assume !(1 == ~E_1~0); 15371#L679-1 assume !(1 == ~E_2~0); 15083#L684-1 assume 1 == ~E_3~0;~E_3~0 := 2; 15084#L689-1 assume !(1 == ~E_4~0); 17708#L694-1 assume !(1 == ~E_5~0); 15243#L699-1 assume { :end_inline_reset_delta_events } true; 15244#L900-2 [2022-12-13 19:31:05,042 INFO L750 eck$LassoCheckResult]: Loop: 15244#L900-2 assume !false; 18365#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 18352#L561 assume !false; 18347#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 18295#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 18285#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 18284#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 18278#L486 assume !(0 != eval_~tmp~0#1); 15050#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 15051#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 15408#L586-3 assume !(0 == ~M_E~0); 15370#L586-5 assume !(0 == ~T1_E~0); 15263#L591-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 15102#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 15103#L601-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 15278#L606-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 15313#L611-3 assume 0 == ~E_1~0;~E_1~0 := 1; 15314#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 14994#L621-3 assume !(0 == ~E_3~0); 14945#L626-3 assume !(0 == ~E_4~0); 14946#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 14951#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 14952#L279-18 assume !(1 == ~m_pc~0); 15198#L279-20 is_master_triggered_~__retres1~0#1 := 0; 15199#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 15191#is_master_triggered_returnLabel#7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 15192#L720-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 15395#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 15281#L298-18 assume !(1 == ~t1_pc~0); 14918#L298-20 is_transmit1_triggered_~__retres1~1#1 := 0; 14919#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 15110#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 15131#L728-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 15132#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15255#L317-18 assume !(1 == ~t2_pc~0); 15256#L317-20 is_transmit2_triggered_~__retres1~2#1 := 0; 15277#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 15289#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 15113#L736-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 15114#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 15398#L336-18 assume 1 == ~t3_pc~0; 15376#L337-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 15377#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 15316#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 15215#L744-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 15052#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 15053#L355-18 assume !(1 == ~t4_pc~0); 15331#L355-20 is_transmit4_triggered_~__retres1~4#1 := 0; 15332#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 15219#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 15220#L752-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 15151#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 15152#L374-18 assume !(1 == ~t5_pc~0); 15349#L374-20 is_transmit5_triggered_~__retres1~5#1 := 0; 15212#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 15153#is_transmit5_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 15154#L760-18 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 15326#L760-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 15327#L649-3 assume !(1 == ~M_E~0); 15448#L649-5 assume !(1 == ~T1_E~0); 18653#L654-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 17505#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 18641#L664-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 18639#L669-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 18637#L674-3 assume 1 == ~E_1~0;~E_1~0 := 2; 18635#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 18611#L684-3 assume 1 == ~E_3~0;~E_3~0 := 2; 17491#L689-3 assume !(1 == ~E_4~0); 18610#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 18609#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 18608#L439-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 18602#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 18601#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 18600#L919 assume !(0 == start_simulation_~tmp~3#1); 18598#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 18571#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 18563#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 18557#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 18554#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 18550#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 18546#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 18544#L932 assume !(0 != start_simulation_~tmp___0~1#1); 15244#L900-2 [2022-12-13 19:31:05,043 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:31:05,043 INFO L85 PathProgramCache]: Analyzing trace with hash -318127708, now seen corresponding path program 1 times [2022-12-13 19:31:05,043 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:31:05,043 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [930025240] [2022-12-13 19:31:05,043 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:31:05,043 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:31:05,051 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:31:05,078 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:31:05,078 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:31:05,078 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [930025240] [2022-12-13 19:31:05,078 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [930025240] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:31:05,078 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:31:05,078 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:31:05,079 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [675765790] [2022-12-13 19:31:05,079 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:31:05,079 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 19:31:05,079 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:31:05,079 INFO L85 PathProgramCache]: Analyzing trace with hash 514413828, now seen corresponding path program 1 times [2022-12-13 19:31:05,079 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:31:05,080 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [779452933] [2022-12-13 19:31:05,080 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:31:05,080 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:31:05,086 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:31:05,114 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:31:05,114 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:31:05,114 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [779452933] [2022-12-13 19:31:05,114 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [779452933] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:31:05,114 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:31:05,114 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-12-13 19:31:05,114 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1989791264] [2022-12-13 19:31:05,114 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:31:05,115 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 19:31:05,115 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 19:31:05,115 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 19:31:05,115 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 19:31:05,115 INFO L87 Difference]: Start difference. First operand 4162 states and 6090 transitions. cyclomatic complexity: 1932 Second operand has 4 states, 4 states have (on average 17.75) internal successors, (71), 3 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:31:05,306 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 19:31:05,307 INFO L93 Difference]: Finished difference Result 11351 states and 16460 transitions. [2022-12-13 19:31:05,307 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 11351 states and 16460 transitions. [2022-12-13 19:31:05,366 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 10788 [2022-12-13 19:31:05,427 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 11351 states to 11351 states and 16460 transitions. [2022-12-13 19:31:05,427 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 11351 [2022-12-13 19:31:05,433 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11351 [2022-12-13 19:31:05,433 INFO L73 IsDeterministic]: Start isDeterministic. Operand 11351 states and 16460 transitions. [2022-12-13 19:31:05,442 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 19:31:05,442 INFO L218 hiAutomatonCegarLoop]: Abstraction has 11351 states and 16460 transitions. [2022-12-13 19:31:05,449 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11351 states and 16460 transitions. [2022-12-13 19:31:05,544 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11351 to 10667. [2022-12-13 19:31:05,556 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 10667 states, 10667 states have (on average 1.4594543920502485) internal successors, (15568), 10666 states have internal predecessors, (15568), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:31:05,573 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10667 states to 10667 states and 15568 transitions. [2022-12-13 19:31:05,573 INFO L240 hiAutomatonCegarLoop]: Abstraction has 10667 states and 15568 transitions. [2022-12-13 19:31:05,573 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 19:31:05,574 INFO L428 stractBuchiCegarLoop]: Abstraction has 10667 states and 15568 transitions. [2022-12-13 19:31:05,574 INFO L335 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2022-12-13 19:31:05,574 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 10667 states and 15568 transitions. [2022-12-13 19:31:05,621 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 10524 [2022-12-13 19:31:05,621 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 19:31:05,621 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 19:31:05,622 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:31:05,622 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:31:05,622 INFO L748 eck$LassoCheckResult]: Stem: 30706#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 30707#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 30828#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 30829#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 30847#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 30848#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 30635#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 30636#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 30987#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 30988#L421-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 30934#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 30601#L586 assume !(0 == ~M_E~0); 30602#L586-2 assume !(0 == ~T1_E~0); 30661#L591-1 assume !(0 == ~T2_E~0); 30788#L596-1 assume !(0 == ~T3_E~0); 30789#L601-1 assume !(0 == ~T4_E~0); 30834#L606-1 assume !(0 == ~T5_E~0); 30835#L611-1 assume !(0 == ~E_1~0); 30950#L616-1 assume !(0 == ~E_2~0); 30951#L621-1 assume !(0 == ~E_3~0); 30527#L626-1 assume !(0 == ~E_4~0); 30528#L631-1 assume !(0 == ~E_5~0); 30699#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 30523#L279 assume !(1 == ~m_pc~0); 30524#L279-2 is_master_triggered_~__retres1~0#1 := 0; 30865#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 30674#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 30675#L720 assume !(0 != activate_threads_~tmp~1#1); 30864#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 30708#L298 assume !(1 == ~t1_pc~0); 30471#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 30472#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 30497#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 30498#L728 assume !(0 != activate_threads_~tmp___0~0#1); 30534#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 30667#L317 assume !(1 == ~t2_pc~0); 30668#L317-2 is_transmit2_triggered_~__retres1~2#1 := 0; 30888#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 30833#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 30718#L736 assume !(0 != activate_threads_~tmp___1~0#1); 30719#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 30928#L336 assume !(1 == ~t3_pc~0); 30929#L336-2 is_transmit3_triggered_~__retres1~3#1 := 0; 31025#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 30445#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 30446#L744 assume !(0 != activate_threads_~tmp___2~0#1); 30874#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 30942#L355 assume !(1 == ~t4_pc~0); 30785#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 30622#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 30567#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 30568#L752 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 30547#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 30548#L374 assume 1 == ~t5_pc~0; 30976#L375 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 30688#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 30680#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 30681#L760 assume !(0 != activate_threads_~tmp___4~0#1); 30816#L760-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 30817#L649 assume !(1 == ~M_E~0); 31013#L649-2 assume !(1 == ~T1_E~0); 30510#L654-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 30511#L659-1 assume !(1 == ~T3_E~0); 30716#L664-1 assume !(1 == ~T4_E~0); 30717#L669-1 assume !(1 == ~T5_E~0); 30918#L674-1 assume !(1 == ~E_1~0); 30919#L679-1 assume !(1 == ~E_2~0); 30606#L684-1 assume 1 == ~E_3~0;~E_3~0 := 2; 30607#L689-1 assume !(1 == ~E_4~0); 31049#L694-1 assume !(1 == ~E_5~0); 31050#L699-1 assume { :end_inline_reset_delta_events } true; 39301#L900-2 [2022-12-13 19:31:05,622 INFO L750 eck$LassoCheckResult]: Loop: 39301#L900-2 assume !false; 38795#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 38164#L561 assume !false; 38162#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 37537#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 37532#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 37530#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 37527#L486 assume !(0 != eval_~tmp~0#1); 37528#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 40263#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 40262#L586-3 assume !(0 == ~M_E~0); 40261#L586-5 assume !(0 == ~T1_E~0); 40260#L591-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 40259#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 40258#L601-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 40257#L606-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 40256#L611-3 assume 0 == ~E_1~0;~E_1~0 := 1; 40255#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 40254#L621-3 assume !(0 == ~E_3~0); 40253#L626-3 assume !(0 == ~E_4~0); 40252#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 40251#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 40250#L279-18 assume !(1 == ~m_pc~0); 40249#L279-20 is_master_triggered_~__retres1~0#1 := 0; 40248#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 40247#is_master_triggered_returnLabel#7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 40246#L720-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 40245#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 40244#L298-18 assume 1 == ~t1_pc~0; 40242#L299-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 40241#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 40240#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 40239#L728-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 40238#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 30790#L317-18 assume !(1 == ~t2_pc~0); 30791#L317-20 is_transmit2_triggered_~__retres1~2#1 := 0; 30811#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 40236#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 40235#L736-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 30958#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 30955#L336-18 assume !(1 == ~t3_pc~0); 30956#L336-20 is_transmit3_triggered_~__retres1~3#1 := 0; 30992#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 30856#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 30749#L744-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 30576#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 30577#L355-18 assume !(1 == ~t4_pc~0); 30870#L355-20 is_transmit4_triggered_~__retres1~4#1 := 0; 30871#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 30754#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 30755#L752-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 30676#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 30677#L374-18 assume 1 == ~t5_pc~0; 30941#L375-6 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 30743#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 30678#is_transmit5_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 30679#L760-18 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 30866#L760-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 30867#L649-3 assume !(1 == ~M_E~0); 31028#L649-5 assume !(1 == ~T1_E~0); 39694#L654-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 39647#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 39691#L664-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 39682#L669-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 39678#L674-3 assume 1 == ~E_1~0;~E_1~0 := 2; 39662#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 39407#L684-3 assume 1 == ~E_3~0;~E_3~0 := 2; 39401#L689-3 assume !(1 == ~E_4~0); 39397#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 39393#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 39387#L439-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 39380#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 39378#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 39367#L919 assume !(0 == start_simulation_~tmp~3#1); 39360#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 39342#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 39331#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 39329#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 39327#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 39322#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 39316#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 39308#L932 assume !(0 != start_simulation_~tmp___0~1#1); 39301#L900-2 [2022-12-13 19:31:05,622 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:31:05,622 INFO L85 PathProgramCache]: Analyzing trace with hash -375271933, now seen corresponding path program 1 times [2022-12-13 19:31:05,623 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:31:05,623 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [133988173] [2022-12-13 19:31:05,623 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:31:05,623 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:31:05,631 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:31:05,681 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:31:05,681 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:31:05,682 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [133988173] [2022-12-13 19:31:05,682 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [133988173] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:31:05,682 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:31:05,682 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-12-13 19:31:05,682 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [901192034] [2022-12-13 19:31:05,682 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:31:05,682 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 19:31:05,683 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:31:05,683 INFO L85 PathProgramCache]: Analyzing trace with hash -1686757595, now seen corresponding path program 1 times [2022-12-13 19:31:05,683 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:31:05,683 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [398507031] [2022-12-13 19:31:05,683 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:31:05,683 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:31:05,692 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:31:05,750 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:31:05,750 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:31:05,750 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [398507031] [2022-12-13 19:31:05,750 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [398507031] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:31:05,751 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:31:05,751 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-12-13 19:31:05,751 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [830838402] [2022-12-13 19:31:05,751 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:31:05,751 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 19:31:05,751 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 19:31:05,751 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-12-13 19:31:05,752 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-12-13 19:31:05,752 INFO L87 Difference]: Start difference. First operand 10667 states and 15568 transitions. cyclomatic complexity: 4909 Second operand has 5 states, 5 states have (on average 14.2) internal successors, (71), 5 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:31:05,987 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 19:31:05,987 INFO L93 Difference]: Finished difference Result 26236 states and 38605 transitions. [2022-12-13 19:31:05,988 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 26236 states and 38605 transitions. [2022-12-13 19:31:06,071 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 25924 [2022-12-13 19:31:06,169 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 26236 states to 26236 states and 38605 transitions. [2022-12-13 19:31:06,169 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 26236 [2022-12-13 19:31:06,182 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 26236 [2022-12-13 19:31:06,182 INFO L73 IsDeterministic]: Start isDeterministic. Operand 26236 states and 38605 transitions. [2022-12-13 19:31:06,202 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 19:31:06,203 INFO L218 hiAutomatonCegarLoop]: Abstraction has 26236 states and 38605 transitions. [2022-12-13 19:31:06,219 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 26236 states and 38605 transitions. [2022-12-13 19:31:06,392 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 26236 to 11150. [2022-12-13 19:31:06,405 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 11150 states, 11150 states have (on average 1.4395515695067265) internal successors, (16051), 11149 states have internal predecessors, (16051), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:31:06,426 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11150 states to 11150 states and 16051 transitions. [2022-12-13 19:31:06,426 INFO L240 hiAutomatonCegarLoop]: Abstraction has 11150 states and 16051 transitions. [2022-12-13 19:31:06,427 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-12-13 19:31:06,427 INFO L428 stractBuchiCegarLoop]: Abstraction has 11150 states and 16051 transitions. [2022-12-13 19:31:06,427 INFO L335 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2022-12-13 19:31:06,427 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 11150 states and 16051 transitions. [2022-12-13 19:31:06,458 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 11004 [2022-12-13 19:31:06,458 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 19:31:06,458 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 19:31:06,459 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:31:06,459 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:31:06,460 INFO L748 eck$LassoCheckResult]: Stem: 67623#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 67624#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 67744#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 67745#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 67763#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 67764#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 67557#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 67558#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 67886#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 67887#L421-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 67842#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 67524#L586 assume !(0 == ~M_E~0); 67525#L586-2 assume !(0 == ~T1_E~0); 67583#L591-1 assume !(0 == ~T2_E~0); 67707#L596-1 assume !(0 == ~T3_E~0); 67708#L601-1 assume !(0 == ~T4_E~0); 67750#L606-1 assume !(0 == ~T5_E~0); 67751#L611-1 assume !(0 == ~E_1~0); 67856#L616-1 assume !(0 == ~E_2~0); 67857#L621-1 assume !(0 == ~E_3~0); 67446#L626-1 assume !(0 == ~E_4~0); 67447#L631-1 assume !(0 == ~E_5~0); 67618#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 67442#L279 assume !(1 == ~m_pc~0); 67443#L279-2 is_master_triggered_~__retres1~0#1 := 0; 67779#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 67596#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 67597#L720 assume !(0 != activate_threads_~tmp~1#1); 67778#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 67625#L298 assume !(1 == ~t1_pc~0); 67389#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 67390#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 67415#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 67416#L728 assume !(0 != activate_threads_~tmp___0~0#1); 67454#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 67589#L317 assume !(1 == ~t2_pc~0); 67590#L317-2 is_transmit2_triggered_~__retres1~2#1 := 0; 67798#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 67749#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 67635#L736 assume !(0 != activate_threads_~tmp___1~0#1); 67636#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 67836#L336 assume !(1 == ~t3_pc~0); 67837#L336-2 is_transmit3_triggered_~__retres1~3#1 := 0; 67930#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 67363#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 67364#L744 assume !(0 != activate_threads_~tmp___2~0#1); 67787#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 67849#L355 assume !(1 == ~t4_pc~0); 67704#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 67543#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 67544#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 67822#L752 assume !(0 != activate_threads_~tmp___3~0#1); 67470#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 67471#L374 assume 1 == ~t5_pc~0; 67875#L375 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 67609#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 67602#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 67603#L760 assume !(0 != activate_threads_~tmp___4~0#1); 67733#L760-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 67734#L649 assume !(1 == ~M_E~0); 67916#L649-2 assume !(1 == ~T1_E~0); 67428#L654-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 67429#L659-1 assume !(1 == ~T3_E~0); 67633#L664-1 assume !(1 == ~T4_E~0); 67634#L669-1 assume !(1 == ~T5_E~0); 67825#L674-1 assume !(1 == ~E_1~0); 67826#L679-1 assume !(1 == ~E_2~0); 67529#L684-1 assume 1 == ~E_3~0;~E_3~0 := 2; 67530#L689-1 assume !(1 == ~E_4~0); 67699#L694-1 assume !(1 == ~E_5~0); 67697#L699-1 assume { :end_inline_reset_delta_events } true; 67698#L900-2 [2022-12-13 19:31:06,460 INFO L750 eck$LassoCheckResult]: Loop: 67698#L900-2 assume !false; 76657#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 76653#L561 assume !false; 76651#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 76609#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 76603#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 76601#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 76597#L486 assume !(0 != eval_~tmp~0#1); 76598#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 67870#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 67871#L586-3 assume !(0 == ~M_E~0); 78315#L586-5 assume !(0 == ~T1_E~0); 78083#L591-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 78081#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 78079#L601-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 78076#L606-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 78074#L611-3 assume 0 == ~E_1~0;~E_1~0 := 1; 67773#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 67435#L621-3 assume !(0 == ~E_3~0); 67387#L626-3 assume !(0 == ~E_4~0); 67388#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 67393#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 67394#L279-18 assume !(1 == ~m_pc~0); 67914#L279-20 is_master_triggered_~__retres1~0#1 := 0; 78058#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 78056#is_master_triggered_returnLabel#7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 78054#L720-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 78052#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 78050#L298-18 assume !(1 == ~t1_pc~0); 78049#L298-20 is_transmit1_triggered_~__retres1~1#1 := 0; 78046#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 78044#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 78042#L728-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 78031#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 78029#L317-18 assume !(1 == ~t2_pc~0); 78027#L317-20 is_transmit2_triggered_~__retres1~2#1 := 0; 78024#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 78022#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 78020#L736-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 78018#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 78016#L336-18 assume !(1 == ~t3_pc~0); 78014#L336-20 is_transmit3_triggered_~__retres1~3#1 := 0; 78013#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 78011#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 78009#L744-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 78008#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 67800#L355-18 assume !(1 == ~t4_pc~0); 67801#L355-20 is_transmit4_triggered_~__retres1~4#1 := 0; 78007#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 78005#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 78003#L752-18 assume !(0 != activate_threads_~tmp___3~0#1); 78000#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 77999#L374-18 assume 1 == ~t5_pc~0; 77993#L375-6 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 77989#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 67600#is_transmit5_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 67601#L760-18 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 67780#L760-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 67781#L649-3 assume !(1 == ~M_E~0); 67934#L649-5 assume !(1 == ~T1_E~0); 67655#L654-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 67508#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 67509#L664-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 67931#L669-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 77760#L674-3 assume 1 == ~E_1~0;~E_1~0 := 2; 67385#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 67386#L684-3 assume 1 == ~E_3~0;~E_3~0 := 2; 74619#L689-3 assume !(1 == ~E_4~0); 77677#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 77675#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 76891#L439-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 76884#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 76881#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 76848#L919 assume !(0 == start_simulation_~tmp~3#1); 76841#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 76836#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 76830#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 76828#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 76826#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 76824#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 76823#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 76822#L932 assume !(0 != start_simulation_~tmp___0~1#1); 67698#L900-2 [2022-12-13 19:31:06,460 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:31:06,460 INFO L85 PathProgramCache]: Analyzing trace with hash -1192920383, now seen corresponding path program 1 times [2022-12-13 19:31:06,460 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:31:06,460 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1151226472] [2022-12-13 19:31:06,460 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:31:06,461 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:31:06,468 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:31:06,496 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:31:06,496 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:31:06,496 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1151226472] [2022-12-13 19:31:06,496 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1151226472] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:31:06,497 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:31:06,497 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-12-13 19:31:06,497 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1475779532] [2022-12-13 19:31:06,497 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:31:06,497 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 19:31:06,497 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:31:06,497 INFO L85 PathProgramCache]: Analyzing trace with hash -1309196734, now seen corresponding path program 1 times [2022-12-13 19:31:06,498 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:31:06,498 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1638874904] [2022-12-13 19:31:06,498 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:31:06,498 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:31:06,506 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:31:06,553 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:31:06,554 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:31:06,554 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1638874904] [2022-12-13 19:31:06,554 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1638874904] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:31:06,554 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:31:06,554 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-12-13 19:31:06,554 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [220706640] [2022-12-13 19:31:06,554 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:31:06,555 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 19:31:06,555 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 19:31:06,555 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 19:31:06,555 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 19:31:06,555 INFO L87 Difference]: Start difference. First operand 11150 states and 16051 transitions. cyclomatic complexity: 4909 Second operand has 3 states, 3 states have (on average 23.666666666666668) internal successors, (71), 2 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:31:06,653 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 19:31:06,654 INFO L93 Difference]: Finished difference Result 22017 states and 31458 transitions. [2022-12-13 19:31:06,654 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 22017 states and 31458 transitions. [2022-12-13 19:31:06,716 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 21740 [2022-12-13 19:31:06,766 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 22017 states to 22017 states and 31458 transitions. [2022-12-13 19:31:06,766 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 22017 [2022-12-13 19:31:06,777 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 22017 [2022-12-13 19:31:06,777 INFO L73 IsDeterministic]: Start isDeterministic. Operand 22017 states and 31458 transitions. [2022-12-13 19:31:06,792 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 19:31:06,792 INFO L218 hiAutomatonCegarLoop]: Abstraction has 22017 states and 31458 transitions. [2022-12-13 19:31:06,809 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 22017 states and 31458 transitions. [2022-12-13 19:31:07,051 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 22017 to 21873. [2022-12-13 19:31:07,077 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 21873 states, 21873 states have (on average 1.4299821697983817) internal successors, (31278), 21872 states have internal predecessors, (31278), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:31:07,110 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21873 states to 21873 states and 31278 transitions. [2022-12-13 19:31:07,110 INFO L240 hiAutomatonCegarLoop]: Abstraction has 21873 states and 31278 transitions. [2022-12-13 19:31:07,110 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 19:31:07,111 INFO L428 stractBuchiCegarLoop]: Abstraction has 21873 states and 31278 transitions. [2022-12-13 19:31:07,111 INFO L335 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2022-12-13 19:31:07,111 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 21873 states and 31278 transitions. [2022-12-13 19:31:07,189 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 21668 [2022-12-13 19:31:07,189 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 19:31:07,189 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 19:31:07,190 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:31:07,190 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:31:07,190 INFO L748 eck$LassoCheckResult]: Stem: 100798#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 100799#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 100920#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 100921#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 100941#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 100942#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 100730#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 100731#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 101060#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 101061#L421-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 101019#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 100697#L586 assume !(0 == ~M_E~0); 100698#L586-2 assume !(0 == ~T1_E~0); 100755#L591-1 assume !(0 == ~T2_E~0); 100880#L596-1 assume !(0 == ~T3_E~0); 100881#L601-1 assume !(0 == ~T4_E~0); 100928#L606-1 assume !(0 == ~T5_E~0); 100929#L611-1 assume !(0 == ~E_1~0); 101031#L616-1 assume !(0 == ~E_2~0); 101032#L621-1 assume !(0 == ~E_3~0); 100620#L626-1 assume !(0 == ~E_4~0); 100621#L631-1 assume !(0 == ~E_5~0); 100793#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 100616#L279 assume !(1 == ~m_pc~0); 100617#L279-2 is_master_triggered_~__retres1~0#1 := 0; 100958#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 100769#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 100770#L720 assume !(0 != activate_threads_~tmp~1#1); 100957#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 100800#L298 assume !(1 == ~t1_pc~0); 100564#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 100565#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 100590#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 100591#L728 assume !(0 != activate_threads_~tmp___0~0#1); 100628#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 100762#L317 assume !(1 == ~t2_pc~0); 100763#L317-2 is_transmit2_triggered_~__retres1~2#1 := 0; 100981#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 100927#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 100810#L736 assume !(0 != activate_threads_~tmp___1~0#1); 100811#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 101016#L336 assume !(1 == ~t3_pc~0); 101017#L336-2 is_transmit3_triggered_~__retres1~3#1 := 0; 101096#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 100538#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 100539#L744 assume !(0 != activate_threads_~tmp___2~0#1); 100966#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 101026#L355 assume !(1 == ~t4_pc~0); 100877#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 100717#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 100663#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 100664#L752 assume !(0 != activate_threads_~tmp___3~0#1); 100645#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 100646#L374 assume !(1 == ~t5_pc~0); 100783#L374-2 is_transmit5_triggered_~__retres1~5#1 := 0; 100784#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 100777#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 100778#L760 assume !(0 != activate_threads_~tmp___4~0#1); 100909#L760-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 100910#L649 assume !(1 == ~M_E~0); 101090#L649-2 assume !(1 == ~T1_E~0); 100603#L654-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 100604#L659-1 assume !(1 == ~T3_E~0); 100809#L664-1 assume !(1 == ~T4_E~0); 100595#L669-1 assume !(1 == ~T5_E~0); 100596#L674-1 assume !(1 == ~E_1~0); 101023#L679-1 assume !(1 == ~E_2~0); 101024#L684-1 assume 1 == ~E_3~0;~E_3~0 := 2; 100704#L689-1 assume !(1 == ~E_4~0); 100871#L694-1 assume !(1 == ~E_5~0); 100869#L699-1 assume { :end_inline_reset_delta_events } true; 100870#L900-2 [2022-12-13 19:31:07,190 INFO L750 eck$LassoCheckResult]: Loop: 100870#L900-2 assume !false; 118612#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 118611#L561 assume !false; 118610#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 118608#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 118603#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 118602#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 118600#L486 assume !(0 != eval_~tmp~0#1); 118601#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 122091#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 122089#L586-3 assume !(0 == ~M_E~0); 122087#L586-5 assume !(0 == ~T1_E~0); 122073#L591-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 122072#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 122070#L601-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 122071#L606-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 122157#L611-3 assume 0 == ~E_1~0;~E_1~0 := 1; 122068#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 122067#L621-3 assume !(0 == ~E_3~0); 122066#L626-3 assume !(0 == ~E_4~0); 122065#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 100568#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 100569#L279-18 assume !(1 == ~m_pc~0); 100821#L279-20 is_master_triggered_~__retres1~0#1 := 0; 100822#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 121879#is_master_triggered_returnLabel#7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 121878#L720-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 121877#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 121876#L298-18 assume !(1 == ~t1_pc~0); 121875#L298-20 is_transmit1_triggered_~__retres1~1#1 := 0; 121873#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 121872#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 121870#L728-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 121868#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 100883#L317-18 assume !(1 == ~t2_pc~0); 100884#L317-20 is_transmit2_triggered_~__retres1~2#1 := 0; 100904#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 100917#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 100732#L736-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 100733#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 101036#L336-18 assume !(1 == ~t3_pc~0); 101037#L336-20 is_transmit3_triggered_~__retres1~3#1 := 0; 101067#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 100949#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 100838#L744-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 100673#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 100674#L355-18 assume !(1 == ~t4_pc~0); 100963#L355-20 is_transmit4_triggered_~__retres1~4#1 := 0; 100964#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 100844#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 100845#L752-18 assume !(0 != activate_threads_~tmp___3~0#1); 100771#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 100772#L374-18 assume !(1 == ~t5_pc~0); 100986#L374-20 is_transmit5_triggered_~__retres1~5#1 := 0; 100835#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 100773#is_transmit5_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 100774#L760-18 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 100959#L760-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 100960#L649-3 assume !(1 == ~M_E~0); 101098#L649-5 assume !(1 == ~T1_E~0); 122176#L654-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 108127#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 119630#L664-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 119629#L669-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 119628#L674-3 assume 1 == ~E_1~0;~E_1~0 := 2; 119627#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 119626#L684-3 assume 1 == ~E_3~0;~E_3~0 := 2; 108114#L689-3 assume !(1 == ~E_4~0); 119625#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 119624#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 118722#L439-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 118715#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 118713#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 118661#L919 assume !(0 == start_simulation_~tmp~3#1); 118659#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 118648#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 118642#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 118640#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 118638#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 118635#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 118633#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 118631#L932 assume !(0 != start_simulation_~tmp___0~1#1); 100870#L900-2 [2022-12-13 19:31:07,190 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:31:07,190 INFO L85 PathProgramCache]: Analyzing trace with hash -52568672, now seen corresponding path program 1 times [2022-12-13 19:31:07,190 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:31:07,190 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1717994389] [2022-12-13 19:31:07,191 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:31:07,191 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:31:07,197 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:31:07,227 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:31:07,227 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:31:07,227 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1717994389] [2022-12-13 19:31:07,227 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1717994389] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:31:07,227 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:31:07,227 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-12-13 19:31:07,228 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [174218157] [2022-12-13 19:31:07,228 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:31:07,228 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 19:31:07,228 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:31:07,228 INFO L85 PathProgramCache]: Analyzing trace with hash -1366340959, now seen corresponding path program 1 times [2022-12-13 19:31:07,228 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:31:07,229 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2124125573] [2022-12-13 19:31:07,229 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:31:07,229 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:31:07,235 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:31:07,265 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:31:07,266 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:31:07,266 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2124125573] [2022-12-13 19:31:07,266 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2124125573] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:31:07,266 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:31:07,266 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-12-13 19:31:07,266 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1180860663] [2022-12-13 19:31:07,266 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:31:07,267 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 19:31:07,267 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 19:31:07,267 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 19:31:07,267 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 19:31:07,268 INFO L87 Difference]: Start difference. First operand 21873 states and 31278 transitions. cyclomatic complexity: 9421 Second operand has 3 states, 3 states have (on average 23.666666666666668) internal successors, (71), 2 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:31:07,363 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 19:31:07,363 INFO L93 Difference]: Finished difference Result 21867 states and 31085 transitions. [2022-12-13 19:31:07,363 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 21867 states and 31085 transitions. [2022-12-13 19:31:07,437 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 21668 [2022-12-13 19:31:07,488 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 21867 states to 21867 states and 31085 transitions. [2022-12-13 19:31:07,488 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 21867 [2022-12-13 19:31:07,498 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 21867 [2022-12-13 19:31:07,498 INFO L73 IsDeterministic]: Start isDeterministic. Operand 21867 states and 31085 transitions. [2022-12-13 19:31:07,512 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 19:31:07,512 INFO L218 hiAutomatonCegarLoop]: Abstraction has 21867 states and 31085 transitions. [2022-12-13 19:31:07,525 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 21867 states and 31085 transitions. [2022-12-13 19:31:07,648 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 21867 to 11243. [2022-12-13 19:31:07,659 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 11243 states, 11243 states have (on average 1.4189273325624834) internal successors, (15953), 11242 states have internal predecessors, (15953), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:31:07,679 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11243 states to 11243 states and 15953 transitions. [2022-12-13 19:31:07,679 INFO L240 hiAutomatonCegarLoop]: Abstraction has 11243 states and 15953 transitions. [2022-12-13 19:31:07,679 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 19:31:07,680 INFO L428 stractBuchiCegarLoop]: Abstraction has 11243 states and 15953 transitions. [2022-12-13 19:31:07,680 INFO L335 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2022-12-13 19:31:07,680 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 11243 states and 15953 transitions. [2022-12-13 19:31:07,709 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 11107 [2022-12-13 19:31:07,709 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 19:31:07,709 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 19:31:07,710 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:31:07,710 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:31:07,710 INFO L748 eck$LassoCheckResult]: Stem: 144541#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 144542#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 144665#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 144666#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 144684#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 144685#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 144476#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 144477#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 144799#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 144800#L421-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 144765#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 144447#L586 assume !(0 == ~M_E~0); 144448#L586-2 assume !(0 == ~T1_E~0); 144502#L591-1 assume !(0 == ~T2_E~0); 144623#L596-1 assume !(0 == ~T3_E~0); 144624#L601-1 assume !(0 == ~T4_E~0); 144672#L606-1 assume !(0 == ~T5_E~0); 144673#L611-1 assume !(0 == ~E_1~0); 144773#L616-1 assume !(0 == ~E_2~0); 144774#L621-1 assume !(0 == ~E_3~0); 144367#L626-1 assume !(0 == ~E_4~0); 144368#L631-1 assume !(0 == ~E_5~0); 144536#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 144365#L279 assume !(1 == ~m_pc~0); 144366#L279-2 is_master_triggered_~__retres1~0#1 := 0; 144701#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 144515#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 144516#L720 assume !(0 != activate_threads_~tmp~1#1); 144700#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 144543#L298 assume !(1 == ~t1_pc~0); 144315#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 144316#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 144341#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 144342#L728 assume !(0 != activate_threads_~tmp___0~0#1); 144374#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 144508#L317 assume !(1 == ~t2_pc~0); 144509#L317-2 is_transmit2_triggered_~__retres1~2#1 := 0; 144722#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 144671#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 144553#L736 assume !(0 != activate_threads_~tmp___1~0#1); 144554#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 144759#L336 assume !(1 == ~t3_pc~0); 144760#L336-2 is_transmit3_triggered_~__retres1~3#1 := 0; 144837#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 144287#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 144288#L744 assume !(0 != activate_threads_~tmp___2~0#1); 144709#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 144769#L355 assume !(1 == ~t4_pc~0); 144622#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 144766#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 144408#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 144409#L752 assume !(0 != activate_threads_~tmp___3~0#1); 144390#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 144391#L374 assume !(1 == ~t5_pc~0); 144529#L374-2 is_transmit5_triggered_~__retres1~5#1 := 0; 144530#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 144521#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 144522#L760 assume !(0 != activate_threads_~tmp___4~0#1); 144652#L760-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 144653#L649 assume !(1 == ~M_E~0); 144828#L649-2 assume !(1 == ~T1_E~0); 144351#L654-1 assume !(1 == ~T2_E~0); 144352#L659-1 assume !(1 == ~T3_E~0); 144551#L664-1 assume !(1 == ~T4_E~0); 144343#L669-1 assume !(1 == ~T5_E~0); 144344#L674-1 assume !(1 == ~E_1~0); 144748#L679-1 assume !(1 == ~E_2~0); 144449#L684-1 assume 1 == ~E_3~0;~E_3~0 := 2; 144450#L689-1 assume !(1 == ~E_4~0); 144617#L694-1 assume !(1 == ~E_5~0); 144614#L699-1 assume { :end_inline_reset_delta_events } true; 144615#L900-2 [2022-12-13 19:31:07,710 INFO L750 eck$LassoCheckResult]: Loop: 144615#L900-2 assume !false; 152316#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 152147#L561 assume !false; 152313#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 152308#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 152302#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 152300#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 152298#L486 assume !(0 != eval_~tmp~0#1); 144415#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 144416#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 144787#L586-3 assume !(0 == ~M_E~0); 144746#L586-5 assume !(0 == ~T1_E~0); 144747#L591-3 assume !(0 == ~T2_E~0); 155305#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 155304#L601-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 155303#L606-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 155302#L611-3 assume 0 == ~E_1~0;~E_1~0 := 1; 155301#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 155300#L621-3 assume !(0 == ~E_3~0); 155298#L626-3 assume !(0 == ~E_4~0); 155296#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 155294#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 155292#L279-18 assume !(1 == ~m_pc~0); 155290#L279-20 is_master_triggered_~__retres1~0#1 := 0; 155288#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 155286#is_master_triggered_returnLabel#7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 155283#L720-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 155281#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 155279#L298-18 assume 1 == ~t1_pc~0; 155276#L299-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 155274#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 155272#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 155271#L728-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 155269#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 155267#L317-18 assume !(1 == ~t2_pc~0); 155265#L317-20 is_transmit2_triggered_~__retres1~2#1 := 0; 144662#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 144660#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 144478#L736-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 144479#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 144778#L336-18 assume !(1 == ~t3_pc~0); 144779#L336-20 is_transmit3_triggered_~__retres1~3#1 := 0; 144805#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 144692#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 144583#L744-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 144418#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 144419#L355-18 assume !(1 == ~t4_pc~0); 144724#L355-20 is_transmit4_triggered_~__retres1~4#1 := 0; 155450#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 155449#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 144630#L752-18 assume !(0 != activate_threads_~tmp___3~0#1); 144517#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 144518#L374-18 assume !(1 == ~t5_pc~0); 144727#L374-20 is_transmit5_triggered_~__retres1~5#1 := 0; 144576#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 144519#is_transmit5_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 144520#L760-18 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 144702#L760-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 144703#L649-3 assume !(1 == ~M_E~0); 144841#L649-5 assume !(1 == ~T1_E~0); 155493#L654-3 assume !(1 == ~T2_E~0); 155492#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 155491#L664-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 155490#L669-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 155489#L674-3 assume 1 == ~E_1~0;~E_1~0 := 2; 155488#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 155487#L684-3 assume 1 == ~E_3~0;~E_3~0 := 2; 155356#L689-3 assume !(1 == ~E_4~0); 155355#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 154231#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 152361#L439-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 152354#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 152352#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 152343#L919 assume !(0 == start_simulation_~tmp~3#1); 152341#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 152336#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 152330#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 152327#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 152325#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 152323#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 152321#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 152319#L932 assume !(0 != start_simulation_~tmp___0~1#1); 144615#L900-2 [2022-12-13 19:31:07,711 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:31:07,711 INFO L85 PathProgramCache]: Analyzing trace with hash -445595682, now seen corresponding path program 1 times [2022-12-13 19:31:07,711 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:31:07,711 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [579470957] [2022-12-13 19:31:07,711 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:31:07,711 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:31:07,720 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:31:07,758 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:31:07,758 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:31:07,758 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [579470957] [2022-12-13 19:31:07,759 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [579470957] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:31:07,759 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:31:07,759 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:31:07,759 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1098147930] [2022-12-13 19:31:07,759 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:31:07,759 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 19:31:07,760 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:31:07,760 INFO L85 PathProgramCache]: Analyzing trace with hash 658170302, now seen corresponding path program 1 times [2022-12-13 19:31:07,760 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:31:07,760 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [192433262] [2022-12-13 19:31:07,760 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:31:07,760 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:31:07,769 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:31:07,803 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:31:07,803 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:31:07,803 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [192433262] [2022-12-13 19:31:07,803 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [192433262] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:31:07,803 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:31:07,804 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-12-13 19:31:07,804 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1675086204] [2022-12-13 19:31:07,804 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:31:07,804 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 19:31:07,804 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 19:31:07,804 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 19:31:07,805 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 19:31:07,805 INFO L87 Difference]: Start difference. First operand 11243 states and 15953 transitions. cyclomatic complexity: 4718 Second operand has 4 states, 4 states have (on average 17.75) internal successors, (71), 3 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:31:07,929 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 19:31:07,929 INFO L93 Difference]: Finished difference Result 18761 states and 26436 transitions. [2022-12-13 19:31:07,929 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 18761 states and 26436 transitions. [2022-12-13 19:31:08,016 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 18573 [2022-12-13 19:31:08,066 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 18761 states to 18761 states and 26436 transitions. [2022-12-13 19:31:08,066 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 18761 [2022-12-13 19:31:08,075 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 18761 [2022-12-13 19:31:08,075 INFO L73 IsDeterministic]: Start isDeterministic. Operand 18761 states and 26436 transitions. [2022-12-13 19:31:08,085 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 19:31:08,086 INFO L218 hiAutomatonCegarLoop]: Abstraction has 18761 states and 26436 transitions. [2022-12-13 19:31:08,094 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 18761 states and 26436 transitions. [2022-12-13 19:31:08,186 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 18761 to 11243. [2022-12-13 19:31:08,196 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 11243 states, 11243 states have (on average 1.4069198612469982) internal successors, (15818), 11242 states have internal predecessors, (15818), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:31:08,208 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11243 states to 11243 states and 15818 transitions. [2022-12-13 19:31:08,209 INFO L240 hiAutomatonCegarLoop]: Abstraction has 11243 states and 15818 transitions. [2022-12-13 19:31:08,209 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 19:31:08,210 INFO L428 stractBuchiCegarLoop]: Abstraction has 11243 states and 15818 transitions. [2022-12-13 19:31:08,210 INFO L335 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2022-12-13 19:31:08,210 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 11243 states and 15818 transitions. [2022-12-13 19:31:08,240 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 11107 [2022-12-13 19:31:08,241 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 19:31:08,241 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 19:31:08,242 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:31:08,242 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:31:08,242 INFO L748 eck$LassoCheckResult]: Stem: 174557#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 174558#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 174677#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 174678#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 174695#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 174696#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 174491#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 174492#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 174814#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 174815#L421-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 174779#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 174461#L586 assume !(0 == ~M_E~0); 174462#L586-2 assume !(0 == ~T1_E~0); 174516#L591-1 assume !(0 == ~T2_E~0); 174637#L596-1 assume !(0 == ~T3_E~0); 174638#L601-1 assume !(0 == ~T4_E~0); 174682#L606-1 assume !(0 == ~T5_E~0); 174683#L611-1 assume !(0 == ~E_1~0); 174788#L616-1 assume !(0 == ~E_2~0); 174789#L621-1 assume !(0 == ~E_3~0); 174385#L626-1 assume !(0 == ~E_4~0); 174386#L631-1 assume !(0 == ~E_5~0); 174550#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 174383#L279 assume !(1 == ~m_pc~0); 174384#L279-2 is_master_triggered_~__retres1~0#1 := 0; 174712#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 174527#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 174528#L720 assume !(0 != activate_threads_~tmp~1#1); 174711#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 174559#L298 assume !(1 == ~t1_pc~0); 174332#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 174333#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 174359#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 174360#L728 assume !(0 != activate_threads_~tmp___0~0#1); 174392#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 174521#L317 assume !(1 == ~t2_pc~0); 174522#L317-2 is_transmit2_triggered_~__retres1~2#1 := 0; 174733#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 174681#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 174570#L736 assume !(0 != activate_threads_~tmp___1~0#1); 174571#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 174773#L336 assume !(1 == ~t3_pc~0); 174774#L336-2 is_transmit3_triggered_~__retres1~3#1 := 0; 174852#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 174304#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 174305#L744 assume !(0 != activate_threads_~tmp___2~0#1); 174721#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 174785#L355 assume !(1 == ~t4_pc~0); 174636#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 174782#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 174423#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 174424#L752 assume !(0 != activate_threads_~tmp___3~0#1); 174406#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 174407#L374 assume !(1 == ~t5_pc~0); 174541#L374-2 is_transmit5_triggered_~__retres1~5#1 := 0; 174542#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 174533#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 174534#L760 assume !(0 != activate_threads_~tmp___4~0#1); 174664#L760-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 174665#L649 assume !(1 == ~M_E~0); 174841#L649-2 assume !(1 == ~T1_E~0); 174369#L654-1 assume !(1 == ~T2_E~0); 174370#L659-1 assume !(1 == ~T3_E~0); 174567#L664-1 assume !(1 == ~T4_E~0); 174361#L669-1 assume !(1 == ~T5_E~0); 174362#L674-1 assume !(1 == ~E_1~0); 174763#L679-1 assume !(1 == ~E_2~0); 174463#L684-1 assume !(1 == ~E_3~0); 174464#L689-1 assume !(1 == ~E_4~0); 174631#L694-1 assume !(1 == ~E_5~0); 174628#L699-1 assume { :end_inline_reset_delta_events } true; 174629#L900-2 [2022-12-13 19:31:08,242 INFO L750 eck$LassoCheckResult]: Loop: 174629#L900-2 assume !false; 179053#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 179051#L561 assume !false; 179049#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 179045#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 179039#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 179035#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 179032#L486 assume !(0 != eval_~tmp~0#1); 179033#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 179337#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 179335#L586-3 assume !(0 == ~M_E~0); 179332#L586-5 assume !(0 == ~T1_E~0); 179329#L591-3 assume !(0 == ~T2_E~0); 179326#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 179323#L601-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 179320#L606-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 179317#L611-3 assume 0 == ~E_1~0;~E_1~0 := 1; 179314#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 179311#L621-3 assume !(0 == ~E_3~0); 179308#L626-3 assume !(0 == ~E_4~0); 179305#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 179297#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 179294#L279-18 assume !(1 == ~m_pc~0); 179291#L279-20 is_master_triggered_~__retres1~0#1 := 0; 179287#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 179285#is_master_triggered_returnLabel#7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 179282#L720-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 179279#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 179276#L298-18 assume 1 == ~t1_pc~0; 179272#L299-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 179268#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 179265#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 179262#L728-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 179258#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 179255#L317-18 assume !(1 == ~t2_pc~0); 179252#L317-20 is_transmit2_triggered_~__retres1~2#1 := 0; 179249#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 179246#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 179243#L736-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 179240#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 179237#L336-18 assume !(1 == ~t3_pc~0); 179234#L336-20 is_transmit3_triggered_~__retres1~3#1 := 0; 179231#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 179227#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 179223#L744-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 179219#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 179215#L355-18 assume 1 == ~t4_pc~0; 179210#L356-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 179204#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 179198#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 179191#L752-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 179185#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 179180#L374-18 assume !(1 == ~t5_pc~0); 179175#L374-20 is_transmit5_triggered_~__retres1~5#1 := 0; 179170#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 179166#is_transmit5_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 179162#L760-18 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 179158#L760-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 179154#L649-3 assume !(1 == ~M_E~0); 179149#L649-5 assume !(1 == ~T1_E~0); 179146#L654-3 assume !(1 == ~T2_E~0); 179143#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 179139#L664-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 179136#L669-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 179133#L674-3 assume 1 == ~E_1~0;~E_1~0 := 2; 179130#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 179127#L684-3 assume !(1 == ~E_3~0); 179124#L689-3 assume !(1 == ~E_4~0); 179120#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 179116#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 179112#L439-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 179103#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 179100#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 179096#L919 assume !(0 == start_simulation_~tmp~3#1); 179094#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 179091#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 179084#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 179081#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 179078#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 179070#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 179066#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 179062#L932 assume !(0 != start_simulation_~tmp___0~1#1); 174629#L900-2 [2022-12-13 19:31:08,243 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:31:08,243 INFO L85 PathProgramCache]: Analyzing trace with hash -445536100, now seen corresponding path program 1 times [2022-12-13 19:31:08,243 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:31:08,243 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [335666889] [2022-12-13 19:31:08,243 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:31:08,243 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:31:08,253 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 19:31:08,253 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 19:31:08,260 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 19:31:08,292 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 19:31:08,292 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:31:08,293 INFO L85 PathProgramCache]: Analyzing trace with hash 1127158943, now seen corresponding path program 1 times [2022-12-13 19:31:08,293 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:31:08,293 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [183788849] [2022-12-13 19:31:08,293 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:31:08,293 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:31:08,302 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:31:08,324 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:31:08,324 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:31:08,324 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [183788849] [2022-12-13 19:31:08,324 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [183788849] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:31:08,325 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:31:08,325 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:31:08,325 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [588427270] [2022-12-13 19:31:08,325 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:31:08,325 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 19:31:08,325 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 19:31:08,326 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 19:31:08,326 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 19:31:08,326 INFO L87 Difference]: Start difference. First operand 11243 states and 15818 transitions. cyclomatic complexity: 4583 Second operand has 3 states, 3 states have (on average 27.333333333333332) internal successors, (82), 3 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:31:08,435 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 19:31:08,435 INFO L93 Difference]: Finished difference Result 19860 states and 27670 transitions. [2022-12-13 19:31:08,435 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 19860 states and 27670 transitions. [2022-12-13 19:31:08,487 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 19614 [2022-12-13 19:31:08,533 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 19860 states to 19860 states and 27670 transitions. [2022-12-13 19:31:08,534 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 19860 [2022-12-13 19:31:08,543 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 19860 [2022-12-13 19:31:08,544 INFO L73 IsDeterministic]: Start isDeterministic. Operand 19860 states and 27670 transitions. [2022-12-13 19:31:08,555 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 19:31:08,555 INFO L218 hiAutomatonCegarLoop]: Abstraction has 19860 states and 27670 transitions. [2022-12-13 19:31:08,565 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 19860 states and 27670 transitions. [2022-12-13 19:31:08,730 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 19860 to 19848. [2022-12-13 19:31:08,744 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 19848 states, 19848 states have (on average 1.393490528012898) internal successors, (27658), 19847 states have internal predecessors, (27658), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:31:08,767 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19848 states to 19848 states and 27658 transitions. [2022-12-13 19:31:08,767 INFO L240 hiAutomatonCegarLoop]: Abstraction has 19848 states and 27658 transitions. [2022-12-13 19:31:08,768 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 19:31:08,768 INFO L428 stractBuchiCegarLoop]: Abstraction has 19848 states and 27658 transitions. [2022-12-13 19:31:08,768 INFO L335 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2022-12-13 19:31:08,768 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 19848 states and 27658 transitions. [2022-12-13 19:31:08,824 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 19602 [2022-12-13 19:31:08,824 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 19:31:08,824 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 19:31:08,825 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:31:08,825 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:31:08,825 INFO L748 eck$LassoCheckResult]: Stem: 205669#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 205670#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 205790#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 205791#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 205810#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 205811#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 205606#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 205607#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 205944#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 205945#L421-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 205899#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 205578#L586 assume !(0 == ~M_E~0); 205579#L586-2 assume !(0 == ~T1_E~0); 205630#L591-1 assume !(0 == ~T2_E~0); 205750#L596-1 assume !(0 == ~T3_E~0); 205751#L601-1 assume !(0 == ~T4_E~0); 205798#L606-1 assume !(0 == ~T5_E~0); 205799#L611-1 assume !(0 == ~E_1~0); 205911#L616-1 assume !(0 == ~E_2~0); 205912#L621-1 assume !(0 == ~E_3~0); 205494#L626-1 assume 0 == ~E_4~0;~E_4~0 := 1; 205495#L631-1 assume !(0 == ~E_5~0); 205869#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 205490#L279 assume !(1 == ~m_pc~0); 205491#L279-2 is_master_triggered_~__retres1~0#1 := 0; 205932#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 205933#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 205828#L720 assume !(0 != activate_threads_~tmp~1#1); 205829#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 205671#L298 assume !(1 == ~t1_pc~0); 205672#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 205988#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 205989#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 205503#L728 assume !(0 != activate_threads_~tmp___0~0#1); 205504#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 205635#L317 assume !(1 == ~t2_pc~0); 205636#L317-2 is_transmit2_triggered_~__retres1~2#1 := 0; 206039#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 206038#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 206036#L736 assume !(0 != activate_threads_~tmp___1~0#1); 206035#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 206034#L336 assume !(1 == ~t3_pc~0); 206032#L336-2 is_transmit3_triggered_~__retres1~3#1 := 0; 206030#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 205413#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 205414#L744 assume !(0 != activate_threads_~tmp___2~0#1); 205904#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 205905#L355 assume !(1 == ~t4_pc~0); 205953#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 206046#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 206045#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 206042#L752 assume !(0 != activate_threads_~tmp___3~0#1); 206041#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 206040#L374 assume !(1 == ~t5_pc~0); 205656#L374-2 is_transmit5_triggered_~__retres1~5#1 := 0; 205657#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 205946#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 206033#L760 assume !(0 != activate_threads_~tmp___4~0#1); 206031#L760-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 206029#L649 assume !(1 == ~M_E~0); 206028#L649-2 assume !(1 == ~T1_E~0); 205477#L654-1 assume !(1 == ~T2_E~0); 205478#L659-1 assume !(1 == ~T3_E~0); 205681#L664-1 assume !(1 == ~T4_E~0); 205682#L669-1 assume !(1 == ~T5_E~0); 206025#L674-1 assume !(1 == ~E_1~0); 206024#L679-1 assume !(1 == ~E_2~0); 206023#L684-1 assume !(1 == ~E_3~0); 205743#L689-1 assume 1 == ~E_4~0;~E_4~0 := 2; 205744#L694-1 assume !(1 == ~E_5~0); 205740#L699-1 assume { :end_inline_reset_delta_events } true; 205741#L900-2 [2022-12-13 19:31:08,826 INFO L750 eck$LassoCheckResult]: Loop: 205741#L900-2 assume !false; 214160#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 214156#L561 assume !false; 214152#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 214133#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 214124#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 214119#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 214113#L486 assume !(0 != eval_~tmp~0#1); 214114#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 219583#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 219581#L586-3 assume !(0 == ~M_E~0); 219577#L586-5 assume !(0 == ~T1_E~0); 219575#L591-3 assume !(0 == ~T2_E~0); 219574#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 219573#L601-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 219566#L606-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 219564#L611-3 assume 0 == ~E_1~0;~E_1~0 := 1; 219562#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 219560#L621-3 assume !(0 == ~E_3~0); 219557#L626-3 assume !(0 == ~E_4~0); 219555#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 219553#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 219551#L279-18 assume !(1 == ~m_pc~0); 219550#L279-20 is_master_triggered_~__retres1~0#1 := 0; 219549#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 219548#is_master_triggered_returnLabel#7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 219547#L720-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 219545#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 219423#L298-18 assume !(1 == ~t1_pc~0); 219422#L298-20 is_transmit1_triggered_~__retres1~1#1 := 0; 219420#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 219419#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 219417#L728-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 219415#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 219413#L317-18 assume !(1 == ~t2_pc~0); 219412#L317-20 is_transmit2_triggered_~__retres1~2#1 := 0; 219411#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 219410#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 219409#L736-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 217421#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 217416#L336-18 assume !(1 == ~t3_pc~0); 217411#L336-20 is_transmit3_triggered_~__retres1~3#1 := 0; 217409#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 217407#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 217406#L744-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 217405#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 217402#L355-18 assume 1 == ~t4_pc~0; 217403#L356-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 205962#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 224873#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 224872#L752-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 205643#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 205644#L374-18 assume !(1 == ~t5_pc~0); 205861#L374-20 is_transmit5_triggered_~__retres1~5#1 := 0; 205707#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 205645#is_transmit5_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 205646#L760-18 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 205832#L760-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 205833#L649-3 assume !(1 == ~M_E~0); 205991#L649-5 assume !(1 == ~T1_E~0); 225083#L654-3 assume !(1 == ~T2_E~0); 225081#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 225080#L664-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 224672#L669-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 224671#L674-3 assume 1 == ~E_1~0;~E_1~0 := 2; 211458#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 211453#L684-3 assume !(1 == ~E_3~0); 211450#L689-3 assume 1 == ~E_4~0;~E_4~0 := 2; 211446#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 211305#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 211131#L439-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 211126#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 211119#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 211120#L919 assume !(0 == start_simulation_~tmp~3#1); 214223#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 214218#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 214210#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 214206#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 214202#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 214196#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 214193#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 214174#L932 assume !(0 != start_simulation_~tmp___0~1#1); 205741#L900-2 [2022-12-13 19:31:08,826 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:31:08,826 INFO L85 PathProgramCache]: Analyzing trace with hash 1583048088, now seen corresponding path program 1 times [2022-12-13 19:31:08,826 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:31:08,826 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [387312777] [2022-12-13 19:31:08,826 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:31:08,827 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:31:08,834 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:31:08,866 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:31:08,866 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:31:08,866 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [387312777] [2022-12-13 19:31:08,867 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [387312777] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:31:08,867 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:31:08,867 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:31:08,867 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1026858036] [2022-12-13 19:31:08,867 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:31:08,867 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 19:31:08,867 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:31:08,867 INFO L85 PathProgramCache]: Analyzing trace with hash -1785143428, now seen corresponding path program 1 times [2022-12-13 19:31:08,868 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:31:08,868 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1629137484] [2022-12-13 19:31:08,868 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:31:08,868 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:31:08,875 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:31:08,900 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:31:08,900 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:31:08,900 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1629137484] [2022-12-13 19:31:08,900 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1629137484] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:31:08,900 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:31:08,900 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-12-13 19:31:08,900 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1130426800] [2022-12-13 19:31:08,900 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:31:08,900 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 19:31:08,900 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 19:31:08,901 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 19:31:08,901 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 19:31:08,901 INFO L87 Difference]: Start difference. First operand 19848 states and 27658 transitions. cyclomatic complexity: 7818 Second operand has 4 states, 4 states have (on average 17.75) internal successors, (71), 3 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:31:09,048 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 19:31:09,048 INFO L93 Difference]: Finished difference Result 39005 states and 54351 transitions. [2022-12-13 19:31:09,048 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 39005 states and 54351 transitions. [2022-12-13 19:31:09,154 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 35729 [2022-12-13 19:31:09,283 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 39005 states to 39005 states and 54351 transitions. [2022-12-13 19:31:09,284 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 39005 [2022-12-13 19:31:09,296 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 39005 [2022-12-13 19:31:09,296 INFO L73 IsDeterministic]: Start isDeterministic. Operand 39005 states and 54351 transitions. [2022-12-13 19:31:09,313 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 19:31:09,313 INFO L218 hiAutomatonCegarLoop]: Abstraction has 39005 states and 54351 transitions. [2022-12-13 19:31:09,324 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 39005 states and 54351 transitions. [2022-12-13 19:31:09,459 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 39005 to 19815. [2022-12-13 19:31:09,473 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 19815 states, 19815 states have (on average 1.3918748422911935) internal successors, (27580), 19814 states have internal predecessors, (27580), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:31:09,494 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19815 states to 19815 states and 27580 transitions. [2022-12-13 19:31:09,495 INFO L240 hiAutomatonCegarLoop]: Abstraction has 19815 states and 27580 transitions. [2022-12-13 19:31:09,495 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 19:31:09,495 INFO L428 stractBuchiCegarLoop]: Abstraction has 19815 states and 27580 transitions. [2022-12-13 19:31:09,496 INFO L335 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2022-12-13 19:31:09,496 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 19815 states and 27580 transitions. [2022-12-13 19:31:09,534 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 19602 [2022-12-13 19:31:09,535 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 19:31:09,535 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 19:31:09,535 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:31:09,535 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:31:09,536 INFO L748 eck$LassoCheckResult]: Stem: 264528#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 264529#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 264649#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 264650#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 264669#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 264670#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 264464#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 264465#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 264798#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 264799#L421-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 264747#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 264433#L586 assume !(0 == ~M_E~0); 264434#L586-2 assume !(0 == ~T1_E~0); 264488#L591-1 assume !(0 == ~T2_E~0); 264609#L596-1 assume !(0 == ~T3_E~0); 264610#L601-1 assume !(0 == ~T4_E~0); 264655#L606-1 assume !(0 == ~T5_E~0); 264656#L611-1 assume !(0 == ~E_1~0); 264765#L616-1 assume !(0 == ~E_2~0); 264766#L621-1 assume !(0 == ~E_3~0); 264357#L626-1 assume !(0 == ~E_4~0); 264358#L631-1 assume !(0 == ~E_5~0); 264521#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 264353#L279 assume !(1 == ~m_pc~0); 264354#L279-2 is_master_triggered_~__retres1~0#1 := 0; 264686#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 264499#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 264500#L720 assume !(0 != activate_threads_~tmp~1#1); 264685#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 264530#L298 assume !(1 == ~t1_pc~0); 264304#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 264305#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 264329#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 264330#L728 assume !(0 != activate_threads_~tmp___0~0#1); 264364#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 264493#L317 assume !(1 == ~t2_pc~0); 264494#L317-2 is_transmit2_triggered_~__retres1~2#1 := 0; 264708#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 264654#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 264540#L736 assume !(0 != activate_threads_~tmp___1~0#1); 264541#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 264741#L336 assume !(1 == ~t3_pc~0); 264742#L336-2 is_transmit3_triggered_~__retres1~3#1 := 0; 264835#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 264278#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 264279#L744 assume !(0 != activate_threads_~tmp___2~0#1); 264694#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 264759#L355 assume !(1 == ~t4_pc~0); 264608#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 264450#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 264451#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 264729#L752 assume !(0 != activate_threads_~tmp___3~0#1); 264730#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 264786#L374 assume !(1 == ~t5_pc~0); 264787#L374-2 is_transmit5_triggered_~__retres1~5#1 := 0; 264800#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 264801#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 264819#L760 assume !(0 != activate_threads_~tmp___4~0#1); 264820#L760-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 264823#L649 assume !(1 == ~M_E~0); 264824#L649-2 assume !(1 == ~T1_E~0); 264341#L654-1 assume !(1 == ~T2_E~0); 264342#L659-1 assume !(1 == ~T3_E~0); 264538#L664-1 assume !(1 == ~T4_E~0); 264539#L669-1 assume !(1 == ~T5_E~0); 264732#L674-1 assume !(1 == ~E_1~0); 264733#L679-1 assume !(1 == ~E_2~0); 264437#L684-1 assume !(1 == ~E_3~0); 264438#L689-1 assume !(1 == ~E_4~0); 264602#L694-1 assume !(1 == ~E_5~0); 264598#L699-1 assume { :end_inline_reset_delta_events } true; 264599#L900-2 [2022-12-13 19:31:09,536 INFO L750 eck$LassoCheckResult]: Loop: 264599#L900-2 assume !false; 270131#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 270130#L561 assume !false; 270126#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 270122#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 270116#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 270114#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 270111#L486 assume !(0 != eval_~tmp~0#1); 270109#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 270107#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 270105#L586-3 assume !(0 == ~M_E~0); 270103#L586-5 assume !(0 == ~T1_E~0); 270100#L591-3 assume !(0 == ~T2_E~0); 270098#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 270096#L601-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 270094#L606-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 270092#L611-3 assume 0 == ~E_1~0;~E_1~0 := 1; 270090#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 270088#L621-3 assume !(0 == ~E_3~0); 270086#L626-3 assume !(0 == ~E_4~0); 270084#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 270082#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 270080#L279-18 assume !(1 == ~m_pc~0); 270078#L279-20 is_master_triggered_~__retres1~0#1 := 0; 270076#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 270074#is_master_triggered_returnLabel#7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 270072#L720-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 270070#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 270068#L298-18 assume 1 == ~t1_pc~0; 270064#L299-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 270062#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 270060#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 270058#L728-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 270055#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 270053#L317-18 assume !(1 == ~t2_pc~0); 269806#L317-20 is_transmit2_triggered_~__retres1~2#1 := 0; 269803#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 269801#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 269799#L736-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 269797#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 269790#L336-18 assume !(1 == ~t3_pc~0); 269788#L336-20 is_transmit3_triggered_~__retres1~3#1 := 0; 269786#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 269783#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 269781#L744-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 269779#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 269774#L355-18 assume !(1 == ~t4_pc~0); 269772#L355-20 is_transmit4_triggered_~__retres1~4#1 := 0; 269770#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 269768#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 269765#L752-18 assume !(0 != activate_threads_~tmp___3~0#1); 269763#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 269761#L374-18 assume !(1 == ~t5_pc~0); 269759#L374-20 is_transmit5_triggered_~__retres1~5#1 := 0; 269747#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 269741#is_transmit5_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 269735#L760-18 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 269728#L760-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 269722#L649-3 assume !(1 == ~M_E~0); 269576#L649-5 assume !(1 == ~T1_E~0); 269712#L654-3 assume !(1 == ~T2_E~0); 269706#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 269700#L664-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 269694#L669-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 269688#L674-3 assume 1 == ~E_1~0;~E_1~0 := 2; 269682#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 269677#L684-3 assume !(1 == ~E_3~0); 269671#L689-3 assume !(1 == ~E_4~0); 269666#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 269664#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 269639#L439-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 269627#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 269621#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 269615#L919 assume !(0 == start_simulation_~tmp~3#1); 269616#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 270259#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 270253#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 270252#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 270248#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 270246#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 270244#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 270242#L932 assume !(0 != start_simulation_~tmp___0~1#1); 264599#L900-2 [2022-12-13 19:31:09,536 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:31:09,536 INFO L85 PathProgramCache]: Analyzing trace with hash -445536100, now seen corresponding path program 2 times [2022-12-13 19:31:09,536 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:31:09,536 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1638566303] [2022-12-13 19:31:09,536 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:31:09,536 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:31:09,543 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 19:31:09,543 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 19:31:09,548 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 19:31:09,566 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 19:31:09,566 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:31:09,566 INFO L85 PathProgramCache]: Analyzing trace with hash -362898052, now seen corresponding path program 1 times [2022-12-13 19:31:09,566 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:31:09,566 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [587692380] [2022-12-13 19:31:09,566 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:31:09,566 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:31:09,572 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:31:09,596 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:31:09,597 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:31:09,597 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [587692380] [2022-12-13 19:31:09,597 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [587692380] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:31:09,597 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:31:09,597 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-12-13 19:31:09,597 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [129699106] [2022-12-13 19:31:09,597 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:31:09,597 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 19:31:09,598 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 19:31:09,598 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-12-13 19:31:09,598 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-12-13 19:31:09,598 INFO L87 Difference]: Start difference. First operand 19815 states and 27580 transitions. cyclomatic complexity: 7773 Second operand has 5 states, 5 states have (on average 16.4) internal successors, (82), 5 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:31:09,796 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 19:31:09,796 INFO L93 Difference]: Finished difference Result 34705 states and 47778 transitions. [2022-12-13 19:31:09,796 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 34705 states and 47778 transitions. [2022-12-13 19:31:09,914 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 34372 [2022-12-13 19:31:09,985 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 34705 states to 34705 states and 47778 transitions. [2022-12-13 19:31:09,985 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 34705 [2022-12-13 19:31:09,999 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 34705 [2022-12-13 19:31:09,999 INFO L73 IsDeterministic]: Start isDeterministic. Operand 34705 states and 47778 transitions. [2022-12-13 19:31:10,015 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 19:31:10,015 INFO L218 hiAutomatonCegarLoop]: Abstraction has 34705 states and 47778 transitions. [2022-12-13 19:31:10,030 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 34705 states and 47778 transitions. [2022-12-13 19:31:10,203 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 34705 to 20031. [2022-12-13 19:31:10,218 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 20031 states, 20031 states have (on average 1.387649143827068) internal successors, (27796), 20030 states have internal predecessors, (27796), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:31:10,250 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 20031 states to 20031 states and 27796 transitions. [2022-12-13 19:31:10,250 INFO L240 hiAutomatonCegarLoop]: Abstraction has 20031 states and 27796 transitions. [2022-12-13 19:31:10,251 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2022-12-13 19:31:10,251 INFO L428 stractBuchiCegarLoop]: Abstraction has 20031 states and 27796 transitions. [2022-12-13 19:31:10,251 INFO L335 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2022-12-13 19:31:10,252 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 20031 states and 27796 transitions. [2022-12-13 19:31:10,303 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 19818 [2022-12-13 19:31:10,303 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 19:31:10,303 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 19:31:10,304 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:31:10,304 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:31:10,305 INFO L748 eck$LassoCheckResult]: Stem: 319067#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 319068#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 319186#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 319187#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 319209#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 319210#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 319001#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 319002#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 319330#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 319331#L421-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 319286#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 318969#L586 assume !(0 == ~M_E~0); 318970#L586-2 assume !(0 == ~T1_E~0); 319025#L591-1 assume !(0 == ~T2_E~0); 319148#L596-1 assume !(0 == ~T3_E~0); 319149#L601-1 assume !(0 == ~T4_E~0); 319195#L606-1 assume !(0 == ~T5_E~0); 319196#L611-1 assume !(0 == ~E_1~0); 319298#L616-1 assume !(0 == ~E_2~0); 319299#L621-1 assume !(0 == ~E_3~0); 318893#L626-1 assume !(0 == ~E_4~0); 318894#L631-1 assume !(0 == ~E_5~0); 319060#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 318889#L279 assume !(1 == ~m_pc~0); 318890#L279-2 is_master_triggered_~__retres1~0#1 := 0; 319227#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 319037#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 319038#L720 assume !(0 != activate_threads_~tmp~1#1); 319226#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 319069#L298 assume !(1 == ~t1_pc~0); 318840#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 318841#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 318865#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 318866#L728 assume !(0 != activate_threads_~tmp___0~0#1); 318900#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 319031#L317 assume !(1 == ~t2_pc~0); 319032#L317-2 is_transmit2_triggered_~__retres1~2#1 := 0; 319249#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 319192#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 319079#L736 assume !(0 != activate_threads_~tmp___1~0#1); 319080#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 319281#L336 assume !(1 == ~t3_pc~0); 319282#L336-2 is_transmit3_triggered_~__retres1~3#1 := 0; 319364#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 318814#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 318815#L744 assume !(0 != activate_threads_~tmp___2~0#1); 319235#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 319291#L355 assume !(1 == ~t4_pc~0); 319145#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 318987#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 318988#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 319269#L752 assume !(0 != activate_threads_~tmp___3~0#1); 319270#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 319319#L374 assume !(1 == ~t5_pc~0); 319320#L374-2 is_transmit5_triggered_~__retres1~5#1 := 0; 319332#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 319333#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 319350#L760 assume !(0 != activate_threads_~tmp___4~0#1); 319351#L760-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 319355#L649 assume !(1 == ~M_E~0); 319356#L649-2 assume !(1 == ~T1_E~0); 318877#L654-1 assume !(1 == ~T2_E~0); 318878#L659-1 assume !(1 == ~T3_E~0); 319390#L664-1 assume !(1 == ~T4_E~0); 318869#L669-1 assume !(1 == ~T5_E~0); 318870#L674-1 assume !(1 == ~E_1~0); 319272#L679-1 assume !(1 == ~E_2~0); 318973#L684-1 assume !(1 == ~E_3~0); 318974#L689-1 assume !(1 == ~E_4~0); 319140#L694-1 assume !(1 == ~E_5~0); 319137#L699-1 assume { :end_inline_reset_delta_events } true; 319138#L900-2 [2022-12-13 19:31:10,305 INFO L750 eck$LassoCheckResult]: Loop: 319138#L900-2 assume !false; 336120#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 333395#L561 assume !false; 335658#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 335655#L439 assume !(0 == ~m_st~0); 335652#L443 assume !(0 == ~t1_st~0); 335648#L447 assume !(0 == ~t2_st~0); 335644#L451 assume !(0 == ~t3_st~0); 335641#L455 assume !(0 == ~t4_st~0); 335637#L459 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6#1 := 0; 335633#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 335629#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 335628#L486 assume !(0 != eval_~tmp~0#1); 335626#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 335624#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 335622#L586-3 assume !(0 == ~M_E~0); 335620#L586-5 assume !(0 == ~T1_E~0); 335618#L591-3 assume !(0 == ~T2_E~0); 335616#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 335614#L601-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 335612#L606-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 335610#L611-3 assume 0 == ~E_1~0;~E_1~0 := 1; 335608#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 335606#L621-3 assume !(0 == ~E_3~0); 335604#L626-3 assume !(0 == ~E_4~0); 335602#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 335600#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 335598#L279-18 assume !(1 == ~m_pc~0); 335596#L279-20 is_master_triggered_~__retres1~0#1 := 0; 335594#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 335592#is_master_triggered_returnLabel#7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 335590#L720-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 335588#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 335586#L298-18 assume !(1 == ~t1_pc~0); 335583#L298-20 is_transmit1_triggered_~__retres1~1#1 := 0; 335580#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 335578#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 335576#L728-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 335574#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 335572#L317-18 assume !(1 == ~t2_pc~0); 335570#L317-20 is_transmit2_triggered_~__retres1~2#1 := 0; 335568#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 335566#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 335564#L736-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 335562#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 335560#L336-18 assume !(1 == ~t3_pc~0); 335558#L336-20 is_transmit3_triggered_~__retres1~3#1 := 0; 335556#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 335554#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 335552#L744-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 335547#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 335544#L355-18 assume !(1 == ~t4_pc~0); 335541#L355-20 is_transmit4_triggered_~__retres1~4#1 := 0; 335538#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 335535#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 335532#L752-18 assume !(0 != activate_threads_~tmp___3~0#1); 335530#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 335528#L374-18 assume !(1 == ~t5_pc~0); 335526#L374-20 is_transmit5_triggered_~__retres1~5#1 := 0; 335524#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 335522#is_transmit5_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 335520#L760-18 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 335518#L760-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 335516#L649-3 assume !(1 == ~M_E~0); 335042#L649-5 assume !(1 == ~T1_E~0); 335514#L654-3 assume !(1 == ~T2_E~0); 335512#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 335510#L664-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 335508#L669-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 335506#L674-3 assume 1 == ~E_1~0;~E_1~0 := 2; 335504#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 335502#L684-3 assume !(1 == ~E_3~0); 335500#L689-3 assume !(1 == ~E_4~0); 335499#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 335498#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 335497#L439-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 335488#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 335482#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 335478#L919 assume !(0 == start_simulation_~tmp~3#1); 335479#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 336154#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 336142#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 336139#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 336136#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 336133#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 336130#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 336128#L932 assume !(0 != start_simulation_~tmp___0~1#1); 319138#L900-2 [2022-12-13 19:31:10,305 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:31:10,305 INFO L85 PathProgramCache]: Analyzing trace with hash -445536100, now seen corresponding path program 3 times [2022-12-13 19:31:10,305 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:31:10,305 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1958027437] [2022-12-13 19:31:10,306 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:31:10,306 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:31:10,314 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 19:31:10,314 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 19:31:10,318 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 19:31:10,327 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 19:31:10,328 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:31:10,328 INFO L85 PathProgramCache]: Analyzing trace with hash 1144927642, now seen corresponding path program 1 times [2022-12-13 19:31:10,328 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:31:10,328 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [533936581] [2022-12-13 19:31:10,328 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:31:10,328 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:31:10,337 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:31:10,396 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:31:10,396 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:31:10,396 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [533936581] [2022-12-13 19:31:10,396 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [533936581] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:31:10,396 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:31:10,396 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-12-13 19:31:10,396 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [86993432] [2022-12-13 19:31:10,396 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:31:10,397 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 19:31:10,397 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 19:31:10,397 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-12-13 19:31:10,397 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-12-13 19:31:10,397 INFO L87 Difference]: Start difference. First operand 20031 states and 27796 transitions. cyclomatic complexity: 7773 Second operand has 5 states, 5 states have (on average 17.4) internal successors, (87), 5 states have internal predecessors, (87), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:31:10,614 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 19:31:10,614 INFO L93 Difference]: Finished difference Result 32075 states and 44605 transitions. [2022-12-13 19:31:10,614 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 32075 states and 44605 transitions. [2022-12-13 19:31:10,730 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 31862 [2022-12-13 19:31:10,803 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 32075 states to 32075 states and 44605 transitions. [2022-12-13 19:31:10,803 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 32075 [2022-12-13 19:31:10,820 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 32075 [2022-12-13 19:31:10,820 INFO L73 IsDeterministic]: Start isDeterministic. Operand 32075 states and 44605 transitions. [2022-12-13 19:31:10,836 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 19:31:10,836 INFO L218 hiAutomatonCegarLoop]: Abstraction has 32075 states and 44605 transitions. [2022-12-13 19:31:10,852 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 32075 states and 44605 transitions. [2022-12-13 19:31:11,065 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 32075 to 20283. [2022-12-13 19:31:11,077 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 20283 states, 20283 states have (on average 1.3720356949169255) internal successors, (27829), 20282 states have internal predecessors, (27829), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:31:11,099 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 20283 states to 20283 states and 27829 transitions. [2022-12-13 19:31:11,100 INFO L240 hiAutomatonCegarLoop]: Abstraction has 20283 states and 27829 transitions. [2022-12-13 19:31:11,100 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-12-13 19:31:11,100 INFO L428 stractBuchiCegarLoop]: Abstraction has 20283 states and 27829 transitions. [2022-12-13 19:31:11,101 INFO L335 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2022-12-13 19:31:11,101 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 20283 states and 27829 transitions. [2022-12-13 19:31:11,141 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 20070 [2022-12-13 19:31:11,141 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 19:31:11,141 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 19:31:11,142 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:31:11,142 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:31:11,142 INFO L748 eck$LassoCheckResult]: Stem: 371187#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 371188#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 371313#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 371314#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 371336#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 371337#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 371124#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 371125#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 371466#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 371467#L421-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 371415#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 371091#L586 assume !(0 == ~M_E~0); 371092#L586-2 assume !(0 == ~T1_E~0); 371147#L591-1 assume !(0 == ~T2_E~0); 371272#L596-1 assume !(0 == ~T3_E~0); 371273#L601-1 assume !(0 == ~T4_E~0); 371321#L606-1 assume !(0 == ~T5_E~0); 371322#L611-1 assume !(0 == ~E_1~0); 371432#L616-1 assume !(0 == ~E_2~0); 371433#L621-1 assume !(0 == ~E_3~0); 371012#L626-1 assume !(0 == ~E_4~0); 371013#L631-1 assume !(0 == ~E_5~0); 371180#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 371008#L279 assume !(1 == ~m_pc~0); 371009#L279-2 is_master_triggered_~__retres1~0#1 := 0; 371356#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 371158#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 371159#L720 assume !(0 != activate_threads_~tmp~1#1); 371355#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 371189#L298 assume !(1 == ~t1_pc~0); 370958#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 370959#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 370983#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 370984#L728 assume !(0 != activate_threads_~tmp___0~0#1); 371020#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 371152#L317 assume !(1 == ~t2_pc~0); 371153#L317-2 is_transmit2_triggered_~__retres1~2#1 := 0; 371376#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 371318#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 371199#L736 assume !(0 != activate_threads_~tmp___1~0#1); 371200#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 371410#L336 assume !(1 == ~t3_pc~0); 371411#L336-2 is_transmit3_triggered_~__retres1~3#1 := 0; 371517#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 370932#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 370933#L744 assume !(0 != activate_threads_~tmp___2~0#1); 371364#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 371422#L355 assume !(1 == ~t4_pc~0); 371269#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 371109#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 371110#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 371399#L752 assume !(0 != activate_threads_~tmp___3~0#1); 371400#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 371454#L374 assume !(1 == ~t5_pc~0); 371455#L374-2 is_transmit5_triggered_~__retres1~5#1 := 0; 371468#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 371469#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 371494#L760 assume !(0 != activate_threads_~tmp___4~0#1); 371495#L760-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 371504#L649 assume !(1 == ~M_E~0); 371505#L649-2 assume !(1 == ~T1_E~0); 370996#L654-1 assume !(1 == ~T2_E~0); 370997#L659-1 assume !(1 == ~T3_E~0); 371539#L664-1 assume !(1 == ~T4_E~0); 370988#L669-1 assume !(1 == ~T5_E~0); 370989#L674-1 assume !(1 == ~E_1~0); 371402#L679-1 assume !(1 == ~E_2~0); 371095#L684-1 assume !(1 == ~E_3~0); 371096#L689-1 assume !(1 == ~E_4~0); 371264#L694-1 assume !(1 == ~E_5~0); 371261#L699-1 assume { :end_inline_reset_delta_events } true; 371262#L900-2 [2022-12-13 19:31:11,143 INFO L750 eck$LassoCheckResult]: Loop: 371262#L900-2 assume !false; 377561#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 374331#L561 assume !false; 377560#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 377559#L439 assume !(0 == ~m_st~0); 377558#L443 assume !(0 == ~t1_st~0); 377557#L447 assume !(0 == ~t2_st~0); 377556#L451 assume !(0 == ~t3_st~0); 377555#L455 assume !(0 == ~t4_st~0); 377553#L459 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6#1 := 0; 377552#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 377551#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 377550#L486 assume !(0 != eval_~tmp~0#1); 374960#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 374956#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 374953#L586-3 assume !(0 == ~M_E~0); 374950#L586-5 assume !(0 == ~T1_E~0); 374947#L591-3 assume !(0 == ~T2_E~0); 374944#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 374941#L601-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 374938#L606-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 374935#L611-3 assume 0 == ~E_1~0;~E_1~0 := 1; 374932#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 374929#L621-3 assume !(0 == ~E_3~0); 374926#L626-3 assume !(0 == ~E_4~0); 374923#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 374921#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 374918#L279-18 assume !(1 == ~m_pc~0); 374915#L279-20 is_master_triggered_~__retres1~0#1 := 0; 374912#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 374909#is_master_triggered_returnLabel#7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 374905#L720-18 assume !(0 != activate_threads_~tmp~1#1); 374739#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 374736#L298-18 assume 1 == ~t1_pc~0; 374733#L299-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 374731#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 374729#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 374727#L728-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 374725#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 374723#L317-18 assume !(1 == ~t2_pc~0); 374721#L317-20 is_transmit2_triggered_~__retres1~2#1 := 0; 374719#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 374717#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 374715#L736-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 374713#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 374711#L336-18 assume !(1 == ~t3_pc~0); 374709#L336-20 is_transmit3_triggered_~__retres1~3#1 := 0; 374707#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 374705#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 374703#L744-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 374700#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 374696#L355-18 assume !(1 == ~t4_pc~0); 374694#L355-20 is_transmit4_triggered_~__retres1~4#1 := 0; 374690#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 374688#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 374611#L752-18 assume !(0 != activate_threads_~tmp___3~0#1); 374603#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 374594#L374-18 assume !(1 == ~t5_pc~0); 374586#L374-20 is_transmit5_triggered_~__retres1~5#1 := 0; 374578#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 374569#is_transmit5_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 374560#L760-18 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 374551#L760-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 374542#L649-3 assume !(1 == ~M_E~0); 374534#L649-5 assume !(1 == ~T1_E~0); 374525#L654-3 assume !(1 == ~T2_E~0); 374518#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 374512#L664-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 374504#L669-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 374496#L674-3 assume 1 == ~E_1~0;~E_1~0 := 2; 374489#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 374483#L684-3 assume !(1 == ~E_3~0); 374478#L689-3 assume !(1 == ~E_4~0); 374400#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 374399#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 374397#L439-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 374392#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 374367#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 374368#L919 assume !(0 == start_simulation_~tmp~3#1); 374359#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 374360#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 377567#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 377566#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 377565#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 377564#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 377563#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 377562#L932 assume !(0 != start_simulation_~tmp___0~1#1); 371262#L900-2 [2022-12-13 19:31:11,143 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:31:11,143 INFO L85 PathProgramCache]: Analyzing trace with hash -445536100, now seen corresponding path program 4 times [2022-12-13 19:31:11,143 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:31:11,143 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1380303651] [2022-12-13 19:31:11,143 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:31:11,144 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:31:11,150 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 19:31:11,150 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 19:31:11,155 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 19:31:11,162 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 19:31:11,162 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:31:11,162 INFO L85 PathProgramCache]: Analyzing trace with hash 1082801145, now seen corresponding path program 1 times [2022-12-13 19:31:11,162 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:31:11,162 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [686707590] [2022-12-13 19:31:11,162 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:31:11,163 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:31:11,169 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:31:11,188 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:31:11,188 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:31:11,188 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [686707590] [2022-12-13 19:31:11,188 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [686707590] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:31:11,188 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:31:11,188 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:31:11,188 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1431087965] [2022-12-13 19:31:11,188 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:31:11,189 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 19:31:11,189 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 19:31:11,189 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 19:31:11,189 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 19:31:11,189 INFO L87 Difference]: Start difference. First operand 20283 states and 27829 transitions. cyclomatic complexity: 7554 Second operand has 3 states, 3 states have (on average 29.0) internal successors, (87), 3 states have internal predecessors, (87), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:31:11,279 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 19:31:11,279 INFO L93 Difference]: Finished difference Result 30540 states and 41404 transitions. [2022-12-13 19:31:11,279 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 30540 states and 41404 transitions. [2022-12-13 19:31:11,366 INFO L131 ngComponentsAnalysis]: Automaton has 18 accepting balls. 30385 [2022-12-13 19:31:11,419 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 30540 states to 30540 states and 41404 transitions. [2022-12-13 19:31:11,419 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 30540 [2022-12-13 19:31:11,432 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 30540 [2022-12-13 19:31:11,433 INFO L73 IsDeterministic]: Start isDeterministic. Operand 30540 states and 41404 transitions. [2022-12-13 19:31:11,444 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 19:31:11,444 INFO L218 hiAutomatonCegarLoop]: Abstraction has 30540 states and 41404 transitions. [2022-12-13 19:31:11,456 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 30540 states and 41404 transitions. [2022-12-13 19:31:11,607 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 30540 to 29916. [2022-12-13 19:31:11,625 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 29916 states, 29916 states have (on average 1.3575344297365959) internal successors, (40612), 29915 states have internal predecessors, (40612), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:31:11,661 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 29916 states to 29916 states and 40612 transitions. [2022-12-13 19:31:11,662 INFO L240 hiAutomatonCegarLoop]: Abstraction has 29916 states and 40612 transitions. [2022-12-13 19:31:11,662 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 19:31:11,662 INFO L428 stractBuchiCegarLoop]: Abstraction has 29916 states and 40612 transitions. [2022-12-13 19:31:11,662 INFO L335 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2022-12-13 19:31:11,663 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 29916 states and 40612 transitions. [2022-12-13 19:31:11,729 INFO L131 ngComponentsAnalysis]: Automaton has 18 accepting balls. 29761 [2022-12-13 19:31:11,729 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 19:31:11,729 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 19:31:11,730 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:31:11,730 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:31:11,730 INFO L748 eck$LassoCheckResult]: Stem: 422018#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 422019#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 422153#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 422154#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 422173#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 422174#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 421952#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 421953#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 422300#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 422301#L421-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 422256#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 421920#L586 assume !(0 == ~M_E~0); 421921#L586-2 assume !(0 == ~T1_E~0); 421978#L591-1 assume !(0 == ~T2_E~0); 422107#L596-1 assume !(0 == ~T3_E~0); 422108#L601-1 assume !(0 == ~T4_E~0); 422160#L606-1 assume !(0 == ~T5_E~0); 422161#L611-1 assume !(0 == ~E_1~0); 422265#L616-1 assume !(0 == ~E_2~0); 422266#L621-1 assume !(0 == ~E_3~0); 421844#L626-1 assume !(0 == ~E_4~0); 421845#L631-1 assume !(0 == ~E_5~0); 422013#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 421842#L279 assume !(1 == ~m_pc~0); 421843#L279-2 is_master_triggered_~__retres1~0#1 := 0; 422192#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 421990#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 421991#L720 assume !(0 != activate_threads_~tmp~1#1); 422191#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 422020#L298 assume !(1 == ~t1_pc~0); 421790#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 421791#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 421817#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 421818#L728 assume !(0 != activate_threads_~tmp___0~0#1); 421851#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 421984#L317 assume !(1 == ~t2_pc~0); 421985#L317-2 is_transmit2_triggered_~__retres1~2#1 := 0; 422214#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 422157#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 422033#L736 assume !(0 != activate_threads_~tmp___1~0#1); 422034#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 422249#L336 assume !(1 == ~t3_pc~0); 422250#L336-2 is_transmit3_triggered_~__retres1~3#1 := 0; 422338#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 421762#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 421763#L744 assume !(0 != activate_threads_~tmp___2~0#1); 422200#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 422260#L355 assume !(1 == ~t4_pc~0); 422106#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 421939#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 421940#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 422236#L752 assume !(0 != activate_threads_~tmp___3~0#1); 422237#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 422288#L374 assume !(1 == ~t5_pc~0); 422289#L374-2 is_transmit5_triggered_~__retres1~5#1 := 0; 422302#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 422303#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 422322#L760 assume !(0 != activate_threads_~tmp___4~0#1); 422323#L760-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 422326#L649 assume !(1 == ~M_E~0); 422327#L649-2 assume !(1 == ~T1_E~0); 421827#L654-1 assume !(1 == ~T2_E~0); 421828#L659-1 assume !(1 == ~T3_E~0); 422364#L664-1 assume !(1 == ~T4_E~0); 421819#L669-1 assume !(1 == ~T5_E~0); 421820#L674-1 assume !(1 == ~E_1~0); 422238#L679-1 assume !(1 == ~E_2~0); 421922#L684-1 assume !(1 == ~E_3~0); 421923#L689-1 assume !(1 == ~E_4~0); 422100#L694-1 assume !(1 == ~E_5~0); 422096#L699-1 assume { :end_inline_reset_delta_events } true; 422097#L900-2 assume !false; 443371#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 443369#L561 [2022-12-13 19:31:11,730 INFO L750 eck$LassoCheckResult]: Loop: 443369#L561 assume !false; 443367#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 443364#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 443361#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 443359#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 443357#L486 assume 0 != eval_~tmp~0#1; 443354#L486-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 443351#L494 assume !(0 != eval_~tmp_ndt_1~0#1); 443329#L491 assume !(0 == ~t1_st~0); 443172#L505 assume !(0 == ~t2_st~0); 443170#L519 assume !(0 == ~t3_st~0); 443376#L533 assume !(0 == ~t4_st~0); 443374#L547 assume !(0 == ~t5_st~0); 443369#L561 [2022-12-13 19:31:11,731 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:31:11,731 INFO L85 PathProgramCache]: Analyzing trace with hash 1336547998, now seen corresponding path program 1 times [2022-12-13 19:31:11,731 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:31:11,731 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [623453216] [2022-12-13 19:31:11,731 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:31:11,731 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:31:11,739 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 19:31:11,739 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 19:31:11,743 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 19:31:11,754 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 19:31:11,754 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:31:11,754 INFO L85 PathProgramCache]: Analyzing trace with hash -519083082, now seen corresponding path program 1 times [2022-12-13 19:31:11,755 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:31:11,755 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1307146010] [2022-12-13 19:31:11,755 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:31:11,755 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:31:11,757 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 19:31:11,757 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 19:31:11,759 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 19:31:11,760 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 19:31:11,760 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:31:11,760 INFO L85 PathProgramCache]: Analyzing trace with hash -517720007, now seen corresponding path program 1 times [2022-12-13 19:31:11,760 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:31:11,761 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1150395139] [2022-12-13 19:31:11,761 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:31:11,761 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:31:11,767 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:31:11,785 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:31:11,786 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:31:11,786 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1150395139] [2022-12-13 19:31:11,786 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1150395139] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:31:11,786 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:31:11,786 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:31:11,786 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [425890413] [2022-12-13 19:31:11,786 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:31:11,855 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 19:31:11,855 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 19:31:11,855 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 19:31:11,855 INFO L87 Difference]: Start difference. First operand 29916 states and 40612 transitions. cyclomatic complexity: 10714 Second operand has 3 states, 3 states have (on average 28.666666666666668) internal successors, (86), 3 states have internal predecessors, (86), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:31:11,994 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 19:31:11,994 INFO L93 Difference]: Finished difference Result 54702 states and 73437 transitions. [2022-12-13 19:31:11,994 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 54702 states and 73437 transitions. [2022-12-13 19:31:12,291 INFO L131 ngComponentsAnalysis]: Automaton has 18 accepting balls. 54398 [2022-12-13 19:31:12,373 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 54702 states to 54702 states and 73437 transitions. [2022-12-13 19:31:12,373 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 54702 [2022-12-13 19:31:12,395 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 54702 [2022-12-13 19:31:12,395 INFO L73 IsDeterministic]: Start isDeterministic. Operand 54702 states and 73437 transitions. [2022-12-13 19:31:12,412 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 19:31:12,412 INFO L218 hiAutomatonCegarLoop]: Abstraction has 54702 states and 73437 transitions. [2022-12-13 19:31:12,433 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 54702 states and 73437 transitions. [2022-12-13 19:31:12,701 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 54702 to 50770. [2022-12-13 19:31:12,731 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 50770 states, 50770 states have (on average 1.3517628520779987) internal successors, (68629), 50769 states have internal predecessors, (68629), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:31:12,796 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 50770 states to 50770 states and 68629 transitions. [2022-12-13 19:31:12,796 INFO L240 hiAutomatonCegarLoop]: Abstraction has 50770 states and 68629 transitions. [2022-12-13 19:31:12,797 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 19:31:12,797 INFO L428 stractBuchiCegarLoop]: Abstraction has 50770 states and 68629 transitions. [2022-12-13 19:31:12,797 INFO L335 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2022-12-13 19:31:12,797 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 50770 states and 68629 transitions. [2022-12-13 19:31:12,917 INFO L131 ngComponentsAnalysis]: Automaton has 18 accepting balls. 50466 [2022-12-13 19:31:12,917 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 19:31:12,917 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 19:31:12,918 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:31:12,918 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:31:12,918 INFO L748 eck$LassoCheckResult]: Stem: 506653#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 506654#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 506800#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 506801#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 506822#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 506823#L401-2 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 506586#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 506587#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 506954#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 506955#L421-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 506906#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 506548#L586 assume !(0 == ~M_E~0); 506549#L586-2 assume !(0 == ~T1_E~0); 506611#L591-1 assume !(0 == ~T2_E~0); 506745#L596-1 assume !(0 == ~T3_E~0); 506746#L601-1 assume !(0 == ~T4_E~0); 506808#L606-1 assume !(0 == ~T5_E~0); 506809#L611-1 assume !(0 == ~E_1~0); 506923#L616-1 assume !(0 == ~E_2~0); 506924#L621-1 assume !(0 == ~E_3~0); 506467#L626-1 assume !(0 == ~E_4~0); 506468#L631-1 assume !(0 == ~E_5~0); 506646#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 506463#L279 assume !(1 == ~m_pc~0); 506464#L279-2 is_master_triggered_~__retres1~0#1 := 0; 506841#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 506623#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 506624#L720 assume !(0 != activate_threads_~tmp~1#1); 506840#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 506655#L298 assume !(1 == ~t1_pc~0); 506413#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 506414#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 506438#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 506439#L728 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 506475#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 527612#L317 assume !(1 == ~t2_pc~0); 527611#L317-2 is_transmit2_triggered_~__retres1~2#1 := 0; 527610#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 527609#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 527608#L736 assume !(0 != activate_threads_~tmp___1~0#1); 527607#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 527606#L336 assume !(1 == ~t3_pc~0); 527605#L336-2 is_transmit3_triggered_~__retres1~3#1 := 0; 527604#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 527603#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 527602#L744 assume !(0 != activate_threads_~tmp___2~0#1); 527601#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 527600#L355 assume !(1 == ~t4_pc~0); 506912#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 506913#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 507059#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 507060#L752 assume !(0 != activate_threads_~tmp___3~0#1); 507057#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 507058#L374 assume !(1 == ~t5_pc~0); 507055#L374-2 is_transmit5_triggered_~__retres1~5#1 := 0; 507056#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 507053#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 507054#L760 assume !(0 != activate_threads_~tmp___4~0#1); 507051#L760-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 507052#L649 assume !(1 == ~M_E~0); 507032#L649-2 assume !(1 == ~T1_E~0); 507033#L654-1 assume !(1 == ~T2_E~0); 507046#L659-1 assume !(1 == ~T3_E~0); 507047#L664-1 assume !(1 == ~T4_E~0); 506443#L669-1 assume !(1 == ~T5_E~0); 506444#L674-1 assume !(1 == ~E_1~0); 506911#L679-1 assume !(1 == ~E_2~0); 506552#L684-1 assume !(1 == ~E_3~0); 506553#L689-1 assume !(1 == ~E_4~0); 507028#L694-1 assume !(1 == ~E_5~0); 507029#L699-1 assume { :end_inline_reset_delta_events } true; 527539#L900-2 assume !false; 527534#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 527532#L561 [2022-12-13 19:31:12,918 INFO L750 eck$LassoCheckResult]: Loop: 527532#L561 assume !false; 527530#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 527528#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 527519#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 527520#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 527501#L486 assume 0 != eval_~tmp~0#1; 527502#L486-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 528056#L494 assume !(0 != eval_~tmp_ndt_1~0#1); 527582#L491 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 527566#L508 assume !(0 != eval_~tmp_ndt_2~0#1); 527559#L505 assume !(0 == ~t2_st~0); 527550#L519 assume !(0 == ~t3_st~0); 527540#L533 assume !(0 == ~t4_st~0); 527537#L547 assume !(0 == ~t5_st~0); 527532#L561 [2022-12-13 19:31:12,919 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:31:12,919 INFO L85 PathProgramCache]: Analyzing trace with hash -632671842, now seen corresponding path program 1 times [2022-12-13 19:31:12,919 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:31:12,919 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [431624668] [2022-12-13 19:31:12,919 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:31:12,919 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:31:12,925 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:31:12,936 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:31:12,936 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:31:12,937 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [431624668] [2022-12-13 19:31:12,937 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [431624668] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:31:12,937 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:31:12,937 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:31:12,937 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1201924652] [2022-12-13 19:31:12,937 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:31:12,937 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 19:31:12,937 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:31:12,937 INFO L85 PathProgramCache]: Analyzing trace with hash 140407213, now seen corresponding path program 1 times [2022-12-13 19:31:12,937 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:31:12,938 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1872193220] [2022-12-13 19:31:12,938 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:31:12,938 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:31:12,940 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 19:31:12,940 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 19:31:12,942 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 19:31:12,943 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 19:31:13,013 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 19:31:13,014 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 19:31:13,014 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 19:31:13,014 INFO L87 Difference]: Start difference. First operand 50770 states and 68629 transitions. cyclomatic complexity: 17877 Second operand has 3 states, 3 states have (on average 24.333333333333332) internal successors, (73), 3 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:31:13,135 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 19:31:13,135 INFO L93 Difference]: Finished difference Result 50681 states and 68508 transitions. [2022-12-13 19:31:13,135 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 50681 states and 68508 transitions. [2022-12-13 19:31:13,295 INFO L131 ngComponentsAnalysis]: Automaton has 18 accepting balls. 50466 [2022-12-13 19:31:13,490 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 50681 states to 50681 states and 68508 transitions. [2022-12-13 19:31:13,490 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 50681 [2022-12-13 19:31:13,508 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 50681 [2022-12-13 19:31:13,508 INFO L73 IsDeterministic]: Start isDeterministic. Operand 50681 states and 68508 transitions. [2022-12-13 19:31:13,522 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 19:31:13,522 INFO L218 hiAutomatonCegarLoop]: Abstraction has 50681 states and 68508 transitions. [2022-12-13 19:31:13,536 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 50681 states and 68508 transitions. [2022-12-13 19:31:13,789 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 50681 to 50681. [2022-12-13 19:31:13,821 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 50681 states, 50681 states have (on average 1.3517491762198852) internal successors, (68508), 50680 states have internal predecessors, (68508), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:31:13,890 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 50681 states to 50681 states and 68508 transitions. [2022-12-13 19:31:13,890 INFO L240 hiAutomatonCegarLoop]: Abstraction has 50681 states and 68508 transitions. [2022-12-13 19:31:13,891 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 19:31:13,891 INFO L428 stractBuchiCegarLoop]: Abstraction has 50681 states and 68508 transitions. [2022-12-13 19:31:13,891 INFO L335 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2022-12-13 19:31:13,891 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 50681 states and 68508 transitions. [2022-12-13 19:31:14,019 INFO L131 ngComponentsAnalysis]: Automaton has 18 accepting balls. 50466 [2022-12-13 19:31:14,019 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 19:31:14,019 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 19:31:14,020 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:31:14,020 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:31:14,020 INFO L748 eck$LassoCheckResult]: Stem: 608106#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 608107#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 608239#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 608240#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 608266#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 608267#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 608038#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 608039#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 608397#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 608398#L421-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 608351#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 608003#L586 assume !(0 == ~M_E~0); 608004#L586-2 assume !(0 == ~T1_E~0); 608063#L591-1 assume !(0 == ~T2_E~0); 608195#L596-1 assume !(0 == ~T3_E~0); 608196#L601-1 assume !(0 == ~T4_E~0); 608250#L606-1 assume !(0 == ~T5_E~0); 608251#L611-1 assume !(0 == ~E_1~0); 608364#L616-1 assume !(0 == ~E_2~0); 608365#L621-1 assume !(0 == ~E_3~0); 607925#L626-1 assume !(0 == ~E_4~0); 607926#L631-1 assume !(0 == ~E_5~0); 608099#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 607921#L279 assume !(1 == ~m_pc~0); 607922#L279-2 is_master_triggered_~__retres1~0#1 := 0; 608283#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 608075#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 608076#L720 assume !(0 != activate_threads_~tmp~1#1); 608282#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 608108#L298 assume !(1 == ~t1_pc~0); 607871#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 607872#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 607897#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 607898#L728 assume !(0 != activate_threads_~tmp___0~0#1); 607932#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 608069#L317 assume !(1 == ~t2_pc~0); 608070#L317-2 is_transmit2_triggered_~__retres1~2#1 := 0; 608306#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 608245#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 608119#L736 assume !(0 != activate_threads_~tmp___1~0#1); 608120#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 608346#L336 assume !(1 == ~t3_pc~0); 608347#L336-2 is_transmit3_triggered_~__retres1~3#1 := 0; 608441#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 607845#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 607846#L744 assume !(0 != activate_threads_~tmp___2~0#1); 608291#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 608358#L355 assume !(1 == ~t4_pc~0); 608192#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 608024#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 608025#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 608335#L752 assume !(0 != activate_threads_~tmp___3~0#1); 608336#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 608387#L374 assume !(1 == ~t5_pc~0); 608388#L374-2 is_transmit5_triggered_~__retres1~5#1 := 0; 608399#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 608400#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 608421#L760 assume !(0 != activate_threads_~tmp___4~0#1); 608422#L760-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 608428#L649 assume !(1 == ~M_E~0); 608429#L649-2 assume !(1 == ~T1_E~0); 607909#L654-1 assume !(1 == ~T2_E~0); 607910#L659-1 assume !(1 == ~T3_E~0); 608470#L664-1 assume !(1 == ~T4_E~0); 607901#L669-1 assume !(1 == ~T5_E~0); 607902#L674-1 assume !(1 == ~E_1~0); 608338#L679-1 assume !(1 == ~E_2~0); 608007#L684-1 assume !(1 == ~E_3~0); 608008#L689-1 assume !(1 == ~E_4~0); 608187#L694-1 assume !(1 == ~E_5~0); 608184#L699-1 assume { :end_inline_reset_delta_events } true; 608185#L900-2 assume !false; 636109#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 636107#L561 [2022-12-13 19:31:14,020 INFO L750 eck$LassoCheckResult]: Loop: 636107#L561 assume !false; 636105#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 636102#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 636092#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 636091#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 635973#L486 assume 0 != eval_~tmp~0#1; 635974#L486-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 636071#L494 assume !(0 != eval_~tmp_ndt_1~0#1); 635971#L491 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 635969#L508 assume !(0 != eval_~tmp_ndt_2~0#1); 635970#L505 assume !(0 == ~t2_st~0); 636126#L519 assume !(0 == ~t3_st~0); 636114#L533 assume !(0 == ~t4_st~0); 636112#L547 assume !(0 == ~t5_st~0); 636107#L561 [2022-12-13 19:31:14,021 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:31:14,021 INFO L85 PathProgramCache]: Analyzing trace with hash 1336547998, now seen corresponding path program 2 times [2022-12-13 19:31:14,021 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:31:14,021 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1155874946] [2022-12-13 19:31:14,021 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:31:14,021 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:31:14,028 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 19:31:14,028 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 19:31:14,032 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 19:31:14,041 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 19:31:14,041 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:31:14,041 INFO L85 PathProgramCache]: Analyzing trace with hash 140407213, now seen corresponding path program 2 times [2022-12-13 19:31:14,041 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:31:14,041 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1333728242] [2022-12-13 19:31:14,041 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:31:14,041 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:31:14,044 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 19:31:14,044 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 19:31:14,045 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 19:31:14,046 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 19:31:14,047 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:31:14,047 INFO L85 PathProgramCache]: Analyzing trace with hash 182662538, now seen corresponding path program 1 times [2022-12-13 19:31:14,047 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:31:14,047 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [137849537] [2022-12-13 19:31:14,047 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:31:14,047 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:31:14,054 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:31:14,071 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:31:14,071 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:31:14,071 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [137849537] [2022-12-13 19:31:14,071 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [137849537] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:31:14,071 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:31:14,071 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:31:14,071 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [546924319] [2022-12-13 19:31:14,071 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:31:14,136 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 19:31:14,137 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 19:31:14,137 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 19:31:14,137 INFO L87 Difference]: Start difference. First operand 50681 states and 68508 transitions. cyclomatic complexity: 17845 Second operand has 3 states, 3 states have (on average 29.0) internal successors, (87), 3 states have internal predecessors, (87), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:31:14,310 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 19:31:14,310 INFO L93 Difference]: Finished difference Result 77791 states and 104450 transitions. [2022-12-13 19:31:14,310 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 77791 states and 104450 transitions. [2022-12-13 19:31:14,678 INFO L131 ngComponentsAnalysis]: Automaton has 20 accepting balls. 77496 [2022-12-13 19:31:14,826 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 77791 states to 77791 states and 104450 transitions. [2022-12-13 19:31:14,826 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 77791 [2022-12-13 19:31:14,854 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 77791 [2022-12-13 19:31:14,854 INFO L73 IsDeterministic]: Start isDeterministic. Operand 77791 states and 104450 transitions. [2022-12-13 19:31:14,883 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 19:31:14,883 INFO L218 hiAutomatonCegarLoop]: Abstraction has 77791 states and 104450 transitions. [2022-12-13 19:31:14,911 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 77791 states and 104450 transitions. [2022-12-13 19:31:15,457 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 77791 to 75559. [2022-12-13 19:31:15,506 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 75559 states, 75559 states have (on average 1.346153337127278) internal successors, (101714), 75558 states have internal predecessors, (101714), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:31:15,636 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 75559 states to 75559 states and 101714 transitions. [2022-12-13 19:31:15,636 INFO L240 hiAutomatonCegarLoop]: Abstraction has 75559 states and 101714 transitions. [2022-12-13 19:31:15,637 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 19:31:15,637 INFO L428 stractBuchiCegarLoop]: Abstraction has 75559 states and 101714 transitions. [2022-12-13 19:31:15,637 INFO L335 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2022-12-13 19:31:15,637 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 75559 states and 101714 transitions. [2022-12-13 19:31:15,937 INFO L131 ngComponentsAnalysis]: Automaton has 20 accepting balls. 75264 [2022-12-13 19:31:15,937 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 19:31:15,937 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 19:31:15,937 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:31:15,938 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:31:15,938 INFO L748 eck$LassoCheckResult]: Stem: 736583#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 736584#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 736725#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 736726#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 736750#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 736751#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 736514#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 736515#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 736894#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 736895#L421-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 736844#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 736480#L586 assume !(0 == ~M_E~0); 736481#L586-2 assume !(0 == ~T1_E~0); 736539#L591-1 assume !(0 == ~T2_E~0); 736675#L596-1 assume !(0 == ~T3_E~0); 736676#L601-1 assume !(0 == ~T4_E~0); 736735#L606-1 assume !(0 == ~T5_E~0); 736736#L611-1 assume !(0 == ~E_1~0); 736860#L616-1 assume !(0 == ~E_2~0); 736861#L621-1 assume !(0 == ~E_3~0); 736403#L626-1 assume !(0 == ~E_4~0); 736404#L631-1 assume !(0 == ~E_5~0); 736576#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 736399#L279 assume !(1 == ~m_pc~0); 736400#L279-2 is_master_triggered_~__retres1~0#1 := 0; 736770#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 736551#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 736552#L720 assume !(0 != activate_threads_~tmp~1#1); 736769#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 736585#L298 assume !(1 == ~t1_pc~0); 736350#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 736351#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 736375#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 736376#L728 assume !(0 != activate_threads_~tmp___0~0#1); 736411#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 736545#L317 assume !(1 == ~t2_pc~0); 736546#L317-2 is_transmit2_triggered_~__retres1~2#1 := 0; 736793#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 736730#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 736596#L736 assume !(0 != activate_threads_~tmp___1~0#1); 736597#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 736838#L336 assume !(1 == ~t3_pc~0); 736839#L336-2 is_transmit3_triggered_~__retres1~3#1 := 0; 736950#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 736324#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 736325#L744 assume !(0 != activate_threads_~tmp___2~0#1); 736778#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 736849#L355 assume !(1 == ~t4_pc~0); 736672#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 736500#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 736501#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 736826#L752 assume !(0 != activate_threads_~tmp___3~0#1); 736827#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 736884#L374 assume !(1 == ~t5_pc~0); 736885#L374-2 is_transmit5_triggered_~__retres1~5#1 := 0; 736896#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 736897#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 736929#L760 assume !(0 != activate_threads_~tmp___4~0#1); 736930#L760-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 736937#L649 assume !(1 == ~M_E~0); 736938#L649-2 assume !(1 == ~T1_E~0); 736387#L654-1 assume !(1 == ~T2_E~0); 736388#L659-1 assume !(1 == ~T3_E~0); 736987#L664-1 assume !(1 == ~T4_E~0); 736379#L669-1 assume !(1 == ~T5_E~0); 736380#L674-1 assume !(1 == ~E_1~0); 736830#L679-1 assume !(1 == ~E_2~0); 736484#L684-1 assume !(1 == ~E_3~0); 736485#L689-1 assume !(1 == ~E_4~0); 736667#L694-1 assume !(1 == ~E_5~0); 736664#L699-1 assume { :end_inline_reset_delta_events } true; 736665#L900-2 assume !false; 747601#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 747594#L561 [2022-12-13 19:31:15,938 INFO L750 eck$LassoCheckResult]: Loop: 747594#L561 assume !false; 747588#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 747581#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 747574#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 747567#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 747560#L486 assume 0 != eval_~tmp~0#1; 747552#L486-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 747539#L494 assume !(0 != eval_~tmp_ndt_1~0#1); 747532#L491 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 747525#L508 assume !(0 != eval_~tmp_ndt_2~0#1); 747242#L505 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 746414#L522 assume !(0 != eval_~tmp_ndt_3~0#1); 746415#L519 assume !(0 == ~t3_st~0); 747612#L533 assume !(0 == ~t4_st~0); 747604#L547 assume !(0 == ~t5_st~0); 747594#L561 [2022-12-13 19:31:15,938 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:31:15,938 INFO L85 PathProgramCache]: Analyzing trace with hash 1336547998, now seen corresponding path program 3 times [2022-12-13 19:31:15,938 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:31:15,938 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1957051814] [2022-12-13 19:31:15,938 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:31:15,939 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:31:15,944 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 19:31:15,944 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 19:31:15,948 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 19:31:15,955 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 19:31:15,956 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:31:15,956 INFO L85 PathProgramCache]: Analyzing trace with hash -111462417, now seen corresponding path program 1 times [2022-12-13 19:31:15,956 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:31:15,956 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [444911243] [2022-12-13 19:31:15,956 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:31:15,956 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:31:15,958 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 19:31:15,958 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 19:31:15,960 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 19:31:15,961 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 19:31:15,961 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:31:15,961 INFO L85 PathProgramCache]: Analyzing trace with hash 1198452658, now seen corresponding path program 1 times [2022-12-13 19:31:15,961 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:31:15,961 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [487885574] [2022-12-13 19:31:15,961 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:31:15,962 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:31:15,966 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:31:15,981 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:31:15,981 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:31:15,982 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [487885574] [2022-12-13 19:31:15,982 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [487885574] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:31:15,982 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:31:15,982 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:31:15,982 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1289644877] [2022-12-13 19:31:15,982 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:31:16,075 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 19:31:16,076 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 19:31:16,076 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 19:31:16,076 INFO L87 Difference]: Start difference. First operand 75559 states and 101714 transitions. cyclomatic complexity: 26175 Second operand has 3 states, 3 states have (on average 29.333333333333332) internal successors, (88), 3 states have internal predecessors, (88), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:31:16,365 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 19:31:16,365 INFO L93 Difference]: Finished difference Result 120051 states and 161118 transitions. [2022-12-13 19:31:16,365 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 120051 states and 161118 transitions. [2022-12-13 19:31:16,768 INFO L131 ngComponentsAnalysis]: Automaton has 22 accepting balls. 119676 [2022-12-13 19:31:17,004 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 120051 states to 120051 states and 161118 transitions. [2022-12-13 19:31:17,005 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 120051 [2022-12-13 19:31:17,062 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 120051 [2022-12-13 19:31:17,062 INFO L73 IsDeterministic]: Start isDeterministic. Operand 120051 states and 161118 transitions. [2022-12-13 19:31:17,109 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 19:31:17,109 INFO L218 hiAutomatonCegarLoop]: Abstraction has 120051 states and 161118 transitions. [2022-12-13 19:31:17,161 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 120051 states and 161118 transitions. [2022-12-13 19:31:18,016 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 120051 to 118575. [2022-12-13 19:31:18,086 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 118575 states, 118575 states have (on average 1.3439089184060722) internal successors, (159354), 118574 states have internal predecessors, (159354), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:31:18,387 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 118575 states to 118575 states and 159354 transitions. [2022-12-13 19:31:18,387 INFO L240 hiAutomatonCegarLoop]: Abstraction has 118575 states and 159354 transitions. [2022-12-13 19:31:18,388 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 19:31:18,388 INFO L428 stractBuchiCegarLoop]: Abstraction has 118575 states and 159354 transitions. [2022-12-13 19:31:18,388 INFO L335 stractBuchiCegarLoop]: ======== Iteration 23 ============ [2022-12-13 19:31:18,388 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 118575 states and 159354 transitions. [2022-12-13 19:31:18,629 INFO L131 ngComponentsAnalysis]: Automaton has 22 accepting balls. 118200 [2022-12-13 19:31:18,629 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 19:31:18,629 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 19:31:18,629 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:31:18,629 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:31:18,630 INFO L748 eck$LassoCheckResult]: Stem: 932194#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 932195#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 932326#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 932327#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 932346#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 932347#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 932129#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 932130#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 932482#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 932483#L421-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 932434#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 932095#L586 assume !(0 == ~M_E~0); 932096#L586-2 assume !(0 == ~T1_E~0); 932154#L591-1 assume !(0 == ~T2_E~0); 932281#L596-1 assume !(0 == ~T3_E~0); 932282#L601-1 assume !(0 == ~T4_E~0); 932332#L606-1 assume !(0 == ~T5_E~0); 932333#L611-1 assume !(0 == ~E_1~0); 932445#L616-1 assume !(0 == ~E_2~0); 932446#L621-1 assume !(0 == ~E_3~0); 932021#L626-1 assume !(0 == ~E_4~0); 932022#L631-1 assume !(0 == ~E_5~0); 932187#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 932017#L279 assume !(1 == ~m_pc~0); 932018#L279-2 is_master_triggered_~__retres1~0#1 := 0; 932365#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 932165#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 932166#L720 assume !(0 != activate_threads_~tmp~1#1); 932364#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 932196#L298 assume !(1 == ~t1_pc~0); 931968#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 931969#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 931993#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 931994#L728 assume !(0 != activate_threads_~tmp___0~0#1); 932028#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 932159#L317 assume !(1 == ~t2_pc~0); 932160#L317-2 is_transmit2_triggered_~__retres1~2#1 := 0; 932386#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 932331#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 932207#L736 assume !(0 != activate_threads_~tmp___1~0#1); 932208#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 932429#L336 assume !(1 == ~t3_pc~0); 932430#L336-2 is_transmit3_triggered_~__retres1~3#1 := 0; 932535#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 931942#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 931943#L744 assume !(0 != activate_threads_~tmp___2~0#1); 932373#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 932439#L355 assume !(1 == ~t4_pc~0); 932278#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 932115#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 932116#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 932418#L752 assume !(0 != activate_threads_~tmp___3~0#1); 932419#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 932469#L374 assume !(1 == ~t5_pc~0); 932470#L374-2 is_transmit5_triggered_~__retres1~5#1 := 0; 932484#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 932485#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 932519#L760 assume !(0 != activate_threads_~tmp___4~0#1); 932520#L760-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 932525#L649 assume !(1 == ~M_E~0); 932526#L649-2 assume !(1 == ~T1_E~0); 932005#L654-1 assume !(1 == ~T2_E~0); 932006#L659-1 assume !(1 == ~T3_E~0); 932570#L664-1 assume !(1 == ~T4_E~0); 931997#L669-1 assume !(1 == ~T5_E~0); 931998#L674-1 assume !(1 == ~E_1~0); 932421#L679-1 assume !(1 == ~E_2~0); 932099#L684-1 assume !(1 == ~E_3~0); 932100#L689-1 assume !(1 == ~E_4~0); 932272#L694-1 assume !(1 == ~E_5~0); 932269#L699-1 assume { :end_inline_reset_delta_events } true; 932270#L900-2 assume !false; 1005983#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1005984#L561 [2022-12-13 19:31:18,630 INFO L750 eck$LassoCheckResult]: Loop: 1005984#L561 assume !false; 1006405#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 1005974#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 1005972#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 1005970#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1005968#L486 assume 0 != eval_~tmp~0#1; 1005965#L486-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 1005962#L494 assume !(0 != eval_~tmp_ndt_1~0#1); 1005960#L491 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 1005958#L508 assume !(0 != eval_~tmp_ndt_2~0#1); 1005959#L505 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 1006498#L522 assume !(0 != eval_~tmp_ndt_3~0#1); 1006497#L519 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 1006496#L536 assume !(0 != eval_~tmp_ndt_4~0#1); 1006412#L533 assume !(0 == ~t4_st~0); 1006410#L547 assume !(0 == ~t5_st~0); 1005984#L561 [2022-12-13 19:31:18,630 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:31:18,630 INFO L85 PathProgramCache]: Analyzing trace with hash 1336547998, now seen corresponding path program 4 times [2022-12-13 19:31:18,630 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:31:18,630 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [611259873] [2022-12-13 19:31:18,630 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:31:18,631 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:31:18,636 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 19:31:18,637 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 19:31:18,640 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 19:31:18,648 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 19:31:18,649 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:31:18,649 INFO L85 PathProgramCache]: Analyzing trace with hash 834182516, now seen corresponding path program 1 times [2022-12-13 19:31:18,649 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:31:18,649 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1579290129] [2022-12-13 19:31:18,649 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:31:18,649 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:31:18,651 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 19:31:18,651 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 19:31:18,653 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 19:31:18,654 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 19:31:18,654 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:31:18,654 INFO L85 PathProgramCache]: Analyzing trace with hash -1508123119, now seen corresponding path program 1 times [2022-12-13 19:31:18,654 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:31:18,654 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2024932805] [2022-12-13 19:31:18,654 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:31:18,654 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:31:18,660 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:31:18,675 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:31:18,675 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:31:18,676 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2024932805] [2022-12-13 19:31:18,676 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2024932805] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:31:18,676 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:31:18,676 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:31:18,676 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1320804184] [2022-12-13 19:31:18,676 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:31:18,789 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 19:31:18,789 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 19:31:18,789 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 19:31:18,790 INFO L87 Difference]: Start difference. First operand 118575 states and 159354 transitions. cyclomatic complexity: 40801 Second operand has 3 states, 3 states have (on average 29.666666666666668) internal successors, (89), 3 states have internal predecessors, (89), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:31:19,357 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 19:31:19,357 INFO L93 Difference]: Finished difference Result 196899 states and 264506 transitions. [2022-12-13 19:31:19,358 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 196899 states and 264506 transitions. [2022-12-13 19:31:20,099 INFO L131 ngComponentsAnalysis]: Automaton has 22 accepting balls. 196244 [2022-12-13 19:31:20,491 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 196899 states to 196899 states and 264506 transitions. [2022-12-13 19:31:20,491 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 196899 [2022-12-13 19:31:20,567 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 196899 [2022-12-13 19:31:20,568 INFO L73 IsDeterministic]: Start isDeterministic. Operand 196899 states and 264506 transitions. [2022-12-13 19:31:20,644 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 19:31:20,644 INFO L218 hiAutomatonCegarLoop]: Abstraction has 196899 states and 264506 transitions. [2022-12-13 19:31:20,843 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 196899 states and 264506 transitions. [2022-12-13 19:31:21,889 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 196899 to 193455. [2022-12-13 19:31:22,002 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 193455 states, 193455 states have (on average 1.3460804838334497) internal successors, (260406), 193454 states have internal predecessors, (260406), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:31:22,251 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 193455 states to 193455 states and 260406 transitions. [2022-12-13 19:31:22,252 INFO L240 hiAutomatonCegarLoop]: Abstraction has 193455 states and 260406 transitions. [2022-12-13 19:31:22,252 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 19:31:22,253 INFO L428 stractBuchiCegarLoop]: Abstraction has 193455 states and 260406 transitions. [2022-12-13 19:31:22,253 INFO L335 stractBuchiCegarLoop]: ======== Iteration 24 ============ [2022-12-13 19:31:22,253 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 193455 states and 260406 transitions. [2022-12-13 19:31:22,925 INFO L131 ngComponentsAnalysis]: Automaton has 22 accepting balls. 192800 [2022-12-13 19:31:22,926 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 19:31:22,926 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 19:31:22,926 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:31:22,926 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:31:22,927 INFO L748 eck$LassoCheckResult]: Stem: 1247680#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 1247681#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 1247820#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1247821#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1247845#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 1247846#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1247613#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1247614#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1247992#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1247993#L421-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1247935#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1247579#L586 assume !(0 == ~M_E~0); 1247580#L586-2 assume !(0 == ~T1_E~0); 1247639#L591-1 assume !(0 == ~T2_E~0); 1247774#L596-1 assume !(0 == ~T3_E~0); 1247775#L601-1 assume !(0 == ~T4_E~0); 1247829#L606-1 assume !(0 == ~T5_E~0); 1247830#L611-1 assume !(0 == ~E_1~0); 1247948#L616-1 assume !(0 == ~E_2~0); 1247949#L621-1 assume !(0 == ~E_3~0); 1247503#L626-1 assume !(0 == ~E_4~0); 1247504#L631-1 assume !(0 == ~E_5~0); 1247675#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1247499#L279 assume !(1 == ~m_pc~0); 1247500#L279-2 is_master_triggered_~__retres1~0#1 := 0; 1247863#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1247650#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1247651#L720 assume !(0 != activate_threads_~tmp~1#1); 1247862#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1247682#L298 assume !(1 == ~t1_pc~0); 1247450#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1247451#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1247475#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1247476#L728 assume !(0 != activate_threads_~tmp___0~0#1); 1247510#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1247644#L317 assume !(1 == ~t2_pc~0); 1247645#L317-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1247887#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1247826#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1247693#L736 assume !(0 != activate_threads_~tmp___1~0#1); 1247694#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1247929#L336 assume !(1 == ~t3_pc~0); 1247930#L336-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1248054#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1247425#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1247426#L744 assume !(0 != activate_threads_~tmp___2~0#1); 1247871#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1247940#L355 assume !(1 == ~t4_pc~0); 1247771#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1247598#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1247599#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1247916#L752 assume !(0 != activate_threads_~tmp___3~0#1); 1247917#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1247976#L374 assume !(1 == ~t5_pc~0); 1247977#L374-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1247994#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1247995#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1248029#L760 assume !(0 != activate_threads_~tmp___4~0#1); 1248030#L760-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1248036#L649 assume !(1 == ~M_E~0); 1248037#L649-2 assume !(1 == ~T1_E~0); 1247487#L654-1 assume !(1 == ~T2_E~0); 1247488#L659-1 assume !(1 == ~T3_E~0); 1248089#L664-1 assume !(1 == ~T4_E~0); 1247479#L669-1 assume !(1 == ~T5_E~0); 1247480#L674-1 assume !(1 == ~E_1~0); 1247919#L679-1 assume !(1 == ~E_2~0); 1247583#L684-1 assume !(1 == ~E_3~0); 1247584#L689-1 assume !(1 == ~E_4~0); 1247766#L694-1 assume !(1 == ~E_5~0); 1247763#L699-1 assume { :end_inline_reset_delta_events } true; 1247764#L900-2 assume !false; 1394143#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1394142#L561 [2022-12-13 19:31:22,927 INFO L750 eck$LassoCheckResult]: Loop: 1394142#L561 assume !false; 1394141#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 1394138#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 1394136#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 1394134#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1394132#L486 assume 0 != eval_~tmp~0#1; 1394129#L486-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 1394127#L494 assume !(0 != eval_~tmp_ndt_1~0#1); 1394125#L491 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 1394053#L508 assume !(0 != eval_~tmp_ndt_2~0#1); 1394122#L505 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 1416188#L522 assume !(0 != eval_~tmp_ndt_3~0#1); 1416186#L519 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 1309671#L536 assume !(0 != eval_~tmp_ndt_4~0#1); 1309672#L533 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0#1;eval_~tmp_ndt_5~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 1394147#L550 assume !(0 != eval_~tmp_ndt_5~0#1); 1394146#L547 assume !(0 == ~t5_st~0); 1394142#L561 [2022-12-13 19:31:22,927 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:31:22,928 INFO L85 PathProgramCache]: Analyzing trace with hash 1336547998, now seen corresponding path program 5 times [2022-12-13 19:31:22,928 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:31:22,928 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2122900394] [2022-12-13 19:31:22,928 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:31:22,928 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:31:22,937 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 19:31:22,937 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 19:31:22,942 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 19:31:22,954 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 19:31:22,954 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:31:22,954 INFO L85 PathProgramCache]: Analyzing trace with hash 89684008, now seen corresponding path program 1 times [2022-12-13 19:31:22,955 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:31:22,955 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [476636536] [2022-12-13 19:31:22,955 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:31:22,955 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:31:22,958 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 19:31:22,958 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 19:31:22,960 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 19:31:22,961 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 19:31:22,961 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:31:22,962 INFO L85 PathProgramCache]: Analyzing trace with hash 492653355, now seen corresponding path program 1 times [2022-12-13 19:31:22,962 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:31:22,962 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [255217981] [2022-12-13 19:31:22,962 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:31:22,962 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:31:22,969 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:31:22,990 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:31:22,991 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:31:22,991 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [255217981] [2022-12-13 19:31:22,991 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [255217981] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:31:22,991 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:31:22,991 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-12-13 19:31:22,991 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1778722371] [2022-12-13 19:31:22,991 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:31:23,105 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 19:31:23,106 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 19:31:23,106 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 19:31:23,106 INFO L87 Difference]: Start difference. First operand 193455 states and 260406 transitions. cyclomatic complexity: 66973 Second operand has 3 states, 2 states have (on average 45.0) internal successors, (90), 3 states have internal predecessors, (90), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:31:23,811 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 19:31:23,811 INFO L93 Difference]: Finished difference Result 228139 states and 306350 transitions. [2022-12-13 19:31:23,811 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 228139 states and 306350 transitions. [2022-12-13 19:31:24,739 INFO L131 ngComponentsAnalysis]: Automaton has 23 accepting balls. 220868 [2022-12-13 19:31:25,141 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 228139 states to 228139 states and 306350 transitions. [2022-12-13 19:31:25,141 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 228139 [2022-12-13 19:31:25,236 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 228139 [2022-12-13 19:31:25,237 INFO L73 IsDeterministic]: Start isDeterministic. Operand 228139 states and 306350 transitions. [2022-12-13 19:31:25,425 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 19:31:25,425 INFO L218 hiAutomatonCegarLoop]: Abstraction has 228139 states and 306350 transitions. [2022-12-13 19:31:25,492 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 228139 states and 306350 transitions. [2022-12-13 19:31:26,998 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 228139 to 228139. [2022-12-13 19:31:27,115 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 228139 states, 228139 states have (on average 1.3428217008052108) internal successors, (306350), 228138 states have internal predecessors, (306350), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:31:27,565 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 228139 states to 228139 states and 306350 transitions. [2022-12-13 19:31:27,565 INFO L240 hiAutomatonCegarLoop]: Abstraction has 228139 states and 306350 transitions. [2022-12-13 19:31:27,566 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 19:31:27,566 INFO L428 stractBuchiCegarLoop]: Abstraction has 228139 states and 306350 transitions. [2022-12-13 19:31:27,566 INFO L335 stractBuchiCegarLoop]: ======== Iteration 25 ============ [2022-12-13 19:31:27,566 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 228139 states and 306350 transitions. [2022-12-13 19:31:28,177 INFO L131 ngComponentsAnalysis]: Automaton has 23 accepting balls. 220868 [2022-12-13 19:31:28,177 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 19:31:28,177 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 19:31:28,177 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:31:28,177 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:31:28,177 INFO L748 eck$LassoCheckResult]: Stem: 1669289#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 1669290#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 1669428#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1669429#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1669452#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 1669453#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1669221#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1669222#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1669596#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1669597#L421-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1669546#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1669187#L586 assume !(0 == ~M_E~0); 1669188#L586-2 assume !(0 == ~T1_E~0); 1669246#L591-1 assume !(0 == ~T2_E~0); 1669378#L596-1 assume !(0 == ~T3_E~0); 1669379#L601-1 assume !(0 == ~T4_E~0); 1669435#L606-1 assume !(0 == ~T5_E~0); 1669436#L611-1 assume !(0 == ~E_1~0); 1669556#L616-1 assume !(0 == ~E_2~0); 1669557#L621-1 assume !(0 == ~E_3~0); 1669106#L626-1 assume !(0 == ~E_4~0); 1669107#L631-1 assume !(0 == ~E_5~0); 1669284#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1669104#L279 assume !(1 == ~m_pc~0); 1669105#L279-2 is_master_triggered_~__retres1~0#1 := 0; 1669473#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1669257#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1669258#L720 assume !(0 != activate_threads_~tmp~1#1); 1669472#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1669291#L298 assume !(1 == ~t1_pc~0); 1669054#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1669055#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1669079#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1669080#L728 assume !(0 != activate_threads_~tmp___0~0#1); 1669113#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1669251#L317 assume !(1 == ~t2_pc~0); 1669252#L317-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1669497#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1669434#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1669305#L736 assume !(0 != activate_threads_~tmp___1~0#1); 1669306#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1669540#L336 assume !(1 == ~t3_pc~0); 1669541#L336-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1669661#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1669027#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1669028#L744 assume !(0 != activate_threads_~tmp___2~0#1); 1669482#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1669551#L355 assume !(1 == ~t4_pc~0); 1669377#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1669209#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1669210#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1669525#L752 assume !(0 != activate_threads_~tmp___3~0#1); 1669526#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1669582#L374 assume !(1 == ~t5_pc~0); 1669583#L374-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1669598#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1669599#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1669631#L760 assume !(0 != activate_threads_~tmp___4~0#1); 1669632#L760-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1669644#L649 assume !(1 == ~M_E~0); 1669645#L649-2 assume !(1 == ~T1_E~0); 1669089#L654-1 assume !(1 == ~T2_E~0); 1669090#L659-1 assume !(1 == ~T3_E~0); 1669698#L664-1 assume !(1 == ~T4_E~0); 1669081#L669-1 assume !(1 == ~T5_E~0); 1669082#L674-1 assume !(1 == ~E_1~0); 1669527#L679-1 assume !(1 == ~E_2~0); 1669189#L684-1 assume !(1 == ~E_3~0); 1669190#L689-1 assume !(1 == ~E_4~0); 1669371#L694-1 assume !(1 == ~E_5~0); 1669367#L699-1 assume { :end_inline_reset_delta_events } true; 1669368#L900-2 assume !false; 1828965#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1827487#L561 [2022-12-13 19:31:28,178 INFO L750 eck$LassoCheckResult]: Loop: 1827487#L561 assume !false; 1828962#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 1828959#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 1828957#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 1828955#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1828954#L486 assume 0 != eval_~tmp~0#1; 1828949#L486-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 1828947#L494 assume !(0 != eval_~tmp_ndt_1~0#1); 1828945#L491 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 1828941#L508 assume !(0 != eval_~tmp_ndt_2~0#1); 1828939#L505 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 1828937#L522 assume !(0 != eval_~tmp_ndt_3~0#1); 1828935#L519 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 1828933#L536 assume !(0 != eval_~tmp_ndt_4~0#1); 1827494#L533 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0#1;eval_~tmp_ndt_5~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 1827491#L550 assume !(0 != eval_~tmp_ndt_5~0#1); 1827489#L547 assume 0 == ~t5_st~0;havoc eval_~tmp_ndt_6~0#1;eval_~tmp_ndt_6~0#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; 1827486#L564 assume !(0 != eval_~tmp_ndt_6~0#1); 1827487#L561 [2022-12-13 19:31:28,178 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:31:28,178 INFO L85 PathProgramCache]: Analyzing trace with hash 1336547998, now seen corresponding path program 6 times [2022-12-13 19:31:28,178 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:31:28,178 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1963602029] [2022-12-13 19:31:28,178 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:31:28,178 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:31:28,185 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 19:31:28,185 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 19:31:28,189 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 19:31:28,197 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 19:31:28,197 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:31:28,198 INFO L85 PathProgramCache]: Analyzing trace with hash -1514762949, now seen corresponding path program 1 times [2022-12-13 19:31:28,198 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:31:28,198 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2028873696] [2022-12-13 19:31:28,198 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:31:28,198 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:31:28,201 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 19:31:28,201 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 19:31:28,202 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 19:31:28,203 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 19:31:28,204 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:31:28,204 INFO L85 PathProgramCache]: Analyzing trace with hash -1907615080, now seen corresponding path program 1 times [2022-12-13 19:31:28,204 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:31:28,204 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1410945704] [2022-12-13 19:31:28,204 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:31:28,205 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:31:28,210 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 19:31:28,210 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 19:31:28,213 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 19:31:28,225 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 19:31:29,537 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 19:31:29,537 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 19:31:29,551 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 19:31:29,693 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 13.12 07:31:29 BoogieIcfgContainer [2022-12-13 19:31:29,693 INFO L132 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2022-12-13 19:31:29,693 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2022-12-13 19:31:29,693 INFO L271 PluginConnector]: Initializing Witness Printer... [2022-12-13 19:31:29,693 INFO L275 PluginConnector]: Witness Printer initialized [2022-12-13 19:31:29,694 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.12 07:31:03" (3/4) ... [2022-12-13 19:31:29,696 INFO L134 WitnessPrinter]: Generating witness for non-termination counterexample [2022-12-13 19:31:29,764 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f5200838-b26d-417b-8c3a-fd86d82f1b34/bin/uautomizer-uyxdKDjOR8/witness.graphml [2022-12-13 19:31:29,765 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2022-12-13 19:31:29,765 INFO L158 Benchmark]: Toolchain (without parser) took 27708.90ms. Allocated memory was 109.1MB in the beginning and 8.7GB in the end (delta: 8.6GB). Free memory was 69.6MB in the beginning and 5.2GB in the end (delta: -5.1GB). Peak memory consumption was 3.5GB. Max. memory is 16.1GB. [2022-12-13 19:31:29,765 INFO L158 Benchmark]: CDTParser took 0.18ms. Allocated memory is still 109.1MB. Free memory was 83.3MB in the beginning and 83.1MB in the end (delta: 140.3kB). There was no memory consumed. Max. memory is 16.1GB. [2022-12-13 19:31:29,765 INFO L158 Benchmark]: CACSL2BoogieTranslator took 246.18ms. Allocated memory is still 109.1MB. Free memory was 69.5MB in the beginning and 53.5MB in the end (delta: 16.0MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB. [2022-12-13 19:31:29,766 INFO L158 Benchmark]: Boogie Procedure Inliner took 54.51ms. Allocated memory is still 109.1MB. Free memory was 53.5MB in the beginning and 49.0MB in the end (delta: 4.5MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2022-12-13 19:31:29,766 INFO L158 Benchmark]: Boogie Preprocessor took 55.42ms. Allocated memory is still 109.1MB. Free memory was 48.6MB in the beginning and 44.4MB in the end (delta: 4.2MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2022-12-13 19:31:29,766 INFO L158 Benchmark]: RCFGBuilder took 819.87ms. Allocated memory was 109.1MB in the beginning and 132.1MB in the end (delta: 23.1MB). Free memory was 44.4MB in the beginning and 55.4MB in the end (delta: -11.0MB). Peak memory consumption was 15.1MB. Max. memory is 16.1GB. [2022-12-13 19:31:29,766 INFO L158 Benchmark]: BuchiAutomizer took 26457.49ms. Allocated memory was 132.1MB in the beginning and 8.7GB in the end (delta: 8.6GB). Free memory was 54.9MB in the beginning and 5.2GB in the end (delta: -5.2GB). Peak memory consumption was 3.4GB. Max. memory is 16.1GB. [2022-12-13 19:31:29,767 INFO L158 Benchmark]: Witness Printer took 71.35ms. Allocated memory is still 8.7GB. Free memory was 5.2GB in the beginning and 5.2GB in the end (delta: 9.4MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. [2022-12-13 19:31:29,768 INFO L339 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.18ms. Allocated memory is still 109.1MB. Free memory was 83.3MB in the beginning and 83.1MB in the end (delta: 140.3kB). There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 246.18ms. Allocated memory is still 109.1MB. Free memory was 69.5MB in the beginning and 53.5MB in the end (delta: 16.0MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 54.51ms. Allocated memory is still 109.1MB. Free memory was 53.5MB in the beginning and 49.0MB in the end (delta: 4.5MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * Boogie Preprocessor took 55.42ms. Allocated memory is still 109.1MB. Free memory was 48.6MB in the beginning and 44.4MB in the end (delta: 4.2MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * RCFGBuilder took 819.87ms. Allocated memory was 109.1MB in the beginning and 132.1MB in the end (delta: 23.1MB). Free memory was 44.4MB in the beginning and 55.4MB in the end (delta: -11.0MB). Peak memory consumption was 15.1MB. Max. memory is 16.1GB. * BuchiAutomizer took 26457.49ms. Allocated memory was 132.1MB in the beginning and 8.7GB in the end (delta: 8.6GB). Free memory was 54.9MB in the beginning and 5.2GB in the end (delta: -5.2GB). Peak memory consumption was 3.4GB. Max. memory is 16.1GB. * Witness Printer took 71.35ms. Allocated memory is still 8.7GB. Free memory was 5.2GB in the beginning and 5.2GB in the end (delta: 9.4MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 24 terminating modules (24 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.24 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 228139 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 26.2s and 25 iterations. TraceHistogramMax:1. Analysis of lassos took 3.9s. Construction of modules took 0.6s. Büchi inclusion checks took 19.0s. Highest rank in rank-based complementation 0. Minimization of det autom 24. Minimization of nondet autom 0. Automata minimization 8.8s AutomataMinimizationTime, 24 MinimizatonAttempts, 91676 StatesRemovedByMinimization, 16 NontrivialMinimizations. Non-live state removal took 5.9s Buchi closure took 0.4s. Biggest automaton had -1 states and ocurred in iteration -1. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 23563 SdHoareTripleChecker+Valid, 0.8s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 23563 mSDsluCounter, 36896 SdHoareTripleChecker+Invalid, 0.6s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 17661 mSDsCounter, 341 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 802 IncrementalHoareTripleChecker+Invalid, 1143 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 341 mSolverCounterUnsat, 19235 mSDtfsCounter, 802 mSolverCounterSat, 0.1s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI4 SFLT0 conc5 concLT0 SILN1 SILU0 SILI14 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s InitialAbstractionConstructionTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - LassoShapedNonTerminationArgument [Line: 481]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite program execution. Stem: [L25] int m_pc = 0; [L26] int t1_pc = 0; [L27] int t2_pc = 0; [L28] int t3_pc = 0; [L29] int t4_pc = 0; [L30] int t5_pc = 0; [L31] int m_st ; [L32] int t1_st ; [L33] int t2_st ; [L34] int t3_st ; [L35] int t4_st ; [L36] int t5_st ; [L37] int m_i ; [L38] int t1_i ; [L39] int t2_i ; [L40] int t3_i ; [L41] int t4_i ; [L42] int t5_i ; [L43] int M_E = 2; [L44] int T1_E = 2; [L45] int T2_E = 2; [L46] int T3_E = 2; [L47] int T4_E = 2; [L48] int T5_E = 2; [L49] int E_1 = 2; [L50] int E_2 = 2; [L51] int E_3 = 2; [L52] int E_4 = 2; [L53] int E_5 = 2; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=0, m_pc=0, m_st=0, T1_E=2, t1_i=0, t1_pc=0, t1_st=0, T2_E=2, t2_i=0, t2_pc=0, t2_st=0, T3_E=2, t3_i=0, t3_pc=0, t3_st=0, T4_E=2, t4_i=0, t4_pc=0, t4_st=0, T5_E=2, t5_i=0, t5_pc=0, t5_st=0] [L945] int __retres1 ; [L949] CALL init_model() [L856] m_i = 1 [L857] t1_i = 1 [L858] t2_i = 1 [L859] t3_i = 1 [L860] t4_i = 1 [L861] t5_i = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L949] RET init_model() [L950] CALL start_simulation() [L886] int kernel_st ; [L887] int tmp ; [L888] int tmp___0 ; [L892] kernel_st = 0 [L893] FCALL update_channels() [L894] CALL init_threads() [L401] COND TRUE m_i == 1 [L402] m_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L406] COND TRUE t1_i == 1 [L407] t1_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L411] COND TRUE t2_i == 1 [L412] t2_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L416] COND TRUE t3_i == 1 [L417] t3_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L421] COND TRUE t4_i == 1 [L422] t4_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L426] COND TRUE t5_i == 1 [L427] t5_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L894] RET init_threads() [L895] CALL fire_delta_events() [L586] COND FALSE !(M_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L591] COND FALSE !(T1_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L596] COND FALSE !(T2_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L601] COND FALSE !(T3_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L606] COND FALSE !(T4_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L611] COND FALSE !(T5_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L616] COND FALSE !(E_1 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L621] COND FALSE !(E_2 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L626] COND FALSE !(E_3 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L631] COND FALSE !(E_4 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L636] COND FALSE !(E_5 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L895] RET fire_delta_events() [L896] CALL activate_threads() [L709] int tmp ; [L710] int tmp___0 ; [L711] int tmp___1 ; [L712] int tmp___2 ; [L713] int tmp___3 ; [L714] int tmp___4 ; [L718] CALL, EXPR is_master_triggered() [L276] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L279] COND FALSE !(m_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L289] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L291] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L718] RET, EXPR is_master_triggered() [L718] tmp = is_master_triggered() [L720] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, tmp=0] [L726] CALL, EXPR is_transmit1_triggered() [L295] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L298] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L308] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L310] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L726] RET, EXPR is_transmit1_triggered() [L726] tmp___0 = is_transmit1_triggered() [L728] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, tmp=0, tmp___0=0] [L734] CALL, EXPR is_transmit2_triggered() [L314] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L317] COND FALSE !(t2_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L327] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L329] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L734] RET, EXPR is_transmit2_triggered() [L734] tmp___1 = is_transmit2_triggered() [L736] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, tmp=0, tmp___0=0, tmp___1=0] [L742] CALL, EXPR is_transmit3_triggered() [L333] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L336] COND FALSE !(t3_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L346] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L348] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L742] RET, EXPR is_transmit3_triggered() [L742] tmp___2 = is_transmit3_triggered() [L744] COND FALSE !(\read(tmp___2)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0] [L750] CALL, EXPR is_transmit4_triggered() [L352] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L355] COND FALSE !(t4_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L365] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L367] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L750] RET, EXPR is_transmit4_triggered() [L750] tmp___3 = is_transmit4_triggered() [L752] COND FALSE !(\read(tmp___3)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0] [L758] CALL, EXPR is_transmit5_triggered() [L371] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L374] COND FALSE !(t5_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L384] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L386] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L758] RET, EXPR is_transmit5_triggered() [L758] tmp___4 = is_transmit5_triggered() [L760] COND FALSE !(\read(tmp___4)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0, tmp___4=0] [L896] RET activate_threads() [L897] CALL reset_delta_events() [L649] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L654] COND FALSE !(T1_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L659] COND FALSE !(T2_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L664] COND FALSE !(T3_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L669] COND FALSE !(T4_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L674] COND FALSE !(T5_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L679] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L684] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L689] COND FALSE !(E_3 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L694] COND FALSE !(E_4 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L699] COND FALSE !(E_5 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L897] RET reset_delta_events() [L900] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L903] kernel_st = 1 [L904] CALL eval() [L477] int tmp ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] Loop: [L481] COND TRUE 1 [L484] CALL, EXPR exists_runnable_thread() [L436] int __retres1 ; [L439] COND TRUE m_st == 0 [L440] __retres1 = 1 [L472] return (__retres1); [L484] RET, EXPR exists_runnable_thread() [L484] tmp = exists_runnable_thread() [L486] COND TRUE \read(tmp) [L491] COND TRUE m_st == 0 [L492] int tmp_ndt_1; [L493] tmp_ndt_1 = __VERIFIER_nondet_int() [L494] COND FALSE !(\read(tmp_ndt_1)) [L505] COND TRUE t1_st == 0 [L506] int tmp_ndt_2; [L507] tmp_ndt_2 = __VERIFIER_nondet_int() [L508] COND FALSE !(\read(tmp_ndt_2)) [L519] COND TRUE t2_st == 0 [L520] int tmp_ndt_3; [L521] tmp_ndt_3 = __VERIFIER_nondet_int() [L522] COND FALSE !(\read(tmp_ndt_3)) [L533] COND TRUE t3_st == 0 [L534] int tmp_ndt_4; [L535] tmp_ndt_4 = __VERIFIER_nondet_int() [L536] COND FALSE !(\read(tmp_ndt_4)) [L547] COND TRUE t4_st == 0 [L548] int tmp_ndt_5; [L549] tmp_ndt_5 = __VERIFIER_nondet_int() [L550] COND FALSE !(\read(tmp_ndt_5)) [L561] COND TRUE t5_st == 0 [L562] int tmp_ndt_6; [L563] tmp_ndt_6 = __VERIFIER_nondet_int() [L564] COND FALSE !(\read(tmp_ndt_6)) End of lasso representation. - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 481]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L25] int m_pc = 0; [L26] int t1_pc = 0; [L27] int t2_pc = 0; [L28] int t3_pc = 0; [L29] int t4_pc = 0; [L30] int t5_pc = 0; [L31] int m_st ; [L32] int t1_st ; [L33] int t2_st ; [L34] int t3_st ; [L35] int t4_st ; [L36] int t5_st ; [L37] int m_i ; [L38] int t1_i ; [L39] int t2_i ; [L40] int t3_i ; [L41] int t4_i ; [L42] int t5_i ; [L43] int M_E = 2; [L44] int T1_E = 2; [L45] int T2_E = 2; [L46] int T3_E = 2; [L47] int T4_E = 2; [L48] int T5_E = 2; [L49] int E_1 = 2; [L50] int E_2 = 2; [L51] int E_3 = 2; [L52] int E_4 = 2; [L53] int E_5 = 2; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=0, m_pc=0, m_st=0, T1_E=2, t1_i=0, t1_pc=0, t1_st=0, T2_E=2, t2_i=0, t2_pc=0, t2_st=0, T3_E=2, t3_i=0, t3_pc=0, t3_st=0, T4_E=2, t4_i=0, t4_pc=0, t4_st=0, T5_E=2, t5_i=0, t5_pc=0, t5_st=0] [L945] int __retres1 ; [L949] CALL init_model() [L856] m_i = 1 [L857] t1_i = 1 [L858] t2_i = 1 [L859] t3_i = 1 [L860] t4_i = 1 [L861] t5_i = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L949] RET init_model() [L950] CALL start_simulation() [L886] int kernel_st ; [L887] int tmp ; [L888] int tmp___0 ; [L892] kernel_st = 0 [L893] FCALL update_channels() [L894] CALL init_threads() [L401] COND TRUE m_i == 1 [L402] m_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L406] COND TRUE t1_i == 1 [L407] t1_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L411] COND TRUE t2_i == 1 [L412] t2_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L416] COND TRUE t3_i == 1 [L417] t3_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L421] COND TRUE t4_i == 1 [L422] t4_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L426] COND TRUE t5_i == 1 [L427] t5_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L894] RET init_threads() [L895] CALL fire_delta_events() [L586] COND FALSE !(M_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L591] COND FALSE !(T1_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L596] COND FALSE !(T2_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L601] COND FALSE !(T3_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L606] COND FALSE !(T4_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L611] COND FALSE !(T5_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L616] COND FALSE !(E_1 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L621] COND FALSE !(E_2 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L626] COND FALSE !(E_3 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L631] COND FALSE !(E_4 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L636] COND FALSE !(E_5 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L895] RET fire_delta_events() [L896] CALL activate_threads() [L709] int tmp ; [L710] int tmp___0 ; [L711] int tmp___1 ; [L712] int tmp___2 ; [L713] int tmp___3 ; [L714] int tmp___4 ; [L718] CALL, EXPR is_master_triggered() [L276] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L279] COND FALSE !(m_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L289] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L291] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L718] RET, EXPR is_master_triggered() [L718] tmp = is_master_triggered() [L720] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, tmp=0] [L726] CALL, EXPR is_transmit1_triggered() [L295] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L298] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L308] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L310] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L726] RET, EXPR is_transmit1_triggered() [L726] tmp___0 = is_transmit1_triggered() [L728] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, tmp=0, tmp___0=0] [L734] CALL, EXPR is_transmit2_triggered() [L314] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L317] COND FALSE !(t2_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L327] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L329] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L734] RET, EXPR is_transmit2_triggered() [L734] tmp___1 = is_transmit2_triggered() [L736] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, tmp=0, tmp___0=0, tmp___1=0] [L742] CALL, EXPR is_transmit3_triggered() [L333] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L336] COND FALSE !(t3_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L346] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L348] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L742] RET, EXPR is_transmit3_triggered() [L742] tmp___2 = is_transmit3_triggered() [L744] COND FALSE !(\read(tmp___2)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0] [L750] CALL, EXPR is_transmit4_triggered() [L352] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L355] COND FALSE !(t4_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L365] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L367] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L750] RET, EXPR is_transmit4_triggered() [L750] tmp___3 = is_transmit4_triggered() [L752] COND FALSE !(\read(tmp___3)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0] [L758] CALL, EXPR is_transmit5_triggered() [L371] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L374] COND FALSE !(t5_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L384] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L386] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L758] RET, EXPR is_transmit5_triggered() [L758] tmp___4 = is_transmit5_triggered() [L760] COND FALSE !(\read(tmp___4)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0, tmp___4=0] [L896] RET activate_threads() [L897] CALL reset_delta_events() [L649] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L654] COND FALSE !(T1_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L659] COND FALSE !(T2_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L664] COND FALSE !(T3_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L669] COND FALSE !(T4_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L674] COND FALSE !(T5_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L679] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L684] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L689] COND FALSE !(E_3 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L694] COND FALSE !(E_4 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L699] COND FALSE !(E_5 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L897] RET reset_delta_events() [L900] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L903] kernel_st = 1 [L904] CALL eval() [L477] int tmp ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] Loop: [L481] COND TRUE 1 [L484] CALL, EXPR exists_runnable_thread() [L436] int __retres1 ; [L439] COND TRUE m_st == 0 [L440] __retres1 = 1 [L472] return (__retres1); [L484] RET, EXPR exists_runnable_thread() [L484] tmp = exists_runnable_thread() [L486] COND TRUE \read(tmp) [L491] COND TRUE m_st == 0 [L492] int tmp_ndt_1; [L493] tmp_ndt_1 = __VERIFIER_nondet_int() [L494] COND FALSE !(\read(tmp_ndt_1)) [L505] COND TRUE t1_st == 0 [L506] int tmp_ndt_2; [L507] tmp_ndt_2 = __VERIFIER_nondet_int() [L508] COND FALSE !(\read(tmp_ndt_2)) [L519] COND TRUE t2_st == 0 [L520] int tmp_ndt_3; [L521] tmp_ndt_3 = __VERIFIER_nondet_int() [L522] COND FALSE !(\read(tmp_ndt_3)) [L533] COND TRUE t3_st == 0 [L534] int tmp_ndt_4; [L535] tmp_ndt_4 = __VERIFIER_nondet_int() [L536] COND FALSE !(\read(tmp_ndt_4)) [L547] COND TRUE t4_st == 0 [L548] int tmp_ndt_5; [L549] tmp_ndt_5 = __VERIFIER_nondet_int() [L550] COND FALSE !(\read(tmp_ndt_5)) [L561] COND TRUE t5_st == 0 [L562] int tmp_ndt_6; [L563] tmp_ndt_6 = __VERIFIER_nondet_int() [L564] COND FALSE !(\read(tmp_ndt_6)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2022-12-13 19:31:29,833 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f5200838-b26d-417b-8c3a-fd86d82f1b34/bin/uautomizer-uyxdKDjOR8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Forceful destruction successful, exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)